RE: [PATCH 1/2] drm/amd/powerplay: fix pre-check condition for setting clock range
> -Original Message- > From: Bjorn Helgaas > Sent: Monday, March 9, 2020 9:11 PM > To: Liang, Prike > Cc: amd-gfx@lists.freedesktop.org; Quan, Evan ; > Huang, Ray ; linux-ker...@vger.org; Deucher, > Alexander > Subject: Re: [PATCH 1/2] drm/amd/powerplay: fix pre-check condition for > setting clock range > > On Wed, Mar 04, 2020 at 10:55:37AM +0800, Prike Liang wrote: > > This fix will handle some MP1 FW issue like as mclk dpm table in > > renoir has a reverse dpm clock layout and a zero frequency dpm level > > as following case. > > > > cat pp_dpm_mclk > > 0: 1200Mhz > > 1: 1200Mhz > > 2: 800Mhz > > 3: 0Mhz > > > > Signed-off-by: Prike Liang > > --- > > drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +- > > drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 3 --- > > 2 files changed, 1 insertion(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c > > b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c > > index e3398f9..d454493 100644 > > --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c > > +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c > > @@ -214,7 +214,7 @@ int smu_set_soft_freq_range(struct smu_context > > *smu, enum smu_clk_type clk_type, { > > int ret = 0; > > > > - if (min <= 0 && max <= 0) > > + if (min < 0 && max < 0) > > This change causes the following Coverity warning because min and max are > both unsigned: > > int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type > clk_type, > uint32_t min, uint32_t max) > > >>> CID 1460516: Integer handling issues (NO_EFFECT) > >>> This less-than-zero comparison of an unsigned value is never true. > "min < 0U". [Prike] Thanks and will fix the Coverity warning. > 225 if (min < 0 && max < 0) > 226 return -EINVAL; > > > return -EINVAL; > > > > if (!smu_clk_dpm_is_enabled(smu, clk_type)) ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/2] drm/amd/powerplay: fix pre-check condition for setting clock range
On Wed, Mar 04, 2020 at 10:55:37AM +0800, Prike Liang wrote: > This fix will handle some MP1 FW issue like as mclk dpm table in > renoir has a reverse dpm clock layout and a zero frequency dpm level > as following case. > > cat pp_dpm_mclk > 0: 1200Mhz > 1: 1200Mhz > 2: 800Mhz > 3: 0Mhz > > Signed-off-by: Prike Liang > --- > drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +- > drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 3 --- > 2 files changed, 1 insertion(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c > b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c > index e3398f9..d454493 100644 > --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c > +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c > @@ -214,7 +214,7 @@ int smu_set_soft_freq_range(struct smu_context *smu, enum > smu_clk_type clk_type, > { > int ret = 0; > > - if (min <= 0 && max <= 0) > + if (min < 0 && max < 0) This change causes the following Coverity warning because min and max are both unsigned: int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max) >>> CID 1460516: Integer handling issues (NO_EFFECT) >>> This less-than-zero comparison of an unsigned value is never true. "min >>> < 0U". 225 if (min < 0 && max < 0) 226 return -EINVAL; > return -EINVAL; > > if (!smu_clk_dpm_is_enabled(smu, clk_type)) ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/2] drm/amd/powerplay: fix pre-check condition for setting clock range
This fix will handle some MP1 FW issue like as mclk dpm table in renoir has a reverse dpm clock layout and a zero frequency dpm level as following case. cat pp_dpm_mclk 0: 1200Mhz 1: 1200Mhz 2: 800Mhz 3: 0Mhz Signed-off-by: Prike Liang --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +- drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 3 --- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index e3398f9..d454493 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -214,7 +214,7 @@ int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, { int ret = 0; - if (min <= 0 && max <= 0) + if (min < 0 && max < 0) return -EINVAL; if (!smu_clk_dpm_is_enabled(smu, clk_type)) diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c index 93b8558..d52e624 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c +++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c @@ -461,9 +461,6 @@ int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_ { int ret = 0; - if (max < min) - return -EINVAL; - switch (clk_type) { case SMU_GFXCLK: case SMU_SCLK: -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx