RE: [PATCH 2/2] drm/amdgpu: init umc functions for arcturus umc ras

[Clements, John]

Reviewed-by: John Clements 

-Original Message-
From: Hawking Zhang  
Sent: Wednesday, November 13, 2019 10:57 PM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander 
; Li, Dennis ; Clements, John 

Cc: Zhang, Hawking 
Subject: [PATCH 2/2] drm/amdgpu: init umc functions for arcturus umc ras

reuse vg20 umc functions for arcturus umc ras

Change-Id: Ia8af3c20a717c76ec18aa5fa332cfd81ca60ff69
Signed-off-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 3784b62201b0..8a5b722ce5b7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -635,6 +635,7 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device 
*adev)
adev->umc.funcs = _v6_0_funcs;
break;
case CHIP_VEGA20:
+   case CHIP_ARCTURUS:
adev->umc.max_ras_err_cnt_per_query = 
UMC_V6_1_TOTAL_CHANNEL_NUM;
adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; @@ -748,6 
+749,7 @@ static int gmc_v9_0_late_init(void *handle)
switch (adev->asic_type) {
case CHIP_VEGA10:
case CHIP_VEGA20:
+   case CHIP_ARCTURUS:
r = amdgpu_atomfirmware_mem_ecc_supported(adev);
if (!r) {
DRM_INFO("ECC is not present.\n");
--
2.17.1

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Re: [PATCH 2/2] drm/amdgpu: init umc functions for arcturus umc ras

[Alex Deucher]

On Wed, Nov 13, 2019 at 9:57 AM Hawking Zhang  wrote:
>
> reuse vg20 umc functions for arcturus umc ras
>
> Change-Id: Ia8af3c20a717c76ec18aa5fa332cfd81ca60ff69
> Signed-off-by: Hawking Zhang 

Series is:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 3784b62201b0..8a5b722ce5b7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -635,6 +635,7 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device 
> *adev)
> adev->umc.funcs = _v6_0_funcs;
> break;
> case CHIP_VEGA20:
> +   case CHIP_ARCTURUS:
> adev->umc.max_ras_err_cnt_per_query = 
> UMC_V6_1_TOTAL_CHANNEL_NUM;
> adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
> adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
> @@ -748,6 +749,7 @@ static int gmc_v9_0_late_init(void *handle)
> switch (adev->asic_type) {
> case CHIP_VEGA10:
> case CHIP_VEGA20:
> +   case CHIP_ARCTURUS:
> r = amdgpu_atomfirmware_mem_ecc_supported(adev);
> if (!r) {
> DRM_INFO("ECC is not present.\n");
> --
> 2.17.1
>
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