Re: [ARTIQ] ARTIQ hardware proposal
Hi all, Overall I think this looks pretty good. Here are a few comments: * I like the 2x AD9656 better than the 1x ADC16DX370 for the ADC on the DSP boards. I think the most common use case for these will be pulsed laser power stabilization, and for that we'll need the # DAC channels to match the # ADC channels. Additionally, the servo bandwidth will be limited by the acoustic wave propagation time in an AOM to ~500 kHz, so we don't need the higher sampling speed of the ADC16DX370. The pipeline delay of the AD9656 is small enough to support 500 kHz servo bandwidth. Perhaps it might be good to add a spec for the total DAC + ADC + signal processing latency for feedback purposes. I think a good number would be in the 0.5 to 1.0 us range. * Is FMC good for high-speed analog signals? * Use of FMC for the DSP daughterboards makes it more difficult to quickly hack together a new daughterboard, since the FMC connector can't be hand soldered. I'm not sure if this is a problem, but just thought I'd throw it out there. Best, Dave -Original Message- From: ARTIQ [mailto:artiq-boun...@lists.m-labs.hk] On Behalf Of Sébastien Bourdeauducq Sent: Friday, March 18, 2016 9:47 AM To: artiq@lists.m-labs.hk Subject: [ARTIQ] ARTIQ hardware proposal Hi, I've been collecting ideas about the new hardware we've been talking about for a while. Please see the attached document and let me know what you think. Sébastien ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] ARTIQ hardware proposal
-Original Message- From: ARTIQ [mailto:artiq-boun...@lists.m-labs.hk] On Behalf Of Tan, Ting Rei (IntlAssoc) Sent: Saturday, March 19, 2016 3:50 PM To: Robert Jördens Cc: artiq@lists.m-labs.hk Subject: Re: [ARTIQ] ARTIQ hardware proposal I agree that not stuffing ADC does not make things worthwhile. How about considering a DSP breakout board similar to the standalone digital box? This, obviously, is another piece of hardware need to be maintained. But I think this makes more sense for the application of laser stabilization, i.e. you want the servo controller physically closer to your laser system rather than have all of them sitting inside a crate. I don't think so. We have all of our laser intensity servos in the same rack as our experiment control FPGA anyway, since they're not so fast that the cable propagation time matters. In any case, I think we can take any card and stick it on the optical table in a single slot rack. I am not very clear about the analog FMC card (item 6) as it is not indicated in the 'system overview' diagram. Is this basically a DSP breakout board? Also, how about considering a 2:1 DAC to ADC channels ratio for DSP? I think most experiments prefer more output than input. I think this would only save a couple hundred dollars per board. If you want a cheaper option for driving trap electrodes, I think it would be better to have a second board with many channels of lower speed DAC. Ting Rei -Original Message- From: Robert Jördens [mailto:jord...@gmail.com] Sent: Saturday, March 19, 2016 3:10 PM To: Tan, Ting Rei (IntlAssoc) Cc: artiq@lists.m-labs.hk Subject: Re: [ARTIQ] ARTIQ hardware proposal On Sat, Mar 19, 2016 at 8:54 PM, Tan, Ting Rei (IntlAssoc) wrote: > For complicated trap users, the most common use case is to drive trap > electrode so we will need much more DAC channels and ADC channels. One > possible solution is to have two kind of DSP boards? One with balanced > DAC and ADC channels and the other with only DAC. Specifying, designing, producing, stocking, and selling more boards just to get variations is quite time consuming and expensive. Two things to consider here: We can probably do a run where the ADCs are not populated. But you won't get more DAC channels and the amount of money saved might not make it worth the trouble. Also for "many DAC channels" we will probably end up needing to do hardware anyway. -- Robert Jordens. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] FW: initial specification of the project
I like this plan. I think 4 + 4 channels will also make the front panel connector density more reasonable. What are you thinking for number of daughter cards? I suppose that more would give us more flexibility, but less would be more economical in terms of cost and layout area. Perhaps two daughter cards would be reasonable: one for all of the inputs and one for all of the outputs? Best, Dave -Original Message- From: ARTIQ [mailto:artiq-boun...@lists.m-labs.hk] On Behalf Of Sébastien Bourdeauducq Sent: Wednesday, March 30, 2016 5:50 AM To: Grzegorz Kasprowicz Cc: 'Grzegorz Kasprowicz' ; artiq@lists.m-labs.hk; Slichter, Daniel H. (Fed) Subject: Re: [ARTIQ] FW: initial specification of the project On Tuesday, 29 March 2016 11:55:19 PM HKT Grzegorz Kasprowicz wrote: > - they can be used immediately with existing OSHW carriers like AFC/AFCK. AFCK may be overkill. We are still working on evaluating the FPGA resource requirements. > - it could be hard to fit FPGA, supply, DACs and several RF modules, > all on single dual width AMC, especially when shielding is required. > RTM relaxes these constraints > - on AMC+RTM you can place 8 ADC channels + 8 DAC channels + 8 RF > modules. In case of single AMC board it would be hard to achieve such > channels density. How about this: * we reduce the number of channels per AMC to 4 DACs + 4 ADCs * we can therefore use a smaller FPGA. Communication lanes to the master board are relatively cheap if we put them on IOSERDES. * the power density and cooling requirements are also reduced. * for the RF daughter cards, we use a custom form factor that can use at least 2/3 of the AMC front panel * connectors between the DSP card and the RF daughter card are 2mm header and 8x SMP * the rest of the AMC front panel used for (optional, runtime selectable) clock input and some TTLs. Sébastien ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] proposed DAC gateware
Maybe this is implied, but it'd be nice to have example artiq experiments that demonstrate at least all of the functionality covered by the test cases. -Original Message- From: ARTIQ [mailto:artiq-boun...@lists.m-labs.hk] On Behalf Of j arl Sent: Thursday, July 28, 2016 3:14 PM To: artiq@lists.m-labs.hk; Sébastien Bourdeauducq ; Robert Jördens ; Slichter, Daniel H. (Fed) ; jase...@gmail.com; camaca...@gmail.com Subject: [ARTIQ] proposed DAC gateware Dear prospective Sayma users, please comment on the attached gateware and ARTIQ-integration specification. It is intended to be stand-alone and make minimal reference to the microTCA hardware. The aim is to provide isolation of the gateware development from broader Sayma/Metlino system. Detailed specification of the other components are forthcoming. Many thanks to long conversations with Robert Jordens and Sebastien Bourdeauducq (m-labs), Jonathan Mizrahi (JQI) and Daniel Slichter (NIST Boulder). Huge props to developers of the NIST PDQ system Ryan Bowler (U. Washington) and Jason Heidecker. And to Robert Jordens (m-labs.hk) who developed its successor PDQ2. -Joe --- Joe Britton Sensors and Electron Devices Army Research Lab 2800 Powder Mill Rd Adelphi, MD 20783 301-394-3130 joseph.w.britton5@mail.mil ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] DSP gateware
Hi Robert, This is a nice writeup. A couple questions for now: 1. I assume this logic would be followed by some sort of digital filter to remove the unwanted Nyquist images. Have you thought about how good of suppression you might be able to achieve, and at what FPGA resource and phase distortion cost? 2. Do you have an idea of the latency of the signal chain? Say I wanted to do a phase lock by feeding new p1 values into the RTIO. What sort of bandwidth could I achieve? Thanks, Dave -Original Message- From: Robert Jördens [mailto:r...@m-labs.hk] Sent: Sunday, July 31, 2016 5:32 AM To: artiq@lists.m-labs.hk; Jonathan Mizrahi ; Sébastien Bourdeauducq ; Joe Britton ; Slichter, Daniel H. (Fed) ; Leibrandt, David R. (Fed) ; Allcock, David T. (IntlAssoc) ; Ken Brown Subject: Re: DSP gateware Hello, to fuel the discussion and planning of the smart arbitrary waveform generator requirements for the different applications, I did another extended design study for the proposed ARTIQ/Sayma DSP gateware and signal flow, looking at actual signal quality, resource usage and possible parametrizations. This time, take the following parametrization of a channel's output o: z = (a1*exp(i*(f1*t+p1)) + a2*exp(i*(f2*t+p2))) * exp(i*(f0*t+p0)) o = u + b*Re(z) + c*Im(z_buddy) * u and a are 16 bit cubic spline inteprolators * p are 16 bit constant (non-) interpolators * f are 48 bit linear interpolators * z_buddy refers to the (complex, IQ) z data coming from each channel's "buddy" channel, ignore it for now * b, c are switches (with values 0 or 1) that allow a bunch of different configurations, ignore them for now * all spline interpolators (u, a, f, p) sample at 200 MHz * the f1/p1 and f2/p2 oscillators sample at 200 MHz and their data is fed to the f0/p0 oscillator without interpolation * the f0/p0 oscillator samples at 8*200 MHz = 1.6 GHz * data width is at least 16 bit everywhere This setup can -- for example -- generate a two-tone signal at 162 MHz and 238 MHz by setting f0=157 MHz, f1=5 MHz, f2=81 MHz. The attached plot has the data and the spectrum from a bit-accurate simulation of the full FPGA gateware. Units are "natural" (sample rate=1, full scale=1): the relevant tones are close to 0.1 and 0.15 sample rate. Output amplitude is below clipping. This is a bit-accurate representation of the data that would be sent to the DAC. Actual analog output would only differ by the DAC's interpolation and it's analog output transfer function and DAC noise. Don't be confused by the way the samples look: this is only due to the un-interpolated data from the f1/f2 oscillators. Same goes for the Nyquist images all around. A very rough and conservative estimate for wideband SNR is > 85 dB not counting the images. There are a lot of things that can be tweaked still, this demo is not supposed to be show the optimum. * 200 MHz is a bit under maximum achievable speed for this logic on a -2 speed grade kintex 7. * 1.6 GHz * 4 channels is more than we can push to a DAC. The design can obviously also run at 1 GHz (f1,f2 at 125 MHz, f0 at 1 GHz) which would just about fill eight JESD204B pipes. * The design can also be built for 800 MHz with significantly lower resource usage (then running the f1,f2 NCOs at 200 MHz, f0 at 4*200 MHz = 800 MHz). This would free a lot of room on the FPGA, fit the JESD pipes, and would still be able to comfortably generate the signal above. * DAC interpolation could be 2x if desired to get to 2 GHz or 1.6 GHz DAC sample rate depending on the choice of scenario. * Eight channels of this 1.6 GHz design occupy about 62% of the LUTs of a xc7k325t (without _any_ other logic like everything related to the transcievers, ARTIQ, DRTIO, FIFOs...). * Wrapping it in a minimal ARTIQ system brings the LUT resource usage to about 72%. * On a xcku040 the utilization estimate (same gateware as for the 62% xc7k325t system) is below 51%, (can't get a good number because of a Xilinx-Vivado bug). * Take the LUT usage percentages with a grain of salt. They don't react kindly to extrapolation. * Interpolation schemes for the f1/p1, f2/p2 oscillator data before it reaches the f0 oscillator might be interesting to look at. * Spline knot behavior (ramping, switching, synchronization, latency matching, interpolation) for frequency, phase, amplitude is as expected (see e.g. the pdq2 documentation). This demonstrates that we can actually get very good high-data-rate two-tone signals for eight channels out of gateware that fits on currently available development boards. The parametrization is intuitive and extremely flexible (you can e.g. rewire it at run-time to exploit and feed the full IQ datapaths of the DACs giving you twice the bandwidth on half the channels and all the other features in the DAC and downstream). Any set of spline interpolators can receive new knot data at the same time from their RTIO FIFOs:
Re: [ARTIQ] DSP gateware
>> This is very nice work, thanks for the detailed write-up. It seems that >> this gateware design would cover just about any use case for high-bandwidth >> two-tone designs. To Dave L's question, there are already interpolation >> filters with sharp cutoffs in the AD9154 to eliminate Nyquist images if >> desired; I have done some measurements on the AD9154 hardware and they work >> quite well, up to what the datasheet says (~85 dB image rejection in the >> stopband, which would take us effectively to the noise floor of the outputs >> generated by the gateware Robert demonstrates). TI gives the filter >> coefficients for their FIR filters in the datasheets; you might be able to >> email Analog Devices and ask them for the filter coefficients for the >> AD9154, and this would allow you to evaluate the phase and amplitude >> response vs your needs. > Those AA filters won't do anything to the images from the f1/f2 oscillators. > I assume Dave was referring to those. Yup, that's what I was thinking. It sounds like this won't be too difficult to do, just something that needs to be thought about (i.e., how well we need to suppress the spurs). ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
