I like this plan.  I think 4 + 4 channels will also make the front panel 
connector density more reasonable.  What are you thinking for number of 
daughter cards?  I suppose that more would give us more flexibility, but less 
would be more economical in terms of cost and layout area.  Perhaps two 
daughter cards would be reasonable: one for all of the inputs and one for all 
of the outputs?

Best,
Dave

-----Original Message-----
From: ARTIQ [mailto:artiq-boun...@lists.m-labs.hk] On Behalf Of Sébastien 
Bourdeauducq
Sent: Wednesday, March 30, 2016 5:50 AM
To: Grzegorz Kasprowicz <kaspr...@gmail.com>
Cc: 'Grzegorz Kasprowicz' <gkasp...@elka.pw.edu.pl>; artiq@lists.m-labs.hk; 
Slichter, Daniel H. (Fed) <daniel.slich...@nist.gov>
Subject: Re: [ARTIQ] FW: initial specification of the project

On Tuesday, 29 March 2016 11:55:19 PM HKT Grzegorz Kasprowicz wrote:
> - they can be used immediately with existing OSHW carriers like AFC/AFCK. 

AFCK may be overkill. We are still working on evaluating the FPGA resource 
requirements.

> - it could be hard to fit FPGA, supply, DACs and several RF modules, 
> all on single dual width AMC, especially when shielding is required. 
> RTM relaxes these constraints
> - on AMC+RTM you can place 8 ADC channels + 8 DAC channels + 8 RF 
> modules. In case of single AMC board it would be hard to achieve such 
> channels density.

How about this:
* we reduce the number of channels per AMC to 4 DACs + 4 ADCs
* we can therefore use a smaller FPGA. Communication lanes to the master board 
are relatively cheap if we put them on IOSERDES.
* the power density and cooling requirements are also reduced.
* for the RF daughter cards, we use a custom form factor that can use at least
2/3 of the AMC front panel
* connectors between the DSP card and the RF daughter card are 2mm header and 
8x SMP
* the rest of the AMC front panel used for (optional, runtime selectable) clock 
input and some TTLs.

Sébastien

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