Re: [ARTIQ] TTL + slow DACs
On Thursday, 31 March 2016 8:11:54 PM HKT Grzegorz Kasprowicz wrote: > At the moment we have step pricing for FPGAs used in AFC, AFCK, SPEC and WR > switch. Then let's put a 7K325T (=AFCK) in the DSP cards and a 6SLX45T (=SPEC) in the standalone digital boxes. In the master board this remains to be determined, *maybe* Zynq *if* there is a compelling *technical* argument for the MPSoC. Sébastien ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] TTL + slow DACs
If you run it over 1G fiber, you can consider using WR protocol. You don't need WR switch since it can be used as point to point. WR gives absolute 1ns of accuracy and about 15ps of jitter, over 10km fiber. Greg -Original Message- From: Robert Jördens [mailto:r...@m-labs.hk] Sent: Thursday, March 31, 2016 9:55 PM To: Slichter, Daniel H. (Fed) Cc: Sébastien Bourdeauducq ; Grzegorz Kasprowicz ; Grzegorz Kasprowicz ; Leibrandt, David R. (Fed) ; artiq@lists.m-labs.hk Subject: Re: [ARTIQ] TTL + slow DACs On Thu, Mar 31, 2016 at 7:45 PM, Slichter, Daniel H. (Fed) wrote: >> Since this is another piece of hardware and the processing >> constraints as well as the electrical constraints are so different, >> it seems prudent to account for these differences. Consider doing proper >> galvanic isolation with a fiber: >> ground potential differences easily >> -- and even in well controlled labs -- exceed the common mode >> tolerances of lvds if the devices are a few tens of meters apart. >> >> This is why we would like to consider a very low barrier, non-rack >> form factor that is connected by fiber plus a simple power supply and >> provides a good number of analog voltages and a good number of ttls. >> That obsoletes the LVDS breakout board which also doesn't help with >> the galvanic isolation for the high density low speed DAC that we >> would like to bundle with that box. > > OK, fiber is superior for galvanic isolation, but at the end of the day this > would be a solution with just a few TTL lines per board, and you would then > sprinkle these around the lab, correct? And clock/timing transfer can be > done over the fiber in a suitable way? Yes. We suggest to run DRTIO over that 1 GBit/s fiber link. That way we get absolute ns-timing and a clock. TTL timing jitter would just be limited by how far we drive the "good stable low noise LO" game and then FPGA IO jitter. Same as for what we could do from within a crate. But it would be worse than the jitter from the high performance RF crate DSP AMC. TTL numbers around 16 or 32 and DAC channels around whatever AD53[67][0123] one chooses. This scattered box should be very cost efficient. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] TTL + slow DACs
On Thu, Mar 31, 2016 at 7:45 PM, Slichter, Daniel H. (Fed) wrote: >> Since this is another piece of hardware and the processing constraints as >> well >> as the electrical constraints are so different, it seems prudent to account >> for >> these differences. Consider doing proper galvanic isolation with a fiber: >> ground potential differences easily >> -- and even in well controlled labs -- exceed the common mode tolerances of >> lvds if the devices are a few tens of meters apart. >> >> This is why we would like to consider a very low barrier, non-rack form >> factor >> that is connected by fiber plus a simple power supply and provides a good >> number of analog voltages and a good number of ttls. >> That obsoletes the LVDS breakout board which also doesn't help with the >> galvanic isolation for the high density low speed DAC that we would like to >> bundle with that box. > > OK, fiber is superior for galvanic isolation, but at the end of the day this > would be a solution with just a few TTL lines per board, and you would then > sprinkle these around the lab, correct? And clock/timing transfer can be > done over the fiber in a suitable way? Yes. We suggest to run DRTIO over that 1 GBit/s fiber link. That way we get absolute ns-timing and a clock. TTL timing jitter would just be limited by how far we drive the "good stable low noise LO" game and then FPGA IO jitter. Same as for what we could do from within a crate. But it would be worse than the jitter from the high performance RF crate DSP AMC. TTL numbers around 16 or 32 and DAC channels around whatever AD53[67][0123] one chooses. This scattered box should be very cost efficient. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] TTL + slow DACs
Hi Before we decide about FPGA technology, keep in mind that Xilinx and other vendors have pricing policy. It is called step pricing. So the price of the particular component, depends of cumulated order history. That's why I will push towards using same FPGA or SoC in all boards because once you exceed 10 pieces, you get about 30% discount. But once you approach to 101 pieces, such FPGA gets 70% cheaper. So it makes sense to apply bigger FPGA even if you don't want to use all its resources because such solution is cheaper. IF you look at ZynQ 7 chips in Digikey and the price is 5k$ and scares you, I can get such chips about 500..800$ per piece because I used it in several of my designs and long time ago exceeded 100pieces:) Because I will use ZynQ US+ in 3 other projects (Zu7/9 and ZU11), that is the reason I proposed this particular chip for our application because I can get zu11 cheaper than older Kintex 7K325 The same applies to other production companies. You must ask about step pricing before you get an offer for production:) At the moment we have step pricing for FPGAs used in AFC, AFCK, SPEC and WR switch. Sometimes it is cheaper to install bigger chip than smaller one because they belong to different price steps. Greg -Original Message- From: Slichter, Daniel H. (Fed) [mailto:daniel.slich...@nist.gov] Sent: Thursday, March 31, 2016 5:30 PM To: Sébastien Bourdeauducq ; Grzegorz Kasprowicz Cc: Robert Jördens ; Grzegorz Kasprowicz ; Leibrandt, David R. (Fed) ; artiq@lists.m-labs.hk Subject: RE: [ARTIQ] TTL + slow DACs > We'll probably want a few dozen TTLs, broken out on SMA, so the FMC > panel is not an option there. > > We can remove PCIe indeed, but keeping the WR oscillators is probably > a good idea as they can be used for clock synchronization with the master. For the purpose of a TTL card, I would recommend that the TTL be broken out to LVDS over cat5/cat6 using RJ45 connectors, as is currently done in the ARTIQ hardware. It would be possible to send 64 TTL lines out of a single AMC card of 6 HP width in this manner, much more than you could ever do with SMA, and with vastly cheaper cabling and excellent signal integrity for long cabling runs (tested to work fine with 30 m cable, for example). We have existing breakout boards that convert between 4 TTL signals on SMA and 4 LVDS signals on Ethernet cables. This card would not have an FMC mezzanine, but would rather just break things out directly from the FPGA. I would recommend using a similar architecture on the AMC board to our existing TTL riser card that interfaces between TTL at the FPGA and LVDS. I know we could directly drive LVDS to/from the FPGA, but then we don't have any isolation between the FPGA user IO and the end user application, which makes me nervous that users could more easily fry the FPGA. One could use a very inexpensive FPGA for this particular task, although it might be nice to have a hard processor if it is driving so many TTL lines. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] TTL + slow DACs
> Since this is another piece of hardware and the processing constraints as well > as the electrical constraints are so different, it seems prudent to account > for > these differences. Consider doing proper galvanic isolation with a fiber: > ground potential differences easily > -- and even in well controlled labs -- exceed the common mode tolerances of > lvds if the devices are a few tens of meters apart. > > This is why we would like to consider a very low barrier, non-rack form factor > that is connected by fiber plus a simple power supply and provides a good > number of analog voltages and a good number of ttls. > That obsoletes the LVDS breakout board which also doesn't help with the > galvanic isolation for the high density low speed DAC that we would like to > bundle with that box. OK, fiber is superior for galvanic isolation, but at the end of the day this would be a solution with just a few TTL lines per board, and you would then sprinkle these around the lab, correct? And clock/timing transfer can be done over the fiber in a suitable way? ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] TTL + slow DACs
On Thu, Mar 31, 2016 at 5:29 PM, Slichter, Daniel H. (Fed) wrote: >> We'll probably want a few dozen TTLs, broken out on SMA, so the FMC panel >> is not an option there. >> >> We can remove PCIe indeed, but keeping the WR oscillators is probably a >> good idea as they can be used for clock synchronization with the master. > > For the purpose of a TTL card, I would recommend that the TTL be broken out > to LVDS over cat5/cat6 using RJ45 connectors, as is currently done in the > ARTIQ hardware. It would be possible to send 64 TTL lines out of a single > AMC card of 6 HP width in this manner, much more than you could ever do with > SMA, and with vastly cheaper cabling and excellent signal integrity for long > cabling runs (tested to work fine with 30 m cable, for example). We have > existing breakout boards that convert between 4 TTL signals on SMA and 4 LVDS > signals on Ethernet cables. > > This card would not have an FMC mezzanine, but would rather just break things > out directly from the FPGA. I would recommend using a similar architecture > on the AMC board to our existing TTL riser card that interfaces between TTL > at the FPGA and LVDS. I know we could directly drive LVDS to/from the FPGA, > but then we don't have any isolation between the FPGA user IO and the end > user application, which makes me nervous that users could more easily fry the > FPGA. > > One could use a very inexpensive FPGA for this particular task, although it > might be nice to have a hard processor if it is driving so many TTL lines. Since this is another piece of hardware and the processing constraints as well as the electrical constraints are so different, it seems prudent to account for these differences. Consider doing proper galvanic isolation with a fiber: ground potential differences easily -- and even in well controlled labs -- exceed the common mode tolerances of lvds if the devices are a few tens of meters apart. This is why we would like to consider a very low barrier, non-rack form factor that is connected by fiber plus a simple power supply and provides a good number of analog voltages and a good number of ttls. That obsoletes the LVDS breakout board which also doesn't help with the galvanic isolation for the high density low speed DAC that we would like to bundle with that box. Robert. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] TTL + slow DACs
> We'll probably want a few dozen TTLs, broken out on SMA, so the FMC panel > is not an option there. > > We can remove PCIe indeed, but keeping the WR oscillators is probably a > good idea as they can be used for clock synchronization with the master. For the purpose of a TTL card, I would recommend that the TTL be broken out to LVDS over cat5/cat6 using RJ45 connectors, as is currently done in the ARTIQ hardware. It would be possible to send 64 TTL lines out of a single AMC card of 6 HP width in this manner, much more than you could ever do with SMA, and with vastly cheaper cabling and excellent signal integrity for long cabling runs (tested to work fine with 30 m cable, for example). We have existing breakout boards that convert between 4 TTL signals on SMA and 4 LVDS signals on Ethernet cables. This card would not have an FMC mezzanine, but would rather just break things out directly from the FPGA. I would recommend using a similar architecture on the AMC board to our existing TTL riser card that interfaces between TTL at the FPGA and LVDS. I know we could directly drive LVDS to/from the FPGA, but then we don't have any isolation between the FPGA user IO and the end user application, which makes me nervous that users could more easily fry the FPGA. One could use a very inexpensive FPGA for this particular task, although it might be nice to have a hard processor if it is driving so many TTL lines. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] TTL + slow DACs
We'll probably want a few dozen TTLs, broken out on SMA, so the FMC panel is not an option there. We can remove PCIe indeed, but keeping the WR oscillators is probably a good idea as they can be used for clock synchronization with the master. Sébastien On Thursday, 31 March 2016 3:58:11 PM HKT Grzegorz Kasprowicz wrote: > Here is the box > http://www.ohwr.org/projects/spec-box-1n/wiki > > On 31 March 2016 at 15:57, Grzegorz Kasprowicz wrote: > > for this purpose one can use this board > > http://www.ohwr.org/projects/spec/wiki > > there is available also stand-alone aluminium box.The cost can be lowered > > by factor of two when WR oscillators, PCie chip and memory is not mounted. > > Just leave FPGA,supply and FMC connector. > > Greg > > ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] TTL + slow DACs
Here is the box http://www.ohwr.org/projects/spec-box-1n/wiki On 31 March 2016 at 15:57, Grzegorz Kasprowicz wrote: > for this purpose one can use this board > http://www.ohwr.org/projects/spec/wiki > there is available also stand-alone aluminium box.The cost can be lowered > by factor of two when WR oscillators, PCie chip and memory is not mounted. > Just leave FPGA,supply and FMC connector. > Greg > > On 31 March 2016 at 14:48, Grzegorz Kasprowicz wrote: > >> Well, yes, providing that you find charger that won't fail after 500 hours >> :) >> >> >> -Original Message- >> From: Sébastien Bourdeauducq [mailto:s...@m-labs.hk] >> Sent: Thursday, March 31, 2016 12:42 PM >> To: Grzegorz Kasprowicz >> Cc: Slichter, Daniel H. (Fed) ; Robert Jördens >> ; Grzegorz Kasprowicz ; Leibrandt, >> David R. (Fed) ; artiq@lists.m-labs.hk >> Subject: Re: [ARTIQ] TTL + slow DACs >> >> On Thursday, 31 March 2016 12:40:55 PM HKT Grzegorz Kasprowicz wrote: >> > Well, we can use in this case the AMC board plugged into dual AMC box >> > which has 4 SFPs. >> > In some cases this could be an overkill, but it is working solution. >> > http://www.ohwr.org/projects/amc-ubackplane-sfp/wiki >> >> A Spartan-6 FPGA powered by a mobile phone charger is sufficient. >> >> >> > ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] TTL + slow DACs
for this purpose one can use this board http://www.ohwr.org/projects/spec/wiki there is available also stand-alone aluminium box.The cost can be lowered by factor of two when WR oscillators, PCie chip and memory is not mounted. Just leave FPGA,supply and FMC connector. Greg On 31 March 2016 at 14:48, Grzegorz Kasprowicz wrote: > Well, yes, providing that you find charger that won't fail after 500 hours > :) > > > -Original Message- > From: Sébastien Bourdeauducq [mailto:s...@m-labs.hk] > Sent: Thursday, March 31, 2016 12:42 PM > To: Grzegorz Kasprowicz > Cc: Slichter, Daniel H. (Fed) ; Robert Jördens > ; Grzegorz Kasprowicz ; Leibrandt, > David R. (Fed) ; artiq@lists.m-labs.hk > Subject: Re: [ARTIQ] TTL + slow DACs > > On Thursday, 31 March 2016 12:40:55 PM HKT Grzegorz Kasprowicz wrote: > > Well, we can use in this case the AMC board plugged into dual AMC box > > which has 4 SFPs. > > In some cases this could be an overkill, but it is working solution. > > http://www.ohwr.org/projects/amc-ubackplane-sfp/wiki > > A Spartan-6 FPGA powered by a mobile phone charger is sufficient. > > > ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] TTL + slow DACs
Well, yes, providing that you find charger that won't fail after 500 hours :) -Original Message- From: Sébastien Bourdeauducq [mailto:s...@m-labs.hk] Sent: Thursday, March 31, 2016 12:42 PM To: Grzegorz Kasprowicz Cc: Slichter, Daniel H. (Fed) ; Robert Jördens ; Grzegorz Kasprowicz ; Leibrandt, David R. (Fed) ; artiq@lists.m-labs.hk Subject: Re: [ARTIQ] TTL + slow DACs On Thursday, 31 March 2016 12:40:55 PM HKT Grzegorz Kasprowicz wrote: > Well, we can use in this case the AMC board plugged into dual AMC box > which has 4 SFPs. > In some cases this could be an overkill, but it is working solution. > http://www.ohwr.org/projects/amc-ubackplane-sfp/wiki A Spartan-6 FPGA powered by a mobile phone charger is sufficient. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] TTL + slow DACs
On Thursday, 31 March 2016 12:40:55 PM HKT Grzegorz Kasprowicz wrote: > Well, we can use in this case the AMC board plugged into dual AMC box which > has 4 SFPs. > In some cases this could be an overkill, but it is working solution. > http://www.ohwr.org/projects/amc-ubackplane-sfp/wiki A Spartan-6 FPGA powered by a mobile phone charger is sufficient. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] TTL + slow DACs
Well, we can use in this case the AMC board plugged into dual AMC box which has 4 SFPs. In some cases this could be an overkill, but it is working solution. http://www.ohwr.org/projects/amc-ubackplane-sfp/wiki On 31 March 2016 at 12:05, Sébastien Bourdeauducq wrote: > On Wednesday, 30 March 2016 11:45:16 PM HKT Slichter, Daniel H. (Fed) > wrote: > > One further question: is there a plan to make a “TTL” card or a > multichannel > > “slow” DAC card (e.g. for trap voltages), using a Centronics or d-sub > type > > connector? These could both be more readily accomplished with their own > > FMC modules if we go with this architecture. > > No. They will need breakout boxes anyway, and better put an FPGA in that > box > and connect it to the root master with a fiber. > > Sébastien > > ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] TTL + slow DACs
On Wednesday, 30 March 2016 11:45:16 PM HKT Slichter, Daniel H. (Fed) wrote: > One further question: is there a plan to make a “TTL” card or a multichannel > “slow” DAC card (e.g. for trap voltages), using a Centronics or d-sub type > connector? These could both be more readily accomplished with their own > FMC modules if we go with this architecture. No. They will need breakout boxes anyway, and better put an FPGA in that box and connect it to the root master with a fiber. Sébastien ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
