> We'll probably want a few dozen TTLs, broken out on SMA, so the FMC panel > is not an option there. > > We can remove PCIe indeed, but keeping the WR oscillators is probably a > good idea as they can be used for clock synchronization with the master.
For the purpose of a TTL card, I would recommend that the TTL be broken out to LVDS over cat5/cat6 using RJ45 connectors, as is currently done in the ARTIQ hardware. It would be possible to send 64 TTL lines out of a single AMC card of 6 HP width in this manner, much more than you could ever do with SMA, and with vastly cheaper cabling and excellent signal integrity for long cabling runs (tested to work fine with 30 m cable, for example). We have existing breakout boards that convert between 4 TTL signals on SMA and 4 LVDS signals on Ethernet cables. This card would not have an FMC mezzanine, but would rather just break things out directly from the FPGA. I would recommend using a similar architecture on the AMC board to our existing TTL riser card that interfaces between TTL at the FPGA and LVDS. I know we could directly drive LVDS to/from the FPGA, but then we don't have any isolation between the FPGA user IO and the end user application, which makes me nervous that users could more easily fry the FPGA. One could use a very inexpensive FPGA for this particular task, although it might be nice to have a hard processor if it is driving so many TTL lines. _______________________________________________ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
