Re: [ath9k-devel] uart interface issues (fixed)
Am 02.05.2013 09:15, schrieb Eugene Krasnikov: Hi Oleksij, Have you tried remote debugging? Or it's only about garbing logs from the chip. Have you tried to send commands to the chip? Yes, it works. You need this resistors to make chip start with ttl adapter attached. Without them this chip may not start. 2013/5/2 Oleksij Rempel li...@rempel-privat.de: Am 28.04.2013 16:17, schrieb Oleksij Rempel: Am 28.04.2013 13:38, schrieb Adrian Chadd: .. is it triggering BREAK interrupts or something? I don't know, there is no serial output on this stage. JTAG may help if the protocol is some how similar to EJTAG. Are there any documentation about Xtensa dubug interface ;)? I will need to dig in it, but not this week. That may be something that the boot ROM code interprets as a magical don't start sequence or something. So, this issue is fixed now. ttl TX --[2K]o RX pin on AR7010 |[4K pull up]--- 3,3V In attachment are pictures from my setup ;) -- Regards, Oleksij -- Regards, Oleksij ___ ath9k-devel mailing list ath9k-devel@lists.ath9k.org https://lists.ath9k.org/mailman/listinfo/ath9k-devel
Re: [ath9k-devel] uart interface issues (fixed)
What kind of commands did you try to send? I will try the same with my dongle and update you if that works or not;) 2013/5/2 Oleksij Rempel li...@rempel-privat.de: Am 02.05.2013 09:15, schrieb Eugene Krasnikov: Hi Oleksij, Have you tried remote debugging? Or it's only about garbing logs from the chip. Have you tried to send commands to the chip? Yes, it works. You need this resistors to make chip start with ttl adapter attached. Without them this chip may not start. 2013/5/2 Oleksij Rempel li...@rempel-privat.de: Am 28.04.2013 16:17, schrieb Oleksij Rempel: Am 28.04.2013 13:38, schrieb Adrian Chadd: .. is it triggering BREAK interrupts or something? I don't know, there is no serial output on this stage. JTAG may help if the protocol is some how similar to EJTAG. Are there any documentation about Xtensa dubug interface ;)? I will need to dig in it, but not this week. That may be something that the boot ROM code interprets as a magical don't start sequence or something. So, this issue is fixed now. ttl TX --[2K]o RX pin on AR7010 |[4K pull up]--- 3,3V In attachment are pictures from my setup ;) -- Regards, Oleksij -- Regards, Oleksij -- Best regards, Eugene ___ ath9k-devel mailing list ath9k-devel@lists.ath9k.org https://lists.ath9k.org/mailman/listinfo/ath9k-devel
Re: [ath9k-devel] uart interface issues (fixed)
Am 02.05.2013 09:22, schrieb Eugene Krasnikov: What kind of commands did you try to send? I will try the same with my dongle and update you if that works or not;) all command are here: ./target_firmware/magpie_fw_dev/target/cmnos/dbg_api.c working commands: help info ram wdt rst (restart system) wdt off (turn off watchdog) wdt on (...) memdmp 5 50010 (memdump of 0x5 0x50010 area) be careful with memdmp command. If watchdog enabled i can be triggered on memdmp, so disable it. If you hit some prottected memory area, system on chip will oops. 2013/5/2 Oleksij Rempel li...@rempel-privat.de: Am 02.05.2013 09:15, schrieb Eugene Krasnikov: Hi Oleksij, Have you tried remote debugging? Or it's only about garbing logs from the chip. Have you tried to send commands to the chip? Yes, it works. You need this resistors to make chip start with ttl adapter attached. Without them this chip may not start. 2013/5/2 Oleksij Rempel li...@rempel-privat.de: Am 28.04.2013 16:17, schrieb Oleksij Rempel: Am 28.04.2013 13:38, schrieb Adrian Chadd: .. is it triggering BREAK interrupts or something? I don't know, there is no serial output on this stage. JTAG may help if the protocol is some how similar to EJTAG. Are there any documentation about Xtensa dubug interface ;)? I will need to dig in it, but not this week. That may be something that the boot ROM code interprets as a magical don't start sequence or something. So, this issue is fixed now. ttl TX --[2K]o RX pin on AR7010 |[4K pull up]--- 3,3V In attachment are pictures from my setup ;) -- Regards, Oleksij -- Regards, Oleksij -- Regards, Oleksij ___ ath9k-devel mailing list ath9k-devel@lists.ath9k.org https://lists.ath9k.org/mailman/listinfo/ath9k-devel
Re: [ath9k-devel] uart interface issues (fixed)
Hi Oleksij, Have you tried remote debugging? Or it's only about garbing logs from the chip. Have you tried to send commands to the chip? 2013/5/2 Oleksij Rempel li...@rempel-privat.de: Am 28.04.2013 16:17, schrieb Oleksij Rempel: Am 28.04.2013 13:38, schrieb Adrian Chadd: .. is it triggering BREAK interrupts or something? I don't know, there is no serial output on this stage. JTAG may help if the protocol is some how similar to EJTAG. Are there any documentation about Xtensa dubug interface ;)? I will need to dig in it, but not this week. That may be something that the boot ROM code interprets as a magical don't start sequence or something. So, this issue is fixed now. ttl TX --[2K]o RX pin on AR7010 |[4K pull up]--- 3,3V In attachment are pictures from my setup ;) -- Regards, Oleksij -- Best regards, Eugene ___ ath9k-devel mailing list ath9k-devel@lists.ath9k.org https://lists.ath9k.org/mailman/listinfo/ath9k-devel