Re: [PATCH] commands: firmwareload: add CMD_GROUP
On Thu, Oct 09, 2014 at 11:19:28AM +0200, Steffen Trumtrar wrote: To be able to build the documentation the CMD_GROUP macro needs to be defined. Without this the firmwareload command breaks make docs. Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de Applied, thanks Sascha --- commands/firmwareload.c | 1 + 1 file changed, 1 insertion(+) diff --git a/commands/firmwareload.c b/commands/firmwareload.c index a2596951a795..071f25be99b5 100644 --- a/commands/firmwareload.c +++ b/commands/firmwareload.c @@ -62,5 +62,6 @@ BAREBOX_CMD_HELP_END BAREBOX_CMD_START(firmwareload) .cmd = do_firmwareload, BAREBOX_CMD_DESC(Program a firmware file into a device) + BAREBOX_CMD_GROUP(CMD_GRP_MISC) BAREBOX_CMD_HELP(cmd_firmwareload_help) BAREBOX_CMD_END -- 2.1.0 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH 0/2] mips: qemu-malta: add little-endian mode support
On Fri, Oct 10, 2014 at 12:08:55AM +0400, Antony Pavlov wrote: Antony Pavlov (2): mips: qemu-malta: add little-endian mode support Documentation: mips: add little-endian qemu-malta HOWTO Hm, nice. Adding big endian support to Arm would not be that simple. Applied, thanks Sascha Documentation/boards/mips/qemu-malta.rst | 24 arch/mips/Kconfig| 1 + arch/mips/include/asm/gt64120.h | 7 +++ 3 files changed, 32 insertions(+) -- 2.1.1 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: Wrong relocation with Mini2440
Hi Luigi,
On Fri, Oct 10, 2014 at 12:24:40AM +0200, luigi origa wrote:
I'm trying to have barebox working on my mini2440. After many test,
today i got a jtag interface and after some check i found this:
- source s3c24x0_nand_boot -
2: ldr sp, =(TEXT_BASE - SZ_2M) /* Setup a temporary stack in SDRAM */
/*
* We still run at a location we are not linked to. But lets still running
* from the internal SRAM, this may speed up the boot
*/
push {lr}
bl nand_boot
pop {lr}
/*
* Adjust the return address to the correct address in SDRAM
*/
ldr r1, =(TEXT_BASE - SZ_2M)
add lr, lr, r1
mov pc, lr
- compiled s3c24x0_nand_boot -
ROM:0320 loc_320 ; CODE XREF:
s3c24x0_nand_boot+10j
ROM:0320 MOV SP, #0x33C0
ROM:0324 STMFD SP!, {LR}
ROM:0328 BL nand_boot
ROM:032C LDMFD SP!, {LR}
ROM:0330 MOV R1, #0x33C0
ROM:0334 ADD LR, LR, R1
- source nand_boot -
void __nand_boot_init nand_boot(void)
{
void *dest = _text;
int size = ld_var(_barebox_image_size);
int page = 0;
s3c24x0_nand_load_image(dest, size, page);
}
- compiled nand_boot-
ROM:01E0 MOV R1, R0 // size
ROM:01E4 LDR R0, =0x33E0 // *dest
ROM:01E8 MOV R2, #0
ROM:01EC LDMFD SP!, {R4,LR}
ROM:01F0 B s3c24x0_nand_load_image
0x33c0 is the sdram stack where the program should be copied from
nand. Unfortunately the function nand_boot copy from nand to sdram
@0x33e0.
When s3c24x0_nand_boot try to jump in sdram, use a wrong address
(0x33c00220 instead 0x33e00220).
I don't know if the problem is in TEXT_BASE - SZ_2M or _text.
Do you have PBL enabled? Could you enable PBL if not? Additionally
could you revert:
commit 558d72dc5116fc6275ea77c783cc65d6d1a5b521
Author: Michael Olbrich m.olbr...@pengutronix.de
Date: Sun May 18 16:46:29 2014 +0200
ARM Samsung: fix booting from NAND with pbl
The ARM pbl is linked at (TEXT_BASE - SZ_2M). This conflicts with the
temporary
stack used in s3c24x0_nand_boot. Moving the stack to (TEXT_BASE - SZ_2M)
fixes
this problem. With this patch a compressed barebox with pbl can boot on
mini2440 from NAND.
Signed-off-by: Michael Olbrich m.olbr...@pengutronix.de
Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
I suspect This patch fixed booting with PBL enabled but broke booting
without PBL.
Sascha
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Re: [PATCH 0/2] mips: qemu-malta: add little-endian mode support
On Fri, 10 Oct 2014 08:38:21 +0200 Sascha Hauer s.ha...@pengutronix.de wrote: On Fri, Oct 10, 2014 at 12:08:55AM +0400, Antony Pavlov wrote: Antony Pavlov (2): mips: qemu-malta: add little-endian mode support Documentation: mips: add little-endian qemu-malta HOWTO Hm, nice. Adding big endian support to Arm would not be that simple. Actually most of mips chips supported by barebox are little-endian only (bcm47xx, loongson, xburst). So all little-endian support work was already done before. Malta is bi-endian but I suppose little-endian mode is more popular so it is handy to have real working little-endian qemu-malta support. Nevertheless I prefer to use big-endian qemu-malta most of the time as it does not need this odd boot image file byte swapping (see Documentation-related second patch in this series). Documentation/boards/mips/qemu-malta.rst | 24 arch/mips/Kconfig| 1 + arch/mips/include/asm/gt64120.h | 7 +++ 3 files changed, 32 insertions(+) -- 2.1.1 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | -- -- Best regards, Antony Pavlov ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH 1/6] ARM: defconfig: Enable of_display_timings in am335x_defconfig
Signed-off-by: Teresa Gámez t.ga...@phytec.de --- arch/arm/configs/am335x_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/am335x_defconfig b/arch/arm/configs/am335x_defconfig index 6ef9c83..7dcfaed 100644 --- a/arch/arm/configs/am335x_defconfig +++ b/arch/arm/configs/am335x_defconfig @@ -79,6 +79,7 @@ CONFIG_CMD_USBGADGET=y CONFIG_CMD_BAREBOX_UPDATE=y CONFIG_CMD_OF_NODE=y CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OF_DISPLAY_TIMINGS=y CONFIG_CMD_OFTREE=y CONFIG_CMD_TIME=y CONFIG_NET=y -- 1.9.1 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH 2/6] net: cpsw: Fix probe for one port ethernet
If only one port is pinned out, probe fails
as the second port phy_id is not found.
Signed-off-by: Teresa Gámez t.ga...@phytec.de
---
drivers/net/cpsw.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index 167b2dd..9c8cff3 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -1071,7 +1071,7 @@ static int cpsw_probe_dt(struct cpsw_priv *priv)
return ret;
}
- if (!strncmp(child-name, slave, 5)) {
+ if (i priv-num_slaves !strncmp(child-name, slave, 5)) {
struct cpsw_slave *slave = priv-slaves[i];
uint32_t phy_id[2];
@@ -1088,7 +1088,7 @@ static int cpsw_probe_dt(struct cpsw_priv *priv)
}
}
- for (i = 0; i 2; i++) {
+ for (i = 0; i priv-num_slaves; i++) {
struct cpsw_slave *slave = priv-slaves[i];
cpsw_gmii_sel_am335x(slave);
--
1.9.1
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[PATCH 3/6] phyCORE-AM335x: Update default enviroment
- Set default bootsource to the $boosource variable - Pass ip to kernel on all boot options - mount rootfs rw Signed-off-by: Teresa Gámez t.ga...@phytec.de --- .../phytec-phycore-am335x/defaultenv-phycore-am335x/boot/mmc | 7 +-- .../phytec-phycore-am335x/defaultenv-phycore-am335x/boot/nand | 5 - .../phytec-phycore-am335x/defaultenv-phycore-am335x/boot/spi | 4 +++- .../defaultenv-phycore-am335x/config-board | 10 ++ 4 files changed, 22 insertions(+), 4 deletions(-) diff --git a/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/boot/mmc b/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/boot/mmc index 32854d1..6a60761 100644 --- a/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/boot/mmc +++ b/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/boot/mmc @@ -1,5 +1,8 @@ #!/bin/sh -global.bootm.image=/boot/uImage +global.bootm.image=/boot/linuximage #global.bootm.oftree=/boot/oftree -global.linux.bootargs.dyn.root=root=/dev/mmcblk0p2 rootfstype=ext3 rootwait + +bootargs-ip + +global.linux.bootargs.dyn.root=root=/dev/mmcblk0p2 rootfstype=ext3 rw rootwait diff --git a/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/boot/nand b/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/boot/nand index cdfd93d..d9ef145 100644 --- a/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/boot/nand +++ b/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/boot/nand @@ -2,4 +2,7 @@ global.bootm.image=/dev/nand0.kernel.bb #global.bootm.oftree=/env/oftree -global.linux.bootargs.dyn.root=root=ubi0:root ubi.mtd=nand0.root,2048 rootfstype=ubifs + +bootargs-ip + +global.linux.bootargs.dyn.root=root=ubi0:root ubi.mtd=nand0.root,2048 rw rootfstype=ubifs diff --git a/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/boot/spi b/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/boot/spi index 7a53d84..c87299a 100644 --- a/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/boot/spi +++ b/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/boot/spi @@ -2,5 +2,7 @@ global.bootm.image=/dev/m25p0.kernel +bootargs-ip + # Use rootfs form NAND for now as rootfs partition 4MB -global.linux.bootargs.dyn.root=root=ubi0:root ubi.mtd=nand0.root,2048 rootfstype=ubifs +global.linux.bootargs.dyn.root=root=ubi0:root ubi.mtd=nand0.root,2048 rw rootfstype=ubifs diff --git a/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/config-board b/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/config-board index 7f0b2b7..a492ed1 100644 --- a/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/config-board +++ b/arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/config-board @@ -5,3 +5,13 @@ global.hostname=pcm051 global.linux.bootargs.base=console=ttyO0,115200 + +if [ $bootsource = mmc ]; then + global.boot.default=mmc nand spi net +elif [ $boosource = nand ]; then + global.boot.default=nand spi mmc net +elif [ $boosource = spi ]; then + global.boot.default=spi nand mmc net +elif [ $boosource = net ]; then + global.boot.default=net nand spi mmc +fi -- 1.9.1 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH 4/6] phyCORE-AM335x: Strip down device tree
The phyCORE-AM335x is a SOM that can be connected to different
carrierboards like PCM-953, phyBOARD-WEGA and phyBOARD-MAIA.
It is enough for the bootloader to support the SOM specific
parts and can be so used also on different carrierboards.
Removed carrierboard specific settings like led and the
second ethernet slave.
Signed-off-by: Teresa Gámez t.ga...@phytec.de
---
arch/arm/dts/am335x-phytec-phycore.dts | 41 +-
1 file changed, 1 insertion(+), 40 deletions(-)
diff --git a/arch/arm/dts/am335x-phytec-phycore.dts
b/arch/arm/dts/am335x-phytec-phycore.dts
index e7e7780..1a1352f 100644
--- a/arch/arm/dts/am335x-phytec-phycore.dts
+++ b/arch/arm/dts/am335x-phytec-phycore.dts
@@ -21,23 +21,6 @@
status = disabled;
};
};
-
- gpio-leds {
- compatible = gpio-leds;
- pinctrl-names = default;
- pinctrl-0 = pcm051_led_pins;
-
- led-green {
- label = green;
- gpios = gpio1 30 0;
- linux,default-trigger = heartbeat;
- };
-
- led-amber {
- label = amber;
- gpios = gpio1 31 1;
- };
- };
};
am33xx_pinmux {
@@ -72,7 +55,6 @@
0xfc (MUX_MODE0 | INPUT_EN | PULL_UP) /*
mmc0_dat0.mmc0_dat0 */
0x100 (MUX_MODE0 | INPUT_EN | PULL_UP) /*
mmc0_clk.mmc0_clk */
0x104 (MUX_MODE0 | INPUT_EN | PULL_UP) /*
mmc0_cmd.mmc0_cmd */
- 0x160 (MUX_MODE7 | INPUT_EN | PULL_UP) /* spi0_cs1.??,
card detect */
;
};
@@ -86,20 +68,6 @@
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /*
mii1_rxd1.rmii1_rxd1 */
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /*
mii1_rxd0.rmii1_rxd0 */
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /*
rmii1_refclk.rmii1_refclk */
-
- /* Slave 2 */
- 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
gpmc_a0.rgmii2_tctl */
- 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
gpmc_a1.rgmii2_rctl */
- 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
gpmc_a2.rgmii2_td3 */
- 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
gpmc_a3.rgmii2_td2 */
- 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
gpmc_a4.rgmii2_td1 */
- 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
gpmc_a5.rgmii2_td0 */
- 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /*
gpmc_a6.rgmii2_tclk */
- 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
gpmc_a7.rgmii2_rclk */
- 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
gpmc_a8.rgmii2_rd3 */
- 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
gpmc_a9.rgmii2_rd2 */
- 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
gpmc_a10.rgmii2_rd1 */
- 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /*
gpmc_a11.rgmii2_rd0 */
;
};
@@ -224,19 +192,12 @@
cpsw_emac0 {
phy_id = davinci_mdio, 0;
phy-mode = rmii;
- dual_emac_res_vlan = 1;
-};
-
-cpsw_emac1 {
- phy_id = davinci_mdio, 2;
- phy-mode = rgmii;
- dual_emac_res_vlan = 2;
};
mac {
pinctrl-names = default;
pinctrl-0 = emac_rmii1_pins;
- dual_emac = 1;
+ slaves = 1;
status = okay;
};
--
1.9.1
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[PATCH 6/6] phyCORE-AM335x: Add barebox image without SPI NOR
Boards like phyBOARD-WEGA RDK have an phyCORE-AM335x
connected with no SPI NOR flash. Added dts to support this.
Signed-off-by: Teresa Gámez t.ga...@phytec.de
---
arch/arm/boards/phytec-phycore-am335x/lowlevel.c | 10 ++
arch/arm/dts/Makefile | 2 +-
arch/arm/dts/am335x-phytec-phycore-som-no-spi.dts | 20
images/Makefile.am33xx| 4
4 files changed, 35 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/am335x-phytec-phycore-som-no-spi.dts
diff --git a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
index 47902d0..55cc667 100644
--- a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
+++ b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
@@ -118,6 +118,7 @@ struct pcm051_sdram_timings timings[] = {
};
extern char __dtb_am335x_phytec_phycore_som_start[];
+extern char __dtb_am335x_phytec_phycore_som_no_spi_start[];
/**
* @brief The basic entry point for board initialization.
@@ -202,3 +203,12 @@ ENTRY_FUNCTION(start_am33xx_phytec_phycore_sdram, r0, r1,
r2)
am335x_barebox_entry(fdt);
}
+
+ENTRY_FUNCTION(start_am33xx_phytec_phycore_no_spi_sdram, r0, r1, r2)
+{
+ void *fdt;
+
+ fdt = __dtb_am335x_phytec_phycore_som_no_spi_start -
get_runtime_offset();
+
+ am335x_barebox_entry(fdt);
+}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 65ed022..ede2b59 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -26,7 +26,7 @@ pbl-dtb-$(CONFIG_MACH_NVIDIA_JETSON) +=
tegra124-jetson-tk1.dtb.o
pbl-dtb-$(CONFIG_MACH_PCA100) += imx27-phytec-phycard-s-rdk-bb.dtb.o
pbl-dtb-$(CONFIG_MACH_PCAAXL3) += imx6q-phytec-pbaa03.dtb.o
pbl-dtb-$(CONFIG_MACH_PCM038) += imx27-phytec-phycore-rdk.dtb.o
-pbl-dtb-$(CONFIG_MACH_PCM051) += am335x-phytec-phycore-som.dtb.o
+pbl-dtb-$(CONFIG_MACH_PCM051) += am335x-phytec-phycore-som.dtb.o
am335x-phytec-phycore-som-no-spi.dtb.o
pbl-dtb-$(CONFIG_MACH_PHYTEC_PFLA02) += imx6s-phytec-pbab01.dtb.o
imx6dl-phytec-pbab01.dtb.o imx6q-phytec-pbab01.dtb.o
pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) +=
armada-xp-openblocks-ax3-4-bb.dtb.o
pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) +=
kirkwood-openblocks_a6-bb.dtb.o
diff --git a/arch/arm/dts/am335x-phytec-phycore-som-no-spi.dts
b/arch/arm/dts/am335x-phytec-phycore-som-no-spi.dts
new file mode 100644
index 000..6350706
--- /dev/null
+++ b/arch/arm/dts/am335x-phytec-phycore-som-no-spi.dts
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2014 Teresa Gámez t.ga...@phytec.de Phytec Messtechnik GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include am33xx.dtsi
+#include am335x-phytec-phycore-som.dtsi
+
+/ {
+ model = Phytec phyCORE AM335x;
+ compatible = phytec,phycore-am335x-som, ti,am33xx;
+};
+
+eeprom {
+ status = okay;
+};
diff --git a/images/Makefile.am33xx b/images/Makefile.am33xx
index 92dd61a..8d58733 100644
--- a/images/Makefile.am33xx
+++ b/images/Makefile.am33xx
@@ -19,6 +19,10 @@ pblx-$(CONFIG_MACH_PCM051) +=
start_am33xx_phytec_phycore_sdram
FILE_barebox-am33xx-phytec-phycore.img = start_am33xx_phytec_phycore_sdram.pblx
am33xx-barebox-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore.img
+pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_no_spi_sdram
+FILE_barebox-am33xx-phytec-phycore-no-spi.img =
start_am33xx_phytec_phycore_no_spi_sdram.pblx
+am33xx-barebox-$(CONFIG_MACH_PCM051) +=
barebox-am33xx-phytec-phycore-no-spi.img
+
pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram_256mb
FILE_barebox-am33xx-phytec-phycore-mlo-256mb.img =
start_am33xx_phytec_phycore_sram_256mb.pblx.mlo
am33xx-mlo-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore-mlo-256mb.img
--
1.9.1
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[PATCH 5/6] ARM: dts: split phyCORE-AM335x device tree
To support different module variants, split the phyCORE dts
in dts and dtsi. Configurable parts which are supported by
barebox are spi nor flash and i2c eeprom.
Signed-off-by: Teresa Gámez t.ga...@phytec.de
---
arch/arm/boards/phytec-phycore-am335x/board.c| 4 +-
arch/arm/boards/phytec-phycore-am335x/lowlevel.c | 6 +-
arch/arm/dts/Makefile| 2 +-
arch/arm/dts/am335x-phytec-phycore-som.dts | 24 ++
arch/arm/dts/am335x-phytec-phycore-som.dtsi | 286 ++
arch/arm/dts/am335x-phytec-phycore.dts | 292 ---
6 files changed, 316 insertions(+), 298 deletions(-)
create mode 100644 arch/arm/dts/am335x-phytec-phycore-som.dts
create mode 100644 arch/arm/dts/am335x-phytec-phycore-som.dtsi
delete mode 100644 arch/arm/dts/am335x-phytec-phycore.dts
diff --git a/arch/arm/boards/phytec-phycore-am335x/board.c
b/arch/arm/boards/phytec-phycore-am335x/board.c
index 035866b..64e3904 100644
--- a/arch/arm/boards/phytec-phycore-am335x/board.c
+++ b/arch/arm/boards/phytec-phycore-am335x/board.c
@@ -34,7 +34,7 @@
static int pcm051_coredevice_init(void)
{
- if (!of_machine_is_compatible(phytec,pcm051))
+ if (!of_machine_is_compatible(phytec,phycore-am335x-som))
return 0;
am33xx_register_ethaddr(0, 0);
@@ -58,7 +58,7 @@ static char *xloadslots[] = {
static int pcm051_devices_init(void)
{
- if (!of_machine_is_compatible(phytec,pcm051))
+ if (!of_machine_is_compatible(phytec,phycore-am335x-som))
return 0;
switch (bootsource_get()) {
diff --git a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
index 66bae80..47902d0 100644
--- a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
+++ b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
@@ -117,7 +117,7 @@ struct pcm051_sdram_timings timings[] = {
},
};
-extern char __dtb_am335x_phytec_phycore_start[];
+extern char __dtb_am335x_phytec_phycore_som_start[];
/**
* @brief The basic entry point for board initialization.
@@ -153,7 +153,7 @@ static noinline void pcm051_board_init(int sdram)
omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE);
putc_ll('');
- fdt = __dtb_am335x_phytec_phycore_start - get_runtime_offset();
+ fdt = __dtb_am335x_phytec_phycore_som_start - get_runtime_offset();
am335x_barebox_entry(fdt);
}
@@ -198,7 +198,7 @@ ENTRY_FUNCTION(start_am33xx_phytec_phycore_sdram, r0, r1,
r2)
{
void *fdt;
- fdt = __dtb_am335x_phytec_phycore_start - get_runtime_offset();
+ fdt = __dtb_am335x_phytec_phycore_som_start - get_runtime_offset();
am335x_barebox_entry(fdt);
}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3fcd5f1..65ed022 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -26,7 +26,7 @@ pbl-dtb-$(CONFIG_MACH_NVIDIA_JETSON) +=
tegra124-jetson-tk1.dtb.o
pbl-dtb-$(CONFIG_MACH_PCA100) += imx27-phytec-phycard-s-rdk-bb.dtb.o
pbl-dtb-$(CONFIG_MACH_PCAAXL3) += imx6q-phytec-pbaa03.dtb.o
pbl-dtb-$(CONFIG_MACH_PCM038) += imx27-phytec-phycore-rdk.dtb.o
-pbl-dtb-$(CONFIG_MACH_PCM051) += am335x-phytec-phycore.dtb.o
+pbl-dtb-$(CONFIG_MACH_PCM051) += am335x-phytec-phycore-som.dtb.o
pbl-dtb-$(CONFIG_MACH_PHYTEC_PFLA02) += imx6s-phytec-pbab01.dtb.o
imx6dl-phytec-pbab01.dtb.o imx6q-phytec-pbab01.dtb.o
pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) +=
armada-xp-openblocks-ax3-4-bb.dtb.o
pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) +=
kirkwood-openblocks_a6-bb.dtb.o
diff --git a/arch/arm/dts/am335x-phytec-phycore-som.dts
b/arch/arm/dts/am335x-phytec-phycore-som.dts
new file mode 100644
index 000..93f09e2
--- /dev/null
+++ b/arch/arm/dts/am335x-phytec-phycore-som.dts
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2014 Teresa Gámez t.ga...@phytec.de Phytec Messtechnik GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include am33xx.dtsi
+#include am335x-phytec-phycore-som.dtsi
+
+/ {
+ model = Phytec phyCORE AM335x;
+ compatible = phytec,phycore-am335x-som, ti,am33xx;
+};
+
+spi0 {
+ status = okay;
+};
+
+eeprom {
+ status = okay;
+};
diff --git a/arch/arm/dts/am335x-phytec-phycore-som.dtsi
b/arch/arm/dts/am335x-phytec-phycore-som.dtsi
new file mode 100644
index 000..f1bcb8b
--- /dev/null
+++ b/arch/arm/dts/am335x-phytec-phycore-som.dtsi
@@ -0,0 +1,286 @@
+/ {
+ chosen {
+ linux,stdout-path = uart0;
+
+ environment-spi {
+ compatible = barebox,environment;
+ device-path = flash, partname:bareboxenv;
+ status = disabled;
+ };
+
+ environment-nand {
+ compatible = barebox,environment;
+
Re: Wrong relocation with Mini2440
I tried enabling pbl with the default values and it works. I tried
also changing the address at 0x33c0 (instead the default
0x33e0) with pbl disabled and works again.
Thanks for the help.
Luigi
2014-10-10 8:42 GMT+02:00 Sascha Hauer s.ha...@pengutronix.de:
Hi Luigi,
On Fri, Oct 10, 2014 at 12:24:40AM +0200, luigi origa wrote:
I'm trying to have barebox working on my mini2440. After many test,
today i got a jtag interface and after some check i found this:
- source s3c24x0_nand_boot -
2: ldr sp, =(TEXT_BASE - SZ_2M) /* Setup a temporary stack in SDRAM */
/*
* We still run at a location we are not linked to. But lets still running
* from the internal SRAM, this may speed up the boot
*/
push {lr}
bl nand_boot
pop {lr}
/*
* Adjust the return address to the correct address in SDRAM
*/
ldr r1, =(TEXT_BASE - SZ_2M)
add lr, lr, r1
mov pc, lr
- compiled s3c24x0_nand_boot -
ROM:0320 loc_320 ; CODE XREF:
s3c24x0_nand_boot+10 j
ROM:0320 MOV SP, #0x33C0
ROM:0324 STMFD SP!, {LR}
ROM:0328 BL nand_boot
ROM:032C LDMFD SP!, {LR}
ROM:0330 MOV R1, #0x33C0
ROM:0334 ADD LR, LR, R1
- source nand_boot -
void __nand_boot_init nand_boot(void)
{
void *dest = _text;
int size = ld_var(_barebox_image_size);
int page = 0;
s3c24x0_nand_load_image(dest, size, page);
}
- compiled nand_boot-
ROM:01E0 MOV R1, R0 // size
ROM:01E4 LDR R0, =0x33E0 // *dest
ROM:01E8 MOV R2, #0
ROM:01EC LDMFD SP!, {R4,LR}
ROM:01F0 B s3c24x0_nand_load_image
0x33c0 is the sdram stack where the program should be copied from
nand. Unfortunately the function nand_boot copy from nand to sdram
@0x33e0.
When s3c24x0_nand_boot try to jump in sdram, use a wrong address
(0x33c00220 instead 0x33e00220).
I don't know if the problem is in TEXT_BASE - SZ_2M or _text.
Do you have PBL enabled? Could you enable PBL if not? Additionally
could you revert:
commit 558d72dc5116fc6275ea77c783cc65d6d1a5b521
Author: Michael Olbrich m.olbr...@pengutronix.de
Date: Sun May 18 16:46:29 2014 +0200
ARM Samsung: fix booting from NAND with pbl
The ARM pbl is linked at (TEXT_BASE - SZ_2M). This conflicts with the
temporary
stack used in s3c24x0_nand_boot. Moving the stack to (TEXT_BASE - SZ_2M)
fixes
this problem. With this patch a compressed barebox with pbl can boot on
mini2440 from NAND.
Signed-off-by: Michael Olbrich m.olbr...@pengutronix.de
Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
I suspect This patch fixed booting with PBL enabled but broke booting
without PBL.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
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