Re: [PATCH 14/14] don't cast negative error codes to unsigned size_t

[Juergen Beisert]

On Friday 07 February 2014 09:48:56 Lucas Stach wrote:
 The cast prevents us from doing proper error checking.

 Signed-off-by: Lucas Stach d...@lynxeye.de
 ---
  common/uimage.c | 6 +++---
  include/image.h | 2 +-
  2 files changed, 4 insertions(+), 4 deletions(-)

 diff --git a/common/uimage.c b/common/uimage.c
 index 7fbef86..4296359 100644
 --- a/common/uimage.c
 +++ b/common/uimage.c
 @@ -74,7 +74,7 @@ void uimage_print_contents(struct uimage_handle *handle)
  }
  EXPORT_SYMBOL(uimage_print_contents);

 -size_t uimage_get_size(struct uimage_handle *handle, unsigned int image_no)
 +int uimage_get_size(struct uimage_handle *handle, unsigned int image_no)

What about ssize_t?

jbe

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[PATCH 1/3] FPGA: add a simple programming handler framework

[Juergen Beisert]

This framework handles a list of registered FPGA programming handlers
to unify a firmware programming interface by hiding the details how
to program a specific FPGA in its handler.

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 common/Kconfig|   3 ++
 common/Makefile   |   1 +
 common/fpgamgr.c  | 122 ++
 include/fpgamgr.h |  58 ++
 4 files changed, 184 insertions(+)
 create mode 100644 common/fpgamgr.c
 create mode 100644 include/fpgamgr.h

diff --git a/common/Kconfig b/common/Kconfig
index ccfbc80..d87e59b 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -297,6 +297,9 @@ config MAXARGS
prompt max. Number of arguments accepted for monitor commands
default 16
 
+config FPGAMANAGER
+   bool
+
 choice
prompt Select your shell
 
diff --git a/common/Makefile b/common/Makefile
index 6f6e360..537dea4 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -48,6 +48,7 @@ obj-y += bootsource.o
 obj-$(CONFIG_BOOTM) += bootm.o
 extra-$(CONFIG_MODULES) += module.lds
 extra-y += barebox_default_env barebox_default_env.h
+obj-$(CONFIG_FPGAMANAGER) += fpgamgr.o
 
 ifdef CONFIG_DEFAULT_ENVIRONMENT
 $(obj)/startup.o: $(obj)/barebox_default_env.h
diff --git a/common/fpgamgr.c b/common/fpgamgr.c
new file mode 100644
index 000..4e36330
--- /dev/null
+++ b/common/fpgamgr.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2013 Juergen Beisert ker...@pengutronix.de, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include common.h
+#include fpgamgr.h
+#include linux/list.h
+#include xfuncs.h
+#include malloc.h
+
+struct fpga_mgr {
+   struct list_head list;
+   struct fpga_handler *handler; /* the program handler */
+   unsigned index;
+   unsigned flags;
+};
+
+static LIST_HEAD(fpgamgr_prog_handlers);
+
+static struct fpga_mgr *fpgamgr_init(void)
+{
+   struct fpga_mgr *handler;
+
+   handler = xzalloc(sizeof(struct fpga_mgr));
+   return handler;
+}
+
+struct fpga_mgr *fpgamgr_find_handler(const char *name, int index)
+{
+   struct fpga_mgr *mgr;
+
+   if (!name)
+   return -EINVAL;
+
+   list_for_each_entry(mgr, fpgamgr_prog_handlers, list) {
+   if (!strcmp(mgr-handler-name, name)) {
+   if (index == -1 || index == mgr-index)
+   return mgr;
+   }
+   }
+
+   return NULL;
+}
+
+void fpgamgr_handlers_list(void)
+{
+   struct fpga_mgr *mgr;
+
+   if (list_empty(fpgamgr_prog_handlers))
+   printf((none)\n);
+
+   list_for_each_entry(mgr, fpgamgr_prog_handlers, list)
+   printf(%s%-11s idx %u\n,
+   mgr-flags  FPGAMGR_HANDLER_FLAG_DEFAULT ?
+   *  :   , mgr-handler-name, mgr-index);
+}
+
+/* make the device accessible to the public via its handler */
+int fpgamgr_register_handler(struct fpga_handler *h)
+{
+   struct fpga_mgr *mgr;
+   int index = 0;
+
+   if (fpgamgr_find_handler(h-name, -1) != 0) {
+   /* find the next free index for this name */
+   do
+   index++;
+   while (fpgamgr_find_handler(h-name, index) != NULL);
+   }
+
+   mgr = fpgamgr_init();
+   mgr-handler = h;
+   mgr-index = index;
+
+   list_add_tail(mgr-list, fpgamgr_prog_handlers);
+
+   return 0;
+}
+
+int fpgamgr_open_fpga(struct fpga_mgr *m)
+{
+   struct fpga_handler *h = m-handler;
+
+   if (h-open)
+   return h-open(h);
+
+   return -ENOSYS;
+}
+
+/*
+ * Expectation is 'cnt' in bytes and it *must* be a multiple of 8 bytes.
+ * Only the last call prior calling fpgamgr_close_fpga() can violate
+ * this rule.
+ */
+int fpgamgr_prog_fpga(struct fpga_mgr *m, const void *data, size_t cnt)
+{
+   struct fpga_handler *h = m-handler;
+
+   if (h-write)
+   return h-write(h, data, cnt);
+
+   return -ENOSYS;
+}
+
+int fpgamgr_close_fpga(struct fpga_mgr *m)
+{
+   struct fpga_handler *h = m-handler;
+
+   if (h-close)
+   return h-close(h);
+
+   return -ENOSYS;
+}
diff --git a/include/fpgamgr.h b/include/fpgamgr.h
new file mode 100644
index 000..8f94998
--- /dev/null
+++ b/include/fpgamgr.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2013 Juergen Beisert ker...@pengutronix.de, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published

[PATCH 3/3] FPGA: provide a handler to program ALTERA FPGAs

[Juergen Beisert]

This handler uses a regular SPI master and a few GPIO to program an ALTERA FPGA
in serial mode.

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 drivers/Kconfig  |   1 +
 drivers/Makefile |   1 +
 drivers/fpga/Kconfig |  10 ++
 drivers/fpga/Makefile|   2 +
 drivers/fpga/altera_serial.c | 278 +++
 5 files changed, 292 insertions(+)
 create mode 100644 drivers/fpga/Kconfig
 create mode 100644 drivers/fpga/Makefile
 create mode 100644 drivers/fpga/altera_serial.c

diff --git a/drivers/Kconfig b/drivers/Kconfig
index d34d2c7..ac3c699 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -25,5 +25,6 @@ source drivers/gpio/Kconfig
 source drivers/w1/Kconfig
 source drivers/pinctrl/Kconfig
 source drivers/bus/Kconfig
+source drivers/fpga/Kconfig
 
 endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index ba1dc6d..fa4aace 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_OFTREE) += of/
 obj-$(CONFIG_W1) += w1/
 obj-y += pinctrl/
 obj-y += bus/
+obj-y += fpga/
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
new file mode 100644
index 000..204e852
--- /dev/null
+++ b/drivers/fpga/Kconfig
@@ -0,0 +1,10 @@
+menu FPGA programming
+
+config ALTERA_SERIAL
+   bool Altera SPI programming
+   depends on FPGAMANAGER  OFDEVICE
+   help
+ Programming an Altera FPGA via a few GPIOs for the control lines and
+ MOSI, MISO and clock from an SPI interface for the data lines
+
+endmenu
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
new file mode 100644
index 000..3147634
--- /dev/null
+++ b/drivers/fpga/Makefile
@@ -0,0 +1,2 @@
+
+obj-$(CONFIG_ALTERA_SERIAL) += altera_serial.o
diff --git a/drivers/fpga/altera_serial.c b/drivers/fpga/altera_serial.c
new file mode 100644
index 000..cf05845
--- /dev/null
+++ b/drivers/fpga/altera_serial.c
@@ -0,0 +1,278 @@
+/*
+ * Copyright (c) 2013 Juergen Beisert ker...@pengutronix.de, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include common.h
+#include init.h
+#include driver.h
+#include fpgamgr.h
+#include of_gpio.h
+#include xfuncs.h
+#include malloc.h
+#include gpio.h
+#include clock.h
+#include spi/spi.h
+
+/*
+ * Physical requirements:
+ * - three free GPIOs for the signals nCONFIG, CONFIGURE_DONE, nSTATUS
+ * - 32 bit per word, LSB first capable SPI master (MOSI + clock)
+ *
+ * Example how to configure this driver via device tree
+ *
+ * fpga@0 {
+ * compatible = altera_serial;
+ * nstat-gpio = gpio4 18 0;
+ * confd-gpio = gpio4 19 0;
+ * nconfig-gpio = gpio4 20 0;
+ * spi-max-frequency = 1000;
+ * reg = 0;
+ * };
+ */
+
+struct fpga_spi {
+   int nstat_gpio; /* input GPIO to read the status line */
+   int confd_gpio; /* input GPIO to read the config done line */
+   int nconfig_gpio; /* output GPIO to start the FPGA's config */
+   struct device_d *dev;
+   struct spi_device *spi;
+   bool padding_done;
+};
+
+static int altera_spi_open(struct fpga_handler *h)
+{
+   struct fpga_spi *this = (struct fpga_spi *)h-private_data;
+   struct device_d *dev = this-dev;
+   int ret;
+
+   dev_dbg(dev, Initiating programming\n);
+
+   /* initiate an FPGA programming */
+   gpio_set_value(this-nconfig_gpio, 0);
+
+   /*
+* after about 2 µs the FPGA must acknowledge with
+* STATUS and CONFIG DONE lines at low level
+*/
+   ret = wait_on_timeout(2 * 1000,
+   (gpio_get_value(this-nstat_gpio) == 0) 
+   (gpio_get_value(this-confd_gpio) == 0));
+
+   if (ret != 0) {
+   dev_err(dev, FPGA does not acknowledge the programming 
initiation\n);
+   if (gpio_get_value(this-nstat_gpio))
+   dev_err(dev, STATUS is still high!\n);
+   if (gpio_get_value(this-confd_gpio))
+   dev_err(dev, CONFIG DONE is still high!\n);
+   return ret;
+   }
+
+   /* arm the FPGA to await its new firmware */
+   gpio_set_value(this-nconfig_gpio, 1);
+
+   /* once again, we might need padding the data */
+   this-padding_done = false;
+
+   /*
+* after about 1506 µs the FPGA must acknowledge this step
+* with the STATUS line at high level
+*/
+   ret = wait_on_timeout(1600 * 1000,
+   gpio_get_value(this-nstat_gpio) == 1);
+   if (ret != 0

Re: [PATCH 2/6] mci: do not limit clock to card capabilities

[Juergen Beisert]

Hi Sascha,

Sascha Hauer wrote:
 No need to limit the clock to the cards capabilities since the values
 passed to mci_set_clock are based on the cards capabilities. This
 enables MMC high speed cards to operate at higher speeds since on
 this cards the csd field only holds the non highspeed maximum clock.

 Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
 ---
  drivers/mci/mci-core.c | 4 
  1 file changed, 4 deletions(-)

 diff --git a/drivers/mci/mci-core.c b/drivers/mci/mci-core.c
 index 283df2f..895108f 100644
 --- a/drivers/mci/mci-core.c
 +++ b/drivers/mci/mci-core.c
 @@ -664,10 +664,6 @@ static void mci_set_clock(struct mci *mci, unsigned 
 clock)
   if (clock  host-f_min) 
   clock = host-f_min;

 - /* check against the limit at the card's side */
 - if (mci-tran_speed != 0  clock  mci-tran_speed)
 - clock = mci-tran_speed;
 -
   host-clock = clock;/* the new target frequency */
   mci_set_ios(mci);
  }

I'm not sure. In mci_startup_sd() there is a very primitive decision for the
clock frequency.

/* if possible, speed up the transfer */
if (mci-card_caps  MMC_MODE_HS)
mci_set_clock(mci, 5000);
else
mci_set_clock(mci, 2500);

And yes, the spec tells us, there are two cards at 3.3 V available: 25 MHz and
50 MHz. But theoretically a vendor can limit the max transfer speed to a
different value. I'm confused about the spec here, as the card reports a max
transfer speed *and* a standard/high speed bit. Which one is reliable?

jbe

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Re: [PATCH 1/6] mci: print current clock in info

[Juergen Beisert]

Sascha Hauer wrote:
 When printing the cards information the actual clock is much
 more interesting than what the card could support.

 Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
 ---
  drivers/mci/mci-core.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

 diff --git a/drivers/mci/mci-core.c b/drivers/mci/mci-core.c
 index 416168f..283df2f 100644
 --- a/drivers/mci/mci-core.c
 +++ b/drivers/mci/mci-core.c
 @@ -1395,7 +1395,7 @@ static void mci_info(struct device_d *dev)
   mci-cid[2], mci-cid[3]);
   printf(   CSD: %08X-%08X-%08X-%08X\n, mci-csd[0], mci-csd[1],
   mci-csd[2], mci-csd[3]);
 - printf(  Max. transfer speed: %u Hz\n, mci-tran_speed);
 + printf(  clock: %u Hz\n, mci-host-clock);
   printf(  Manufacturer ID: %02X\n, extract_mid(mci));
   printf(  OEM/Application ID: %04X\n, extract_oid(mci));
   printf(  Product name: '%c%c%c%c%c'\n, mci-cid[0]  0xff,

But here you ask for the card itself. If you want to know the currently *used* 
transfer speed you must ask the interface.

Please keep this information available, as it helps others to get some 
information about the used card and might help to debug.

jbe
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Re: [PATCH 3/6] mci: rename trans_speed field to csd_max_dtr

[Juergen Beisert]

Sascha Hauer wrote:
 tran_speed is confusing since the name doesn't tell us if this
 is the maximum speed, the current speed or whatever else. Rename
 it to csd_max_dtr since this variable holds the maximum data transfer
 rate we extracted from csd.

 Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
 ---
  drivers/mci/mci-core.c | 4 ++--
  include/mci.h  | 2 +-
  2 files changed, 3 insertions(+), 3 deletions(-)

 diff --git a/drivers/mci/mci-core.c b/drivers/mci/mci-core.c
 index 895108f..d7b8fc9 100644
 --- a/drivers/mci/mci-core.c
 +++ b/drivers/mci/mci-core.c
 @@ -779,8 +779,8 @@ static void mci_extract_max_tran_speed_from_csd(struct 
 mci *mci)
   return; 
   }

 - mci-tran_speed = time * unit;
 - dev_dbg(mci-dev, Transfer speed: %u\n, mci-tran_speed);
 + mci-csd_max_dtr = time * unit;
 + dev_dbg(mci-dev, Transfer speed: %u\n, mci-csd_max_dtr);
  }

  /**
 diff --git a/include/mci.h b/include/mci.h
 index 1eb967d..2b87691 100644
 --- a/include/mci.h
 +++ b/include/mci.h
 @@ -340,7 +340,7 @@ struct mci {
   unsigned csd[4];/** card's card specific data register */
   unsigned cid[4];/** card's card identification register */
   unsigned short rca; /* FIXME */
 - unsigned tran_speed;/** not yet used */
 + unsigned csd_max_dtr;   /** max data transfer rate as decoded from csd 
 */

^^

\o/ \o/ \o/ ;)

   /** currently used data block length for read accesses */
   unsigned read_bl_len;
   /** currently used data block length for write accesses */

Acked-by: Juergen Beisert j...@pengutronix.de

jbe

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Re: Unable to Boot from NAND on Mini2440

[Juergen Beisert]

Vikram Narayanan wrote:
 On 21/05/2013 00:26, Juergen Beisert wrote:
  Hmm, never had a Mini2440 with a 1 GiB NAND. Can you see, what kind of
  SDRAM devices are on your Mini2440 board? Maybe they also changed the
  SDRAMs...

 Sorry, I was totally away from mail access.
 Here is the name on the chip.
 K4S561632N - 256 Mbit x 2

This memory is different from the HY57V561620 and MT48LC16M16 types I know and 
Barebox is adapted to.

Maybe your system doesn't come up due to a wrong SDRAM configuration.

You should compare the SDRAM datasheets and check if the SDRAM controller 
settings in Mini2440 'config.h' match the requirements of your SDRAM type.

Regards,
Juergen

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[PATCH] MXS/i.MX23: add boot source detection

[Juergen Beisert]

The boot source for the i.MX23 is configured via a few GPIOs, which are later
be used for different purposes (like LCD data for example). The SoC internal
ROM reads these GPIOs and uses the selected boot source.

For various reasons the boot source is also of interest when Barebox is running.
This detection approach reads again the GPIOs. It switches temporarily the pins
to act as GPIOs and input, reads their settings, and switches back to their
previous functions.

Signed-off-by: Juergen Beisert j...@pengutronix.de

---
 arch/arm/mach-mxs/imx.c |   44 +++-
 1 file changed, 43 insertions(+), 1 deletion(-)

Index: barebox-2013.05.0/arch/arm/mach-mxs/imx.c
===
--- barebox-2013.05.0.orig/arch/arm/mach-mxs/imx.c
+++ barebox-2013.05.0/arch/arm/mach-mxs/imx.c
@@ -112,6 +112,48 @@ static void mxs_silicon_revision(void)
silicon_revision_set(product, revision);
 }
 
+#define HW_PINCTRL_MUXSEL2 0x120
+#define HW_PINCTRL_MUXSEL3 0x130
+#define HW_PINCTRL_DOE1 0x710
+#define HW_PINCTRL_DIN1 0x610
+
+/*
+ * we are interested in the setting of:
+ * - GPIO BANK1/19: 1 = the ROM has used the following pins for boot source 
selection
+ * - GPIO BANK1/5: ETM enable
+ * - GPIO BANK1/3: BM3
+ * - GPIO BANK1/2: BM2
+ * - GPIO BANK1/1: BM1
+ * - GPIO BANK1/0: BM0
+ */
+static uint32_t mx23_detect_bootsource(void)
+{
+   uint32_t mux2, mux3, dir, mode;
+
+   mux3 = readl(IMX_IOMUXC_BASE + HW_PINCTRL_MUXSEL3);
+   mux2 = readl(IMX_IOMUXC_BASE + HW_PINCTRL_MUXSEL2);
+   dir = readl(IMX_IOMUXC_BASE + HW_PINCTRL_DOE1);
+
+   /* force the GPIO lines of interest to input */
+   writel(0x0008002f, IMX_IOMUXC_BASE + HW_PINCTRL_DOE1 + 8);
+   /* force the GPIO lines of interest to act as GPIO */
+   writel(0x0cff, IMX_IOMUXC_BASE + HW_PINCTRL_MUXSEL2 + 4);
+   writel(0x00c0, IMX_IOMUXC_BASE + HW_PINCTRL_MUXSEL3 + 4);
+
+   /* read the bootstrapping */
+   mode = readl(IMX_IOMUXC_BASE + HW_PINCTRL_DIN1)  0x8002f;
+
+   /* restore previous settings */
+   writel(mux3, IMX_IOMUXC_BASE + HW_PINCTRL_MUXSEL3);
+   writel(mux2, IMX_IOMUXC_BASE + HW_PINCTRL_MUXSEL2);
+   writel(dir, IMX_IOMUXC_BASE + HW_PINCTRL_DOE1);
+
+   if (!(mode  (1  19)))
+   return 0xff; /* invalid marker */
+
+   return (mode  0xf) | ((mode  0x20)  1);
+}
+
 #define MX28_REV_1_0_MODE  (0x0001a7f0)
 #define MX28_REV_1_2_MODE  (0x00019bf0)
 
@@ -122,7 +164,7 @@ static void mxs_boot_save_loc(void)
uint32_t mode = 0xff;
 
if (cpu_is_mx23()) {
-   /* not implemented yet */
+   mode = mx23_detect_bootsource();
} else if (cpu_is_mx28()) {
enum silicon_revision rev = silicon_revision_get();
 
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Re: [RFC] MXS/i.MX23: detecting the boot source

[Juergen Beisert]

Sascha Hauer wrote:
 On Fri, May 17, 2013 at 10:18:39AM +0200, Juergen Beisert wrote:
  The boot source for the i.MX23 is configured via a few GPIOs, which are
  later be used for different purposes (like LCD data for example). The SoC
  internal ROM reads these GPIOs and uses the selected boot source.
 
  For various reasons the boot source is also of interest when Barebox is
  running. This detection approach reads again the GPIOs. It switches
  temporarily the pins to act as GPIOs and input, reads their values, and
  switches back to their previous functions.
 
  Could this be a reliable way to detect the boot source?

 I don't know. Are the bootstrap pins used as outputs only in the normal
 usecase? Otherwise I could imagine that something is overriding the
 bootstrap pins by the time you read them.

These where also my thoughts. The pins the ROM reads can also be used as
GPIO, LCD data out and for the Embedded Trace Macrocell (ETM). Maybe not 
perfectly reliable, but the chance is high that it works as expected.

There is no real latch register to save the settings after reset (at least I 
didn't found one). Maybe the ROM stores this value somewhere in the internal 
SRAM (like the i.MX28 ROM does), but how to know where?

  BTW: is there a reason why the bootsource will create environment
  variables, while other detected features find their way to the global
  device?

 No, at least not a good one ;)

Ahh, okay :)

  +static uint32_t mxs23_boot_save_loc(void)

 Should you continue working on this please change the name to something
 like mx23_get_bootsource(). This function does not save anything.

Yes, will do so.

jbe

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[RFC] MXS/i.MX23: detecting the boot source

[Juergen Beisert]

The boot source for the i.MX23 is configured via a few GPIOs, which are later
be used for different purposes (like LCD data for example). The SoC internal
ROM reads these GPIOs and uses the selected boot source.

For various reasons the boot source is also of interest when Barebox is running.
This detection approach reads again the GPIOs. It switches temporarily the pins
to act as GPIOs and input, reads their values, and switches back to their
previous functions.

Could this be a reliable way to detect the boot source?

BTW: is there a reason why the bootsource will create environment variables,
while other detected features find their way to the global device?

---
 arch/arm/mach-mxs/imx.c |   46 +-
 1 file changed, 45 insertions(+), 1 deletion(-)

Index: barebox-2013.05.0/arch/arm/mach-mxs/imx.c
===
--- barebox-2013.05.0.orig/arch/arm/mach-mxs/imx.c
+++ barebox-2013.05.0/arch/arm/mach-mxs/imx.c
@@ -112,6 +114,48 @@ static void mxs_silicon_revision(void)
silicon_revision_set(product, revision);
 }
 
+#define HW_PINCTRL_MUXSEL2 0x120
+#define HW_PINCTRL_MUXSEL3 0x130
+#define HW_PINCTRL_DOE1 0x710
+#define HW_PINCTRL_DIN1 0x610
+
+/*
+ * we are interested in the setting of:
+ * - GPIO BANK1/19: 1 = the ROM has used the following pins for boot source 
selection
+ * - GPIO BANK1/5: ETM enable
+ * - GPIO BANK1/3: BM3
+ * - GPIO BANK1/2: BM2
+ * - GPIO BANK1/1: BM1
+ * - GPIO BANK1/0: BM0
+ */
+static uint32_t mxs23_boot_save_loc(void)
+{
+   uint32_t mux2, mux3, dir, mode;
+
+   mux3 = readl(IMX_IOMUXC_BASE + HW_PINCTRL_MUXSEL3);
+   mux2 = readl(IMX_IOMUXC_BASE + HW_PINCTRL_MUXSEL2);
+   dir = readl(IMX_IOMUXC_BASE + HW_PINCTRL_DOE1);
+
+   /* force the GPIO lines of interest to input */
+   writel(0x0008002f, IMX_IOMUXC_BASE + HW_PINCTRL_DOE1 + 8);
+   /* force the GPIO lines of interest to act as GPIO */
+   writel(0x0cff, IMX_IOMUXC_BASE + HW_PINCTRL_MUXSEL2 + 4);
+   writel(0x00c0, IMX_IOMUXC_BASE + HW_PINCTRL_MUXSEL3 + 4);
+
+   /* read the bootstrapping */
+   mode = readl(IMX_IOMUXC_BASE + HW_PINCTRL_DIN1)  0x8002f;
+
+   /* restore previous settings */
+   writel(mux3, IMX_IOMUXC_BASE + HW_PINCTRL_MUXSEL3);
+   writel(mux2, IMX_IOMUXC_BASE + HW_PINCTRL_MUXSEL2);
+   writel(dir, IMX_IOMUXC_BASE + HW_PINCTRL_DOE1);
+
+   if (!(mode  (1  19)))
+   return 0xff; /* invalid marker */
+
+   return (mode  0xf) | ((mode  0x20)  1);
+}
+
 #define MX28_REV_1_0_MODE  (0x0001a7f0)
 #define MX28_REV_1_2_MODE  (0x00019bf0)
 
@@ -122,7 +166,7 @@ static void mxs_boot_save_loc(void)
uint32_t mode = 0xff;
 
if (cpu_is_mx23()) {
-   /* not implemented yet */
+   mode = mxs23_boot_save_loc();
} else if (cpu_is_mx28()) {
enum silicon_revision rev = silicon_revision_get();
 
Regards,
Juergen

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[PATCH] MCI/MXS: fix signed/unsigned mismatch

[Juergen Beisert]

Using the MXS MCI driver with an eight bit capable eMMC results into the
'devinfo' message the interface uses '0' bits for data transfer:

 barebox:/ devinfo mxs_mci0
 resources:
 num   : 0
 start : 0x80034000
 size  : 0x2000
 driver: mxs_mci
 bus: platform

  Interface
   Min. bus clock: 1476 Hz
   Max. bus clock: 4800 Hz
   Current bus clock: 2400 Hz
   Bus width: 0 bit

The eight bit interface width is stored internally as value '2'. And a two bit
'2' ends up into 0xfffe when used as an array index. Using an unsigned
field instead fixes this issue:

 barebox:/ devinfo mxs_mci0
 resources:
 num   : 0
 start : 0x80034000
 size  : 0x2000
 driver: mxs_mci
 bus: platform

  Interface
   Min. bus clock: 1476 Hz
   Max. bus clock: 4800 Hz
   Current bus clock: 2400 Hz
   Bus width: 8 bit

Signed-off-by: Juergen Beisert j...@pengutronix.de

diff --git a/drivers/mci/mxs.c b/drivers/mci/mxs.c
index c15461c..9dee863 100644
--- a/drivers/mci/mxs.c
+++ b/drivers/mci/mxs.c
@@ -55,7 +55,7 @@ struct mxs_mci_host {
unsignedf_min;
unsignedf_max;
 #endif
-   int bus_width:2; /* 0 = 1 bit, 1 = 4 bit, 2 = 8 bit */
+   unsignedbus_width:2; /* 0 = 1 bit, 1 = 4 bit, 2 = 8 bit */
 };
 
 #define to_mxs_mci(mxs) container_of(mxs, struct mxs_mci_host, host)

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[PATCH 3/6] MCI/Core: increase the transmission frequency while card detection

[Juergen Beisert]

According to the SD card spec the detection can happen at 400 kHz

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 drivers/mci/mci-core.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mci/mci-core.c b/drivers/mci/mci-core.c
index a269aee..9aeaa4d 100644
--- a/drivers/mci/mci-core.c
+++ b/drivers/mci/mci-core.c
@@ -1371,7 +1371,8 @@ static int mci_card_probe(struct mci *mci)
}
 
mci_set_bus_width(mci, MMC_BUS_WIDTH_1);
-   mci_set_clock(mci, 1);  /* set the lowest available clock */
+   /* according to the SD card spec the detection can happen at 400 kHz */
+   mci_set_clock(mci, 40);
 
/* reset the card */
rc = mci_go_idle(mci);
-- 
1.8.2.rc2


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[PATCH 5/6] MCI/MXS: report a better matching error code when the transfer fails

[Juergen Beisert]

EIO is a better error message to describe the data transfer to or from the SD 
cards has failed.

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 drivers/mci/mxs.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mci/mxs.c b/drivers/mci/mxs.c
index 3045e6a..c15461c 100644
--- a/drivers/mci/mxs.c
+++ b/drivers/mci/mxs.c
@@ -186,7 +186,7 @@ static int mxs_mci_read_data(struct mxs_mci_host *mxs_mci, 
void *buffer, unsigne
if (length == 0)
return 0;
 
-   return -EINVAL;
+   return -EIO;
 }
 
 
@@ -223,7 +223,7 @@ static int mxs_mci_write_data(struct mxs_mci_host *mxs_mci, 
const void *buffer,
if (length == 0)
return 0;
 
-   return -EINVAL;
+   return -EIO;
 }
 
 /**
-- 
1.8.2.rc2


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[PATCH 1/6] MXS/MCI: add forgotten header file

[Juergen Beisert]

Commit b36f68d74b5379c216429a0f15aeedbd7917e10d now uses the generic
mxs_reset_block() routine, but this requires the mxs.h header file for the
prototype.

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 drivers/mci/mxs.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mci/mxs.c b/drivers/mci/mxs.c
index 93f5a41..e2ffa43 100644
--- a/drivers/mci/mxs.c
+++ b/drivers/mci/mxs.c
@@ -37,6 +37,7 @@
 #include clock.h
 #include io.h
 #include asm/bitops.h
+#include mach/mxs.h
 #include mach/imx-regs.h
 #include mach/mci.h
 #include mach/clock.h
-- 
1.8.2.rc2


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[PATCH 4/6] MCI/Core: honor transmission limits at the card's side

[Juergen Beisert]

The host limits are only one limit we must honor when changing the transmission 
frequency.
The SD cards have their own limits, so take them also into account.

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 drivers/mci/mci-core.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/mci/mci-core.c b/drivers/mci/mci-core.c
index 9aeaa4d..42e3d4b 100644
--- a/drivers/mci/mci-core.c
+++ b/drivers/mci/mci-core.c
@@ -605,13 +605,17 @@ static void mci_set_clock(struct mci *mci, unsigned clock)
 {
struct mci_host *host = mci-host;
 
-   /* check against any given limits */
+   /* check against any given limits at the host's side */
if (clock  host-f_max)
clock = host-f_max;
 
if (clock  host-f_min)
clock = host-f_min;
 
+   /* check against the limit at the card's side */
+   if (mci-tran_speed != 0  clock  mci-tran_speed)
+   clock = mci-tran_speed;
+
host-clock = clock;/* the new target frequency */
mci_set_ios(mci);
 }
-- 
1.8.2.rc2


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[PATCH 2/6] MXS/MCI: don't touch variables in the host structure

[Juergen Beisert]

MMC_BUS_WIDTH_* macros do not correspond with the real bus width.
After setting a bus width larger than 1 bit the next call to change the
frequency ends in the default handler and the host interface stays silently
at the previous frequency.

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 drivers/mci/mxs.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/mci/mxs.c b/drivers/mci/mxs.c
index e2ffa43..3045e6a 100644
--- a/drivers/mci/mxs.c
+++ b/drivers/mci/mxs.c
@@ -515,23 +515,23 @@ static void mxs_mci_set_ios(struct mci_host *host, struct 
mci_ios *ios)
switch (ios-bus_width) {
case MMC_BUS_WIDTH_8:
mxs_mci-bus_width = 2;
-   host-bus_width = 8;/* 8 bit is possible */
+   pr_debug(IO settings: changing bus width to 8 bits\n);
break;
case MMC_BUS_WIDTH_4:
mxs_mci-bus_width = 1;
-   host-bus_width = 4;/* 4 bit is possible */
+   pr_debug(IO settings: changing bus width to 4 bits\n);
break;
case MMC_BUS_WIDTH_1:
mxs_mci-bus_width = 0;
-   host-bus_width = 1;/* 1 bit is possible */
+   pr_debug(IO settings: changing bus width to 1 bit\n);
break;
default:
+   pr_debug(IO settings: unsupported bus width!\n);
return;
}
 
mxs_mci-clock = mxs_mci_setup_clock_speed(mxs_mci, ios-clock);
-   pr_debug(IO settings: bus width=%d, frequency=%u Hz\n, 
host-bus_width,
-   mxs_mci-clock);
+   pr_debug(IO settings: frequency=%u Hz\n, mxs_mci-clock);
 }
 
 /* --- */
-- 
1.8.2.rc2


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[PATCH 6/6] MCI/Core: move an ugly ifdef to the header file

[Juergen Beisert]

To avoid the compiler complains about an unused variable when no SPI host is
enabled, use an inline function instead of a macro.

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 drivers/mci/mci-core.c |  3 +--
 include/mci.h  | 15 +--
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/mci/mci-core.c b/drivers/mci/mci-core.c
index 42e3d4b..ba7ef55 100644
--- a/drivers/mci/mci-core.c
+++ b/drivers/mci/mci-core.c
@@ -482,9 +482,8 @@ static int sd_change_freq(struct mci *mci)
 {
struct mci_cmd cmd;
struct mci_data data;
-#ifdef CONFIG_MCI_SPI
struct mci_host *host = mci-host;
-#endif
+
uint32_t *switch_status = sector_buf;
uint32_t *scr = sector_buf;
int timeout;
diff --git a/include/mci.h b/include/mci.h
index cf9582d..7f514be 100644
--- a/include/mci.h
+++ b/include/mci.h
@@ -54,12 +54,6 @@
 
 #define IS_SD(x) (x-version  SD_VERSION_SD)
 
-#ifdef CONFIG_MCI_SPI
-#define mmc_host_is_spi(host)  ((host)-host_caps  MMC_CAP_SPI)
-#else
-#define mmc_host_is_spi(host)  0
-#endif
-
 #define MMC_DATA_READ  1
 #define MMC_DATA_WRITE 2
 
@@ -330,6 +324,15 @@ struct mci {
char *ext_csd;
 };
 
+static inline bool mmc_host_is_spi(const struct mci_host *host)
+{
+#ifdef CONFIG_MCI_SPI
+   return !!host-host_caps  MMC_CAP_SPI;
+#else
+   return false;
+#endif
+}
+
 int mci_register(struct mci_host*);
 
 #endif /* _MCI_H_ */
-- 
1.8.2.rc2


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Make Chumby work again with its SD card

[Juergen Beisert]

Due to a missing resource size the Chumby isn't able to work with its SD card
anymore. Instead it hangs forever. By using the generic block reset routine I
was able to discover the cause. The following two patches makes the Chumby
work again. At least the resource size patch should be applied to the current
master.

jbe


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[PATCH 2/2] MXS/MCI: simplify reset of the MCI device block

[Juergen Beisert]

Since a generic block reset function is a available, also the MCI driver
should make use of it.

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 drivers/mci/mxs.c | 15 +--
 1 file changed, 1 insertion(+), 14 deletions(-)

diff --git a/drivers/mci/mxs.c b/drivers/mci/mxs.c
index 3657b3e..93f5a41 100644
--- a/drivers/mci/mxs.c
+++ b/drivers/mci/mxs.c
@@ -446,19 +446,6 @@ static unsigned mxs_mci_setup_clock_speed(struct 
mxs_mci_host *mxs_mci, unsigned
return ssp / div / rate;
 }
 
-/**
- * Reset the MCI engine (the hard way)
- * @param hw_dev Host interface instance
- *
- * This will reset everything in all registers of this unit! (FIXME)
- */
-static void mxs_mci_reset(struct mxs_mci_host *mxs_mci)
-{
-   writel(SSP_CTRL0_SFTRST, mxs_mci-regs + HW_SSP_CTRL0 + 8);
-   while (readl(mxs_mci-regs + HW_SSP_CTRL0)  SSP_CTRL0_SFTRST)
-   ;
-}
-
 /* - MCI API -- */
 
 /**
@@ -475,7 +462,7 @@ static int mxs_mci_initialize(struct mci_host *host, struct 
device_d *mci_dev)
writel(SSP_CTRL0_CLKGATE, mxs_mci-regs + HW_SSP_CTRL0 + 8);
 
/* reset the unit */
-   mxs_mci_reset(mxs_mci);
+   mxs_reset_block(mxs_mci-regs + HW_SSP_CTRL0, 0);
 
/* restore the last settings */
mxs_mci_setup_timeout(mxs_mci, 0x);
-- 
1.8.2.rc2


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[PATCH 1/2] MXS/Chumby: fix MCI device registration

[Juergen Beisert]

Due to some changes in the framework a resource size of zero does not map
anything at all and it does it silently.

Defining the resource size for the MCI interface make it work again on the
Chumby.

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 arch/arm/boards/chumby_falconwing/falconwing.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boards/chumby_falconwing/falconwing.c 
b/arch/arm/boards/chumby_falconwing/falconwing.c
index fd5bc4c..720fe32 100644
--- a/arch/arm/boards/chumby_falconwing/falconwing.c
+++ b/arch/arm/boards/chumby_falconwing/falconwing.c
@@ -293,7 +293,7 @@ static int falconwing_devices_init(void)
imx_set_ioclk(48000); /* enable IOCLK to run at the PLL frequency */
/* run the SSP unit clock at 100,000 kHz */
imx_set_sspclk(0, 1, 1);
-   add_generic_device(mxs_mci, 0, NULL, IMX_SSP1_BASE, 0,
+   add_generic_device(mxs_mci, 0, NULL, IMX_SSP1_BASE, 0x2000,
   IORESOURCE_MEM, mci_pdata);
add_generic_device(stmfb, 0, NULL, IMX_FB_BASE, 4096,
   IORESOURCE_MEM, fb_mode);
-- 
1.8.2.rc2


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Re: can barebox running on mini6410 boot from nand?

[Juergen Beisert]

Hi Yi,

Yi Qingliang wrote:
 can barebox running on mini6410 boot from nand?

Barebox support for Mini6410/Tiny6410 is currently in a very basic state. 
Additional developers are welcome. ;)

Regards
Juergen

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Re: [PATCH 2/4] ARM: head: Add some space behind the image header

[Juergen Beisert]

Sascha Hauer wrote:
 [...]
 +/*
 + * 32 bytes at this is offset is reserved in the barebox head for board/SoC 
 + * usage
 + */
 [...]

Hmm, one 'is' too much in this sentence?

jbe

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Re: [PATCH 3/4] ARM: i.MX: Add bbu handler for external NAND boot

[Juergen Beisert]

Sascha Hauer wrote:
 [...]
 +   if (size_available  0) {
 +   printf(device is too small\n);
 +   ret = -ENOSPC;
 +   goto out;
 +   }
 [...]

As the user only sees bad block info when DEBUG is enabled, you should output 
more info here.
The device (or better partition?) can be too small in general, or it can be 
too small due to many bad blocks inside. IMHO it would be helpful to see more 
info here why it failed.

jbe

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Re: [PATCH 3/4] ARM: i.MX: Add bbu handler for external NAND boot

[Juergen Beisert]

Sascha Hauer wrote:
 On Tue, Mar 12, 2013 at 10:48:16AM +0100, Juergen Beisert wrote:
  Sascha Hauer wrote:
   [...]
   +   if (size_available  0) {
   +   printf(device is too small\n);
   +   ret = -ENOSPC;
   +   goto out;
   +   }
   [...]
 
  As the user only sees bad block info when DEBUG is enabled, you should
  output more info here.
  The device (or better partition?) can be too small in general, or it can
  be too small due to many bad blocks inside. IMHO it would be helpful to
  see more info here why it failed.

 Ok. I reworded this to:

   printf(device is too small.\n
   raw partition size: 0x%08llx\n
   partition size w/o bad blocks: 0x%08llx\n
   size needed: 0x%08x\n,
   s.st_size,
   s.st_size - num_bb * blocksize,
   data-len);

ACK.

jbe

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Re: [PATCH] image and bss size decrease

[Juergen Beisert]

Hi Sascha,

Sascha Hauer wrote:
 [...]
 Also we make the bss smaller by allocating the FILE table and
 the gpio_desc table dynamically. The bss size is may become
 a problem on boards which run from SRAM. Here the malloc pool
 is in the big SDRAM area, but the bss is in SRAM, so it makes
 sense to move the big tables from bss to SDRAM by using malloc.

It would also be possible to instruct the linker to locate the BSS in the big 
SDRAM area. But that might interfere with very running early code using 
variables in BSS while the SDRAM isn't up and running yet.

jbe

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Re: [PATCH 1/2] memsize: Make get_ram_size RAM proof

[Juergen Beisert]

Hi Maxime,

Maxime Ripard wrote:
  []
 
  Unfortunately I had to drop this one. It breaks compilation on some
  architectures which do not have _text and __bss_stop (namely blackfin
  and another one I forgot about).
 
  Anyway, I realized that we now can start the MMU during early startup,
  so when you call this function from your board code your SDRAM might
  already be cached. I assume get_ram_size won't work reliably in this
  case anymore.
 
  Since you only use it to detect whether you have 128MiB or 256Mib, could
  you code a stripped down version of this function especially for your
  board? Could you even adjust the SDRAM controller registers to the size
  you really have? I have no idea if the SDRAM controller can cope with
  that, but it might be worth giving it a try. I have a patch in the
  queue moving the i.MX28 over to dynamically detecting the SDRAM size
  via controller readback, so this then would simply detect the correct
  size.

 I agree that this patch you're mentionning would be the best solution.

 However, the imx28 SDRAM controller doesn't seem to be able to be
 reconfigured, so once it has been configured once, you're screwed.

You have to do this test in the bootlets instead. As they run from the 
internal SRAM, you can do whatever you want with the SDRAM controller.

jbe

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Re: [PATCH 09/10] mtd: nand: Add bbt parameter

[Juergen Beisert]

Sascha Hauer wrote:
 [...]
 --- a/drivers/mtd/nand/nand_base.c
 +++ b/drivers/mtd/nand/nand_base.c
 @@ -1688,6 +1688,23 @@ static int mtd_set_erasebad(struct device_d *dev,
 struct param_d *param, return 0;
  }

 +static const char *mtd_get_bbt_type(struct device_d *dev, struct param_d 
*p) +{
 + struct mtd_info *mtd = container_of(dev, struct mtd_info, class_dev);
 + struct nand_chip *chip = mtd-priv;
 + char *str;

Should also be const char *str

 +
 + if (!chip-bbt)
 + str = none;
 + else if ((chip-bbt_td  chip-bbt_td-pages[0] != -1) ||
 + (chip-bbt_md  chip-bbt_md-pages[0] != -1))
 + str = flashbased;
 + else
 + str = memorybased;
 +
 + return str;
 +}
 +

jbe

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Re: [PATCH 10/10] mtd: nand: Add command to generate a flash BBT

[Juergen Beisert]

Sascha Hauer wrote:
 [...]
 +static int do_imx_nand_bbm(int argc, char *argv[])
 +{
 + int opt, ret;
 + struct cdev *cdev;
 + struct mtd_info *mtd;
 + int yes = 0;
 + void *bbt;
 +
 + while ((opt = getopt(argc, argv, y))  0) {
 + switch (opt) {
 + case 'y':
 + yes = 1;
 + break;
 + default:
 + return COMMAND_ERROR_USAGE;
 + }
 + }
 +
 + cdev = cdev_open(nand0, O_RDWR);

Is a fixed name a good idea?

 [...]

jbe

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Re: [PATCH 1/2] cfa-10036: Use the second MMC partition to store the environment

[Juergen Beisert]

Maxime Ripard wrote:
 Since the only storage medium on the cfa-10036 is the MMC card, we need
 to have a registered environment partition on it if we want to be able
 to modify at runtime.

 Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
 ---
  arch/arm/boards/crystalfontz-cfa10036/cfa10036.c |   44
 +- 1 file changed, 43 insertions(+), 1 deletion(-)

 diff --git a/arch/arm/boards/crystalfontz-cfa10036/cfa10036.c 
 b/arch/arm/boards/crystalfontz-cfa10036/cfa10036.c
 index b59dbab..1821b10 100644 
 --- a/arch/arm/boards/crystalfontz-cfa10036/cfa10036.c
 +++ b/arch/arm/boards/crystalfontz-cfa10036/cfa10036.c
 @@ -97,9 +97,46 @@ static int cfa10036_mem_init(void)
  }
  mem_initcall(cfa10036_mem_init);

 +/**
 + * Try to register an environment storage on the attached MCI card
 + * @return 0 on success
 + *
 + * We rely on the existence of a usable SD card, already attached to
 + * our system, to get something like a persistent memory for our environment.
 + * If this SD card is also the boot media, we can use the second partition
 + * for our environment purpose (if present!). 
 + */
 +static int register_persistant_environment(void)

register_persist*e*nt_environment

Seems a copy from my typo in the falconwing. I really should fix it :))

 [...]

jbe

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[PATCH] arm/i.M23/chumbyfalconwing: just fix a typo

[Juergen Beisert]

diff --git a/arch/arm/boards/chumby_falconwing/falconwing.c 
b/arch/arm/boards/chumby_falconwing/falconwing.c
index 0818666..a8fe00c 100644
--- a/arch/arm/boards/chumby_falconwing/falconwing.c
+++ b/arch/arm/boards/chumby_falconwing/falconwing.c
@@ -274,7 +274,7 @@ mem_initcall(falconwing_mem_init);
  * If this SD card is also the boot media, we can use the second partition
  * for our environment purpose (if present!).
  */
-static int register_persistant_environment(void)
+static int register_persistent_environment(void)
 {
struct cdev *cdev;
 
@@ -338,7 +338,7 @@ static int falconwing_devices_init(void)
armlinux_set_bootparams((void *)IMX_MEMORY_BASE + 0x100);
armlinux_set_architecture(MACH_TYPE_CHUMBY);
 
-   rc = register_persistant_environment();
+   rc = register_persistent_environment();
if (rc != 0)
printf(Cannot create the 'env0' persistant environment storage 
(%d)\n, rc);
 

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[PATCH v2] arm/i.M23/chumbyfalconwing: just fix a typo

[Juergen Beisert]

Juergen Beisert wrote:
 [...]
   if (rc != 0)
   printf(Cannot create the 'env0' persistant environment storage 
 (%d)\n, rc);
 ___^
Arrghh, still two 'a' left. :(

diff --git a/arch/arm/boards/chumby_falconwing/falconwing.c 
b/arch/arm/boards/chumby_falconwing/falconwing.c
index 0818666..a9e1c00 100644
--- a/arch/arm/boards/chumby_falconwing/falconwing.c
+++ b/arch/arm/boards/chumby_falconwing/falconwing.c
@@ -274,7 +274,7 @@ mem_initcall(falconwing_mem_init);
  * If this SD card is also the boot media, we can use the second partition
  * for our environment purpose (if present!).
  */
-static int register_persistant_environment(void)
+static int register_persistent_environment(void)
 {
struct cdev *cdev;
 
@@ -338,9 +338,9 @@ static int falconwing_devices_init(void)
armlinux_set_bootparams((void *)IMX_MEMORY_BASE + 0x100);
armlinux_set_architecture(MACH_TYPE_CHUMBY);
 
-   rc = register_persistant_environment();
+   rc = register_persistent_environment();
if (rc != 0)
-   printf(Cannot create the 'env0' persistant environment storage 
(%d)\n, rc);
+   printf(Cannot create the 'env0' persistent environment storage 
(%d)\n, rc);
 
return 0;
 }
@@ -393,7 +393,7 @@ make ARCH=arm CROSS_COMPILE=armv5compiler
 
 - Create four primary partitions on the MCI card
  - the first one for the bootlets (about 256 kiB)
- - the second one for the persistant environment (size is up to you, at least 
256k)
+ - the second one for the persistent environment (size is up to you, at least 
256k)
  - the third one for the kernel (2 MiB ... 4 MiB in size)
  - the 4th one for the root filesystem which can fill the rest of the 
available space
 


jbe

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RFC, i.MX28 related

[Juergen Beisert]

Hi list,

the i.MX28 SoC has a nice feature which prevents the intended usage of its 
watchdog.

When the SoC is powered via its 5 V power supply input the watchdog triggers a 
simple system reset when it barks. But when the SoC is powered via the 
battery supply input only, the watchdog powers off the whole chip instead, 
because it resets the PMIC.

But we are in luck: a register bit exists to select a system reset or power 
off for the battery powered case when the watchdog barks. It only defaults to 
the power off setting after reset.

Should we re-program this bit to the system reset setting for all i.MX28 based 
system (e.g. in the i.MX28 generic part of Barebox) or better on a board by 
board base?

jbe

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Re: imx23evk NAND support

[Juergen Beisert]

Hi Paul,

Paul B. Henson wrote:
 On 1/12/2013 7:24 PM, Paul B. Henson wrote:
  My understanding is that the SD card and the NAND chip cannot be used at
  the same time due to a pin conflict.

 Hmm, it seems what I read on this wasn't entirely correct. I ended up
 booting the BSP linux kernel and root file system off of SD, and it was
 able to access the NAND device while simultaneously using the SD device
 (as the root filesystem source) so there doesn't seem to be any inherent
 hardware limitation preventing bareboot from accessing it.

 Just for fun, I tried to use the kobs-ng freescale tool from within the
 linux environment to burn the bareboot bootstream to NAND. However,
 after trying to boot, I receive the error code 0x80501003 from the ROM
 loader, which evidently indicates The file signature or file version is
 incorrect. The exact same bootstream on an SD card boots fine, so I
 don't think there's anything wrong with it. I also tried to burn the BSP
 linux kernel bootstream, with the same result. (Side question, what's
 the difference in the bootstream files that contain ivt in the
 filename? I used the non-ivt versions on SD, I tried both on NAND with
 neither working).

IIRC ivt/non-ivt is relevant for the i.MX28 firmware, not for i.MX23. On the 
other hand, for some i.MX23 based systems the encryption must be enabled for 
the bootstream, but with an empty key.

Hope it helps.
Juergen

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Re: s3c2440's register: MRSR6

[Juergen Beisert]

Hi Yi,

niqingliang2...@gmail.com wrote:
 Hello, I compiled barebox (based on mini2440).
 and start from nand, can't start normally,
 after changed MRSRB6 to 0x30, ok.

 I have checked uboot, it does use 0x30 for mini2440.
 but barebox use 0x20 (work on mini2440, but not work on my 2442
 board).

 what does it depend on?
 in other words, what does the CL value depend on?

You should read the manual of the used SDRAM. As SDRAM is a synchronous 
memory, the SDRAM device and the SDRAM controller must be programmed in the 
same way (same CL value).

The CL value in MRSRB6 must correspond with the Trcd in the BANKCON* register.

Note: the impact of higher CL values is huge. Data throughput with 100 MHz @ 
CL2 is higher than at 133 MHz @ CL3.

Regards,
Juergen

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Re: about s3c2442

[Juergen Beisert]

Hi Yi,

Yi Qingliang wrote:
 On Thursday, January 10, 2013 09:36:36 AM Juergen Beisert wrote:
  Yi Qingliang wrote:
 I'm using barebox (based on mini2440) on my s3c2442 board,
  
   1. flash barebox into nand: can't start normally, but can see early
   output on serial.
   2. load it in sdram: can start normally into shell, and then I use it
   to boot kernel (also in sdram, also based on mini2440).
   the kernel hang, no output.
  
   after dig into it, I found something: add mem=64M into the kernel
   paramer, then the kernel can start.
  
   BUT:
   the barebox doesn't pass that paramert to kernel for mini2440,
   why the mini2440 kernel can start normally?
  
   how does the kernel on 2440 get the sdram size?
 
  There is no autodetection possible. Take a look into
  the arch/arm/boards/friendlyarm-mini2440/lowlevel_init.S: This is the
  code which runs immediately after reset. It calls the
  function s3c24x0_sdram_init from the generic part, and uses hard coded
  values from arch/arm/boards/friendlyarm-mini2440/config.h to setup the
  SDRAM controller according to the attached SDRAM type.
  When the SDRAM is up and running, it is very easy to read back the SDRAM
  size from the SDRAM controller's registers (which is done in the
  function s3c24xx_get_memory_size).
 
  So you need routines which do the same job for your S3C2442 CPU.

 and the kernel? how does the kernel know the sdram size for mini2440?
 read the cpu register set by barebox?

No. The bootloader forwards this information to the kernel as an ATAG or via 
device tree. But this can only work, if also the bootloader knows the correct 
SDRAM size!

Regards,
Juergen

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Re: about s3c2442

[Juergen Beisert]

Hi Yi,

Yi Qingliang wrote:
 On Thursday, January 10, 2013 10:14:07 AM Juergen Beisert wrote:
  Yi Qingliang wrote:
   On Thursday, January 10, 2013 09:36:36 AM Juergen Beisert wrote:
Yi Qingliang wrote:
   I'm using barebox (based on mini2440) on my s3c2442 board,

 1. flash barebox into nand: can't start normally, but can see early
 output on serial.
 2. load it in sdram: can start normally into shell, and then I use
 it to boot kernel (also in sdram, also based on mini2440).
 the kernel hang, no output.

 after dig into it, I found something: add mem=64M into the kernel
 paramer, then the kernel can start.

 BUT:
 the barebox doesn't pass that paramert to kernel for mini2440,
 why the mini2440 kernel can start normally?

 how does the kernel on 2440 get the sdram size?
   
There is no autodetection possible. Take a look into
the arch/arm/boards/friendlyarm-mini2440/lowlevel_init.S: This is
the

 I found it,
 but:
 md 0x4828
 4828: 00b2 (represents is 128)
 it looks like the lowlevel_init is not executed, what's the problem.

Is the symbol CONFIG_MACH_DO_LOWLEVEL_INIT enabled in your config?

Regards,
Juergen

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Re: about s3c2442

[Juergen Beisert]

Hi Yi,

Yi Qingliang wrote:
 On Thursday, January 10, 2013 11:00:53 AM Juergen Beisert wrote:
  Yi Qingliang wrote:
   On Thursday, January 10, 2013 10:14:07 AM Juergen Beisert wrote:
Yi Qingliang wrote:
 On Thursday, January 10, 2013 09:36:36 AM Juergen Beisert wrote:
  Yi Qingliang wrote:
 I'm using barebox (based on mini2440) on my s3c2442 board,
  
   1. flash barebox into nand: can't start normally, but can see
   early
   output on serial.
   2. load it in sdram: can start normally into shell, and then I
   use it to boot kernel (also in sdram, also based on mini2440).
   the kernel hang, no output.
  
   after dig into it, I found something: add mem=64M into the
   kernel
   paramer, then the kernel can start.
  
   BUT:
   the barebox doesn't pass that paramert to kernel for mini2440,
   why the mini2440 kernel can start normally?
  
   how does the kernel on 2440 get the sdram size?
 
  There is no autodetection possible. Take a look into
  the arch/arm/boards/friendlyarm-mini2440/lowlevel_init.S: This
  is the
  
   I found it,
   but:
   md 0x4828
   4828: 00b2 (represents is 128)
   it looks like the lowlevel_init is not executed, what's the problem.
 
  Is the symbol CONFIG_MACH_DO_LOWLEVEL_INIT enabled in your config?

 enabled already, but when loaded in sdram, the barebox skipped the sdram
 init code. am i right?

Yes, you are right. It must skip the initialization, because the code itself 
runs already from SDRAM. When you would stop the SDRAM controller in this 
case it would crash your machine.
You must ensure your routines can detect the case where they already run from 
the SDRAM area (I do not know the details how the S3C2440 and S34C2443 
differ).

Regards,
Juergen

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Re: about the dm9000 in mini2440

[Juergen Beisert]

Yi Qingliang wrote:
 and if connected jtager, the ON switch does not work some time.

Seems your jtager powers the system by accident.

Regards,
Juergen

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Re: about the dm9000 in mini2440

[Juergen Beisert]

Yi Qingliang wrote:
 On Thursday, December 06, 2012 12:27:45 PM Eric Bénard wrote:
  Le Thu, 06 Dec 2012 15:55:23 +,
 
  Yi Qingliang niqingliang2...@gmail.com a écrit :
   the address of dm9000 is 0x2800, it should be cs5, but in function
   mini2440_devices_init, it set the cs4 instead, why??
 
  The mini2440 supported in Barebox is this one and maybe not the one
  your are using ;-)
  http://www.friendlyarm.net/products/mini2440

 there is mini2440 friendlyARM on my board, whose color is white.
 blue pcb, maybe friendlyARM has multi version mini2440?

FriendlyARM has some copyist. A blue PCB I have never seen yet.

 I say the 0x2800 is cs5, based on the memory layout picture in the
 manual. although the schematics is same as Juergen Beisert's.

And the schematics says it is CS4.

 I can't get the original disk, only the board. So how to check the EED0?
 ps: In the manual of dm9000, it said that EED0 is pulled down internaly.

Sure. But if you have some power floating around your board the chip might 
detect a high level at system start. But this idea is just a shot into the 
dark.

Regards,
Juergen

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Re: about the dm9000 in mini2440

[Juergen Beisert]

Yi Qingliang wrote:
 the address of dm9000 is 0x2800, it should be cs5, but in function
 mini2440_devices_init, it set the cs4 instead, why??

Hmm, the schematics of the Mini2440 board tells me, the processor's GCS4 (ball 
D3) is in use for the DM9000.

GCS5 is connected to the CON5 instead.

Regards,
Juergen

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Re: about the dm9000 in mini2440

[Juergen Beisert]

Yi Qingliang wrote:
 indeed, I encountered follow error when boot barebox (compiled with default
 cfg):
 dm9000@dm9: Wrong databus width defined at compile time

 and can't use it for tftp

 I have printed out the context, found that is 32bit in the dm9000 register
 (read only), but in mini2440 initialize code is 16bit.

 any suggestion?

This would mean the EED0 pin of the DM9000 has a pull up connected, which is 
not the case for the Mini2440. Are you sure, you are using an original 
Mini2440?

Regards,
Juergen

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[Patch] ARM/MXS/i.MX28: distinguish POR and wake-up event correctly

[Juergen Beisert]

When the built-in RTC in the i.MX28 is programmed to wake-up the SoC, the RTC
reports two events: RST and WAKE. RST is okay in this case, because the PMIC
was really powered down. But the real event is the WAKE from the RTC and
should have precedence over the RST event. So, report the WAKE event for this
special case.

Signed-off-by: Juergen Beisert j...@pengutronix.de

diff --git a/drivers/watchdog/im28wd.c b/drivers/watchdog/im28wd.c
index ca32a72..bc19369 100644
--- a/drivers/watchdog/im28wd.c
+++ b/drivers/watchdog/im28wd.c
@@ -82,6 +82,17 @@ static void __maybe_unused imx28_detect_reset_source(const 
struct imx28_wd *p)
if (reg  MXS_RTC_PERSISTENT0_EXT_RST) {
writel(MXS_RTC_PERSISTENT0_EXT_RST,
p-regs + MXS_RTC_PERSISTENT0 + MXS_RTC_CLR_ADDR);
+   /*
+* if the RTC has woken up the SoC, additionally the ALARM_WAKE
+* bit is set. This bit should have precedence, because it
+* reports the real event, why we are here.
+*/
+   if (reg  MXS_RTC_PERSISTENT0_ALARM_WAKE) {
+   writel(MXS_RTC_PERSISTENT0_ALARM_WAKE,
+   p-regs + MXS_RTC_PERSISTENT0 + 
MXS_RTC_CLR_ADDR);
+   set_reset_source(RESET_WKE);
+   return;
+   }
set_reset_source(RESET_POR);
return;
}


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Re: [PATCH 2/3] dma: apbh: check for errors when resetting ip core

[Juergen Beisert]

Wolfram Sang wrote:
 Signed-off-by: Wolfram Sang w.s...@pengutronix.de
 ---
  drivers/dma/apbh_dma.c |4 +++-
  1 file changed, 3 insertions(+), 1 deletion(-)

 diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
 index 363878f..d30b8fb 100644
 --- a/drivers/dma/apbh_dma.c
 +++ b/drivers/dma/apbh_dma.c
 @@ -555,7 +555,9 @@ int mxs_dma_init(void)
   int ret, channel;
   u32 val, reg;

 - mxs_reset_block(apbh_regs, 0);
 + ret = mxs_reset_block(apbh_regs, 0);
 + if (ret)
 + return ret;

In this case the user faces a MXS: Timeout resetting block via register  
Do you think this message is helpful to give the user a pointer *where* the 
failure happens?

jbe

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Re: [PATCH 2/3] dma: apbh: check for errors when resetting ip core

[Juergen Beisert]

Wolfram Sang wrote:
 On Wed, Oct 31, 2012 at 09:29:56AM +0100, Juergen Beisert wrote:
  Wolfram Sang wrote:
   Signed-off-by: Wolfram Sang w.s...@pengutronix.de
   ---
drivers/dma/apbh_dma.c |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
  
   diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
   index 363878f..d30b8fb 100644
   --- a/drivers/dma/apbh_dma.c
   +++ b/drivers/dma/apbh_dma.c
   @@ -555,7 +555,9 @@ int mxs_dma_init(void)
 int ret, channel;
 u32 val, reg;
  
   - mxs_reset_block(apbh_regs, 0);
   + ret = mxs_reset_block(apbh_regs, 0);
   + if (ret)
   + return ret;
 
  In this case the user faces a MXS: Timeout resetting block via register
   Do you think this message is helpful to give the user a pointer
  *where* the failure happens?

 Yes, since it points to the IP core which was used here. Which again,
 makes clear which driver was trying to reset the IP core.

You mean the reported register offset points to the corresponding IP core?

Just my 2cents: a generic routine should report a failure to the caller. And 
the caller should output a valuable failure message which makes clear what 
the caller had tried to do by calling the generic routine. I think such a 
message would be more helpful. Your generic message is for developers only. 
But also Barebox has more users than developers.

jbe

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Re: [PATCH 2/3] dma: apbh: check for errors when resetting ip core

[Juergen Beisert]

Wolfram Sang wrote:
 On Wed, Oct 31, 2012 at 09:48:31AM +0100, Juergen Beisert wrote:
  Wolfram Sang wrote:
   On Wed, Oct 31, 2012 at 09:29:56AM +0100, Juergen Beisert wrote:
Wolfram Sang wrote:
 Signed-off-by: Wolfram Sang w.s...@pengutronix.de
 ---
  drivers/dma/apbh_dma.c |4 +++-
  1 file changed, 3 insertions(+), 1 deletion(-)

 diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
 index 363878f..d30b8fb 100644
 --- a/drivers/dma/apbh_dma.c
 +++ b/drivers/dma/apbh_dma.c
 @@ -555,7 +555,9 @@ int mxs_dma_init(void)
   int ret, channel;
   u32 val, reg;

 - mxs_reset_block(apbh_regs, 0);
 + ret = mxs_reset_block(apbh_regs, 0);
 + if (ret)
 + return ret;
   
In this case the user faces a MXS: Timeout resetting block via
register  Do you think this message is helpful to give the user
a pointer *where* the failure happens?
  
   Yes, since it points to the IP core which was used here. Which again,
   makes clear which driver was trying to reset the IP core.
 
  You mean the reported register offset points to the corresponding IP
  core?

 Yes, sure. Otherwise the error message would be useless :)

  But also Barebox has more users than developers.

 There is nothing a user could do in this case except asking a developer
 what could have happened? And that's the best option here.

MXS: Timeout resetting block via register friesel. Please ask the developer 
for a solution

:))

jbe

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Re: [PATCH 1/2] Add bcm2835/Raspberry-Pi support

[Juergen Beisert]

Jean-Christophe PLAGNIOL-VILLARD wrote:
 [...]
  diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
  index a54ad03..f8eb1b4 100644
  --- a/arch/arm/Kconfig
  +++ b/arch/arm/Kconfig
  @@ -92,6 +92,11 @@ config ARCH_TEGRA
  select CPU_ARM926T
  select HAS_DEBUG_LL
 
  +config ARCH_BCM2835
  +   bool Broadcom BCM2835 boards
  +   select GENERIC_GPIO
  +   select CPU_ARM1176

 please keep in alphabetic order

What a useless rule...

Just my 2ct.

jbe

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Re: [PATCH 1/2] Add bcm2835/Raspberry-Pi support

[Juergen Beisert]

Jean-Christophe PLAGNIOL-VILLARD wrote:
 On 09:42 Wed 19 Sep , Juergen Beisert wrote:
  Jean-Christophe PLAGNIOL-VILLARD wrote:
   [...]
  
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a54ad03..f8eb1b4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -92,6 +92,11 @@ config ARCH_TEGRA
select CPU_ARM926T
select HAS_DEBUG_LL
   
+config ARCH_BCM2835
+   bool Broadcom BCM2835 boards
+   select GENERIC_GPIO
+   select CPU_ARM1176
  
   please keep in alphabetic order
 
  What a useless rule...

 no when you search for something you expect b to be after a not after z

In Kconfig and Makefiles? Sorry. How often do your search for something in 
these kind of files?

And how often do you search for something in the C-sources?

So, what is important and what is useless?

Some people unfortunately like jumping up and down about spaces but not code.
[...]  I'd rather read good poetry written in very bad hand writing than bad
poetry written in beautiful handwriting, and I think the same is true of code.
           -- Alan Cox 20090701130018.115ce...@lxorguk.ukuu.org.uk

Still just my 2ct.

jbe

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[RFC] Dedicated command to make a target bootable with Barebox

[Juergen Beisert]

Hi all,

currently I'm working on the difficult process to make an i.MX35 SoC boot from 
an externally connected NAND device.

Nothing special with it, only the NAND flash controller in the i.MX35 (also in 
i.MX25, i.MX27 and i.MX31) is braindamaged broken. This controller loses the 
factory bad block markers when used without a workaround and losing these 
markers is a _really_ bad idea.

But to use the workaround on these SoCs it needs a complicated preparation of 
the NAND. Doing it manually is very error prone. And this kind of preparation 
has to be kept when the system should be updated and so on. Not easy to 
explain and so much more chances for the user to brick the system while the 
update process.

This makes me think about a dedicated command which is responsible to make the 
target bootable and does all the (more or less complicated) steps to ensure 
the next time it gets powered it's able to boot again.

There are more architectures which needs a complicated setup to be able to 
boot it from some kind of externally connected devices like NAND or eMMCs for 
example. Some needs special NAND checksums only for the bootloader, others 
needs to keep the partition table even if the bootloader gets updated and so 
on.

Would it be possible to share one command (or one group of commands) by all 
architectures? And each architecture adds its special code to the command? 

What kind of setup procedures we must cover with such a command?

My examples:

- for the Freescale i.MX SoCs with the broken NFC we must write the bootloader
  in a different way than all the remaining data into the NAND device
- for the Samsung S36410 we must save the factory bad block markers first to
  support booting from NAND as its internal ROM expects the checksums at a
  strange offset in the OOB area

Other constraints on different architectures that comes into your minds?

Regards,
Juergen

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Re: SD card experts wanted

[Juergen Beisert]

Hi Johannes,

Johannes Stezenbach wrote:
 On Thu, Aug 30, 2012 at 03:08:19PM +0200, Juergen Beisert wrote:
  Johannes Stezenbach wrote:
   MMC has the following speed modes:
  
   - legacy 0-26MHz
   - high speed SDR 0-52MHz
   - high speed DDR 0-52MHz
   - HS200 SDR 0-200MHz
 
  Ahh, here come the curious 26 MHz and 52 MHz into the game. Its related
  to MMC only.
 
   while SD has:
  
   - SDR12
   - SDR25
   - SDR50
   - SDR104
   - DDR50
  
   So my guess is that MMC_MODE_HS maps to SDR25 for SD-only,
   and MMC_MODE_HS_52MHz maps to SDR50 for SD and MMC.
  
   (Apparently mmc_change_freq always sets MMC_MODE_HS, it is
   meaningless for MMC.)
  
   Thus, mci_startup_sd() should do:
 if (mci-card_caps  MMC_MODE_HS)
 mci_set_clock(mci, 2500);
 else
 mci_set_clock(mci, 1250);
 
  As far as I understand the spec, there is a max. speed field in the CSD
  which tells us the regular max. speed of this card. And the fields from
  the CSR can overwrite the CSD settings. So, a card which reports 25 MHz
  in the CSD can still enable 50 MHz (SDR50) in the CSR and the SDHC then
  can use 50 MHz for the clock. But maybe I'm wrong here.

 What I wrote is not even correct ;-/

 SD has legacy Default Mode and legacy High Speed mode,
 and Ultra High Speed modes.  SDR12, SDR25, SDR50, SDR104 and DDR50
 are all UHS modes.  And Default Mode and SDR12 support up to 12.5MB/s,
 but the bus clock is up to 25MHz (4 bit parallel).
 So the code in mci_startup_sd() is correct as is.

Now I found the Abbreviations in the spec:

UHSUltra High Speed
SDR12  One of UHS modes with single data rate. Up to 12.5MB/sec at 25MHz
SDR25  One of UHS modes with single data rate. Up to 25MB/sec at 50MHz
SDR50  One of UHS modes with single data rate. Up to 50MB/sec at 100MHz
SDR104 One of UHS modes with single data rate. Up to 104MB/sec at 208MHz

So they mean the transfer capacity in bytes per second and not the clock 
speed with their SDRnumber. Thanks for this hint.

Reading further discovers:

 * all these UHS modes are _not_ valid for SDSC type of SD cards (up to 2 GiB
   capacity)

This information should help to get the code right.

 Regarding CSD, my understanding is that TRAN_SPEED only
 applies to legacy Default Mode.  If the card supports HS mode
 or UHS modes then it must be able to use 50MHz clock.

Ack.

Regards,
Juergen

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SD card experts wanted

[Juergen Beisert]

Hi there,

any SD/MMC card experts here? I have trouble with the current SD/MMC detection 
code in Barebox.
The function sd_change_freq() in the file 'drivers/mci/mci-core.c' tries to 
detect the max. transfer frequency the attached card can handle. Nothing 
special here, but the following line in this routine fails on my system:

  if ((__be32_to_cpu(switch_status[4])  0x0f00) == 0x0100)

It checks the clock speed capabilities returned from the card. As far as I 
understand the simplified SD card spec the 0x0100 means SDR25 speed, 
which means still single transfer per clock at 25 MHz clock rate. But the 
sd_change_freq() routine sets the MMC_MODE_HS bit for this case in the card's 
capabilities variable. The remaining routines in 'drivers/mci/mci-core.c' 
then use 50 MHz for the transfer speed.

This behaviour became an issue here, as my SDHC supports 50 MHz, but the 
attached card only up to 25 MHz. After switching to 50 MHz, the card wasn't 
able to respond anymore.
For SDHCs which supports only up to 25 MHz this misinterpretation is no issue, 
as the routines still use the 25 MHz, and the SD card can still respond.

simplified SD card spec talks about the bit's meaning: seems the regular 
speed was SDR12 which means 12.5 MHz. Then SDR25 cards appear, which are also 
called high speed card. Could the MMC_MODE_HS just mean this high speed 
and using it at 50 MHz is just some kind of typo? Or do MMCs act differently 
and the code mixes SD and MMC features?

Any pointers would help.

jbe

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Re: [PATCH 4/8] ARM s3c boards: Do not hardcode image sizes

[Juergen Beisert]

Sascha Hauer wrote:
 The existing nand_boot functions all do the same, so move it to
 a common place. To be flexible enough for future boards the real
 image size is used instead of hardcoded 256k.

 Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
 Cc: Juergen Beisert j...@pengutronix.de
 ---
  arch/arm/boards/a9m2410/a9m2410.c   |7 ---
  arch/arm/boards/a9m2440/a9m2440.c   |7 ---
  arch/arm/boards/friendlyarm-mini2440/mini2440.c |7 ---
  drivers/mtd/nand/nand_s3c24xx.c |   10 ++
  4 files changed, 10 insertions(+), 21 deletions(-)

[...]

I'm fine with this change.

Regards,
Juergen

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Re: [PATCH] omap: use 512k barebox partition

[Juergen Beisert]

Hi Sascha,

Sascha Hauer wrote:
 On Fri, Jul 27, 2012 at 06:54:16PM +0200, Juergen Beisert wrote:
  Sascha Hauer wrote:
   On Fri, Jul 27, 2012 at 01:09:07PM +0200, Jan Weitzel wrote:
Use 512k NAND Partion for barebox. Problem is we don't know the size
of the barebox inside xload. Set it also to 512k
Fix enviroment for boards with size in config
  
   The barebox binary has the size encoded into it at offset 0x2c. We
   could use this to transfer the correct size.
 
  Will this be a reliable API to the outerworld? Also in future versions
  of Barebox?

 Yes, definitely.

 That said, it is not a feature you can generally rely upon, because some
 SoCs may require some special image layout conflicting with this.

This would require a movable marker inside the binary image.

 If your SoC can support this header, barebox will support it in the future
 aswell.

Okay.

 The header is in arch/arm/include/asm/barebox-arm-head.h. As you can see
 it also contains the ascii string 'barebox' which means that you can
 test for it, and if you find it, the next word will contain the address
 this binary should be copied to (only used to skip copying the binary to
 the correct place, it's not mandatory to start the image there). The
 word after it will contain the image size.

 This means, what you can do is:

 - Test if the image contains 'barebox'

This might be very dangerous, as this kind of string can be part of the binary 
more than one times, if it is used as part of an output string for example 
(Hi, barebox here).

 - if yes, use the encoded image size
 - if no, fall back to whatever suitable size (It could be a U-Boot image
   for example)

What we need for this movable marker is:
 - a string like barebox as its start indication
 - in-between some payload data we want to know
   - size of the payload
   - version marker
   - real data
 - something that indicates the end of the whole marker to verify, this entry
   is not a phantom (for example the string xoberab ;) )

jbe

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Re: [PATCH] omap: use 512k barebox partition

[Juergen Beisert]

Sascha Hauer wrote:
 On Mon, Jul 30, 2012 at 10:11:32AM +0200, Juergen Beisert wrote:
  Hi Sascha,
 
  Sascha Hauer wrote:
   On Fri, Jul 27, 2012 at 06:54:16PM +0200, Juergen Beisert wrote:
Sascha Hauer wrote:
 On Fri, Jul 27, 2012 at 01:09:07PM +0200, Jan Weitzel wrote:
  Use 512k NAND Partion for barebox. Problem is we don't know the
  size of the barebox inside xload. Set it also to 512k
  Fix enviroment for boards with size in config

 The barebox binary has the size encoded into it at offset 0x2c. We
 could use this to transfer the correct size.
   
Will this be a reliable API to the outerworld? Also in future
versions of Barebox?
  
   Yes, definitely.
  
   That said, it is not a feature you can generally rely upon, because
   some SoCs may require some special image layout conflicting with this.
 
  This would require a movable marker inside the binary image.
 
   If your SoC can support this header, barebox will support it in the
   future aswell.
 
  Okay.
 
   The header is in arch/arm/include/asm/barebox-arm-head.h. As you can
   see it also contains the ascii string 'barebox' which means that you
   can test for it, and if you find it, the next word will contain the
   address this binary should be copied to (only used to skip copying the
   binary to the correct place, it's not mandatory to start the image
   there). The word after it will contain the image size.
  
   This means, what you can do is:
  
   - Test if the image contains 'barebox'
 
  This might be very dangerous, as this kind of string can be part of the
  binary more than one times, if it is used as part of an output string for
  example (Hi, barebox here).

 Should have said: 'contains the string 'barebox' at offset 0x20'

Okay. This would mean: There might be a marker at 0x20, else nowhere in the 
image.

jbe

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Re: [PATCH 00/12 v3] Add Pre-Bootloader support

[Juergen Beisert]

Jean-Christophe PLAGNIOL-VILLARD wrote:
 [...]
 Currently on the compressed image is implemented the boot really on current
 lowlevel init support.

^ Does this sentence makes any sense?

This patch set seems an important addition, so I think it needs a little bit 
more of documentation. But wait...I know...nobody reads documentation...

jbe

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Re: [PATCH 00/12 v3] Add Pre-Bootloader support

[Juergen Beisert]

Jean-Christophe PLAGNIOL-VILLARD wrote:
 On 16:44 Mon 30 Jul , Thomas Petazzoni wrote:
  Le Mon, 30 Jul 2012 12:38:43 +0200,
 
  Juergen Beisert j...@pengutronix.de a écrit :
   Jean-Christophe PLAGNIOL-VILLARD wrote:
[...]
Currently on the compressed image is implemented the boot really on
current lowlevel init support.
  
   ^ Does this sentence makes any sense?
  
   This patch set seems an important addition, so I think it needs a
   little bit more of documentation. But wait...I know...nobody reads
   documentation...
 
  I agree. I also very interested by this feature and it sounds a great
  feature, but the patch set lacks a little of explanations on what it
  does and how it works.

 simple does like the ARM linux kernel

 I've not time to do the DoC those days

e: lame excuse
d: faule Ausrede
f: mauvaise excuse

;)

jbe

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Re: Barebox hangs after boot

[Juergen Beisert]

Hi Alexey,

Alexey Galakhov wrote:
 While debugging S5PV210 code I ran into the following problem. Barebox
 starts, the barebox command line appears on the console but does not
 react to keypresses. I found no obvious dependence on the config
 settings.

 What may be the cause of this problem and how do I debug it?

Broken timer?

Regards,
Juergen

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[PATCH 6/8] ARM/Samsung: add the S3C6410 SoC

[Juergen Beisert]

After adding the base support, the SoC can now be enabled in the build system.

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 arch/arm/Kconfig  |6 ++
 arch/arm/mach-samsung/Kconfig |9 +
 2 files changed, 15 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index af4cb59..af937d1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -79,6 +79,12 @@ config ARCH_S5PCxx
select CPU_V7
select GENERIC_GPIO
 
+config ARCH_S3C64xx
+   bool Samsung S3C64xx
+   select ARCH_SAMSUNG
+   select CPU_V6
+   select GENERIC_GPIO
+
 config ARCH_VERSATILE
bool ARM Versatile boards (ARM926EJ-S)
select CPU_ARM926T
diff --git a/arch/arm/mach-samsung/Kconfig b/arch/arm/mach-samsung/Kconfig
index c60f5ed..7e41880 100644
--- a/arch/arm/mach-samsung/Kconfig
+++ b/arch/arm/mach-samsung/Kconfig
@@ -17,6 +17,8 @@ config BOARDINFO
 config ARCH_BAREBOX_MAX_BARE_INIT_SIZE
hex
default 0x1ff0 if ARCH_S5PCxx
+# TODO
+   default 0x2000 if ARCH_S3C64xx
 
 if ARCH_S3C24xx
 
@@ -84,6 +86,13 @@ endmenu
 
 endif
 
+if ARCH_S3C64xx
+
+config CPU_S3C6410
+   bool
+
+endif
+
 if ARCH_S5PCxx
 
 config CPU_S5PC110
-- 
1.7.10.4


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[PATCH 1/8] ARM/Samsung: add S3C6410 SoC iomap

[Juergen Beisert]

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 arch/arm/mach-samsung/include/mach/s3c-iomap.h |3 ++
 arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h |   51 
 2 files changed, 54 insertions(+)
 create mode 100644 arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h

diff --git a/arch/arm/mach-samsung/include/mach/s3c-iomap.h 
b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
index d34ace4..09a6891 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-iomap.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
@@ -22,6 +22,9 @@
 #ifdef CONFIG_ARCH_S3C24xx
 # include mach/s3c24xx-iomap.h
 #endif
+#ifdef CONFIG_ARCH_S3C64xx
+# include mach/s3c64xx-iomap.h
+#endif
 #ifdef CONFIG_ARCH_S5PCxx
 # include mach/s5pcxx-iomap.h
 #endif
diff --git a/arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h 
b/arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h
new file mode 100644
index 000..9cc3a1b
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2012 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* S3C64xx device base addresses */
+#define S3C_SROM_SFR   0x7000
+#define S3C_NAND_BASE  0x7020
+#define S3C_SDI0_BASE  0x7c20
+#define S3C_SDI0_SIZE  0x100
+#define S3C_SDI1_BASE  0x7c30
+#define S3C_SDI1_SIZE  0x100
+#define S3C_SDI2_BASE  0x7c40
+#define S3C_SDI2_SIZE  0x100
+#define S3C_DRAMC  0x7e001000
+#define S3C_WATCHDOG_BASE  0x7e004000
+#define S3C_CLOCK_POWER_BASE   0x7e00f000
+#define S3C_UART_BASE  0x7f005000
+#define S3C_TIMER_BASE 0x7f006000
+#define S3C_GPIO_BASE  0x7f008000
+
+#define S3C_UART1_BASE (S3C_UART_BASE)
+#define S3C_UART1_SIZE 0x400
+#define S3C_UART2_BASE (S3C_UART_BASE + 0x400)
+#define S3C_UART2_SIZE 0x400
+#define S3C_UART3_BASE (S3C_UART_BASE + 0x800)
+#define S3C_UART3_SIZE 0x400
+#define S3C_UART4_BASE (S3C_UART_BASE + 0xc00)
+#define S3C_UART4_SIZE 0x400
+
+#define S3C_SDRAM_BASE 0x5000
+#define S3C_SDRAM_END (S3C_SDRAM_BASE + 0x1000)
+
+#define S3C_SROM_BW (S3C_SROM_SFR)
+#define S3C_SROM_BC0 (S3C_SROM_SFR + 4)
+
+#define S3C_CS0_BASE 0x1000
+#define S3C_CS1_BASE 0x1800
+#define S3C_CS2_BASE 0x2000
+#define S3C_CS3_BASE 0x2800
+#define S3C_CS4_BASE 0x3000
+#define S3C_CS5_BASE 0x3800
-- 
1.7.10.4


___
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[PATCH 5/8] ARM/Samsung: add generic S3C6410 SoC specific functions

[Juergen Beisert]

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 arch/arm/mach-samsung/Makefile |2 +-
 .../mach-samsung/include/mach/devices-s3c64xx.h|   40 
 arch/arm/mach-samsung/include/mach/s3c-generic.h   |   17 +
 arch/arm/mach-samsung/mem-s3c64xx.c|   66 
 4 files changed, 124 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-samsung/include/mach/devices-s3c64xx.h
 create mode 100644 arch/arm/mach-samsung/mem-s3c64xx.c

diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
index 70489da..4df1887 100644
--- a/arch/arm/mach-samsung/Makefile
+++ b/arch/arm/mach-samsung/Makefile
@@ -2,6 +2,6 @@ obj-y += s3c-timer.o generic.o
 obj-lowlevel-$(CONFIG_ARCH_S3C24xx) += lowlevel-s3c24x0.o
 obj-lowlevel-$(CONFIG_ARCH_S5PCxx) += lowlevel-s5pcxx.o
 obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o s3c24xx-clocks.o mem-s3c24x0.o
-obj-$(CONFIG_ARCH_S3C64xx) += gpio-s3c64xx.o clocks-s3c64xx.o
+obj-$(CONFIG_ARCH_S3C64xx) += gpio-s3c64xx.o clocks-s3c64xx.o mem-s3c64xx.o
 obj-$(CONFIG_ARCH_S5PCxx) += gpio-s5pcxx.o clocks-s5pcxx.o
 obj-$(CONFIG_S3C_LOWLEVEL_INIT) += $(obj-lowlevel-y)
diff --git a/arch/arm/mach-samsung/include/mach/devices-s3c64xx.h 
b/arch/arm/mach-samsung/include/mach/devices-s3c64xx.h
new file mode 100644
index 000..bcbee97
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/devices-s3c64xx.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2012 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef INCLUDE_MACH_DEVICES_S3C64XX_H
+# define INCLUDE_MACH_DEVICES_S3C64XX_H
+
+#include driver.h
+#include mach/s3c64xx-iomap.h
+
+static inline void s3c64xx_add_uart1(void)
+{
+   add_generic_device(s3c_serial, DEVICE_ID_DYNAMIC, NULL, 
S3C_UART1_BASE,
+   S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
+}
+
+static inline void s3c64xx_add_uart2(void)
+{
+   add_generic_device(s3c_serial, DEVICE_ID_DYNAMIC, NULL, 
S3C_UART2_BASE,
+   S3C_UART2_SIZE, IORESOURCE_MEM, NULL);
+}
+
+static inline void s3c64xx_add_uart3(void)
+{
+   add_generic_device(s3c_serial, DEVICE_ID_DYNAMIC, NULL, 
S3C_UART3_BASE,
+   S3C_UART3_SIZE, IORESOURCE_MEM, NULL);
+}
+
+#endif /* INCLUDE_MACH_DEVICES_S3C64XX_H */
diff --git a/arch/arm/mach-samsung/include/mach/s3c-generic.h 
b/arch/arm/mach-samsung/include/mach/s3c-generic.h
index 11b083d..b11e8e3 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-generic.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-generic.h
@@ -41,3 +41,20 @@ void s3c24xx_disable_second_sdram_bank(void);
 #ifdef CONFIG_ARCH_S5PCxx
 void s5p_init_pll(void);
 #endif
+
+#ifdef CONFIG_ARCH_S3C64xx
+unsigned s3c_set_epllclk(unsigned, unsigned, unsigned, unsigned);
+uint32_t s3c_get_epllclk(void);
+unsigned s3c_get_hsmmc_clk(int);
+void s3c_set_hsmmc_clk(int, int, unsigned);
+unsigned s3c6410_get_memory_size(void);
+struct s3c6410_chipselect {
+   unsigned adr_setup_t; /* in [ns] */
+   unsigned access_setup_t; /* in [ns] */
+   unsigned access_t; /* in [ns] */
+   unsigned cs_hold_t; /* in [ns] */
+   unsigned adr_hold_t; /* in [ns] */
+   unsigned char width; /* 8 or 16 */
+};
+int s3c6410_setup_chipselect(int, const struct s3c6410_chipselect*);
+#endif
diff --git a/arch/arm/mach-samsung/mem-s3c64xx.c 
b/arch/arm/mach-samsung/mem-s3c64xx.c
new file mode 100644
index 000..aca2cf5
--- /dev/null
+++ b/arch/arm/mach-samsung/mem-s3c64xx.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2012 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include common.h
+#include errno.h
+#include io.h
+#include mach/s3c-iomap.h
+#include mach/s3c-generic.h
+
+#define S3C_DRAMC_CHIP_0_CFG (S3C_DRAMC + 0x200)
+
+/* note: this routine honors the first memory bank only */
+unsigned s3c6410_get_memory_size(void)
+{
+   unsigned reg = readl(S3C_DRAMC_CHIP_0_CFG)  0xff;
+
+   return ~(reg  24) + 1;
+}
+
+/* configure the timing of one of the available external chip select lines */
+int

[PATCH 7/8] ARM/Samsung: add the Mini6410 platform as a user of the S3C6410 SoC

[Juergen Beisert]

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 arch/arm/Makefile   |1 +
 arch/arm/boards/friendlyarm-mini6410/Makefile   |1 +
 arch/arm/boards/friendlyarm-mini6410/config.h   |8 +
 arch/arm/boards/friendlyarm-mini6410/env/config |   56 +
 arch/arm/boards/friendlyarm-mini6410/mini6410.c |  305 +++
 arch/arm/configs/friendlyarm_mini6410_defconfig |   40 +++
 arch/arm/mach-samsung/Kconfig   |   16 ++
 7 files changed, 427 insertions(+)
 create mode 100644 arch/arm/boards/friendlyarm-mini6410/Makefile
 create mode 100644 arch/arm/boards/friendlyarm-mini6410/config.h
 create mode 100644 arch/arm/boards/friendlyarm-mini6410/env/config
 create mode 100644 arch/arm/boards/friendlyarm-mini6410/mini6410.c
 create mode 100644 arch/arm/configs/friendlyarm_mini6410_defconfig

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1225df7..bd03fe6 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -123,6 +123,7 @@ board-$(CONFIG_MACH_FREESCALE_MX53_LOCO):= 
freescale-mx53-loco
 board-$(CONFIG_MACH_FREESCALE_MX53_SMD):= freescale-mx53-smd
 board-$(CONFIG_MACH_GUF_CUPID) := guf-cupid
 board-$(CONFIG_MACH_MINI2440)  := mini2440
+board-$(CONFIG_MACH_MINI6410)  := friendlyarm-mini6410
 board-$(CONFIG_MACH_QIL_A9260) := qil-a9260
 board-$(CONFIG_MACH_TNY_A9260) := tny-a926x
 board-$(CONFIG_MACH_TNY_A9263) := tny-a926x
diff --git a/arch/arm/boards/friendlyarm-mini6410/Makefile 
b/arch/arm/boards/friendlyarm-mini6410/Makefile
new file mode 100644
index 000..cd7a427
--- /dev/null
+++ b/arch/arm/boards/friendlyarm-mini6410/Makefile
@@ -0,0 +1 @@
+obj-y += mini6410.o
diff --git a/arch/arm/boards/friendlyarm-mini6410/config.h 
b/arch/arm/boards/friendlyarm-mini6410/config.h
new file mode 100644
index 000..ee38192
--- /dev/null
+++ b/arch/arm/boards/friendlyarm-mini6410/config.h
@@ -0,0 +1,8 @@
+/* FriendlyARM Mini6410 specific global settings */
+
+#ifndef _MINI6410_CONFIG_H_
+# define _MINI6410_CONFIG_H_
+
+#define S3C64XX_CLOCK_REFERENCE 1200
+
+#endif /* _MINI6410_CONFIG_H_ */
diff --git a/arch/arm/boards/friendlyarm-mini6410/env/config 
b/arch/arm/boards/friendlyarm-mini6410/env/config
new file mode 100644
index 000..a1c86e1
--- /dev/null
+++ b/arch/arm/boards/friendlyarm-mini6410/env/config
@@ -0,0 +1,56 @@
+#!/bin/sh
+
+machine=mini6410
+eth0.serverip=a.b.c.d.e
+user=
+
+# use 'dhcp' to do dhcp in barebox and in kernel
+# use 'none' if you want to skip kernel ip autoconfiguration
+ip=dhcp
+
+# or set your networking parameters here
+#eth0.ipaddr=a.b.c.d.e
+#eth0.netmask=a.b.c.d.e
+#eth0.gateway=a.b.c.d.e
+eth0.ethaddr=08:90:90:90:90:90
+
+# can be either 'nfs', 'tftp' or 'nand'
+kernel_loc=tftp
+# can be either 'net', 'nand' or 'initrd'
+rootfs_loc=net
+
+# can be either 'jffs2' or 'ubifs'
+rootfs_type=ubifs
+rootfsimage=root-${machine}.${rootfs_type}
+
+# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
+kernelimage_type=zimage
+kernelimage=zImage-${machine}
+#kernelimage_type=uimage
+#kernelimage=uImage-$machine
+#kernelimage_type=raw
+#kernelimage=Image-$machine
+#kernelimage_type=raw_lzo
+#kernelimage=Image-$machine.lzo
+
+if [ -n $user ]; then
+   kernelimage=${user}-${kernelimage}
+   nfsroot=${eth0.serverip}:/home/${user}/nfsroot/${machine}
+   rootfsimage=${user}-${rootfsimage}
+else
+   nfsroot=${eth0.serverip}:/path/to/nfs/root
+fi
+
+autoboot_timeout=3
+
+#
+# mini6410 kernel parameter
+# 0 .. 9 = screen type
+# i = touchscreen with propritary FriendlyARM protocol
+# Note: can be minit6410=  if nothing of these components are connected
+#
+bootargs=console=ttySAC0,115200 mini6410=0
+
+nand_device=nand
+nand_parts=256k(barebox),128k(bareboxenv),1536k(kernel),-(root)
+rootfs_mtdblock_nand=3
diff --git a/arch/arm/boards/friendlyarm-mini6410/mini6410.c 
b/arch/arm/boards/friendlyarm-mini6410/mini6410.c
new file mode 100644
index 000..01437ac
--- /dev/null
+++ b/arch/arm/boards/friendlyarm-mini6410/mini6410.c
@@ -0,0 +1,305 @@
+/*
+ * Copyright (C) 2012 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include common.h
+#include driver.h
+#include init.h
+#include dm9000.h
+#include gpio.h
+#include generated/mach-types.h
+#include asm/armlinux.h
+#include mach/s3c-iomap.h
+#include mach/devices-s3c64xx.h
+#include mach/s3c-generic.h
+
+/*
+ * dm9000 network controller onboard

[PATCH 8/8] ARM/Samsung: add the Tiny6410 platform as a user of the S3C6410 SoC

[Juergen Beisert]

The Tiny6410 and its base board is a pure development platform.

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 arch/arm/Makefile  |1 +
 arch/arm/boards/friendlyarm-tiny6410/Kconfig   |   19 
 arch/arm/boards/friendlyarm-tiny6410/Makefile  |3 +
 arch/arm/boards/friendlyarm-tiny6410/config.h  |8 ++
 .../friendlyarm-tiny6410/development-board.c   |  100 
 arch/arm/boards/friendlyarm-tiny6410/env/config|   56 +++
 arch/arm/boards/friendlyarm-tiny6410/tiny6410.c|   80 
 arch/arm/boards/friendlyarm-tiny6410/tiny6410.h|   14 +++
 arch/arm/configs/friendlyarm_tiny6410_defconfig|   41 
 arch/arm/mach-samsung/Kconfig  |   15 +++
 10 files changed, 337 insertions(+)
 create mode 100644 arch/arm/boards/friendlyarm-tiny6410/Kconfig
 create mode 100644 arch/arm/boards/friendlyarm-tiny6410/Makefile
 create mode 100644 arch/arm/boards/friendlyarm-tiny6410/config.h
 create mode 100644 arch/arm/boards/friendlyarm-tiny6410/development-board.c
 create mode 100644 arch/arm/boards/friendlyarm-tiny6410/env/config
 create mode 100644 arch/arm/boards/friendlyarm-tiny6410/tiny6410.c
 create mode 100644 arch/arm/boards/friendlyarm-tiny6410/tiny6410.h
 create mode 100644 arch/arm/configs/friendlyarm_tiny6410_defconfig

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index bd03fe6..ab3f730 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -124,6 +124,7 @@ board-$(CONFIG_MACH_FREESCALE_MX53_SMD) := 
freescale-mx53-smd
 board-$(CONFIG_MACH_GUF_CUPID) := guf-cupid
 board-$(CONFIG_MACH_MINI2440)  := mini2440
 board-$(CONFIG_MACH_MINI6410)  := friendlyarm-mini6410
+board-$(CONFIG_MACH_TINY6410)  := friendlyarm-tiny6410
 board-$(CONFIG_MACH_QIL_A9260) := qil-a9260
 board-$(CONFIG_MACH_TNY_A9260) := tny-a926x
 board-$(CONFIG_MACH_TNY_A9263) := tny-a926x
diff --git a/arch/arm/boards/friendlyarm-tiny6410/Kconfig 
b/arch/arm/boards/friendlyarm-tiny6410/Kconfig
new file mode 100644
index 000..374820f
--- /dev/null
+++ b/arch/arm/boards/friendlyarm-tiny6410/Kconfig
@@ -0,0 +1,19 @@
+if MACH_TINY6410
+
+choice
+   prompt FriendlyARM Tiny6410 baseboard
+   help
+ Since the Tiny6410 is a CPU card only, it requires a basebord to make
+ it work. Select here the baseboard Barebox should expect and
+ configure.
+
+config MACH_TINY6410_FA
+   bool
+   select HAS_DM9000
+   prompt FA development platform
+   help
+ FriendlyARM's Tiny6410 evaluation board.
+
+endchoice
+
+endif
diff --git a/arch/arm/boards/friendlyarm-tiny6410/Makefile 
b/arch/arm/boards/friendlyarm-tiny6410/Makefile
new file mode 100644
index 000..b3ab12e
--- /dev/null
+++ b/arch/arm/boards/friendlyarm-tiny6410/Makefile
@@ -0,0 +1,3 @@
+obj-y += tiny6410.o
+
+obj-$(CONFIG_MACH_TINY6410_FA) += development-board.o
diff --git a/arch/arm/boards/friendlyarm-tiny6410/config.h 
b/arch/arm/boards/friendlyarm-tiny6410/config.h
new file mode 100644
index 000..04f6857
--- /dev/null
+++ b/arch/arm/boards/friendlyarm-tiny6410/config.h
@@ -0,0 +1,8 @@
+/* FriendlyARM Tiny6410 specific global settings */
+
+#ifndef _TINY6410_CONFIG_H_
+# define _TINY6410_CONFIG_H_
+
+#define S3C64XX_CLOCK_REFERENCE 1200
+
+#endif /* _TINY6410_CONFIG_H_ */
diff --git a/arch/arm/boards/friendlyarm-tiny6410/development-board.c 
b/arch/arm/boards/friendlyarm-tiny6410/development-board.c
new file mode 100644
index 000..5595900
--- /dev/null
+++ b/arch/arm/boards/friendlyarm-tiny6410/development-board.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright (C) 2012 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * The FriendlyARM's Tiny6410 evaluation board comes with all connectors and
+ * devices to make the Tiny6410 CPU card work. This includes:
+ *
+ * - the DM9000 network controller
+ * - USB/MCI connectors
+ * - display connector
+ *
+ */
+#include common.h
+#include driver.h
+#include init.h
+#include gpio.h
+#include dm9000.h
+#include mach/devices-s3c64xx.h
+#include mach/s3c-generic.h
+
+#include tiny6410.h
+
+/*
+ * dm9000 network controller onboard
+ * Connected to CS line 1 and interrupt line EINT7,
+ * data width is 16 bit
+ * Area 1: Offset 0x300...0x301
+ * Area 2: Offset 0x304...0x305
+ */
+static struct dm9000_platform_data dm9000_data = {
+   .srom = 0,  /* no serial ROM

[PATCH 4/8] ARM/Samsung: add GPIO handling support for the S3C6410 SoC

[Juergen Beisert]

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 arch/arm/mach-samsung/Makefile |2 +-
 arch/arm/mach-samsung/gpio-s3c64xx.c   |  301 +++
 arch/arm/mach-samsung/include/mach/gpio.h  |3 +
 arch/arm/mach-samsung/include/mach/iomux-s3c64xx.h |  542 
 4 files changed, 847 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-samsung/gpio-s3c64xx.c
 create mode 100644 arch/arm/mach-samsung/include/mach/iomux-s3c64xx.h

diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
index 71dc0de..70489da 100644
--- a/arch/arm/mach-samsung/Makefile
+++ b/arch/arm/mach-samsung/Makefile
@@ -2,6 +2,6 @@ obj-y += s3c-timer.o generic.o
 obj-lowlevel-$(CONFIG_ARCH_S3C24xx) += lowlevel-s3c24x0.o
 obj-lowlevel-$(CONFIG_ARCH_S5PCxx) += lowlevel-s5pcxx.o
 obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o s3c24xx-clocks.o mem-s3c24x0.o
-obj-$(CONFIG_ARCH_S3C64xx) += clocks-s3c64xx.o
+obj-$(CONFIG_ARCH_S3C64xx) += gpio-s3c64xx.o clocks-s3c64xx.o
 obj-$(CONFIG_ARCH_S5PCxx) += gpio-s5pcxx.o clocks-s5pcxx.o
 obj-$(CONFIG_S3C_LOWLEVEL_INIT) += $(obj-lowlevel-y)
diff --git a/arch/arm/mach-samsung/gpio-s3c64xx.c 
b/arch/arm/mach-samsung/gpio-s3c64xx.c
new file mode 100644
index 000..ee68261
--- /dev/null
+++ b/arch/arm/mach-samsung/gpio-s3c64xx.c
@@ -0,0 +1,301 @@
+/*
+ * Copyright (C) 2012 Juergen Beisert
+ *
+ * This code bases partially on code from the Linux kernel:
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks b...@simtec.co.uk
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include common.h
+#include errno.h
+#include io.h
+#include gpio.h
+#include mach/s3c-iomap.h
+
+#define S3C_GPACON (S3C_GPIO_BASE)
+#define S3C_GPADAT (S3C_GPIO_BASE + 0x04)
+#define S3C_GPAPUD (S3C_GPIO_BASE + 0x08)
+
+static const unsigned short group_offset[] = {
+   0x000,  /* GPA */ /* 8 pins, 4 bit each */
+   0x020,  /* GPB */ /* 7 pins, 4 bit each */
+   0x040,  /* GPC */ /* 8 pins, 4 bit each */
+   0x060,  /* GPD */ /* 5 pins, 4 bit each */
+   0x080,  /* GPE */ /* 5 pins, 4 bit each */
+   0x0a0,  /* GPF */ /* 16 pins, 2 bit each */
+   0x0c0,  /* GPG */ /* 7 pins, 4 bit each */
+   0x0e0,  /* GPH */ /* two registers, 8 + 2 pins, 4 bit each */
+   0x100,  /* GPI */ /* 16 pins, 2 bit each */
+   0x120,  /* GPJ */ /* 12 pins, 2 bit each */
+   0x800,  /* GPK */ /* two registers, 8 + 8 pins, 4 bit each */
+   0x810,  /* GPL */ /* two registers, 8 + 8 pins, 4 bit each */
+   0x820,  /* GPM */ /* 6 pins, 4 bit each */
+   0x830,  /* GPN */ /* 16 pins, 2 bit each */
+   0x140,  /* GPO */ /* 16 pins, 2 bit each */
+   0x160,  /* GPP */ /* 15 pins, 2 bit each */
+   0x180,  /* GPQ */ /* 9 pins, 2 bit each */
+};
+
+void gpio_set_value(unsigned gpio, int value)
+{
+   unsigned group = GET_GROUP(gpio);
+   unsigned bit = GET_BIT(gpio);
+   unsigned offset;
+   uint32_t reg;
+
+   offset = group_offset[group];
+
+   switch (group) {
+   case 7: /* GPH */
+   case 10:/* GPK */
+   case 11:/* GPL */
+   offset += 4;
+   break;
+   }
+
+   reg = readl(S3C_GPADAT + offset);
+   reg = ~(1  bit);
+   reg |= (!!value)  bit;
+   writel(reg, S3C_GPADAT + offset);
+}
+
+int gpio_get_value(unsigned gpio)
+{
+   unsigned group = GET_GROUP(gpio);
+   unsigned bit = GET_BIT(gpio);
+   unsigned offset;
+   uint32_t reg;
+
+   offset = group_offset[group];
+
+   switch (group) {
+   case 7: /* GPH */
+   case 10:/* GPK */
+   case 11:/* GPL */
+   offset += 4;
+   break;
+   }
+
+   /* value */
+   reg = readl(S3C_GPADAT + offset);
+
+   return !!(reg  (1  bit));
+}
+
+static void gpio_direction_input_4b(unsigned offset, unsigned bit)
+{
+   uint32_t reg;
+
+   if (bit  31) {
+   offset += 4;
+   bit -= 32;
+   }
+
+   reg = readl(S3C_GPACON + offset)  ~(0xf  bit);
+   writel(reg, S3C_GPACON + offset); /* b means 'GPIO input' */
+}
+
+static void gpio_direction_input_2b(unsigned offset, unsigned bit)
+{
+   uint32_t reg;
+
+   reg = readl(S3C_GPACON + offset)  ~(0x3  bit);
+   writel(reg, S3C_GPACON + offset); /* b00 means 'GPIO input' */
+}
+
+int gpio_direction_input(unsigned gpio

[PATCH 3/8] ARM/Samsung: add the clock tree support for the S3C6410 SoC

[Juergen Beisert]

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 arch/arm/mach-samsung/Makefile |1 +
 arch/arm/mach-samsung/clocks-s3c64xx.c |  338 
 arch/arm/mach-samsung/include/mach/s3c-clocks.h|3 +
 .../arm/mach-samsung/include/mach/s3c64xx-clocks.h |   67 
 4 files changed, 409 insertions(+)
 create mode 100644 arch/arm/mach-samsung/clocks-s3c64xx.c
 create mode 100644 arch/arm/mach-samsung/include/mach/s3c64xx-clocks.h

diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
index d7344c8..71dc0de 100644
--- a/arch/arm/mach-samsung/Makefile
+++ b/arch/arm/mach-samsung/Makefile
@@ -2,5 +2,6 @@ obj-y += s3c-timer.o generic.o
 obj-lowlevel-$(CONFIG_ARCH_S3C24xx) += lowlevel-s3c24x0.o
 obj-lowlevel-$(CONFIG_ARCH_S5PCxx) += lowlevel-s5pcxx.o
 obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o s3c24xx-clocks.o mem-s3c24x0.o
+obj-$(CONFIG_ARCH_S3C64xx) += clocks-s3c64xx.o
 obj-$(CONFIG_ARCH_S5PCxx) += gpio-s5pcxx.o clocks-s5pcxx.o
 obj-$(CONFIG_S3C_LOWLEVEL_INIT) += $(obj-lowlevel-y)
diff --git a/arch/arm/mach-samsung/clocks-s3c64xx.c 
b/arch/arm/mach-samsung/clocks-s3c64xx.c
new file mode 100644
index 000..cf7d071
--- /dev/null
+++ b/arch/arm/mach-samsung/clocks-s3c64xx.c
@@ -0,0 +1,338 @@
+/*
+ * Copyright (C) 2012 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include config.h
+#include common.h
+#include init.h
+#include clock.h
+#include io.h
+#include asm-generic/div64.h
+#include mach/s3c-iomap.h
+#include mach/s3c-generic.h
+#include mach/s3c-clocks.h
+
+/*
+ * The main clock tree:
+ *
+ * ref_in
+ *|
+ *v
+ *o---\
+ *|MUX -o\
+ *|   / ^   | MUX --- DIV_APLL --- ARMCLK - CPU 
core
+ *o--- APLL --  |   |/ |
+ *| |   o--/2 ---  |
+ *|   APLL_SEL  |  |-MISC_CON_SYN667
+ *| \  |
+ *o---\  MUX-o---\ |
+ *|MUX--/ ^  |MUX --- DIV -o- HCLKx2 - SDRAM 
(max. 266 MHz)
+ *|   / ^ |  |   / |
+ *o MPLL--  | |  o--/5 --  o-- DIV -- HCLK - AXI / 
AHB (max. 133 MHz)
+ *| | ||
+ *|   MPLL_SEL  OTHERS_CLK_SELECT  o-- DIV -- PCLK - APB 
(max. 66 MHz)
+ *|
+ *o---\
+ *|MUX to various hardware
+ *|   / ^
+ *o EPLL--  EPLL_SEL
+ *
+ */
+
+static unsigned s3c_get_apllclk(void)
+{
+   uint32_t m, p, s, reg_val;
+
+   if (!(readl(S3C_CLK_SRC)  S3C_CLK_SRC_FOUTAPLL))
+   return S3C64XX_CLOCK_REFERENCE;
+
+   reg_val = readl(S3C_APLLCON);
+   if (!(reg_val  S3C_APLLCON_ENABLE))
+   return 0;
+   m = S3C_APLLCON_GET_MDIV(reg_val);
+   p = S3C_APLLCON_GET_PDIV(reg_val);
+   s = S3C_APLLCON_GET_SDIV(reg_val);
+
+   return (S3C64XX_CLOCK_REFERENCE * m) / (p  s);
+}
+
+uint32_t s3c_get_mpllclk(void)
+{
+   uint32_t m, p, s, reg_val;
+
+   if (!(readl(S3C_CLK_SRC)  S3C_CLK_SRC_FOUTMPLL))
+   return S3C64XX_CLOCK_REFERENCE;
+
+   reg_val = readl(S3C_MPLLCON);
+   if (!(reg_val  S3C_MPLLCON_ENABLE))
+   return 0;
+
+   m = S3C_MPLLCON_GET_MDIV(reg_val);
+   p = S3C_MPLLCON_GET_PDIV(reg_val);
+   s = S3C_MPLLCON_GET_SDIV(reg_val);
+
+   return (S3C64XX_CLOCK_REFERENCE * m) / (p  s);
+}
+
+unsigned s3c_get_epllclk(void)
+{
+   u32 m, p, s, k, reg0_val, reg1_val;
+   u64 tmp;
+
+   if (!(readl(S3C_CLK_SRC)  S3C_CLK_SRC_FOUTEPLL))
+   return S3C64XX_CLOCK_REFERENCE;
+
+   reg0_val = readl(S3C_EPLLCON0);
+   if (!(reg0_val  S3C_EPLLCON0_ENABLE))
+   return 0;   /* PLL is disabled */
+
+   reg1_val = readl(S3C_EPLLCON1);
+   m = S3C_EPLLCON0_GET_MDIV(reg0_val);
+   p = S3C_EPLLCON0_GET_PDIV(reg0_val);
+   s = S3C_EPLLCON0_GET_SDIV(reg0_val);
+   k = S3C_EPLLCON1_GET_KDIV(reg1_val);
+
+   tmp = S3C64XX_CLOCK_REFERENCE;
+   tmp *= (m  16) + k;
+   do_div(tmp, (p  s));
+
+   return (unsigned)(tmp  16);
+}
+
+unsigned s3c_set_epllclk(unsigned m, unsigned p, unsigned s, unsigned k)
+{
+   u32 con0, con1, src = readl(S3C_CLK_SRC)  ~S3C_CLK_SRC_FOUTEPLL;
+
+   /* do not use the EPLL clock when it is in transit to the new frequency 
*/
+   writel(src, S3C_CLK_SRC);
+
+   con0 = S3C_EPLLCON0_SET_MDIV

RFC: How to setup and handle NAND flashes in Barebox

[Juergen Beisert]

Sascha Hauer wrote:
 On Fri, Jul 27, 2012 at 11:24:48AM +1000, Marc Reilly wrote:
  Thanks for your ideas.
 
  I managed to clear the BBT, it was a bit of a hack... the saga is below
  for anyone who runs into similar problem.
 
  On Thursday, July 26, 2012 11:27:48 AM Juergen Beisert wrote:
   The flash blocks which contains the bad block table are protected by
   the bad block table aware MTD layer.
  
   So, the ugly way: run a bootloader which does not use the in-flash bad
   block table. Then the tables are regular blocks in the flash and can be
   erased. After that run again the bad block table aware bootloader and
   it will re-create the in-flash table. But be careful: In this case the
   generic functions scans all blocks in the NAND to collect the bad block
   markers in each NAND block's OOB. If this information is already
   destroyed somehow, this solution does not help.
 
  Recompiling barebox with bbt support disabled stopped the all the bad
  block messages, however erasing the nand didn't clear the BBT for
  subsequent reboots...
  The issue was that the erase commands and functions skip erasing bad
  blocks, and the blocks that held the actual BBT were being considered
  bad, so they weren't getting erased. After commenting out calls to
  nand_block_checkbad() in nand_write.c and block_isbad() in
  mtd_erase()/core.c I was able to manually erase the blocks. (erasing
  actual bad blocks results in I/O error) Next restart of barebox the BBT
  was regenerated with the two actual bad blocks.
 
  After all that, I noticed imx_low_erase() in nand_imx.c. Probably would
  have been easier to make up a command around that.

 This problem comes up regularly. I remember Wolfram implemented a nand
 'scrub' command. He was working on i.MX28. I don't know wether his
 command was i.MX28 specific, but it would be nice to have such a command
 around.

Just an idea:

I think we need something like a NAND handling environment. For example the 
MTD generates a in-flash bad block table without any interaction. That might 
be a nice feature, but only when:

 - the factory bad block markers are still intact
 - the regular NAND driver can read the factory bad block markers (the i.MX
   driver for example cannot)
 - the flash is more or less untouched yet

Whenever one of these dependencies are not valid (anymore), we are in trouble 
with automatically generation of the in-flash bad block table.
Use cases are for example: general development on NAND drivers, a Linux driver 
that crashes the NAND somehow or a different bootloader/operation system that 
uses its own ways to handle and mark bad blocks.
For these use-cases we need a different approach: something we can do 
manually.

 - a 'test' command that checks if the factory bad block markers seems still
   intact (or not). This command should have some parameters where you can
   describe the expected OOB layout to be able to check for various ways to
   mark bad blocks
 - a 'list' command which lists all the currently known bad blocks (from
   whatever source, in-flash or in-ram BBT or freshly read from the OOB area)
   This list could be stored somewhere (like the bad sector table in the
   early days of hard disks). At least this would help later on to still use a
   NAND memory where all the OOB based bad block markers are lost. For example
   with my S3C6410 CPU the internal ROM routines force me to write the
   checksums into a position in the OOB where most of the manufacturers 
   stores the factory bad block info. So, there is no simple way later
   on to distinguish checksums from bad block markers.
 - a 'create' command for the in-flash BBT. This command can use the the
   result of the 'list' command or should accept a list of *known' bad blocks
   manually entered

With these tools we could instruct Barebox to use an in-flash BBT only if it 
already exists. If not, it should fall back to OOB scan, and should not write 
an in-flash BBT with the collected information.
A user then can run the various tools to get an idea if the NAND is intact (or 
not) and the 'create' command would then write a correct in-flash BBT (with 
the help of the other collecting commands) to be used by Barebox itself and 
Linux. 

jbe

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Linux Solutions for Science and Industry  | http://www.pengutronix.de/  |


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Re: [PATCH RFC] arm/imx: provide command to add ram device with autodetected size

[Juergen Beisert]

Uwe Kleine-König wrote:
 The amount of available ram is determined by the ESDCTL register, so
 better don't hardcode the value.

 This commit provides a command that can be used instead of
 arm_add_mem_device and convertes pcm043 (on which this patch was tested)
 to it.

 Signed-off-by: Uwe Kleine-König u.kleine-koe...@pengutronix.de
 ---
 Hello,

 maybe better move the new function into a new file
 arch/arm/mach-imx/esdctl.c and the prototype into mach/esdctl.h?

 Also imx_add_ram1() is still missing. I will implement that when we
 agree the patch's idea is useful.

It is a really good idea. I is useful for all my Samsung targets, too.
Maybe it should be a generic feature, because *most* of the supported SoCs are 
able to detect the available RAM size in such a way.

jbe


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[PATCH] ARM/Samsung: remaining clean up...

[Juergen Beisert]

...in preparation to add the S3C6410 SoC support.

Mostly simplifying the Samsung serial driver and some more cosmetic. These
patches are a re-work and re-send of the remaining ones not yet included from
the previous ARM/Samsung: more clean up... series.

The patches 1/3 and 3/3 base on the current next, because they touch code
for the new S5Pxx SoCs.

jbe


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[PATCH 5/8] ARM/Samsung: add generic S3C6410 SoC specific functions

[Juergen Beisert]

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 arch/arm/mach-samsung/Makefile |2 +-
 .../mach-samsung/include/mach/devices-s3c64xx.h|   40 
 arch/arm/mach-samsung/include/mach/s3c-generic.h   |   16 +
 arch/arm/mach-samsung/mem-s3c64xx.c|   66 
 4 files changed, 123 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-samsung/include/mach/devices-s3c64xx.h
 create mode 100644 arch/arm/mach-samsung/mem-s3c64xx.c

diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
index 9a2484f..42a6708 100644
--- a/arch/arm/mach-samsung/Makefile
+++ b/arch/arm/mach-samsung/Makefile
@@ -2,5 +2,5 @@ obj-y += s3c-timer.o generic.o
 obj-lowlevel-$(CONFIG_ARCH_S3C24xx) += lowlevel-s3c24x0.o
 obj-lowlevel-$(CONFIG_ARCH_S5PCxx) += lowlevel-s5pcxx.o
 obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o clocks-s3c24xx.o mem-s3c24x0.o
-obj-$(CONFIG_ARCH_S3C64xx) += gpio-s3c64xx.o clocks-s3c64xx.o
+obj-$(CONFIG_ARCH_S3C64xx) += gpio-s3c64xx.o clocks-s3c64xx.o mem-s3c64xx.o
 obj-$(CONFIG_S3C_LOWLEVEL_INIT) += $(obj-lowlevel-y)
diff --git a/arch/arm/mach-samsung/include/mach/devices-s3c64xx.h 
b/arch/arm/mach-samsung/include/mach/devices-s3c64xx.h
new file mode 100644
index 000..bcbee97
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/devices-s3c64xx.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2012 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef INCLUDE_MACH_DEVICES_S3C64XX_H
+# define INCLUDE_MACH_DEVICES_S3C64XX_H
+
+#include driver.h
+#include mach/s3c64xx-iomap.h
+
+static inline void s3c64xx_add_uart1(void)
+{
+   add_generic_device(s3c_serial, DEVICE_ID_DYNAMIC, NULL, 
S3C_UART1_BASE,
+   S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
+}
+
+static inline void s3c64xx_add_uart2(void)
+{
+   add_generic_device(s3c_serial, DEVICE_ID_DYNAMIC, NULL, 
S3C_UART2_BASE,
+   S3C_UART2_SIZE, IORESOURCE_MEM, NULL);
+}
+
+static inline void s3c64xx_add_uart3(void)
+{
+   add_generic_device(s3c_serial, DEVICE_ID_DYNAMIC, NULL, 
S3C_UART3_BASE,
+   S3C_UART3_SIZE, IORESOURCE_MEM, NULL);
+}
+
+#endif /* INCLUDE_MACH_DEVICES_S3C64XX_H */
diff --git a/arch/arm/mach-samsung/include/mach/s3c-generic.h 
b/arch/arm/mach-samsung/include/mach/s3c-generic.h
index 11b083d..b4a9e69 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-generic.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-generic.h
@@ -41,3 +41,19 @@ void s3c24xx_disable_second_sdram_bank(void);
 #ifdef CONFIG_ARCH_S5PCxx
 void s5p_init_pll(void);
 #endif
+
+#ifdef CONFIG_ARCH_S3C64xx
+uint32_t s3c_get_epllclk(void);
+unsigned s3c_get_hsmmc_clk(int);
+void s3c_set_hsmmc_clk(int, int, unsigned);
+unsigned s3c6410_get_memory_size(void);
+struct s3c6410_chipselect {
+   unsigned adr_setup_t; /* in [ns] */
+   unsigned access_setup_t; /* in [ns] */
+   unsigned access_t; /* in [ns] */
+   unsigned cs_hold_t; /* in [ns] */
+   unsigned adr_hold_t; /* in [ns] */
+   unsigned char width; /* 8 or 16 */
+};
+int s3c6410_setup_chipselect(int, const struct s3c6410_chipselect*);
+#endif
diff --git a/arch/arm/mach-samsung/mem-s3c64xx.c 
b/arch/arm/mach-samsung/mem-s3c64xx.c
new file mode 100644
index 000..aca2cf5
--- /dev/null
+++ b/arch/arm/mach-samsung/mem-s3c64xx.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2012 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include common.h
+#include errno.h
+#include io.h
+#include mach/s3c-iomap.h
+#include mach/s3c-generic.h
+
+#define S3C_DRAMC_CHIP_0_CFG (S3C_DRAMC + 0x200)
+
+/* note: this routine honors the first memory bank only */
+unsigned s3c6410_get_memory_size(void)
+{
+   unsigned reg = readl(S3C_DRAMC_CHIP_0_CFG)  0xff;
+
+   return ~(reg  24) + 1;
+}
+
+/* configure the timing of one of the available external chip select lines */
+int s3c6410_setup_chipselect(int no, const struct s3c6410_chipselect *c)
+{
+   unsigned per_t = 10 / s3c_get_hclk

[PATCH 2/8] ARM/Samsung: adapt the generic timer driver to support the S3C6410 SoC

[Juergen Beisert]

The S3C64XX SoC has a real 32 bit counter, but almost the same style of
registers. It's enough to change the parameters, to get the routines work on
this SoC.

TODO: what about the S5P SoCs?

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 arch/arm/mach-samsung/s3c-timer.c |   17 +
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-samsung/s3c-timer.c 
b/arch/arm/mach-samsung/s3c-timer.c
index 6665c8c..271f97d 100644
--- a/arch/arm/mach-samsung/s3c-timer.c
+++ b/arch/arm/mach-samsung/s3c-timer.c
@@ -37,11 +37,20 @@
 #define S3C_TCNTB4 (S3C_TIMER_BASE + 0x3c)
 #define S3C_TCNTO4 (S3C_TIMER_BASE + 0x40)
 
-#define TIMER_WIDTH 16
-#define TIMER_SHIFT 10
-#define PRE_MUX 3
-#define PRE_MUX_ADD 1
+#ifdef CONFIG_ARCH_S3C24xx
+# define TIMER_WIDTH 16
+# define TIMER_SHIFT 10
+# define PRE_MUX 3
+# define PRE_MUX_ADD 1
 static const uint32_t max = 0x;
+#endif
+#ifdef CONFIG_ARCH_S3C64xx
+# define TIMER_WIDTH 32
+# define TIMER_SHIFT 10
+# define PRE_MUX 4
+# define PRE_MUX_ADD 0
+static const uint32_t max = ~0;
+#endif
 
 static void s3c_init_t4_clk_source(void)
 {
-- 
1.7.10.4


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[PATCH] Addd the Samsung S3C6410 SoC to Barebox

[Juergen Beisert]

This patch series tries to add support for the Samsung's S3C6410 ARMv11 SoC
and with this main support also two popular platforms which are using this
SoC: FriendlyARM's Mini6410 and Tiny6410.

Comments are welcome.

If someone wants to try this series it can be found here
git://git.pengutronix.de/git/jbe/barebox.git, branch master_s3c6410_inclusion

Note: this series depends on the previously sent patch series
ARM/Samsung: more clean up...

Juergen


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[PATCH 8/8] ARM/Samsung: add the Tiny6410 platform as the second user of the S3C6410 SoC

[Juergen Beisert]

The Tiny6410 and its base board is a pure development platform.

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 arch/arm/Makefile  |1 +
 arch/arm/boards/friendlyarm-tiny6410/Kconfig   |   19 
 arch/arm/boards/friendlyarm-tiny6410/Makefile  |3 +
 arch/arm/boards/friendlyarm-tiny6410/config.h  |8 ++
 .../friendlyarm-tiny6410/development-board.c   |  100 
 arch/arm/boards/friendlyarm-tiny6410/env/config|   56 +++
 arch/arm/boards/friendlyarm-tiny6410/tiny6410.c|   80 
 arch/arm/boards/friendlyarm-tiny6410/tiny6410.h|   14 +++
 arch/arm/configs/friendlyarm_tiny6410_defconfig|   41 
 arch/arm/configs/tiny6410_defconfig|   41 
 arch/arm/mach-samsung/Kconfig  |   11 +++
 11 files changed, 374 insertions(+)
 create mode 100644 arch/arm/boards/friendlyarm-tiny6410/Kconfig
 create mode 100644 arch/arm/boards/friendlyarm-tiny6410/Makefile
 create mode 100644 arch/arm/boards/friendlyarm-tiny6410/config.h
 create mode 100644 arch/arm/boards/friendlyarm-tiny6410/development-board.c
 create mode 100644 arch/arm/boards/friendlyarm-tiny6410/env/config
 create mode 100644 arch/arm/boards/friendlyarm-tiny6410/tiny6410.c
 create mode 100644 arch/arm/boards/friendlyarm-tiny6410/tiny6410.h
 create mode 100644 arch/arm/configs/friendlyarm_tiny6410_defconfig
 create mode 100644 arch/arm/configs/tiny6410_defconfig

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index bd03fe6..ab3f730 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -124,6 +124,7 @@ board-$(CONFIG_MACH_FREESCALE_MX53_SMD) := 
freescale-mx53-smd
 board-$(CONFIG_MACH_GUF_CUPID) := guf-cupid
 board-$(CONFIG_MACH_MINI2440)  := mini2440
 board-$(CONFIG_MACH_MINI6410)  := friendlyarm-mini6410
+board-$(CONFIG_MACH_TINY6410)  := friendlyarm-tiny6410
 board-$(CONFIG_MACH_QIL_A9260) := qil-a9260
 board-$(CONFIG_MACH_TNY_A9260) := tny-a926x
 board-$(CONFIG_MACH_TNY_A9263) := tny-a926x
diff --git a/arch/arm/boards/friendlyarm-tiny6410/Kconfig 
b/arch/arm/boards/friendlyarm-tiny6410/Kconfig
new file mode 100644
index 000..374820f
--- /dev/null
+++ b/arch/arm/boards/friendlyarm-tiny6410/Kconfig
@@ -0,0 +1,19 @@
+if MACH_TINY6410
+
+choice
+   prompt FriendlyARM Tiny6410 baseboard
+   help
+ Since the Tiny6410 is a CPU card only, it requires a basebord to make
+ it work. Select here the baseboard Barebox should expect and
+ configure.
+
+config MACH_TINY6410_FA
+   bool
+   select HAS_DM9000
+   prompt FA development platform
+   help
+ FriendlyARM's Tiny6410 evaluation board.
+
+endchoice
+
+endif
diff --git a/arch/arm/boards/friendlyarm-tiny6410/Makefile 
b/arch/arm/boards/friendlyarm-tiny6410/Makefile
new file mode 100644
index 000..b3ab12e
--- /dev/null
+++ b/arch/arm/boards/friendlyarm-tiny6410/Makefile
@@ -0,0 +1,3 @@
+obj-y += tiny6410.o
+
+obj-$(CONFIG_MACH_TINY6410_FA) += development-board.o
diff --git a/arch/arm/boards/friendlyarm-tiny6410/config.h 
b/arch/arm/boards/friendlyarm-tiny6410/config.h
new file mode 100644
index 000..04f6857
--- /dev/null
+++ b/arch/arm/boards/friendlyarm-tiny6410/config.h
@@ -0,0 +1,8 @@
+/* FriendlyARM Tiny6410 specific global settings */
+
+#ifndef _TINY6410_CONFIG_H_
+# define _TINY6410_CONFIG_H_
+
+#define S3C64XX_CLOCK_REFERENCE 1200
+
+#endif /* _TINY6410_CONFIG_H_ */
diff --git a/arch/arm/boards/friendlyarm-tiny6410/development-board.c 
b/arch/arm/boards/friendlyarm-tiny6410/development-board.c
new file mode 100644
index 000..5595900
--- /dev/null
+++ b/arch/arm/boards/friendlyarm-tiny6410/development-board.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright (C) 2012 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * The FriendlyARM's Tiny6410 evaluation board comes with all connectors and
+ * devices to make the Tiny6410 CPU card work. This includes:
+ *
+ * - the DM9000 network controller
+ * - USB/MCI connectors
+ * - display connector
+ *
+ */
+#include common.h
+#include driver.h
+#include init.h
+#include gpio.h
+#include dm9000.h
+#include mach/devices-s3c64xx.h
+#include mach/s3c-generic.h
+
+#include tiny6410.h
+
+/*
+ * dm9000 network controller onboard
+ * Connected to CS line 1 and interrupt line EINT7,
+ * data width is 16 bit
+ * Area 1: Offset 0x300...0x301

[PATCH 1/3] ARM/Samsung: be able to include the nand header multiple times

[Juergen Beisert]

This is required in preparation for the following patches.

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 arch/arm/mach-samsung/include/mach/s3c24xx-nand.h |5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h 
b/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h
index acd78b8..fa88da1 100644
--- a/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h
+++ b/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h
@@ -18,6 +18,9 @@
  *
  */
 
+#ifndef MACH_S3C24XX_NAND_H
+# define MACH_S3C24XX_NAND_H
+
 #ifdef CONFIG_S3C_NAND_BOOT
 extern void s3c24x0_nand_load_image(void*, int, int);
 #endif
@@ -52,3 +55,5 @@ struct s3c24x0_nand_platform_data {
  * @file
  * @brief Basic declaration to use the s3c24x0 NAND driver
  */
+
+#endif /* MACH_S3C24XX_NAND_H */
-- 
1.7.10.4


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[PATCH 2/3] ARM/Samsung: unify device registration for the S3C24XX SoCs

[Juergen Beisert]

Barebox crashes since it has trouble with a resource size of 0. Most of the
S3C24XX based platforms crashes at runtime and can't use devices with resource
sizes of 0 anymore. This patch fix it by unifying the device registration for
all current Barebox's S3C24XX based platforms.

- A9M2410 and A9M2440 compile time tested only.
- Mini2440 also runtime tested.

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 arch/arm/boards/a9m2410/a9m2410.c  |7 ++-
 arch/arm/boards/a9m2440/a9m2440.c  |7 ++-
 arch/arm/boards/mini2440/mini2440.c|   16 +++---
 .../mach-samsung/include/mach/devices-s3c24xx.h|   55 
 4 files changed, 67 insertions(+), 18 deletions(-)
 create mode 100644 arch/arm/mach-samsung/include/mach/devices-s3c24xx.h

diff --git a/arch/arm/boards/a9m2410/a9m2410.c 
b/arch/arm/boards/a9m2410/a9m2410.c
index eaafdbd..e2044a9 100644
--- a/arch/arm/boards/a9m2410/a9m2410.c
+++ b/arch/arm/boards/a9m2410/a9m2410.c
@@ -32,6 +32,7 @@
 #include partition.h
 #include nand.h
 #include io.h
+#include mach/devices-s3c24xx.h
 #include mach/s3c-iomap.h
 #include mach/s3c24xx-nand.h
 #include mach/s3c-generic.h
@@ -109,8 +110,7 @@ static int a9m2410_devices_init(void)
writel(reg, S3C_MISCCR);
 
/* --- the devices the boot loader should work with  */
-   add_generic_device(s3c24x0_nand, DEVICE_ID_DYNAMIC, NULL, 
S3C24X0_NAND_BASE,
-   0, IORESOURCE_MEM, nand_info);
+   s3c24xx_add_nand(nand_info);
/*
 * SMSC 91C111 network controller on the baseboard
 * connected to CS line 1 and interrupt line
@@ -145,8 +145,7 @@ void __bare_init nand_boot(void)
 
 static int a9m2410_console_init(void)
 {
-   add_generic_device(s3c_serial, DEVICE_ID_DYNAMIC, NULL, 
S3C_UART1_BASE,
-   S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
+   s3c24xx_add_uart1();
return 0;
 }
 
diff --git a/arch/arm/boards/a9m2440/a9m2440.c 
b/arch/arm/boards/a9m2440/a9m2440.c
index 1d20248..8975c15 100644
--- a/arch/arm/boards/a9m2440/a9m2440.c
+++ b/arch/arm/boards/a9m2440/a9m2440.c
@@ -32,6 +32,7 @@
 #include partition.h
 #include nand.h
 #include io.h
+#include mach/devices-s3c24xx.h
 #include mach/s3c-iomap.h
 #include mach/s3c24xx-nand.h
 #include mach/s3c-generic.h
@@ -129,8 +130,7 @@ static int a9m2440_devices_init(void)
writel(reg, S3C_MISCCR);
 
/* --- the devices the boot loader should work with  */
-   add_generic_device(s3c24x0_nand, DEVICE_ID_DYNAMIC, NULL, 
S3C24X0_NAND_BASE, 0,
-  IORESOURCE_MEM, nand_info);
+   s3c24xx_add_nand(nand_info);
/*
 * cs8900 network controller onboard
 * Connected to CS line 5 + A24 and interrupt line EINT9,
@@ -164,8 +164,7 @@ void __bare_init nand_boot(void)
 
 static int a9m2440_console_init(void)
 {
-   add_generic_device(s3c_serial, DEVICE_ID_DYNAMIC, NULL, 
S3C_UART1_BASE,
-   S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
+   s3c24xx_add_uart1();
return 0;
 }
 
diff --git a/arch/arm/boards/mini2440/mini2440.c 
b/arch/arm/boards/mini2440/mini2440.c
index 3d3b820..3523949 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -39,6 +39,7 @@
 #include io.h
 #include mach/gpio.h
 #include mach/s3c-iomap.h
+#include mach/devices-s3c24xx.h
 #include mach/s3c24xx-nand.h
 #include mach/s3c-generic.h
 #include mach/s3c-mci.h
@@ -297,8 +298,7 @@ static int mini2440_devices_init(void)
reg |= 0x1;
writel(reg, S3C_MISCCR);
 
-   add_generic_device(s3c24x0_nand, DEVICE_ID_DYNAMIC, NULL, 
S3C24X0_NAND_BASE,
-   0, IORESOURCE_MEM, nand_info);
+   s3c24xx_add_nand(nand_info);
 
add_dm9000_device(0, S3C_CS4_BASE + 0x300, S3C_CS4_BASE + 0x304,
  IORESOURCE_MEM_16BIT, dm9000_data);
@@ -312,12 +312,9 @@ static int mini2440_devices_init(void)
devfs_add_partition(nand0, 0x4, 0x2, DEVFS_PARTITION_FIXED, 
env_raw);
dev_add_bb_dev(env_raw, env0);
 #endif
-   add_generic_device(s3c_mci, 0, NULL, S3C2410_SDI_BASE, 0,
-  IORESOURCE_MEM, mci_data);
-   add_generic_device(s3c_fb, 0, NULL, S3C2410_LCD_BASE, 0,
-  IORESOURCE_MEM, s3c24x0_fb_data);
-   add_generic_device(ohci, 0, NULL, S3C2410_USB_HOST_BASE, 0x100,
-  IORESOURCE_MEM, NULL);
+   s3c24xx_add_mci(mci_data);
+   s3c24xx_add_fb(s3c24x0_fb_data);
+   s3c24xx_add_ohci();
armlinux_set_bootparams((void*)S3C_SDRAM_BASE + 0x100);
armlinux_set_architecture(MACH_TYPE_MINI2440);
 
@@ -344,8 +341,7 @@ static int mini2440_console_init(void)
s3c_gpio_mode(GPH2_TXD0);
s3c_gpio_mode(GPH3_RXD0);
 
-   add_generic_device(s3c_serial, DEVICE_ID_DYNAMIC, NULL, 
S3C_UART1_BASE,
-   S3C_UART1_SIZE

[PATCH/master] ARM/MXS: pull-up and bitkeeper must be handled differently

[Juergen Beisert]

Since commit 2f6b1f7690640f571f8e72fc2f2564acb2e13778 the pull-up and
bitkeeper handling for i.MX23/28 is correct. But now it is important to
distinguish these pin features as their programmed bit values are different.
With this patch the bitkeeper and pull-up enable/disable bits are now handled
separately.

Signed-off-by: Juergen Beisert j...@pengutronix.de

diff --git a/arch/arm/mach-mxs/include/mach/iomux-imx23.h 
b/arch/arm/mach-mxs/include/mach/iomux-imx23.h
index 7b2883c..82362d7 100644
--- a/arch/arm/mach-mxs/include/mach/iomux-imx23.h
+++ b/arch/arm/mach-mxs/include/mach/iomux-imx23.h
@@ -22,13 +22,14 @@
  *   Bit offset
  *^^ Function
  *   ^__ Drive strength feature present
- *  ^___ Pull up / bit keeper present
+ *  ^___ Pull up present
  *^^ Drive strength setting
  *   ^__ Pull up / bit keeper setting
  *  ^___ Voltage select present
  * ^ Voltage selection
  * ^ direction if enabled as GPIO (1 = output)
  *^_ initial output value if enabled as GPIO 
and configured as output
+ *   ^__ Bit keeper present
  */
 #ifndef __ASM_MACH_IOMUX_H
 #define __ASM_MACH_IOMUX_H
@@ -63,7 +64,7 @@
 
 /* control pad's pull up / bit keeper feature */
 #define PE (1  10)
-#define BK (1  11)   /* FIXME useful to distinguish? */
+#define BK (1  21)
 #define PE_PRESENT(x) (!!((x)  PE))
 #define BK_PRESENT(x) (!!((x)  BK))
 #define PULLUP(x) ((x)  13)
diff --git a/arch/arm/mach-mxs/include/mach/iomux-imx28.h 
b/arch/arm/mach-mxs/include/mach/iomux-imx28.h
index ea1c3d8..82918cf 100644
--- a/arch/arm/mach-mxs/include/mach/iomux-imx28.h
+++ b/arch/arm/mach-mxs/include/mach/iomux-imx28.h
@@ -16,7 +16,7 @@
  * ^^^__ Register Number
  *   ^^_ Function
  *  ^___ Drive strength feature present
- * ^ Pull up / bit keeper present
+ * ^ Pull up present
  *   ^^_ Drive strength setting
  *  ^___ Pull up / bit keeper setting
  * ^ Voltage select present
@@ -24,6 +24,7 @@
  *^_ direction if enabled as GPIO (1 = output)
  *   ^__ initial output value if enabled as GPIO
  *   and configured as output
+ *  ^___ Bit keeper present
  */
 #ifndef __MACH_IOMUX_IMX28_H
 #define __MACH_IOMUX_IMX28_H
@@ -57,7 +58,7 @@
 
 /* control pad's pull up / bit keeper feature */
 #define PE (1  11)
-#define BK (1  11)   /* FIXME useful to distinguish? */
+#define BK (1  22)
 #define PE_PRESENT(x) (!!((x)  PE))
 #define BK_PRESENT(x) (!!((x)  BK))
 #define PULLUP(x) ((x)  14)

-- 
Pengutronix e.K.  | Juergen Beisert |
Linux Solutions for Science and Industry  | http://www.pengutronix.de/  |

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[PATCH] ARM/Samsung: more clean up...

[Juergen Beisert]

...in preparation to add the S3C6410 SoC support.

Mostly simplifying the Samsung serial driver and some more cosmetic.

Comments are welcome.

Regards,
Juergen

The following changes since commit b47220d7f70df9191fc456dbcaeaa6ead72c6c02:

  NAND/Samsung: remove a leftover from architeture clean ups (2012-07-20 
08:41:35 +0200)

are available in the git repository at:

  git://git.pengutronix.de/git/jbe/barebox.git master_samsung_clean_up

for you to fetch changes up to fc361ff7de449f9bb8a7653a5705621320d84560:

  Samsung/serial: make the clock source configureable (2012-07-20 21:16:02 
+0200)


Juergen Beisert (9):
  ARM/Samsung: List only really supported S3C24xx SoCs
  ARM/Samsung: follow the name style of the other source files in this 
directory
  Samsung/serial: remove more ugly ifdef lines
  Samsung/serial: make the code more readable
  Samsung/serial: there is no need to ifdef these register defines
  Samsung/serial: there is no need to ifdef the slot table
  Samsung/serial: move the decision about an improved UART into Kconfig
  Samsung/serial: unify UCON register settings
  Samsung/serial: make the clock source configureable

 arch/arm/Kconfig   |2 +-
 arch/arm/mach-samsung/Kconfig  |5 ++
 arch/arm/mach-samsung/Makefile |3 +-
 .../{s3c24xx-clocks.c = clocks-s3c24xx.c} |0
 arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h  |5 +-
 drivers/serial/serial_s3c.c|   71 +++-
 6 files changed, 48 insertions(+), 38 deletions(-)
 rename arch/arm/mach-samsung/{s3c24xx-clocks.c = clocks-s3c24xx.c} (100%)


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[PATCH 9/9] Samsung/serial: make the clock source configureable

[Juergen Beisert]

Instead of taking the value from somewhere, use the selected architecture to
select one. This ensures the selected clock source corresponds to the values
setup in the clocks-*.c from the mach directory.

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 drivers/serial/serial_s3c.c |   18 --
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/serial/serial_s3c.c b/drivers/serial/serial_s3c.c
index 39680ae..53ac77f 100644
--- a/drivers/serial/serial_s3c.c
+++ b/drivers/serial/serial_s3c.c
@@ -45,11 +45,6 @@
 #define UBRDIVSLOT 0x2c/* baudrate slot generator */
 #define UINTM 0x38 /* interrupt mask register */
 
-#ifndef S3C_UART_CLKSEL
-/* Use pclk */
-# define S3C_UART_CLKSEL 0
-#endif
-
 struct s3c_uart {
void __iomem *regs;
struct console_device cdev;
@@ -57,6 +52,17 @@ struct s3c_uart {
 
 #define to_s3c_uart(c) container_of(c, struct s3c_uart, cdev)
 
+/* each architecture has a preferred reference clock for its UARTs */
+static unsigned s3c_select_arch_input_clock(void)
+{
+   /* S3C24xx: 0=2=PCLK, 1=UEXTCLK, 3=FCLK/n */
+   if (IS_ENABLED(CONFIG_ARCH_S3C24xx))
+   return 0;   /* use the internal PCLK */
+   /* S5PCxx: 0=PCLK, 1=SCLK_UART */
+   if (IS_ENABLED(CONFIG_ARCH_S5PCxx))
+   return 0;   /* use the internal PCLK */
+}
+
 static unsigned s3c_get_arch_uart_input_clock(void __iomem *base)
 {
unsigned reg = readw(base + UCON);
@@ -108,7 +114,7 @@ static int s3c_serial_init_port(struct console_device *cdev)
 * all SoCs:
 *  - enable receive and transmit mode
 */
-   writew(0x0005 | UCON_SET_CLK_SRC(S3C_UART_CLKSEL),
+   writew(0x0005 | UCON_SET_CLK_SRC(s3c_select_arch_input_clock()),
base + UCON);
 
if (IS_ENABLED(CONFIG_SAMSUNG_IMPROVED_UART))
-- 
1.7.10.4


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[PATCH 7/9] Samsung/serial: move the decision about an improved UART into Kconfig

[Juergen Beisert]

More or less just cosmetic (removing ifdefs!).

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 arch/arm/mach-samsung/Kconfig |5 +
 arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h |5 +++--
 drivers/serial/serial_s3c.c   |   16 
 3 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-samsung/Kconfig b/arch/arm/mach-samsung/Kconfig
index c60f5ed..37d1aa3 100644
--- a/arch/arm/mach-samsung/Kconfig
+++ b/arch/arm/mach-samsung/Kconfig
@@ -18,6 +18,9 @@ config ARCH_BAREBOX_MAX_BARE_INIT_SIZE
hex
default 0x1ff0 if ARCH_S5PCxx
 
+config SAMSUNG_IMPROVED_UART
+   bool
+
 if ARCH_S3C24xx
 
 config CPU_S3C2410
@@ -87,9 +90,11 @@ endif
 if ARCH_S5PCxx
 
 config CPU_S5PC110
+   select SAMSUNG_IMPROVED_UART
bool
 
 config CPU_S5PV210
+   select SAMSUNG_IMPROVED_UART
bool
 
 #choice
diff --git a/arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h 
b/arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h
index cb05527..448e3b8 100644
--- a/arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h
+++ b/arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h
@@ -45,5 +45,6 @@
 #define S3C_UART2_SIZE 0x400
 #define S3C_UART3_BASE (S3C_UART_BASE + 0x800)
 #define S3C_UART3_SIZE 0x400
-#define S3C_UART_HAS_UBRDIVSLOT
-#define S3C_UART_HAS_UINTM
+
+#define S5P_DMC0_BASE 0xF000
+#define S5P_DMC1_BASE 0xF140
diff --git a/drivers/serial/serial_s3c.c b/drivers/serial/serial_s3c.c
index 2cb2eef..01f2246 100644
--- a/drivers/serial/serial_s3c.c
+++ b/drivers/serial/serial_s3c.c
@@ -79,10 +79,11 @@ static int s3c_serial_setbaudrate(struct console_device 
*cdev, int baudrate)
void __iomem *base = priv-regs;
unsigned val;
 
-#ifdef S3C_UART_HAS_UBRDIVSLOT
-   val = s3c_get_arch_uart_input_clock(base) / baudrate;
-   writew(udivslot_table[val  15], base + UBRDIVSLOT);
-#endif
+   if (IS_ENABLED(CONFIG_SAMSUNG_IMPROVED_UART)) {
+   val = s3c_get_arch_uart_input_clock(base) / baudrate;
+   writew(udivslot_table[val  15], base + UBRDIVSLOT);
+   }
+
val = s3c_get_arch_uart_input_clock(base) / (16 * baudrate) - 1;
writew(val, base + UBRDIV);
 
@@ -106,10 +107,9 @@ static int s3c_serial_init_port(struct console_device 
*cdev)
writew(0x0245 | UCON_SET_CLK_SRC(S3C_UART_CLKSEL),
base + UCON);
 
-#ifdef S3C_UART_HAS_UINTM
-   /* 'interrupt or polling mode' for both directions */
-   writeb(0xf, base + UINTM);
-#endif
+   if (IS_ENABLED(CONFIG_SAMSUNG_IMPROVED_UART))
+   /* 'interrupt or polling mode' for both directions */
+   writeb(0xf, base + UINTM);
 
if (IS_ENABLED(CONFIG_DRIVER_SERIAL_S3C_AUTOSYNC))
writeb(0x10, base + UMCON); /* enable auto flow control */
-- 
1.7.10.4


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[PATCH] ARM/Samsung: add the vendor FriendlyARM to the board's directory name

[Juergen Beisert]

Since a look into arch/arm/boards/ offers various boards starting with the
vendor's name in their directory name (like 'eukrea' and 'freescale').
This patch does the same with the currently existing FriendlyARM boards
Mini2440 and Tiny210. More boards of this vendor will follow.

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 arch/arm/Makefile  |4 ++--
 arch/arm/boards/{mini2440 = friendlyarm-mini2440}/Kconfig |0
 arch/arm/boards/{mini2440 = friendlyarm-mini2440}/Makefile|0
 arch/arm/boards/{mini2440 = friendlyarm-mini2440}/config.h|0
 arch/arm/boards/{mini2440 = friendlyarm-mini2440}/env/config  |0
 arch/arm/boards/{mini2440 = friendlyarm-mini2440}/lowlevel_init.S |0
 arch/arm/boards/{mini2440 = friendlyarm-mini2440}/mini2440.c  |0
 arch/arm/boards/{tiny210 = friendlyarm-tiny210}/Makefile  |0
 arch/arm/boards/{tiny210 = friendlyarm-tiny210}/config.h  |0
 arch/arm/boards/{tiny210 = friendlyarm-tiny210}/lowlevel.c|0
 arch/arm/boards/{tiny210 = friendlyarm-tiny210}/tiny210.c |0
 .../configs/{mini2440_defconfig = friendlyarm_mini2440_defconfig} |2 +-
 .../configs/{tiny210_defconfig = friendlyarm_tiny210_defconfig}   |0
 arch/arm/mach-samsung/Kconfig  |2 +-
 14 files changed, 4 insertions(+), 4 deletions(-)
 rename arch/arm/boards/{mini2440 = friendlyarm-mini2440}/Kconfig (100%)
 rename arch/arm/boards/{mini2440 = friendlyarm-mini2440}/Makefile (100%)
 rename arch/arm/boards/{mini2440 = friendlyarm-mini2440}/config.h (100%)
 rename arch/arm/boards/{mini2440 = friendlyarm-mini2440}/env/config (100%)
 rename arch/arm/boards/{mini2440 = friendlyarm-mini2440}/lowlevel_init.S 
(100%)
 rename arch/arm/boards/{mini2440 = friendlyarm-mini2440}/mini2440.c (100%)
 rename arch/arm/boards/{tiny210 = friendlyarm-tiny210}/Makefile (100%)
 rename arch/arm/boards/{tiny210 = friendlyarm-tiny210}/config.h (100%)
 rename arch/arm/boards/{tiny210 = friendlyarm-tiny210}/lowlevel.c (100%)
 rename arch/arm/boards/{tiny210 = friendlyarm-tiny210}/tiny210.c (100%)
 rename arch/arm/configs/{mini2440_defconfig = friendlyarm_mini2440_defconfig} 
(92%)
 rename arch/arm/configs/{tiny210_defconfig = friendlyarm_tiny210_defconfig} 
(100%)

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 9488359..8d661a4 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -122,7 +122,7 @@ board-$(CONFIG_MACH_FREESCALE_MX51_PDK) := 
freescale-mx51-pdk
 board-$(CONFIG_MACH_FREESCALE_MX53_LOCO)   := freescale-mx53-loco
 board-$(CONFIG_MACH_FREESCALE_MX53_SMD):= freescale-mx53-smd
 board-$(CONFIG_MACH_GUF_CUPID) := guf-cupid
-board-$(CONFIG_MACH_MINI2440)  := mini2440
+board-$(CONFIG_MACH_MINI2440)  := friendlyarm-mini2440
 board-$(CONFIG_MACH_QIL_A9260) := qil-a9260
 board-$(CONFIG_MACH_TNY_A9260) := tny-a926x
 board-$(CONFIG_MACH_TNY_A9263) := tny-a926x
@@ -137,7 +137,7 @@ board-$(CONFIG_MACH_TX51)   := karo-tx51
 board-$(CONFIG_MACH_MX6Q_ARM2) := freescale-mx6-arm2
 board-$(CONFIG_MACH_TOSHIBA_AC100) := toshiba-ac100
 board-$(CONFIG_MACH_CCMX51):= ccxmx51
-board-$(CONFIG_MACH_TINY210)   := tiny210
+board-$(CONFIG_MACH_TINY210)   := friendlyarm-tiny210
 
 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
 
diff --git a/arch/arm/boards/mini2440/Kconfig 
b/arch/arm/boards/friendlyarm-mini2440/Kconfig
similarity index 100%
rename from arch/arm/boards/mini2440/Kconfig
rename to arch/arm/boards/friendlyarm-mini2440/Kconfig
diff --git a/arch/arm/boards/mini2440/Makefile 
b/arch/arm/boards/friendlyarm-mini2440/Makefile
similarity index 100%
rename from arch/arm/boards/mini2440/Makefile
rename to arch/arm/boards/friendlyarm-mini2440/Makefile
diff --git a/arch/arm/boards/mini2440/config.h 
b/arch/arm/boards/friendlyarm-mini2440/config.h
similarity index 100%
rename from arch/arm/boards/mini2440/config.h
rename to arch/arm/boards/friendlyarm-mini2440/config.h
diff --git a/arch/arm/boards/mini2440/env/config 
b/arch/arm/boards/friendlyarm-mini2440/env/config
similarity index 100%
rename from arch/arm/boards/mini2440/env/config
rename to arch/arm/boards/friendlyarm-mini2440/env/config
diff --git a/arch/arm/boards/mini2440/lowlevel_init.S 
b/arch/arm/boards/friendlyarm-mini2440/lowlevel_init.S
similarity index 100%
rename from arch/arm/boards/mini2440/lowlevel_init.S
rename to arch/arm/boards/friendlyarm-mini2440/lowlevel_init.S
diff --git a/arch/arm/boards/mini2440/mini2440.c 
b/arch/arm/boards/friendlyarm-mini2440/mini2440.c
similarity index 100%
rename from arch/arm/boards/mini2440/mini2440.c
rename to arch/arm/boards/friendlyarm-mini2440/mini2440.c
diff --git a/arch/arm/boards/tiny210/Makefile 
b/arch/arm/boards

[PATCHv5] Enable a way to provide the reason for being here

[Juergen Beisert]

Many architectures support a way to detect why the bootloader is running.
This patch adds a global variable to be able to use the cause in some kind of
shell code to do special things on demand. For example to do an emergency boot,
when the last boot fails and the watchdog reactivates the hanging system.

V2 includes Marc's suggesion.
V3 includes the detection for the i.MX28 SoC and fixes its usage for other
i.MX SoCs.
V4 includes Marc's recent suggestion.
V5 includes Sascha's comments.

Comments are still welcome.

Juergen

The following changes since commit 6e566b211351bba74d6118f983f5fcd29e78a5b6:

  Merge branch 'for-next/imx-keypad' into next (2012-07-17 20:46:17 +0200)

are available in the git repository at:

  git://git.pengutronix.de/git/jbe/barebox.git next_provide_reset_sourceV5

for you to fetch changes up to 92cc203ac2806fe0818d2aa4ad5bea04bdb4121b:

  ARM/MXS: add reset cause detection (2012-07-18 10:40:22 +0200)


Juergen Beisert (4):
  Enable a way to provide the reason for being here
  ARM/Samsung: add support to detect the reset source
  ARM/i.MX: add support to detect the reset source
  ARM/MXS: add reset cause detection

 arch/arm/mach-imx/Makefile   |1 +
 arch/arm/mach-imx/reset_source.c |   72 ++
 arch/arm/mach-samsung/Makefile   |1 +
 arch/arm/mach-samsung/reset_source.c |   56 ++
 common/Kconfig   |8 
 common/Makefile  |1 +
 common/reset_source.c|   44 +
 drivers/watchdog/im28wd.c|   25 
 include/reset_source.h   |   27 +
 9 files changed, 235 insertions(+)
 create mode 100644 arch/arm/mach-imx/reset_source.c
 create mode 100644 arch/arm/mach-samsung/reset_source.c
 create mode 100644 common/reset_source.c
 create mode 100644 include/reset_source.h

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[PATCH 3/4] ARM/i.MX: add support to detect the reset source

[Juergen Beisert]

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 arch/arm/mach-imx/Makefile   |1 +
 arch/arm/mach-imx/reset_source.c |   72 ++
 2 files changed, 73 insertions(+)
 create mode 100644 arch/arm/mach-imx/reset_source.c

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 89a8946..2ff537a 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,4 +1,5 @@
 obj-y += clocksource.o gpio.o
+obj-$(CONFIG_RESET_SOURCE) += reset_source.o
 obj-$(CONFIG_ARCH_IMX1)  += speed-imx1.o  imx1.o  iomux-v1.o
 obj-$(CONFIG_ARCH_IMX25) += speed-imx25.o imx25.o iomux-v3.o
 obj-$(CONFIG_ARCH_IMX21) += speed-imx21.o imx21.o iomux-v1.o
diff --git a/arch/arm/mach-imx/reset_source.c b/arch/arm/mach-imx/reset_source.c
new file mode 100644
index 000..e7b2a90
--- /dev/null
+++ b/arch/arm/mach-imx/reset_source.c
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2012 Juergen Beisert - ker...@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include common.h
+#include init.h
+#include io.h
+#include reset_source.h
+#include mach/imx-regs.h
+
+#ifdef CONFIG_ARCH_IMX1
+#  define IMX_RESET_SRC_WDOG (1  1)
+#  define IMX_RESET_SRC_HRDRESET (1  0)
+/* let the compiler sort out useless code on this arch */
+#  define IMX_RESET_SRC_WARMSTART 0
+#  define IMX_RESET_SRC_COLDSTART 0
+#else
+  /* WRSR checked for i.MX25, i.MX27, i.MX31, i.MX35 and i.MX51 */
+# define WDOG_WRSR 0x04
+  /* valid for i.MX25, i.MX27, i.MX31, i.MX35, i.MX51 */
+#  define IMX_RESET_SRC_WARMSTART (1  0)
+  /* valid for i.MX25, i.MX27, i.MX31, i.MX35, i.MX51 */
+#  define IMX_RESET_SRC_WDOG (1  1)
+  /* valid for i.MX27, i.MX31, always '0' on i.MX25, i.MX35, i.MX51 */
+#  define IMX_RESET_SRC_HRDRESET (1  3)
+  /* valid for i.MX27, i.MX31, always '0' on i.MX25, i.MX35, i.MX51 */
+#  define IMX_RESET_SRC_COLDSTART (1  4)
+#endif
+
+static unsigned read_detection_register(void)
+{
+#ifdef CONFIG_ARCH_IMX1
+   return readl(IMX_SYSCTRL_BASE);
+#else
+   return readw(IMX_WDT_BASE + WDOG_WRSR);
+#endif
+}
+
+static int imx_detect_reset_source(void)
+{
+   unsigned reg = read_detection_register();
+
+   if (reg  IMX_RESET_SRC_COLDSTART) {
+   set_reset_source(RESET_POR);
+   return 0;
+   }
+
+   if (reg  (IMX_RESET_SRC_HRDRESET | IMX_RESET_SRC_WARMSTART)) {
+   set_reset_source(RESET_RST);
+   return 0;
+   }
+
+   if (reg  IMX_RESET_SRC_WDOG) {
+   set_reset_source(RESET_WDG);
+   return 0;
+   }
+
+   /* else keep the default 'unknown' state */
+   return 0;
+}
+
+device_initcall(imx_detect_reset_source);
-- 
1.7.10.4


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[PATCH 1/4] Enable a way to provide the reason for being here

[Juergen Beisert]

Many architectures support a way to detect why the bootloader is running.
This patch adds a global variable to be able to use the cause in some kind of
shell code to do special things on demand. For example to do an emergency boot,
when the last boot fails and the watchdog reactivate the hanging system.

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 common/Kconfig |8 
 common/Makefile|1 +
 common/reset_source.c  |   44 
 include/reset_source.h |   27 +++
 4 files changed, 80 insertions(+)
 create mode 100644 common/reset_source.c
 create mode 100644 include/reset_source.h

diff --git a/common/Kconfig b/common/Kconfig
index 5fe997d..9652e5d 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -554,6 +554,14 @@ config BAREBOXENV_TARGET
 config POLLER
bool generic polling infrastructure
 
+config RESET_SOURCE
+   bool detect Reset cause
+   depends on GLOBALVAR
+   help
+ Provide a global variable at runtine which reflects the possible cause
+ of the reset and why the bootloader is currently running. It can be
+ useful for any kind of system recovery or repair.
+
 endmenu
 
 menu Debugging 
diff --git a/common/Makefile b/common/Makefile
index d99dfa2..d74dffb 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -30,6 +30,7 @@ obj-y += startup.o
 obj-y += misc.o
 obj-y += memsize.o
 obj-$(CONFIG_GLOBALVAR) += globalvar.o
+obj-$(CONFIG_RESET_SOURCE) += reset_source.o
 obj-$(CONFIG_FILETYPE) += filetype.o
 obj-y += resource.o
 obj-$(CONFIG_MENU) += menu.o
diff --git a/common/reset_source.c b/common/reset_source.c
new file mode 100644
index 000..2a7f9ff
--- /dev/null
+++ b/common/reset_source.c
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2012 Juergen Beisert - ker...@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include common.h
+#include init.h
+#include environment.h
+#include globalvar.h
+#include reset_source.h
+
+static const char * const reset_src_names[] = {
+   [RESET_UKWN] = unknown,
+   [RESET_POR] = POR,
+   [RESET_RST] = RST,
+   [RESET_WDG] = WDG,
+   [RESET_WKE] = WKE,
+   [RESET_JTAG] = JTAG,
+};
+
+void set_reset_source(enum reset_src_type st)
+{
+   setenv(global.system.reset, reset_src_names[st]);
+}
+EXPORT_SYMBOL(set_reset_source);
+
+/* ensure this runs after the 'global' device is already registerd */
+static int init_reset_source(void)
+{
+   globalvar_add_simple(system.reset);
+   set_reset_source(RESET_UKWN);
+   return 0;
+}
+
+coredevice_initcall(init_reset_source);
diff --git a/include/reset_source.h b/include/reset_source.h
new file mode 100644
index 000..6734fbde
--- /dev/null
+++ b/include/reset_source.h
@@ -0,0 +1,27 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __INCLUDE_RESET_SOURCE_H
+# define __INCLUDE_RESET_SOURCE_H
+
+enum reset_src_type {
+   RESET_UKWN, /* maybe the SoC cannot detect the reset source */
+   RESET_POR,  /* Power On Reset (cold start) */
+   RESET_RST,  /* generic ReSeT (warm start) */
+   RESET_WDG,  /* watchdog */
+   RESET_WKE,  /* wake-up (some SoCs can handle this) */
+   RESET_JTAG, /* JTAG reset */
+};
+
+void set_reset_source(enum reset_src_type);
+
+#endif /* __INCLUDE_RESET_SOURCE_H */
-- 
1.7.10.4


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[PATCH 2/4] ARM/Samsung: add support to detect the reset source

[Juergen Beisert]

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 arch/arm/mach-samsung/Makefile   |1 +
 arch/arm/mach-samsung/reset_source.c |   56 ++
 2 files changed, 57 insertions(+)
 create mode 100644 arch/arm/mach-samsung/reset_source.c

diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
index 6020587..f7db1f7 100644
--- a/arch/arm/mach-samsung/Makefile
+++ b/arch/arm/mach-samsung/Makefile
@@ -1,4 +1,5 @@
 obj-y += s3c-timer.o generic.o
+obj-$(CONFIG_RESET_SOURCE) += reset_source.o
 obj-lowlevel-$(CONFIG_ARCH_S3C24xx) += lowlevel-s3c24x0.o
 obj-lowlevel-$(CONFIG_ARCH_S5PCxx) += lowlevel-s5pcxx.o
 obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o s3c24xx-clocks.o mem-s3c24x0.o
diff --git a/arch/arm/mach-samsung/reset_source.c 
b/arch/arm/mach-samsung/reset_source.c
new file mode 100644
index 000..2456e3f
--- /dev/null
+++ b/arch/arm/mach-samsung/reset_source.c
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2012 Juergen Beisert - ker...@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include common.h
+#include init.h
+#include io.h
+#include reset_source.h
+#include mach/s3c-iomap.h
+
+/* S3C2440 relevant */
+#define S3C2440_GSTATUS2 0xb4
+# define S3C2440_GSTATUS2_PWRST (1  0)
+# define S3C2440_GSTATUS2_SLEEPRST (1  1)
+# define S3C2440_GSTATUS2_WDRST (1  2)
+
+static int s3c_detect_reset_source(void)
+{
+   u32 reg = readl(S3C_GPIO_BASE + S3C2440_GSTATUS2);
+
+   if (reg  S3C2440_GSTATUS2_PWRST) {
+   set_reset_source(RESET_POR);
+   writel(S3C2440_GSTATUS2_PWRST,
+   S3C_GPIO_BASE + S3C2440_GSTATUS2);
+   return 0;
+   }
+
+   if (reg  S3C2440_GSTATUS2_SLEEPRST) {
+   set_reset_source(RESET_WKE);
+   writel(S3C2440_GSTATUS2_SLEEPRST,
+   S3C_GPIO_BASE + S3C2440_GSTATUS2);
+   return 0;
+   }
+
+   if (reg  S3C2440_GSTATUS2_WDRST) {
+   set_reset_source(RESET_WDG);
+   writel(S3C2440_GSTATUS2_WDRST,
+   S3C_GPIO_BASE + S3C2440_GSTATUS2);
+   return 0;
+   }
+
+   /* else keep the default 'unknown' state */
+   return 0;
+}
+
+device_initcall(s3c_detect_reset_source);
-- 
1.7.10.4


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Board's naming style

[Juergen Beisert]

Hi,

a look into arch/arm/boards/ offers various boards starting with the 
vendor's name in their directory name (eukrea/freescale).
I would like to have the same for the FriendlyARM boards. Currently the 
Mini2440 and Tiny210 are part of the tree and I'm still working on the 
Mini6410 and Tiny6410 inclusion. Can we rename the currently existing 
Mini2440 and Tiny210 to friendlyarm-mini2440 and friendlyarm-tiny210?

@Sascha: Do you need a patch for this?

Regards,
Juergen

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Re: [PATCH 02/18] ARM/Samsung: unify device registration for the S3C24XX SoCs

[Juergen Beisert]

Sascha Hauer wrote:
 On Fri, Jul 13, 2012 at 09:00:54PM +0200, Juergen Beisert wrote:
  Barebox crashes since it has trouble with a resource size of 0. Most of
  the S3C24XX based platforms crashes at runtime and can't use devices with
  resource sizes of 0 anymore. This patch fix it by unifying the device
  registration for all current Barebox's S3C24XX based platforms.
 
  - A9M2410 and A9M2440 compile time tested only.
  - Mini2440 also runtime tested.

 So this is stuff for master, right?

Hmm, yes. :)

jbe

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Vertretung Sued/Muenchen, Germany | Fax:   +49-5121-206917- |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de/  |

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[PATCH 2/4] ARM/Samsung: add support to detect the reset source

[Juergen Beisert]

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 arch/arm/mach-samsung/Makefile   |1 +
 arch/arm/mach-samsung/reset_source.c |   56 ++
 2 files changed, 57 insertions(+)
 create mode 100644 arch/arm/mach-samsung/reset_source.c

diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
index 6020587..5ac8e3c 100644
--- a/arch/arm/mach-samsung/Makefile
+++ b/arch/arm/mach-samsung/Makefile
@@ -1,4 +1,5 @@
 obj-y += s3c-timer.o generic.o
+obj-$(CONFIG_GLOBALVAR) += reset_source.o
 obj-lowlevel-$(CONFIG_ARCH_S3C24xx) += lowlevel-s3c24x0.o
 obj-lowlevel-$(CONFIG_ARCH_S5PCxx) += lowlevel-s5pcxx.o
 obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o s3c24xx-clocks.o mem-s3c24x0.o
diff --git a/arch/arm/mach-samsung/reset_source.c 
b/arch/arm/mach-samsung/reset_source.c
new file mode 100644
index 000..2456e3f
--- /dev/null
+++ b/arch/arm/mach-samsung/reset_source.c
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2012 Juergen Beisert - ker...@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include common.h
+#include init.h
+#include io.h
+#include reset_source.h
+#include mach/s3c-iomap.h
+
+/* S3C2440 relevant */
+#define S3C2440_GSTATUS2 0xb4
+# define S3C2440_GSTATUS2_PWRST (1  0)
+# define S3C2440_GSTATUS2_SLEEPRST (1  1)
+# define S3C2440_GSTATUS2_WDRST (1  2)
+
+static int s3c_detect_reset_source(void)
+{
+   u32 reg = readl(S3C_GPIO_BASE + S3C2440_GSTATUS2);
+
+   if (reg  S3C2440_GSTATUS2_PWRST) {
+   set_reset_source(RESET_POR);
+   writel(S3C2440_GSTATUS2_PWRST,
+   S3C_GPIO_BASE + S3C2440_GSTATUS2);
+   return 0;
+   }
+
+   if (reg  S3C2440_GSTATUS2_SLEEPRST) {
+   set_reset_source(RESET_WKE);
+   writel(S3C2440_GSTATUS2_SLEEPRST,
+   S3C_GPIO_BASE + S3C2440_GSTATUS2);
+   return 0;
+   }
+
+   if (reg  S3C2440_GSTATUS2_WDRST) {
+   set_reset_source(RESET_WDG);
+   writel(S3C2440_GSTATUS2_WDRST,
+   S3C_GPIO_BASE + S3C2440_GSTATUS2);
+   return 0;
+   }
+
+   /* else keep the default 'unknown' state */
+   return 0;
+}
+
+device_initcall(s3c_detect_reset_source);
-- 
1.7.10.4


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[PATCH 4/4] ARM/MXS: add reset cause detection

[Juergen Beisert]

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 drivers/watchdog/im28wd.c |   25 +
 1 file changed, 25 insertions(+)

diff --git a/drivers/watchdog/im28wd.c b/drivers/watchdog/im28wd.c
index b016910..eb6099a 100644
--- a/drivers/watchdog/im28wd.c
+++ b/drivers/watchdog/im28wd.c
@@ -21,6 +21,7 @@
 #include errno.h
 #include malloc.h
 #include watchdog.h
+#include reset_source.h
 
 #define MXS_RTC_CTRL 0x0
 #define MXS_RTC_SET_ADDR 0x4
@@ -73,6 +74,27 @@ static int imx28_watchdog_set_timeout(struct watchdog *wd, 
unsigned timeout)
return 0;
 }
 
+static void __maybe_unused imx28_detect_reset_source(const struct imx28_wd *p)
+{
+   u32 reg;
+
+   reg = readl(p-regs + MXS_RTC_PERSISTENT0);
+   if (reg  MXS_RTC_PERSISTENT0_EXT_RST) {
+   writel(MXS_RTC_PERSISTENT0_EXT_RST,
+   p-regs + MXS_RTC_PERSISTENT0 + MXS_RTC_CLR_ADDR);
+   set_reset_source(RESET_POR);
+   return;
+   }
+   if (reg  MXS_RTC_PERSISTENT0_THM_RST) {
+   writel(MXS_RTC_PERSISTENT0_THM_RST,
+   p-regs + MXS_RTC_PERSISTENT0 + MXS_RTC_CLR_ADDR);
+   set_reset_source(RESET_RST);
+   return;
+   }
+
+   set_reset_source(RESET_RST);
+}
+
 static int imx28_wd_probe(struct device_d *dev)
 {
struct imx28_wd *priv;
@@ -94,6 +116,9 @@ static int imx28_wd_probe(struct device_d *dev)
if (rc != 0)
goto on_error;
 
+   if (IS_ENABLED(CONFIG_GLOBALVAR))
+   imx28_detect_reset_source(priv);
+
dev-priv = priv;
return 0;
 
-- 
1.7.10.4


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[PATCHv4] Enable a way to provide the reason for being here

[Juergen Beisert]

Many architectures support a way to detect why the bootloader is running.
This patch adds a global variable to be able to use the cause in some kind of
shell code to do special things on demand. For example to do an emergency boot,
when the last boot fails and the watchdog reactivates the hanging system.

V2 includes Marc's suggesion.
V3 includes the detection for the i.MX28 SoC and fixes its usage for other
i.MX SoCs.
V4 includes Marc's recent suggestion.

Comments are still welcome.

Juergen

The following changes since commit 279d3c29437ff84d4542ba4fc81de4fff0381233:

  Merge branch 'for-next/tqma53' into next (2012-07-09 09:24:04 +0200)

are available in the git repository at:

  git://git.pengutronix.de/git/jbe/barebox.git next_provide_reset_sourceV4

for you to fetch changes up to 8a94e229a42fad93f5cb5ff2b4b1cbe8e85e2927:

  ARM/MXS: add reset cause detection (2012-07-13 07:36:00 +0200)


Juergen Beisert (4):
  Enable a way to provide the reason for being here
  ARM/Samsung: add support to detect the reset source
  ARM/i.MX: add support to detect the reset source
  ARM/MXS: add reset cause detection

 arch/arm/mach-imx/Makefile   |1 +
 arch/arm/mach-imx/reset_source.c |   72 ++
 arch/arm/mach-samsung/Makefile   |1 +
 arch/arm/mach-samsung/reset_source.c |   56 ++
 common/Makefile  |2 +-
 common/reset_source.c|   44 +
 drivers/watchdog/im28wd.c|   25 
 include/reset_source.h   |   27 +
 8 files changed, 227 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-imx/reset_source.c
 create mode 100644 arch/arm/mach-samsung/reset_source.c
 create mode 100644 common/reset_source.c
 create mode 100644 include/reset_source.h

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[PATCH 1/4] Enable a way to provide the reason for being here

[Juergen Beisert]

Many architectures support a way to detect why the bootloader is running.
This patch adds a global variable to be able to use the cause in some kind of
shell code to do special things on demand. For example to do an emergency boot,
when the last boot fails and the watchdog reactivate the hanging system.

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 common/Makefile|2 +-
 common/reset_source.c  |   44 
 include/reset_source.h |   27 +++
 3 files changed, 72 insertions(+), 1 deletion(-)
 create mode 100644 common/reset_source.c
 create mode 100644 include/reset_source.h

diff --git a/common/Makefile b/common/Makefile
index d99dfa2..baf4539 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -29,7 +29,7 @@ obj-$(CONFIG_UIMAGE) += uimage.o
 obj-y += startup.o
 obj-y += misc.o
 obj-y += memsize.o
-obj-$(CONFIG_GLOBALVAR) += globalvar.o
+obj-$(CONFIG_GLOBALVAR) += globalvar.o reset_source.o
 obj-$(CONFIG_FILETYPE) += filetype.o
 obj-y += resource.o
 obj-$(CONFIG_MENU) += menu.o
diff --git a/common/reset_source.c b/common/reset_source.c
new file mode 100644
index 000..2a7f9ff
--- /dev/null
+++ b/common/reset_source.c
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2012 Juergen Beisert - ker...@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include common.h
+#include init.h
+#include environment.h
+#include globalvar.h
+#include reset_source.h
+
+static const char * const reset_src_names[] = {
+   [RESET_UKWN] = unknown,
+   [RESET_POR] = POR,
+   [RESET_RST] = RST,
+   [RESET_WDG] = WDG,
+   [RESET_WKE] = WKE,
+   [RESET_JTAG] = JTAG,
+};
+
+void set_reset_source(enum reset_src_type st)
+{
+   setenv(global.system.reset, reset_src_names[st]);
+}
+EXPORT_SYMBOL(set_reset_source);
+
+/* ensure this runs after the 'global' device is already registerd */
+static int init_reset_source(void)
+{
+   globalvar_add_simple(system.reset);
+   set_reset_source(RESET_UKWN);
+   return 0;
+}
+
+coredevice_initcall(init_reset_source);
diff --git a/include/reset_source.h b/include/reset_source.h
new file mode 100644
index 000..8bb366c
--- /dev/null
+++ b/include/reset_source.h
@@ -0,0 +1,27 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __INCLUDE_RESET_SOURCE_H
+# define __INCLUDE_RESET_SOURCE_H
+
+enum reset_src_type {
+   RESET_UKWN, /* maybe the SoC cannot detect the reset source */
+   RESET_POR,  /* Power On Reset (cold start) */
+   RESET_RST,  /* generic ReSeT (warm start) */
+   RESET_WDG,  /* watchdog */
+   RESET_WKE,  /* wake-up (some SoCs can handle this) */
+   RESET_JTAG, /* JTAG reset */
+};
+
+extern void set_reset_source(enum reset_src_type);
+
+#endif /* __INCLUDE_RESET_SOURCE_H */
-- 
1.7.10.4


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[PATCH 06/18] Samsung/serial: make the code more readable

[Juergen Beisert]

This bit magic is just setting and reading the UART's selected clock source.

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 drivers/serial/serial_s3c.c |8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/serial/serial_s3c.c b/drivers/serial/serial_s3c.c
index 5c05ba8..a4c1f68 100644
--- a/drivers/serial/serial_s3c.c
+++ b/drivers/serial/serial_s3c.c
@@ -31,6 +31,8 @@
 /* Note: Offsets are for little endian access */
 #define ULCON 0x00 /* line control */
 #define UCON 0x04  /* UART control */
+# define UCON_SET_CLK_SRC(x) (((x)  0x03)  10)
+# define UCON_GET_CLK_SRC(x) (((x)  10)  0x03)
 #define UFCON 0x08 /* FIFO control */
 #define UMCON 0x0c /* modem control */
 #define UTRSTAT 0x10   /* Rx/Tx status */
@@ -57,8 +59,7 @@ struct s3c_uart {
 static unsigned s3c_get_arch_uart_input_clock(void __iomem *base)
 {
unsigned reg = readw(base + UCON);
-   reg = (reg  10)  0x3;
-   return s3c_get_uart_clk(reg);
+   return s3c_get_uart_clk(UCON_GET_CLK_SRC(reg));
 }
 
 #ifdef S3C_UART_HAS_UBRDIVSLOT
@@ -103,7 +104,8 @@ static int s3c_serial_init_port(struct console_device *cdev)
 
/* tx=level,rx=edge,disable timeout int.,enable rx error int.,
 * normal, interrupt or polling, no pre-divider */
-   writew(0x0245 | ((CONFIG_DRIVER_SERIAL_S3C_CLK)  10), base + UCON);
+   writew(0x0245 | UCON_SET_CLK_SRC(CONFIG_DRIVER_SERIAL_S3C_CLK),
+   base + UCON);
 
 #ifdef S3C_UART_HAS_UINTM
/* 'interrupt or polling mode' for both directions */
-- 
1.7.10.4


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[PATCH 05/18] Samsung/serial: make the clock source configureable

[Juergen Beisert]

Instead of taking the value from somewhere, use the menu to select one. Also
provide sane default values for known SoCs.

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 drivers/serial/Kconfig  |   12 
 drivers/serial/serial_s3c.c |7 +--
 2 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index a9383da..a118aaf 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -85,6 +85,18 @@ config DRIVER_SERIAL_S3C
help
  Say Y here if you want to use the CONS on a Samsung S3C CPU
 
+config DRIVER_SERIAL_S3C_CLK
+   int
+   prompt input clock reference
+   depends on DRIVER_SERIAL_S3C
+   default 0 if ARCH_S3C24xx
+   default 3 if ARCH_S5PCxx
+   help
+ Select one of up to four available clock sources for the UART:
+  0+1: PCLK, 2: UCLK0, 3: UCLK1
+ Note: not all values are possible on all Samsung SoCs. Read the
+ manual if unsure.
+
 config DRIVER_SERIAL_S3C_AUTOSYNC
bool Enable auto flow
depends on DRIVER_SERIAL_S3C
diff --git a/drivers/serial/serial_s3c.c b/drivers/serial/serial_s3c.c
index ff3792b..5c05ba8 100644
--- a/drivers/serial/serial_s3c.c
+++ b/drivers/serial/serial_s3c.c
@@ -47,11 +47,6 @@
 # define UINTM 0x38/* interrupt mask register */
 #endif
 
-#ifndef S3C_UART_CLKSEL
-/* Use pclk */
-# define S3C_UART_CLKSEL 0
-#endif
-
 struct s3c_uart {
void __iomem *regs;
struct console_device cdev;
@@ -108,7 +103,7 @@ static int s3c_serial_init_port(struct console_device *cdev)
 
/* tx=level,rx=edge,disable timeout int.,enable rx error int.,
 * normal, interrupt or polling, no pre-divider */
-   writew(0x0245 | ((S3C_UART_CLKSEL)  10), base + UCON);
+   writew(0x0245 | ((CONFIG_DRIVER_SERIAL_S3C_CLK)  10), base + UCON);
 
 #ifdef S3C_UART_HAS_UINTM
/* 'interrupt or polling mode' for both directions */
-- 
1.7.10.4


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[PATCH 04/18] Samsung/serial: remove more ugly ifdef lines

[Juergen Beisert]

More or less just cosmetic. Easier to read, and lets the compiler remove unused
code.

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 drivers/serial/serial_s3c.c |9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/serial/serial_s3c.c b/drivers/serial/serial_s3c.c
index 7a9b355..ff3792b 100644
--- a/drivers/serial/serial_s3c.c
+++ b/drivers/serial/serial_s3c.c
@@ -115,11 +115,10 @@ static int s3c_serial_init_port(struct console_device 
*cdev)
writeb(0xf, base + UINTM);
 #endif
 
-#ifdef CONFIG_DRIVER_SERIAL_S3C_AUTOSYNC
-   writeb(0x10, base + UMCON); /* enable auto flow control */
-#else
-   writeb(0x01, base + UMCON); /* RTS up */
-#endif
+   if (IS_ENABLED(CONFIG_DRIVER_SERIAL_S3C_AUTOSYNC))
+   writeb(0x10, base + UMCON); /* enable auto flow control */
+   else
+   writeb(0x01, base + UMCON); /* RTS up */
 
return 0;
 }
-- 
1.7.10.4


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[RFC] Inclusion of the Samsung S3C6410 SoC

[Juergen Beisert]

This patch series tries to include the Samsung S3C6410 processor into Barebox.
This SoC is used on the popular FriendlyARM Mini6410 platform and an
implementation for this platfrom is part of this series. This series is WIP,
so please comment if the changes are ready for mainline or not.

Patches 1..3 prepare the current Samsung part of Barebox to simplify the
changes later on.
Patches 4..10 just change the Samsung UART driver to make it more generic for
all current Samsung SoCs.
Patches 11..17 add the new Samsung S3C6410 SoC support.
Patch 18 adds the Mini6410 platform to make use of all the previous changes.

At least these changes should be tested on the S5Pxx SoCs, as I'm not sure if
the UART driver still works for them.

Regards,
Juergen


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[PATCH 01/18] ARM/Samsung: be able to include the nand header multiple times

[Juergen Beisert]

This is required in preparation for the following patches.

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 arch/arm/mach-samsung/include/mach/s3c24xx-nand.h |5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h 
b/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h
index acd78b8..fa88da1 100644
--- a/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h
+++ b/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h
@@ -18,6 +18,9 @@
  *
  */
 
+#ifndef MACH_S3C24XX_NAND_H
+# define MACH_S3C24XX_NAND_H
+
 #ifdef CONFIG_S3C_NAND_BOOT
 extern void s3c24x0_nand_load_image(void*, int, int);
 #endif
@@ -52,3 +55,5 @@ struct s3c24x0_nand_platform_data {
  * @file
  * @brief Basic declaration to use the s3c24x0 NAND driver
  */
+
+#endif /* MACH_S3C24XX_NAND_H */
-- 
1.7.10.4


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[PATCH 11/18] ARM/Samsung: add generic lowlevel init

[Juergen Beisert]

Just a placeholder for some required low level routines
---
 arch/arm/mach-samsung/Makefile   |1 +
 arch/arm/mach-samsung/lowlevel-s3c64xx.c |   14 ++
 2 files changed, 15 insertions(+)
 create mode 100644 arch/arm/mach-samsung/lowlevel-s3c64xx.c

diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
index 091b600..ac34d86 100644
--- a/arch/arm/mach-samsung/Makefile
+++ b/arch/arm/mach-samsung/Makefile
@@ -1,5 +1,6 @@
 obj-y += s3c-timer.o generic.o
 obj-lowlevel-$(CONFIG_ARCH_S3C24xx) += lowlevel-s3c24x0.o
+obj-lowlevel-$(CONFIG_ARCH_S3C64xx) += lowlevel-s3c64x0.o
 obj-lowlevel-$(CONFIG_ARCH_S5PCxx) += lowlevel-s5pcxx.o
 obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o clocks-s3c24xx.o mem-s3c24x0.o
 obj-$(CONFIG_ARCH_S5PCxx) += gpio-s5pcxx.o clocks-s5pcxx.o mem-s5pcxx.o
diff --git a/arch/arm/mach-samsung/lowlevel-s3c64xx.c 
b/arch/arm/mach-samsung/lowlevel-s3c64xx.c
new file mode 100644
index 000..b1ba719
--- /dev/null
+++ b/arch/arm/mach-samsung/lowlevel-s3c64xx.c
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2012 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
-- 
1.7.10.4


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[PATCH 10/18] Samsung/serial: unify UCON register settings

[Juergen Beisert]

This should work on S3C24XX and S3C64XX SoCs.

Tested at runtime on a Mini2440 and Mini6410.

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 drivers/serial/serial_s3c.c |   10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/serial/serial_s3c.c b/drivers/serial/serial_s3c.c
index 8736f0b..dc28dd6 100644
--- a/drivers/serial/serial_s3c.c
+++ b/drivers/serial/serial_s3c.c
@@ -97,9 +97,13 @@ static int s3c_serial_init_port(struct console_device *cdev)
/* Normal,No parity,1 stop,8 bit */
writeb(0x03, base + ULCON);
 
-   /* tx=level,rx=edge,disable timeout int.,enable rx error int.,
-* normal, interrupt or polling, no pre-divider */
-   writew(0x0245 | UCON_SET_CLK_SRC(CONFIG_DRIVER_SERIAL_S3C_CLK),
+   /*
+* S3C2440 SoC:
+*  - no clock divider
+* all SoCs:
+*  - enable receive and transmit mode
+*/
+   writew(0x0005 | UCON_SET_CLK_SRC(CONFIG_DRIVER_SERIAL_S3C_CLK),
base + UCON);
 
if (IS_ENABLED(CONFIG_SAMSUNG_IMPROVED_UART))
-- 
1.7.10.4


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[PATCH 02/18] ARM/Samsung: unify device registration for the S3C24XX SoCs

[Juergen Beisert]

Barebox crashes since it has trouble with a resource size of 0. Most of the
S3C24XX based platforms crashes at runtime and can't use devices with resource
sizes of 0 anymore. This patch fix it by unifying the device registration for
all current Barebox's S3C24XX based platforms.

- A9M2410 and A9M2440 compile time tested only.
- Mini2440 also runtime tested.

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 arch/arm/boards/a9m2410/a9m2410.c  |6 +--
 arch/arm/boards/a9m2440/a9m2440.c  |7 ++-
 arch/arm/boards/mini2440/mini2440.c|   16 +++---
 .../mach-samsung/include/mach/devices-s3c24xx.h|   54 
 4 files changed, 65 insertions(+), 18 deletions(-)
 create mode 100644 arch/arm/mach-samsung/include/mach/devices-s3c24xx.h

diff --git a/arch/arm/boards/a9m2410/a9m2410.c 
b/arch/arm/boards/a9m2410/a9m2410.c
index eaafdbd..c2d4b87 100644
--- a/arch/arm/boards/a9m2410/a9m2410.c
+++ b/arch/arm/boards/a9m2410/a9m2410.c
@@ -32,6 +32,7 @@
 #include partition.h
 #include nand.h
 #include io.h
+#include mach/devices-s3c24xx.h
 #include mach/s3c-iomap.h
 #include mach/s3c24xx-nand.h
 #include mach/s3c-generic.h
@@ -109,8 +110,7 @@ static int a9m2410_devices_init(void)
writel(reg, S3C_MISCCR);
 
/* --- the devices the boot loader should work with  */
-   add_generic_device(s3c24x0_nand, DEVICE_ID_DYNAMIC, NULL, 
S3C24X0_NAND_BASE,
-   0, IORESOURCE_MEM, nand_info);
+   s3c24xx_add_nand(nand_info);
/*
 * SMSC 91C111 network controller on the baseboard
 * connected to CS line 1 and interrupt line
@@ -145,8 +145,6 @@ void __bare_init nand_boot(void)
 
 static int a9m2410_console_init(void)
 {
-   add_generic_device(s3c_serial, DEVICE_ID_DYNAMIC, NULL, 
S3C_UART1_BASE,
-   S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
return 0;
 }
 
diff --git a/arch/arm/boards/a9m2440/a9m2440.c 
b/arch/arm/boards/a9m2440/a9m2440.c
index 1d20248..8975c15 100644
--- a/arch/arm/boards/a9m2440/a9m2440.c
+++ b/arch/arm/boards/a9m2440/a9m2440.c
@@ -32,6 +32,7 @@
 #include partition.h
 #include nand.h
 #include io.h
+#include mach/devices-s3c24xx.h
 #include mach/s3c-iomap.h
 #include mach/s3c24xx-nand.h
 #include mach/s3c-generic.h
@@ -129,8 +130,7 @@ static int a9m2440_devices_init(void)
writel(reg, S3C_MISCCR);
 
/* --- the devices the boot loader should work with  */
-   add_generic_device(s3c24x0_nand, DEVICE_ID_DYNAMIC, NULL, 
S3C24X0_NAND_BASE, 0,
-  IORESOURCE_MEM, nand_info);
+   s3c24xx_add_nand(nand_info);
/*
 * cs8900 network controller onboard
 * Connected to CS line 5 + A24 and interrupt line EINT9,
@@ -164,8 +164,7 @@ void __bare_init nand_boot(void)
 
 static int a9m2440_console_init(void)
 {
-   add_generic_device(s3c_serial, DEVICE_ID_DYNAMIC, NULL, 
S3C_UART1_BASE,
-   S3C_UART1_SIZE, IORESOURCE_MEM, NULL);
+   s3c24xx_add_uart1();
return 0;
 }
 
diff --git a/arch/arm/boards/mini2440/mini2440.c 
b/arch/arm/boards/mini2440/mini2440.c
index 3d3b820..3523949 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -39,6 +39,7 @@
 #include io.h
 #include mach/gpio.h
 #include mach/s3c-iomap.h
+#include mach/devices-s3c24xx.h
 #include mach/s3c24xx-nand.h
 #include mach/s3c-generic.h
 #include mach/s3c-mci.h
@@ -297,8 +298,7 @@ static int mini2440_devices_init(void)
reg |= 0x1;
writel(reg, S3C_MISCCR);
 
-   add_generic_device(s3c24x0_nand, DEVICE_ID_DYNAMIC, NULL, 
S3C24X0_NAND_BASE,
-   0, IORESOURCE_MEM, nand_info);
+   s3c24xx_add_nand(nand_info);
 
add_dm9000_device(0, S3C_CS4_BASE + 0x300, S3C_CS4_BASE + 0x304,
  IORESOURCE_MEM_16BIT, dm9000_data);
@@ -312,12 +312,9 @@ static int mini2440_devices_init(void)
devfs_add_partition(nand0, 0x4, 0x2, DEVFS_PARTITION_FIXED, 
env_raw);
dev_add_bb_dev(env_raw, env0);
 #endif
-   add_generic_device(s3c_mci, 0, NULL, S3C2410_SDI_BASE, 0,
-  IORESOURCE_MEM, mci_data);
-   add_generic_device(s3c_fb, 0, NULL, S3C2410_LCD_BASE, 0,
-  IORESOURCE_MEM, s3c24x0_fb_data);
-   add_generic_device(ohci, 0, NULL, S3C2410_USB_HOST_BASE, 0x100,
-  IORESOURCE_MEM, NULL);
+   s3c24xx_add_mci(mci_data);
+   s3c24xx_add_fb(s3c24x0_fb_data);
+   s3c24xx_add_ohci();
armlinux_set_bootparams((void*)S3C_SDRAM_BASE + 0x100);
armlinux_set_architecture(MACH_TYPE_MINI2440);
 
@@ -344,8 +341,7 @@ static int mini2440_console_init(void)
s3c_gpio_mode(GPH2_TXD0);
s3c_gpio_mode(GPH3_RXD0);
 
-   add_generic_device(s3c_serial, DEVICE_ID_DYNAMIC, NULL, 
S3C_UART1_BASE,
-   S3C_UART1_SIZE, IORESOURCE_MEM, NULL

[PATCH 17/18] ARM/Samsung: add the S3C6410 SoC

[Juergen Beisert]

After adding the base support, the CPU can now be enabled in the build system.

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 arch/arm/Kconfig  |6 ++
 arch/arm/mach-samsung/Kconfig |   21 -
 drivers/serial/Kconfig|2 +-
 3 files changed, 27 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9590db9..2e79005 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -81,6 +81,12 @@ config ARCH_S3C24xx
 #  select CPU_V7
 #  select GENERIC_GPIO
 
+config ARCH_S3C64xx
+   bool Samsung S3C64xx
+   select ARCH_SAMSUNG
+   select CPU_V6
+   select GENERIC_GPIO
+
 config ARCH_VERSATILE
bool ARM Versatile boards (ARM926EJ-S)
select CPU_ARM926T
diff --git a/arch/arm/mach-samsung/Kconfig b/arch/arm/mach-samsung/Kconfig
index 28bbc97..8acb7c9 100644
--- a/arch/arm/mach-samsung/Kconfig
+++ b/arch/arm/mach-samsung/Kconfig
@@ -19,6 +19,8 @@ config BOARDINFO
 config ARCH_BAREBOX_MAX_BARE_INIT_SIZE
hex
default 0x1ff0 if ARCH_S5PCxx
+# TODO
+   default 0x2000 if ARCH_S3C64xx
 
 config SAMSUNG_IMPROVED_UART
bool
@@ -89,6 +91,24 @@ endmenu
 
 endif
 
+if ARCH_S3C64xx
+
+config CPU_S3C6410
+   select SAMSUNG_IMPROVED_UART
+   bool
+
+choice
+
+   prompt S3C64xx Board Type
+
+endchoice
+
+menu Board specific settings   
+
+endmenu
+
+endif
+
 if ARCH_S5PCxx
 
 config CPU_S5PC110
@@ -114,7 +134,6 @@ endchoice
 
 endif
 
-
 menu S3C Features  
 
 config S3C_LOWLEVEL_INIT
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index a118aaf..283573e 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -90,7 +90,7 @@ config DRIVER_SERIAL_S3C_CLK
prompt input clock reference
depends on DRIVER_SERIAL_S3C
default 0 if ARCH_S3C24xx
-   default 3 if ARCH_S5PCxx
+   default 3 if ARCH_S3C64xx || ARCH_S5PCxx
help
  Select one of up to four available clock sources for the UART:
   0+1: PCLK, 2: UCLK0, 3: UCLK1
-- 
1.7.10.4


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[PATCH 09/18] Samsung/serial: move the decision about an improved UART into Kconfig

[Juergen Beisert]

More or less just cosmetic (removing ifdefs!).

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 arch/arm/mach-samsung/Kconfig |5 +
 arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h |2 --
 drivers/serial/serial_s3c.c   |   16 
 3 files changed, 13 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-samsung/Kconfig b/arch/arm/mach-samsung/Kconfig
index 90cda30..28bbc97 100644
--- a/arch/arm/mach-samsung/Kconfig
+++ b/arch/arm/mach-samsung/Kconfig
@@ -20,6 +20,9 @@ config ARCH_BAREBOX_MAX_BARE_INIT_SIZE
hex
default 0x1ff0 if ARCH_S5PCxx
 
+config SAMSUNG_IMPROVED_UART
+   bool
+
 if ARCH_S3C24xx
 
 config CPU_S3C2410
@@ -89,9 +92,11 @@ endif
 if ARCH_S5PCxx
 
 config CPU_S5PC110
+   select SAMSUNG_IMPROVED_UART
bool
 
 config CPU_S5PV210
+   select SAMSUNG_IMPROVED_UART
bool
 
 choice
diff --git a/arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h 
b/arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h
index 248f868..448e3b8 100644
--- a/arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h
+++ b/arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h
@@ -45,8 +45,6 @@
 #define S3C_UART2_SIZE 0x400
 #define S3C_UART3_BASE (S3C_UART_BASE + 0x800)
 #define S3C_UART3_SIZE 0x400
-#define S3C_UART_HAS_UBRDIVSLOT
-#define S3C_UART_HAS_UINTM
 
 #define S5P_DMC0_BASE 0xF000
 #define S5P_DMC1_BASE 0xF140
diff --git a/drivers/serial/serial_s3c.c b/drivers/serial/serial_s3c.c
index a2b8e56..8736f0b 100644
--- a/drivers/serial/serial_s3c.c
+++ b/drivers/serial/serial_s3c.c
@@ -74,10 +74,11 @@ static int s3c_serial_setbaudrate(struct console_device 
*cdev, int baudrate)
void __iomem *base = priv-regs;
unsigned val;
 
-#ifdef S3C_UART_HAS_UBRDIVSLOT
-   val = s3c_get_arch_uart_input_clock(base) / baudrate;
-   writew(udivslot_table[val  15], base + UBRDIVSLOT);
-#endif
+   if (IS_ENABLED(CONFIG_SAMSUNG_IMPROVED_UART)) {
+   val = s3c_get_arch_uart_input_clock(base) / baudrate;
+   writew(udivslot_table[val  15], base + UBRDIVSLOT);
+   }
+
val = s3c_get_arch_uart_input_clock(base) / (16 * baudrate) - 1;
writew(val, base + UBRDIV);
 
@@ -101,10 +102,9 @@ static int s3c_serial_init_port(struct console_device 
*cdev)
writew(0x0245 | UCON_SET_CLK_SRC(CONFIG_DRIVER_SERIAL_S3C_CLK),
base + UCON);
 
-#ifdef S3C_UART_HAS_UINTM
-   /* 'interrupt or polling mode' for both directions */
-   writeb(0xf, base + UINTM);
-#endif
+   if (IS_ENABLED(CONFIG_SAMSUNG_IMPROVED_UART))
+   /* 'interrupt or polling mode' for both directions */
+   writeb(0xf, base + UINTM);
 
if (IS_ENABLED(CONFIG_DRIVER_SERIAL_S3C_AUTOSYNC))
writeb(0x10, base + UMCON); /* enable auto flow control */
-- 
1.7.10.4


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[PATCH 12/18] ARM/Samsung: add S3C6410 SoC iomap

[Juergen Beisert]

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 arch/arm/mach-samsung/include/mach/s3c-iomap.h |3 ++
 arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h |   44 
 2 files changed, 47 insertions(+)
 create mode 100644 arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h

diff --git a/arch/arm/mach-samsung/include/mach/s3c-iomap.h 
b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
index d34ace4..09a6891 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-iomap.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
@@ -22,6 +22,9 @@
 #ifdef CONFIG_ARCH_S3C24xx
 # include mach/s3c24xx-iomap.h
 #endif
+#ifdef CONFIG_ARCH_S3C64xx
+# include mach/s3c64xx-iomap.h
+#endif
 #ifdef CONFIG_ARCH_S5PCxx
 # include mach/s5pcxx-iomap.h
 #endif
diff --git a/arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h 
b/arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h
new file mode 100644
index 000..267cd4f
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/s3c64xx-iomap.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2012 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* S3C64xx device base addresses */
+# define S3C_SROM_SFR  0x7000
+# define S3C_DRAMC 0x7e001000
+# define S3C_WATCHDOG_BASE 0x7e004000
+# define S3C_CLOCK_POWER_BASE  0x7e00f000
+# define S3C_UART_BASE 0x7f005000
+# define S3C_TIMER_BASE0x7f006000
+# define S3C_GPIO_BASE 0x7f008000
+
+# define S3C_UART1_BASE (S3C_UART_BASE)
+# define S3C_UART1_SIZE 0x400
+# define S3C_UART2_BASE (S3C_UART_BASE + 0x400)
+# define S3C_UART2_SIZE 0x400
+# define S3C_UART3_BASE (S3C_UART_BASE + 0x800)
+# define S3C_UART3_SIZE 0x400
+# define S3C_UART4_BASE (S3C_UART_BASE + 0xc00)
+# define S3C_UART4_SIZE 0x400
+
+# define S3C_SDRAM_BASE 0x5000
+# define S3C_SDRAM_END (S3C_SDRAM_BASE + 0x1000)
+
+# define S3C_SROM_BW (S3C_SROM_SFR)
+# define S3C_SROM_BC0 (S3C_SROM_SFR + 4)
+
+# define S3C_CS0_BASE 0x1000
+# define S3C_CS1_BASE 0x1800
+# define S3C_CS2_BASE 0x2000
+# define S3C_CS3_BASE 0x2800
+# define S3C_CS4_BASE 0x3000
+# define S3C_CS5_BASE 0x3800
-- 
1.7.10.4


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[PATCH 16/18] ARM/Samsung: add generic S3C6410 SoC specific functions

[Juergen Beisert]

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 arch/arm/mach-samsung/Makefile   |2 +-
 arch/arm/mach-samsung/include/mach/s3c-generic.h |   13 +
 arch/arm/mach-samsung/mem-s3c64xx.c  |   65 ++
 3 files changed, 79 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-samsung/mem-s3c64xx.c

diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
index 5187170..9402289 100644
--- a/arch/arm/mach-samsung/Makefile
+++ b/arch/arm/mach-samsung/Makefile
@@ -3,6 +3,6 @@ obj-lowlevel-$(CONFIG_ARCH_S3C24xx) += lowlevel-s3c24x0.o
 obj-lowlevel-$(CONFIG_ARCH_S3C64xx) += lowlevel-s3c64x0.o
 obj-lowlevel-$(CONFIG_ARCH_S5PCxx) += lowlevel-s5pcxx.o
 obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o clocks-s3c24xx.o mem-s3c24x0.o
-obj-$(CONFIG_ARCH_S3C64xx) += gpio-s3c64xx.o clocks-s3c64xx.o
+obj-$(CONFIG_ARCH_S3C64xx) += gpio-s3c64xx.o clocks-s3c64xx.o mem-s3c64xx.o
 obj-$(CONFIG_ARCH_S5PCxx) += gpio-s5pcxx.o clocks-s5pcxx.o mem-s5pcxx.o
 obj-$(CONFIG_S3C_LOWLEVEL_INIT) += $(obj-lowlevel-y)
diff --git a/arch/arm/mach-samsung/include/mach/s3c-generic.h 
b/arch/arm/mach-samsung/include/mach/s3c-generic.h
index 329c2b4..42e8c5f 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-generic.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-generic.h
@@ -47,3 +47,16 @@ void s5p_init_dram_bank_lpddr2(phys_addr_t base, uint32_t 
mc0, uint32_t mc1, int
 void s5p_init_dram_bank_ddr2(phys_addr_t base, uint32_t mc0, uint32_t mc1, int 
bus16);
 uint32_t s5p_get_memory_size(void);
 #endif
+
+#ifdef CONFIG_ARCH_S3C64xx
+unsigned s3c6410_get_memory_size(void);
+struct s3c6410_chipselect {
+   unsigned adr_setup_t; /* in [ns] */
+   unsigned access_setup_t; /* in [ns] */
+   unsigned access_t; /* in [ns] */
+   unsigned cs_hold_t; /* in [ns] */
+   unsigned adr_hold_t; /* in [ns] */
+   unsigned char width; /* 8 or 16 */
+};
+int s3c6410_setup_chipselect(int, const struct s3c6410_chipselect*);
+#endif
diff --git a/arch/arm/mach-samsung/mem-s3c64xx.c 
b/arch/arm/mach-samsung/mem-s3c64xx.c
new file mode 100644
index 000..f312fb2
--- /dev/null
+++ b/arch/arm/mach-samsung/mem-s3c64xx.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2012 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include errno.h
+#include io.h
+#include mach/s3c-iomap.h
+#include mach/s3c-generic.h
+
+#define S3C_DRAMC_CHIP_0_CFG (S3C_DRAMC + 0x200)
+
+/* note: this routine honors the first memory bank only */
+unsigned s3c6410_get_memory_size(void)
+{
+   unsigned reg = readl(S3C_DRAMC_CHIP_0_CFG)  0xff;
+
+   return ~(reg  24) + 1;
+}
+
+/* configure the timing of one of the available external chip select lines */
+int s3c6410_setup_chipselect(int no, const struct s3c6410_chipselect *c)
+{
+   unsigned per_t = 10 / s3c_get_hclk();
+   unsigned tacs, tcos, tacc, tcoh, tcah, shift;
+   uint32_t reg;
+
+   /* start of cycle to chip select assertion (= address/data setup) */
+   tacs = DIV_ROUND_UP(c-adr_setup_t, per_t);
+   /* start of CS to read/write assertion (= access setup) */
+   tcos = DIV_ROUND_UP(c-access_setup_t, per_t);
+   /* length of read/write assertion (= access lenght) */
+   tacc = DIV_ROUND_UP(c-access_t, per_t) - 1;
+   /* CS hold after access is finished */
+   tcoh = DIV_ROUND_UP(c-cs_hold_t, per_t);
+   /* adress/data hold after CS is deasserted */
+   tcah = DIV_ROUND_UP(c-adr_hold_t, per_t);
+
+   shift = no * 4;
+   reg = readl(S3C_SROM_BW)  ~(0xf  shift);
+   if (c-width == 16)
+   reg |= 0x1  shift;
+   writel(reg, S3C_SROM_BW);
+#ifdef DEBUG
+   if (tacs  15 || tcos  15 || tacc  31 || tcoh  15 || tcah  15) {
+   pr_err(At least one of the timings are invalid\n);
+   return -EINVAL;
+   }
+   pr_info(Will write 0x%08X\n, tacs  28 | tcos  24 | tacc  16 |
+   tcoh  12 | tcah  8);
+#endif
+   writel(tacs  28 | tcos  24 | tacc  16 | tcoh  12 | tcah  8,
+   S3C_SROM_BC0 + shift);
+
+   return 0;
+}
-- 
1.7.10.4


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[PATCH 03/18] ARM/Samsung: follow the name style of the other source files in this directory

[Juergen Beisert]

Signed-off-by: Juergen Beisert j...@pengutronix.de
---
 arch/arm/mach-samsung/Makefile |2 +-
 arch/arm/mach-samsung/clocks-s3c24xx.c |  157 
 arch/arm/mach-samsung/s3c24xx-clocks.c |  157 
 3 files changed, 158 insertions(+), 158 deletions(-)
 create mode 100644 arch/arm/mach-samsung/clocks-s3c24xx.c
 delete mode 100644 arch/arm/mach-samsung/s3c24xx-clocks.c

diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
index 6020587..091b600 100644
--- a/arch/arm/mach-samsung/Makefile
+++ b/arch/arm/mach-samsung/Makefile
@@ -1,6 +1,6 @@
 obj-y += s3c-timer.o generic.o
 obj-lowlevel-$(CONFIG_ARCH_S3C24xx) += lowlevel-s3c24x0.o
 obj-lowlevel-$(CONFIG_ARCH_S5PCxx) += lowlevel-s5pcxx.o
-obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o s3c24xx-clocks.o mem-s3c24x0.o
+obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o clocks-s3c24xx.o mem-s3c24x0.o
 obj-$(CONFIG_ARCH_S5PCxx) += gpio-s5pcxx.o clocks-s5pcxx.o mem-s5pcxx.o
 obj-$(CONFIG_S3C_LOWLEVEL_INIT) += $(obj-lowlevel-y)
diff --git a/arch/arm/mach-samsung/clocks-s3c24xx.c 
b/arch/arm/mach-samsung/clocks-s3c24xx.c
new file mode 100644
index 000..13e6867
--- /dev/null
+++ b/arch/arm/mach-samsung/clocks-s3c24xx.c
@@ -0,0 +1,157 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include config.h
+#include common.h
+#include init.h
+#include clock.h
+#include io.h
+#include mach/s3c-iomap.h
+#include mach/s3c-generic.h
+#include mach/s3c-clocks.h
+#include mach/s3c-busctl.h
+
+/**
+ * Calculate the current M-PLL clock.
+ * @return Current frequency in Hz
+ */
+uint32_t s3c_get_mpllclk(void)
+{
+   uint32_t m, p, s, reg_val;
+
+   reg_val = readl(S3C_MPLLCON);
+   m = ((reg_val  0xFF000)  12) + 8;
+   p = ((reg_val  0x003F0)  4) + 2;
+   s = reg_val  0x3;
+#ifdef CONFIG_CPU_S3C2410
+   return (S3C24XX_CLOCK_REFERENCE * m) / (p  s);
+#endif
+#ifdef CONFIG_CPU_S3C2440
+   return 2 * m * (S3C24XX_CLOCK_REFERENCE / (p  s));
+#endif
+}
+
+/**
+ * Calculate the current U-PLL clock
+ * @return Current frequency in Hz
+ */
+uint32_t s3c_get_upllclk(void)
+{
+   uint32_t m, p, s, reg_val;
+
+   reg_val = readl(S3C_UPLLCON);
+   m = ((reg_val  0xFF000)  12) + 8;
+   p = ((reg_val  0x003F0)  4) + 2;
+   s = reg_val  0x3;
+
+   return (S3C24XX_CLOCK_REFERENCE * m) / (p  s);
+}
+
+/**
+ * Calculate the FCLK frequency used for the ARM CPU core
+ * @return Current frequency in Hz
+ */
+uint32_t s3c_get_fclk(void)
+{
+   return s3c_get_mpllclk();
+}
+
+/**
+ * Calculate the HCLK frequency used for the AHB bus (CPU to main peripheral)
+ * @return Current frequency in Hz
+ */
+uint32_t s3c_get_hclk(void)
+{
+   uint32_t f_clk;
+
+   f_clk = s3c_get_fclk();
+#ifdef CONFIG_CPU_S3C2410
+   if (readl(S3C_CLKDIVN)  0x02)
+   return f_clk  1;
+#endif
+#ifdef CONFIG_CPU_S3C2440
+   switch(readl(S3C_CLKDIVN)  0x06) {
+   case 2:
+   return f_clk  1;
+   case 4:
+   return f_clk  2;  /* TODO consider CAMDIVN */
+   case 6:
+   return f_clk / 3;   /* TODO consider CAMDIVN */
+   }
+#endif
+   return f_clk;
+}
+
+/**
+ * Calculate the PCLK frequency used for the slower peripherals
+ * @return Current frequency in Hz
+ */
+uint32_t s3c_get_pclk(void)
+{
+   uint32_t p_clk;
+
+   p_clk = s3c_get_hclk();
+   if (readl(S3C_CLKDIVN)  0x01)
+   return p_clk  1;
+   return p_clk;
+}
+
+/**
+ * Calculate the UCLK frequency used by the USB host device
+ * @return Current frequency in Hz
+ */
+uint32_t s3c24_get_uclk(void)
+{
+   return s3c_get_upllclk();
+}
+
+/**
+ * Return correct UART frequency based on the UCON register
+ */
+unsigned s3c_get_uart_clk(unsigned src)
+{
+   switch (src  3) {
+   case 0:
+   case 2:
+   return s3c_get_pclk();
+   case 1:
+   return 0; /* TODO UEXTCLK */
+   case 3:
+   return 0; /* TODO FCLK/n */
+   }
+   return 0; /* not reached, to make compiler happy */
+}
+
+/**
+ * Show the user the current clock settings
+ */
+int s3c24xx_dump_clocks(void)
+{
+   printf(refclk:  %7d kHz\n, S3C24XX_CLOCK_REFERENCE / 1000);
+   printf(mpll:%7d kHz\n, s3c_get_mpllclk() / 1000);
+   printf(upll:%7d kHz\n, s3c_get_upllclk() / 1000);
+   printf(fclk:%7d kHz\n, s3c_get_fclk() / 1000