Re: [casper] ROACH 1 DRAM
Hi Marc, Thanks for the reply. I would have expected that selecting the 64 MB chunk with the dram_controller register as described in the DRAM block documentation on the wiki would get around any such PPC address space limitation. Is that not the case? Glenn On Feb 25, 2014 2:30 AM, "Marc Welz" wrote: > On Mon, Feb 24, 2014 at 7:57 PM, G Jones wrote: > > Hi, > > Sorry to repost this. Just curious if anyone has experience using more > than > > 256 MB of FPGA DRAM on the ROACH, in particular through the PPC > interface. > > The PowerPC's virtual memory subsystem maps things in 256Mb > regions/segments, > and only one is used to access the FPGA(*) - so you will probably have > to implement > some sort of windowing/base+offset scheme. > > (The address space of the PowerPC is pretty constrained) > > regards > > marc >
Re: [casper] ROACH 1 DRAM
On Mon, Feb 24, 2014 at 7:57 PM, G Jones wrote: > Hi, > Sorry to repost this. Just curious if anyone has experience using more than > 256 MB of FPGA DRAM on the ROACH, in particular through the PPC interface. The PowerPC's virtual memory subsystem maps things in 256Mb regions/segments, and only one is used to access the FPGA(*) - so you will probably have to implement some sort of windowing/base+offset scheme. (The address space of the PowerPC is pretty constrained) regards marc
Re: [casper] Component switching limit
Hi Jay, Component switching limits test that individual components of your design are running within their specified operating frequency parameters -- a few brief posts are here -- http://forums.xilinx.com/t5/Timing-Analysis/component-switching-limit/m-p/73419 -- so to fix them you basically just have to find the specific component which is unhappy, and work out how to use it within it's allowed ranges. I've sometimes seen these errors with misconfigured MMCMs and things like that. Does the timing report shed any light on where you are getting these errors? If it's something in the ADC yellow block (which would surprise me a little because I've compiled for 50MSa on ROACH 2) then I'll try and recreate your error and fix it. Cheers, Jack On 24 February 2014 23:30, Jay Brady wrote: > Hi all, > > I've just started working on porting a design I had done for a ROACH 1 up to > ROACH 2. The design is based off of the 64ADCx64-12 running at 50Msps with a > handful of VHDL/Coregen blocks. I've finally got all the green/yellow blocks > updated for ROACH 2 so that it will actually synthesize, but now I'm getting > a bunch of timing errors, all component switching limit error. I'm > comfortable clearing up setup/hold errors by pipelining and whatnot, but > I've never had component switching errors, so I'm not even sure where to > begin to diagnose and fix them (or even what they really mean...) Does > anyone have any general tips or references for these kind of timing errors? > > Thanks, > Jay Brady
[casper] Component switching limit
Hi all, I've just started working on porting a design I had done for a ROACH 1 up to ROACH 2. The design is based off of the 64ADCx64-12 running at 50Msps with a handful of VHDL/Coregen blocks. I've finally got all the green/yellow blocks updated for ROACH 2 so that it will actually synthesize, but now I'm getting a bunch of timing errors, all component switching limit error. I'm comfortable clearing up setup/hold errors by pipelining and whatnot, but I've never had component switching errors, so I'm not even sure where to begin to diagnose and fix them (or even what they really mean...) Does anyone have any general tips or references for these kind of timing errors? Thanks, Jay Brady
Re: [casper] ROACH 1 DRAM
Hi, Sorry to repost this. Just curious if anyone has experience using more than 256 MB of FPGA DRAM on the ROACH, in particular through the PPC interface. Thanks, Glenn On Wed, Feb 12, 2014 at 12:44 PM, G Jones wrote: > Hi, > I'm using the ROACH 1 DRAM for a lookup table for waveform generation with > the DAC. Everything has been working well and as I expected, until I tried > to use more than 256 MB. It looks like the ROACH has a single sided 1 GB > DRAM module in the FPGA DRAM slot, but I don't have the exact part number > (it came as shipped from Mo). I figured I might only be able to use 512 MB > because of the caveat listed on the DRAM wiki page: > "Many ROACHs have been shipped with 1 GB dual rank DIMMs by default. The > current DRAM controller is not able to handle multiple ranks, so when a > dual-rank DIMM is installed on the board, only half the memory is > available. In order to use the full 1 GB, a single rank DIMM is needed, or > in principle a dual rank 2 GB module." > > But I was surprised to have issues passed 256 MB. Has anyone seen anything > like this before? Is it a known issue? > > Thanks, > Glenn >
