Re: [casper] SSL error, can't see the wiki

[Jonathon Kocz]

Hi David,

Hopefully the website will be back up soon, but in case it helps, for that
specific PFB link, there is a copy of the memo here:
https://github.com/casper-astro/publications/blob/master/Memos/files/Casper_memo_pfb.pdf

(More generally, while we don't have all the hardware info there, most of
the memo's etc from the wiki are available here:
https://github.com/casper-astro/publications).

Cheers,
Jonathon

On Wed, 11 Jan 2023 at 13:08, dps7802  wrote:

> Casperites,
>
> I'm getting SSL errors when I try to look at links from my notes.
>
> I can see the main page
> https://casper.berkeley.edu/
>
> but when I click the Wiki link on the main page I get an SSL error.
> https://casper.astro.berkeley.edu/wiki/Main_Page
>
> Error code: SSL_ERROR_RX_RECORD_TOO_LONG
>
> The url in my notes that produces the same error is
>  https://casper.berkeley.edu/wiki/The_Polyphase_Filter_Bank_Technique
>
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[casper] CASPER Workshop 2023 - First Announcement

[Jonathon Kocz]

Dear Colleagues,

We are pleased to announce that the CASPER Workshop of 2023 will be held at
the University of Central Florida, with proposed dates of the 6th - 10th
November.

A more detailed announcement with registration and other information will
follow in a few weeks. Until then, it would greatly assist the organisers
if you would consider filling out a short questionnaire
<https://forms.gle/bHLuhY9MkRDrZ2rs6>regarding anticipated participation.

If you have any questions, please do not hesitate to contact the local
organizing committee at "casper2...@ucf.edu"

Best regards,
Jonathon Kocz, on behalf of the LOC:

Robert Brown (UCF)
Allison Cross (UCF)
Kara Kennedy (UCF)
John Kiriazes (UCF)
Hamid Rassoul (FIT)

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Re: [casper] XPORT adress

[Jonathon Kocz]

Hi Kuma,

1) The ROACH2 does not support XPORT (that was only for the ROACH1). - You
can find the hardware specs of both on the old wiki:
https://casper.astro.berkeley.edu/wiki/ROACH,
https://casper.astro.berkeley.edu/wiki/ROACH-2_Revision_2)

2) As (1) above.

3) The V6 Net interface is a direct connection to the FPGA, instead of the
PPC chip, so you can use it e.g. for 1Gb Ethernet transmission from the
FPGA.

Cheers,
Jonathon

On Sun, 23 Apr 2023 at 09:39, Bartholemew Kuma  wrote:

> Hi everyone,
>
> I'm using roachnest to monitor and manage ROACH2.
> I have never changed the relevant configuration of Xport.
> The default Xport address of ROACH2 is 192.168.4.20.
> I entered 192.168.4.20 in the Xport address, but the address failed to be
> pinged.
> [image: roachnest.png]
> I have some questions:
> 1) I suspect that my ROACH2 does not support the use of Xport to access
> the monitoring and management subsystem. Is this a built-in feature?
>
> 2) My ROACH2 uses netboot.Does this change the Xport address?
> How can I check the Xport adress for the current device?
>
> 3) I noticed that there is a V6 NET interface. What is it used for?
>
> cheers,
> Kuma
>
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Re: [casper] SNAP Tutorial 3

[Jonathon Kocz]

Jason,

I think the data problem is with the ADC calibration. - And I agree, the
inconsistent renames were hugely frustrating. Sorry you've hit these
errors. The original SNAP calibration routine did not work with python3 and
needed to be rewritten entirely. It was left in a broken state for a while
as the merged commit didn't fix the various issues and updated some of the
syntax.

A working version has recently been merged into the py38-dev branch of
casperfpga: https://github.com/casper-astro/casperfpga/tree/py38-dev

The tut script will need updating, but an example adc calibration code
developed by Wei Liu is here:
https://github.com/liuweiseu/limbo_scripts/blob/lab_test/ipynb/snap_adc.ipynb

I'm not sure about the build error - does this only occur for SNAP builds,
or any build?

Best,
Jonathon




On Fri, 12 May 2023 at 05:03, Jason Gallicchio  wrote:

> I had the same issue and still do. I see similar spikes, even with a
> signal. It's because I see zero or near-zero samples that occur in groups
> of 8. (See attached.)
>
> I've attached my snapshot from fpga.devices['adc'].read(man_trig=True).
>
> I get a similar result from calling adc.readRAM()[0].reshape(128*8)
>
> It's not as obvious that this pattern exists for low-power inputs. I saw
> the same spectrum as in the original post when I had no or small input
> because of the regular pattern of zeros hidden in the near-zero noise.
>
> I have NOT figured out why this is happening. It happens when I use any of
> the 3 ADC chips. It happens for sampling frequencies slower than 800 MHz.
>
> I don't know how to tell if it's a hardware problem or (more likely) a
> configuration one -- the tutorial didn't work out of the box.
>
> I started with the python code on the main branch of tutorials_devel:
>
> https://github.com/casper-astro/tutorials_devel/blob/main/snap/tut_spec/snap_tut_spec.py
>
>
> However, I had to do several things to get even this far:
>
> * convert the python2 code to python3 to work with the py38 branch of
> casperfpga
>
> * Do my own initialization after calling  init(): I called
> either adc.rampTest(retry=True) (which passes) or adc.alignLineClock()
> and adc.alignFrameClock(). I might have to call these manually now because
> of the cryptic "Snipped off ADC calibration here;" comment in
> https://github.com/casper-astro/casperfpga/blob/py38/src/snapadc.py#L269
> and I'm not sure what other steps I should be taking here.
>
> * Wonder why adc.set_gain(gain) doesn't seem to do anything. Maybe I
> should be playing with adc.adc.cGain() and adc.adc.fGain()? Does this need
> to get called before or after some other initialization step?
>
> * Wonder why some functions seem to have been inconsistently renames that
> I manually tweaked, like
> - casperfpga.snapadc.SnapAdc = casperfpga.snapadc.SNAPADC
> - adc.testPatterns = adc.test_patterns
> - adc.select_adc = adc.selectADC
> - adc.controller = type(adc.adc)
>
> * liberally interpret references to ROACH in the docs
> https://github.com/casper-astro/tutorials_devel/blob/main/docs/tutorials/snap/tut_spec.md
>
>
> I am using the random Raspberry Pi 3b+ image I got from the google drive
> link on:
> https://www.mail-archive.com/casper@lists.berkeley.edu/msg07317.html
> because the link on the more official Bringup page had issues that I no
> longer remember:
> https://casper.astro.berkeley.edu/wiki/SNAP_Bringup
>
> I get the same bad data whether I use the pre-built snap_tut_spec.fpg and
> also my own build. Admittedly, this is only my second simulink jasper build
> after tutorial 1, and these builds always end with
> FileNotFoundError: [Errno 2] No such file or directory:
> '.../tutorials_devel/snap/tut_spec/snap_tut_spec/myproj/myproj.runs/impl_1/top.xsa'
>
> If I get these things figured out, I'd be happy to do a pull request for
> or whatever would be helpful.
>
> Thanks,
> Jason
>
> On Monday, January 21, 2019 at 5:50:50 PM UTC+11 James Smith wrote:
>
> Hello David,
>
> A little late to the party but I thought I'd throw in 2c from our
> perspective.
>
> The other thing we usually try to do with ADCs (this was an issue on the
> ROACH1s) is to put in a bit of white noise with whatever test signal we
> were using (sine wave usually). When you get actual sky, then you will have
> to fiddle with signal levels again until you get an optimum, because the
> sky signal will invariably be different from your lab test signals.
>
> Regards,
> James
>
>
> On Fri, Jan 18, 2019 at 7:37 PM David Marsh  wrote:
>
> Thank you Dan!
>
> Using the adc snapshot, I saw that with no input the adc was toggling
> between -1 and 0. This was the cause of the
> spikes in the spectrum. I also looked at the adc samples with a sine wave
> as the input and everything looked as
> expected as you described.
>
> Thanks,
> David
>
>
>
> On Tue, Jan 15, 2019 at 11:07 AM Dan Werthimer 
> wrote:
>
>
> hi david,
>
> when you have no signal going into an adc, it will typically chatter
> between two values, around -1, 0 and +1,
> a

Re: [casper] SNAP Tutorial 3

[Jonathon Kocz]

>
> Wei Liu's code helped because it gave me the idea to call rampTest()
> first. Is rampTest() the only "calibration" that Wei Liu's code is
> doing? rampTest() calls alignLineClock() and alignFrameClock(). Is this all
> that you mean by "calibration"? Not some fine-tuning or balancing of gains
> or delays for different sub-ADCs, which then get interleaved together?
>
> As you probably know the ADC has 8-cores (each of the 4 main cores are
actually two sub-cores which are interleaved, and they start in a random
order on power up. The main focus of the casper calibration code is for
ordering these samples in the correct way. Aligning the clocks should also
deal with the delays, but we don't apply gain inter-core corrections.

>
> adc.set_gain() still does nothing, even when called where Wei Liu's code
> calls it. Where in the startup process should this get called?
>

I believe that set gain is for input signals, so it won't impact the actual
calibration (I would actually recommend keeping it below 8, it moves into a
"digital" gain after that which mostly just confuses things).

The py38-dev and py38 branches of casperfpga differ in only trivial ways
> in snapadc.py. Maybe the changes you spoke of have already been merged into
> py38?
>
> py38 was supposed to work, but there were still some hiccups - Wei fixed
them up, so they should be close.


> As for the build error, I've only tried SNAP tutorial 1 and 3 and I got
> the error for both. Once Xilinx finally gets back to me about an academic
> license, I'll be able to try it on my RFSoC 4x2. Does it normally take more
> than a month to process a donation request? I've asked twice.
>
> For a software donation, I've typically found it to be fairly fast (almost
automated - a few days at most), but it has been a long time since I last
asked - someone with more recent experience might be able to chime in.

Best,
Jonathon



>

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Re: [casper] tut_rfdc on RFSoC4x2

[Jonathon Kocz]

Hi Cedric and Nhung,

A couple of things to check:

1) Have you updated the startsg.local file with the paths for creating the
.dtbo files?

You'll need to set the JASPER_BACKEND to vitis also (e.g):

JASPER_BACKEND=vitisXLNX_DT_REPO_PATH=/sandbox/xilinx/device-tree-xlnx


The dtbo file will not be generated without this (see "Toolflow Setup"
https://casper-toolflow.readthedocs.io/projects/tutorials/en/latest/tutorials/rfsoc/tut_getting_started.html
)

2) For populating the ADC information, try the "get_system_information"
call (fpga.get_system_information() or fpga.get_system_information(''))

Cheers,
Jonathon

On Thu, 8 Jun 2023 at 08:02, Cedric Viou  wrote:

> Hi!
>
> We are starting to use ADCs with our RFSoC4x2 and we encounter 2 related
> (?) problems.
>
> First, the tutorials says that we should pay attention to the generation
> of a .dtbo by Vivado.
> We can't find it after building the tutorials (and not in the
> jasper/vivado logs).  That was ok for tutorial 1 (RFSoC Platform ...
> Overview), however this seems to be mandatory for tutorial 2 (RFDC
> interface).
> Where (and how) is this supposed to be created?
>
> Then, to make some progress, we tried to use prebuilt .fpg and .dtbo from
> the github repository to start to use it anyway, but when the fpga is
> programmed with tut_rfdc, we can play with the counter and adder part, BUT
> we can't get information (configure, or use) about the ADC: my_RFSoC.adcs
> returns [].  Only my_RFSoC.listdev() returns a list of strings that
> contains 'rfdc', but we can't do anything with it.
>
> Any idea about what we are doing wrong?
>
> Cheers,
>
> Cedric and Nhung
>
>
>
> ###Tutorial devel
> commit 26fce95d9f965d7b5f5bb7c9251ca096b53272a6 (HEAD -> main,
> origin/main, origin/HEAD)
> Merge: 644f5da 81a21a1
> Author: Mitch Burnett 
> Date:   Thu Oct 6 17:31:31 2022 -0600
>
>
> ###mlib delvel
> commit 7f187b32133697bfdacc4fb122e9575e33acb705 (HEAD -> m2021a,
> origin/m2021a, origin/HEAD)
> Merge: 110926427 d86acbcb8
> Author: J. Kocz <1220894+jk...@users.noreply.github.com>
> Date:   Tue Oct 25 09:46:08 2022 -0700
>
> Matlab: R2021a
> Vivado: v2021.1 (64-bit)
>
>
> --
> Cedric Viou 
>
> Ingénieur de recherche
>
> Observatoire Radioastronomique de Nançay,
> Observatoire de Paris, PSL Research University, CNRS, Univ. Orléans, OSUC,
> 18330 Nançay, France
> http://www.obs-nancay.fr
>
> phone : +33 (0) 248 51 8609
>
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> .
>

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Re: [casper] Error in Matlab running startsg

[Jonathon Kocz]

Hi Ben,

You may have already, but there are a couple of other places to move libgmp
that might be worth trying:

(From this issue: https://github.com/casper-astro/mlib_devel/issues/190)

cd /opt/Xilinx/Model_Composer/2021.1/lib/lnx64.o/Ubuntu
mkdir exclude
mv libgmp.so* exclude/

cd /opt/Xilinx/Vivado/2021.1/lib/lnx64.o
mkdir exclude
mv libgmp.so* exclude/

I've heard of a couple of other people with this issue - it seems something
updated in Ubuntu 20.04.5 since we did our guide - we'll try and track it
down. - In the meantime, another solution is to use an existing VM. -
Andrew Martens kindly put this one together with the tools installed which
should work - you just have to add licenses (you may have to request
permission for the download):
https://drive.google.com/file/d/1FfsZddV5_tRMd3ZBibDvolPTPPSjBfRk/view?usp=sharing

Best,
Jonathon



On Fri, 9 Jun 2023 at 13:01, benjamin.fischer via casper@lists.berkeley.edu
 wrote:

> Hi all,
>
> I have been trying to set up the Toolflow quite closely following the
> setup guide (using the recommended versions: a completely fresh Ubuntu
> 20.04 install, Vivado 2021.1, mlib_devel m2021a). I get to the point under
> "Running the toolflow" but when I run the startsg script while Matlab does
> open it presents me with the error "Caught "std::exception" Exception
> message is:
> Error loading
> /usr/local/MATLAB/R2021a/bin/glnxa64/builtins/sl_main/mwlibmwsimulink_builtinimpl.so.
> /lib/x86_64-linux-gnu/libhogweed.so.5: undefined symbol: __gmpn_cnd_sub_n:
> Success: Success".
> This looked similar to what Craig Ramsay solved (
> https://strath-sdr.github.io/tools/matlab/sysgen/vivado/linux/2021/01/28/sysgen-on-20-04.html)
> which is also linked in the installation guide, so I followed that as well.
> This however didn't fix the issue. I get into Matlab and can start Simulink
> but it is quite slow and the toolbar in the Simulink window is missing.
> Additionally, when opening a Simulink window Matlab spits out copious
> amounts of errors and warnings in the background. Running the
> "jasper_frontend" command when following the tutorial further also results
> in an error. If I start Matlab manually, though, everything seems to
> behave.
>
> Perhaps someone has encountered similar issues or has an idea how to fix
> this.
>
> Many thanks and best wishes,
> Ben
>
> --
> FreeMail powered by mail.co.uk
>
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> 
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>

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Re: [casper] Error in Matlab running startsg

[Jonathon Kocz]

Hi Ben,

I just took a look and this seems to an issue with the model. - Some of
test models in that folder appear to be out of date, and this particular
test file used a custom bit of code to test the crc of the packet that
looks like it was not checked in along with the model, so the model can't
initialize.

You might be better off trying the "test_snap_adc.slx" file or the "golden"
SNAP image. (jasper_library/golden/snap160t_golden.slx)

Two notes:

1) If you're using a Rpi to do the communication, in the golden image you
need to uncheck the "use microblaze" check box before compiling.
2) If you're using the microblaze over the 10gb for communication, I
recommend either the m2019 branch or the m2021a-dev branch (there was a
microblaze bug for the SNAP that was introduced in m2021a that has been
fixed in -dev, but not merged back into the main branch yet).

Cheers,
Jonathon


On Sat, 10 Jun 2023 at 08:58, benjamin.fischer via casper@lists.berkeley.edu
 wrote:

> Hi Jonathon, hi all,
>
> Thank you - this did the trick! Simulink looks normal now and I can get
> into the model without errors. However, when updating the test_snap.slx
> model (just to check that things are indeed working alright), I now
> encounter a new error (or rather, set of similar errors) thrown at me by
> the diagnostic viewer:
>
> Could not find the configuration m-function "crc32x64_config".
> Error occurred during "Block Configuration".
>
> Reported by:
> 'test_snap/crc_check0/crc32x64_check1'
> Could not find the configuration m-function "crc32x64_config".
> Error occurred during "Block Configuration".
>
> Reported by:
> 'test_snap/crc_check1/crc32x64_check1'
> Could not find the configuration m-function "crc32x64_config".
> Error occurred during "Block Configuration".
>
> Reported by:
> 'test_snap/pkt_sim0/crc32x64'
> Could not find the configuration m-function "crc32x64_config".
> Error occurred during "Block Configuration".
>
> Reported by:
> 'test_snap/pkt_sim1/crc32x64'
>
> Any idea what this could be due to?
>
> Many thanks,
> Ben
>
>
> On 09-Jun-2023 22:17:40 +0200, jxk...@gmail.com wrote:
>
> Hi Ben,
>
> You may have already, but there are a couple of other places to move
> libgmp that might be worth trying:
>
> (From this issue: https://github.com/casper-astro/mlib_devel/issues/190)
>
> cd /opt/Xilinx/Model_Composer/2021.1/lib/lnx64.o/Ubuntu
> mkdir exclude
> mv libgmp.so* exclude/
>
> cd /opt/Xilinx/Vivado/2021.1/lib/lnx64.o
> mkdir exclude
> mv libgmp.so* exclude/
>
> I've heard of a couple of other people with this issue - it seems
> something updated in Ubuntu 20.04.5 since we did our guide - we'll try and
> track it down. - In the meantime, another solution is to use an existing
> VM. - Andrew Martens kindly put this one together with the tools installed
> which should work - you just have to add licenses (you may have to request
> permission for the download):
> https://drive.google.com/file/d/1FfsZddV5_tRMd3ZBibDvolPTPPSjBfRk/view?usp=sharing
>
> Best,
> Jonathon
>
>
>
> On Fri, 9 Jun 2023 at 13:01, benjamin.fischer via
> casper@lists.berkeley.edu  wrote:
>
>> Hi all,
>>
>> I have been trying to set up the Toolflow quite closely following the
>> setup guide (using the recommended versions: a completely fresh Ubuntu
>> 20.04 install, Vivado 2021.1, mlib_devel m2021a). I get to the point under
>> "Running the toolflow" but when I run the startsg script while Matlab does
>> open it presents me with the error "Caught "std::exception" Exception
>> message is:
>> Error loading
>> /usr/local/MATLAB/R2021a/bin/glnxa64/builtins/sl_main/mwlibmwsimulink_builtinimpl.so.
>> /lib/x86_64-linux-gnu/libhogweed.so.5: undefined symbol: __gmpn_cnd_sub_n:
>> Success: Success".
>> This looked similar to what Craig Ramsay solved (
>> https://strath-sdr.github.io/tools/matlab/sysgen/vivado/linux/2021/01/28/sysgen-on-20-04.html)
>> which is also linked in the installation guide, so I followed that as well.
>> This however didn't fix the issue. I get into Matlab and can start Simulink
>> but it is quite slow and the toolbar in the Simulink window is missing.
>> Additionally, when opening a Simulink window Matlab spits out copious
>> amounts of errors and warnings in the background. Running the
>> "jasper_frontend" command when following the tutorial further also results
>> in an error. If I start Matlab manually, though, everything seems to
>> behave.
>>
>> Perhaps someone has encountered similar issues or has an idea how to fix
>> this.
>>
>> Many thanks and best wishes,
>> Ben
>>
>> --
>> FreeMail powered by mail.co.uk
>>
>>
>> --
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[casper] CASPER Workshop 2023 - Registration Open

[Jonathon Kocz]

Dear Colleagues,

I am pleased to announce that registration
for the
CASPER Workshop 2023 is now open. Please note that due to a delay with the
payment processing system, we will collect the registration fee separately
at a later date.

The workshop will be hosted by The University of Central Florida, and held
at the Hilton Hotel at Cocoa Beach in Florida, from the 6th - 10th of
November 2023.

A discounted rate has been negotiated for those that would like to stay at
the hotel. If you wish to do so, please be sure to follow the link listed
below. This page will ensure the contracted rate for the room, with
discounted self-parking and complimentary guest room Wi-Fi included.

Booking Steps:
1. Reservation Website: CASPER WORKSHOP 2023 (hilton.com)

2. Click on Book a room
3. Enter your Arrival/Departure Dates and the number of guests in the room
4. Confirm Reservation with Contact Details and Credit Card

 Telephone Booking Steps:
1. Reservation Telephone: 1-866-580-7402
2. Provide the group code: CASPER
3. Provide your Arrival/Departure Dates and the number of guests in the room
4. Confirm Reservation with Contact Details and Credit Card

During the workshop, a visit to the nearby Kennedy Space Center Visitor
Center will be arranged.

General information about the workshop can be found at:
https://casper.astro.berkeley.edu/workshop2023/

Please forward this announcement to anyone who would be interested, and if
you have any questions or issues, please email the LOC: casper2...@ucf.edu

Hoping to see you all in November,
Jonathon

On behalf on the LOC:

Robert Bernath - UCF
Robert Brown - UCF
Allison Cross - UCF
Kara Kennedy - UCF
John Kiriazes - UCF
Hamid Rassoul - FIT

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[casper] CASPER Workshop 2023 - Registration & Payment Open

[Jonathon Kocz]

A few quick additional notes on the CASPER workshop:

1) For anyone who has been holding off, the payment system for registration
<https://casper.astro.berkeley.edu/workshop2023/registration/>is now also
set up.
2) Early registration ($400) will finish on July 31. General
registration ($450) will continue until August 31.
3) The hotel block (details below) will remain available through July and
August, but we encourage those that plan to stay at the conference hotel to
book early.

Best regards,
Jonathon

On behalf of the LOC:

Juan Avendano Arbelaez - FIT
Robert Bernath - UCF
Robert Brown - UCF
Allison Cross - UCF
John Kiriazes - UCF
Luis Quiroga - FIT
Hamid Rassoul - FIT

On Fri, 30 Jun 2023 at 06:50, Jonathon Kocz wrote:

> Dear Colleagues,
>
> I am pleased to announce that registration
> <https://casper.astro.berkeley.edu/workshop2023/registration/>for the
> CASPER Workshop 2023 is now open. Please note that due to a delay with the
> payment processing system, we will collect the registration fee separately
> at a later date.
>
> The workshop will be hosted by The University of Central Florida, and held
> at the Hilton Hotel at Cocoa Beach in Florida, from the 6th - 10th of
> November 2023.
>
> A discounted rate has been negotiated for those that would like to stay at
> the hotel. If you wish to do so, please be sure to follow the link listed
> below. This page will ensure the contracted rate for the room, with
> discounted self-parking and complimentary guest room Wi-Fi included.
>
> Booking Steps:
> 1. Reservation Website: CASPER WORKSHOP 2023 (hilton.com)
> <https://www.hilton.com/en/attend-my-event/ccbchhf-casper-e767dde8-084a-4072-a3c8-63206b75a5d0/>
> 2. Click on Book a room
> 3. Enter your Arrival/Departure Dates and the number of guests in the room
> 4. Confirm Reservation with Contact Details and Credit Card
>
>  Telephone Booking Steps:
> 1. Reservation Telephone: 1-866-580-7402
> 2. Provide the group code: CASPER
> 3. Provide your Arrival/Departure Dates and the number of guests in the
> room
> 4. Confirm Reservation with Contact Details and Credit Card
>
> During the workshop, a visit to the nearby Kennedy Space Center Visitor
> Center will be arranged.
>
> General information about the workshop can be found at:
> https://casper.astro.berkeley.edu/workshop2023/
>
> Please forward this announcement to anyone who would be interested, and if
> you have any questions or issues, please email the LOC: casper2...@ucf.edu
>
> Hoping to see you all in November,
> Jonathon
>
> On behalf on the LOC:
>
> Robert Bernath - UCF
> Robert Brown - UCF
> Allison Cross - UCF
> Kara Kennedy - UCF
> John Kiriazes - UCF
> Hamid Rassoul - FIT
>
>

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Re: [casper] zcu216_tut_onehundred_gbe.slx

[Jonathon Kocz]

The port order is read from the platform yaml file (for the zcu216, see:
https://github.com/casper-astro/mlib_devel/blob/m2021a/jasper_library/platforms/zcu216.yaml#L131-L152).
Worth double checking, but from a quick glance it looks like order 0,1,2,3,
which from https://docs.xilinx.com/v/u/en-US/ug1390-zcu216-eval-bd (p49) is
left top, left lower, right top, right lower.

Cheers,
Jonathon

On Mon, 31 Jul 2023 at 01:56, Gianni Comoretto 
wrote:

> A related question. How are the 4 SFP ports mapped to the 4 channels in
> the 100GB? In other words, which connector of the breakout cable must be
> plugged in each of the 4 cages?
>
> Thank you
>
> Gianni
> Il 31/07/23 09:03, David Harold Edward MacMahon ha scritto:
>
> Hi, Mitch,
>
> Does this mean that the four ports on the ZCU216 can function as a single
> 100 GbE interface?  If so, then I'll need to amend my response to Ken in a
> different thread.
>
> Thanks,
> Dave
>
> On Jul 30, 2023, at 22:28, Mitch Burnett 
>  wrote:
>
> Ken,
>
> If you plan to use fiber you can use this MTP to 4 UPC/LC breakout cable:
> https://www.fs.com/products/68059.html With these generic SFP28
> transceivers for the LC end: https://www.fs.com/products/75296.html
>
> The MTP end of the connector will need to have a transceiver programmed to
> be compatible for your target NIC/switch. For example, targeting a Mellanox
> NIC you can purchase the following transceiver making sure to select the
> “Mellanox” compatible configuration:
> https://www.fs.com/products/71009.html
>
> If you want to use copper cables you can purchase this 100G to 4x25G
> breakout cable:
> https://www.fs.com/products/49617.html?attribute=10201&id=197844
>
> When choosing cooper, make sure the configuration is the “dual
> compatibility” solution. This configuration will have “end A” targeting
> your hardware brand that the QSFP28 end will plug into (e.g., select
> Mellanox for a Mellanox NIC) and that “end B” is selected to be “generic”.
> For copper, it is also not recommended to purchase lengths longer than 3
> meters.
>
> A few other notes to get the ZCU216 100G running. Jumpers need to be
> installed on each of the 4 headers next to the 4x SFP28 cage to enable
> transmit. See the ZCU216 UG for more information regarding this. The
> reference clock for the 100G CMAC also needs to be programmed. For this,
> there is a `prg_8a34001` binary distributed with the CASPER ZCU216 image in
> the `/home/casper/bin` directory.
>
> Hope this helps,
>
> Mitch
>
> On Jul 28, 2023, at 6:27 AM, Ken Semanov 
>  wrote:
>
> 
> Dear Mitch,
>
> Thanks for the help with this.  Would you happen to know the make and
> model of the cable that was used for implementing the tutorial?  Also the
> receiving NIC?   I believe we have enough resources here to closely
> replicate your hardware.
>
>
>
> On Monday, July 24, 2023 at 7:20:45 PM UTC-4 Mitch Burnett wrote:
>
>> By default, the tool will targeting the first CMAC location in this case
>> it is the 4x25 SFP28 cage for the ZCU216.
>>
>> The 100G port option is the one you would want to select.
>>
>> Best,
>>
>> Mitch
>>
>> On Jul 24, 2023, at 3:40 PM, Ken Semanov  wrote:
>>
>> 
>>
>> A simulink model appears below with the hosting github. Is this tutorial
>> intended to target a ZCU216 with a mezzanine card containing a 100GbE port,
>> or is it intended to target to the J29 4xSFP28 cage?
>>
>> zcu216_tut_onehundred_gbe.slx
>>
>>
>> https://github.com/mitchburnett/tutorials_devel/tree/main/rfsoc/tut_onehundred_gbe
>>
>> In light of the above question, what should be the port configuration on
>> the receiving NIC?   The following options are available.  Thank you !
>>
>> 
>>
>>
>>
>>
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[casper] CASPER Workshop - General Registration

[Jonathon Kocz]

Dear Casperites,

Just a gentle reminder that general registration
for the
CASPER Workshop 2023 is closing at the end of August. If you would like to
attend, but need more time to register, please let the LOC know.

The workshop will be hosted by The University of Central Florida, and held
at the Hilton Hotel at Cocoa Beach in Florida, from the 6th - 10th of
November 2023.

A discounted rate has been negotiated for those that would like to stay at
the hotel. If you wish to do so, please be sure to follow the link listed
below. This page will ensure the contracted rate for the room, with
discounted self-parking and complimentary guest room Wi-Fi included.

Booking Steps:
1. Reservation Website: CASPER WORKSHOP 2023 (hilton.com)

2. Click on Book a room
3. Enter your Arrival/Departure Dates and the number of guests in the room
4. Confirm Reservation with Contact Details and Credit Card

During the workshop, a visit to the nearby Kennedy Space Center Visitor
Center will be arranged for those that wish to attend.

General information about the workshop can be found at:
https://casper.astro.berkeley.edu/workshop2023/

Please forward this announcement to anyone who would be interested, and if
you have any questions or issues, please email the LOC: casper2...@ucf.edu

Hoping to see you all in November,
Jonathon

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Re: [casper] Failed to build Casperfpga

[Jonathon Kocz]

Hi Bishnu,

It looks like the culprit is progska - which is a c program included in the
library for programming the SKARAB boards. You could manually remove the
dependency (you won't need it for rfsoc work) but it may be easier to
install the required os packages.

You will almost certainly need Kaj's suggested fix for running the
toolflow, but I think for installing casperfpga you will need to install
python3-dev and build-essential.

I do not unfortunately have a clean install to test on, but I think they
are the only two you should need:

$sudo apt install python3-dev
$sudo apt install build-essential

Cheers,
Jonathon


On Wed, 22 Nov 2023 at 00:58, Kaj Wiik  wrote:

> Hi Bishnu,
>
> I vaguely remember stumbling into this, the problem was a broken Linux
> release of Matlab. I found this from my notes:
>
> Ubuntu 20 comes with gcc 7.x to 9.x versions by default; you need to
> either install gcc 6.x manually or create a symbolic link using the
> following sudo commands:
> sudo ln -s /usr/include/asm-generic /usr/include/asm
> sudo ln -s /usr/include/x86_64-linux-gnu/sys /usr/include/sys
> sudo ln -s /usr/include/x86_64-linux-gnu/bits /usr/include/bits
> sudo ln -s /usr/include/x86_64-linux-gnu/gnu /usr/include/gnu
> Ubuntu 20 by default comes with dash shell. To avoid any issue that you
> may encounter while running the downstream AI Engine flows, it is
> recommended to change the shell from dash to bash using the following sudo
> command:
> sudo dpkg-reconfigure dash
>
> I found that installing gcc 6.x was difficult if not almost impossible
> (and possibilities to break your whole system), so I just created those
> links.
>
> There is a preinstalled Ubuntu virtual machine image made by Andrew
> Martens that works very well. If you are interested I can send you a
> download link.
>
> Cheers,
> Kaj
>
> On Wed, 22 Nov 2023 at 10:36, Bishnu Kumar Sharma <
> bksha...@asiaa.sinica.edu.tw> wrote:
>
>> Dear Community member,
>> I tried to install casperfpga from CASPER FPGA tutorial "
>> https://casper-toolflow.readthedocs.io/en/latest/src/Installing-the-Toolflow.html#";.
>> I am using Ubuntu 20.04 and python version is 3.8. While installing
>> casperfpga, i am getting error and it says
>> -
>> /usr/include/features.h:461:12: fatal error: sys/cdefs.h: No such file or
>> directory
>> 461 | #  include 
>> |^
>>   compilation terminated.
>>   error: command '/usr/bin/x86_64-linux-gnu-gcc' failed with exit
>> code 1
>>   [end of output]
>>
>>   note: This error originates from a subprocess, and is likely not a
>> problem with pip.
>>   ERROR: Failed building wheel for casperfpga
>>   Running setup.py clean for casperfpga
>> Failed to build casperfpga
>> ERROR: Could not build wheels for casperfpga, which is required to
>> install pyproject.toml-based projects
>> - I am attaching the
>> screenshot of it as well. I hope somebody can help me from here.
>> Thank you all.
>>
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[casper] Job opening - JPL

[Jonathon Kocz]

Hi all,

There is a job opening at JPL that may be of interest to some on the
mailing list. Details can be found at:

https://experienced-jpl.icims.com/jobs/4004/signal-analysis-engineer-ii/job

or if you have trouble with the link, go to:

http://www.jpl.nasa.gov/opportunities/

and search for number 2014-4004.

Cheers,
Jonathon

[casper] FFT problems

[Jonathon Kocz]

Hi Casper,

While we're talking weird FFT problems...

I have experienced an interesting problem with the FFT libraries when
compiling for ROACH2, that I'm hoping someone might be able to explain.

I have tried multiple versions of the libraries, and various branches
(latest CASPER, SKA-SA, SMA), on Ubuntu, CentOS, RedHat and Windows, all
using Xilinx 14.7 and Matlab 2012b, but the error stays the same: the FFT
(various sizes/number of inputs/wb/biplex_2x/biplex_4x) simulates fine, but
when I compile I get zeros for some of the outputs.

After various experiments, I found that if I black box the FFT, and then
include it in the design, everything works, so I'm presuming the problem is
something in the system generator options when run by the tool flow.

Can anyone help me out with an explanation for why this might occur?

Thanks,
Jonathon

Re: [casper] Matlab path is not determined when running startsg.local

[Jonathon Kocz]

Hi Srinath,

This problem is caused when using newer versions of Ubuntu. The easiest way
I've found to fix it is to edit the Xilinx .settings64 files, so that they
point to the system libraries first, instead of the Xilinx ones.

e.g in the four paths you listed, move the current LD_LIBRARY_PATH
declaration from the end of the line to the start:

So

if [ -n "$LD_LIBRARY_PATH" ]; then
  LD_LIBRARY_PATH=${XILINX_EDK}/lib/lin64:${LD_LIBRARY_PATH};export
LD_LIBRARY_PATH;

becomes


if [ -n "$LD_LIBRARY_PATH" ]; then
  LD_LIBRARY_PATH=:${LD_LIBRARY_PATH}:${XILINX_EDK}/lib/lin64;export
LD_LIBRARY_PATH;


Cheers,
Jonathon


On 29 November 2016 at 01:50, srinath.reddy 
wrote:

> Hi,
>
> I encountered following error after updating Ubuntu 16.04 to classic
> gnome. How to rectify this error?
>
> Reading local definitions from './startsg.local'
> . /opt/Xilinx/14.7/ISE_DS/common/.settings64.sh
> /opt/Xilinx/14.7/ISE_DS/common
> . /opt/Xilinx/14.7/ISE_DS/EDK/.settings64.sh /opt/Xilinx/14.7/ISE_DS/EDK
> . /opt/Xilinx/14.7/ISE_DS/PlanAhead/.settings64.sh
> /opt/Xilinx/14.7/ISE_DS/PlanAhead
> . /opt/Xilinx/14.7/ISE_DS/ISE/.settings64.sh /opt/Xilinx/14.7/ISE_DS/ISE
> awk: symbol lookup error: awk: undefined symbol: mpfr_z_sub
>
> Internal error 2: Could not determine the path of the
>   MATLAB root directory.
>
>   original command path = /usr/local/MATLAB/R2012b/bin/
> matlab
>   current  command path = /usr/local/MATLAB/R2012b/bin/
> matlab
>
>   Please contact:
>
>   MathWorks Technical Support
>
>   for further assistance.
>
> WARNING: XILINX_PLATFORM is not defined in the current environment,
> assuming 'lin64'.
> Using MATLAB_PATH=/usr/local/MATLAB/R2012b
> Using XILINX_PATH=/opt/Xilinx/14.7/ISE_DS
> Using XILINX_PLATFORM=lin64
> Using MLIB_DEVEL_PATH=/home/srinath/casper/mlib_devel-master
> awk: symbol lookup error: awk: undefined symbol: mpfr_z_sub
>
> Internal error 2: Could not determine the path of the
>   MATLAB root directory.
>
>   original command path = /usr/local/MATLAB/R2012b/bin/
> matlab
>   current  command path = /usr/local/MATLAB/R2012b/bin/
> matlab
>
>   Please contact:
>
>   MathWorks Technical Support
>
>   for further assistance.
>
> --
> P.Srinath Reddy,
> Integrated M.Tech-PhD(2015),
> IIA.
>
>

Re: [casper] MATLAB startup error

[Jonathon Kocz]

Forwarding to the mail list to archive the solution.

Setting the default LD_LIBRARY_PATH is also required for the solution
mentioned in https://www.mail-archive.com/casper@lists.berkeley.edu/msg06
619.html to work.

-- Jonathon

-- Forwarded message --
From: Jonathon Kocz 
Date: 2 May 2017 at 08:48
Subject: Re: [casper] MATLAB startup error
To: Franco 


Hi Franco,

Do you have a default LD_LIBRARY_PATH set? You probably want it to be (in
addition to anything specific you need) LD_LIBRARY_PATH=/usr/lib/x86_
64-linux-gnu/:/lib/x86_64-linux-gnu:/lib64/:/lib/

Let me know if this helps!

Cheers,
Jonathon



On 1 May 2017 at 21:46, Franco  wrote:

> Dear all,
>
>
> I tried to load MATLAB today as I do everyday when I suddenly got this
> error:
>
>
> Reading local definitions from './startsg.local'
> Using MATLAB_PATH=/home/franco/Software/STEM/MATLAB-R2013a
> Using XILINX_PATH=/home/franco/Software/STEM/Xilinx-ISE/14.7/ISE_DS
> Using XILINX_PLATFORM=lin64
> Using MLIB_DEVEL_PATH=/home/franco/Software/Workspace/Calan/mlib_d
> evel_calan
> awk: symbol lookup error: awk: undefined symbol: mpfr_z_sub
>
> Internal error 2: Could not determine the path of the
>   MATLAB root directory.
>
>   original command path = /home/franco/Software/STEM/MAT
> LAB-R2013a/bin/matlab
>   current  command path = /home/franco/Software/STEM/MAT
> LAB-R2013a/bin/matlab
>
>   Please contact:
>
>   MathWorks Technical Support
>
>   for further assistance.
>
> I did what is suggested in this previous answer:
> https://www.mail-archive.com/casper@lists.berkeley.edu/msg06619.html, but
> it didn't worked. Does anyone has any other idea?
>
>
> Thanks,
>
>
> Franco
>
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Re: [casper] Problems with the corr library

[Jonathon Kocz]

Hi Roberto,

If you downgrade the construct library to version 2.5.5-reupload that
should fix things.

Cheers,
Jonathon


On May 17, 2017 12:17, "Roberto F."  wrote:

Hi there,

I upgraded the python library to version 0.7.3.
When I run a python script I get the following error:

 from corr import katcp_wrapper
  File "/usr/local/lib/python2.7/dist-packages/corr/__init__.py", line 11,
in 
import cn_conf, katcp_wrapper, log_handlers, corr_functions, corr_wb,
corr_nb, corr_ddc, scroll, katadc, iadc, termcolors, rx, sim, snap
  File "/usr/local/lib/python2.7/dist-packages/corr/corr_wb.py", line 13,
in 
construct.Flag('tvgsel_noise'), # 20
TypeError: 'Mapping' object is not callable

I don't know why this is happening.

Greatings
_


Roberto M. Fuentes P.

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[casper] CASPER Workshop 2017 - Student Support & Registration Reminder

[Jonathon Kocz]

Hi All,

Some funding to support student attendance at the CASPER Workshop 2017 has
become available for students based at US institutions. If you are, or
have, a graduate or undergraduate student who who would like to attend,
please reply to this email or send a note to the organizing committee.

Also, just a gentle reminder that general registration for the CASPER
workshop is scheduled to close on June 30.  Registration can be made at the
conference website:
http://www.tauceti.caltech.edu/casper-workshop-2017/registration/

If you are planning on attending, but do not think you will be able to
register by this date, please contact the organizing committee.

Best regards,
Jonathon

(on behalf of the LOC).

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Re: [casper] Trouble compiling tutorial 1

[Jonathon Kocz]

Hi Colin,

It looks to me like your design is compiling fine (generating the .bit and
.bin files), but that there is a issue with the final script that turns the
.bin file into the .bof file that we load onto the hardware.

Under the model directory, there will be an XPS_ROACH_BASE (or
XPS_ROACH2_BASE) directory, that will have a "gen_prog_files.bat" script.
If you manually run that script (or the commands in that script)  via a
command window  (you really only need the mkbof.exe line: "mkbof.exe -o
implementation\system.bof -s core_info.tab -t 3 implementation\system.bin")
that should generate the .bof file that you need to upload.

There is probably a permanent fix for this, but I'm not sure 100% sure what
the cause is. - Is it recognizing windows as your OS when you first start
running the toolflow? It could be that it's trying to run the wrong command
for windows, or that the gen_prog_files.bat script needs an update to deal
with newer versions of windows.

Hope this helps,

Jonathon





On 28 June 2017 at 09:21,  wrote:

> Hi everyone,
>
> I am having trouble compiling tutorial 1 from the casper site.
> I have come across a few errors for which I found solutions to in the mail
> archive but I cannot find a solution to my current error.
>
> "Running Bitgen.."
> "*"
> cd implementation & bitgen -w -f bitgen.ut system & cd ..
> Release 14.7 - Bitgen P.20131013 (nt64)
> Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
> PMSPEC -- Overriding Xilinx file
>  with local file
> 
> Loading device for application Rf_Device from file '5vsx95t.nph' in
> environment
> C:\Xilinx\14.7\ISE_DS\ISE\;C:\Xilinx\14.7\ISE_DS\EDK.
>"system" is an NCD, version 3.2, device xc5vsx95t, package ff1136,
> speed -1
> Opened constraints file system.pcf.
>
> Wed Jun 28 17:07:21 2017
>
> Running DRC.
> WARNING:PhysDesignRules:367 - The signal  is
>incomplete. The signal does not drive any load pins in the design.
> DRC detected 0 errors and 1 warnings.  Please see the previously displayed
> individual error or warning messages for more details.
> Creating bit map...
> Saving bit stream in "system.bit".
> Saving bit stream in "system.bin".
> Bitstream generation is complete.
> '.' is not recognized as an internal or external command,
> operable program or batch file.
>
> : Programation files generation failed, EDK compilation probably also
> failed.
> Backtrace 1: gen_xps_files:701
> Backtrace 2: run_Callback:158
> Backtrace 3: casper_xps:88
> Backtrace 4: @(hObject,eventdata)casper_xps('run_Callback',hObject,
> eventdata,guidata(hObject)):0
>
> Everything seems to run fine until I get to the  "Running Bitgen.."part
> and then I run into 'Programation files generation failed, EDK compilation
> probably also failed' and no files get generated. I also get an error popup
> from matlab which is attached, stating "error detected running casper xps:
> Programation files generation failed, EDK compilation probably also failed"
>
> I am running Xilinx 14.7 with pcores added from 11.x with Matlab 2013a.
>
> Any help would be much appreciated.
>
> Regards,
>
> Colin.
>
>
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[casper] CASPER Workshop 2017 - Registration Closing

[Jonathon Kocz]

Hi All,

Just a last reminder that registration for the CASPER Workshop 2017 is
closing tomorrow, June 30th.

The workshop runs for one week, the 14th - 18th August, and consists of
presentations in the morning, followed by various hands-on tutorials and
break out sessions in the afternoon.

Registration can be made at the conference website:
http://www.tauceti.caltech.edu/casper-workshop-2017/registration/

If you will need to register late, and have not already contacted the LOC,
please reply to this email.

Best regards,
Jonathon

(on behalf of the LOC).

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[casper] CASPER Workshop 2017 - Video Access

[Jonathon Kocz]

Hi All,

For those who are interested in the talks at the CASPER workshop this year,
but were unable to attend, we will be attempting to stream the
presentations online as we go via BlueJeans at:

 https://bluejeans.com/545091626

The schedule for the presentations can be found at:
http://www.tauceti.caltech.edu/casper-workshop-2017/agenda/

Best wishes,
Jonathon

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[casper] CASPER Workshop 2017 - New Video Access

[Jonathon Kocz]

Hi All,

For some reason out conference video link expired early.

The updated meeting number for today is: 4387584875

Best wishes,
Jonathon

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Re: [casper] Warnings with new mlib_devel

[Jonathon Kocz]

Hi Franco,

It's probably the Matlab 2013a version that's causing the warning. If you
switch to 2013b it should go away.

(As you found from your simple model, you can ignore the warning and stick
with 2013a, but if you're opening a model with an FFT or similar, it can
take a *long* time to get through all the warnings).

Hope this helps,
Jonathon

On 2 January 2018 at 06:51, Franco Curotto  wrote:

> Dear all,
>
> I'm doing a fresh install of mlib_devel for ROACH and ROACH2 programming.
> I cloned the repository from github.com/casper-astro/mlib_devel, and
> switched to roach2 branch. I setup the startsg.local for my version of
> Xilinx ISE (14.7) and Matlab (2013a), but when I start Matlab I get a bunch
> of warnings like this:
>
> Warning: xps_library.mdl, line 31617: line does not have a parameter named
> 'ZOrder'
> > In load_system at 21
>   In startup at 24
>   In matlabrc at 188
>
> I compiled a simple model for testing and it worked, but I'm wonder if
> those warnings are important, or is normal behavior. Should I switch to
> another mlib_devel/Matlab/Xilinx version?
>
> Thanks,
>
> Franco Curotto
>
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[casper] ROACH2 Power off when V6 eth disconnected

[Jonathon Kocz]

Hi all,

We're running a set of ROACH2 spectrometers, all using the V6 1GbE to
transmit data.

During some reconfiguration, we noticed that when disconnecting the V6
ethernet cables, some of the ROACH2s occasionally power off.

Is this a known issue I've somehow managed to miss?

Cheers,
Jonathon

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[casper] CASPER Conference Breakout Session Suggestions

[Jonathon Kocz]

Hi All,

As has become standard with the CASPER conference, there will be breakout
sessions to discuss topics of interest to the community.

There will be some time to discuss topics at the conference, but if you
have a particular topic in mind you know you would like to bring up please
send me an email* with suggestions.

Previous popular topics have included:

   - GPUs
   - Future FPGA Hardware
   - ADCs
   - CASPER Wiki/Documentation

Cheers,
Jonathon

* remember that by default if you reply to this email it will probably go
to the whole list, I recommend double checking the email address.

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Re: Re: [casper] ROACH Network is unreachable

[Jonathon Kocz]

I know you had this running earlier, but looking at the printenv, I'm
wondering if you're actually doing an mmcboot rather than netboot. (rather
than typing "boot", perhaps try "run netboot" specifically).

The stale nfs filehandle is something a few people have encountered when
using mmcboot.

One potential solution might be:

https://www.mail-archive.com/casper@lists.berkeley.edu/msg03241.html

Cheers,
Jonathon


On Wed, 19 Jun 2019 at 03:28, zhang laiyu  wrote:

>Thanks Mars.
> I had checked the file: /etc/network/interfaces. It is the same
> configuration as what I set before and operated very well several days
> before.
> I found some warning  information such as: find: ./sshd.pid: Stale NFS
> file handle
> I had resort to internet but not solved it.
>
> JACK: can you give me some suggestion?
>
> > -Original Messages-
> > From: Marc 
> > Sent Time: 2019-06-19 16:03:51 (Wednesday)
> > To: casper@lists.berkeley.edu
> > Cc: jackhick...@gmail.com
> > Subject: Re: [casper] ROACH Network is unreachable
> >
> > On 6/18/19, zhang laiyu  wrote:
> > ...
> > > Starting NTP server: ntpdstart-stop-daemon: open pidfile
> /var/run/ntpd.pid:
> > > Stale NFS file handle (Stale)
> > >  failed!
> > >
> > > tcpborphserver: starting
> > >
> > > SIOCADDRT: Network is unreachable
> > >
> >
> > Could it be that something in /etc/network/interfaces isn't
> > configured, or that a route is being initialised that doesn't make
> > sense on the current network ?
> >
> > regards
> >
> > marc
> >
> > --
> > You received this message because you are subscribed to the Google
> Groups "casper@lists.berkeley.edu" group.
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> an email to casper+unsubscr...@lists.berkeley.edu.
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> .
>
>
> --
> Cheers!
> >
> ZHANG Laiyu
> Phone(China)   010-88236415
> Cellphone(China)   13681385567
> E-mail:zhan...@ihep.ac.cn
> Address:   19B Yuquan Road,Shijingshan District,Beijing，China
> Department:Center for Particle Astrophysics
> Office:Astrophysics Building 205Institute of High Energy
> Physics, CAS
> web: http://www.ihep.cas.cn
> >
>
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Re: [casper] python problem

[Jonathon Kocz]

If you can't update tcpborphserver, I recommend going with the other
suggestion of:

katcp=0.5.5
corr=0.7.3

you'll also possibly need older versions of some other packages (there was
a while I had to downgrade construct to 2.5.5).

you can then access the fpga via:

import corr
fpga = corr.katcp_wrapper.FpgaClient('ipaddress')

-- Jonathon


On Thu, 22 Aug 2019 at 13:55, Jack Hickish  wrote:

> The latest Casperfpga from GitHub should be fine. The problem is likely at
> the server end (which is why your tcpborphserver is complaining that
> Casperfpga is using commands it doesn't understand).
> If you can update that using the info in the mailarchive links you should
> be able to get going.
>
> On Thu, 22 Aug 2019, 1:49 pm luis javier Ulloa, 
> wrote:
>
>> Hi ... Thanks for the help ...
>> Ho no, any recommendations? ... I had a hard time getting a roach2 that
>> worked (I had to throw the previous card in the trash), which casperfpga
>> version will be good for me?
>> regards
>>
>> El jue., 22 ago. 2019 a las 15:43, Jack Hickish ()
>> escribió:
>>
>>> Howdy,
>>>
>>> This is a compatibility error between the version of casperfpga and
>>> tcpborphserver (which is the process running on the roach2 which
>>> listens for commands).
>>> casperfpga has never been particularly well supported on roach2 with
>>> the stock software supplied by digicom.
>>>
>>> If you checkout the message at
>>> https://www.mail-archive.com/casper@lists.berkeley.edu/msg07428.html
>>> that should give you some options. You can either use the ancient
>>> "corr" library, or try and update your tcpborphserver install. There
>>> is also a link here --
>>> https://www.mail-archive.com/casper@lists.berkeley.edu/msg07451.html
>>> -- to a complete roach2 filesystem (the one we use in Berkeley) which
>>> should support ROACH2 with the latest casperfpga.
>>>
>>> Sorry this doesn't work out the box, but glad you're getting closer to
>>> success...
>>>
>>> Cheers
>>> Jack
>>>
>>> (also, FWIW, the "correct" way of instantiating a casperfpga object is:
>>> ```
>>> fpga = casperfpga.CasperFpga('192.168.6.19')
>>> ```
>>>
>>> or, if you know it is a roach board speaking katcp you can do:
>>>
>>> ```
>>> fpga = casperfpga.CasperFpga('192.168.6.19',
>>> transport=casperfpga.KatcpTransport)
>>> ```
>>>
>>> On Thu, 22 Aug 2019 at 13:30, luis javier Ulloa
>>>  wrote:
>>> >
>>> > Hello everyone, I am in a similar problem, everything seems to be
>>> going very well, the steps I follow are the following:
>>> > cd / path / to / casperfpga
>>> > git payment v0.4.3
>>> > sudo python setup.py install
>>> >
>>> > deleting the files previously as mentioned in the mail ...
>>> >
>>> > on the home route, where Casperfpga is located inside the terminal:
>>> > >> ipyton
>>> > >> fpga = casperfpga.katcp_fpga.KatcpFpga ('IP roach2')
>>> > >> fpga.upload_to_ram_and_program ('.fpg file directory')
>>> > After that he returns the following:
>>> >
>>> >
>>> ---
>>> > RuntimeError  Traceback (most recent call
>>> last)
>>> >  in ()
>>> > > 1 fpga.upload_to_ram_and_program('roach2_tut_intro.fpg')
>>> >
>>> > /usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
>>> upload_to_ram_and_program(self, filename, port, timeout, wait_complete)
>>> > 442 if request_result != '':
>>> > 443 raise RuntimeError('progremote request(%s) on host
>>> %s failed' %
>>> > --> 444(request_result, self.host))
>>> > 445
>>> > 446 # start the upload thread and join
>>> >
>>> > RuntimeError: progremote request(Request to client 192.168.6.19
>>> failed.) on host 192.168.6.19 failed
>>> >
>>> > In [15]: fpga.upload_to_ram_and_program('roach2_tut_intro.fpg')
>>> >
>>> ---
>>> > RuntimeError  Traceback (most recent call
>>> last)
>>> >  in ()
>>> > > 1 fpga.upload_to_ram_and_program('roach2_tut_intro.fpg')
>>> >
>>> > /usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
>>> upload_to_ram_and_program(self, filename, port, timeout, wait_complete)
>>> > 442 if request_result != '':
>>> > 443 raise RuntimeError('progremote request(%s) on host
>>> %s failed' %
>>> > --> 444(request_result, self.host))
>>> > 445
>>> > 446 # start the upload thread and join
>>> >
>>> > RuntimeError: progremote request(Request to client 192.168.6.19
>>> failed.) on host 192.168.6.19 failed
>>> >
>>> >
>>> >
>>> > at the same time that by means of a minicom I verify that from the
>>> roach there is ping towards my pc, at the moment that in ipython it throws
>>> the previous message, in the roach it throws me: call: no dispatch function
>>> for? progremote.
>>> > I enclose a screenshot with the above.
>>> > regards.
>>> >
>>> >
>>> >
>>> > El mar., 

Re: [casper] Compiling for roach2 on RHEL7

[Jonathon Kocz]

Hi Michael,

You might be able to get 2014b to play nicely with the toolflow, but 2013b
was the last supported version for ISE 14.7, so it would be better to go
with that if you can. What sort of OS errors are you getting?

One alternative, if you can't get RHEL to work, might be to create a VM of
e.g. ubuntu 16.04 or similar to spin up when you need to do ROACH2 work.

Cheers,
Jonathon



On Tue, 30 Jun 2020 at 13:29, Michael D'Cruze <
michael.dcr...@manchester.ac.uk> wrote:

> Hi everyone,
>
>
>
> I’m clutching at straws a little, but I’ve recently obtained a RHEL7
> system for use with the Vivado toolflow. What we’d really like is to be
> able to compile models using the “old” ISE toolflow on this new machine. I
> wondered if anyone had been able to make this happen? I’ve got RHEL 7.8,
> various Matlab versions, and ISE 14.7.
>
>
>
> There appear to be some fairly fundamental compatibility issues between
> the OS and Matlab versions prior to 2014b, though I’m going to ask our
> local IT support to look at this. Versions at least 2016b and later throw a
> tantrum when casper_xps is run. 2014b is the most promising at the moment,
> getting a fair way through casper_xps before complaining about certain
> Matlab files requiring absolute paths. An internet search doesn’t yield
> anything promising.
>
>
>
> Anyway, if you’ve been able to make a combination similar to what I’ve got
> work correctly, please get in touch.
>
>
>
> Thanks!
> Michael
>
>
>
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Re: [casper] Help with timing constraint

[Jonathon Kocz]

Hi Heystek,

One other question: How fast is the clock rate you are trying to compile?
For ROACH2, if you're above a 200MHz clock (and definitely if you're above
250MHz), or if you have a very full design, I've often found that you need
to use PlanAhead to make the design meet timing.

A (very outdated) set of instructions on how to run planAhead is here:
https://casper.ssl.berkeley.edu/wiki/Tutorial_PlanAhead

Opening up the design in PlanAhead should give you the option to interact
with the failing timing paths manually.

If you just wanted to browse the timing report, it should be under:
/XPS_ROACH2_BASE/implementation/system_map.twr

Cheers,
Jonathon


On Thu, 27 Aug 2020 at 15:24, David MacMahon  wrote:

> Hi, Heystek,
>
> I think the build will generate a timing report in a file that ends with
> ".twr".  If it's not, you can generate one using the "trce" utility (part
> of ISE).  This will tell you how many nets failed timing and show details
> of the N worst offenders (I think N defaults to 3 or maybe 10?).  If you
> have a large number of nets failing timing it's likely more difficult to
> rectify, but if there's only a few it's usually not too hard to resolve.
>
> Happy hunting,
> Dave
>
> On Aug 27, 2020, at 04:46, Heystek Grobler 
> wrote:
>
> Hey Andrew and James and everyone.
>
> After probed around and the following timing constraint is not met:
>
> TS_sys_clk_n
>
> I assume that my system clock is not running at an appropriate frequency?
>
> Thanks for the help!
>
> Heystek
>
>
>
> On Wed, Aug 26, 2020 at 10:59 AM Andrew Martens  wrote:
>
>> Hi Heystek
>>
>> Output reports and their location change over versions, between ISE and
>> Vivado etc. I think the output reports for ISE are located in the
>> 'implementation' folder. I think the timing related ones have 'timing' in
>> the name... A quick Google search of the error will help.
>>
>> Note that there are archives of the mailing list available at
>> https://www.mail-archive.com/casper@lists.berkeley.edu/ - your problem
>> has probably been answered already previously.
>>
>> Regards
>> Andrew
>>
>> On Wed, Aug 26, 2020 at 10:49 AM Andrew van der Byl 
>> wrote:
>>
>>> Hi Heystek,
>>>
>>> It's possible that you then have another issue that causes the build
>>> process to exit prior to generating that file. You'll need to debug that
>>> first.
>>>
>>> Regards,
>>> Andrew
>>>
>>> On Wed, Aug 26, 2020 at 10:40 AM Heystek Grobler <
>>> heystekgrob...@gmail.com> wrote:
>>>
 Hey Andrew

 It is strange, I cant seem to locate top_timing_summary_routed.rpt

 I am running Matlab 2012B with ISE 14.7



 On 26 Aug 2020, at 10:27, Andrew van der Byl  wrote:

 Hi Heystek,

 1) Navigate to your project folder
 2) Then go to and open: /myproj/myproj.runs/impl_1/
 top_timing_summary_routed.rpt

 Just a note - this file is usually fairly large as text files go ~20MB.

 Regards,
 Andrew

 On Wed, Aug 26, 2020 at 10:22 AM Heystek Grobler <
 heystekgrob...@gmail.com> wrote:

> Hey James and Andrew
>
> Thank you so much for the advice!
>
> @Andrew, this might be a stupid question, but where do I locate the 
> top_timing_summary_routed.rpt
> file?
>
> Heystek
>
>
> On 26 Aug 2020, at 10:17, Andrew van der Byl  wrote:
>
> Hi Heystek,
>
> Have a look in top_timing_summary_routed.rpt and search for 'VIOLATED'
> - this usually shows up which paths are hurting your design. Then, as 
> James
> said, start pipeling your design.
>
> Hope this helps.
>
> Regards,
> Andrew
>
> On Wed, Aug 26, 2020 at 10:13 AM James Smith  wrote:
>
>> Hello Heystek,
>>
>> You will have to go through the timing reports and see which signal
>> path is failing timing, and by how much.
>>
>> Once you have an idea, you will need to sprinkle delay blocks and /
>> or adjust latencies in your logic to get to a point where the
>> place-and-route can find a layout that satisfies timing requirements.
>>
>> It's a bit of a black art, always hit and miss for me.
>>
>> Regards,
>> James
>>
>>
>>
>>
>> On Wed, Aug 26, 2020 at 8:00 AM Heystek Grobler <
>> heystekgrob...@gmail.com> wrote:
>>
>>> Good day everyone
>>>
>>> I am running a design but ran into this problem:
>>>
>>> xflow done!
>>> touch __xps/system_routed
>>> xilperl /opt/Xilinx_ISE/14.7/ISE_DS/EDK/data/fpga_impl/
>>> observe_par.pl -error yes implementation/system.par
>>> Analyzing implementation/system.par
>>>
>>> 
>>> ERROR: 1 constraint not met.
>>>
>>> PAR could not meet all timing constraints. A bitstream will not be
>>> generated.
>>>
>>> To disable the PAR timing check:
>>>
>>> 1> Disable the "Treat timing 

[casper] Ultrascale+HBM DSP48's + CASPER FFT

[Jonathon Kocz]

Hi CASPER,

I was wondering if anyone had encountered difficulties in compiling larger
CASPER FFTs for Ultrascale+ HBM devices?

I have found I can compile the CASPER FFTs fine for Ultrascale+ devices,
but HBM devices seem to object ("Cannot target DSP48 on this device,
virtexuplusHBM").

As far as I know DSP48E2 should be backward compatible with DSP48E1 (and
certainly as other Ultrascale+ devices will compile, this seems to be true).

The only thing I've been able to find specifically relating to HBM devices
is that the number you can cascade may be different due to the difference
in SLRs with the HBM interface (UG579).

Is this just Simulink needing an update (I've tried Vivado 2019.1.1 and
2019.2, both with Matlab 2019a), do we finally need to explicitly change
the DSP48's in the toolflow to be E2 for devices like this, or is there
something more fundamental I'm missing?

Thanks,
Jonathon

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Re: [casper] Ultrascale+HBM DSP48's + CASPER FFT

[Jonathon Kocz]

Thanks Adam. Good to know it wasn't just me!

As an update: I installed Vivado 2020.1 this afternoon. Running with matlab
2019a it does seem they fixed the issue, and it compiles without error.

Caveat: I've only tested with simple counters. I haven't yet looked to see
what in the toolflow might need updating before it is fully compatible with
vivado 2020.

Cheers,
Jonathon

On Fri, 28 Aug 2020 at 03:55, Adam Isaacson  wrote:

> Hi Jonathon,
>
> We have the same issue for our 1K channeliser using the Alveo U280 boards
> - see screen capture. To fix this we changed the Simulink counters not to
> use DSP - not very practical, but at least we got the compile through. I
> have looked at the DSP architecture for the Virtex UltraScale+ with HBM and
> it definitely has the DSP architecture. We used Matlab R2018a and Vivado
> 2019.1.1 and Vivado 2019.2 - they all had this issue. I believe it to be a
> Simulink/sysgen bug. I never got around to logging a support request with
> Xilinx yet, as we were focusing on the Alveo U280 100GbE testing. We
> haven't looked into this much more yet.
>
> This is from Andrew van der Byl: "The - a snag.There seems to be an
> issue when counters are set to use DSP logic. Jasper_frontend fails (see
> attached pic) if a counter is set to use DSP (it's fine when Fabric or
> behavioural is selected). You can regenerate the issue by changing any of
> the counters in the base design to use DSP. The DSP slices used in the
> PFB are fine though. I did have to change all counters in the design that
> by default are set to use DSP slices or the build would fail. Thought I'd
> give you the heads up. I'll start to work in the rest of the logic and
> build in some test logic as well".
>
> Kind regards,
>
> Adam Isaacson
> South African Radio Astronomy Observatory (SARAO)
> Hardware Manager
> Cell: (+27) 825639602
> Tel:  (+27) 215067300
> email: aisaac...@ska.ac.za
>
>
>
> On Fri, Aug 28, 2020 at 2:31 AM Jonathon Kocz  wrote:
>
>> Hi CASPER,
>>
>> I was wondering if anyone had encountered difficulties in compiling
>> larger CASPER FFTs for Ultrascale+ HBM devices?
>>
>> I have found I can compile the CASPER FFTs fine for Ultrascale+ devices,
>> but HBM devices seem to object ("Cannot target DSP48 on this device,
>> virtexuplusHBM").
>>
>> As far as I know DSP48E2 should be backward compatible with DSP48E1 (and
>> certainly as other Ultrascale+ devices will compile, this seems to be true).
>>
>> The only thing I've been able to find specifically relating to HBM
>> devices is that the number you can cascade may be different due to the
>> difference in SLRs with the HBM interface (UG579).
>>
>> Is this just Simulink needing an update (I've tried Vivado 2019.1.1 and
>> 2019.2, both with Matlab 2019a), do we finally need to explicitly change
>> the DSP48's in the toolflow to be E2 for devices like this, or is there
>> something more fundamental I'm missing?
>>
>> Thanks,
>> Jonathon
>>
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Re: [casper] RedPitaya Compilation Error: "script generated with Vivado <2019.1.1> beign run as <2019.1>"

[Jonathon Kocz]

Hi Xavi,

As I found recently, the block diagram tcl scripts are *really* pedantic
about the version they are run in. If it doesn't match, they just don't
run, and then the design can't be compiled.

Checking out git, it looks like this happened during the last hardware
porting workshop, and the docs should have been updated to be accurate a
few months ago. - It looks like they ask for Vivado 2019.1.1
https://casper-toolflow.readthedocs.io/en/latest/src/Installing-the-Toolflow.html,
but there might be a page we missed with old instructions. If there is one
with 2019.1 listed, can you let me know and I'll get it fixed.

A few things you could try:

1) Edit the tcl script for the block diagram so it checks for version
2019.1 instead of 2019.1.1 (a little risky, but it might work -
https://github.com/casper-astro/mlib_devel/blob/master/jasper_library/hdl_sources/infrastructure/red_pitaya.tcl
line 23)
2) Regenerate the block diagram as the error message suggests (a bit more
effort than 1, but not too bad)
3) Upgrading to 2019.1.1 should solve the problem.

Cheers,
Jonathon


On Tue, 8 Sep 2020 at 22:13, Xavier Bosch 
wrote:

> Hi all,
>
> I installed a fresh 16.04 Ubuntu with Xilinx Vivado 2019.1 and Matalb
> 2018a, as readthedocs suggested for the RedPitaya board.
> I am using the master branch from mlib_devel commit
> ee6841c5b6392e1a9e6b302e2edbe875034efdcf from Thu 28 May, 2020.
>
> I created the  pithon3 virtual environment and installed the requirements
> As a comment my stratsg.local file is correctly populated except for the
> variable  "XML2VHDL_PATH", that I do not know how to configure, it seems a
> new parameter to me.
>
> I succeeded in compiling an old SNAP design, no problems. Then I proceeded
> to do a new design inspired by the Wide-ish band Spectrometer Tutorial and
> I got an error message as follows (see screenshot):
>
>
> *ERROR: [BD_TCL-109] This script was generated using Vivado <2019.1.1> and
> is being run in <2019.1> of Vivado. Please run the script in Vivado
> <2019.1.1> then open the design in Vivado <2019.1>. Upgrade the design by
> running "Tools => Report => Report IP Status...", then run write_bd_tcl to
> create an updated script.*
> *WARNING: [Vivado 12-818] No files matched
> '/home/javierb/workspace/designs/rpitaya_test01/myproj/myproj.srcs/sources_1/bd/red_pitaya/red_pitaya.bd
> '*
> *# generate_target all [get_files [get_property directory
> [current_project]]/myproj.srcs/sources_1/bd/red_pitaya/red_pitaya.bd
> ]*
> *WARNING: [Vivado 12-818] No files matched
> '/home/javierb/workspace/designs/rpitaya_test01/myproj/myproj.srcs/sources_1/bd/red_pitaya/red_pitaya.bd
> '*
> *# make_wrapper -files [get_files [get_property directory
> [current_project]]/myproj.srcs/sources_1/bd/red_pitaya/red_pitaya.bd
> ] -top*
> *# add_files -norecurse [get_property directory
> [current_project]]/myproj.srcs/sources_1/bd/red_pitaya/hdl/red_pitaya_wrapper.vhd*
> *ERROR: [Vivado 12-172] File or Directory
> '/home/javierb/workspace/designs/rpitaya_test01/myproj/myproj.srcs/sources_1/bd/red_pitaya/hdl/red_pitaya_wrapper.vhd'
> does not exist*
> *INFO: [Common 17-206] Exiting Vivado at Tue Sep  8 14:32:38 2020...*
> *Traceback (most recent call last):*
> *  File "/home/javierb/workspace/mlib_devel/jasper_library/exec_flow.py",
> line 226, in *
> *synth_strat=opts.synth_strat, impl_strat=opts.impl_strat)*
> *  File "/home/javierb/workspace/mlib_devel/jasper_library/toolflow.py",
> line 1834, in compile*
> *raise Exception('Vivado failed!')*
> *Exception: Vivado failed!**Error using jasper (line 23)*
> *Backend build failed! Check log files for more information *
>
>
>
> My understanding is that there is a conflict between the Vivado 19.1.1 and
> some other part that requires 19.1.
> I am confident I followed the installation steps recommended at
> readthedocs.com website.
> Have you seen an error like that before? Any idea what it could be?
>
> Thank you for your time,
> XB
>
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Re: [casper] Jasper error while compiling

[Jonathon Kocz]

Hi Guillermo,

I'm not sure what is causing that specific error - normally it's that
there's something like an invalid input (somewhere) in the signal chain
leading up to the block it is complaining about (though it looks like it's
complaining about the register block yellow block itself).

Did you put the design together following the instructions, or are you just
trying to compile the example design provided? Have you been able to
compile any of the other SNAP designs?

To confirm, you're using matlab 2018a and vivado 2019.1?

As an aside, there was some work done on the toolflow last week, and as
part of that there is now an update
on the main branch (as of this
morning). I tested those libraries against the SNAP tutorial designs as
part of the verification, so they should work, if you want to try using
them instead. (They have not yet been propagated into the tutorials_devel
branch submodules, this will probably happen in the next week or so).

Cheers,
Jonathon

On Mon, 19 Oct 2020 at 15:04, Guillermo Gancio  wrote:

> Hi all,
>
> I'm having trouble compiling the SNAP tutorial designs, I guess that
> I'm missing some (silly) variable config but after a week of looking
> around I couldn't find it, I did a fresh tool-flow installation and
> I'm using virtual env for python 3...If any one has any idea.
>
> the error that I got is this:
>
> Error using jasper_frontend (line 33)
> The S-function 'sysgen' in 'snap_tut_corr/fft_shift/io_delay' has
> specified the option SS_OPTION_PORT_SAMPLE_TIMES_ASSIGNED and
> specified inherited for sample time number 0. Inheriting a sample time
> is not supported when specifying
> SS_OPTION_PORT_SAMPLE_TIMES_ASSIGNED
>
> Error in jasper (line 6)
> build_cmd = jasper_frontend; - Show complete stack trace
>
> Thanks!
>
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Re: [casper] Jasper error while compiling

[Jonathon Kocz]

> I'm working on Ubuntu 18, matlab 2019a and vivado 2019.1.3
>
> So I hadn't tried these tutorials in 2019a, only 2018a. (See recommended
versions here:
https://casper-toolflow.readthedocs.io/en/latest/src/Installing-the-Toolflow.html
Vivado/Matlab are extraordinarily picky about which combinations will work)

Just quickly testing:

tut_intro ran, and took about 10 minutes.

spec/corr would not compile without updating the blocks in 2019a. Did you
run update_casper_blocks / regen the fft with a new one from the library
before running jasper?

So these ones not working *might* be a matlab version issue, but they
should work once you update the blocks.

I also tried tut_intro and I didnt get any error but it reaches
> Skipping diagram update
> Running system generator ...
> and never finishes.
>

This seems like something else.

I'm wondering if this is an Ubuntu 18 issue - do you have kde installed?
(See this post by Jack in the mail archive:
https://www.mail-archive.com/casper@lists.berkeley.edu/msg07886.html). Even
though it's not quite the same, the timeout makes me wonder.

Cheers,
Jonathon

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Re: [casper] SNAP ADC calibration - ramp test issues

[Jonathon Kocz]

Hi Tim,

Unfortunately this *is* a common issue with the SNAP ADC and the current
calibration code, but it is non-critical.

To the best of my understanding, it has to do with the way the individual
lanes for each ADC core are aligned. Because there are multiple windows in
which there are no errors for each lane individually, it's possible for the
lanes to end up in a situation where they work singularly, but not
together, hence failing the final ramp test.

The simplest solution I've found in the interim is just to put the ADC
calibration in a loop. It's rare for a board to get into this state
multiple times in a row, so a loop of a few times will solve the problem,
if not in the most elegant way!

As a side note, Aaron Parsons recently rewrote parts of this code to be
python 3 compatible, and in the process made the calibration much faster.
We're looking into integrating that into the main casperfpga repo, and I'll
take another look at finding a proper way to fix this particular problem as
we do (it may be that we should just internalize the loop...).

Hope this helps,
Jonathon

On Thu, 17 Dec 2020 at 15:15, 'Timothy Bateman' via
casper@lists.berkeley.edu  wrote:

> Hi all,
>
> I'm using SNAP boards and at times we are having random ADC calibration
> issues on several boards that just go away:
>
> Using config file: config/correlator_m12_f8/s06.scfg
> Connected to SNAP
> Upload and program ../firmware/bofs/um2d_2020g_2020-05-16_1637.fpg...
> Initialize ADCs...
> ERROR:casperfpga.snapadc:ADCs failed on ramp test.
> ADC CALIBRATION ERROR
>
> Any insight into what can cause the error ? Is this a common issue ?
>
> Thanks Tim
>
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Re: [casper] New setup installation problems (python setup.py egg_info" failed with error code 1)

[Jonathon Kocz]

Hi Kaj,

I have invited you and Derek to the casper slack - please let me know if
you run into any trouble.

A couple of notes on the ZCU111: The ZCU111 branch on casper-astro is a bit
out of date. Wei Liu recently completed yellow blocks for the ZCU111. These
have not yet been merged into the main casper repository I hope to do this
merge into the soak-test branch in the near future). Until then, for those
that missed Wei's email, they can be found here:
https://github.com/liuweiseu/ZCU111 As far as I am aware this is the most
up to date code for the ZCU111 in the casper toolflow.

There are several people subscribed to the ZCU111 casper slack channel,
though there hasn't really been communication on it since inception,
however, some discussion regarding the ZCU111 has taken place on the #rfsoc
channel, and I recommend checking out the history there as well.

Cheers,
Jonathon

On Fri, 22 Jan 2021 at 08:50, Kaj Wiik  wrote:

> Hi!
>
> I tried a bit different route: I installed python3-numpy and
> python3-setuptools-git Ubuntu packages first and commented out numpy
> from requirements.txt. At least the installation went fine using these
> workarounds.
>
> About ZCU111 Slack channel, I am very interested (and my colleague
> derek.mc...@utu.fi also), could you please send us an invitation?
>
> Many thanks for your kind help!
>
> Kaj
>
> On 1/20/21 10:22 PM, Dan Werthimer wrote:
> >
> > hi kaj,
> >
> > regarding your interest in ZCU111:
> > there's a casper slack channel on RFSOC that you might find useful.
> > wei liu recently developed a casper ADC yellow block for the ZCU111.
> >
> > best wishes,
> >
> > dan
> >
> >
> >
> > Dan Werthimer
> > Marilyn and Watson Alberts Chair
> > Astronomy Dept and Space Sciences Lab
> > University of California, Berkeley
> >
> >
> > On Wed, Jan 20, 2021 at 12:17 PM Kaj Wiik  > > wrote:
> >
> >
> >
> > On 20/01/2021 18:49, Jack Hickish wrote:
> >
> >  > I've been using Ubuntu 18.04 LTS without issues, at least with
> > the boards which use Vivado 2019. I'm not sure  what versions of
> > python the OS came with, but I'm currently running the toolflow in a
> > python 3.6.9 virtual env.
> >
> > I first tried with Ubuntu 18.04 LTS but I got stuck with a problem
> > with Matlab and some system library versions.
> >
> > I think I'll change the requirements.txt file to read "numpy<1.19"
> > and try with that first.
> >
> > I am very interested of all information and experiences with Casper
> > on ZCU111. Thanks to Adam for pointing out of a mlib_devel ZCU111
> > branch, I haven't noticed that!
> >
> > Thanks!
> >
> > Kaj
> >
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Re: [casper] general SNAP toolflow setup guidance

[Jonathon Kocz]

Hi Eamon,


   1.  Is it likely to work with more recent versions of any of these
   components?

System generator and Vivado are *very* finicky as to version compatibility.

You could update Ubuntu if you were really keen (it will run on 18.04, but
with caveats (e.g. you have to install kde-full, or system generator
doesn't seem to work)). However, you definitely can't sub in new versions
of Matlab and Vivado.

There are a few versions of the toolflow that people have individually
ported to Matlab 2019a, but these have not yet made it back to the main
repository. This is on my todo list for the near future.


>
>1. Or are we really better off just sticking to whatever is specified?
>Accounts of positive or negative experiences welcome.
>
> As a new user, I would highly recommend sticking to what it specified.


   1. Does Vivado include all of the Xilinx components needed?

VIvado System Edition includes what you need (Design Edition does not).


   1. Does anyone have a virtual environment they can share, or advice on
   this? Conversely, is this even worth asking about, or should we be able to
   get it up and running without much fuss?

You should be able to get it up and running without too many difficulties
following the instructions here:
https://casper-toolflow.readthedocs.io/en/latest/src/Installing-the-Toolflow.html

We had some trouble recently with python versions becoming unsupported, but
this should have been fixed. - Please do email the list if you run into
trouble.


   1. Has anyone used Docker to containerize their environment, or know if
   this is a reasonable thing to do? We would like to be able to move a
   (virtual) build machine around as easily as possible. What about Virtualbox?

I think a few people on the list have done this. I'll leave it to them to
discuss pros/cons.


Hope this helps,

Jonathon

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Re: [casper] Re: Cannot Join Casper List Server & Question about Error in Jasper Tutorial

[Jonathon Kocz]

Hi Kathryn,

Welcome to the list. - To follow up from Jack's questions:

- Which dead websites did you find? - We'll aim to clean these up.
- Many people struggle a bit bringing up the toolflow the first time (as
you can see from the mail archive). The most up to date documentation is
the read the docs here: https://casper-toolflow.readthedocs.io/en/latest/
- In an effort to get people started who just want to try out the toolflow,
with the help of the Pacific Research Platform the CASPER toolflow is now
also working in the cloud. We are working on adding hardware that can be
used to test designs as well, but for those that want to just run some
simple (or not simple) tests/compiles:
1) go to casper.nautilus.optiputer.net
2) Once you've logged in, open the "Desktop".From there, you can open a
terminal, and clone mlib_devel. - You want the m2019a branch from
casper-astro: (git clone -b m2019a
https://github.com/casper-astro/mlib_devel.git)You can then start the
toolflow from within the mlib_devel directory with "startsg
./startsg.cloud.local" (there is also a #prp-cloud channel on the slack for
assistance.)

Cheers,
Joanthon


On Fri, 25 Jun 2021 at 04:39, Jack Hickish  wrote:

> Hi Kathryn, cc list
>
> Did emailing casper+subscr...@lists.berkeley.edu (as per
> https://casper.berkeley.edu/index.php/contact/) not work? In any case,
> I've added you manually, so you should be able to post directly to
> casper@lists.berkeley.edu from this JPL email address. Let me know if
> this doesn't work.
>
> That "test_snap" file is generated by the toolflow. In general, the
> toolflow always generates a module with the same name as your Simulink
> design.
>
> - What versions of MATLAB / Vivado / OS are you using?
> - Do things behave the same if, instead of running `jasper_frontend`
> followed by `exec_flow.py`, you simply run "jasper" in the MATLAB prompt?
> - If you use a model name/path with no capital letters (i.e. not a
> simulink design in the "Documents" directory) does that make any
> difference. In the olden days capitals used to upset MATLAB. Not sure if
> this is still the case.
>
> Cheers
> Jack
>
>
> On Thu, 24 Jun 2021 at 22:54, Chamberlin, Kathryn (US 386E) <
> kathryn.chamber...@jpl.nasa.gov> wrote:
>
>> Hello,
>>
>>
>>
>> I am using the Casper tool flow and am trying to contact the Casper list
>> server with a question. I have had no success in subscribing to the list
>> server due to unfound (dead) websites and Google groups, but I saw via the
>> Casper Mail Archive that you are an active member of the list serve.
>>
>>
>>
>> Would you be able to add me to the list serve manually? I am trying to
>> find a solution to a simulation error I have for the Jasper test_snap
>> tutorial.
>>
>>
>>
>> When running the Jasper test_snap tutorial
>> ,
>> I am able to follow the directions to step 9. After I execute the
>> exec_flow.py command, I can see everything working and Vivado synthesis
>> begin. During the Synthesis I get an error and the test stops.
>>
>>
>>
>> After looking in vivado.log for the error, the error says:
>>
>> ERROR: [Synth 8-439] module 'test_snap' not found
>> [/home/ice_sensing/Documents/fpga/mlib_devel/jasper_library/test_models/test_snap/myproj/myproj.srcs/sources_1/imports/test_snap/top.v:614]
>>
>> ERROR: [Synth 8-6156] failed synthesizing module 'top'
>> [/home/ice_sensing/Documents/fpga/mlib_devel/jasper_library/test_models/test_snap/myproj/myproj.srcs/sources_1/imports/test_snap/top.v:7]
>>
>>
>>
>> I see test_snap is a module instance in top.v, but cannot find any
>> Verilog/vhdl file that may correspond with the module. Is this file
>> supposed to be included in the repo? Or is it generated in the tool flow
>> operation and somehow my operation is failing to produce this file?
>>
>>
>>
>> Any support in joining the Casper list serve so I can ask this question
>> in that group, or help solving it 1:1, is greatly appreciated.
>>
>>
>>
>> *Kathryn Chamberlin*
>>
>> Instrument Embedded Systems
>>
>> NASA Jet Propulsion Laboratory
>>
>> Pasadenca, CA, USA
>>
>>
>>
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Re: [casper] FW: casperfpga screenshots

[Jonathon Kocz]

Hi Jeff,

I'd have to check up on the write_int/_uint functionality, but in terms of
versions, what I *think* might be happening is:

If you follow the readthedocs instructions exactly, it's installing the
required packages (requirements.txt) and then installing the version of
casperfpga registered with pip (which is not up to date with the casperfpga
source, but should be stable).

If you want to install from the source you downloaded, you could "pip
install ." from the casperfpga directory after installing the requirements
(instead of "pip install casperfpga"), and that should build and install
from the local repo.

Cheers,
Jonathon

On Fri, 6 Aug 2021 at 08:14, 'Kobesky, Jeffrey CIV USN NRL ()
Washington DC (USA)' via casper@lists.berkeley.edu <
casper@lists.berkeley.edu> wrote:

> Hello CASPER,
>
>
>
> I’ve followed the casperfpga install directions found here using pip:
> https://casper-toolflow.readthedocs.io/projects/casperfpga/en/latest/How-to-install-casperfpga.html
>
>
>
> Bewildering to me, my pip-installed casperfpga does not match my cloned
> casperfpga (from casper-astro repo).  See “try” statement in attachments,
> they are different.  Does anyone know how that could happen, how did my
> struct.pack statement get commented out during the pip install?  Does
> anyone recognize the comment “# Breaking backwards compatibility” in the
> “pip_installed” attachment?
>
>
>
> Note I came across this because I can’t seem to write a 32 bit unsigned
> integer to the yellow block software register using “write_int”.  The max
> number I can write without getting error is 2^31 – 1, which seems to
> suggest my number entry is being interpreted as a signed integer.  Looking
> at the “write_int” code, it seems the (‘>i’ if integer < 0 else ‘>I’,
> integer) argument should sort that out, but for some reason it’s commented
> out in the /usr/…/dist-packages/casperfpga.
>
>
>
> Any help is greatly appreciated, I don’t understand how the installed
> source code could be different than the cloned source code.  Maybe
> something about pip or git that I don’t understand?
>
>
>
> Thanks again – Jeff
>
>
>
> Jeffrey Kobesky
>
> Electronics Engineer, Naval Research Laboratory
>
> O: (202) 404-7109 M: (443) 243-1554
>
> OS:  Pop!_OS 18.04 LTS (derived from Ubuntu 18.04 LTS)
>
> Vivado 19.1.1MATLAB 2018amlib_devel branch:  master
>
> Python 2.7 for casperfpga and 3.6 running in (casper_venv) for toolflow
>
> Devices:  Red Pitaya, SKARAB
>
>
>
>
>
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Re: [casper] Error installing in python3 environment on SELinux7

[Jonathon Kocz]

Hi Jeb,

There are a couple of branches and forks of casperfpga that *mostly* work
in python 3 - it's a work in progress, and hopefully we'll have the main
branch of the repository updated soon. In the interim there is a py3 branch
of casperfpga here:
https://github.com/casper-astro/casperfpga/commits/pcie-transport, which
should mostly work, baring some issues with SNAP boards and ADC
calibration.

Cheers,
Jonathon

On Fri, 27 Aug 2021 at 16:55, Jeb Bailey  wrote:

> Hi Folks,
> We are using a lightly patched version of 0.4.3.1 (here
> ) related
> to #74 I opened. I’m trying to get our readout environment up to python 3
> and in the process discovered that the change of imports (at a minimum)
> means this version won’t work for us any more. I tried pip and the python
> setup.py installing v3.3 but in both cases ran into:
>
> error: [Errno 2] No such file or directory:
> 'build/lib.linux-x86_64-3.7/casperfpga/progska/__init__.py’
>
> The only other warning I’m seeing is: WARNING: Ignoring invalid
> distribution -umpy
> (/home/mecvnc/miniconda3/envs/foo/lib/python3.7/site-packages)
>
> We are trying this on Scientific linux 7 in a conda environment with all
> the requirements.
>
> Any advice on getting up and running in python>=3.6
>
>
>
> -Jeb
>
> ——
> Dr. J.I. Bailey, III (Jeb) / Project Scientist
> Mazin Lab  / Department of
> Physics, UCSB
> jebbailey.com / +1 (734) 389-5143 / skype:spacecolonyone
>
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Re: [casper] Error installing in python3 environment on SELinux7

[Jonathon Kocz]

I have not tried it so I would not like to make guarantees, but I'm not
aware of any reason for it not to work.

If you do try it out and run into issues, please let us know here / on the
#casperfpga slack channel!


On Fri, 27 Aug 2021 at 19:06, Jeb Bailey  wrote:

> What are your thoughts on it working *well *with ROACH2 boards from ~5
> years ago?
>
>
> -Jeb
>
> ——
> Dr. J.I. Bailey, III (Jeb) / Project Scientist
> Mazin Lab <http://web.physics.ucsb.edu/~bmazin/> / Department of
> Physics, UCSB
> jebbailey.com / +1 (734) 389-5143 / skype:spacecolonyone
>
> On Aug 27, 2021, at 6:28 PM, Jonathon Kocz  wrote:
>
> Hi Jeb,
>
> There are a couple of branches and forks of casperfpga that *mostly* work
> in python 3 - it's a work in progress, and hopefully we'll have the main
> branch of the repository updated soon. In the interim there is a py3 branch
> of casperfpga here:
> https://github.com/casper-astro/casperfpga/commits/pcie-transport, which
> should mostly work, baring some issues with SNAP boards and ADC
> calibration.
>
> Cheers,
> Jonathon
>
> On Fri, 27 Aug 2021 at 16:55, Jeb Bailey  wrote:
>
>> Hi Folks,
>> We are using a lightly patched version of 0.4.3.1 (here
>> <https://github.com/MazinLab/casperfpga/releases/tag/v0.4.3.1>) related
>> to #74 I opened. I’m trying to get our readout environment up to python 3
>> and in the process discovered that the change of imports (at a minimum)
>> means this version won’t work for us any more. I tried pip and the python
>> setup.py installing v3.3 but in both cases ran into:
>>
>> error: [Errno 2] No such file or directory:
>> 'build/lib.linux-x86_64-3.7/casperfpga/progska/__init__.py’
>>
>> The only other warning I’m seeing is: WARNING: Ignoring invalid
>> distribution -umpy
>> (/home/mecvnc/miniconda3/envs/foo/lib/python3.7/site-packages)
>>
>> We are trying this on Scientific linux 7 in a conda environment with all
>> the requirements.
>>
>> Any advice on getting up and running in python>=3.6
>>
>>
>>
>> -Jeb
>>
>> ——
>> Dr. J.I. Bailey, III (Jeb) / Project Scientist
>> Mazin Lab <http://web.physics.ucsb.edu/~bmazin/> / Department of
>> Physics, UCSB
>> jebbailey.com / +1 (734) 389-5143 / skype:spacecolonyone
>>
>>
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>>
>
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Re: [casper] Error when running SNAP tutorial

[Jonathon Kocz]

Hi Xin,

Can you confirm for me your toolflow setup?

Are you on ubuntu 16.04 or 18.04? Which versions of matlab and vivado are
you using (2018a/2019.1)?

Are you using the main casper-astro/mlib_devel or are you using the
mlib_devel that is submoduled in the casper-astro/tutorials_devel
repository?

If you create a new model, and rebuild that part of the snap tutorial (not
copying from the other model, but creating from the simulink library) do
you get the same error?

Cheers,
Jonathon

On Thu, 9 Sept 2021 at 09:42, Xin Cui  wrote:

> Hello,
>
> I finished set up the tool flow, which seems to work properly. I can start
> the environment by running 'startsg' without any errors. But I had errors
> when I tried to simulate a SNAP tutorial -- snap_tut_intro.slx. Please see
> the error message below:
>
>
>
> All the 3 errors are about the data width of the input data. The following
> shows where the error happens:
>
>   1, The gateway_in in the yellow block of input a:
>   2, the s function in the yellow block of input a, the same picture as
> shown above.
>
>   3, the delay block in the sum_a_b output
>
> Except the first one, that I can see the output data from the gain_1 is
> ufix64_En31, which I am not sure it is 32 bits or 64 bits, the rests are 32
> bits. So I am wondering if this mismatched data width from the environment
> or not? Could it relate to my tool flow setup? Any suggestions that I can
> try to narrow down this problem will be very helpful.
>
> Thanks in advance!
> Xin
>
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>

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[casper] FASR2021 Workshop

[Jonathon Kocz]

Hi Casper,

Sending this out as some may be interested in attending or presenting
(particularly on instrumentation developments) at the workshop below.

Best,
Jonathon


Second announcement: "FASR2021 workshop: Solar Physics with a Next
Generation Solar Radio Facility", Dec 1-3, 2021 (virtual).
Website/registration are now open.


The need for a high-performance solar radio telescope in the United
States has been recognized for many years. The FASR concept represents
such a telescope, one that provides high-resolution imaging over a broad
range of frequencies, sufficient to probe the solar atmosphere from the
mid-chromosphere to the mid-corona, with high time and spectral
resolution. EOVSA implemented many FASR design elements and, as such,
has served as a valuable pathfinder instrument, spectacularly validating
both the fundamental concept of time-resolved broadband imaging
spectroscopy and the science it enables. In the meantime, science and
technology have advanced and the need for full implementation of the
FASR concept has only grown more important

In anticipation of upcoming funding opportunities, this workshop is
being convened from 2021 Dec 1-3 to highlight progress in solar physics
over the past decade, and to take stock of the unique contributions
enabled by the current suite of new radio instruments, to refine the
science goals and requirements of a next-generation solar radio
facility. The workshop will provide a forum to discuss relevant new and
emerging technologies that will enable this new science. We invite
colleagues with an interest in solar physics and radio technology, and
from other fields that would stand to benefit, to help explore the
frontiers of science and technology that will guide updates and
refinements to the FASR concept.

The workshop will be virtual, hosted from the University of California
Berkeley's Space Sciences Laboratory (LOC: Pascal Saint-Hilaire, Milo
Buitrago-Casas, Jim McTiernan, Gelu Nita). The Scientific and Technical
Organizing Committee is composed of Marin Anderson (JPL), Tim Bastian
(NRAO), Bin Chen (NJIT), James Drake (UMD), Dale Gary (NJIT), Lindsay
Glesener (UMN), Gregg Hallinan (Caltech), Jonathon Kocz (UCB), Haosheng
Lin (U. Hawaii), Sophie Musset (ESA), Dan Werthimer (UCB). Website and
registration are at https://fasr21.ssl.berkeley.edu/. Deadline for
contributions is November 1st, 2021. There is no deadline for participation.

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Re: [casper] incorrect slice end point

[Jonathon Kocz]

Hi Gonzalo,

The problem is probably exactly what it's saying - the input signal is the
wrong width for the slice, so it's trying to grab bits that don't exist. -
Is the input data the expected width?

Possibly try running a short simulation and check out the bit widths of
each signal - I'd guess that some part of the design has an incorrect
parameter.

Cheers,
Jonathon

On Tue, 12 Oct 2021 at 14:56, Gonzalo Burgos  wrote:

> Hi everyone.
> I hope you're keeping well.
> I try to compile a design for roach2 (a spectrometer of 1024 channels, and
> data read of the complex componentes of each channel). But casper_xps shows
> me an error in a slice inside a bram. I attach the info of the
> sysgen_error.log file and the screenshots of the error windows.
>
> - Version Log
> --
> Version Path
> System Generator/opt/Xilinx/14.7/ISE_DS/ISE/sysgen
> Matlab 8.2.0.701 (R2013b)   /usr/local/MATLAB/R2013b
> ISE /opt/Xilinx/14.7/ISE_DS/ISE
>
> 
> Summary of Errors:
> Error 0001: Incorrect slice end point
>  Block: 'try2_1/pbc3/munge_in/split/slice2'
>
> 
> Error 0001:
> Reported by:
>   'try2_1/pbc3/munge_in/split/slice2'
>
> Details:
> Slice endpoints must lie between the LSB and MSB
> Error occurred during "Rate and Type Error Checking".
>
>
> 
> Cheers.
>
> *PD: other spectrometer design don't have this problem and works well*
>
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Re: [casper] CASPER Hardware page showing 404 error

[Jonathon Kocz]

Hi Indrajit,

It looks like there was an error that broke the CASPER webpage a few days
ago. It should be up and running again now (thanks Ryan!).

You should be able to see https://casper.astro.berkeley.edu/wiki/Hardware
again now.

Cheers,
Jonathon

On Thu, 23 Dec 2021 at 20:48, Indrajit Barve  wrote:

> Dear Casper team,
>
> The link to the following hardware page is showing error 404 on github
> webpage:
> https://github.com/casper-astro/casper-hardware/blob/master/ADC2x400-14
> and old CASPER : http://casper.astro.berkeley.edu/wiki/Hardware
> Any updates on that.
>
> Season's Greetings
>
> Thanks and regards
> Indrajit
>
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Re: [casper] Different Software Versions

[Jonathon Kocz]

As a quick reminder to all, don't forget that the PRP cloud version of
CASPER exists these days as well! (Login here:
https://casper.nautilus.optiputer.net/).

In addition to the normal toolflow, Vivado 2020.1 is now installed (I know
that 2020.2 is recommended for RFSoC, but 2020.1 should work as well: use
the m2019a-cloud branch rather than m2019a, this has the downgraded tcl
files so they run in 2020.1).

For RFSoC work, use the startsg.cloud.2020.local file instead of
startsg.cloud.local.

You will also at this point not be able to use the Vitis backend side of
things (leave the JASPER_BACKEND as Vivado). I will look into installing
Vitis.

I ran some tests this morning, and was able to compile an fpg for a ZCU111.
(zcu111_tut_platform).

If you use the PRP cloud, I also encourage you to join the CASPER slack (if
you have not already), and post questions / problems on the #prp-cloud
channel. - Please just let me know if you need an invite.

Best,
Jonathon


On Mon, 21 Feb 2022 at 04:58, Adam Isaacson  wrote:

> Hi Kaj and Wesley,
>
> You are both right. The Python upgrades have proved a problem and it would
> help to list it in the documents.
>
> The requirements.txt can be too general though using versions "<" or ">".
>
> RFSOC is a new development, so I understand there could be bugs. I was
> more referring to the older developments. My email was not aimed at anyone
> particular :). I learnt my lesson over the years (or maybe I didn't) and
> with SKARAB.
>
> Kind regards,
>
> Adam
>
>
>
> On Mon, 21 Feb 2022, 1:32 PM Wesley New,  wrote:
>
>> Hi Kaj,
>>
>> There is generally a requirements.txt in the root of the mlib_devel which
>> should list any python dependencies and appropriate versions. I am not sure
>> how well this is kept uptodate though.
>>
>> Regards
>>
>> Wes
>>
>>
>>
>> On Mon, Feb 21, 2022 at 1:24 PM Kaj Wiik  wrote:
>>
>>> Hi Adam,
>>>
>>> I am sorry but I missed your reply too.
>>>
>>> The reason for us to experiment with different versions was to get RFSoC
>>> (specifically ZCU111) stuff working (by following the documentation in
>>> https://github.com/casper-astro/tutorials_devel/blob/master/docs/tutorials/rfsoc/tut_getting_started.md
>>> ). If I understand correctly, the original toolflow in the casper repo does
>>> not (yet) support RFSoC's?
>>>
>>> We will now try to get the Ubuntu 20.04 based versions working, thanks
>>> Mitch, because Ubuntu 20.04 will be supported longer (perhaps until my
>>> retirement ;-)). I still have the 18.04 container so I could try out your
>>> repo too.
>>>
>>> I think one of the main problems is that after one group gets everything
>>> working, there will be Python package upgrades that later installers get
>>> (without intention) and suddenly the toolflow is not working anymore. I
>>> think it would be very useful if the versions of all Python packages of a
>>> working setup would be listed in the documentation.
>>>
>>> Many thanks to all who support and develop the Casper toolchain, it
>>> certainly is not an easy task!
>>>
>>> Best regards,
>>> Kaj
>>>
>>> On 2/21/22 12:22, Adam Isaacson wrote:
>>> > Hi Casperites,
>>> >
>>> > I hope you are well. I have been reading the mail list and there are
>>> lots of queries about which version of Ubuntu, Python, Matlab and Simulink.
>>> >
>>> > We have documented this quite well on our Casper website, but I have
>>> noticed that some people try it on Windows, different versions and expect
>>> it to work first time around.
>>> >
>>> > My honest opinion is that the odds of this working would be slight. My
>>> advice is to rather stick to the mentioned versions, as those have been
>>> tested. You are welcome to try new versions, but my feeling is that it
>>> mostly won't work. My advice is to stick to the software versions.
>>> >
>>> > SARAO and CASPER spend a lot of time testing with specific versions.
>>> We then move onto other projects and move onto newer software versions.
>>> This is more efficient in my opinion. If there is a major bug then we
>>> upgrade.
>>> >
>>> > Kind regards,
>>> >
>>> > Adam
>>> >
>>> > --
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>>> > To unsubscribe from this group and stop receiving emails from it, send
>>> an email to casper+unsubscr...@lists.berkeley.edu >> casper+unsubscr...@lists.berkeley.edu>.
>>> > To view this discussion on the web visit
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>>> <
>>> https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CADTJ%3DnEv0CTDQsW4bpaTXk-6ZB%3D5nsPnb_7%2B5%2BO1Bk8ECwXBxQ%40mail.gmail.com?utm_medium=email&utm_source=footer
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>>>
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Re: [casper] control SNAP1 with raspberry PI 4

[Jonathon Kocz]

Hi Duan,

Unfortunately the PI4 doesn't work out of the box with the SNAP board. -
Aaron Parsons did some debugging on this and found that the GPIO base
address changed on the PI4, and needs to be updated in the JTAG header file.

I think the required fix has been pushed to a branch that you can try here:
https://github.com/jack-h/katcp_devel/tree/rpi-devel-casperfpga/tcpborphserver3

Cheers,
Jonathon



On Mon, 11 Apr 2022 at 04:12, duanxuef...@xao.ac.cn 
wrote:

> Hello,CASPER！
> I am trying to control SNAP1 with raspberry PI 4. I download this
> link (
> https://github.com/casper-astro/katcp_devel/tree/rpi-devel-casperfpga)
> katcp code. I build tcpborphserver on my PI4 but I can't  upload .fpg file
> use casperfpga and the upload_to_ram_and_program method.
> Who  can  give me some help? I would appreciate it.
> Duan
> --
>
> 
>
> 段雪峰(Duan Xuefeng)
>
> 中国科学院新疆天文台
>
> Xinjiang Astronomical Observatory (XAO), CAS
>
> 乌鲁木齐市新市区科学一街150号，830011
>
> 150 Science 1-Street, Urumqi, 830011, China
>
> 电话(Tel):0991-3689068 15719983612
>
>
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> 
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Re: [casper] viability of VCU128 eval board as production CASPER instrument

[Jonathon Kocz]

 Hi Jonathan,

A couple of follow up questions (sorry for getting into nitty gritty you
wanted to avoid!):

1) Are you actually using the HBM? You can get much cheaper FPGAs with
similar DSP/BRAM resources without HBM (if you are using HBM, are you doing
this via CASPER?!)
2) I've been using the VCU128 a bit - I'm working on a couple of projects
with your ADC board now. I've not found any issues (yet!) with loading of
code on power up, or with the 1Gb coming up - though I note that the 1Gb
CASPER core for the VCU128 doesn't work properly (an init issue, it's on my
list to fix that in the next couple of weeks). - Which set of libraries are
you using, or are you working outside CASPER?
3) On the CASPER conference/busy week front: With the 100Gb, is that also a
CASPER core? We currently have at least two in the CASPER libraries, and
part of the busy week I want to try to either integrate or find a use case
where one might use one or the other to reduce confusion for users - if you
have a third (and it's open source) it would be good to merge that in as
well!

In terms of eval boards in general:

I've fielded a few VCU128s and they're fine, but we're not running them in
an extreme environment - just in labs / server rooms. I've previously had
issues with other eval boards when trying to use them to maximum capacity -
as Dan said, they're not really designed for it.

In terms of other boards - which should be merged into the main branch
after the busy week:

We've put the HiTech Global HTG940 and HTG9200 boards into the CASPER
library if either of those was useful.

I would definitely recommend looking at Alpha Data as well - I've had good
experiences with them so far, and I've recently put the ADA-SDEV-3 into
CASPER [it has an FMC+ connector, but the FPGA might be too small for all 4
ADCs depending on what you want to do with the input/channel resolution
required].

Cheers,
Jonathon

On Mon, 9 May 2022 at 10:41, Jack Hickish  wrote:

> Hi Jonathan,
>
> On Mon, 9 May 2022 at 17:26, 'Jonathan Weintroub' via
> casper@lists.berkeley.edu  wrote:
>
>> Hi CASPERites,
>>
>> At SAO we’ve been developing high performance instruments based on the
>> Xilinx VCU128 evaluation board
>>  and the 
>> Adsantec
>> ASNT7123A  16 GS/s
>> 4-bit direct flash ADC.   Currently VCU128 is currently priced at
>> $10,794/each (it’s gone up a bit like everything but this is still good or
>> even incredible value) and the lead time per the prior page is 2-weeks,
>> essentially ex-stock.  Some time ago I had discussions with Xilinx and
>> various distributors, and there was no obstruction to buying multiple piece
>> quantities of the eval board.  Though its not the last word on acquisition
>> I’ll note that the XCVU37P-L2FSVH2892E, a very large and high performance
>> DSP oriented Ultrascale+ FPGA with 8GB of HBM and 9,024 DSP slices, is
>> listed at $90,786 and no lead time quoted (though I hear 12 months is not
>> uncommon for FPGAs these days) at Digikey
>> 
>>  and
>> other distributors.
>>
>> While our development with VCU128 has been very successful in terms of
>> validating ADC performance, developing 100 Gbps Ethernet and various
>> application firmware codes, we are hitting a variety of reliability and
>> related issues with the VCU128.  There is a bit of a laundry list of these,
>> following are examples: The 1 Gbps Ethernet control port doesn’t always
>> come up reliably and loading of FPGA codes can be intermittent on
>> power-up.  Looking more at electromechanical, we have concerns that the
>> FMC+ high speed connector (which we use to connect a “mezzanine” ADC board
>> to the FPGA) is not mechanically robust, and has no built in positive
>> locking or similar mechanism.  Also the eval board has quite of lot of
>> circuitry we don’t need, notably the PCIe bus and connector, not in of
>> itself a showstopper, however does interact with concerns we have about
>> thermal design of the PCB and the impact on the overall system.
>>
>> With all of the above as background, and noting that at one time the
>> VCU128 (and its predecessor the VCU118) has been suggested as a possibly
>> viable CASPER-supported solution (I vaguely recall there was at one time a
>> working group focused no eval boards generally), we are wondering what the
>> broader experience of the collaboration has been?  Has any group been
>> successful at fielding a viable production instrument based on VCU128 or
>> other eval board?  Do the experiences reported in the second paragraph
>> sound familiar to anyone?
>>
>> We are going

Re: [casper] ROACH's filesystem

[Jonathon Kocz]

Hi Wang,

I think as Jack said earlier, all of the links are valid and work, however
the website security certificate has expired, which gives an error. We are
looking into fixing it.

Best,
Jonathon

On Thu, 30 Jun 2022 at 10:19, Wang  wrote:

> Hi CASPER,
>
> How‘s it going？I'm having some problems starting ROACH2 on the netboot.
>
> I have finished setting the kernel. When setting the system file, I found
> that the link was invalid. Could you send me a copy?
>
> ROACH NFS guide - Casper (berkeley.edu)
> 
> [image: etch.png]
>
> I would be really appreciated if you reply!
>
> Thanks！
> Wang
>
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> 
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Re: [casper] ROACH's filesystem

[Jonathon Kocz]

Hi Wang,

Sorry, I see now you were talking about the specific kernel file - not the
website.

For ROACH files, I'm not sure where they are all still available, but at
least some of those linked files are located here:
https://github.com/casper-astro/roach2_nfs_uboot/tree/master/tftpboot/uboot-roach1

Best,
Jonathon






On Thu, 30 Jun 2022 at 10:33, Jonathon Kocz  wrote:

> Hi Wang,
>
> I think as Jack said earlier, all of the links are valid and work, however
> the website security certificate has expired, which gives an error. We are
> looking into fixing it.
>
> Best,
> Jonathon
>
> On Thu, 30 Jun 2022 at 10:19, Wang  wrote:
>
>> Hi CASPER,
>>
>> How‘s it going？I'm having some problems starting ROACH2 on the netboot.
>>
>> I have finished setting the kernel. When setting the system file, I found
>> that the link was invalid. Could you send me a copy?
>>
>> ROACH NFS guide - Casper (berkeley.edu)
>> <https://casper.astro.berkeley.edu/wiki/ROACH_NFS_guide>
>> [image: etch.png]
>>
>> I would be really appreciated if you reply!
>>
>> Thanks！
>> Wang
>>
>> --
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>> "casper@lists.berkeley.edu" group.
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>> email to casper+unsubscr...@lists.berkeley.edu.
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>> .
>>
>

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Re: [casper] RA Instruments using CASPER hardware and tools

[Jonathon Kocz]

On that note, the COMAP system at OVRO also uses ROACH2s.

On Wed, 31 Aug 2022 at 07:37, Vikram Ravi  wrote:

> DSA-110 at the Owens Valley Radio Observatory (OVRO) uses 40 SNAP-1 boards
> for its f-engine, and the STARE-2 all-sky FRB project also uses a SNAP at
> each site.  The SPRITE instrument at OVRO, which is resurrecting a few
> 10.4m Leighton dishes, is also using CASPER hardware/toolfllow in multiple
> places, including the correlator, lobe rotation, and phase switching.
>
> On Wed, Aug 31, 2022 at 07:21, David Harold Edward MacMahon <
> dav...@berkeley.edu> wrote:
>
>> Also, the “Infrared Spatial Interferometer” (ISI) project started by the
>> late :( Charles Townes uses CASPER hardware.
>>
>>
>> On Aug 31, 2022, at 3:59 PM, David Harold Edward MacMahon <
>> dav...@berkeley.edu> wrote:
>>
>> SERENDIP VI and Alfaburst were spectrometers that used CASPER hardware.
>> It may be more correct to call them two backends for the same
>> spectrometer.  These ran at Arecibo.  Greenburst is a version of Alfaburst
>> that is at Green Bank.
>>
>> There’s also PhRInGES.  Besides being a tortured (b)acronym for “Phased
>> Array Recording Instrument for Galactic Even horizon Studies”, PhRInGES was
>> a time domain phased array beamformer for CARMA and SMA (two of the first
>> three EHT sites).
>>
>> Cheers,
>> Dave
>>
>> On Aug 31, 2022, at 12:53 PM, Morag Brown  wrote:
>>
>> Ciao dalla Sardegna, collaborati!
>>
>> I'm hoping to put together a more up-to-date list of instruments that
>> have been built using CASPER hardware and tools. The most current list was
>> compiled in 2016 for the "A Decade of Developing Radio-Astronomy
>> Instrumentation using CASPER Open-Source Technology" paper by Jack et al,
>> so it could probably use updating.
>>
>> The list is currently as follows:
>>
>> *Spectrometers and packetizers -*
>> Fly’s Eye
>> GUPPY
>> CASPER
>> BPSR
>> GAVRT
>> SERENDIP V.v
>> HiTREKS
>> NUPPI
>> Skynet
>> RATTY
>> cycSpec
>> C-BASS
>> HIPSTER
>> KuPol
>> VEGAS
>> ALMA Phasing Project
>> Leuschner
>> R2DBE
>> DSN Transient Observatory
>> VGOS
>> AVN-Ghana
>> COMAP
>>
>> *MKID readout systems -*
>> Columbia MKID
>> Mustang2
>> DARKNESS
>> MEC
>> BLAST-TNG
>> HOLMES
>>
>> *Correlators and beamformers -*
>> KAT7
>> PAPER
>> ATA
>> LEDA
>> ARI
>> MAD
>> pocketcorr
>> Medicina FFTT
>> GMRT
>> Meteor
>> AMI
>> MeerKAT AR-1
>> FLAG
>> BIRALES
>> Starburst
>> AMiBA
>> EOVSA
>> SWARM
>> MeerKAT
>> HERA
>>
>> If you are not (or know of any instruments that are not) on this list,
>> please reach out to me for it to be added?
>>
>> Grazie!
>> Morag
>>
>>
>>
>>
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>>
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Re: [casper] Installing the toolchain

[Jonathon Kocz]

Hi Giovanni,

I haven't had a chance to look at this in detail,  but in case it helps:

Do you have kde-full installed on your 18.04 ubuntu? The system generator
socket error sounds similar to the one in the docs?

https://casper-toolflow.readthedocs.io/en/latest/index.html#a-note-on-operating-systems

Best,
Jonathon

On Thu, Sep 15, 2022, 00:46 Giovanni Comoretto 
wrote:

> I am now trying to install the new toolchain (R2021).
> - start with a blank standard installation of Ubuntu 18.04.4-desktop.
> - add just the packages git, virtualenv and python3-pip.
> - install Xilinx Vitis 2021.1 and Matlab R2021a,
> - install mlib_devel from github.com/casper-astro/mlib_devel
> - create a virtual environment, activate it and install packages in
> requirements.txt
> - edit startsg.local to point to the correct directories for vitis and
> matlab.
>
> Starting startsg I get:
> gtk message: failed to load module "canberra-gtk-module"
> (in Matlab): Error loading
> /opt/MATLAB/R2021a/bin/glnxa64/builtins/sl_main/mwlibmwsimulink_builtinimpl.so.
> /home/casper/.XILINX_MATLAB_RUNTIME/XMC_2021.1_R2021a/Ubuntu/18/libhogweed.so.4:
> undefined symbol: __gmpn_cnd_sub_n
> Then I cannot connect to the System Generator GUI: The System Generator
> GUI socket server timedout while waiting for an incoming socket connection.
> I can import blocks from the Xilinx blockset but I cannot open the
> associate paramenter window (same timeout error each time).
>
> I get the same error on Ubuntu 20.4, using different versions of Matlab
> and of the Xilinx tools, using Vitis or Vivado as backend (in export
> JASPER_BACKEND).
> I tried to install libcanberra-gtk-module, but the first error stays
> there.
>
> Running the model generator outside the casper environment seems to work
>
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Re: [casper] Ethernet speed interoperability

[Jonathon Kocz]

>
>
> I would imagine (though no claims that my imagination aligns with reality)
> that any switch with QSFP28 ports which advertise 4x25G breakout mode will
> also support 4x10G. The former might be more obviously advertised.
>
>
I think this is correct, the only caveat I'd add is for some switches (at
least I found with an Arista 7060X and optic connectors) you need a 40G
connector on the switch side rather than a 100G, because it expects RSFEC
for 25G+ (and we don't have that in our 10G core) and it will not allow the
port to be configured for 10G breakout unless you have a 40G connector.

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[casper] ROACH2 J10

[Jonathon Kocz]

Hi All,

We are attempting to bring in a PPS signal on the ROACH2 J10 SMA connector.

Does this still come in as with the ROACH using the GPIO block? Is there a
page or document somewhere that describes how to bring this signal in?
(GPIO bit map/other, similar to
https://casper.berkeley.edu/wiki/ROACH_FPGA_Interfaces ?)

Many thanks,
Jonathon

[casper] ROACH2 and adc083000

[Jonathon Kocz]

Hi All,

I am putting together a design that uses the ADC083000. It works fine in a
ROACH, but when I tried to move it to a ROACH2 it started complaining about
the clock rate (error below).

Does anyone have experience using this block in a ROACH2, or have an
updated version that uses the MMCM directly?

Many thanks,
Jonathon



ERROR:MapLib:1213 - DCM to MMCM retargeting of block
   'temp_baa_adc083000x2/temp_baa_adc083000x2/ADC0/DCM_ZDOK0/DCM_ADV' is not
   possible. Its target frequency, FVCO, is out of range. Valid FVCO range
   varies depending on speed grade: 600 - 1200MHz(-1), 1440MHz(-2),
1600MHz(-3).
   The computed FCVO is a function of the input frequency CLKIN_PERIOD, the
   division factor DIVCLK_DIVIDE, and the CLKFX_DIVIDE and CLKFX_MULTIPLY
   attributes. The CLKIN_PERIOD attribute may have been set by ngdbuild
based on
   the user specified PERIOD constraint.

[casper] CASPER Postdoctoral Fellow Opportunity at UC Berkeley

[&#x27;Jonathon Kocz' via casper@lists.berkeley.edu]

Hi Everyone,

We are advertising a new CASPER postdoc position at UC Berkeley, working on
the development of hardware and software instrumentation for the community.

https://aprecruit.berkeley.edu/JPF04224

Please feel free to send this on to anyone who may be interested.

Note that the anticipated start date is flexible, and we will continue
reviewing applications until the position is filled.

Cheers,
Jonathon

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