Re: [casper] Configuring 40GbE Yellow Block in JASPER

[Paul Prozesky]

Morning Mark

Please have a look here for SKARAB 40gbe TX and RX models with demo
software.

https://github.com/ska-sa/mkat_fpga/tree/devel/source/skarab_dev/tut2

Cheers
Paul


On 30 June 2017 at 07:46, Jason Manley  wrote:

> Hi Mark
>
> The current SKARAB 40G yellowblock is a bit of a hack.
>
>   1) It is currently not parameterised, and is hard-coded for the first
> port on Mezzanine slot 3.
>
>   2) The tx_valid and rx_valid lines are 4-bits wide, not 1 bit. This will
> be rectified soon, but in the meanwhile, just feed the value "3" to
> tx_valid to send packets.
>
>   3) Note that there was a recent change to the TX and RX 64-bit word
> ordering (was previously incorrectly swapped). Make you built your
> bitstreams with a recent git checkout.
>
> It's on our todo list to get it properly parameterised and to fix the
> 4-bit weirdness, but it's not clear when we'll have that done.  In the
> meanwhile, the 40G does work, and we are successfully using this first port
> actively at SKA-SA.
>
> Some things you should try to help debug:
>
>   1) The microblaze will attempt to DHCP on the 40G interface. Did it
> obtain a lease? Check your DHCP server logs.
>
>   2) Check (using casperfpga software) that the cores are actually
> configured like you think. There was a version of microblaze that overwrote
> things. And if it's DHCP'ing (this is how we use the ports), then the IP
> will have changed from what you expect. myfpgaobject.gbes['my_forty_
> gbe_core'].print_core_details() (or g.get_core_details()).
>
>   3) What does tcpdump/wireshark show is coming out of the TX board?
>
>   4) Did you select different MAC addresses for the "hardcoded"
> yellowblocks on the TX and RX side? Else a switch might not forward the
> packets.
>
>   5) Can you ping both 40G interfaces from a computer?
>
> Jason Manley
> CBF Manager
> SKA-SA
>
> Cell: +27 82 662 7726
> Work: +27 21 506 7300
>
> On 29 Jun 2017, at 20:37, Peryer, Mark A. 
> wrote:
>
> > Hello,
> >
> > I am trying to send data from one SKARAB to another SKARAB over 40GbE. I
> have created two separate JASPER files, one for receiving and one for
> transmitting. Each design has one forty_gbe yellow block and are configured
> similar to Tutorial 2 on the casper website. In the JASPER file used for
> transmitting, I have placed a snapshot block on the tx_data signal for the
> forty_gbe block and am able to read the correct data from the snapshot
> block using casperfpga. While it appears that the correct data is being
> transmitted, nothing is received by the second SKARAB. In the JASPER file
> used for receiving data, I have a snapshot block on the rx_data signal,
> which should trigger once a valid frame is received. However, when I run
> fpga01.snapshots.snapshot2.print_snap(50) it just hangs, indicating
> nothing has been received.
> >
> > I did notice that when I right click on the forty_gbe yellow block and
> go to Mask >> Edit Mask >> Parameters, there is a menu that allows
> for the card slot location of the 40GbE card to be selected. Our SKARAB
> units have the 40GbE card populated on Mezzanine Slot 3, however only Card
> Slot 0 and 1 are available to be selected. Should this option be set to
> slot 3 in order to properly use the 40GbE ports?
> >
> > I should also mention that I have configured the tx_dest_ip block input
> to be 192.168.5.20 and the tx_dest_port to be 1, which are the default
> values for the forty_gbe block.
> >
> > If there is anything else I should look at in order to properly
> configure the forty_gbe yellow blocks please advise.
> >
> > Thanks,
> >
> > Mark
> >
> >
> >
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Re: [casper] casperfpga library

[Paul Prozesky]

Hi Vishwa

1. It's meant to make using CASPER fpga designs a bit easier to use. This
mostly revolves around pulling information about the design from the
running FPGA or bitstream file and then providing methods to access the
hardware. So, for example, for registers and snapblocks, it provides easier
access to bitfields in those memories. It provides some other helper
methods such as running ops on many board in parallel for time saving. It's
the board-level corr functionality, but improved.
2. Pull it from the ska-sa github repo. The devel branch is where the love
is.
3. No, not entirely. It is for the lower-level access to FPGA boards. So it
has no concept, for example, of performing a VACC synch operation in a
correlator. So for us (SKA SA), that functionality is in the corr2 package.
It should be compatible with instrument-level functions from the corr
package, though, if you want to continue to use those.

Apologies for the lack of documentation. Please shout if you need more help.

Regards
Paul



On 4 March 2016 at 02:15, Vishwa Seneviratne  wrote:

> Hi,
>
> I noticed that the new updated tutorials (2016) uses the casperfpga
> library. But, I could not find any proper documentation about it. I would
> like to know about the following,
> 1. What is new in casper-fpga?
> 2. How to install it or update the existing binaries.
> 3. What is included in the library. Does it contain all features of 'corr'?
>
> I would be grateful if someone can provide come detailed description about
> it.
>
> Thank you
>
> Sincerely,
>
>
> *Vishwa Seneviratne*
>
> *Graduate Student*
>
> *Dept. of Electrical and Computer Engineering*
> *University of Akron*
>

Re: [casper] ROCH 2 communication through Python

[Paul Prozesky]

Afternoon Aniket

If you can telnet to the katcp interface on the ROACH2 then casperfpga
should work. Two things to bear in mind:

1. You only really benefit from using casperfpga if you're using .fpg files
(.bof + design info) from the toolflow, not .bofs. The SKA SA mlib_devel
produces fpgs, I'm not sure about other repos.
2. There have been many, many ROACH2 romfs, and therefore katcp server,
updates over the last year. We'd want to get you current before debugging.
What does the ?version katcp command return.

Cheers
Paul


On 2 September 2015 at 12:40, aniket  wrote:

> On 2015-09-02 12:22, Craig Tong wrote:
>
>> Hi Aniket.
>>
>> As James has said, if you have been making various telnet connections to
>> your Roach2 before running the script it might be worth just rebooting
>> the board before trying the casperFPGA scripts. The tcpborphserver may
>> have crashed due to receiving some commands it didn't like.
>>
>> Kind regards.
>> Craig
>>
>> On 2015-09-02 08:18, aniket wrote:
>>
>>> On 2015-09-02 11:28, James Smith wrote:
>>>
 Hello Aniket,

 You seem to have gone about it the right way. That error usually means
 that either your ROACH isn't connected or the tcpborphserver running
 on the ROACH has crashed. Also, check the spelling of your ROACH's
 name.

 I myself use ROACH1, not ROACH2 (in fact I had to modify casperfpga
 slightly to work with ROACH), so if you don't come right, reply to the
 group again (you can just do a "reply-all" to my previous mail), and
 some of those more experienced in using ROACH2 may be able to help
 you.

 Regards,
 James

 On Wed, Sep 2, 2015 at 7:35 AM, aniket 
 wrote:

 On 2015-09-01 15:21, James Smith wrote:
> Hello Aniket,
>
> casperfpga is the one you want:
> https://github.com/ska-sa/casperfpga [1] [2]
>
> It has a few dependencies to build, but it's much nicer than corr.
>
> Regards,
> James
>
> On Tue, Sep 1, 2015 at 11:39 AM, aniket
> 
> wrote:
>
> Dear CASPER colleagues,
>
> Myself Aniket Hendre working as a Project Engineer-C in Giant
> Metrewave Radio Telescope (GMRT), India.
>
> I am using ROACH 2 for my experiments. I have executed some modular
> design on ROACH 2 successfully.
>
> Now I am facing problem to communicate with ROACH 2 using Python
> environment. I have communicated with ROACH 2 successfully using
> telnet.
>
> Like for ROACH 1 Corr package any one knows package for ROACH 2 ?
>
> Please guide me regarding the same.
>
> Thanks and Regards,
>
> ANIKET S. HENDRE
> Project Engineer -C,
> Giant Metrewave Radio Telescope,
> The National Centre for Radio Astrophysics,
> Khodad, Pune,
> Maharashtra 410504.
> Tel:- 02132-258365.
> Web: www.ncra.tifr.res.in [2] [1]
>
> Links:
> --
> [1] http://www.ncra.tifr.res.in [2]
> [2] https://github.com/ska-sa/casperfpga [1]
>
  Dear James,

 Thanks for the replay. I have clone the casperfpga and installed on my
 machine. First I just want check that my ROACH2 has been connected to
 my PC. So from the modular script which is there in casperfpga
 directory I have extracted a required part. But still I am getting
 error. The statement which I am executing in ipython is as follows.

 In [8]: #!/usr/bin/env python

 In [9]: from casperfpga import katcp_fpga

 In [10]: HOSTCLASS = katcp_fpga.KatcpFpga

 In [11]: fpga = HOSTCLASS('roach02082A', 7147)

 ---

 KatcpRequestError Traceback (most recent call
 last)
  in ()
 > 1 fpga = HOSTCLASS('roach02082A', 7147)

 /usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
 __init__(self, host, port, timeout, connect)
  64 self._timeout = timeout
  65 if connect:
 ---> 66 self.connect()
  67 LOGGER.info('%s: port(%s) created%s.' % (self.host,
 port,
  68  ' &
 connected' if connect else ''))

 /usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
 connect(self, timeout)
  89 _stime = time.time()
  90 while time.time() < _stime + timeout:
 ---> 91 if self.ping():
  92 got_ping = True
  93 break

 /usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
 ping(self)
 163 :return: True or False
 164 """
 --> 165 reply, _ = self.katcprequest(name='watchdog',
 request_timeout=self._timeout)
 166   

Re: [casper] Compiling error

[Paul Prozesky]

Morning James

I've added some more debugging to the script, so check out the latest
version.

Have you used the debug logging before? Try setting:

casper_log_groups={'all'}

And rerunning your scripts.

Cheers
Paul



On 1 June 2015 at 15:24, James Smith jsm...@ska.ac.za wrote:

 Hi Paul,

 I wasn't sure what debug information I'd be able to get from this script
 directly, but I found that it gets called by write_info_table.m in the same
 folder.

 So at around line 16 in the script I added a try .. catch around the
 call to the sblock_to_info function, with e.stack and error(['Error
 occurred when processing ', tag, '.'])

 Should that tell me a little more info about where the problem occurs? Or
 is there another more elegant way to get that information?

 Regards,
 James


 On Mon, Jun 1, 2015 at 10:54 AM, Paul Prozesky paul.proze...@gmail.com
 wrote:

 Hi James

 You can see that your error is happening in this section of that script:

 if isempty(strtrim(value)) == 1,
 error('Empty value?');
 end


 So add some debug logging there and rerun the gen_xps_add_design_info
 part of the build.

 Cheers
 Paul





 On 1 June 2015 at 10:39, James Smith jsm...@ska.ac.za wrote:

 Hi Paul,

 Thanks, I have found that script. I can't think of a way to go about
 finding out which part it has a problem with though, except possibly
 starting several different compiles, removing a component from each, and
 seeing which ones pass / fail.

 Is this a sound approach?

 James


 On Mon, Jun 1, 2015 at 10:34 AM, Paul Prozesky paul.proze...@gmail.com
 wrote:

 Hi James

 Check the sblock_to_info script in the +design_info (no, the plus isn't
 a mistake, it's a matlab thing) folder in your xps_library folder.
 Something is that script is not happy with one of the blocks in your model
 file.

 Cheers
 Paul


 On 1 June 2015 at 10:27, James Smith jsm...@ska.ac.za wrote:

 Hi all,

 I'm working on a simple design for a two-stage high-resolution
 spectrometer, which almost gets finished compiling, sysgen seems to 
 finish,
 and then at the end fails with a most uninformative error message:

 ##
 ## Creating EDK files   ##
 ##
 Error using design_info.sblock_to_info (line 18)
 Empty value?

 Anyone else seen this problem before? The sysgen*.log files contain
 basically zero information, and I've grepped for as many combinations of
 the design_info.sblock_to_info string as I can think of, to no avail.

 If anyone has some insight that can point me in the right direction,
 I'd appreciate it. I can send the .slx file to anyone who would like to
 look at it, I didn't think the mailing list would be an appropriate place
 to attach it (about 7 MB).

 Regards,
 James

Re: [casper] Compiling error

[Paul Prozesky]

Hi James

You can see that your error is happening in this section of that script:

if isempty(strtrim(value)) == 1,
error('Empty value?');
end


So add some debug logging there and rerun the gen_xps_add_design_info part
of the build.

Cheers
Paul





On 1 June 2015 at 10:39, James Smith jsm...@ska.ac.za wrote:

 Hi Paul,

 Thanks, I have found that script. I can't think of a way to go about
 finding out which part it has a problem with though, except possibly
 starting several different compiles, removing a component from each, and
 seeing which ones pass / fail.

 Is this a sound approach?

 James


 On Mon, Jun 1, 2015 at 10:34 AM, Paul Prozesky paul.proze...@gmail.com
 wrote:

 Hi James

 Check the sblock_to_info script in the +design_info (no, the plus isn't a
 mistake, it's a matlab thing) folder in your xps_library folder. Something
 is that script is not happy with one of the blocks in your model file.

 Cheers
 Paul


 On 1 June 2015 at 10:27, James Smith jsm...@ska.ac.za wrote:

 Hi all,

 I'm working on a simple design for a two-stage high-resolution
 spectrometer, which almost gets finished compiling, sysgen seems to finish,
 and then at the end fails with a most uninformative error message:

 ##
 ## Creating EDK files   ##
 ##
 Error using design_info.sblock_to_info (line 18)
 Empty value?

 Anyone else seen this problem before? The sysgen*.log files contain
 basically zero information, and I've grepped for as many combinations of
 the design_info.sblock_to_info string as I can think of, to no avail.

 If anyone has some insight that can point me in the right direction, I'd
 appreciate it. I can send the .slx file to anyone who would like to look at
 it, I didn't think the mailing list would be an appropriate place to attach
 it (about 7 MB).

 Regards,
 James

Re: [casper] Compiling error

[Paul Prozesky]

Hi James

Check the sblock_to_info script in the +design_info (no, the plus isn't a
mistake, it's a matlab thing) folder in your xps_library folder. Something
is that script is not happy with one of the blocks in your model file.

Cheers
Paul


On 1 June 2015 at 10:27, James Smith jsm...@ska.ac.za wrote:

 Hi all,

 I'm working on a simple design for a two-stage high-resolution
 spectrometer, which almost gets finished compiling, sysgen seems to finish,
 and then at the end fails with a most uninformative error message:

 ##
 ## Creating EDK files   ##
 ##
 Error using design_info.sblock_to_info (line 18)
 Empty value?

 Anyone else seen this problem before? The sysgen*.log files contain
 basically zero information, and I've grepped for as many combinations of
 the design_info.sblock_to_info string as I can think of, to no avail.

 If anyone has some insight that can point me in the right direction, I'd
 appreciate it. I can send the .slx file to anyone who would like to look at
 it, I didn't think the mailing list would be an appropriate place to attach
 it (about 7 MB).

 Regards,
 James

Re: [casper] Suggested convention for writing registers

[Paul Prozesky]

Morning James

We do this in already in the casperfpga package:
https://github.com/ska-sa/casperfpga

It turns out construct is pretty slow, so we just do the conversions and
shifts manually. I think currently the fpg files that are automatically
parsed by casperfpga are only generated for ROACH2, but it would be easy to
add ROACH support.

Cheers
Paul




On 20 March 2015 at 09:08, James Smith jsm...@ska.ac.za wrote:

 Hello all,

 I've given some thought to the topic of writing (and reading) registers on
 the ROACH using the python corr module. Often in a design a single register
 may be sliced into many bits to control various things. The way I've
 normally seen such a register written in python looks something like this:

 fpga.write_int('control',19|110|025|12|13)

 My feeling is that this approach is difficult to maintain - inheriting
 code from someone else (or even from one's self 6 months down the line) is
 likely to bring about some confusion in this case, and lead to a fair
 amount of spelunking through the Simulink model in order to figure out what
 bit 9 and bit 10 etc. do. On top of this, it places limitations on changing
 one of the bits later without modifying the other ones - bitwise or
 functions work well enough when you're over-writing zeros, but if there's
 something there already it might not work so well.

 With this in mind, I would like to suggest a convention which I worked
 out. It uses python modules struct and construct to make code a bit
 easier to read.
 (For reference if anyone is unfamiliar:
 struct - https://docs.python.org/2/library/struct.html
 construct - http://construct.readthedocs.org/en/latest/ )

 In the design I'm working on at the moment (a wideband spectrometer), I
 wrote a python module with the following in it:

 # Bitstruct to control the control register on the ROACH
 control_reg_bitstruct = construct.BitStruct('control_reg',
 construct.Padding(4),   #28-31
 construct.BitField('debug_snap_select',3),  #25-27
 construct.Padding(3),   #22-24
 construct.Flag('fine_tvg_en'),  #21
 construct.Flag('adc_tvg'),  #20
 construct.Flag('fd_fs_tvg'),#19
 construct.Flag('packetiser_tvg'),   #18
 construct.Flag('ct_tvg'),   #17
 construct.Flag('tvg_en'),   #16
 construct.Padding(4),   #12-15
 construct.Flag('fancy_en'), #11
 construct.Flag('adc_protect_disable'),  #10
 construct.Flag('gbe_enable'),   #09
 construct.Flag('gbe_rst'),  #08
 construct.Padding(4),   #04-07
 construct.Flag('clr_status'),   #03
 construct.Flag('arm'),  #02
 construct.Flag('man_sync'), #01
 construct.Flag('sys_rst') ) #00

 This BitStruct makes the code a little bit more readable, tells you what
 each bit does, and if you've done this declaration right once, then you
 don't need to worry about whether you'e shifting numbers by the right
 amount of bits. For the BitFields where several bits are passed, I used a
 dictionary to make remembering things (and reading the code) easier as well:

 # Dictionary for selecting the debug_snap_select bit
 debug_snap_select = {
 'coarse_72':   0,
 'fine_128':1,
 'quant_16':2,
 'ct_64':   3,
 'xaui_128':4,
 'gbetx0_128':  5,
 'buffer_72':   6,
 'finepfb_72':  7 }

 So writing to the register for the first time works like this:

 control_reg = avn.control_reg_bitstruct.parse('\x00\x00\x00\x00') # Create
 a blank one to use...
 # Pulse arm and clr_status high, along with setting gbe_enable and
 adc_protect_disable high
 control_reg.gbe_enable = True
 control_reg.adc_protect_disable = True
 control_reg.clr_status = True
 control_reg.arm = True
 fpga.write_int('control', struct.unpack('I',
 avn.control_reg_bitstruct.build(control_reg))[0]) # The [0] is necessary
 because the fpga.write_int function wants an integer datatype, and
 struct.unpack returns a tuple for some reason.
 # Bring arm and clr_status low again.
 control_reg.clr_status = False
 control_reg.arm = False
 fpga.write_int('control',
 struct.unpack('I',avn.control_reg_bitstruct.build(control_reg))[0])

 Then, for example if you're controlling something with a function and you
 need to change only one part of what's in the register and leave the rest
 unaffected, this is quite easy as well:

 control_reg =
 control_reg_bitstruct.parse(struct.pack('I',fpga.read_uint('control'))) #
 Read the data that's in the register already
 control_reg.debug_snap_select = debug_snap_select['coarse_72'] #
 Update the desired bit (or bits, using the conveniently provided dictionary
 in this case)
 

Re: [casper] casperfpga and fpg's

[Paul Prozesky]

Morning Matt

Yeah, you need to have the new commands in your tcpborphserver3. I'll check
with Marc to get you a newer version and mail you off-list. You're
solo-booting, right?

Regards
Paul


On 18 February 2015 at 03:57, Matt Strader mstra...@physics.ucsb.edu
wrote:

 Hello Casperites,

 I'm looking into using the QDR on Roach2, which I understand needs some
 software calibration.  So, I was looking into the ska-sa/casperfpga repo,
 but I see some code in here uses KATCP commands that I don't have (e.g.
 ?meta, ?progremote).  Is there a newer tcpborphserver3 that has these?

 When connecting to the roach, it tells me my tcpborphserver version is
 #version memcpy-88-g38ad77a-dirty
 #build-state 2013-04-11T11:50:43

 On a possibly related note, I understood from the Casper workshop last
 summer, that .fpg files are like .bof files but contain metadata for the
 gateware design.  Should I be able to use ?progdev to load a .fpg onto a
 Roach2?  When I try I get:

 #log info 11090019 raw
 attempting\_to\_program\_qdr_bram2_2014_May_29_1919.fpg
 #log error 11090028 raw bad\_magic\_in\_file\_bof\_header
 !progdev fail


 Thanks,
 Matt Strader
 Mazin Lab
 UC Santa Barbara

Re: [casper] Simulink freezing after moving blocks

[Paul Prozesky]

Hey Coppers

Ja, Andrew and I both have the same problem and it seems to be Ubuntu.
Andrew went so far as to swap out his AMD/ATi video card for a nVidia one
and it didn't help.

Cheers, save often!
Paul


On 17 February 2015 at 14:01, Charles Copley chop...@gmail.com wrote:

 Hi all,

 Is anyone else having a problem with Simulink freezing (and remaining
 permanently in that state) after dragging/moving something in the design?

 I am having this problem using the following configuration:

 1) mlib_devel_casper
 commit 4c7ba5efb421fda1cec0640cf0e3b830a9987640
 Author: David MacMahon dav...@astro.berkeley.edu
 Date:   Fri Jul 11 13:35:54 2014 -0700

 2) Xilinx version 14.7

 3) Matlab 2012b

 4) This is running on Ubuntu (which may be the problem?)

 Any thoughts/commiseration?

 Cheers,




 Charles Copley

 Cell: +27 (0) 84 430 1160

  ---

Re: [casper] Goto block right click menu helper

[Paul Prozesky]

Hi all

So I added Danny's right-click menu shortcuts to our repo (
github.com/ska-sa/mlib_devel) with some helpers that I use quite a lot. So
all in all:

-Get the size of a block and...
-...Resize selected blocks to that size
-Increment tags in Goto/From blocks
-Make new Goto block with incremented tab
-Make From blocks from Goto blocks

Herewith the demo video: http://www.youtube.com/watch?v=fNdw9Fba8R4

Cheers
Paul


On 3 October 2013 23:41, Danny Price dpr...@cfa.harvard.edu wrote:

 Hi All

 I stumbled across a lifechanging simulink menu customization to
automatically create simulink blocks:

http://www.mathworks.com/matlabcentral/fileexchange/25736-create-from-blocks
 You can see a gif of it in action here:

http://blogs.mathworks.com/images/pick/will_campbell/potw_create_from_blocks/From_Goto.gif

 I modified it a bit so you can also create goto blocks with incremented
names,
 e.g. adc0, adc1, adc2, etc too. For now you can grab them from:
 https://dl.dropboxusercontent.com/u/9870263/sl_menu.zip

 To install, you just need to copy the m-files in that zip to your
mlib_devel/caper_library and restart matlab.

 If any of the git ninjas think this is main-repo worthy, please add it
in...

 Cheers
 Danny

Re: [casper] SFP+ MDIO on ROACH2

[Paul Prozesky]

Afternoon Dave

Yeah, we have a small Python library for interacting with the PHYs and
turning LEDs on and off. I'll get it to you.

Regards
Paul



On 4 October 2013 06:11, David MacMahon dav...@astro.berkeley.edu wrote:

 Does anyone know how to read the SFP+ MDIO information from KATCP?  Would
 there be any useful diagnostic info in there for detecting problematic
 behavior?

 We have found two SFP+ mezzanine boards that have an SFP+ port that seems
 to be misbehaving and we'd like to get as much status info as possible from
 the PHYs.

 Thanks,
 Dave

 P.S.  Is there some trick to making the SFP+ status LEDs work?  Ours are
 always off (and it's not just a light pipe problem, they are really off).

Re: casper-scm registers.info problems

[Paul Prozesky]

Morning.

Yeah, sorry, that was me. I've fixed it. Thanks for the heads-up, Glenn.

It's for a block that wraps the software register so that bitfields written
to/from a register are written to a text file on generation. Then your
control software can read that file and set up bit structures to/from
registers automatically, as opposed to having to enter that information
manually for every bof file.

Cheers
Paul



On Tue, Apr 16, 2013 at 7:13 PM, G Jones jones...@caltech.edu wrote:

 Hi,
 I just tried building a very simple (counter - software register +
 mssge block) roach system with a fresh checkout of ska-sa/mlib_devel
 and ran into a final error: cp cannot stat registers.info: No such
 file or directory. I assume this is related to the latest commits, but
 haven't delved into what's going on. Just wanted to point out that
 whatever this new feature in probably needs to be made more robust.

 Glenn

Re: [casper] Roach2 configuration and setup

[Paul Prozesky]

Afternoon Guy

Regarding question 3... if you're running tcpborphserver3 you can use the
upload_bof method in the FpgaClient class in corr to upload a bof file to
your ROACH. I just checked and it took about 12s to copy a boffile using
this. Once it's uploaded, though, it will skip uploading it unless you
force it to do so. Use progdev to program the device as usual.

Regards
Paul


On 12 February 2013 00:32, Guy kenfack guy.kenf...@gmail.com wrote:

 Hello,
 we received 2 roach2 boards from digicom (20th dec 2012).we managed to
 configure our minicom with centos6.2 final, and tty usb2.
 I've several questions about the advised version for the uboot and the
 tcborphserver3
 u-boot versionof my boards:
 u-boot 2011.06-rc2-0-gd422dc0-dirty(Nov 8 2012 - :16:04:14)
 #SN : Roach2.2 batch = D#6#10
 #kernel : Linux roach 02 06 0A 3.4.0 - rc3+
 Tcpborphserver3
 1/
 a- how can I find the version of my romfs and also how can I find the
 version of my Tcpborphserver3
 b- which version for the uboot and the tcborphserver3 should I use, should
 I keep the current version above ?
 where is it located?

 2/ I heard that the configuration with the SD card is not yet working  ?
 is it still the case ?

 3/I want to load my boffiles, can I use ssh  ? or should Iuse the telnet
 to tranfer my files ?
 How should I do If I want to keep my boffiles alive? I used to store them
 on the SD card, even when shutting down my roach board. Do I need to
 re-load or to copy my boffiles after switching on my roach2 boards?
 I read somewhere that it could be possible to upload from the python
 ?(I've never done it)
 How long does it take to the boffile to be copied ? before launching the
 fpgaprogdev() ?

 Thank you for your help,

Re: [casper] Problem setting parameters in fft blocks using mlib_devel

[Paul Prozesky]

Afternoon Ken

I've seen similar behaviour when the block I'm using is cached by Matlab
oddly. Or that's how I'd describe what happens, anyway. Two quick things to
try:

1. Browse to the CASPER libraries in the library browser. Do they refresh
when you open them?
2. Right click on the offending FFT in the model, click Link Options -
Restore Link, and then click Use Library Block. I recall on occasion having
to actually delete the block from the model and add it again from the
library.

It could also be a problem with the init scripts, though, so post back if
you're still having trouble.

Regards
Paul



On 18 January 2013 17:02, Andrew Martens and...@ska.ac.za wrote:

 Hey Ken

 Problem is a bit hard to get my head around, I don't seem to be getting
 the same results. It may be a version problem, I still am (rather
 ashamedly) using a very old Matlab version. It would be cool if someone
 with similar versions to you could try to replicate your results...

 I will prod the problem again on Monday if no-one has managed to get
 further, the init scripts can be made to generate logs as they run that
 may be helpful.

 Regards
 Andrew

Re: [casper] Request for a sample bof file

[Paul Prozesky]

Morning Tom

The init scripts for the PFB weren't actually ever telling you that you had
an error. Now they do. So you will see some error messages if you open a
design with the old PFB block. And unfortunately, the way the init scripts
are called, you may see the popup more than a few times. So delete the PFB
block and replace it with the one from the library and you should be okay.

Regards
Paul

On 5 April 2012 01:29, Tom Kuiper kui...@jpl.nasa.gov wrote:

 **
 Hi Jason!

 I recently got an account on a machine at JPL that has the CASPER toolflow
 running under Red Hat.  It has ISE 13.4.  I got the SKA-SA mlib_devel
 library and put it in my home directory.  I started Simulink after adding
 this library to the Matlab search path.  Then I loaded the r_spec_1ghz
 model.  It came up with none of the blocks connected and an error message
 pop-up about some vector having width 0 instead of 16.  (Sorry to be vague
 but my notes are at work and I'm not.)  I OK'ed that and then tried to
 update the diagram.  That got me an unending set of error pop-ups.  I had
 to log in from another computer and kill all my MATLAB processes.

 Do you have any thoughts about this?

 Thanks and regards

 Tom


 On 03/05/2012 12:02 AM, Jason Manley wrote:

  For those interested, here is a design similar to tut3 for the katADC...

 Attached is an example of an RFI monitoring system that we used last year
 to do some electric fence measurements, along with some basic software to
 control it. Apologies for the messy nature... it was thrown together rather
 hurriedly. Still, it should demonstrate most of what you want. It uses the
 KATADC in interleaved mode to give a ~900MHz band from a 900MHz, 0dBm clock
 source.

 There is a katadc yellow block in the SKA-SA mlib_devel library and I
 think it's already made its way into the stable, standard CASPER library.
 Get ours here: https://github.com/ska-sa/mlib_devel

 The yellow block initialises the ADC and everything automatically, so you
 shouldn't need anything else in the way of software to configure it. But if
 you want to play with it, the katadc control software resides in corr (the
 packetised correlator control package), available on pypi:
 http://pypi.python.org/pypi/corr or get the bleeding-edge version here:
 https://github.com/ska-sa/corr/. CORR's probably got a lot more in there
 than you need but you can rip-out the bits you want (see src/katadc).

 Jason

 PS:
 to use the included software, run rfi_init.py, then run either rfi_spec or
 rfi_time.py to bring up some plots. Try 'em with the -h flag to see
 command-line options. You will need corr installed to make this lot work
 and you'll also need to modify line 13 in src/cam.py to reflect your
 roach's IP address. You can also add antenna calibration files and things
 to take calibrated electric field measurements so this is a useful little
 instrument.




 On 04 Mar 2012, at 21:38, Tom Kuiper wrote:

  I would like to test a set-up that I've just configured.  I've got a
 KatADC in Z-Doc 0 of a ROACH-1.  The signal is going into IF 0.  Pretty
 much anything will do, though.   It's easy to swap Z-Docs and IF inputs, so
 that's not a constraint.
 
  Even the first stage of a FX correlator would be fine.  The ROACH is
 connected to a computer with a 10 GBe card and there are two GPU enabled
 computers, also with 10 GBe ports, on the same subnet.
 
  The KatADC version of Workshop 2010 Tutorial 3 is nice because it has a
 graphical output that shows everything is working, i.e., I don't have to do
 anymore work :-) .
 
  Thanks and regards,
 
  Tom
 
  --
  I or me? http://www.oxforddictionaries.com/page/145
 
 
 



 --
 I or me? http://www.oxforddictionaries.com/page/145