Re: [casper] questions on DRAM
Thanks Andrew. Good info. Does the address word count bytes? That is, are the lowest 4 bits unused as in a normal DRAM controller. I am getting something out of my DRAM, but it is odd... Does the address count 144bit words or 288 bit words? if I have address count on each clock cycle 0,0,1,1,2,2, etc. so the address is held for 2 clocks, is this correct? Or do I have address go as 0,0,2,2,4,4, etc? I am using the dram by writing to it w/ PPC interface through software, which works. then I read it out to a DAC. The problem is that I am getting wierd data. Is there a way to simulate this? Can I use simulink to store data into the ram (without having to design write-to-dram logic). I would like to have some setting where, say, cos(xx xx xx) is stored into the dram, spec'ed in simulink. Then I can test my readout logic. The idea is to simulate the software interface writing the dram, and firmware reads it out. Thanks Tim - Original Message - From: Andrew Martens and...@ska.ac.za To: Timothy Madden tmad...@aps.anl.gov Cc: casper@lists.berkeley.edu Sent: Sunday, August 25, 2013 4:48:38 PM Subject: Re: [casper] questions on DRAM Hi Tim I have a ROACH board and am using a design I got from another ROACH person. The design uses a lookup table stored in a dram. The software interface is used to load the dram with the data. later, the dram is read out to stream data to MKID DAC board. Questions: I have my FPGA running at 128MHz. The DRAM runs at 200MHz. What speed does the dataout port of the dram spit data? Does it just work at 128MHz and I get a 144 bit word every clock at 128MHz? Or is the dataout running at 200MHz, where I have to send data to FIFO at 200MHz, then readout the FIFO at 128MHz? The data interface to you is a pair of asynchronous FIFOs, one for reading, one for writing. You can write in data or read it back at 128MHz. The logic internal to the SDRAM controller (reading or writing data to or from the FIFOs on the other interface) is running at 200MHz. The higher clock rate ensures that SDRAM overhead (refreshing of banks etc) can be performed at the same time as your operations, even if you are running at the full 128MHz. Do I really care about the FIFO clock rate as long as I can get data at 128MHz? You should care enough to ensure there is enough margin for the overhead but everything else is taken care of for you. From the dram docs on the web: To read data out of the DRAM, hold 'RWn' high, keep the address constant for two FPGA clock cycles, and toggle the 'cmd_valid' pin every clock. Note that a new word will be available on the 'data_out' pin on every clock cycle. 'rd_valid' will frame valid output data some indeterminate number of clock cycles after the read 'cmd_valid' toggles. 'cmd_ack' is high unless an attempt to write a command into the input FIFO failed, at which point it will go low synchronously with the issuing of the failed command. So if I wish to read out address 0, 1, 2, I have to keep the address constant for 2 fpga clocks. Then I can only read out dram at fpga_clock/2? Or, do I toggle cmd_valid, to get address 0, 1 at the 128MHz fpga clock. Now I have to set the addr to 2 and toggle cmd_valid again. IN this case, I still cannot readout the dram at 128MHz. Or perhaps I toggle cmd_valid forever and get data from address 0,1,2,3... on every fpga clock cycle? Yes, you need to hold the address constant for two clock cycles while keeping 'RWn' and 'cmd_valid' high. It reads data in a 'burst', two words are stored at the same address so at some point later 'rd_valid' will go high for two clock cycles and you will get two words. Writing is a similar process, you write two words to the same address in a two word 'burst'. As far as I remember, the Simulink simulation models quite accurately modelled this behaviour. Hope this helps. Regards Andrew
[casper] questions on DRAM
I have a ROACH board and am using a design I got from another ROACH person. The design uses a lookup table stored in a dram. The software interface is used to load the dram with the data. later, the dram is read out to stream data to MKID DAC board. Questions: I have my FPGA running at 128MHz. The DRAM runs at 200MHz. What speed does the dataout port of the dram spit data? Does it just work at 128MHz and I get a 144 bit word every clock at 128MHz? Or is the dataout running at 200MHz, where I have to send data to FIFO at 200MHz, then readout the FIFO at 128MHz? Do I really care about the FIFO clock rate as long as I can get data at 128MHz? From the dram docs on the web: To read data out of the DRAM, hold 'RWn' high, keep the address constant for two FPGA clock cycles, and toggle the 'cmd_valid' pin every clock. Note that a new word will be available on the 'data_out' pin on every clock cycle. 'rd_valid' will frame valid output data some indeterminate number of clock cycles after the read 'cmd_valid' toggles. 'cmd_ack' is high unless an attempt to write a command into the input FIFO failed, at which point it will go low synchronously with the issuing of the failed command. So if I wish to read out address 0, 1, 2, I have to keep the address constant for 2 fpga clocks. Then I can only read out dram at fpga_clock/2? Or, do I toggle cmd_valid, to get address 0, 1 at the 128MHz fpga clock. Now I have to set the addr to 2 and toggle cmd_valid again. IN this case, I still cannot readout the dram at 128MHz. Or perhaps I toggle cmd_valid forever and get data from address 0,1,2,3... on every fpga clock cycle? All of the example model files run at 200MHz, and dram is at 200MHz. So it is not much help. Tim Madden
[casper] Question on fft_wideband_real
Folks I am implementing the ROACH polyphase method w/ pfb_fir and fft_wideband_real. In simulation, nothing seems to come out: all zeros...Do these fft blocks simulate correctly? Question on FFT Say we have 4 input streams, that is, 4 lines of data of one data stream divided into 4 busses that are decimated by 4. So sample rate of whole stream is 512MHz, and sample rate of each decimated stream is 128MHz. This is the normal output from the 4x MKID ADC, where the data is divided into 4 streams. We connect these streams to FFT inputs, assuming a 4K FFT. What will the sample rate of each bin be? Will it be 128MHz/ 4096, or is there more delay and some time domain data is missed? Also, what does sync_out do? I assume it is high for valid FFT coef. data output, but is there any way to trigger on the start of a new FFT coef. set? I guess we have to make a counter to count bins, and hope the counter stays in sync w/ FFT output? Also, what is difference between simultaneous streams and simultaneous inputs when setting up the FFT? Tim Madden
Re: [casper] Question on fft_wideband_real
Thanks for the useful info. Tim - Original Message - From: David MacMahon dav...@astro.berkeley.edu To: Timothy Madden tmad...@aps.anl.gov Cc: casper@lists.berkeley.edu Sent: Thursday, August 22, 2013 12:34:52 PM Subject: Re: [casper] Question on fft_wideband_real Hi, Tim, On Aug 22, 2013, at 10:03 AM, Timothy Madden wrote: In simulation, nothing seems to come out: all zeros...Do these fft blocks simulate correctly? Yes, they should simulate fine. Question on FFT Say we have 4 input streams, that is, 4 lines of data of one data stream divided into 4 busses that are decimated by 4. So sample rate of whole stream is 512MHz, and sample rate of each decimated stream is 128MHz. This is the normal output from the 4x MKID ADC, where the data is divided into 4 streams. We connect these streams to FFT inputs, assuming a 4K FFT. What will the sample rate of each bin be? Will it be 128MHz/ 4096, or is there more delay and some time domain data is missed? Also, what does sync_out do? I assume it is high for valid FFT coef. data output, but is there any way to trigger on the start of a new FFT coef. set? I guess we have to make a counter to count bins, and hope the counter stays in sync w/ FFT output? Also, what is difference between simultaneous streams and simultaneous inputs when setting up the FFT? I think the number of simultaneous inputs is the de-multiplex factor. Fast ADCs sample at a clock rate much higher than the FPGA clock rate. To work with the data, the FPGA must handle multiple ADC samples per FPGA clock cycle. The number of samples handled per FPGA clock cycle (for a single digitized signal) is often called the demux factor. It sounds like the demux factor is 4 for the MKID ADC. For ADC sample rate Fadc and demux factor D, the FPGA fabric will run at Ffpga = Fadc / D. I think the number of simultaneous streams refers to how many signals you want to process in parallel in the FFT. I think it makes multiple parallel FFTs that share twiddle factors. The sync_out lets you know when the output spectrum starts. sync_out hoes high for one cycle preceding the first channel of the output spectrum. sync_out need not go high for every output spectrum. Since the FFT is streaming, the spectra come out one right after the other so you only really need the first sync_out pulse to make sense of the output spectra. Regarding FFT sync, the casper website has a memo that describes some restrictions on the FFT sync_in signal (and therefore the sync_out signal). Basically, you can't assert sync_in for each input window of the FFT. See the memo for details. Are you waiting long enough for the data to start appearing at the output? Which mlib_devel are you using? There is an ongoing flurry of activity (especially related to the FFT and PFB_FIR blocks) as mlib_devel is getting updated for the upcoming CASPER workshop. Hope this helps, Dave
Re: [casper] Problem setting parameters in fft blocks using mlib_devel
Andrew You solved the problem. Thanks for the good work. My fft's seem happy now. Tim - Original Message - From: Andrew Martens and...@ska.ac.za To: Timothy Madden tmad...@aps.anl.gov Cc: casper@lists.berkeley.edu Sent: Monday, August 19, 2013 1:31:40 PM Subject: Re: [casper] Problem setting parameters in fft blocks using mlib_devel Hi Tim Was the following issue (see below) ever solved? I have exactly the same problem with latest libraries at https://github.com/ska-sa Matlab R2012b System Generator is 14.2.4415 Linux- Redhat See below from Ken Treptow from Fermilab: Tim Madden I get the following simulink error if I place a new fft block from the library and try to set parameters. Error:Error invoking object method Error due to multiple causes. -- Error in 'new_adc_test/fft': Initialization commands cannot be evaluated. -- Invalid object name: fft_biplex0/4 This happens with the fft, fft_biplex_real_2x, and fft_biplex_real_4x blocks, but not with the fft_wideband_real block it is working and I can compile with it. I am using Matlab 2012a, Xilinx 14.2, and the latest mlib_devel libraries from today(1/17/2013). Anyone have any ideas on what the problem maybe? Thanks, Ken Not sure about the above issue, but there was a small typo in the fft_biplex init script that I just fixed and pushed the change to the ska-sa repo. This block is shared by the whole fft family. It should now be working if you don't mind doing a git pull. Let me know if you have any further problems. Regards Andrew
Re: [casper] casper libraries- casper_xps in new mlib_devel?
Hi John Thanks for the tip. I got the newest libraries. Question: Is casper_xps no longer casper_xps? Seems to not be defined. What is the command to bring up the xilinx compiler window. Thanks Tim - Original Message - From: John Ford jf...@nrao.edu To: Timothy Madden tmad...@aps.anl.gov Cc: casper@lists.berkeley.edu Sent: Friday, August 16, 2013 4:40:37 PM Subject: Re: [casper] casper libraries Folks It seems that the libraries listed on https://casper.berkeley.edu/wiki/Repositories are all at least 2 years old. Is there REALLY no development on Casper libraries for 2 years? Where does one get something more recent? Tim Madden It's all been moved to github. There are other forks as well. I'm not sure of all of them, but these 2 will get you started. :) https://github.com/casper-astro https://github.com/ska-sa
Re: [casper] casper libraries
John It seems the https://github.com/casper-astro repo has bee_xps.m. There is no casper_xps The ska-sa repo has a casper_xps. I will try out the ska-aa repo. Tim - Original Message - From: Timothy Madden tmad...@aps.anl.gov To: John Ford jf...@nrao.edu Cc: casper@lists.berkeley.edu Sent: Monday, August 19, 2013 10:19:58 AM Subject: Re: [casper] casper libraries I am in, T - Original Message - From: John Ford jf...@nrao.edu To: Timothy Madden tmad...@aps.anl.gov Cc: casper@lists.berkeley.edu Sent: Friday, August 16, 2013 4:40:37 PM Subject: Re: [casper] casper libraries Folks It seems that the libraries listed on https://casper.berkeley.edu/wiki/Repositories are all at least 2 years old. Is there REALLY no development on Casper libraries for 2 years? Where does one get something more recent? Tim Madden It's all been moved to github. There are other forks as well. I'm not sure of all of them, but these 2 will get you started. :) https://github.com/casper-astro https://github.com/ska-sa
Re: [casper] Problem setting parameters in fft blocks using mlib_devel
Was the following issue (see below) ever solved? I have exactly the same problem with latest libraries at https://github.com/ska-sa Matlab R2012b System Generator is 14.2.4415 Linux- Redhat See below from Ken Treptow from Fermilab: Tim Madden I get the following simulink error if I place a new fft block from the library and try to set parameters. Error:Error invoking object method Error due to multiple causes. -- Error in 'new_adc_test/fft': Initialization commands cannot be evaluated. -- Invalid object name: fft_biplex0/4 This happens with the fft, fft_biplex_real_2x, and fft_biplex_real_4x blocks, but not with the fft_wideband_real block it is working and I can compile with it. I am using Matlab 2012a, Xilinx 14.2, and the latest mlib_devel libraries from today(1/17/2013). Anyone have any ideas on what the problem maybe? Thanks, Ken
[casper] casper libraries
Folks It seems that the libraries listed on https://casper.berkeley.edu/wiki/Repositories are all at least 2 years old. Is there REALLY no development on Casper libraries for 2 years? Where does one get something more recent? Tim Madden
Re: [casper] Changing Clock Source on MSSGE ROACH Block
That makes sense. Thanks alot! T - Original Message - From: Henno Kriel he...@ska.ac.za To: Timothy Madden tmad...@aps.anl.gov Cc: Casper Lists casper@lists.berkeley.edu Sent: Thursday, April 25, 2013 11:39:05 PM Subject: Re: [casper] Changing Clock Source on MSSGE ROACH Block Hi Tim Are you using one of the CASPER DAC yellow blocks? You are also using dac1_clk and not dac0_clk - are you using 2 DAC boards? Henno On Thu, Apr 25, 2013 at 10:49 PM, Timothy Madden tmad...@aps.anl.gov wrote: Dear Caspar: I have a design that compiles fine when I have the clock on the MSSGE ROACH block set to sys_clk 100MHz. If I set the clock to dac1_clk, 100MHz, or other clocks I get lots of compile errors of the sort below. Basically, the Xilinx compiler thinks the clock pins are disconnected on many of the blocks. If I set the clock back to sys_clk, it compiles fine again. Here is an example error. I get many of these. Constructing platform-level connectivity ... ERROR:EDK:4072 - INSTANCE: sys_block_inst, PORT: fab_clk - port is driven by a sourceless connector - /home/oxygen26/TMADDEN/ROACH/projcts/singen/XPS_ROACH_base/system.mhs line 148 I am running in Linux, Matlab R2012b. XSG version is 14.2 Tim Madden Argonne Lab -- Henno Kriel DSP Engineer Digital Back End meerKAT SKA South Africa Third Floor The Park Park Road (off Alexandra Road) Pinelands 7405 Western Cape South Africa Latitude: -33.94329 (South); Longitude: 18.48945 (East). (p) +27 (0)21 506 7300 (p) +27 (0)21 506 7365 (direct) (f) +27 (0)21 506 7375 (m) +27 (0)84 504 5050
Re: [casper] Changing Clock Source on MSSGE ROACH Block
That has to be the problem! Thanks. T - Original Message - From: Andrew Martens and...@ska.ac.za To: Henno Kriel he...@ska.ac.za Cc: Timothy Madden tmad...@aps.anl.gov, Casper Lists casper@lists.berkeley.edu Sent: Friday, April 26, 2013 12:35:48 AM Subject: Re: [casper] Changing Clock Source on MSSGE ROACH Block Hi Tim Are you using one of the CASPER DAC yellow blocks? You are also using dac1_clk and not dac0_clk - are you using 2 DAC boards? Henno To expand on what Henno has said, if you specify that you will be using a clock source besides those derived from the onboard oscillator (sys_clk, arb_clk), then you need to include the related yellow block i.e if you say you are going to use dac1_clk, then you must include a DAC yellow block with the appropriate parameters set. The toolflow does not check that you have added the required block and will find that it is missing the required clock signal at some later time in the compile. Cheers Andrew On Thu, Apr 25, 2013 at 10:49 PM, Timothy Madden tmad...@aps.anl.gov wrote: Dear Caspar: I have a design that compiles fine when I have the clock on the MSSGE ROACH block set to sys_clk 100MHz. If I set the clock to dac1_clk, 100MHz, or other clocks I get lots of compile errors of the sort below. Basically, the Xilinx compiler thinks the clock pins are disconnected on many of the blocks. If I set the clock back to sys_clk, it compiles fine again. Here is an example error. I get many of these. Constructing platform-level connectivity ... ERROR:EDK:4072 - INSTANCE: sys_block_inst, PORT: fab_clk - port is driven by a sourceless connector - /home/oxygen26/TMADDEN/ROACH/projcts/singen/XPS_ROACH_base/system.mhs line 148 I am running in Linux, Matlab R2012b. XSG version is 14.2 Tim Madden Argonne Lab -- Henno Kriel DSP Engineer Digital Back End meerKAT SKA South Africa Third Floor The Park Park Road (off Alexandra Road) Pinelands 7405 Western Cape South Africa Latitude: -33.94329 (South); Longitude: 18.48945 (East). (p) +27 (0)21 506 7300 (p) +27 (0)21 506 7365 (direct) (f) +27 (0)21 506 7375 (m) +27 (0)84 504 5050
[casper] Changing Clock Source on MSSGE ROACH Block
Dear Caspar: I have a design that compiles fine when I have the clock on the MSSGE ROACH block set to sys_clk 100MHz. If I set the clock to dac1_clk, 100MHz, or other clocks I get lots of compile errors of the sort below. Basically, the Xilinx compiler thinks the clock pins are disconnected on many of the blocks. If I set the clock back to sys_clk, it compiles fine again. Here is an example error. I get many of these. Constructing platform-level connectivity ... ERROR:EDK:4072 - INSTANCE: sys_block_inst, PORT: fab_clk - port is driven by a sourceless connector - /home/oxygen26/TMADDEN/ROACH/projcts/singen/XPS_ROACH_base/system.mhs line 148 I am running in Linux, Matlab R2012b. XSG version is 14.2 Tim Madden Argonne Lab
[casper] Questino on Shared RAM
Dear Casper I am simulating a design in simulink. I am using a yellow shared memory block for a Roach board. In pure software simulation, is there a way to see what was written to the memory? Tim
[casper] Linux Toolflow
To the Casper list: I have written a few times in this topic... I am now using ISE14.2 with matlab 2012b. I am using the scripts from https://github.com/ska-sa/mlib_devel, found in https://github.com/ska-sa/mlib_devel/startsg I can now draw the 1st part of Tutorial 1, adding counter, slice, gpio, System Generator, XSG core config, and terminator. I am just trying to compile the 1st part to flash a LED on the roach board. The compilier runs for awhile, generates lots of messages and ends up with the following: --- Xilinx EDK 14.1 Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Input File: system.xmp Creating backup of system.log as system_log.13.4 Format revision from 13.4 to 14.1 completed. No changes to design files while updating the design from 13.4 to 14.1 Moving all revup related files to 'revup' folder... Xilinx EDK 14.2 Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. Input File: system.xmp Creating backup of system.log as system_log.14.1 Format revision from 14.1 to 14.2 completed. No changes to design files while updating the design from 14.1 to 14.2 Moving all revup related files to 'revup' folder... Format revision of project to EDK 14.2 completed ERROR:EDK - IPNAME: opb_v20, INSTANCE: opb0 - cannot find MPD for the pcore 'opb_v20_v1_10_c' in any of the repositories - /home/oxygen26/TMADDEN/ROACH/projects/t1/XPS_ROACH_base/system.mhs line 95 ERROR:EDK - IPNAME: opb_v20, INSTANCE: opb0 - cannot find MPD for the pcore - /home/oxygen26/TMADDEN/ROACH/projects/t1/XPS_ROACH_base/system.mhs line 95 ERROR:EDK - while loading XMP file XPS% Evaluating file run_xps.tcl ERROR:EDK - Load a MHS or XMP file first Error using gen_xps_files (line 640) XPS failed. My version info is as follows: Linux 64, Redhat ver --- MATLAB Version: 8.0.0.783 (R2012b) MATLAB License Number: 2136 Operating System: Linux 2.6.32-220.7.1.el6.x86_64 #1 SMP Fri Feb 10 15:22:22 EST 2012 x86_64 Java Version: Java 1.6.0_17-b04 with Sun Microsystems Inc. Java HotSpot(TM) 64-Bit Server VM mixed mode --- MATLABVersion 8.0 (R2012b) Simulink Version 8.0 (R2012b) Control System ToolboxVersion 9.4 (R2012b) Curve Fitting Toolbox Version 3.3 (R2012b) DSP System ToolboxVersion 8.3 (R2012b) Fixed-Point Toolbox Version 3.6 (R2012b) Image Processing Toolbox Version 8.1 (R2012b) MATLAB Compiler Version 4.18 (R2012b) Optimization Toolbox Version 6.2.1 (R2012b) Partial Differential Equation Toolbox Version 1.1 (R2012b) Robust Control ToolboxVersion 4.2 (R2012b) Signal Processing Toolbox Version 6.18 (R2012b) Simulink Control Design Version 3.6 (R2012b) Simulink Fixed Point Version 7.2 (R2012b) Statistics ToolboxVersion 8.1 (R2012b) System Identification Toolbox Version 8.1 (R2012b) Wavelet Toolbox Version 4.10 (R2012b) Xilinx System Generator Version 14.2 production build Thanks Tim Madden
[casper] Linux Toolflow
It is Tim Madden again. I fixed the problem from the last email. Now I am on to the next problem The fix is in https://casper.berkeley.edu/wiki/MSSGE_Setup_with_Xilinx_14.2_and_Matlab_2012a Tim
[casper] Problem with Toolflow in Linux
To whom it may concern: I am getting start with Casper/Roach at Argonne Lab in Chicago. I cannot get the 1st tutorial to work. When I drop a counter (from the Xilinx library) on to a model, and try to set up the counter I get a window that says: --Error evaluating 'OpenFcn' callback of Xilinx Counter Block block (mask) 'tut1/Counter'.-- Undefined variable com or class com/x ilinx.sysgen.socketinterface.NativeMatlabInterface.getInstance. Below are the versions I am using. Tim Madden Argonne Lab. ver --- MATLAB Version: 8.0.0.783 (R2012b) MATLAB License Number: 2136 Operating System: Linux 2.6.32-220.7.1.el6.x86_64 #1 SMP Fri Feb 10 15:22:22 EST 2012 x86_64 Java Version: Java 1.6.0_17-b04 with Sun Microsystems Inc. Java HotSpot(TM) 64-Bit Server VM mixed mode --- MATLABVersion 8.0 (R2012b) Simulink Version 8.0 (R2012b) Control System ToolboxVersion 9.4 (R2012b) Curve Fitting Toolbox Version 3.3 (R2012b) DSP System ToolboxVersion 8.3 (R2012b) Fixed-Point Toolbox Version 3.6 (R2012b) Image Processing Toolbox Version 8.1 (R2012b) MATLAB Compiler Version 4.18 (R2012b) Optimization Toolbox Version 6.2.1 (R2012b) Partial Differential Equation Toolbox Version 1.1 (R2012b) Robust Control ToolboxVersion 4.2 (R2012b) Signal Processing Toolbox Version 6.18 (R2012b) Simulink Control Design Version 3.6 (R2012b) Simulink Fixed Point Version 7.2 (R2012b) Statistics ToolboxVersion 8.1 (R2012b) System Identification Toolbox Version 8.1 (R2012b) Wavelet Toolbox Version 4.10 (R2012b) Xilinx System Generator Version 14.1 production build
