Hey Suraj.
I've been working on Verilog code that requires the application of a
MAXDELAY constraint to an 8 bit data bus output from a register
explicitly forced into the Input/Output Buffer. When I apply the
constraint to the whole bus, PAR results show that the Xilinx tools
attempt to apply a MAXDELAY of 0 ns to bit 6 ONLY, while properly
applying the MAXDELAY = 2 ns to the other bits. This result is the
same over each of the 16 busses to which I have applied this
constraint. A workaround I am using right now is to apply the
constraint to each individual bit, but this prevents me from
parameterizing the module how I would like to. Does anybody know
either (1) how I can use some equivalent of a Verilog generate to make
sure that the constraint gets applied to each bit of an arbitrary
width bus, or (2) why the constraint gets misinterpreted?
This is an interesting problem that I have run into and, up until now,
never found a solution to.
However, today I cracked it.
Consider this verilog code snippet:
wire [3:0] leddies_reg;
wire [3:0] leddies_int;
genvar gen_i;
generate for (gen_i = 0; gen_i < 4; gen_i = gen_i + 1) begin: max_delay_gen
(* MAXDELAY = "8 ns" *) wire int0 = leddies_reg[gen_i];
assign leddies_int[gen_i] = int0;
end endgenerate
This will attach the MAXDELAY constraint by attaching the constraint to
the intermediate int0 wire, and using that wire to connect the
target(leddies_reg) to the intermediate(leddies_int) one by one.
It ain't pretty but it works.
Also I'm damn sure that there is some kind of xilinx bug with attaching
constraints to buses.
In my opinion:
wire [7:0] mybus
//synthesis attribute MAXDELAY of mybus is 2 ns
or
(* MAXDELAY = "2 ns") wire [7:0] mybus;
should both work. But they don't. For some reason, as you have
experienced, some net get the constraint and some get 0ns. I'm almost
100% that this is a xilinx bug.
Hopefully this helps.
Cheers,
David
--
David George
Digital Design Engineer
Karoo Array Telescope
Tel: +27 21 531-7282
Fax: +27 21 531-9761
Email: david.geo...@ska.ac.za
Web: www.ska.ac.za
