[clang] [clang][ARM] Fix warning for using VFP from interrupts. (PR #91870)

[Oliver Stannard via cfe-commits]

https://github.com/ostannard approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/91870
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[clang] [llvm] [ARM] r11 is reserved when using -mframe-chain=aapcs (PR #86951)

[Oliver Stannard via cfe-commits]

https://github.com/ostannard closed 
https://github.com/llvm/llvm-project/pull/86951
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[clang] 5b8e7ed - [AArch64][Driver] Mark test as requiring AArch64 backend

[Oliver Stannard via cfe-commits]

Author: Oliver Stannard
Date: 2024-02-15T12:59:16Z
New Revision: 5b8e7ed787f6e537876c4fdafd070eba9681f343

URL: 
https://github.com/llvm/llvm-project/commit/5b8e7ed787f6e537876c4fdafd070eba9681f343
DIFF: 
https://github.com/llvm/llvm-project/commit/5b8e7ed787f6e537876c4fdafd070eba9681f343.diff

LOG: [AArch64][Driver] Mark test as requiring AArch64 backend

Added: 


Modified: 
clang/test/Driver/aarch64-soft-float-abi.c

Removed: 




diff  --git a/clang/test/Driver/aarch64-soft-float-abi.c 
b/clang/test/Driver/aarch64-soft-float-abi.c
index 08dd5418961932..c277f17aa1c6c4 100644
--- a/clang/test/Driver/aarch64-soft-float-abi.c
+++ b/clang/test/Driver/aarch64-soft-float-abi.c
@@ -1,3 +1,5 @@
+// REQUIRES: aarch64-registered-target
+
 // Hard-float, valid
 // RUN: %clang --target=aarch64-none-elf   -c %s 
-o /dev/null
 // RUN: %clang --target=aarch64-none-elf   -mabi=aapcs -c %s 
-o /dev/null



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[clang] e345b45 - Mark tests as requiring AMDGPU target

[Oliver Stannard via cfe-commits]

Author: Oliver Stannard
Date: 2021-08-05T10:02:51+01:00
New Revision: e345b45bf1b5db03f00c3b3612d2653790a2b879

URL: 
https://github.com/llvm/llvm-project/commit/e345b45bf1b5db03f00c3b3612d2653790a2b879
DIFF: 
https://github.com/llvm/llvm-project/commit/e345b45bf1b5db03f00c3b3612d2653790a2b879.diff

LOG: Mark tests as requiring AMDGPU target

Added: 


Modified: 
clang/test/CodeGenOpenCL/builtins-fp-atomics-gfx8.cl
clang/test/CodeGenOpenCL/builtins-fp-atomics-gfx90a.cl

Removed: 




diff  --git a/clang/test/CodeGenOpenCL/builtins-fp-atomics-gfx8.cl 
b/clang/test/CodeGenOpenCL/builtins-fp-atomics-gfx8.cl
index 07e3c0944b63d..11854733e153b 100644
--- a/clang/test/CodeGenOpenCL/builtins-fp-atomics-gfx8.cl
+++ b/clang/test/CodeGenOpenCL/builtins-fp-atomics-gfx8.cl
@@ -3,6 +3,8 @@
 // RUN: %clang_cc1 -O0 -cl-std=CL2.0 -triple amdgcn-amd-amdhsa -target-cpu 
gfx810 \
 // RUN:   -S -o - %s | FileCheck -check-prefix=GFX8 %s
 
+// REQUIRES: amdgpu-registered-target
+
 // CHECK-LABEL: test_fadd_local
 // CHECK: call float @llvm.amdgcn.ds.fadd.f32(float addrspace(3)* %{{.*}}, 
float %{{.*}}, i32 0, i32 0, i1 false)
 // GFX8-LABEL: test_fadd_local$local:

diff  --git a/clang/test/CodeGenOpenCL/builtins-fp-atomics-gfx90a.cl 
b/clang/test/CodeGenOpenCL/builtins-fp-atomics-gfx90a.cl
index f9e44403a679c..198c51fb873ee 100644
--- a/clang/test/CodeGenOpenCL/builtins-fp-atomics-gfx90a.cl
+++ b/clang/test/CodeGenOpenCL/builtins-fp-atomics-gfx90a.cl
@@ -4,6 +4,8 @@
 // RUN: %clang_cc1 -O0 -cl-std=CL2.0 -triple amdgcn-amd-amdhsa -target-cpu 
gfx90a \
 // RUN:   -S -o - %s | FileCheck -check-prefix=GFX90A %s
 
+// REQUIRES: amdgpu-registered-target
+
 typedef half __attribute__((ext_vector_type(2))) half2;
 
 // CHECK-LABEL: test_global_add_f64



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[clang] 92260d7 - Revert "[CMake][ELF] Add -fno-semantic-interposition and -Bsymbolic-functions"

[Oliver Stannard via cfe-commits]

Author: Oliver Stannard
Date: 2021-05-13T14:31:17+01:00
New Revision: 92260d7a186425510e96b7036b467a6889d08d97

URL: 
https://github.com/llvm/llvm-project/commit/92260d7a186425510e96b7036b467a6889d08d97
DIFF: 
https://github.com/llvm/llvm-project/commit/92260d7a186425510e96b7036b467a6889d08d97.diff

LOG: Revert "[CMake][ELF] Add -fno-semantic-interposition and 
-Bsymbolic-functions"

This reverts commit 3bf1acab5b454ad7fb2074b34663108b53620695.

This is causing the test `gcov-shared-flush.c' to fail on the 2-stage
aarch64 buildbots (https://lab.llvm.org/buildbot/#/builders/7/builds/2720).

Added: 


Modified: 
clang/tools/clang-shlib/CMakeLists.txt
llvm/cmake/modules/HandleLLVMOptions.cmake
llvm/tools/llvm-shlib/CMakeLists.txt

Removed: 




diff  --git a/clang/tools/clang-shlib/CMakeLists.txt 
b/clang/tools/clang-shlib/CMakeLists.txt
index 73e806c49555..5949223fc8e3 100644
--- a/clang/tools/clang-shlib/CMakeLists.txt
+++ b/clang/tools/clang-shlib/CMakeLists.txt
@@ -48,8 +48,3 @@ add_clang_library(clang-cpp
   ${_OBJECTS}
   LINK_LIBS
   ${_DEPS})
-# Optimize function calls and global variable access for default visibility
-# definitions to avoid PLT and reduce dynamic relocations.
-if (NOT APPLE)
-  target_link_options(clang-cpp PRIVATE LINKER:-Bsymbolic-functions)
-endif()

diff  --git a/llvm/cmake/modules/HandleLLVMOptions.cmake 
b/llvm/cmake/modules/HandleLLVMOptions.cmake
index 81f46cf116cf..a64644a08e59 100644
--- a/llvm/cmake/modules/HandleLLVMOptions.cmake
+++ b/llvm/cmake/modules/HandleLLVMOptions.cmake
@@ -305,7 +305,6 @@ if( LLVM_ENABLE_PIC )
 # On Windows all code is PIC. MinGW warns if -fPIC is used.
   else()
 add_flag_or_print_warning("-fPIC" FPIC)
-add_flag_if_supported("-fno-semantic-interposition" 
FNO_SEMANTIC_INTERPOSITION)
   endif()
   # GCC for MIPS can miscompile LLVM due to PR37701.
   if(CMAKE_COMPILER_IS_GNUCXX AND LLVM_NATIVE_ARCH STREQUAL "Mips" AND

diff  --git a/llvm/tools/llvm-shlib/CMakeLists.txt 
b/llvm/tools/llvm-shlib/CMakeLists.txt
index 7259ba263658..b0ee19049e6f 100644
--- a/llvm/tools/llvm-shlib/CMakeLists.txt
+++ b/llvm/tools/llvm-shlib/CMakeLists.txt
@@ -50,9 +50,6 @@ if(LLVM_BUILD_LLVM_DYLIB)
   # Solaris ld does not accept global: *; so there is no way to version 
*all* global symbols
   set(LIB_NAMES 
-Wl,--version-script,${LLVM_LIBRARY_DIR}/tools/llvm-shlib/simple_version_script.map
 ${LIB_NAMES})
 endif()
-# Optimize function calls and global variable access for default visibility
-# definitions to avoid PLT and reduce dynamic relocations.
-target_link_options(LLVM PRIVATE LINKER:-Bsymbolic-functions)
   elseif("${CMAKE_SYSTEM_NAME}" STREQUAL "Darwin")
 set(LIB_NAMES -Wl,-all_load ${LIB_NAMES})
   endif()



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[clang] e80b81d - [Support] Fix formatted_raw_ostream for UTF-8

[Oliver Stannard via cfe-commits]

Author: Oliver Stannard
Date: 2020-07-06T16:18:15+01:00
New Revision: e80b81d1cbf85dcd427759369978afdb48f0998f

URL: 
https://github.com/llvm/llvm-project/commit/e80b81d1cbf85dcd427759369978afdb48f0998f
DIFF: 
https://github.com/llvm/llvm-project/commit/e80b81d1cbf85dcd427759369978afdb48f0998f.diff

LOG: [Support] Fix formatted_raw_ostream for UTF-8

* The getLine and getColumn functions need to update the position, or
  they will return stale data for buffered streams. This fixes a bug in
  the clang -analyzer-checker-option-help option, which was not wrapping
  the help text correctly when stdout is not a TTY.
* If the stream contains multi-byte UTF-8 sequences, then the whole
  sequence needs to be considered to be a single character. This has the
  edge case that the buffer might fill up and be flushed part way
  through a character.
* If the stream contains East Asian wide characters, these will be
  rendered twice as wide as other characters, so we need to increase the
  column count to match.

This doesn't attempt to handle everything unicode can do (combining
characters, right-to-left markers, ...), but hopefully covers most
things likely to be common in messages and source code we might want to
print.

Differential revision: https://reviews.llvm.org/D76291

Added: 


Modified: 
clang/test/Analysis/checker-plugins.c
llvm/include/llvm/Support/FormattedStream.h
llvm/lib/Support/FormattedStream.cpp
llvm/test/MC/ARM/lsl-zero.s
llvm/unittests/Support/formatted_raw_ostream_test.cpp

Removed: 




diff  --git a/clang/test/Analysis/checker-plugins.c 
b/clang/test/Analysis/checker-plugins.c
index fbc9c9bd1c22..69fab8fa6eed 100644
--- a/clang/test/Analysis/checker-plugins.c
+++ b/clang/test/Analysis/checker-plugins.c
@@ -116,4 +116,5 @@ void caller() {
 // RUN:   2>&1 | FileCheck %s -check-prefix=CHECK-CHECKER-OPTION-HELP
 
 // CHECK-CHECKER-OPTION-HELP: example.MyChecker:ExampleOption  (bool) This is 
an
-// CHECK-CHECKER-OPTION-HELP-SAME: example checker opt. (default: false)
+// CHECK-CHECKER-OPTION-HELP-SAME: example checker opt. (default:
+// CHECK-CHECKER-OPTION-HELP-NEXT: false)

diff  --git a/llvm/include/llvm/Support/FormattedStream.h 
b/llvm/include/llvm/Support/FormattedStream.h
index b49c8d86531d..5f937cfa7984 100644
--- a/llvm/include/llvm/Support/FormattedStream.h
+++ b/llvm/include/llvm/Support/FormattedStream.h
@@ -14,6 +14,7 @@
 #ifndef LLVM_SUPPORT_FORMATTEDSTREAM_H
 #define LLVM_SUPPORT_FORMATTEDSTREAM_H
 
+#include "llvm/ADT/SmallString.h"
 #include "llvm/Support/raw_ostream.h"
 #include 
 
@@ -21,8 +22,11 @@ namespace llvm {
 
 /// formatted_raw_ostream - A raw_ostream that wraps another one and keeps 
track
 /// of line and column position, allowing padding out to specific column
-/// boundaries and querying the number of lines written to the stream.
-///
+/// boundaries and querying the number of lines written to the stream. This
+/// assumes that the contents of the stream is valid UTF-8 encoded text. This
+/// doesn't attempt to handle everything Unicode can do (combining characters,
+/// right-to-left markers, etc), but should cover the cases likely to appear in
+/// source code or diagnostic messages.
 class formatted_raw_ostream : public raw_ostream {
   /// TheStream - The real stream we output to. We set it to be
   /// unbuffered, since we're already doing our own buffering.
@@ -40,6 +44,14 @@ class formatted_raw_ostream : public raw_ostream {
   ///
   const char *Scanned;
 
+  /// PartialUTF8Char - Either empty or a prefix of a UTF-8 code unit sequence
+  /// for a Unicode scalar value which should be prepended to the buffer for 
the
+  /// next call to ComputePosition. This is needed when the buffer is flushed
+  /// when it ends part-way through the UTF-8 encoding of a Unicode scalar
+  /// value, so that we can compute the display width of the character once we
+  /// have the rest of it.
+  SmallString<4> PartialUTF8Char;
+
   void write_impl(const char *Ptr, size_t Size) override;
 
   /// current_pos - Return the current position within the stream,
@@ -52,10 +64,16 @@ class formatted_raw_ostream : public raw_ostream {
   }
 
   /// ComputePosition - Examine the given output buffer and figure out the new
-  /// position after output.
-  ///
+  /// position after output. This is safe to call multiple times on the same
+  /// buffer, as it records the most recently scanned character and resumes 
from
+  /// there when the buffer has not been flushed.
   void ComputePosition(const char *Ptr, size_t size);
 
+  /// UpdatePosition - scan the characters in [Ptr, Ptr+Size), and update the
+  /// line and column numbers. Unlike ComputePosition, this must be called
+  /// exactly once on each region of the buffer.
+  void UpdatePosition(const char *Ptr, size_t Size);
+
   void setStream(raw_ostream ) {
 releaseStream();
 
@@ -105,11 +123,17 @@ class 

[clang] 78654e8 - Revert "Reland D74436 "Change clang option -ffp-model=precise to select ffp-contract=on"""

[Oliver Stannard via cfe-commits]

Author: Oliver Stannard
Date: 2020-02-19T12:03:27Z
New Revision: 78654e8511cf16d49f6680d782f3771a767ba942

URL: 
https://github.com/llvm/llvm-project/commit/78654e8511cf16d49f6680d782f3771a767ba942
DIFF: 
https://github.com/llvm/llvm-project/commit/78654e8511cf16d49f6680d782f3771a767ba942.diff

LOG: Revert "Reland D74436 "Change clang option -ffp-model=precise to select 
ffp-contract=on"""

Reverting because this patch is causing ~20 llvm-test-suite failures on
a number of different bots:
* http://lab.llvm.org:8011/builders/clang-cmake-armv8-lld/builds/3366
* http://lab.llvm.org:8011/builders/clang-cmake-aarch64-lld/builds/8222
* http://lab.llvm.org:8011/builders/clang-cmake-x86_64-avx2-linux/builds/13275
* http://lab.llvm.org:8011/builders/clang-s390x-linux-lnt/builds/17213

This reverts commit cd2c5af6dfd6e32ee7043894bcb42981ce99e8ac.

Added: 


Modified: 
clang/docs/UsersManual.rst
clang/lib/Driver/ToolChains/Clang.cpp
clang/test/CodeGen/ppc-emmintrin.c
clang/test/CodeGen/ppc-xmmintrin.c
clang/test/Driver/fp-model.c

Removed: 




diff  --git a/clang/docs/UsersManual.rst b/clang/docs/UsersManual.rst
index 6c8c9f802082..856d5e34bbcc 100644
--- a/clang/docs/UsersManual.rst
+++ b/clang/docs/UsersManual.rst
@@ -1190,50 +1190,8 @@ installed.
 Controlling Floating Point Behavior
 ---
 
-Clang provides a number of ways to control floating point behavior, including
-with command line options and source pragmas. This section
-describes the various floating point semantic modes and the corresponding 
options.
-
-.. csv-table:: Floating Point Semantic Modes
-  :header: "Mode", "Values"
-  :widths: 15, 30, 30
-
-  "except_behavior", "{ignore, strict, may_trap}", "ffp-exception-behavior"
-  "fenv_access", "{off, on}", "(none)"
-  "rounding_mode", "{dynamic, tonearest, downward, upward, towardzero}", 
"frounding-math"
-  "contract", "{on, off, fast}", "ffp-contract"
-  "denormal_fp_math", "{IEEE, PreserveSign, PositiveZero}", "fdenormal-fp-math"
-  "denormal_fp32_math", "{IEEE, PreserveSign, PositiveZero}", 
"fdenormal-fp-math-fp32"
-  "support_math_errno", "{on, off}", "fmath-errno"
-  "no_honor_nans", "{on, off}", "fhonor-nans"
-  "no_honor_infinities", "{on, off}", "fhonor-infinities"
-  "no_signed_zeros", "{on, off}", "fsigned-zeros"
-  "allow_reciprocal", "{on, off}", "freciprocal-math"
-  "allow_approximate_fns", "{on, off}", "(none)"
-  "allow_reassociation", "{on, off}", "fassociative-math"
-
-
-This table describes the option settings that correspond to the three
-floating point semantic models: precise (the default), strict, and fast.
-
-
-.. csv-table:: Floating Point Models
-  :header: "Mode", "Precise", "Strict", "Fast"
-  :widths: 25, 15, 15, 15
-
-  "except_behavior", "ignore", "strict", "ignore"
-  "fenv_access", "off", "on", "off"
-  "rounding_mode", "tonearest", "dynamic", "tonearest"
-  "contract", "on", "off", "fast"
-  "denormal_fp_math", "IEEE", "IEEE", "PreserveSign"
-  "denormal_fp32_math", "IEEE","IEEE", "PreserveSign"
-  "support_math_errno", "on", "on", "off"
-  "no_honor_nans", "off", "off", "on"
-  "no_honor_infinities", "off", "off", "on"
-  "no_signed_zeros", "off", "off", "on"
-  "allow_reciprocal", "off", "off", "on"
-  "allow_approximate_fns", "off", "off", "on"
-  "allow_reassociation", "off", "off", "on"
+Clang provides a number of ways to control floating point behavior. The options
+are listed below.
 
 .. option:: -ffast-math
 
@@ -1427,7 +1385,7 @@ Note that floating-point operations performed as part of 
constant initialization
and ``fast``.
Details:
 
-   * ``precise`` Disables optimizations that are not value-safe on 
floating-point data, although FP contraction (FMA) is enabled 
(``-ffp-contract=on``).  This is the default behavior.
+   * ``precise`` Disables optimizations that are not value-safe on 
floating-point data, although FP contraction (FMA) is enabled 
(``-ffp-contract=fast``).  This is the default behavior.
* ``strict`` Enables ``-frounding-math`` and 
``-ffp-exception-behavior=strict``, and disables contractions (FMA).  All of 
the ``-ffast-math`` enablements are disabled.
* ``fast`` Behaves identically to specifying both ``-ffast-math`` and 
``ffp-contract=fast``
 

diff  --git a/clang/lib/Driver/ToolChains/Clang.cpp 
b/clang/lib/Driver/ToolChains/Clang.cpp
index 1d9e741f4cf8..1091db691858 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -2525,9 +2525,10 @@ static void RenderFloatingPointOptions(const ToolChain 
, const Driver ,
 
   llvm::DenormalMode DenormalFPMath = DefaultDenormalFPMath;
   llvm::DenormalMode DenormalFP32Math = DefaultDenormalFP32Math;
-  StringRef FPContract = "on";
+  StringRef FPContract = "";
   bool StrictFPModel = false;
 
+
   if (const Arg *A = Args.getLastArg(options::OPT_flimited_precision_EQ)) {
 

[clang] 6c20314 - [clang] Remove raw string literals in macros

[Oliver Stannard via cfe-commits]

Author: Oliver Stannard
Date: 2020-01-13T12:38:58Z
New Revision: 6c203149b60e92e802df0c7a431744c337830a09

URL: 
https://github.com/llvm/llvm-project/commit/6c203149b60e92e802df0c7a431744c337830a09
DIFF: 
https://github.com/llvm/llvm-project/commit/6c203149b60e92e802df0c7a431744c337830a09.diff

LOG: [clang] Remove raw string literals in macros

Older (but still supported) versions of GCC don't handle C++11 raw
string literals in macro parameters correctly.

Added: 


Modified: 
clang/unittests/AST/ASTTraverserTest.cpp
clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp

Removed: 




diff  --git a/clang/unittests/AST/ASTTraverserTest.cpp 
b/clang/unittests/AST/ASTTraverserTest.cpp
index 4b982431297c..88921a002053 100644
--- a/clang/unittests/AST/ASTTraverserTest.cpp
+++ b/clang/unittests/AST/ASTTraverserTest.cpp
@@ -342,9 +342,7 @@ B func12() {
 
   {
 auto FN = getFunctionNode("func1");
-
-EXPECT_EQ(dumpASTString(ast_type_traits::TK_AsIs, FN),
-  R"cpp(
+llvm::StringRef Expected = R"cpp(
 FunctionDecl 'func1'
 `-CompoundStmt
   `-ReturnStmt
@@ -354,97 +352,106 @@ FunctionDecl 'func1'
   `-ImplicitCastExpr
 `-CXXConstructExpr
   `-IntegerLiteral
-)cpp");
+)cpp";
 
-EXPECT_EQ(
-dumpASTString(ast_type_traits::TK_IgnoreUnlessSpelledInSource, FN),
-R"cpp(
+EXPECT_EQ(dumpASTString(ast_type_traits::TK_AsIs, FN), Expected);
+
+Expected = R"cpp(
 FunctionDecl 'func1'
 `-CompoundStmt
   `-ReturnStmt
 `-IntegerLiteral
-)cpp");
+)cpp";
+EXPECT_EQ(
+dumpASTString(ast_type_traits::TK_IgnoreUnlessSpelledInSource, FN),
+Expected);
   }
 
-  EXPECT_EQ(dumpASTString(ast_type_traits::TK_IgnoreUnlessSpelledInSource,
-  getFunctionNode("func2")),
-R"cpp(
+  llvm::StringRef Expected = R"cpp(
 FunctionDecl 'func2'
 `-CompoundStmt
   `-ReturnStmt
 `-CXXTemporaryObjectExpr
   `-IntegerLiteral
-)cpp");
-
+)cpp";
   EXPECT_EQ(dumpASTString(ast_type_traits::TK_IgnoreUnlessSpelledInSource,
-  getFunctionNode("func3")),
-R"cpp(
+  getFunctionNode("func2")),
+Expected);
+
+  Expected = R"cpp(
 FunctionDecl 'func3'
 `-CompoundStmt
   `-ReturnStmt
 `-CXXFunctionalCastExpr
   `-IntegerLiteral
-)cpp");
-
+)cpp";
   EXPECT_EQ(dumpASTString(ast_type_traits::TK_IgnoreUnlessSpelledInSource,
-  getFunctionNode("func4")),
-R"cpp(
+  getFunctionNode("func3")),
+Expected);
+
+  Expected = R"cpp(
 FunctionDecl 'func4'
 `-CompoundStmt
   `-ReturnStmt
 `-CXXTemporaryObjectExpr
-)cpp");
-
+)cpp";
   EXPECT_EQ(dumpASTString(ast_type_traits::TK_IgnoreUnlessSpelledInSource,
-  getFunctionNode("func5")),
-R"cpp(
+  getFunctionNode("func4")),
+Expected);
+
+  Expected = R"cpp(
 FunctionDecl 'func5'
 `-CompoundStmt
   `-ReturnStmt
 `-CXXTemporaryObjectExpr
-)cpp");
-
+)cpp";
   EXPECT_EQ(dumpASTString(ast_type_traits::TK_IgnoreUnlessSpelledInSource,
-  getFunctionNode("func6")),
-R"cpp(
+  getFunctionNode("func5")),
+Expected);
+
+  Expected = R"cpp(
 FunctionDecl 'func6'
 `-CompoundStmt
   `-ReturnStmt
 `-CXXTemporaryObjectExpr
-)cpp");
-
+)cpp";
   EXPECT_EQ(dumpASTString(ast_type_traits::TK_IgnoreUnlessSpelledInSource,
-  getFunctionNode("func7")),
-R"cpp(
+  getFunctionNode("func6")),
+Expected);
+
+  Expected = R"cpp(
 FunctionDecl 'func7'
 `-CompoundStmt
   `-ReturnStmt
 `-CXXTemporaryObjectExpr
-)cpp");
-
+)cpp";
   EXPECT_EQ(dumpASTString(ast_type_traits::TK_IgnoreUnlessSpelledInSource,
-  getFunctionNode("func8")),
-R"cpp(
+  getFunctionNode("func7")),
+Expected);
+
+  Expected = R"cpp(
 FunctionDecl 'func8'
 `-CompoundStmt
   `-ReturnStmt
 `-CXXFunctionalCastExpr
   `-InitListExpr
-)cpp");
-
+)cpp";
   EXPECT_EQ(dumpASTString(ast_type_traits::TK_IgnoreUnlessSpelledInSource,
-  getFunctionNode("func9")),
-R"cpp(
+  getFunctionNode("func8")),
+Expected);
+
+  Expected = R"cpp(
 FunctionDecl 'func9'
 `-CompoundStmt
   `-ReturnStmt
 `-CXXFunctionalCastExpr
   `-InitListExpr
-)cpp");
-
+)cpp";
   EXPECT_EQ(dumpASTString(ast_type_traits::TK_IgnoreUnlessSpelledInSource,
-  getFunctionNode("func10")),
-R"cpp(
+  getFunctionNode("func9")),
+Expected);
+
+  Expected = R"cpp(
 FunctionDecl 'func10'
 `-CompoundStmt
   |-DeclStmt
@@ -452,11 +459,12 @@ FunctionDecl 'func10'
   |   `-CXXConstructExpr
   

[clang-tools-extra] b96ec49 - [clangd] Remove raw string literals in macros

[Oliver Stannard via cfe-commits]

Author: Oliver Stannard
Date: 2020-01-13T11:45:05Z
New Revision: b96ec492d34ecf31fd2c8d2f0033f00e36cc2b9c

URL: 
https://github.com/llvm/llvm-project/commit/b96ec492d34ecf31fd2c8d2f0033f00e36cc2b9c
DIFF: 
https://github.com/llvm/llvm-project/commit/b96ec492d34ecf31fd2c8d2f0033f00e36cc2b9c.diff

LOG: [clangd] Remove raw string literals in macros

Older (but still supported) versions of GCC don't handle C++11 raw
string literals in macro parameters correctly.

Added: 


Modified: 
clang-tools-extra/clangd/unittests/FormattedStringTests.cpp

Removed: 




diff  --git a/clang-tools-extra/clangd/unittests/FormattedStringTests.cpp 
b/clang-tools-extra/clangd/unittests/FormattedStringTests.cpp
index 825bf5bbd866..80d0934bed3e 100644
--- a/clang-tools-extra/clangd/unittests/FormattedStringTests.cpp
+++ b/clang-tools-extra/clangd/unittests/FormattedStringTests.cpp
@@ -194,10 +194,10 @@ TEST(BulletList, Render) {
   EXPECT_EQ(L.asPlainText(), "- foo");
 
   L.addItem().addParagraph().appendText("bar");
-  EXPECT_EQ(L.asMarkdown(), R"md(- foo
-- bar)md");
-  EXPECT_EQ(L.asPlainText(), R"pt(- foo
-- bar)pt");
+  llvm::StringRef Expected = R"md(- foo
+- bar)md";
+  EXPECT_EQ(L.asMarkdown(), Expected);
+  EXPECT_EQ(L.asPlainText(), Expected);
 
   // Nested list, with a single item.
   Document  = L.addItem();
@@ -215,24 +215,26 @@ TEST(BulletList, Render) {
   Document  = InnerList.addItem();
   DeepDoc.addParagraph().appendText("baz");
   DeepDoc.addParagraph().appendText("baz");
-  EXPECT_EQ(L.asMarkdown(), R"md(- foo
+  StringRef ExpectedMarkdown = R"md(- foo
 - bar
 - foo  
   baz  
   - foo  
 - baz  
-  baz)md");
-  EXPECT_EQ(L.asPlainText(), R"pt(- foo
+  baz)md";
+  EXPECT_EQ(L.asMarkdown(), ExpectedMarkdown);
+  StringRef ExpectedPlainText = R"pt(- foo
 - bar
 - foo
   baz
   - foo
 - baz
-  baz)pt");
+  baz)pt";
+  EXPECT_EQ(L.asPlainText(), ExpectedPlainText);
 
   // Termination
   Inner.addParagraph().appendText("after");
-  EXPECT_EQ(L.asMarkdown(), R"md(- foo
+  ExpectedMarkdown = R"md(- foo
 - bar
 - foo  
   baz  
@@ -240,15 +242,17 @@ TEST(BulletList, Render) {
 - baz  
   baz
 
-after)md");
-  EXPECT_EQ(L.asPlainText(), R"pt(- foo
+after)md";
+  EXPECT_EQ(L.asMarkdown(), ExpectedMarkdown);
+  ExpectedPlainText = R"pt(- foo
 - bar
 - foo
   baz
   - foo
 - baz
   baz
-after)pt");
+after)pt";
+  EXPECT_EQ(L.asPlainText(), ExpectedPlainText);
 }
 
 } // namespace



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r375094 - Reland: Dead Virtual Function Elimination

[Oliver Stannard via cfe-commits]

Author: ostannard
Date: Thu Oct 17 02:58:57 2019
New Revision: 375094

URL: http://llvm.org/viewvc/llvm-project?rev=375094=rev
Log:
Reland: Dead Virtual Function Elimination

Remove dead virtual functions from vtables with
replaceNonMetadataUsesWith, so that CGProfile metadata gets cleaned up
correctly.

Original commit message:

Currently, it is hard for the compiler to remove unused C++ virtual
functions, because they are all referenced from vtables, which are referenced
by constructors. This means that if the constructor is called from any live
code, then we keep every virtual function in the final link, even if there
are no call sites which can use it.

This patch allows unused virtual functions to be removed during LTO (and
regular compilation in limited circumstances) by using type metadata to match
virtual function call sites to the vtable slots they might load from. This
information can then be used in the global dead code elimination pass instead
of the references from vtables to virtual functions, to more accurately
determine which functions are reachable.

To make this transformation safe, I have changed clang's code-generation to
always load virtual function pointers using the llvm.type.checked.load
intrinsic, instead of regular load instructions. I originally tried writing
this using clang's existing code-generation, which uses the llvm.type.test
and llvm.assume intrinsics after doing a normal load. However, it is possible
for optimisations to obscure the relationship between the GEP, load and
llvm.type.test, causing GlobalDCE to fail to find virtual function call
sites.

The existing linkage and visibility types don't accurately describe the scope
in which a virtual call could be made which uses a given vtable. This is
wider than the visibility of the type itself, because a virtual function call
could be made using a more-visible base class. I've added a new
!vcall_visibility metadata type to represent this, described in
TypeMetadata.rst. The internalization pass and libLTO have been updated to
change this metadata when linking is performed.

This doesn't currently work with ThinLTO, because it needs to see every call
to llvm.type.checked.load in the linkage unit. It might be possible to
extend this optimisation to be able to use the ThinLTO summary, as was done
for devirtualization, but until then that combination is rejected in the
clang driver.

To test this, I've written a fuzzer which generates random C++ programs with
complex class inheritance graphs, and virtual functions called through object
and function pointers of different types. The programs are spread across
multiple translation units and DSOs to test the different visibility
restrictions.

I've also tried doing bootstrap builds of LLVM to test this. This isn't
ideal, because only classes in anonymous namespaces can be optimised with
-fvisibility=default, and some parts of LLVM (plugins and bugpoint) do not
work correctly with -fvisibility=hidden. However, there are only 12 test
failures when building with -fvisibility=hidden (and an unmodified compiler),
and this change does not cause any new failures for either value of
-fvisibility.

On the 7 C++ sub-benchmarks of SPEC2006, this gives a geomean code-size
reduction of ~6%, over a baseline compiled with "-O2 -flto
-fvisibility=hidden -fwhole-program-vtables". The best cases are reductions
of ~14% in 450.soplex and 483.xalancbmk, and there are no code size
increases.

I've also run this on a set of 8 mbed-os examples compiled for Armv7M, which
show a geomean size reduction of ~3%, again with no size increases.

I had hoped that this would have no effect on performance, which would allow
it to awlays be enabled (when using -fwhole-program-vtables). However, the
changes in clang to use the llvm.type.checked.load intrinsic are causing ~1%
performance regression in the C++ parts of SPEC2006. It should be possible to
recover some of this perf loss by teaching optimisations about the
llvm.type.checked.load intrinsic, which would make it worth turning this on
by default (though it's still dependent on -fwhole-program-vtables).

Differential revision: https://reviews.llvm.org/D63932

Added:
cfe/trunk/test/CodeGenCXX/vcall-visibility-metadata.cpp
cfe/trunk/test/CodeGenCXX/virtual-function-elimination.cpp
cfe/trunk/test/Driver/virtual-function-elimination.cpp
Modified:
cfe/trunk/include/clang/Basic/CodeGenOptions.def
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/CodeGen/CGClass.cpp
cfe/trunk/lib/CodeGen/CGVTables.cpp
cfe/trunk/lib/CodeGen/CodeGenModule.h
cfe/trunk/lib/CodeGen/ItaniumCXXABI.cpp
cfe/trunk/lib/Driver/ToolChains/Clang.cpp
cfe/trunk/lib/Frontend/CompilerInvocation.cpp

Modified: cfe/trunk/include/clang/Basic/CodeGenOptions.def
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/CodeGenOptions.def?rev=375094=375093=375094=diff
==

r374539 - Dead Virtual Function Elimination

[Oliver Stannard via cfe-commits]

Author: ostannard
Date: Fri Oct 11 04:59:55 2019
New Revision: 374539

URL: http://llvm.org/viewvc/llvm-project?rev=374539=rev
Log:
Dead Virtual Function Elimination

Currently, it is hard for the compiler to remove unused C++ virtual
functions, because they are all referenced from vtables, which are referenced
by constructors. This means that if the constructor is called from any live
code, then we keep every virtual function in the final link, even if there
are no call sites which can use it.

This patch allows unused virtual functions to be removed during LTO (and
regular compilation in limited circumstances) by using type metadata to match
virtual function call sites to the vtable slots they might load from. This
information can then be used in the global dead code elimination pass instead
of the references from vtables to virtual functions, to more accurately
determine which functions are reachable.

To make this transformation safe, I have changed clang's code-generation to
always load virtual function pointers using the llvm.type.checked.load
intrinsic, instead of regular load instructions. I originally tried writing
this using clang's existing code-generation, which uses the llvm.type.test
and llvm.assume intrinsics after doing a normal load. However, it is possible
for optimisations to obscure the relationship between the GEP, load and
llvm.type.test, causing GlobalDCE to fail to find virtual function call
sites.

The existing linkage and visibility types don't accurately describe the scope
in which a virtual call could be made which uses a given vtable. This is
wider than the visibility of the type itself, because a virtual function call
could be made using a more-visible base class. I've added a new
!vcall_visibility metadata type to represent this, described in
TypeMetadata.rst. The internalization pass and libLTO have been updated to
change this metadata when linking is performed.

This doesn't currently work with ThinLTO, because it needs to see every call
to llvm.type.checked.load in the linkage unit. It might be possible to
extend this optimisation to be able to use the ThinLTO summary, as was done
for devirtualization, but until then that combination is rejected in the
clang driver.

To test this, I've written a fuzzer which generates random C++ programs with
complex class inheritance graphs, and virtual functions called through object
and function pointers of different types. The programs are spread across
multiple translation units and DSOs to test the different visibility
restrictions.

I've also tried doing bootstrap builds of LLVM to test this. This isn't
ideal, because only classes in anonymous namespaces can be optimised with
-fvisibility=default, and some parts of LLVM (plugins and bugpoint) do not
work correctly with -fvisibility=hidden. However, there are only 12 test
failures when building with -fvisibility=hidden (and an unmodified compiler),
and this change does not cause any new failures for either value of
-fvisibility.

On the 7 C++ sub-benchmarks of SPEC2006, this gives a geomean code-size
reduction of ~6%, over a baseline compiled with "-O2 -flto
-fvisibility=hidden -fwhole-program-vtables". The best cases are reductions
of ~14% in 450.soplex and 483.xalancbmk, and there are no code size
increases.

I've also run this on a set of 8 mbed-os examples compiled for Armv7M, which
show a geomean size reduction of ~3%, again with no size increases.

I had hoped that this would have no effect on performance, which would allow
it to awlays be enabled (when using -fwhole-program-vtables). However, the
changes in clang to use the llvm.type.checked.load intrinsic are causing ~1%
performance regression in the C++ parts of SPEC2006. It should be possible to
recover some of this perf loss by teaching optimisations about the
llvm.type.checked.load intrinsic, which would make it worth turning this on
by default (though it's still dependent on -fwhole-program-vtables).

Differential revision: https://reviews.llvm.org/D63932

Added:
cfe/trunk/test/CodeGenCXX/vcall-visibility-metadata.cpp
cfe/trunk/test/CodeGenCXX/virtual-function-elimination.cpp
cfe/trunk/test/Driver/virtual-function-elimination.cpp
Modified:
cfe/trunk/include/clang/Basic/CodeGenOptions.def
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/CodeGen/CGClass.cpp
cfe/trunk/lib/CodeGen/CGVTables.cpp
cfe/trunk/lib/CodeGen/CodeGenModule.h
cfe/trunk/lib/CodeGen/ItaniumCXXABI.cpp
cfe/trunk/lib/Driver/ToolChains/Clang.cpp
cfe/trunk/lib/Frontend/CompilerInvocation.cpp

Modified: cfe/trunk/include/clang/Basic/CodeGenOptions.def
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/CodeGenOptions.def?rev=374539=374538=374539=diff
==
--- cfe/trunk/include/clang/Basic/CodeGenOptions.def (original)
+++ cfe/trunk/include/clang/Basic/CodeGenOptions.def Fri Oct 11 04:59:55 2019
@@ -278,6 +278,10 @@ 

r357250 - [AArch64] Support selecting TPIDR_EL[1-3] as the thread base

[Oliver Stannard via cfe-commits]

Author: olista01
Date: Fri Mar 29 06:32:41 2019
New Revision: 357250

URL: http://llvm.org/viewvc/llvm-project?rev=357250=rev
Log:
[AArch64] Support selecting TPIDR_EL[1-3] as the thread base

Add an -mtp=el[0-3] option to select which of the AArch64 thread ID registers
will be used for the TLS base pointer.

This is a followup to rL356657 which added subtarget features to enable
accesses to the privileged thread ID registers.

Patch by Philip Derrin!

Differential revision: https://reviews.llvm.org/D59631


Modified:
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/Driver/ToolChains/Arch/AArch64.cpp
cfe/trunk/test/Driver/clang-translation.c

Modified: cfe/trunk/include/clang/Driver/Options.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=357250=357249=357250=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Fri Mar 29 06:32:41 2019
@@ -2016,8 +2016,8 @@ def mexecute_only : Flag<["-"], "mexecut
   HelpText<"Disallow generation of data access to code sections (ARM only)">;
 def mno_execute_only : Flag<["-"], "mno-execute-only">, 
Group,
   HelpText<"Allow generation of data access to code sections (ARM only)">;
-def mtp_mode_EQ : Joined<["-"], "mtp=">, Group, 
Values<"soft, cp15">,
-  HelpText<"Read thread pointer from coprocessor register (ARM only)">;
+def mtp_mode_EQ : Joined<["-"], "mtp=">, Group, 
Values<"soft,cp15,el0,el1,el2,el3">,
+  HelpText<"Thread pointer access method (AArch32/AArch64 only)">;
 def mpure_code : Flag<["-"], "mpure-code">, Alias; // Alias for 
GCC compatibility
 def mno_pure_code : Flag<["-"], "mno-pure-code">, Alias;
 def mtvos_version_min_EQ : Joined<["-"], "mtvos-version-min=">, Group;

Modified: cfe/trunk/lib/Driver/ToolChains/Arch/AArch64.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Arch/AArch64.cpp?rev=357250=357249=357250=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Arch/AArch64.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Arch/AArch64.cpp Fri Mar 29 06:32:41 2019
@@ -194,6 +194,18 @@ void aarch64::getAArch64TargetFeatures(c
 Features.push_back("-neon");
   }
 
+  if (Arg *A = Args.getLastArg(options::OPT_mtp_mode_EQ)) {
+StringRef Mtp = A->getValue();
+if (Mtp == "el3")
+  Features.push_back("+tpidr-el3");
+else if (Mtp == "el2")
+  Features.push_back("+tpidr-el2");
+else if (Mtp == "el1")
+  Features.push_back("+tpidr-el1");
+else if (Mtp != "el0")
+  D.Diag(diag::err_drv_invalid_mtp) << A->getAsString(Args);
+  }
+
   // En/disable crc
   if (Arg *A = Args.getLastArg(options::OPT_mcrc, options::OPT_mnocrc)) {
 if (A->getOption().matches(options::OPT_mcrc))

Modified: cfe/trunk/test/Driver/clang-translation.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/clang-translation.c?rev=357250=357249=357250=diff
==
--- cfe/trunk/test/Driver/clang-translation.c (original)
+++ cfe/trunk/test/Driver/clang-translation.c Fri Mar 29 06:32:41 2019
@@ -120,6 +120,36 @@
 // RUN: FileCheck -check-prefix=ARMv7_THREAD_POINTER_NON %s
 // ARMv7_THREAD_POINTER_NON-NOT: "-target-feature" "+read-tp-hard"
 
+// RUN: %clang -target aarch64-linux -### -S %s -arch armv8a 2>&1 | \
+// RUN: FileCheck -check-prefix=ARMv8_THREAD_POINTER_NON %s
+// ARMv8_THREAD_POINTER_NON-NOT: "-target-feature" "+tpidr-el1"
+// ARMv8_THREAD_POINTER_NON-NOT: "-target-feature" "+tpidr-el2"
+// ARMv8_THREAD_POINTER_NON-NOT: "-target-feature" "+tpidr-el3"
+
+// RUN: %clang -target aarch64-linux -### -S %s -arch armv8a -mtp=el0 2>&1 | \
+// RUN: FileCheck -check-prefix=ARMv8_THREAD_POINTER_EL0 %s
+// ARMv8_THREAD_POINTER_EL0-NOT: "-target-feature" "+tpidr-el1"
+// ARMv8_THREAD_POINTER_EL0-NOT: "-target-feature" "+tpidr-el2"
+// ARMv8_THREAD_POINTER_EL0-NOT: "-target-feature" "+tpidr-el3"
+
+// RUN: %clang -target aarch64-linux -### -S %s -arch armv8a -mtp=el1 2>&1 | \
+// RUN: FileCheck -check-prefix=ARMv8_THREAD_POINTER_EL1 %s
+// ARMv8_THREAD_POINTER_EL1: "-target-feature" "+tpidr-el1"
+// ARMv8_THREAD_POINTER_EL1-NOT: "-target-feature" "+tpidr-el2"
+// ARMv8_THREAD_POINTER_EL1-NOT: "-target-feature" "+tpidr-el3"
+
+// RUN: %clang -target aarch64-linux -### -S %s -arch armv8a -mtp=el2 2>&1 | \
+// RUN: FileCheck -check-prefix=ARMv8_THREAD_POINTER_EL2 %s
+// ARMv8_THREAD_POINTER_EL2-NOT: "-target-feature" "+tpidr-el1"
+// ARMv8_THREAD_POINTER_EL2: "-target-feature" "+tpidr-el2"
+// ARMv8_THREAD_POINTER_EL2-NOT: "-target-feature" "+tpidr-el3"
+
+// RUN: %clang -target aarch64-linux -### -S %s -arch armv8a -mtp=el3 2>&1 | \
+// RUN: FileCheck -check-prefix=ARMv8_THREAD_POINTER_EL3 %s
+// ARMv8_THREAD_POINTER_EL3-NOT: "-target-feature" "+tpidr-el1"
+// ARMv8_THREAD_POINTER_EL3-NOT: 

r354265 - [ARM] Add pre-defined macros for ROPI and RWPI

[Oliver Stannard via cfe-commits]

Author: olista01
Date: Mon Feb 18 04:39:47 2019
New Revision: 354265

URL: http://llvm.org/viewvc/llvm-project?rev=354265=rev
Log:
[ARM] Add pre-defined macros for ROPI and RWPI

This adds ACLE-defined macros to test for code being compiled in the ROPI and
RWPI position-independence modes.

Differential revision: https://reviews.llvm.org/D23610


Added:
cfe/trunk/test/Preprocessor/arm-pic-predefines.c
Modified:
cfe/trunk/include/clang/Basic/LangOptions.def
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/Basic/Targets/ARM.cpp
cfe/trunk/lib/Driver/ToolChains/Clang.cpp
cfe/trunk/lib/Frontend/CompilerInvocation.cpp

Modified: cfe/trunk/include/clang/Basic/LangOptions.def
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/LangOptions.def?rev=354265=354264=354265=diff
==
--- cfe/trunk/include/clang/Basic/LangOptions.def (original)
+++ cfe/trunk/include/clang/Basic/LangOptions.def Mon Feb 18 04:39:47 2019
@@ -170,6 +170,8 @@ VALUE_LANGOPT(MaxTypeAlign  , 32, 0,
 VALUE_LANGOPT(AlignDouble, 1, 0, "Controls if doubles should be 
aligned to 8 bytes (x86 only)")
 COMPATIBLE_VALUE_LANGOPT(PICLevel, 2, 0, "__PIC__ level")
 COMPATIBLE_VALUE_LANGOPT(PIE , 1, 0, "is pie")
+LANGOPT(ROPI , 1, 0, "Read-only position independence")
+LANGOPT(RWPI , 1, 0, "Read-write position 
independence")
 COMPATIBLE_LANGOPT(GNUInline , 1, 0, "GNU inline semantics")
 COMPATIBLE_LANGOPT(NoInlineDefine, 1, 0, "__NO_INLINE__ predefined macro")
 COMPATIBLE_LANGOPT(Deprecated, 1, 0, "__DEPRECATED predefined macro")

Modified: cfe/trunk/include/clang/Driver/Options.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=354265=354264=354265=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Mon Feb 18 04:39:47 2019
@@ -1606,9 +1606,9 @@ def fplt : Flag<["-"], "fplt">, Group;
 def fno_plt : Flag<["-"], "fno-plt">, Group, Flags<[CC1Option]>,
   HelpText<"Do not use the PLT to make function calls">;
-def fropi : Flag<["-"], "fropi">, Group;
+def fropi : Flag<["-"], "fropi">, Group, Flags<[CC1Option]>;
 def fno_ropi : Flag<["-"], "fno-ropi">, Group;
-def frwpi : Flag<["-"], "frwpi">, Group;
+def frwpi : Flag<["-"], "frwpi">, Group, Flags<[CC1Option]>;
 def fno_rwpi : Flag<["-"], "fno-rwpi">, Group;
 def fplugin_EQ : Joined<["-"], "fplugin=">, Group, 
Flags<[DriverOption]>, MetaVarName<"">,
   HelpText<"Load the named plugin (dynamic shared object)">;

Modified: cfe/trunk/lib/Basic/Targets/ARM.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/ARM.cpp?rev=354265=354264=354265=diff
==
--- cfe/trunk/lib/Basic/Targets/ARM.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/ARM.cpp Mon Feb 18 04:39:47 2019
@@ -652,6 +652,12 @@ void ARMTargetInfo::getTargetDefines(con
   if (SoftFloat)
 Builder.defineMacro("__SOFTFP__");
 
+  // ACLE position independent code macros.
+  if (Opts.ROPI)
+Builder.defineMacro("__ARM_ROPI", "1");
+  if (Opts.RWPI)
+Builder.defineMacro("__ARM_RWPI", "1");
+
   if (ArchKind == llvm::ARM::ArchKind::XSCALE)
 Builder.defineMacro("__XSCALE__");
 

Modified: cfe/trunk/lib/Driver/ToolChains/Clang.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Clang.cpp?rev=354265=354264=354265=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Clang.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Clang.cpp Mon Feb 18 04:39:47 2019
@@ -3810,6 +3810,13 @@ void Clang::ConstructJob(Compilation ,
   CmdArgs.push_back("-pic-is-pie");
   }
 
+  if (RelocationModel == llvm::Reloc::ROPI ||
+  RelocationModel == llvm::Reloc::ROPI_RWPI)
+CmdArgs.push_back("-fropi");
+  if (RelocationModel == llvm::Reloc::RWPI ||
+  RelocationModel == llvm::Reloc::ROPI_RWPI)
+CmdArgs.push_back("-frwpi");
+
   if (Arg *A = Args.getLastArg(options::OPT_meabi)) {
 CmdArgs.push_back("-meabi");
 CmdArgs.push_back(A->getValue());

Modified: cfe/trunk/lib/Frontend/CompilerInvocation.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Frontend/CompilerInvocation.cpp?rev=354265=354264=354265=diff
==
--- cfe/trunk/lib/Frontend/CompilerInvocation.cpp (original)
+++ cfe/trunk/lib/Frontend/CompilerInvocation.cpp Mon Feb 18 04:39:47 2019
@@ -2662,6 +2662,8 @@ static void ParseLangArgs(LangOptions 
   Opts.MaxTypeAlign = getLastArgIntValue(Args, OPT_fmax_type_align_EQ, 0, 
Diags);
   Opts.AlignDouble = Args.hasArg(OPT_malign_double);
   Opts.PICLevel = getLastArgIntValue(Args, OPT_pic_level, 

r343566 - [AArch64][v8.5A] Test clang option for the Memory Tagging Extension

[Oliver Stannard via cfe-commits]

Author: olista01
Date: Tue Oct  2 02:38:59 2018
New Revision: 343566

URL: http://llvm.org/viewvc/llvm-project?rev=343566=rev
Log:
[AArch64][v8.5A] Test clang option for the Memory Tagging Extension

The implementation of this is in TargetParser, so we only need to add a
test for it in clang.

Patch by Pablo Barrio!

Differential revision: https://reviews.llvm.org/D52493


Added:
cfe/trunk/test/Driver/aarch64-mte.c

Added: cfe/trunk/test/Driver/aarch64-mte.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/aarch64-mte.c?rev=343566=auto
==
--- cfe/trunk/test/Driver/aarch64-mte.c (added)
+++ cfe/trunk/test/Driver/aarch64-mte.c Tue Oct  2 02:38:59 2018
@@ -0,0 +1,13 @@
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a+memtag %s 
2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a+memtag %s 
2>&1 | FileCheck %s
+// CHECK: "-target-feature" "+mte"
+
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a+nomemtag %s 
2>&1 | FileCheck %s --check-prefix=NOMTE
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a+nomemtag %s 
2>&1 | FileCheck %s --check-prefix=NOMTE
+// NOMTE: "-target-feature" "-mte"
+
+// RUN: %clang -### -target aarch64-none-none-eabi %s 2>&1 | 
FileCheck %s --check-prefix=ABSENTMTE
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a %s 2>&1 | 
FileCheck %s --check-prefix=ABSENTMTE
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a %s 2>&1 | 
FileCheck %s --check-prefix=ABSENTMTE
+// ABSENTMTE-NOT: "-target-feature" "+mte"
+// ABSENTMTE-NOT: "-target-feature" "-mte"


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r343220 - [AArch64][v8.5A] Test optional Armv8.5-A random number extension

[Oliver Stannard via cfe-commits]

Author: olista01
Date: Thu Sep 27 07:20:59 2018
New Revision: 343220

URL: http://llvm.org/viewvc/llvm-project?rev=343220=rev
Log:
[AArch64][v8.5A] Test optional Armv8.5-A random number extension

The implementation of this is in TargetParser, so we only need to add a
test for it in clang.

Patch by Pablo Barrio!

Differential revision: https://reviews.llvm.org/D52492


Added:
cfe/trunk/test/Driver/aarch64-rand.c

Added: cfe/trunk/test/Driver/aarch64-rand.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/aarch64-rand.c?rev=343220=auto
==
--- cfe/trunk/test/Driver/aarch64-rand.c (added)
+++ cfe/trunk/test/Driver/aarch64-rand.c Thu Sep 27 07:20:59 2018
@@ -0,0 +1,13 @@
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a+rng %s 2>&1 
| FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a+rng %s 2>&1 
| FileCheck %s
+// CHECK: "-target-feature" "+rand"
+
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a+norng %s 
2>&1 | FileCheck %s --check-prefix=NORAND
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a+norng %s 
2>&1 | FileCheck %s --check-prefix=NORAND
+// NORAND: "-target-feature" "-rand"
+
+// RUN: %clang -### -target aarch64-none-none-eabi %s 2>&1 | 
FileCheck %s --check-prefix=ABSENTRAND
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.4a %s 2>&1 | 
FileCheck %s --check-prefix=ABSENTRAND
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a %s 2>&1 | 
FileCheck %s --check-prefix=ABSENTRAND
+// ABSENTRAND-NOT: "-target-feature" "+rand"
+// ABSENTRAND-NOT: "-target-feature" "-rand"


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r343111 - [ARM/AArch64][v8.5A] Add Armv8.5-A target

[Oliver Stannard via cfe-commits]

Author: olista01
Date: Wed Sep 26 07:20:29 2018
New Revision: 343111

URL: http://llvm.org/viewvc/llvm-project?rev=343111=rev
Log:
[ARM/AArch64][v8.5A] Add Armv8.5-A target

This patch allows targetting Armv8.5-A from Clang. Most of the
implementation is in TargetParser, so this is mostly just adding tests.

Patch by Pablo Barrio!

Differential revision: https://reviews.llvm.org/D52491


Modified:
cfe/trunk/lib/Basic/Targets/ARM.cpp
cfe/trunk/test/Driver/aarch64-cpus.c
cfe/trunk/test/Driver/arm-cortex-cpus.c
cfe/trunk/test/Preprocessor/arm-target-features.c

Modified: cfe/trunk/lib/Basic/Targets/ARM.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/ARM.cpp?rev=343111=343110=343111=diff
==
--- cfe/trunk/lib/Basic/Targets/ARM.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/ARM.cpp Wed Sep 26 07:20:29 2018
@@ -189,6 +189,8 @@ StringRef ARMTargetInfo::getCPUAttr() co
 return "8_3A";
   case llvm::ARM::ArchKind::ARMV8_4A:
 return "8_4A";
+  case llvm::ARM::ArchKind::ARMV8_5A:
+return "8_5A";
   case llvm::ARM::ArchKind::ARMV8MBaseline:
 return "8M_BASE";
   case llvm::ARM::ArchKind::ARMV8MMainline:

Modified: cfe/trunk/test/Driver/aarch64-cpus.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/aarch64-cpus.c?rev=343111=343110=343111=diff
==
--- cfe/trunk/test/Driver/aarch64-cpus.c (original)
+++ cfe/trunk/test/Driver/aarch64-cpus.c Wed Sep 26 07:20:29 2018
@@ -542,6 +542,25 @@
 // RUN: %clang -target aarch64 -march=armv8.4-a+nofp16+fp16fml -### -c %s 2>&1 
| FileCheck -check-prefix=GENERICV84A-NO-FP16-FP16FML %s
 // GENERICV84A-NO-FP16-FP16FML: "-target-feature" "+fp16fml" "-target-feature" 
"+fullfp16"
 
+// RUN: %clang -target aarch64 -march=armv8.5a -### -c %s 2>&1 | FileCheck 
-check-prefix=GENERICV85A %s
+// RUN: %clang -target aarch64 -march=armv8.5-a -### -c %s 2>&1 | FileCheck 
-check-prefix=GENERICV85A %s
+// RUN: %clang -target aarch64 -mlittle-endian -march=armv8.5a -### -c %s 2>&1 
| FileCheck -check-prefix=GENERICV85A %s
+// RUN: %clang -target aarch64 -mlittle-endian -march=armv8.5-a -### -c %s 
2>&1 | FileCheck -check-prefix=GENERICV85A %s
+// RUN: %clang -target aarch64_be -mlittle-endian -march=armv8.5a -### -c %s 
2>&1 | FileCheck -check-prefix=GENERICV85A %s
+// RUN: %clang -target aarch64_be -mlittle-endian -march=armv8.5-a -### -c %s 
2>&1 | FileCheck -check-prefix=GENERICV85A %s
+// GENERICV85A: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" 
"-target-feature" "+neon" "-target-feature" "+v8.5a"
+
+// RUN: %clang -target aarch64_be -march=armv8.5a -### -c %s 2>&1 | FileCheck 
-check-prefix=GENERICV85A-BE %s
+// RUN: %clang -target aarch64_be -march=armv8.5-a -### -c %s 2>&1 | FileCheck 
-check-prefix=GENERICV85A-BE %s
+// RUN: %clang -target aarch64 -mbig-endian -march=armv8.5a -### -c %s 2>&1 | 
FileCheck -check-prefix=GENERICV85A-BE %s
+// RUN: %clang -target aarch64 -mbig-endian -march=armv8.5-a -### -c %s 2>&1 | 
FileCheck -check-prefix=GENERICV85A-BE %s
+// RUN: %clang -target aarch64_be -mbig-endian -march=armv8.5a -### -c %s 2>&1 
| FileCheck -check-prefix=GENERICV85A-BE %s
+// RUN: %clang -target aarch64_be -mbig-endian -march=armv8.5-a -### -c %s 
2>&1 | FileCheck -check-prefix=GENERICV85A-BE %s
+// GENERICV85A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" 
"generic" "-target-feature" "+neon" "-target-feature" "+v8.5a"
+
+// RUN: %clang -target aarch64 -march=armv8.5-a+fp16 -### -c %s 2>&1 | 
FileCheck -check-prefix=GENERICV85A-FP16 %s
+// GENERICV85A-FP16: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"generic" "-target-feature" "+neon" "-target-feature" "+v8.5a" 
"-target-feature" "+fullfp16"
+
 // fullfp16 is off by default for v8a, feature must not be mentioned
 // RUN: %clang -target aarch64 -march=armv8a  -### -c %s 2>&1 | FileCheck 
-check-prefix=V82ANOFP16 -check-prefix=GENERIC %s
 // RUN: %clang -target aarch64 -march=armv8-a -### -c %s 2>&1 | FileCheck 
-check-prefix=V82ANOFP16 -check-prefix=GENERIC %s

Modified: cfe/trunk/test/Driver/arm-cortex-cpus.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/arm-cortex-cpus.c?rev=343111=343110=343111=diff
==
--- cfe/trunk/test/Driver/arm-cortex-cpus.c (original)
+++ cfe/trunk/test/Driver/arm-cortex-cpus.c Wed Sep 26 07:20:29 2018
@@ -318,6 +318,23 @@
 // RUN: %clang -target arm -march=armebv8.4-a -mbig-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-BE-V84A %s
 // CHECK-BE-V84A: "-cc1"{{.*}} "-triple" "armebv8.4{{.*}}" "-target-cpu" 
"generic"
 
+// RUN: %clang -target armv8.5a -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-V85A %s
+// RUN: %clang -target arm -march=armv8.5a -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-V85A %s
+// RUN: %clang -target arm -march=armv8.5-a 

r342126 - [AArch64] Enable return address signing for static ctors

[Oliver Stannard via cfe-commits]

Author: olista01
Date: Thu Sep 13 03:25:36 2018
New Revision: 342126

URL: http://llvm.org/viewvc/llvm-project?rev=342126=rev
Log:
[AArch64] Enable return address signing for static ctors

Functions generated by clang and included in the .init_array section (such as
static constructors) do not follow the usual code path for adding
target-specific function attributes, so we have to add the return address
signing attribute here too, as is currently done for the sanitisers.

Differential revision: https://reviews.llvm.org/D51418


Added:
cfe/trunk/test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
Modified:
cfe/trunk/lib/CodeGen/CGDeclCXX.cpp

Modified: cfe/trunk/lib/CodeGen/CGDeclCXX.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGDeclCXX.cpp?rev=342126=342125=342126=diff
==
--- cfe/trunk/lib/CodeGen/CGDeclCXX.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGDeclCXX.cpp Thu Sep 13 03:25:36 2018
@@ -359,6 +359,12 @@ llvm::Function *CodeGenModule::CreateGlo
   !isInSanitizerBlacklist(SanitizerKind::ShadowCallStack, Fn, Loc))
 Fn->addFnAttr(llvm::Attribute::ShadowCallStack);
 
+  auto RASignKind = getCodeGenOpts().getSignReturnAddress();
+  if (RASignKind != CodeGenOptions::SignReturnAddressScope::None)
+Fn->addFnAttr("sign-return-address",
+  RASignKind == CodeGenOptions::SignReturnAddressScope::All
+  ? "all"
+  : "non-leaf");
   return Fn;
 }
 

Added: cfe/trunk/test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp?rev=342126=auto
==
--- cfe/trunk/test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp 
(added)
+++ cfe/trunk/test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp Thu 
Sep 13 03:25:36 2018
@@ -0,0 +1,21 @@
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - 
-msign-return-address=none  %s | \
+// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NONE
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - 
-msign-return-address=non-leaf %s | \
+// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-PARTIAL
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - 
-msign-return-address=all %s | \
+// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ALL
+
+struct Foo {
+  Foo() {}
+  ~Foo() {}
+};
+
+Foo f;
+
+// CHECK: @llvm.global_ctors {{.*}}i32 65535, void ()* @[[CTOR_FN:.*]], i8* 
null
+
+// CHECK: @[[CTOR_FN]]() #[[ATTR:[0-9]*]]
+
+// CHECK-NONE-NOT: attributes #[[ATTR]] = { {{.*}} 
"sign-return-address"={{.*}} }}
+// CHECK-PARTIAL: attributes #[[ATTR]] = { {{.*}} 
"sign-return-address"="non-leaf" {{.*}}}
+// CHECK-ALL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="all" 
{{.*}} }


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r331039 - [ARM,AArch64] Add intrinsics for dot product instructions

[Oliver Stannard via cfe-commits]

Author: olista01
Date: Fri Apr 27 07:03:32 2018
New Revision: 331039

URL: http://llvm.org/viewvc/llvm-project?rev=331039=rev
Log:
[ARM,AArch64] Add intrinsics for dot product instructions

The ACLE spec which describes these intrinsics hasn't been published yet, but
this is based on the final draft which will be published soon, and these have
already been implemented by GCC.

Differential revision: https://reviews.llvm.org/D46109


Added:
cfe/trunk/test/CodeGen/aarch64-neon-dot-product.c
cfe/trunk/test/CodeGen/arm-neon-dot-product.c
Modified:
cfe/trunk/include/clang/Basic/arm_neon.td
cfe/trunk/include/clang/Basic/arm_neon_incl.td
cfe/trunk/lib/CodeGen/CGBuiltin.cpp
cfe/trunk/utils/TableGen/NeonEmitter.cpp

Modified: cfe/trunk/include/clang/Basic/arm_neon.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/arm_neon.td?rev=331039=331038=331039=diff
==
--- cfe/trunk/include/clang/Basic/arm_neon.td (original)
+++ cfe/trunk/include/clang/Basic/arm_neon.td Fri Apr 27 07:03:32 2018
@@ -199,6 +199,13 @@ def OP_SCALAR_HALF_SET_LNQ : Op<(bitcast
   (bitcast "int16_t", $p0),
   (bitcast "int16x8_t", $p1), $p2))>;
 
+def OP_DOT_LN
+: Op<(call "vdot", $p0, $p1,
+  (bitcast $p1, (splat(bitcast "uint32x2_t", $p2), $p3)))>;
+def OP_DOT_LNQ
+: Op<(call "vdot", $p0, $p1,
+  (bitcast $p1, (splat(bitcast "uint32x4_t", $p2), $p3)))>;
+
 
//===--===//
 // Instructions
 
//===--===//
@@ -1579,3 +1586,13 @@ let ArchGuard = "defined(__ARM_FEATURE_F
   def SCALAR_VDUP_LANEH  : IInst<"vdup_lane", "sdi", "Sh">;
   def SCALAR_VDUP_LANEQH : IInst<"vdup_laneq", "sji", "Sh">;
 }
+
+// v8.2-A dot product instructions.
+let ArchGuard = "defined(__ARM_FEATURE_DOTPROD)" in {
+  def DOT : SInst<"vdot", "dd88", "iQiUiQUi">;
+  def DOT_LANE : SOpInst<"vdot_lane", "dd87i", "iUiQiQUi", OP_DOT_LN>;
+}
+let ArchGuard = "defined(__ARM_FEATURE_DOTPROD) && defined(__aarch64__)" in {
+  // Variants indexing into a 128-bit vector are A64 only.
+  def UDOT_LANEQ : SOpInst<"vdot_laneq", "dd89i", "iUiQiQUi", OP_DOT_LNQ>;
+}

Modified: cfe/trunk/include/clang/Basic/arm_neon_incl.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/arm_neon_incl.td?rev=331039=331038=331039=diff
==
--- cfe/trunk/include/clang/Basic/arm_neon_incl.td (original)
+++ cfe/trunk/include/clang/Basic/arm_neon_incl.td Fri Apr 27 07:03:32 2018
@@ -253,6 +253,9 @@ def OP_UNAVAILABLE : Operation {
 // B,C,D: array of default elts, force 'Q' size modifier.
 // p: pointer type
 // c: const pointer type
+// 7: vector of 8-bit elements, ignore 'Q' size modifier
+// 8: vector of 8-bit elements, same width as default type
+// 9: vector of 8-bit elements, force 'Q' size modifier
 
 // Every intrinsic subclasses Inst.
 class Inst  {

Modified: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGBuiltin.cpp?rev=331039=331038=331039=diff
==
--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp Fri Apr 27 07:03:32 2018
@@ -3867,6 +3867,8 @@ static const NeonIntrinsicInfo ARMSIMDIn
   NEONMAP0(vcvtq_u16_v),
   NEONMAP0(vcvtq_u32_v),
   NEONMAP0(vcvtq_u64_v),
+  NEONMAP2(vdot_v, arm_neon_udot, arm_neon_sdot, 0),
+  NEONMAP2(vdotq_v, arm_neon_udot, arm_neon_sdot, 0),
   NEONMAP0(vext_v),
   NEONMAP0(vextq_v),
   NEONMAP0(vfma_v),
@@ -4061,6 +4063,8 @@ static const NeonIntrinsicInfo AArch64SI
   NEONMAP1(vcvtq_n_u32_v, aarch64_neon_vcvtfp2fxu, 0),
   NEONMAP1(vcvtq_n_u64_v, aarch64_neon_vcvtfp2fxu, 0),
   NEONMAP1(vcvtx_f32_v, aarch64_neon_fcvtxn, AddRetType | Add1ArgType),
+  NEONMAP2(vdot_v, aarch64_neon_udot, aarch64_neon_sdot, 0),
+  NEONMAP2(vdotq_v, aarch64_neon_udot, aarch64_neon_sdot, 0),
   NEONMAP0(vext_v),
   NEONMAP0(vextq_v),
   NEONMAP0(vfma_v),
@@ -4974,6 +4978,14 @@ Value *CodeGenFunction::EmitCommonNeonBu
 }
 return SV;
   }
+  case NEON::BI__builtin_neon_vdot_v:
+  case NEON::BI__builtin_neon_vdotq_v: {
+llvm::Type *InputTy =
+llvm::VectorType::get(Int8Ty, Ty->getPrimitiveSizeInBits() / 8);
+llvm::Type *Tys[2] = { Ty, InputTy };
+Int = Usgn ? LLVMIntrinsic : AltLLVMIntrinsic;
+return EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vdot");
+  }
   }
 
   assert(Int && "Expected valid intrinsic number");

Added: cfe/trunk/test/CodeGen/aarch64-neon-dot-product.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-neon-dot-product.c?rev=331039=auto

r331038 - [ARM] Add __ARM_FEATURE_DOTPROD pre-defined macro

[Oliver Stannard via cfe-commits]

Author: olista01
Date: Fri Apr 27 06:56:02 2018
New Revision: 331038

URL: http://llvm.org/viewvc/llvm-project?rev=331038=rev
Log:
[ARM] Add __ARM_FEATURE_DOTPROD pre-defined macro

This adds a pre-defined macro to test if the compiler has support for the
v8.2-A dot rpoduct intrinsics in AArch32 mode.

The AAcrh64 equivalent has already been added by rL330229.

The ACLE spec which describes this macro hasn't been published yet, but this is
based on the final internal draft, and GCC has already implemented this.

Differential revision: https://reviews.llvm.org/D46108


Modified:
cfe/trunk/lib/Basic/Targets/ARM.cpp
cfe/trunk/lib/Basic/Targets/ARM.h
cfe/trunk/test/Preprocessor/arm-target-features.c

Modified: cfe/trunk/lib/Basic/Targets/ARM.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/ARM.cpp?rev=331038=331037=331038=diff
==
--- cfe/trunk/lib/Basic/Targets/ARM.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/ARM.cpp Fri Apr 27 06:56:02 2018
@@ -390,6 +390,7 @@ bool ARMTargetInfo::handleTargetFeatures
   Unaligned = 1;
   SoftFloat = SoftFloatABI = false;
   HWDiv = 0;
+  DotProd = 0;
 
   // This does not diagnose illegal cases like having both
   // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp".
@@ -432,6 +433,8 @@ bool ARMTargetInfo::handleTargetFeatures
   HW_FP |= HW_FP_HP;
 } else if (Feature == "+fullfp16") {
   HasLegalHalfType = true;
+} else if (Feature == "+dotprod") {
+  DotProd = true;
 }
   }
   HW_FP &= ~HW_FP_remove;
@@ -731,6 +734,9 @@ void ARMTargetInfo::getTargetDefines(con
   if (HasLegalHalfType)
 Builder.defineMacro("__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", "1");
 
+  // Armv8.2-A dot product intrinsics
+  if (DotProd)
+Builder.defineMacro("__ARM_FEATURE_DOTPROD", "1");
 
   switch (ArchKind) {
   default:

Modified: cfe/trunk/lib/Basic/Targets/ARM.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/ARM.h?rev=331038=331037=331038=diff
==
--- cfe/trunk/lib/Basic/Targets/ARM.h (original)
+++ cfe/trunk/lib/Basic/Targets/ARM.h Fri Apr 27 06:56:02 2018
@@ -69,6 +69,7 @@ class LLVM_LIBRARY_VISIBILITY ARMTargetI
   unsigned Crypto : 1;
   unsigned DSP : 1;
   unsigned Unaligned : 1;
+  unsigned DotProd : 1;
 
   enum {
 LDREX_B = (1 << 0), /// byte (8-bit)

Modified: cfe/trunk/test/Preprocessor/arm-target-features.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Preprocessor/arm-target-features.c?rev=331038=331037=331038=diff
==
--- cfe/trunk/test/Preprocessor/arm-target-features.c (original)
+++ cfe/trunk/test/Preprocessor/arm-target-features.c Fri Apr 27 06:56:02 2018
@@ -6,6 +6,7 @@
 // CHECK-V8A: #define __ARM_FEATURE_DIRECTED_ROUNDING 1
 // CHECK-V8A: #define __ARM_FEATURE_NUMERIC_MAXMIN 1
 // CHECK-V8A-NOT: #define __ARM_FP 0x
+// CHECK-V8A-NOT: #define __ARM_FEATURE_DOTPROD
 
 // RUN: %clang -target armv8a-none-linux-gnueabi -x c -E -dM %s -o - | 
FileCheck -match-full-lines --check-prefix=CHECK-V8A-ALLOW-FP-INSTR %s
 // RUN: %clang -target armv8a-none-linux-gnueabihf -x c -E -dM %s -o - | 
FileCheck -match-full-lines --check-prefix=CHECK-V8A-ALLOW-FP-INSTR %s
@@ -18,6 +19,7 @@
 // CHECK-V8A-ALLOW-FP-INSTR: #define __ARM_FP 0xe
 // CHECK-V8A-ALLOW-FP-INSTR: #define __ARM_FP16_ARGS 1
 // CHECK-V8A-ALLOW-FP-INSTR: #define __ARM_FP16_FORMAT_IEEE 1
+// CHECK-V8A-ALLOW-FP-INSTR-V8A-NOT: #define __ARM_FEATURE_DOTPROD
 
 // RUN: %clang -target arm-none-linux-gnueabi -march=armv8.2a+fp16 -x c -E -dM 
%s -o - | FileCheck -match-full-lines 
--check-prefix=CHECK-FULLFP16-VECTOR-SCALAR %s
 // CHECK-FULLFP16-VECTOR-SCALAR: #define __ARM_FEATURE_FP16_SCALAR_ARITHMETIC 1
@@ -30,6 +32,9 @@
 // CHECK-FULLFP16-SCALAR-NOT:   #define __ARM_FEATURE_FP16_VECTOR_ARITHMETIC 1
 // CHECK-FULLFP16-SCALAR:   #define __ARM_FP 0xe
 // CHECK-FULLFP16-SCALAR:   #define __ARM_FP16_FORMAT_IEEE 1
+//
+// RUN: %clang -target arm-none-linux-gnueabi -march=armv8.2a+dotprod -x c -E 
-dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-DOTPROD %s
+// CHECK-DOTPROD: #define __ARM_FEATURE_DOTPROD 1
 
 // RUN: %clang -target armv8r-none-linux-gnu -x c -E -dM %s -o - | FileCheck 
-match-full-lines --check-prefix=CHECK-V8R %s
 // CHECK-V8R: #define __ARMEL__ 1


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r311325 - [ObjC] Use consistent comment style in inline asm

[Oliver Stannard via cfe-commits]

Author: olista01
Date: Mon Aug 21 02:54:46 2017
New Revision: 311325

URL: http://llvm.org/viewvc/llvm-project?rev=311325=rev
Log:
[ObjC] Use consistent comment style in inline asm

The comment markers accepted by the assembler vary between different targets,
but '//' is always accepted, so we should use that for consistency.

Differential revision: https://reviews.llvm.org/D3


Modified:
cfe/trunk/lib/CodeGen/TargetInfo.cpp
cfe/trunk/test/CodeGenObjC/arc-arm.m

Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=311325=311324=311325=diff
==
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Mon Aug 21 02:54:46 2017
@@ -1085,7 +1085,7 @@ public:
 
   StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
 return "movl\t%ebp, %ebp"
-   "\t\t## marker for objc_retainAutoreleaseReturnValue";
+   "\t\t// marker for objc_retainAutoreleaseReturnValue";
   }
 };
 
@@ -4880,7 +4880,7 @@ public:
   : TargetCodeGenInfo(new AArch64ABIInfo(CGT, Kind)) {}
 
   StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
-return "mov\tfp, fp\t\t# marker for objc_retainAutoreleaseReturnValue";
+return "mov\tfp, fp\t\t// marker for objc_retainAutoreleaseReturnValue";
   }
 
   int getDwarfEHStackPointer(CodeGen::CodeGenModule ) const override {
@@ -5486,7 +5486,7 @@ public:
   }
 
   StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
-return "mov\tr7, r7\t\t@ marker for objc_retainAutoreleaseReturnValue";
+return "mov\tr7, r7\t\t// marker for objc_retainAutoreleaseReturnValue";
   }
 
   bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction ,

Modified: cfe/trunk/test/CodeGenObjC/arc-arm.m
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenObjC/arc-arm.m?rev=311325=311324=311325=diff
==
--- cfe/trunk/test/CodeGenObjC/arc-arm.m (original)
+++ cfe/trunk/test/CodeGenObjC/arc-arm.m Mon Aug 21 02:54:46 2017
@@ -13,7 +13,7 @@ id test0(void) {
 void test1(void) {
   extern id test1_helper(void);
   // CHECK:  [[T0:%.*]] = call [[CC]]i8* @test1_helper()
-  // CHECK-NEXT: call void asm sideeffect "mov
+  // CHECK-NEXT: call void asm sideeffect "mov\09{{fp, fp|r7, r7}}\09\09// 
marker for objc_retainAutoreleaseReturnValue"
   // CHECK-NEXT: [[T1:%.*]] = call [[CC]]i8* 
@objc_retainAutoreleasedReturnValue(i8* [[T0]])
   // CHECK-NEXT: store i8* [[T1]],
   // CHECK-NEXT: call [[CC]]void @objc_storeStrong(


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r300550 - [ARM] Add hardware build attributes in assembler

[Oliver Stannard via cfe-commits]

Author: olista01
Date: Tue Apr 18 08:21:05 2017
New Revision: 300550

URL: http://llvm.org/viewvc/llvm-project?rev=300550=rev
Log:
[ARM] Add hardware build attributes in assembler

This passes an option to the ARM assembly parser to emit build
attributes for the hardware selected by command line options, when
assembling an assembly file.

This is not enabled for C/C++, as this would result in duplicate build
attribute directives being emitted in each inline assembly block, when
emitting assembly.

This also adds an option to allow disabling this behaviour for assembly
files, for users who were relying on the old behaviour.

Differential revision: https://reviews.llvm.org/D31813


Added:
cfe/trunk/test/Driver/arm-default-build-attributes.s
Modified:
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/Driver/ToolChains/Clang.cpp

Modified: cfe/trunk/include/clang/Driver/Options.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=300550=300549=300550=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Tue Apr 18 08:21:05 2017
@@ -1646,6 +1646,8 @@ def march_EQ : Joined<["-"], "march=">,
 def masm_EQ : Joined<["-"], "masm=">, Group, Flags<[DriverOption]>;
 def mcmodel_EQ : Joined<["-"], "mcmodel=">, Group;
 def mimplicit_it_EQ : Joined<["-"], "mimplicit-it=">, Group;
+def mdefault_build_attributes : Joined<["-"], "mdefault-build-attributes">, 
Group;
+def mno_default_build_attributes : Joined<["-"], 
"mno-default-build-attributes">, Group;
 def mconstant_cfstrings : Flag<["-"], "mconstant-cfstrings">, 
Group;
 def mconsole : Joined<["-"], "mconsole">, Group, 
Flags<[DriverOption]>;
 def mwindows : Joined<["-"], "mwindows">, Group, 
Flags<[DriverOption]>;

Modified: cfe/trunk/lib/Driver/ToolChains/Clang.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Clang.cpp?rev=300550=300549=300550=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Clang.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Clang.cpp Tue Apr 18 08:21:05 2017
@@ -4996,6 +4996,19 @@ void ClangAs::ConstructJob(Compilation &
   case llvm::Triple::x86_64:
 AddX86TargetArgs(Args, CmdArgs);
 break;
+
+  case llvm::Triple::arm:
+  case llvm::Triple::armeb:
+  case llvm::Triple::thumb:
+  case llvm::Triple::thumbeb:
+// This isn't in AddARMTargetArgs because we want to do this for assembly
+// only, not C/C++.
+if (Args.hasFlag(options::OPT_mdefault_build_attributes,
+ options::OPT_mno_default_build_attributes, true)) {
+CmdArgs.push_back("-mllvm");
+CmdArgs.push_back("-arm-add-build-attributes");
+}
+break;
   }
 
   // Consume all the warning flags. Usually this would be handled more

Added: cfe/trunk/test/Driver/arm-default-build-attributes.s
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/arm-default-build-attributes.s?rev=300550=auto
==
--- cfe/trunk/test/Driver/arm-default-build-attributes.s (added)
+++ cfe/trunk/test/Driver/arm-default-build-attributes.s Tue Apr 18 08:21:05 
2017
@@ -0,0 +1,20 @@
+// Enabled by default for assembly
+// RUN: %clang -target armv7--none-eabi -### %s 2>&1 \
+// RUN:| FileCheck %s -check-prefix CHECK-ENABLED
+
+// Can be forced on or off for assembly.
+// RUN: %clang -target armv7--none-eabi -### %s 2>&1 
-mno-default-build-attributes \
+// RUN:| FileCheck %s -check-prefix CHECK-DISABLED
+// RUN: %clang -target armv7--none-eabi -### %s 2>&1 
-mdefault-build-attributes \
+// RUN:| FileCheck %s -check-prefix CHECK-ENABLED
+
+// Option ignored C/C++ (since we always emit hardware and ABI build attributes
+// during codegen).
+// RUN: %clang -target armv7--none-eabi -### -x c %s 
-mdefault-build-attributes -verify 2>&1 \
+// RUN:| FileCheck %s -check-prefix CHECK-DISABLED
+// RUN: %clang -target armv7--none-eabi -### -x c++ %s 
-mdefault-build-attributes -verify 2>&1 \
+// RUN:| FileCheck %s -check-prefix CHECK-DISABLED
+
+// CHECK-DISABLED-NOT: "-arm-add-build-attributes"
+// CHECK-ENABLED: "-arm-add-build-attributes"
+// expected-warning {{argument unused during compilation: 
'-mno-default-build-attributes'}}


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r300549 - [ARM, AArch64] Define __ELF__ for arm-none-eabihf and AArch64

[Oliver Stannard via cfe-commits]

Author: olista01
Date: Tue Apr 18 08:12:36 2017
New Revision: 300549

URL: http://llvm.org/viewvc/llvm-project?rev=300549=rev
Log:
[ARM,AArch64] Define __ELF__ for arm-none-eabihf and AArch64

This macro is defined for arm-none-eabi as of r266625, but it should also be
defined for eabihf and aarch64.


Modified:
cfe/trunk/lib/Basic/Targets.cpp
cfe/trunk/test/Preprocessor/init.c

Modified: cfe/trunk/lib/Basic/Targets.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=300549=300548=300549=diff
==
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Tue Apr 18 08:12:36 2017
@@ -5467,9 +5467,11 @@ public:
 Builder.defineMacro("__arm__");
 // For bare-metal none-eabi.
 if (getTriple().getOS() == llvm::Triple::UnknownOS &&
-getTriple().getEnvironment() == llvm::Triple::EABI)
+(getTriple().getEnvironment() == llvm::Triple::EABI ||
+ getTriple().getEnvironment() == llvm::Triple::EABIHF))
   Builder.defineMacro("__ELF__");
 
+
 // Target properties.
 Builder.defineMacro("__REGISTER_PREFIX__", "");
 
@@ -6118,6 +6120,11 @@ public:
 MacroBuilder ) const override {
 // Target identification.
 Builder.defineMacro("__aarch64__");
+// For bare-metal none-eabi.
+if (getTriple().getOS() == llvm::Triple::UnknownOS &&
+(getTriple().getEnvironment() == llvm::Triple::EABI ||
+ getTriple().getEnvironment() == llvm::Triple::EABIHF))
+  Builder.defineMacro("__ELF__");
 
 // Target properties.
 Builder.defineMacro("_LP64");

Modified: cfe/trunk/test/Preprocessor/init.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Preprocessor/init.c?rev=300549=300548=300549=diff
==
--- cfe/trunk/test/Preprocessor/init.c (original)
+++ cfe/trunk/test/Preprocessor/init.c Tue Apr 18 08:12:36 2017
@@ -2378,6 +2378,9 @@
 // ARM-NETBSD:#define __arm__ 1
 
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=arm-none-eabi < /dev/null | 
FileCheck -match-full-lines -check-prefix ARM-NONE-EABI %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=arm-none-eabihf < /dev/null | 
FileCheck -match-full-lines -check-prefix ARM-NONE-EABI %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=aarch64-none-eabi < /dev/null 
| FileCheck -match-full-lines -check-prefix ARM-NONE-EABI %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=aarch64-none-eabihf < 
/dev/null | FileCheck -match-full-lines -check-prefix ARM-NONE-EABI %s
 // ARM-NONE-EABI: #define __ELF__ 1
 
 // No MachO targets use the full EABI, even if AAPCS is used.


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RE: [libunwind] r292722 - DWARF: allow enabling tracing at runtime

[Oliver Stannard via cfe-commits]

Hi Saleem,

This patch is causing our internal runs of the libc++ and libc++abi tests to 
fail, because logDWARF is referenced but not defined in release builds (with 
NDEBUG defined).

However, I see that all of the libc++ buildbots are passing. Does this patch 
need modifying to make _LIBUNWIND_TRACE_DWARF conditional on NDEBUG, or is 
there something in the Linux environment that we might need to replicate in our 
bare-metal environment to make this work?

Thanks,
Oliver

> -Original Message-
> From: cfe-commits [mailto:cfe-commits-boun...@lists.llvm.org] On Behalf Of
> Saleem Abdulrasool via cfe-commits
> Sent: 21 January 2017 16:23
> To: cfe-commits@lists.llvm.org
> Subject: [libunwind] r292722 - DWARF: allow enabling tracing at runtime
> 
> Author: compnerd
> Date: Sat Jan 21 10:22:57 2017
> New Revision: 292722
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=292722=rev
> Log:
> DWARF: allow enabling tracing at runtime
> 
> Introduce `logDWARF` and the associated environment variable
> `LIBUNWIND_PRINT_DWARF` to trace the CFI instructions.
> 
> Modified:
> libunwind/trunk/src/DwarfParser.hpp
> libunwind/trunk/src/libunwind.cpp
> 
> Modified: libunwind/trunk/src/DwarfParser.hpp
> URL: http://llvm.org/viewvc/llvm-
> project/libunwind/trunk/src/DwarfParser.hpp?rev=292722=292721=292722
> =diff
> ==
> 
> --- libunwind/trunk/src/DwarfParser.hpp (original)
> +++ libunwind/trunk/src/DwarfParser.hpp Sat Jan 21 10:22:57 2017
> @@ -23,6 +23,14 @@
> 
>  #include "AddressSpace.hpp"
> 
> +extern "C" bool logDWARF();
> +
> +#define _LIBUNWIND_TRACE_DWARF(...)
> \
> +  do {
> \
> +if (logDWARF())
> \
> +  fprintf(stderr, __VA_ARGS__);
> \
> +  } while (0)
> +
>  namespace libunwind {
> 
>  /// CFI_Parser does basic parsing of a CFI (Call Frame Information)
> records.
> @@ -364,13 +372,12 @@ bool CFI_Parser::parseInstructions(A
>const CIE_Info , pint_t
> pcoffset,
>PrologInfoStackEntry
> *,
>PrologInfo *results) {
> -  const bool logDwarf = false;
>pint_t p = instructions;
>pint_t codeOffset = 0;
>PrologInfo initialState = *results;
> -  if (logDwarf)
> -fprintf(stderr, "parseInstructions(instructions=0x%0" PRIx64 ")\n",
> -(uint64_t)instructionsEnd);
> +
> +  _LIBUNWIND_TRACE_DWARF("parseInstructions(instructions=0x%0" PRIx64
> ")\n",
> + static_cast(instructionsEnd));
> 
>// see DWARF Spec, section 6.4.2 for details on unwind opcodes
>while ((p < instructionsEnd) && (codeOffset < pcoffset)) {
> @@ -386,35 +393,30 @@ bool CFI_Parser::parseInstructions(A
>  ++p;
>  switch (opcode) {
>  case DW_CFA_nop:
> -  if (logDwarf)
> -fprintf(stderr, "DW_CFA_nop\n");
> +  _LIBUNWIND_TRACE_DWARF("DW_CFA_nop\n");
>break;
>  case DW_CFA_set_loc:
>codeOffset =
>addressSpace.getEncodedP(p, instructionsEnd,
> cieInfo.pointerEncoding);
> -  if (logDwarf)
> -fprintf(stderr, "DW_CFA_set_loc\n");
> +  _LIBUNWIND_TRACE_DWARF("DW_CFA_set_loc\n");
>break;
>  case DW_CFA_advance_loc1:
>codeOffset += (addressSpace.get8(p) * cieInfo.codeAlignFactor);
>p += 1;
> -  if (logDwarf)
> -fprintf(stderr, "DW_CFA_advance_loc1: new offset=%" PRIu64 "\n",
> -(uint64_t)codeOffset);
> +  _LIBUNWIND_TRACE_DWARF("DW_CFA_advance_loc1: new offset=%" PRIu64
> "\n",
> + static_cast(codeOffset));
>break;
>  case DW_CFA_advance_loc2:
>codeOffset += (addressSpace.get16(p) * cieInfo.codeAlignFactor);
>p += 2;
> -  if (logDwarf)
> -fprintf(stderr, "DW_CFA_advance_loc2: new offset=%" PRIu64 "\n",
> -(uint64_t)codeOffset);
> +  _LIBUNWIND_TRACE_DWARF("DW_CFA_advance_loc2: new offset=%" PRIu64
> "\n",
> + static_cast(codeOffset));
>break;
>  case DW_CFA_advance_loc4:
>codeOffset += (addressSpace.get32(p) * cieInfo.codeAlignFactor);
>p += 4;
> -  if (logDwarf)
> -fprintf(stderr, "DW_CFA_advance_loc4: new offset=%" PRIu64 "\n",
> -(uint64_t)codeOffset);
> +  _LIBUNWIND_TRACE_DWARF("DW_CFA_advance_loc4: new offset=%" PRIu64
> "\n",
> + static_cast(codeOffset));
>break;
>  case DW_CFA_offset_extended:
>reg = addressSpace.getULEB128(p, instructionsEnd);
> @@ -426,21 +428,18 @@ bool CFI_Parser::parseInstructions(A
>}
>results->savedRegisters[reg].location = kRegisterInCFA;
>results->savedRegisters[reg].value = offset;
> -  if (logDwarf)
> -fprintf(stderr,
> -"DW_CFA_offset_extended(reg=%" PRIu64 ", offset=%" PRId64
> ")\n",
> -reg, offset);
> +  

Re: [PATCH] D24245: [ARM] ARM-specific attributes should be accepted for big-endian

[Oliver Stannard via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL281596: [ARM] ARM-specific attributes should be accepted for 
big-endian (authored by olista01).

Changed prior to commit:
  https://reviews.llvm.org/D24245?vs=70364=71485#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D24245

Files:
  cfe/trunk/include/clang/Basic/Attr.td
  cfe/trunk/test/Sema/arm-interrupt-attr.c

Index: cfe/trunk/include/clang/Basic/Attr.td
===
--- cfe/trunk/include/clang/Basic/Attr.td
+++ cfe/trunk/include/clang/Basic/Attr.td
@@ -254,7 +254,7 @@
   list OSes;
   list CXXABIs;
 }
-def TargetARM : TargetArch<["arm", "thumb"]>;
+def TargetARM : TargetArch<["arm", "thumb", "armeb", "thumbeb"]>;
 def TargetMips : TargetArch<["mips", "mipsel"]>;
 def TargetMSP430 : TargetArch<["msp430"]>;
 def TargetX86 : TargetArch<["x86"]>;
Index: cfe/trunk/test/Sema/arm-interrupt-attr.c
===
--- cfe/trunk/test/Sema/arm-interrupt-attr.c
+++ cfe/trunk/test/Sema/arm-interrupt-attr.c
@@ -1,4 +1,7 @@
 // RUN: %clang_cc1 %s -triple arm-apple-darwin -verify -fsyntax-only
+// RUN: %clang_cc1 %s -triple thumb-apple-darwin -verify -fsyntax-only
+// RUN: %clang_cc1 %s -triple armeb-none-eabi -verify -fsyntax-only
+// RUN: %clang_cc1 %s -triple thumbeb-none-eabi -verify -fsyntax-only
 
 __attribute__((interrupt(IRQ))) void foo() {} // expected-error {{'interrupt' 
attribute requires a string}}
 __attribute__((interrupt("irq"))) void foo1() {} // expected-warning 
{{'interrupt' attribute argument not supported: irq}}


Index: cfe/trunk/include/clang/Basic/Attr.td
===
--- cfe/trunk/include/clang/Basic/Attr.td
+++ cfe/trunk/include/clang/Basic/Attr.td
@@ -254,7 +254,7 @@
   list OSes;
   list CXXABIs;
 }
-def TargetARM : TargetArch<["arm", "thumb"]>;
+def TargetARM : TargetArch<["arm", "thumb", "armeb", "thumbeb"]>;
 def TargetMips : TargetArch<["mips", "mipsel"]>;
 def TargetMSP430 : TargetArch<["msp430"]>;
 def TargetX86 : TargetArch<["x86"]>;
Index: cfe/trunk/test/Sema/arm-interrupt-attr.c
===
--- cfe/trunk/test/Sema/arm-interrupt-attr.c
+++ cfe/trunk/test/Sema/arm-interrupt-attr.c
@@ -1,4 +1,7 @@
 // RUN: %clang_cc1 %s -triple arm-apple-darwin -verify -fsyntax-only
+// RUN: %clang_cc1 %s -triple thumb-apple-darwin -verify -fsyntax-only
+// RUN: %clang_cc1 %s -triple armeb-none-eabi -verify -fsyntax-only
+// RUN: %clang_cc1 %s -triple thumbeb-none-eabi -verify -fsyntax-only
 
 __attribute__((interrupt(IRQ))) void foo() {} // expected-error {{'interrupt' attribute requires a string}}
 __attribute__((interrupt("irq"))) void foo1() {} // expected-warning {{'interrupt' attribute argument not supported: irq}}
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r281596 - [ARM] ARM-specific attributes should be accepted for big-endian

[Oliver Stannard via cfe-commits]

Author: olista01
Date: Thu Sep 15 03:55:41 2016
New Revision: 281596

URL: http://llvm.org/viewvc/llvm-project?rev=281596=rev
Log:
[ARM] ARM-specific attributes should be accepted for big-endian

The ARM-specific C attributes (currently just interrupt) need to check
for both the big- and little-endian versions of the triples, so that
they are accepted for both big and little endian targets.

TargetWindows and TargetMicrosoftCXXABI also only use the little-endian
triples, but this is correct as windows is not supported on big-endian
ARM targets (and this is asserted in lib/Basic/Targets.cpp).

Differential Revision: https://reviews.llvm.org/D24245


Modified:
cfe/trunk/include/clang/Basic/Attr.td
cfe/trunk/test/Sema/arm-interrupt-attr.c

Modified: cfe/trunk/include/clang/Basic/Attr.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/Attr.td?rev=281596=281595=281596=diff
==
--- cfe/trunk/include/clang/Basic/Attr.td (original)
+++ cfe/trunk/include/clang/Basic/Attr.td Thu Sep 15 03:55:41 2016
@@ -254,7 +254,7 @@ class TargetArch {
   list OSes;
   list CXXABIs;
 }
-def TargetARM : TargetArch<["arm", "thumb"]>;
+def TargetARM : TargetArch<["arm", "thumb", "armeb", "thumbeb"]>;
 def TargetMips : TargetArch<["mips", "mipsel"]>;
 def TargetMSP430 : TargetArch<["msp430"]>;
 def TargetX86 : TargetArch<["x86"]>;

Modified: cfe/trunk/test/Sema/arm-interrupt-attr.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Sema/arm-interrupt-attr.c?rev=281596=281595=281596=diff
==
--- cfe/trunk/test/Sema/arm-interrupt-attr.c (original)
+++ cfe/trunk/test/Sema/arm-interrupt-attr.c Thu Sep 15 03:55:41 2016
@@ -1,4 +1,7 @@
 // RUN: %clang_cc1 %s -triple arm-apple-darwin -verify -fsyntax-only
+// RUN: %clang_cc1 %s -triple thumb-apple-darwin -verify -fsyntax-only
+// RUN: %clang_cc1 %s -triple armeb-none-eabi -verify -fsyntax-only
+// RUN: %clang_cc1 %s -triple thumbeb-none-eabi -verify -fsyntax-only
 
 __attribute__((interrupt(IRQ))) void foo() {} // expected-error {{'interrupt' 
attribute requires a string}}
 __attribute__((interrupt("irq"))) void foo1() {} // expected-warning 
{{'interrupt' attribute argument not supported: irq}}


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Re: [PATCH] D24245: [ARM] ARM-specific attributes should be accepted for big-endian

[Oliver Stannard via cfe-commits]

olista01 added a comment.

Ping.


Repository:
  rL LLVM

https://reviews.llvm.org/D24245



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[PATCH] D24245: [ARM] ARM-specific attributes should be accepted for big-endian

[Oliver Stannard via cfe-commits]

olista01 created this revision.
olista01 added reviewers: rengolin, t.p.northover.
olista01 added a subscriber: cfe-commits.
olista01 set the repository for this revision to rL LLVM.
Herald added subscribers: samparker, rengolin, aemerson.

The ARM-specific C attributes (currently just interrupt) need to check
for both the big- and little-endian versions of the triples, so that
they are accepted for both big and little endian targets.

TargetWindows and TargetMicrosoftCXXABI also only use the little-endian
triples, but this is correct as windows is not supported on big-endian
ARM targets (and this is asserted in lib/Basic/Targets.cpp).

Repository:
  rL LLVM

https://reviews.llvm.org/D24245

Files:
  include/clang/Basic/Attr.td
  test/Sema/arm-interrupt-attr.c

Index: test/Sema/arm-interrupt-attr.c
===
--- test/Sema/arm-interrupt-attr.c
+++ test/Sema/arm-interrupt-attr.c
@@ -1,4 +1,7 @@
 // RUN: %clang_cc1 %s -triple arm-apple-darwin -verify -fsyntax-only
+// RUN: %clang_cc1 %s -triple thumb-apple-darwin -verify -fsyntax-only
+// RUN: %clang_cc1 %s -triple armeb-none-eabi -verify -fsyntax-only
+// RUN: %clang_cc1 %s -triple thumbeb-none-eabi -verify -fsyntax-only
 
 __attribute__((interrupt(IRQ))) void foo() {} // expected-error {{'interrupt' 
attribute requires a string}}
 __attribute__((interrupt("irq"))) void foo1() {} // expected-warning 
{{'interrupt' attribute argument not supported: irq}}
Index: include/clang/Basic/Attr.td
===
--- include/clang/Basic/Attr.td
+++ include/clang/Basic/Attr.td
@@ -254,7 +254,7 @@
   list OSes;
   list CXXABIs;
 }
-def TargetARM : TargetArch<["arm", "thumb"]>;
+def TargetARM : TargetArch<["arm", "thumb", "armeb", "thumbeb"]>;
 def TargetMips : TargetArch<["mips", "mipsel"]>;
 def TargetMSP430 : TargetArch<["msp430"]>;
 def TargetX86 : TargetArch<["x86"]>;


Index: test/Sema/arm-interrupt-attr.c
===
--- test/Sema/arm-interrupt-attr.c
+++ test/Sema/arm-interrupt-attr.c
@@ -1,4 +1,7 @@
 // RUN: %clang_cc1 %s -triple arm-apple-darwin -verify -fsyntax-only
+// RUN: %clang_cc1 %s -triple thumb-apple-darwin -verify -fsyntax-only
+// RUN: %clang_cc1 %s -triple armeb-none-eabi -verify -fsyntax-only
+// RUN: %clang_cc1 %s -triple thumbeb-none-eabi -verify -fsyntax-only
 
 __attribute__((interrupt(IRQ))) void foo() {} // expected-error {{'interrupt' attribute requires a string}}
 __attribute__((interrupt("irq"))) void foo1() {} // expected-warning {{'interrupt' attribute argument not supported: irq}}
Index: include/clang/Basic/Attr.td
===
--- include/clang/Basic/Attr.td
+++ include/clang/Basic/Attr.td
@@ -254,7 +254,7 @@
   list OSes;
   list CXXABIs;
 }
-def TargetARM : TargetArch<["arm", "thumb"]>;
+def TargetARM : TargetArch<["arm", "thumb", "armeb", "thumbeb"]>;
 def TargetMips : TargetArch<["mips", "mipsel"]>;
 def TargetMSP430 : TargetArch<["msp430"]>;
 def TargetX86 : TargetArch<["x86"]>;
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[PATCH] D23610: [ARM] Add pre-defined macros for ROPI, RWPI and FPIC

[Oliver Stannard via cfe-commits]

olista01 created this revision.
olista01 added reviewers: rengolin, t.p.northover.
olista01 added a subscriber: cfe-commits.
olista01 set the repository for this revision to rL LLVM.
Herald added subscribers: samparker, rengolin, aemerson.

This adds pre-defined macros to test for code being compiled in the FPIC, ROPI 
and RWPI position-independence modes. The names of the macros match those used 
by armcc, which also implements all of the PIC modes.

Repository:
  rL LLVM

https://reviews.llvm.org/D23610

Files:
  include/clang/Basic/LangOptions.def
  include/clang/Driver/Options.td
  lib/Basic/Targets.cpp
  lib/Driver/Tools.cpp
  lib/Frontend/CompilerInvocation.cpp
  test/Preprocessor/arm-pic-predefines.c

Index: test/Preprocessor/arm-pic-predefines.c
===
--- /dev/null
+++ test/Preprocessor/arm-pic-predefines.c
@@ -0,0 +1,20 @@
+// REQUIRES: aarch64-registered-target
+// REQUIRES: arm-registered-target
+//
+// RUN: %clang -target armv8--none-eabi   -x c -E -dM %s -o -   | FileCheck %s --check-prefix=NO-FPIC --check-prefix=NO-ROPI --check-prefix=NO-RWPI
+// RUN: %clang -target armv8--none-eabi   -x c -E -dM %s -o - -fpic | FileCheck %s --check-prefix=FPIC--check-prefix=NO-ROPI --check-prefix=NO-RWPI
+// RUN: %clang -target armv8--none-eabi   -x c -E -dM %s -o - -fropi| FileCheck %s --check-prefix=NO-FPIC --check-prefix=ROPI--check-prefix=NO-RWPI
+// RUN: %clang -target armv8--none-eabi   -x c -E -dM %s -o - -frwpi| FileCheck %s --check-prefix=NO-FPIC --check-prefix=NO-ROPI --check-prefix=RWPI
+// RUN: %clang -target armv8--none-eabi   -x c -E -dM %s -o - -fropi -frwpi | FileCheck %s --check-prefix=NO-FPIC --check-prefix=ROPI--check-prefix=RWPI
+// RUN: %clang -target aarch64--none-eabi -x c -E -dM %s -o - -fpic | FileCheck %s --check-prefix=FPIC--check-prefix=NO-ROPI --check-prefix=NO-RWPI
+
+// Pre-defined macros for position-independence modes
+
+// NO-FPIC-NOT: #define __APCS_FPIC
+// FPIC: #define __APCS_FPIC
+
+// NO-ROPI-NOT: #define __APCS_ROPI
+// ROPI: #define __APCS_ROPI
+
+// NO-RWPI-NOT: #define __APCS_RWPI
+// RWPI: #define __APCS_RWPI
Index: lib/Frontend/CompilerInvocation.cpp
===
--- lib/Frontend/CompilerInvocation.cpp
+++ lib/Frontend/CompilerInvocation.cpp
@@ -1933,6 +1933,8 @@
   Opts.MaxTypeAlign = getLastArgIntValue(Args, OPT_fmax_type_align_EQ, 0, Diags);
   Opts.AlignDouble = Args.hasArg(OPT_malign_double);
   Opts.PICLevel = getLastArgIntValue(Args, OPT_pic_level, 0, Diags);
+  Opts.ROPI = Args.hasArg(OPT_fropi);
+  Opts.RWPI = Args.hasArg(OPT_frwpi);
   Opts.PIE = Args.hasArg(OPT_pic_is_pie);
   Opts.Static = Args.hasArg(OPT_static_define);
   Opts.DumpRecordLayoutsSimple = Args.hasArg(OPT_fdump_record_layouts_simple);
Index: lib/Driver/Tools.cpp
===
--- lib/Driver/Tools.cpp
+++ lib/Driver/Tools.cpp
@@ -4143,6 +4143,12 @@
 if (IsPIE)
   CmdArgs.push_back("-pic-is-pie");
   }
+  if (RelocationModel == llvm::Reloc::ROPI ||
+  RelocationModel == llvm::Reloc::ROPI_RWPI)
+CmdArgs.push_back("-fropi");
+  if (RelocationModel == llvm::Reloc::RWPI ||
+  RelocationModel == llvm::Reloc::ROPI_RWPI)
+CmdArgs.push_back("-frwpi");
 
   if (Arg *A = Args.getLastArg(options::OPT_meabi)) {
 CmdArgs.push_back("-meabi");
Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -5311,6 +5311,13 @@
 
 if (ArchKind == llvm::ARM::AK_ARMV8_1A)
   Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
+
+if (Opts.PICLevel)
+  Builder.defineMacro("__APCS_FPIC", "1");
+if (Opts.ROPI)
+  Builder.defineMacro("__APCS_ROPI", "1");
+if (Opts.RWPI)
+  Builder.defineMacro("__APCS_RWPI", "1");
   }
 
   ArrayRef getTargetBuiltins() const override {
@@ -5830,6 +5837,9 @@
 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
+
+if (Opts.PICLevel)
+  Builder.defineMacro("__APCS_FPIC", "1");
   }
 
   ArrayRef getTargetBuiltins() const override {
Index: include/clang/Driver/Options.td
===
--- include/clang/Driver/Options.td
+++ include/clang/Driver/Options.td
@@ -1089,9 +1089,9 @@
 def fno_pic : Flag<["-"], "fno-pic">, Group;
 def fpie : Flag<["-"], "fpie">, Group;
 def fno_pie : Flag<["-"], "fno-pie">, Group;
-def fropi : Flag<["-"], "fropi">, Group;
+def fropi : Flag<["-"], "fropi">, Group, Flags<[CC1Option]>;
 def fno_ropi : Flag<["-"], "fno-ropi">, Group;
-def frwpi : Flag<["-"], "frwpi">, Group;
+def frwpi : Flag<["-"], "frwpi">, Group, Flags<[CC1Option]>;
 def fno_rwpi : Flag<["-"], "fno-rwpi">, Group;
 def 

Re: [PATCH] D23196: [ARM] Command-line options for embedded position-independent code

[Oliver Stannard via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL278016: [ARM] Command-line options for embedded 
position-independent code (authored by olista01).

Changed prior to commit:
  https://reviews.llvm.org/D23196?vs=66921=67176#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D23196

Files:
  cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td
  cfe/trunk/include/clang/Driver/Options.td
  cfe/trunk/lib/CodeGen/BackendUtil.cpp
  cfe/trunk/lib/Driver/Tools.cpp
  cfe/trunk/test/Driver/ropi-rwpi.c

Index: cfe/trunk/lib/CodeGen/BackendUtil.cpp
===
--- cfe/trunk/lib/CodeGen/BackendUtil.cpp
+++ cfe/trunk/lib/CodeGen/BackendUtil.cpp
@@ -525,6 +525,12 @@
 RM = llvm::Reloc::Static;
   } else if (CodeGenOpts.RelocationModel == "pic") {
 RM = llvm::Reloc::PIC_;
+  } else if (CodeGenOpts.RelocationModel == "ropi") {
+RM = llvm::Reloc::ROPI;
+  } else if (CodeGenOpts.RelocationModel == "rwpi") {
+RM = llvm::Reloc::RWPI;
+  } else if (CodeGenOpts.RelocationModel == "ropi-rwpi") {
+RM = llvm::Reloc::ROPI_RWPI;
   } else {
 assert(CodeGenOpts.RelocationModel == "dynamic-no-pic" &&
"Invalid PIC model!");
Index: cfe/trunk/lib/Driver/Tools.cpp
===
--- cfe/trunk/lib/Driver/Tools.cpp
+++ cfe/trunk/lib/Driver/Tools.cpp
@@ -3777,10 +3777,52 @@
 return std::make_tuple(llvm::Reloc::DynamicNoPIC, PIC ? 2U : 0U, false);
   }
 
+  bool EmbeddedPISupported;
+  switch (ToolChain.getArch()) {
+case llvm::Triple::arm:
+case llvm::Triple::armeb:
+case llvm::Triple::thumb:
+case llvm::Triple::thumbeb:
+  EmbeddedPISupported = true;
+  break;
+default:
+  EmbeddedPISupported = false;
+  break;
+  }
+
+  bool ROPI = false, RWPI = false;
+  Arg* LastROPIArg = Args.getLastArg(options::OPT_fropi, options::OPT_fno_ropi);
+  if (LastROPIArg && LastROPIArg->getOption().matches(options::OPT_fropi)) {
+if (!EmbeddedPISupported)
+  ToolChain.getDriver().Diag(diag::err_drv_unsupported_opt_for_target)
+  << LastROPIArg->getSpelling() << ToolChain.getTriple().str();
+ROPI = true;
+  }
+  Arg *LastRWPIArg = Args.getLastArg(options::OPT_frwpi, options::OPT_fno_rwpi);
+  if (LastRWPIArg && LastRWPIArg->getOption().matches(options::OPT_frwpi)) {
+if (!EmbeddedPISupported)
+  ToolChain.getDriver().Diag(diag::err_drv_unsupported_opt_for_target)
+  << LastRWPIArg->getSpelling() << ToolChain.getTriple().str();
+RWPI = true;
+  }
+
+  // ROPI and RWPI are not comaptible with PIC or PIE.
+  if ((ROPI || RWPI) && (PIC || PIE)) {
+ToolChain.getDriver().Diag(diag::err_drv_ropi_rwpi_incompatible_with_pic);
+  }
+
   if (PIC)
 return std::make_tuple(llvm::Reloc::PIC_, IsPICLevelTwo ? 2U : 1U, PIE);
 
-  return std::make_tuple(llvm::Reloc::Static, 0U, false);
+  llvm::Reloc::Model RelocM = llvm::Reloc::Static;
+  if (ROPI && RWPI)
+RelocM = llvm::Reloc::ROPI_RWPI;
+  else if (ROPI)
+RelocM = llvm::Reloc::ROPI;
+  else if (RWPI)
+RelocM = llvm::Reloc::RWPI;
+
+  return std::make_tuple(RelocM, 0U, false);
 }
 
 static const char *RelocationModelName(llvm::Reloc::Model Model) {
@@ -3791,6 +3833,12 @@
 return "pic";
   case llvm::Reloc::DynamicNoPIC:
 return "dynamic-no-pic";
+  case llvm::Reloc::ROPI:
+return "ropi";
+  case llvm::Reloc::RWPI:
+return "rwpi";
+  case llvm::Reloc::ROPI_RWPI:
+return "ropi-rwpi";
   }
   llvm_unreachable("Unknown Reloc::Model kind");
 }
@@ -4075,6 +4123,13 @@
   ParsePICArgs(getToolChain(), Triple, Args);
 
   const char *RMName = RelocationModelName(RelocationModel);
+
+  if ((RelocationModel == llvm::Reloc::ROPI ||
+   RelocationModel == llvm::Reloc::ROPI_RWPI) &&
+  types::isCXX(Input.getType()) &&
+  !Args.hasArg(options::OPT_fallow_unsupported))
+D.Diag(diag::err_drv_ropi_incompatible_with_cxx);
+
   if (RMName) {
 CmdArgs.push_back("-mrelocation-model");
 CmdArgs.push_back(RMName);
Index: cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td
===
--- cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td
+++ cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td
@@ -240,6 +240,11 @@
 def warn_drv_invoking_fallback : Warning<"falling back to %0">,
   InGroup;
 
+def err_drv_ropi_rwpi_incompatible_with_pic : Error<
+  "embedded and GOT-based position independence are incompatible">;
+def err_drv_ropi_incompatible_with_cxx : Error<
+  "ROPI is not compatible with c++">;
+
 def warn_target_unsupported_nan2008 : Warning<
   "ignoring '-mnan=2008' option because the '%0' architecture does not support it">,
   InGroup;
Index: cfe/trunk/include/clang/Driver/Options.td
===
--- cfe/trunk/include/clang/Driver/Options.td
+++ cfe/trunk/include/clang/Driver/Options.td
@@ 

r278016 - [ARM] Command-line options for embedded position-independent code

[Oliver Stannard via cfe-commits]

Author: olista01
Date: Mon Aug  8 10:28:40 2016
New Revision: 278016

URL: http://llvm.org/viewvc/llvm-project?rev=278016=rev
Log:
[ARM] Command-line options for embedded position-independent code

This patch (with the corresponding ARM backend patch) adds support for
some new relocation models:

* Read-only position independence (ROPI): Code and read-only data is accessed
  PC-relative. The offsets between all code and RO data sections are known at
  static link time.
* Read-write position independence (RWPI): Read-write data is accessed relative
  to a static base register. The offsets between all writeable data sections
  are known at static link time.

These two modes are independent (they specify how different objects
should be addressed), so they can be used individually or together.

These modes are intended for bare-metal systems or systems with small
real-time operating systems. They are designed to avoid the need for a
dynamic linker, the only initialisation required is setting the static
base register to an appropriate value for RWPI code.

There is one C construct not currently supported by these modes: global
variables initialised to the address of another global variable or
function, where that address is not known at static-link time. There are
a few possible ways to solve this:

* Disallow this, and require the user to write their own initialisation
  function if they need variables like this.
* Emit dynamic initialisers for these variables in the compiler, called from
  the .init_array section (as is currently done for C++ dynamic initialisers).
  We have a patch to do this, described in my original RFC email
  (http://lists.llvm.org/pipermail/llvm-dev/2015-December/093022.html), but the
  feedback from that RFC thread was that this is not something that belongs in
  clang.
* Use a small dynamic loader to fix up these variables, by adding the
  difference between the load and execution address of the relevant section.
  This would require linker co-operation to generate a table of addresses that
  need fixing up.

Differential Revision: https://reviews.llvm.org/D23196


Added:
cfe/trunk/test/Driver/ropi-rwpi.c
Modified:
cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/CodeGen/BackendUtil.cpp
cfe/trunk/lib/Driver/Tools.cpp

Modified: cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td?rev=278016=278015=278016=diff
==
--- cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td (original)
+++ cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td Mon Aug  8 10:28:40 
2016
@@ -240,6 +240,11 @@ def err_test_module_file_extension_forma
 def warn_drv_invoking_fallback : Warning<"falling back to %0">,
   InGroup;
 
+def err_drv_ropi_rwpi_incompatible_with_pic : Error<
+  "embedded and GOT-based position independence are incompatible">;
+def err_drv_ropi_incompatible_with_cxx : Error<
+  "ROPI is not compatible with c++">;
+
 def warn_target_unsupported_nan2008 : Warning<
   "ignoring '-mnan=2008' option because the '%0' architecture does not support 
it">,
   InGroup;

Modified: cfe/trunk/include/clang/Driver/Options.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=278016=278015=278016=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Mon Aug  8 10:28:40 2016
@@ -1087,6 +1087,10 @@ def fpic : Flag<["-"], "fpic">, Group, Group;
 def fpie : Flag<["-"], "fpie">, Group;
 def fno_pie : Flag<["-"], "fno-pie">, Group;
+def fropi : Flag<["-"], "fropi">, Group;
+def fno_ropi : Flag<["-"], "fno-ropi">, Group;
+def frwpi : Flag<["-"], "frwpi">, Group;
+def fno_rwpi : Flag<["-"], "fno-rwpi">, Group;
 def fplugin_EQ : Joined<["-"], "fplugin=">, Group, 
Flags<[DriverOption]>, MetaVarName<"">,
   HelpText<"Load the named plugin (dynamic shared object)">;
 def fpreserve_as_comments : Flag<["-"], "fpreserve-as-comments">, 
Group;

Modified: cfe/trunk/lib/CodeGen/BackendUtil.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/BackendUtil.cpp?rev=278016=278015=278016=diff
==
--- cfe/trunk/lib/CodeGen/BackendUtil.cpp (original)
+++ cfe/trunk/lib/CodeGen/BackendUtil.cpp Mon Aug  8 10:28:40 2016
@@ -525,6 +525,12 @@ void EmitAssemblyHelper::CreateTargetMac
 RM = llvm::Reloc::Static;
   } else if (CodeGenOpts.RelocationModel == "pic") {
 RM = llvm::Reloc::PIC_;
+  } else if (CodeGenOpts.RelocationModel == "ropi") {
+RM = llvm::Reloc::ROPI;
+  } else if (CodeGenOpts.RelocationModel == "rwpi") {
+RM = llvm::Reloc::RWPI;
+  } else if (CodeGenOpts.RelocationModel == "ropi-rwpi") {
+RM 

[PATCH] D23196: [ARM] Command-line options for embedded position-independent code

[Oliver Stannard via cfe-commits]

olista01 created this revision.
olista01 added reviewers: t.p.northover, rengolin, srhines, weimingz.
olista01 added a subscriber: cfe-commits.
olista01 set the repository for this revision to rL LLVM.
Herald added subscribers: samparker, rengolin, aemerson.

This patch (with the corresponding ARM backend patch) adds support for
some new relocation models:
- Read-only position independence (ROPI): Code and read-only data is
  accessed PC-relative. The offsets between all code and RO data
  sections are known at static link time.
- Read-write position independence (RWPI): Read-write data is accessed
  relative to a static base register. The offsets between all writeable
  data sections are known at static link time.

These two modes are independent (they specify how different objects
should be addressed), so they can be used individually or together.

These modes are intended for bare-metal systems or systems with small
real-time operating systems. They are designed to avoid the need for a
dynamic linker, the only initialisation required is setting the static
base register to an appropriate value for RWPI code.

There is one C construct not currently supported by these modes: global
variables initialised to the address of another global variable or
function, where that address is not known at static-link time. There are
a few possible ways to solve this:
- Disallow this, and require the user to write their own initialisation
  function if they need variables like this.
- Emit dynamic initialisers for these variables in the compiler, called
  from the .init_array section (as is currently done for C++ dynamic
  initialisers).  We have a patch to do this, described in my original RFC
  email (http://lists.llvm.org/pipermail/llvm-dev/2015-December/093022.html),
  but the feedback from that RFC thread was that this is not something
  that belongs in clang.
- Use a small dynamic loader to fix up these variables, by adding the
  difference between the load and execution address of the relevant
  section.  This would require linker co-operation to generate a table of
  addresses that need fixing up.

Repository:
  rL LLVM

https://reviews.llvm.org/D23196

Files:
  include/clang/Basic/DiagnosticDriverKinds.td
  include/clang/Driver/Options.td
  lib/CodeGen/BackendUtil.cpp
  lib/Driver/Tools.cpp
  test/Driver/ropi-rwpi.c

Index: test/Driver/ropi-rwpi.c
===
--- /dev/null
+++ test/Driver/ropi-rwpi.c
@@ -0,0 +1,38 @@
+// RUN: %clang -target arm-none-eabi   -### -c %s 2>&1 | FileCheck --check-prefix=STATIC %s
+// RUN: %clang -target arm-none-eabi -fropi-### -c %s 2>&1 | FileCheck --check-prefix=ROPI %s
+// RUN: %clang -target arm-none-eabi-frwpi -### -c %s 2>&1 | FileCheck --check-prefix=RWPI %s
+// RUN: %clang -target arm-none-eabi -fropi -frwpi -### -c %s 2>&1 | FileCheck --check-prefix=ROPI-RWPI %s
+
+// RUN: %clang -target armeb-none-eabi   -fropi-### -c %s 2>&1 | FileCheck --check-prefix=ROPI %s
+// RUN: %clang -target thumb-none-eabi   -fropi-### -c %s 2>&1 | FileCheck --check-prefix=ROPI %s
+// RUN: %clang -target thumbeb-none-eabi -fropi-### -c %s 2>&1 | FileCheck --check-prefix=ROPI %s
+
+// RUN: %clang -target x86_64-linux-gnu -fropi-### -c %s 2>&1 | FileCheck --check-prefix=ROPI-NON-ARM %s
+// RUN: %clang -target x86_64-linux-gnu-frwpi -### -c %s 2>&1 | FileCheck --check-prefix=RWPI-NON-ARM %s
+// RUN: %clang -target x86_64-linux-gnu -fropi -frwpi -### -c %s 2>&1 | FileCheck --check-prefix=ROPI-NON-ARM --check-prefix=RWPI-NON-ARM %s
+
+// RUN: %clang -target arm-none-eabi -fpic-fropi-### -c %s 2>&1 | FileCheck --check-prefix=PIC %s
+// RUN: %clang -target arm-none-eabi -fpie   -frwpi -### -c %s 2>&1 | FileCheck --check-prefix=PIC %s
+// RUN: %clang -target arm-none-eabi -fPIC-fropi -frwpi -### -c %s 2>&1 | FileCheck --check-prefix=PIC %s
+// RUN: %clang -target arm-none-eabi -fno-pic -fropi-### -c %s 2>&1 | FileCheck --check-prefix=ROPI %s
+
+// RUN: %clang -target arm-none-eabi -x c++ -fropi-### -c %s 2>&1 | FileCheck --check-prefix=CXX %s
+// RUN: %clang -target arm-none-eabi -x c++-frwpi -### -c %s 2>&1 | FileCheck --check-prefix=RWPI %s
+// RUN: %clang -target arm-none-eabi -x c++ -fropi -frwpi -### -c %s 2>&1 | FileCheck --check-prefix=CXX %s
+// RUN: %clang -target arm-none-eabi -x c++ -fallow-unsupported -fropi-### -c %s 2>&1 | FileCheck --check-prefix=ROPI %s
+
+
+// STATIC: "-mrelocation-model" "static"
+
+// ROPI: "-mrelocation-model" "ropi"
+
+// RWPI: "-mrelocation-model" "rwpi"
+
+// ROPI-RWPI: "-mrelocation-model" "ropi-rwpi"
+
+// ROPI-NON-ARM: error: unsupported option '-fropi' for target 'x86_64--linux-gnu'
+// RWPI-NON-ARM: error: unsupported option '-frwpi' for target 'x86_64--linux-gnu'
+
+// PIC: error: embedded and GOT-based position independence are incompatible
+
+// CXX: error: ROPI is not compatible 

r276851 - [ARM] Pass -mimplcit-it= to integrated assembler

[Oliver Stannard via cfe-commits]

Author: olista01
Date: Wed Jul 27 03:54:13 2016
New Revision: 276851

URL: http://llvm.org/viewvc/llvm-project?rev=276851=rev
Log:
[ARM] Pass -mimplcit-it= to integrated assembler

Differential Revision: https://reviews.llvm.org/D22761


Added:
cfe/trunk/test/Driver/arm-implicit-it.s
Modified:
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/Driver/Tools.cpp

Modified: cfe/trunk/include/clang/Driver/Options.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=276851=276850=276851=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Wed Jul 27 03:54:13 2016
@@ -1377,6 +1377,7 @@ def mwatchsimulator_version_min_EQ : Joi
 def march_EQ : Joined<["-"], "march=">, Group;
 def masm_EQ : Joined<["-"], "masm=">, Group, Flags<[DriverOption]>;
 def mcmodel_EQ : Joined<["-"], "mcmodel=">, Group;
+def mimplicit_it_EQ : Joined<["-"], "mimplicit-it=">, Group;
 def mconstant_cfstrings : Flag<["-"], "mconstant-cfstrings">, 
Group;
 def mconsole : Joined<["-"], "mconsole">, Group, 
Flags<[DriverOption]>;
 def mwindows : Joined<["-"], "mwindows">, Group, 
Flags<[DriverOption]>;

Modified: cfe/trunk/lib/Driver/Tools.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/Tools.cpp?rev=276851=276850=276851=diff
==
--- cfe/trunk/lib/Driver/Tools.cpp (original)
+++ cfe/trunk/lib/Driver/Tools.cpp Wed Jul 27 03:54:13 2016
@@ -2882,6 +2882,27 @@ static void CollectArgsForIntegratedAsse
DefaultIncrementalLinkerCompatible))
 CmdArgs.push_back("-mincremental-linker-compatible");
 
+  switch (C.getDefaultToolChain().getArch()) {
+  case llvm::Triple::arm:
+  case llvm::Triple::armeb:
+  case llvm::Triple::thumb:
+  case llvm::Triple::thumbeb:
+if (Arg *A = Args.getLastArg(options::OPT_mimplicit_it_EQ)) {
+  StringRef Value = A->getValue();
+  if (Value == "always" || Value == "never" || Value == "arm" ||
+  Value == "thumb") {
+CmdArgs.push_back("-mllvm");
+CmdArgs.push_back(Args.MakeArgString("-arm-implicit-it=" + Value));
+  } else {
+D.Diag(diag::err_drv_unsupported_option_argument)
+<< A->getOption().getName() << Value;
+  }
+}
+break;
+  default:
+break;
+  }
+
   // When passing -I arguments to the assembler we sometimes need to
   // unconditionally take the next argument.  For example, when parsing
   // '-Wa,-I -Wa,foo' we need to accept the -Wa,foo arg after seeing the

Added: cfe/trunk/test/Driver/arm-implicit-it.s
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/arm-implicit-it.s?rev=276851=auto
==
--- cfe/trunk/test/Driver/arm-implicit-it.s (added)
+++ cfe/trunk/test/Driver/arm-implicit-it.s Wed Jul 27 03:54:13 2016
@@ -0,0 +1,24 @@
+// RUN: %clang -target armv7--none-eabi -### %s 2>&1 \
+// RUN:| FileCheck %s -check-prefix CHECK-DEFAULT
+
+// RUN: %clang -target armv7--none-eabi -mimplicit-it=arm -### %s 2>&1 \
+// RUN:| FileCheck %s -check-prefix CHECK-ARM
+
+// RUN: %clang -target armv7--none-eabi -mimplicit-it=thumb -### %s 2>&1 \
+// RUN:| FileCheck %s -check-prefix CHECK-THUMB
+
+// RUN: %clang -target armv7--none-eabi -mimplicit-it=never -### %s 2>&1 \
+// RUN:| FileCheck %s -check-prefix CHECK-NEVER
+
+// RUN: %clang -target armv7--none-eabi -mimplicit-it=always -### %s 2>&1 \
+// RUN:| FileCheck %s -check-prefix CHECK-ALWAYS
+
+// RUN: %clang -target armv7--none-eabi -mimplicit-it=thisisnotavalidoption 
-### %s 2>&1 \
+// RUN:| FileCheck %s -check-prefix CHECK-INVALID
+
+// CHECK-DEFAULT-NOT: "-arm-implicit-it
+// CHECK-ARM: "-arm-implicit-it=arm"
+// CHECK-THUMB: "-arm-implicit-it=thumb"
+// CHECK-NEVER: "-arm-implicit-it=never"
+// CHECK-ALWAYS: "-arm-implicit-it=always"
+// CHECK-INVALID: error: unsupported argument 'thisisnotavalidoption' to 
option 'mimplicit-it='


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Re: [PATCH] D22292: [libunwind] Fix unw_getcontext for ARMv6-m

[Oliver Stannard via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL276625: [libunwind][ARM] Add support for Thumb1 targets 
(authored by olista01).

Changed prior to commit:
  https://reviews.llvm.org/D22292?vs=65039=65317#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D22292

Files:
  libunwind/trunk/src/UnwindRegistersRestore.S
  libunwind/trunk/src/UnwindRegistersSave.S

Index: libunwind/trunk/src/UnwindRegistersRestore.S
===
--- libunwind/trunk/src/UnwindRegistersRestore.S
+++ libunwind/trunk/src/UnwindRegistersRestore.S
@@ -322,9 +322,18 @@
 @
   .p2align 2
 
DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm20restoreCoreAndJumpToEv)
-#if !defined(__ARM_ARCH_ISA_ARM)
-  ldr r2, [r0, #52]
-  ldr r3, [r0, #60]
+#if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
+  @ r8-r11: ldm into r1-r4, then mov to r8-r11
+  adds r0, #0x20
+  ldm r0!, {r1-r4}
+  subs r0, #0x30
+  mov r8, r1
+  mov r9, r2
+  mov r10, r3
+  mov r11, r4
+  @ r12 does not need loading, it it the intra-procedure-call scratch register
+  ldr r2, [r0, #0x34]
+  ldr r3, [r0, #0x3c]
   mov sp, r2
   mov lr, r3 @ restore pc into lr
   ldm r0, {r0-r7}
Index: libunwind/trunk/src/UnwindRegistersSave.S
===
--- libunwind/trunk/src/UnwindRegistersSave.S
+++ libunwind/trunk/src/UnwindRegistersSave.S
@@ -309,28 +309,32 @@
 @
   .p2align 2
 DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
-#if !defined(__ARM_ARCH_ISA_ARM)
-  stm r0, {r0-r7}
+#if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
+  stm r0!, {r0-r7}
+  mov r1, r8
+  mov r2, r9
+  mov r3, r10
+  stm r0!, {r1-r3}
+  mov r1, r11
   mov r2, sp
   mov r3, lr
-  str r2, [r0, #52]
-  str r3, [r0, #56]
-  str r3, [r0, #60]  @ store return address as pc
+  str r1, [r0, #0]   @ r11
+  @ r12 does not need storing, it it the intra-procedure-call scratch register
+  str r2, [r0, #8]   @ sp
+  str r3, [r0, #12]  @ lr
+  str r3, [r0, #16]  @ store return address as pc
+  @ T1 does not have a non-cpsr-clobbering register-zeroing instruction.
+  @ It is safe to use here though because we are about to return, and cpsr is
+  @ not expected to be preserved.
+  movs r0, #0@ return UNW_ESUCCESS
 #else
   @ 32bit thumb-2 restrictions for stm:
   @ . the sp (r13) cannot be in the list
   @ . the pc (r15) cannot be in the list in an STM instruction
   stm r0, {r0-r12}
   str sp, [r0, #52]
   str lr, [r0, #56]
   str lr, [r0, #60]  @ store return address as pc
-#endif
-#if __ARM_ARCH_ISA_THUMB == 1
-  @ T1 does not have a non-cpsr-clobbering register-zeroing instruction.
-  @ It is safe to use here though because we are about to return, and cpsr is
-  @ not expected to be preserved.
-  movs r0, #0@ return UNW_ESUCCESS
-#else
   mov r0, #0 @ return UNW_ESUCCESS
 #endif
   JMP(lr)


Index: libunwind/trunk/src/UnwindRegistersRestore.S
===
--- libunwind/trunk/src/UnwindRegistersRestore.S
+++ libunwind/trunk/src/UnwindRegistersRestore.S
@@ -322,9 +322,18 @@
 @
   .p2align 2
 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm20restoreCoreAndJumpToEv)
-#if !defined(__ARM_ARCH_ISA_ARM)
-  ldr r2, [r0, #52]
-  ldr r3, [r0, #60]
+#if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
+  @ r8-r11: ldm into r1-r4, then mov to r8-r11
+  adds r0, #0x20
+  ldm r0!, {r1-r4}
+  subs r0, #0x30
+  mov r8, r1
+  mov r9, r2
+  mov r10, r3
+  mov r11, r4
+  @ r12 does not need loading, it it the intra-procedure-call scratch register
+  ldr r2, [r0, #0x34]
+  ldr r3, [r0, #0x3c]
   mov sp, r2
   mov lr, r3 @ restore pc into lr
   ldm r0, {r0-r7}
Index: libunwind/trunk/src/UnwindRegistersSave.S
===
--- libunwind/trunk/src/UnwindRegistersSave.S
+++ libunwind/trunk/src/UnwindRegistersSave.S
@@ -309,28 +309,32 @@
 @
   .p2align 2
 DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
-#if !defined(__ARM_ARCH_ISA_ARM)
-  stm r0, {r0-r7}
+#if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
+  stm r0!, {r0-r7}
+  mov r1, r8
+  mov r2, r9
+  mov r3, r10
+  stm r0!, {r1-r3}
+  mov r1, r11
   mov r2, sp
   mov r3, lr
-  str r2, [r0, #52]
-  str r3, [r0, #56]
-  str r3, [r0, #60]  @ store return address as pc
+  str r1, [r0, #0]   @ r11
+  @ r12 does not need storing, it it the intra-procedure-call scratch register
+  str r2, [r0, #8]   @ sp
+  str r3, [r0, #12]  @ lr
+  str r3, [r0, #16]  @ store return address as pc
+  @ T1 does not have a non-cpsr-clobbering register-zeroing instruction.
+  @ It is safe to use here though because we are about to return, and cpsr is
+  @ not expected to be preserved.
+  movs r0, #0@ return UNW_ESUCCESS
 #else
   @ 32bit thumb-2 restrictions for stm:
   @ . the sp (r13) cannot be in the list
   @ . the pc (r15) cannot be in the list in an 

[libunwind] r276625 - [libunwind][ARM] Add support for Thumb1 targets

[Oliver Stannard via cfe-commits]

Author: olista01
Date: Mon Jul 25 04:21:56 2016
New Revision: 276625

URL: http://llvm.org/viewvc/llvm-project?rev=276625=rev
Log:
[libunwind][ARM] Add support for Thumb1 targets

The Thumb1 version of the code for saving and restoring the unwind
context has a few bugs which prevent it from working:
* It uses the STM instruction without writeback, which is not valid for Thumb1
  (It was introduced in Thumb2).
* It only saves/restores the low 8 registers, the sp and the lr, so if a
  program uses r8-r12 they will not be correctly restored when throwing an
  exception.

There aren't currently any Thumb1 build-bots to test this, but we have
been successfully running the libc++abi and libc++ test suites on
Cortex-M0 models, as well as some other test suites that use C++
exceptions on a downstream version of libunwind with this patch applied.

Differential Revision: https://reviews.llvm.org/D22292


Modified:
libunwind/trunk/src/UnwindRegistersRestore.S
libunwind/trunk/src/UnwindRegistersSave.S

Modified: libunwind/trunk/src/UnwindRegistersRestore.S
URL: 
http://llvm.org/viewvc/llvm-project/libunwind/trunk/src/UnwindRegistersRestore.S?rev=276625=276624=276625=diff
==
--- libunwind/trunk/src/UnwindRegistersRestore.S (original)
+++ libunwind/trunk/src/UnwindRegistersRestore.S Mon Jul 25 04:21:56 2016
@@ -322,9 +322,18 @@ DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9li
 @
   .p2align 2
 
DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm20restoreCoreAndJumpToEv)
-#if !defined(__ARM_ARCH_ISA_ARM)
-  ldr r2, [r0, #52]
-  ldr r3, [r0, #60]
+#if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
+  @ r8-r11: ldm into r1-r4, then mov to r8-r11
+  adds r0, #0x20
+  ldm r0!, {r1-r4}
+  subs r0, #0x30
+  mov r8, r1
+  mov r9, r2
+  mov r10, r3
+  mov r11, r4
+  @ r12 does not need loading, it it the intra-procedure-call scratch register
+  ldr r2, [r0, #0x34]
+  ldr r3, [r0, #0x3c]
   mov sp, r2
   mov lr, r3 @ restore pc into lr
   ldm r0, {r0-r7}

Modified: libunwind/trunk/src/UnwindRegistersSave.S
URL: 
http://llvm.org/viewvc/llvm-project/libunwind/trunk/src/UnwindRegistersSave.S?rev=276625=276624=276625=diff
==
--- libunwind/trunk/src/UnwindRegistersSave.S (original)
+++ libunwind/trunk/src/UnwindRegistersSave.S Mon Jul 25 04:21:56 2016
@@ -309,13 +309,24 @@ DEFINE_LIBUNWIND_FUNCTION(unw_getcontext
 @
   .p2align 2
 DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
-#if !defined(__ARM_ARCH_ISA_ARM)
-  stm r0, {r0-r7}
+#if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
+  stm r0!, {r0-r7}
+  mov r1, r8
+  mov r2, r9
+  mov r3, r10
+  stm r0!, {r1-r3}
+  mov r1, r11
   mov r2, sp
   mov r3, lr
-  str r2, [r0, #52]
-  str r3, [r0, #56]
-  str r3, [r0, #60]  @ store return address as pc
+  str r1, [r0, #0]   @ r11
+  @ r12 does not need storing, it it the intra-procedure-call scratch register
+  str r2, [r0, #8]   @ sp
+  str r3, [r0, #12]  @ lr
+  str r3, [r0, #16]  @ store return address as pc
+  @ T1 does not have a non-cpsr-clobbering register-zeroing instruction.
+  @ It is safe to use here though because we are about to return, and cpsr is
+  @ not expected to be preserved.
+  movs r0, #0@ return UNW_ESUCCESS
 #else
   @ 32bit thumb-2 restrictions for stm:
   @ . the sp (r13) cannot be in the list
@@ -324,13 +335,6 @@ DEFINE_LIBUNWIND_FUNCTION(unw_getcontext
   str sp, [r0, #52]
   str lr, [r0, #56]
   str lr, [r0, #60]  @ store return address as pc
-#endif
-#if __ARM_ARCH_ISA_THUMB == 1
-  @ T1 does not have a non-cpsr-clobbering register-zeroing instruction.
-  @ It is safe to use here though because we are about to return, and cpsr is
-  @ not expected to be preserved.
-  movs r0, #0@ return UNW_ESUCCESS
-#else
   mov r0, #0 @ return UNW_ESUCCESS
 #endif
   JMP(lr)


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Re: [PATCH] D22292: [libunwind] Fix unw_getcontext for ARMv6-m

[Oliver Stannard via cfe-commits]

olista01 updated this revision to Diff 65039.
olista01 added a comment.

- ADD must be ADDS for Thumb1 (previous patch was an old version uploaded by 
mistake)


https://reviews.llvm.org/D22292

Files:
  src/UnwindRegistersRestore.S
  src/UnwindRegistersSave.S

Index: src/UnwindRegistersSave.S
===
--- src/UnwindRegistersSave.S
+++ src/UnwindRegistersSave.S
@@ -309,28 +309,32 @@
 @
   .p2align 2
 DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
-#if !defined(__ARM_ARCH_ISA_ARM)
-  stm r0, {r0-r7}
+#if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
+  stm r0!, {r0-r7}
+  mov r1, r8
+  mov r2, r9
+  mov r3, r10
+  stm r0!, {r1-r3}
+  mov r1, r11
   mov r2, sp
   mov r3, lr
-  str r2, [r0, #52]
-  str r3, [r0, #56]
-  str r3, [r0, #60]  @ store return address as pc
+  str r1, [r0, #0]   @ r11
+  @ r12 does not need storing, it it the intra-procedure-call scratch register
+  str r2, [r0, #8]   @ sp
+  str r3, [r0, #12]  @ lr
+  str r3, [r0, #16]  @ store return address as pc
+  @ T1 does not have a non-cpsr-clobbering register-zeroing instruction.
+  @ It is safe to use here though because we are about to return, and cpsr is
+  @ not expected to be preserved.
+  movs r0, #0@ return UNW_ESUCCESS
 #else
   @ 32bit thumb-2 restrictions for stm:
   @ . the sp (r13) cannot be in the list
   @ . the pc (r15) cannot be in the list in an STM instruction
   stm r0, {r0-r12}
   str sp, [r0, #52]
   str lr, [r0, #56]
   str lr, [r0, #60]  @ store return address as pc
-#endif
-#if __ARM_ARCH_ISA_THUMB == 1
-  @ T1 does not have a non-cpsr-clobbering register-zeroing instruction.
-  @ It is safe to use here though because we are about to return, and cpsr is
-  @ not expected to be preserved.
-  movs r0, #0@ return UNW_ESUCCESS
-#else
   mov r0, #0 @ return UNW_ESUCCESS
 #endif
   JMP(lr)
Index: src/UnwindRegistersRestore.S
===
--- src/UnwindRegistersRestore.S
+++ src/UnwindRegistersRestore.S
@@ -322,9 +322,18 @@
 @
   .p2align 2
 
DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm20restoreCoreAndJumpToEv)
-#if !defined(__ARM_ARCH_ISA_ARM)
-  ldr r2, [r0, #52]
-  ldr r3, [r0, #60]
+#if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
+  @ r8-r11: ldm into r1-r4, then mov to r8-r11
+  adds r0, #0x20
+  ldm r0!, {r1-r4}
+  subs r0, #0x30
+  mov r8, r1
+  mov r9, r2
+  mov r10, r3
+  mov r11, r4
+  @ r12 does not need loading, it it the intra-procedure-call scratch register
+  ldr r2, [r0, #0x34]
+  ldr r3, [r0, #0x3c]
   mov sp, r2
   mov lr, r3 @ restore pc into lr
   ldm r0, {r0-r7}


Index: src/UnwindRegistersSave.S
===
--- src/UnwindRegistersSave.S
+++ src/UnwindRegistersSave.S
@@ -309,28 +309,32 @@
 @
   .p2align 2
 DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
-#if !defined(__ARM_ARCH_ISA_ARM)
-  stm r0, {r0-r7}
+#if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
+  stm r0!, {r0-r7}
+  mov r1, r8
+  mov r2, r9
+  mov r3, r10
+  stm r0!, {r1-r3}
+  mov r1, r11
   mov r2, sp
   mov r3, lr
-  str r2, [r0, #52]
-  str r3, [r0, #56]
-  str r3, [r0, #60]  @ store return address as pc
+  str r1, [r0, #0]   @ r11
+  @ r12 does not need storing, it it the intra-procedure-call scratch register
+  str r2, [r0, #8]   @ sp
+  str r3, [r0, #12]  @ lr
+  str r3, [r0, #16]  @ store return address as pc
+  @ T1 does not have a non-cpsr-clobbering register-zeroing instruction.
+  @ It is safe to use here though because we are about to return, and cpsr is
+  @ not expected to be preserved.
+  movs r0, #0@ return UNW_ESUCCESS
 #else
   @ 32bit thumb-2 restrictions for stm:
   @ . the sp (r13) cannot be in the list
   @ . the pc (r15) cannot be in the list in an STM instruction
   stm r0, {r0-r12}
   str sp, [r0, #52]
   str lr, [r0, #56]
   str lr, [r0, #60]  @ store return address as pc
-#endif
-#if __ARM_ARCH_ISA_THUMB == 1
-  @ T1 does not have a non-cpsr-clobbering register-zeroing instruction.
-  @ It is safe to use here though because we are about to return, and cpsr is
-  @ not expected to be preserved.
-  movs r0, #0@ return UNW_ESUCCESS
-#else
   mov r0, #0 @ return UNW_ESUCCESS
 #endif
   JMP(lr)
Index: src/UnwindRegistersRestore.S
===
--- src/UnwindRegistersRestore.S
+++ src/UnwindRegistersRestore.S
@@ -322,9 +322,18 @@
 @
   .p2align 2
 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm20restoreCoreAndJumpToEv)
-#if !defined(__ARM_ARCH_ISA_ARM)
-  ldr r2, [r0, #52]
-  ldr r3, [r0, #60]
+#if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
+  @ r8-r11: ldm into r1-r4, then mov to r8-r11
+  adds r0, #0x20
+  ldm r0!, {r1-r4}
+  subs r0, #0x30
+  mov r8, r1
+  mov r9, r2
+  mov r10, r3
+  mov r11, r4
+  @ r12 does not need loading, it it the intra-procedure-call scratch 

Re: [PATCH] D22292: [libunwind] Fix unw_getcontext for ARMv6-m

[Oliver Stannard via cfe-commits]

olista01 added inline comments.


Comment at: src/UnwindRegistersRestore.S:325-336
@@ -324,5 +324,14 @@
 
DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm20restoreCoreAndJumpToEv)
-#if !defined(__ARM_ARCH_ISA_ARM)
-  ldr r2, [r0, #52]
-  ldr r3, [r0, #60]
+#if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
+  @ r8-r11: ldm into r1-r4, then mov to r8-r11
+  add r0, #0x20
+  ldm r0!, {r1-r4}
+  sub r0, #0x30
+  mov r8, r1
+  mov r9, r2
+  mov r10, r3
+  mov r11, r4
+  @ r12 does not need loading, it it the intra-procedure-call scratch register
+  ldr r2, [r0, #0x34]
+  ldr r3, [r0, #0x3c]
   mov sp, r2

> Maybe we should have three implementations?

Previously, we had two implementations:
* The first one is used for all thumb-only targets, but is only valid thumb2 
code, and doesn't save the high registers
* The second one is ARM code used for all targets that have ARM (despite the 
comment about thumb2)

Now we have:
* The first one is used for Thumb1-only targets
* The second one is used for targets that have Thumb2 or ARM, and assembles as 
either ISA (with a preference for ARM, if that is available)


https://reviews.llvm.org/D22292



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Re: [PATCH] D22292: [libunwind] Fix unw_getcontext for ARMv6-m

[Oliver Stannard via cfe-commits]

olista01 updated this revision to Diff 65037.
olista01 added a comment.
Herald added a subscriber: samparker.

- Don't save/restore r12
- Use LDM when restoring r8-r11


https://reviews.llvm.org/D22292

Files:
  src/UnwindRegistersRestore.S
  src/UnwindRegistersSave.S

Index: src/UnwindRegistersSave.S
===
--- src/UnwindRegistersSave.S
+++ src/UnwindRegistersSave.S
@@ -309,28 +309,32 @@
 @
   .p2align 2
 DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
-#if !defined(__ARM_ARCH_ISA_ARM)
-  stm r0, {r0-r7}
+#if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
+  stm r0!, {r0-r7}
+  mov r1, r8
+  mov r2, r9
+  mov r3, r10
+  stm r0!, {r1-r3}
+  mov r1, r11
   mov r2, sp
   mov r3, lr
-  str r2, [r0, #52]
-  str r3, [r0, #56]
-  str r3, [r0, #60]  @ store return address as pc
+  str r1, [r0, #0]   @ r11
+  @ r12 does not need storing, it it the intra-procedure-call scratch register
+  str r2, [r0, #8]   @ sp
+  str r3, [r0, #12]  @ lr
+  str r3, [r0, #16]  @ store return address as pc
+  @ T1 does not have a non-cpsr-clobbering register-zeroing instruction.
+  @ It is safe to use here though because we are about to return, and cpsr is
+  @ not expected to be preserved.
+  movs r0, #0@ return UNW_ESUCCESS
 #else
   @ 32bit thumb-2 restrictions for stm:
   @ . the sp (r13) cannot be in the list
   @ . the pc (r15) cannot be in the list in an STM instruction
   stm r0, {r0-r12}
   str sp, [r0, #52]
   str lr, [r0, #56]
   str lr, [r0, #60]  @ store return address as pc
-#endif
-#if __ARM_ARCH_ISA_THUMB == 1
-  @ T1 does not have a non-cpsr-clobbering register-zeroing instruction.
-  @ It is safe to use here though because we are about to return, and cpsr is
-  @ not expected to be preserved.
-  movs r0, #0@ return UNW_ESUCCESS
-#else
   mov r0, #0 @ return UNW_ESUCCESS
 #endif
   JMP(lr)
Index: src/UnwindRegistersRestore.S
===
--- src/UnwindRegistersRestore.S
+++ src/UnwindRegistersRestore.S
@@ -322,9 +322,18 @@
 @
   .p2align 2
 
DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm20restoreCoreAndJumpToEv)
-#if !defined(__ARM_ARCH_ISA_ARM)
-  ldr r2, [r0, #52]
-  ldr r3, [r0, #60]
+#if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
+  @ r8-r11: ldm into r1-r4, then mov to r8-r11
+  add r0, #0x20
+  ldm r0!, {r1-r4}
+  sub r0, #0x30
+  mov r8, r1
+  mov r9, r2
+  mov r10, r3
+  mov r11, r4
+  @ r12 does not need loading, it it the intra-procedure-call scratch register
+  ldr r2, [r0, #0x34]
+  ldr r3, [r0, #0x3c]
   mov sp, r2
   mov lr, r3 @ restore pc into lr
   ldm r0, {r0-r7}


Index: src/UnwindRegistersSave.S
===
--- src/UnwindRegistersSave.S
+++ src/UnwindRegistersSave.S
@@ -309,28 +309,32 @@
 @
   .p2align 2
 DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
-#if !defined(__ARM_ARCH_ISA_ARM)
-  stm r0, {r0-r7}
+#if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
+  stm r0!, {r0-r7}
+  mov r1, r8
+  mov r2, r9
+  mov r3, r10
+  stm r0!, {r1-r3}
+  mov r1, r11
   mov r2, sp
   mov r3, lr
-  str r2, [r0, #52]
-  str r3, [r0, #56]
-  str r3, [r0, #60]  @ store return address as pc
+  str r1, [r0, #0]   @ r11
+  @ r12 does not need storing, it it the intra-procedure-call scratch register
+  str r2, [r0, #8]   @ sp
+  str r3, [r0, #12]  @ lr
+  str r3, [r0, #16]  @ store return address as pc
+  @ T1 does not have a non-cpsr-clobbering register-zeroing instruction.
+  @ It is safe to use here though because we are about to return, and cpsr is
+  @ not expected to be preserved.
+  movs r0, #0@ return UNW_ESUCCESS
 #else
   @ 32bit thumb-2 restrictions for stm:
   @ . the sp (r13) cannot be in the list
   @ . the pc (r15) cannot be in the list in an STM instruction
   stm r0, {r0-r12}
   str sp, [r0, #52]
   str lr, [r0, #56]
   str lr, [r0, #60]  @ store return address as pc
-#endif
-#if __ARM_ARCH_ISA_THUMB == 1
-  @ T1 does not have a non-cpsr-clobbering register-zeroing instruction.
-  @ It is safe to use here though because we are about to return, and cpsr is
-  @ not expected to be preserved.
-  movs r0, #0@ return UNW_ESUCCESS
-#else
   mov r0, #0 @ return UNW_ESUCCESS
 #endif
   JMP(lr)
Index: src/UnwindRegistersRestore.S
===
--- src/UnwindRegistersRestore.S
+++ src/UnwindRegistersRestore.S
@@ -322,9 +322,18 @@
 @
   .p2align 2
 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm20restoreCoreAndJumpToEv)
-#if !defined(__ARM_ARCH_ISA_ARM)
-  ldr r2, [r0, #52]
-  ldr r3, [r0, #60]
+#if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
+  @ r8-r11: ldm into r1-r4, then mov to r8-r11
+  add r0, #0x20
+  ldm r0!, {r1-r4}
+  sub r0, #0x30
+  mov r8, r1
+  mov r9, r2
+  mov r10, r3
+  mov r11, r4
+  @ r12 does not need loading, it it the intra-procedure-call 

Re: [PATCH] D22292: [libunwind] Fix unw_getcontext for ARMv6-m

[Oliver Stannard via cfe-commits]

olista01 updated this revision to Diff 64318.

https://reviews.llvm.org/D22292

Files:
  src/UnwindRegistersRestore.S
  src/UnwindRegistersSave.S

Index: src/UnwindRegistersSave.S
===
--- src/UnwindRegistersSave.S
+++ src/UnwindRegistersSave.S
@@ -309,28 +309,32 @@
 @
   .p2align 2
 DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
-#if !defined(__ARM_ARCH_ISA_ARM)
-  stm r0, {r0-r7}
+#if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
+  stm r0!, {r0-r7}
+  mov r1, r8
+  mov r2, r9
+  mov r3, r10
+  stm r0!, {r1-r3}
+  mov r1, r11
+  mov r2, r12
+  stm r0!, {r1-r2}
   mov r2, sp
   mov r3, lr
-  str r2, [r0, #52]
-  str r3, [r0, #56]
-  str r3, [r0, #60]  @ store return address as pc
+  str r2, [r0, #0]
+  str r3, [r0, #4]
+  str r3, [r0, #8]  @ store return address as pc
+  @ T1 does not have a non-cpsr-clobbering register-zeroing instruction.
+  @ It is safe to use here though because we are about to return, and cpsr is
+  @ not expected to be preserved.
+  movs r0, #0@ return UNW_ESUCCESS
 #else
   @ 32bit thumb-2 restrictions for stm:
   @ . the sp (r13) cannot be in the list
   @ . the pc (r15) cannot be in the list in an STM instruction
   stm r0, {r0-r12}
   str sp, [r0, #52]
   str lr, [r0, #56]
   str lr, [r0, #60]  @ store return address as pc
-#endif
-#if __ARM_ARCH_ISA_THUMB == 1
-  @ T1 does not have a non-cpsr-clobbering register-zeroing instruction.
-  @ It is safe to use here though because we are about to return, and cpsr is
-  @ not expected to be preserved.
-  movs r0, #0@ return UNW_ESUCCESS
-#else
   mov r0, #0 @ return UNW_ESUCCESS
 #endif
   JMP(lr)
Index: src/UnwindRegistersRestore.S
===
--- src/UnwindRegistersRestore.S
+++ src/UnwindRegistersRestore.S
@@ -322,9 +322,20 @@
 @
   .p2align 2
 
DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm20restoreCoreAndJumpToEv)
-#if !defined(__ARM_ARCH_ISA_ARM)
-  ldr r2, [r0, #52]
-  ldr r3, [r0, #60]
+#if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
+  @ r8-r12: ldr into r1-r5, then mov to r8-r12
+  ldr r1, [r0, #0x20]
+  ldr r2, [r0, #0x24]
+  ldr r3, [r0, #0x28]
+  ldr r4, [r0, #0x2c]
+  ldr r5, [r0, #0x30]
+  mov r8, r1
+  mov r9, r2
+  mov r10, r3
+  mov r11, r4
+  mov r12, r5
+  ldr r2, [r0, #0x34]
+  ldr r3, [r0, #0x3c]
   mov sp, r2
   mov lr, r3 @ restore pc into lr
   ldm r0, {r0-r7}


Index: src/UnwindRegistersSave.S
===
--- src/UnwindRegistersSave.S
+++ src/UnwindRegistersSave.S
@@ -309,28 +309,32 @@
 @
   .p2align 2
 DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
-#if !defined(__ARM_ARCH_ISA_ARM)
-  stm r0, {r0-r7}
+#if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
+  stm r0!, {r0-r7}
+  mov r1, r8
+  mov r2, r9
+  mov r3, r10
+  stm r0!, {r1-r3}
+  mov r1, r11
+  mov r2, r12
+  stm r0!, {r1-r2}
   mov r2, sp
   mov r3, lr
-  str r2, [r0, #52]
-  str r3, [r0, #56]
-  str r3, [r0, #60]  @ store return address as pc
+  str r2, [r0, #0]
+  str r3, [r0, #4]
+  str r3, [r0, #8]  @ store return address as pc
+  @ T1 does not have a non-cpsr-clobbering register-zeroing instruction.
+  @ It is safe to use here though because we are about to return, and cpsr is
+  @ not expected to be preserved.
+  movs r0, #0@ return UNW_ESUCCESS
 #else
   @ 32bit thumb-2 restrictions for stm:
   @ . the sp (r13) cannot be in the list
   @ . the pc (r15) cannot be in the list in an STM instruction
   stm r0, {r0-r12}
   str sp, [r0, #52]
   str lr, [r0, #56]
   str lr, [r0, #60]  @ store return address as pc
-#endif
-#if __ARM_ARCH_ISA_THUMB == 1
-  @ T1 does not have a non-cpsr-clobbering register-zeroing instruction.
-  @ It is safe to use here though because we are about to return, and cpsr is
-  @ not expected to be preserved.
-  movs r0, #0@ return UNW_ESUCCESS
-#else
   mov r0, #0 @ return UNW_ESUCCESS
 #endif
   JMP(lr)
Index: src/UnwindRegistersRestore.S
===
--- src/UnwindRegistersRestore.S
+++ src/UnwindRegistersRestore.S
@@ -322,9 +322,20 @@
 @
   .p2align 2
 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm20restoreCoreAndJumpToEv)
-#if !defined(__ARM_ARCH_ISA_ARM)
-  ldr r2, [r0, #52]
-  ldr r3, [r0, #60]
+#if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
+  @ r8-r12: ldr into r1-r5, then mov to r8-r12
+  ldr r1, [r0, #0x20]
+  ldr r2, [r0, #0x24]
+  ldr r3, [r0, #0x28]
+  ldr r4, [r0, #0x2c]
+  ldr r5, [r0, #0x30]
+  mov r8, r1
+  mov r9, r2
+  mov r10, r3
+  mov r11, r4
+  mov r12, r5
+  ldr r2, [r0, #0x34]
+  ldr r3, [r0, #0x3c]
   mov sp, r2
   mov lr, r3 @ restore pc into lr
   ldm r0, {r0-r7}
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Re: [PATCH] D18138: Add -fnative-half-arguments-and-returns

[Oliver Stannard via cfe-commits]

olista01 accepted this revision.
olista01 added a comment.
This revision is now accepted and ready to land.

LGTM


http://reviews.llvm.org/D18138



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r260533 - [ARM] Add command-line options for ARMv8.2-A

[Oliver Stannard via cfe-commits]

Author: olista01
Date: Thu Feb 11 10:05:52 2016
New Revision: 260533

URL: http://llvm.org/viewvc/llvm-project?rev=260533=rev
Log:
[ARM] Add command-line options for ARMv8.2-A

This allows ARMv8.2-A to be targeted either by using "armv8.2a" in the
triple, or by using -march=armv8.2-a (or the alias -march=armv8.2a).

The FP16 extension can be enabled with the "+fp16" suffix to the -march
or -mcpu option. This is consistent with the AArch64 option, rather than
the usual ARM option of -mfpu. We have agreed with the team which will
be upstreaming this to GCC that we want to use this new option format
for new architecture extensions for both ARM and AArch64.

Most of the work for this was done by the TargetParser patch in llvm.

Differential Revision: http://reviews.llvm.org/D15040


Modified:
cfe/trunk/lib/Basic/Targets.cpp
cfe/trunk/lib/Driver/Tools.cpp
cfe/trunk/test/Driver/arm-cortex-cpus.c
cfe/trunk/test/Preprocessor/arm-target-features.c

Modified: cfe/trunk/lib/Basic/Targets.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=260533=260532=260533=diff
==
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Thu Feb 11 10:05:52 2016
@@ -4473,6 +4473,8 @@ class ARMTargetInfo : public TargetInfo
   return "8A";
 case llvm::ARM::AK_ARMV8_1A:
   return "8_1A";
+case llvm::ARM::AK_ARMV8_2A:
+  return "8_2A";
 }
   }
 

Modified: cfe/trunk/lib/Driver/Tools.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/Tools.cpp?rev=260533=260532=260533=diff
==
--- cfe/trunk/lib/Driver/Tools.cpp (original)
+++ cfe/trunk/lib/Driver/Tools.cpp Thu Feb 11 10:05:52 2016
@@ -880,10 +880,6 @@ static void getARMTargetFeatures(const T
   Features.push_back("-crc");
   }
 
-  if (Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v8_1a) {
-Features.insert(Features.begin(), "+v8.1a");
-  }
-
   // Look for the last occurrence of -mlong-calls or -mno-long-calls. If
   // neither options are specified, see if we are compiling for kernel/kext and
   // decide whether to pass "+long-calls" based on the OS and its version.

Modified: cfe/trunk/test/Driver/arm-cortex-cpus.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/arm-cortex-cpus.c?rev=260533=260532=260533=diff
==
--- cfe/trunk/test/Driver/arm-cortex-cpus.c (original)
+++ cfe/trunk/test/Driver/arm-cortex-cpus.c Thu Feb 11 10:05:52 2016
@@ -204,7 +204,7 @@
 // RUN: %clang -mcpu=generic -target armv8.1a -mlittle-endian -### -c %s 2>&1 
| FileCheck -check-prefix=CHECK-V81A %s
 // RUN: %clang -mcpu=generic -target arm -march=armv8.1a -mlittle-endian -### 
-c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
 // RUN: %clang -mcpu=generic -target arm -mlittle-endian -march=armv8.1-a 
-mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
-// CHECK-V81A: "-cc1"{{.*}} "-triple" "armv8.1a-{{.*}}" "-target-cpu" 
"generic" "-target-feature" "+v8.1a"
+// CHECK-V81A: "-cc1"{{.*}} "-triple" "armv8.1a-{{.*}}" "-target-cpu" "generic"
 
 // RUN: %clang -target armebv8.1a -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-BE-V81A %s
 // RUN: %clang -target armeb -march=armebv8.1a -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-BE-V81A %s
@@ -212,7 +212,7 @@
 // RUN: %clang -target armv8.1a -mbig-endian -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-BE-V81A %s
 // RUN: %clang -target arm -march=armebv8.1a -mbig-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-BE-V81A %s
 // RUN: %clang -target arm -march=armebv8.1-a -mbig-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-BE-V81A %s
-// CHECK-BE-V81A: "-cc1"{{.*}} "-triple" "armebv8.1a-{{.*}}" "-target-cpu" 
"generic" "-target-feature" "+v8.1a"
+// CHECK-BE-V81A: "-cc1"{{.*}} "-triple" "armebv8.1a-{{.*}}" "-target-cpu" 
"generic"
 
 // RUN: %clang -target armv8.1a -mthumb -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-V81A-THUMB %s
 // RUN: %clang -target arm -march=armv8.1a -mthumb -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-V81A-THUMB %s
@@ -220,7 +220,7 @@
 // RUN: %clang -target armv8.1a -mlittle-endian -mthumb -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-V81A-THUMB %s
 // RUN: %clang -target arm -march=armv8.1a -mlittle-endian -mthumb -### -c %s 
2>&1 | FileCheck -check-prefix=CHECK-V81A-THUMB %s
 // RUN: %clang -target arm -march=armv8.1-a -mlittle-endian -mthumb -### -c %s 
2>&1 | FileCheck -check-prefix=CHECK-V81A-THUMB %s
-// CHECK-V81A-THUMB: "-cc1"{{.*}} "-triple" "thumbv8.1a-{{.*}}" "-target-cpu" 
"generic" "-target-feature" "+v8.1a"
+// CHECK-V81A-THUMB: "-cc1"{{.*}} "-triple" "thumbv8.1a-{{.*}}" "-target-cpu" 
"generic"
 
 // RUN: %clang -target armebv8.1a -mthumb -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-BE-V81A-THUMB %s
 

Re: [PATCH] D15040: [ARM] Add command-line options for ARMv8.2-A

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r259499 - Add backend dignostic printer for unsupported features

[Oliver Stannard via cfe-commits]

Author: olista01
Date: Tue Feb  2 07:52:52 2016
New Revision: 259499

URL: http://llvm.org/viewvc/llvm-project?rev=259499=rev
Log:
Add backend dignostic printer for unsupported features

Re-commit of r258950 after fixing layering violation.

The related LLVM patch adds a backend diagnostic type for reporting
unsupported features, this adds a printer for them to clang.

In the case where debug location information is not available, I've
changed the printer to report the location as the first line of the
function, rather than the closing brace, as the latter does not give the
user any information. This also affects optimisation remarks.


Added:
cfe/trunk/test/CodeGen/backend-unsupported-error.ll
Modified:
cfe/trunk/include/clang/Basic/DiagnosticFrontendKinds.td
cfe/trunk/lib/CodeGen/CodeGenAction.cpp
cfe/trunk/test/Frontend/optimization-remark-analysis.c
cfe/trunk/test/Misc/backend-optimization-failure-nodbg.cpp

Modified: cfe/trunk/include/clang/Basic/DiagnosticFrontendKinds.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/DiagnosticFrontendKinds.td?rev=259499=259498=259499=diff
==
--- cfe/trunk/include/clang/Basic/DiagnosticFrontendKinds.td (original)
+++ cfe/trunk/include/clang/Basic/DiagnosticFrontendKinds.td Tue Feb  2 
07:52:52 2016
@@ -58,8 +58,10 @@ def remark_fe_backend_optimization_remar
 BackendInfo, InGroup;
 def warn_fe_backend_optimization_failure : Warning<"%0">, BackendInfo,
 InGroup, DefaultWarn;
-def note_fe_backend_optimization_remark_invalid_loc : Note<"could "
-  "not determine the original source location for %0:%1:%2">;
+def note_fe_backend_invalid_loc : Note<"could "
+  "not determine the original source location for %0:%1:%2">, BackendInfo;
+
+def err_fe_backend_unsupported : Error<"%0">, BackendInfo;
 
 def remark_sanitize_address_insert_extra_padding_accepted : Remark<
 "-fsanitize-address-field-padding applied to %0">, ShowInSystemHeader,

Modified: cfe/trunk/lib/CodeGen/CodeGenAction.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CodeGenAction.cpp?rev=259499=259498=259499=diff
==
--- cfe/trunk/lib/CodeGen/CodeGenAction.cpp (original)
+++ cfe/trunk/lib/CodeGen/CodeGenAction.cpp Tue Feb  2 07:52:52 2016
@@ -242,6 +242,13 @@ namespace clang {
   ((BackendConsumer *)Context)->DiagnosticHandlerImpl(DI);
 }
 
+/// Get the best possible source location to represent a diagnostic that
+/// may have associated debug info.
+const FullSourceLoc
+getBestLocationFromDebugLoc(const llvm::DiagnosticInfoWithDebugLocBase ,
+bool , StringRef ,
+unsigned , unsigned ) const;
+
 void InlineAsmDiagHandler2(const llvm::SMDiagnostic &,
SourceLocation LocCookie);
 
@@ -254,6 +261,8 @@ namespace clang {
 /// \return True if the diagnostic has been successfully reported, false
 /// otherwise.
 bool StackSizeDiagHandler(const llvm::DiagnosticInfoStackSize );
+/// \brief Specialized handler for unsupported backend feature diagnostic.
+void UnsupportedDiagHandler(const llvm::DiagnosticInfoUnsupported );
 /// \brief Specialized handlers for optimization remarks.
 /// Note that these handlers only accept remarks and they always handle
 /// them.
@@ -439,16 +448,11 @@ BackendConsumer::StackSizeDiagHandler(co
   return false;
 }
 
-void BackendConsumer::EmitOptimizationMessage(
-const llvm::DiagnosticInfoOptimizationBase , unsigned DiagID) {
-  // We only support warnings and remarks.
-  assert(D.getSeverity() == llvm::DS_Remark ||
- D.getSeverity() == llvm::DS_Warning);
-
+const FullSourceLoc BackendConsumer::getBestLocationFromDebugLoc(
+const llvm::DiagnosticInfoWithDebugLocBase , bool , 
StringRef ,
+unsigned , unsigned ) const {
   SourceManager  = Context->getSourceManager();
   FileManager  = SourceMgr.getFileManager();
-  StringRef Filename;
-  unsigned Line, Column;
   SourceLocation DILoc;
 
   if (D.isLocationAvailable()) {
@@ -459,6 +463,7 @@ void BackendConsumer::EmitOptimizationMe
   // source manager, so pass 1 if Column is not set.
   DILoc = SourceMgr.translateFileLineCol(FE, Line, Column ? Column : 1);
 }
+BadDebugInfo = DILoc.isInvalid();
   }
 
   // If a location isn't available, try to approximate it using the associated
@@ -467,18 +472,63 @@ void BackendConsumer::EmitOptimizationMe
   FullSourceLoc Loc(DILoc, SourceMgr);
   if (Loc.isInvalid())
 if (const Decl *FD = Gen->GetDeclForMangledName(D.getFunction().getName()))
-  Loc = FD->getASTContext().getFullLoc(FD->getBodyRBrace());
+  Loc = FD->getASTContext().getFullLoc(FD->getLocation());
+
+  if (DILoc.isInvalid() && D.isLocationAvailable())
+// If we were not able to translate 

Re: [PATCH] D15040: [ARM] Add command-line options for ARMv8.2-A

[Oliver Stannard via cfe-commits]

olista01 added a comment.

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r259043 - Revert r259036, it introduces a cyclic library dependency

[Oliver Stannard via cfe-commits]

Author: olista01
Date: Thu Jan 28 07:09:49 2016
New Revision: 259043

URL: http://llvm.org/viewvc/llvm-project?rev=259043=rev
Log:
Revert r259036, it introduces a cyclic library dependency

Removed:
cfe/trunk/test/CodeGen/backend-unsupported-error.ll
Modified:
cfe/trunk/include/clang/Basic/DiagnosticFrontendKinds.td
cfe/trunk/lib/CodeGen/CodeGenAction.cpp
cfe/trunk/test/Frontend/optimization-remark-analysis.c
cfe/trunk/test/Misc/backend-optimization-failure-nodbg.cpp

Modified: cfe/trunk/include/clang/Basic/DiagnosticFrontendKinds.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/DiagnosticFrontendKinds.td?rev=259043=259042=259043=diff
==
--- cfe/trunk/include/clang/Basic/DiagnosticFrontendKinds.td (original)
+++ cfe/trunk/include/clang/Basic/DiagnosticFrontendKinds.td Thu Jan 28 
07:09:49 2016
@@ -58,10 +58,8 @@ def remark_fe_backend_optimization_remar
 BackendInfo, InGroup;
 def warn_fe_backend_optimization_failure : Warning<"%0">, BackendInfo,
 InGroup, DefaultWarn;
-def note_fe_backend_invalid_loc : Note<"could "
-  "not determine the original source location for %0:%1:%2">, BackendInfo;
-
-def err_fe_backend_unsupported : Error<"%0">, BackendInfo;
+def note_fe_backend_optimization_remark_invalid_loc : Note<"could "
+  "not determine the original source location for %0:%1:%2">;
 
 def remark_sanitize_address_insert_extra_padding_accepted : Remark<
 "-fsanitize-address-field-padding applied to %0">, ShowInSystemHeader,

Modified: cfe/trunk/lib/CodeGen/CodeGenAction.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CodeGenAction.cpp?rev=259043=259042=259043=diff
==
--- cfe/trunk/lib/CodeGen/CodeGenAction.cpp (original)
+++ cfe/trunk/lib/CodeGen/CodeGenAction.cpp Thu Jan 28 07:09:49 2016
@@ -23,7 +23,6 @@
 #include "clang/Lex/Preprocessor.h"
 #include "llvm/ADT/SmallString.h"
 #include "llvm/Bitcode/ReaderWriter.h"
-#include "llvm/CodeGen/DiagnosticInfoCodeGen.h"
 #include "llvm/IR/DebugInfo.h"
 #include "llvm/IR/DiagnosticInfo.h"
 #include "llvm/IR/DiagnosticPrinter.h"
@@ -243,13 +242,6 @@ namespace clang {
   ((BackendConsumer *)Context)->DiagnosticHandlerImpl(DI);
 }
 
-/// Get the best possible source location to represent a diagnostic that
-/// may have associated debug info.
-const FullSourceLoc
-getBestLocationFromDebugLoc(const llvm::DiagnosticInfoWithDebugLocBase ,
-bool , StringRef ,
-unsigned , unsigned ) const;
-
 void InlineAsmDiagHandler2(const llvm::SMDiagnostic &,
SourceLocation LocCookie);
 
@@ -262,8 +254,6 @@ namespace clang {
 /// \return True if the diagnostic has been successfully reported, false
 /// otherwise.
 bool StackSizeDiagHandler(const llvm::DiagnosticInfoStackSize );
-/// \brief Specialized handler for unsupported backend feature diagnostic.
-void UnsupportedDiagHandler(const llvm::DiagnosticInfoUnsupported );
 /// \brief Specialized handlers for optimization remarks.
 /// Note that these handlers only accept remarks and they always handle
 /// them.
@@ -449,11 +439,16 @@ BackendConsumer::StackSizeDiagHandler(co
   return false;
 }
 
-const FullSourceLoc BackendConsumer::getBestLocationFromDebugLoc(
-const llvm::DiagnosticInfoWithDebugLocBase , bool , 
StringRef ,
-unsigned , unsigned ) const {
+void BackendConsumer::EmitOptimizationMessage(
+const llvm::DiagnosticInfoOptimizationBase , unsigned DiagID) {
+  // We only support warnings and remarks.
+  assert(D.getSeverity() == llvm::DS_Remark ||
+ D.getSeverity() == llvm::DS_Warning);
+
   SourceManager  = Context->getSourceManager();
   FileManager  = SourceMgr.getFileManager();
+  StringRef Filename;
+  unsigned Line, Column;
   SourceLocation DILoc;
 
   if (D.isLocationAvailable()) {
@@ -464,7 +459,6 @@ const FullSourceLoc BackendConsumer::get
   // source manager, so pass 1 if Column is not set.
   DILoc = SourceMgr.translateFileLineCol(FE, Line, Column ? Column : 1);
 }
-BadDebugInfo = DILoc.isInvalid();
   }
 
   // If a location isn't available, try to approximate it using the associated
@@ -473,63 +467,18 @@ const FullSourceLoc BackendConsumer::get
   FullSourceLoc Loc(DILoc, SourceMgr);
   if (Loc.isInvalid())
 if (const Decl *FD = Gen->GetDeclForMangledName(D.getFunction().getName()))
-  Loc = FD->getASTContext().getFullLoc(FD->getLocation());
-
-  if (DILoc.isInvalid() && D.isLocationAvailable())
-// If we were not able to translate the file:line:col information
-// back to a SourceLocation, at least emit a note stating that
-// we could not translate this location. This can happen in the
-// case of #line directives.
-Diags.Report(Loc, 

r259036 - Add backend dignostic printer for unsupported features

[Oliver Stannard via cfe-commits]

Author: olista01
Date: Thu Jan 28 04:07:34 2016
New Revision: 259036

URL: http://llvm.org/viewvc/llvm-project?rev=259036=rev
Log:
Add backend dignostic printer for unsupported features

Re-commit of r258950 after fixing layering violation.

Add backend dignostic printer for unsupported features

The related LLVM patch adds a backend diagnostic type for reporting
unsupported features, this adds a printer for them to clang.

In the case where debug location information is not available, I've
changed the printer to report the location as the first line of the
function, rather than the closing brace, as the latter does not give the
user any information. This also affects optimisation remarks.

Differential Revision: http://reviews.llvm.org/D16591


Added:
cfe/trunk/test/CodeGen/backend-unsupported-error.ll
Modified:
cfe/trunk/include/clang/Basic/DiagnosticFrontendKinds.td
cfe/trunk/lib/CodeGen/CodeGenAction.cpp
cfe/trunk/test/Frontend/optimization-remark-analysis.c
cfe/trunk/test/Misc/backend-optimization-failure-nodbg.cpp

Modified: cfe/trunk/include/clang/Basic/DiagnosticFrontendKinds.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/DiagnosticFrontendKinds.td?rev=259036=259035=259036=diff
==
--- cfe/trunk/include/clang/Basic/DiagnosticFrontendKinds.td (original)
+++ cfe/trunk/include/clang/Basic/DiagnosticFrontendKinds.td Thu Jan 28 
04:07:34 2016
@@ -58,8 +58,10 @@ def remark_fe_backend_optimization_remar
 BackendInfo, InGroup;
 def warn_fe_backend_optimization_failure : Warning<"%0">, BackendInfo,
 InGroup, DefaultWarn;
-def note_fe_backend_optimization_remark_invalid_loc : Note<"could "
-  "not determine the original source location for %0:%1:%2">;
+def note_fe_backend_invalid_loc : Note<"could "
+  "not determine the original source location for %0:%1:%2">, BackendInfo;
+
+def err_fe_backend_unsupported : Error<"%0">, BackendInfo;
 
 def remark_sanitize_address_insert_extra_padding_accepted : Remark<
 "-fsanitize-address-field-padding applied to %0">, ShowInSystemHeader,

Modified: cfe/trunk/lib/CodeGen/CodeGenAction.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CodeGenAction.cpp?rev=259036=259035=259036=diff
==
--- cfe/trunk/lib/CodeGen/CodeGenAction.cpp (original)
+++ cfe/trunk/lib/CodeGen/CodeGenAction.cpp Thu Jan 28 04:07:34 2016
@@ -23,6 +23,7 @@
 #include "clang/Lex/Preprocessor.h"
 #include "llvm/ADT/SmallString.h"
 #include "llvm/Bitcode/ReaderWriter.h"
+#include "llvm/CodeGen/DiagnosticInfoCodeGen.h"
 #include "llvm/IR/DebugInfo.h"
 #include "llvm/IR/DiagnosticInfo.h"
 #include "llvm/IR/DiagnosticPrinter.h"
@@ -242,6 +243,13 @@ namespace clang {
   ((BackendConsumer *)Context)->DiagnosticHandlerImpl(DI);
 }
 
+/// Get the best possible source location to represent a diagnostic that
+/// may have associated debug info.
+const FullSourceLoc
+getBestLocationFromDebugLoc(const llvm::DiagnosticInfoWithDebugLocBase ,
+bool , StringRef ,
+unsigned , unsigned ) const;
+
 void InlineAsmDiagHandler2(const llvm::SMDiagnostic &,
SourceLocation LocCookie);
 
@@ -254,6 +262,8 @@ namespace clang {
 /// \return True if the diagnostic has been successfully reported, false
 /// otherwise.
 bool StackSizeDiagHandler(const llvm::DiagnosticInfoStackSize );
+/// \brief Specialized handler for unsupported backend feature diagnostic.
+void UnsupportedDiagHandler(const llvm::DiagnosticInfoUnsupported );
 /// \brief Specialized handlers for optimization remarks.
 /// Note that these handlers only accept remarks and they always handle
 /// them.
@@ -439,16 +449,11 @@ BackendConsumer::StackSizeDiagHandler(co
   return false;
 }
 
-void BackendConsumer::EmitOptimizationMessage(
-const llvm::DiagnosticInfoOptimizationBase , unsigned DiagID) {
-  // We only support warnings and remarks.
-  assert(D.getSeverity() == llvm::DS_Remark ||
- D.getSeverity() == llvm::DS_Warning);
-
+const FullSourceLoc BackendConsumer::getBestLocationFromDebugLoc(
+const llvm::DiagnosticInfoWithDebugLocBase , bool , 
StringRef ,
+unsigned , unsigned ) const {
   SourceManager  = Context->getSourceManager();
   FileManager  = SourceMgr.getFileManager();
-  StringRef Filename;
-  unsigned Line, Column;
   SourceLocation DILoc;
 
   if (D.isLocationAvailable()) {
@@ -459,6 +464,7 @@ void BackendConsumer::EmitOptimizationMe
   // source manager, so pass 1 if Column is not set.
   DILoc = SourceMgr.translateFileLineCol(FE, Line, Column ? Column : 1);
 }
+BadDebugInfo = DILoc.isInvalid();
   }
 
   // If a location isn't available, try to approximate it using the associated
@@ -467,18 +473,63 @@ void 

Re: [PATCH] D16591: Add backend dignostic printer for unsupported features

[Oliver Stannard via cfe-commits]

olista01 added a comment.

This was reverted last night, I've re-committed it as r259036 with the layering 
violation fixed.


Repository:
  rL LLVM

http://reviews.llvm.org/D16591



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r258950 - Add backend dignostic printer for unsupported features

[Oliver Stannard via cfe-commits]

Author: olista01
Date: Wed Jan 27 11:30:28 2016
New Revision: 258950

URL: http://llvm.org/viewvc/llvm-project?rev=258950=rev
Log:
Add backend dignostic printer for unsupported features

The related LLVM patch adds a backend diagnostic type for reporting
unsupported features, this adds a printer for them to clang.

In the case where debug location information is not available, I've
changed the printer to report the location as the first line of the
function, rather than the closing brace, as the latter does not give the
user any information. This also affects optimisation remarks.

Differential Revision: http://reviews.llvm.org/D16591


Added:
cfe/trunk/test/CodeGen/backend-unsupported-error.ll
Modified:
cfe/trunk/include/clang/Basic/DiagnosticFrontendKinds.td
cfe/trunk/lib/CodeGen/CodeGenAction.cpp
cfe/trunk/test/Frontend/optimization-remark-analysis.c
cfe/trunk/test/Misc/backend-optimization-failure-nodbg.cpp

Modified: cfe/trunk/include/clang/Basic/DiagnosticFrontendKinds.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/DiagnosticFrontendKinds.td?rev=258950=258949=258950=diff
==
--- cfe/trunk/include/clang/Basic/DiagnosticFrontendKinds.td (original)
+++ cfe/trunk/include/clang/Basic/DiagnosticFrontendKinds.td Wed Jan 27 
11:30:28 2016
@@ -58,8 +58,10 @@ def remark_fe_backend_optimization_remar
 BackendInfo, InGroup;
 def warn_fe_backend_optimization_failure : Warning<"%0">, BackendInfo,
 InGroup, DefaultWarn;
-def note_fe_backend_optimization_remark_invalid_loc : Note<"could "
-  "not determine the original source location for %0:%1:%2">;
+def note_fe_backend_invalid_loc : Note<"could "
+  "not determine the original source location for %0:%1:%2">, BackendInfo;
+
+def err_fe_backend_unsupported : Error<"%0">, BackendInfo;
 
 def remark_sanitize_address_insert_extra_padding_accepted : Remark<
 "-fsanitize-address-field-padding applied to %0">, ShowInSystemHeader,

Modified: cfe/trunk/lib/CodeGen/CodeGenAction.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CodeGenAction.cpp?rev=258950=258949=258950=diff
==
--- cfe/trunk/lib/CodeGen/CodeGenAction.cpp (original)
+++ cfe/trunk/lib/CodeGen/CodeGenAction.cpp Wed Jan 27 11:30:28 2016
@@ -242,6 +242,13 @@ namespace clang {
   ((BackendConsumer *)Context)->DiagnosticHandlerImpl(DI);
 }
 
+/// Get the best possible source location to represent a diagnostic that
+/// may have associated debug info.
+const FullSourceLoc
+getBestLocationFromDebugLoc(const llvm::DiagnosticInfoWithDebugLocBase ,
+bool , StringRef ,
+unsigned , unsigned ) const;
+
 void InlineAsmDiagHandler2(const llvm::SMDiagnostic &,
SourceLocation LocCookie);
 
@@ -254,6 +261,8 @@ namespace clang {
 /// \return True if the diagnostic has been successfully reported, false
 /// otherwise.
 bool StackSizeDiagHandler(const llvm::DiagnosticInfoStackSize );
+/// \brief Specialized handler for unsupported backend feature diagnostic.
+void UnsupportedDiagHandler(const llvm::DiagnosticInfoUnsupported );
 /// \brief Specialized handlers for optimization remarks.
 /// Note that these handlers only accept remarks and they always handle
 /// them.
@@ -439,16 +448,11 @@ BackendConsumer::StackSizeDiagHandler(co
   return false;
 }
 
-void BackendConsumer::EmitOptimizationMessage(
-const llvm::DiagnosticInfoOptimizationBase , unsigned DiagID) {
-  // We only support warnings and remarks.
-  assert(D.getSeverity() == llvm::DS_Remark ||
- D.getSeverity() == llvm::DS_Warning);
-
+const FullSourceLoc BackendConsumer::getBestLocationFromDebugLoc(
+const llvm::DiagnosticInfoWithDebugLocBase , bool , 
StringRef ,
+unsigned , unsigned ) const {
   SourceManager  = Context->getSourceManager();
   FileManager  = SourceMgr.getFileManager();
-  StringRef Filename;
-  unsigned Line, Column;
   SourceLocation DILoc;
 
   if (D.isLocationAvailable()) {
@@ -459,6 +463,7 @@ void BackendConsumer::EmitOptimizationMe
   // source manager, so pass 1 if Column is not set.
   DILoc = SourceMgr.translateFileLineCol(FE, Line, Column ? Column : 1);
 }
+BadDebugInfo = DILoc.isInvalid();
   }
 
   // If a location isn't available, try to approximate it using the associated
@@ -467,18 +472,63 @@ void BackendConsumer::EmitOptimizationMe
   FullSourceLoc Loc(DILoc, SourceMgr);
   if (Loc.isInvalid())
 if (const Decl *FD = Gen->GetDeclForMangledName(D.getFunction().getName()))
-  Loc = FD->getASTContext().getFullLoc(FD->getBodyRBrace());
+  Loc = FD->getASTContext().getFullLoc(FD->getLocation());
+
+  if (DILoc.isInvalid() && D.isLocationAvailable())
+// If we were not able to translate 

Re: [PATCH] D16591: Add backend dignostic printer for unsupported features

[Oliver Stannard via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL258950: Add backend dignostic printer for unsupported 
features (authored by olista01).

Changed prior to commit:
  http://reviews.llvm.org/D16591?vs=46127=46144#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D16591

Files:
  cfe/trunk/include/clang/Basic/DiagnosticFrontendKinds.td
  cfe/trunk/lib/CodeGen/CodeGenAction.cpp
  cfe/trunk/test/CodeGen/backend-unsupported-error.ll
  cfe/trunk/test/Frontend/optimization-remark-analysis.c
  cfe/trunk/test/Misc/backend-optimization-failure-nodbg.cpp

Index: cfe/trunk/lib/CodeGen/CodeGenAction.cpp
===
--- cfe/trunk/lib/CodeGen/CodeGenAction.cpp
+++ cfe/trunk/lib/CodeGen/CodeGenAction.cpp
@@ -242,6 +242,13 @@
   ((BackendConsumer *)Context)->DiagnosticHandlerImpl(DI);
 }
 
+/// Get the best possible source location to represent a diagnostic that
+/// may have associated debug info.
+const FullSourceLoc
+getBestLocationFromDebugLoc(const llvm::DiagnosticInfoWithDebugLocBase ,
+bool , StringRef ,
+unsigned , unsigned ) const;
+
 void InlineAsmDiagHandler2(const llvm::SMDiagnostic &,
SourceLocation LocCookie);
 
@@ -254,6 +261,8 @@
 /// \return True if the diagnostic has been successfully reported, false
 /// otherwise.
 bool StackSizeDiagHandler(const llvm::DiagnosticInfoStackSize );
+/// \brief Specialized handler for unsupported backend feature diagnostic.
+void UnsupportedDiagHandler(const llvm::DiagnosticInfoUnsupported );
 /// \brief Specialized handlers for optimization remarks.
 /// Note that these handlers only accept remarks and they always handle
 /// them.
@@ -439,16 +448,11 @@
   return false;
 }
 
-void BackendConsumer::EmitOptimizationMessage(
-const llvm::DiagnosticInfoOptimizationBase , unsigned DiagID) {
-  // We only support warnings and remarks.
-  assert(D.getSeverity() == llvm::DS_Remark ||
- D.getSeverity() == llvm::DS_Warning);
-
+const FullSourceLoc BackendConsumer::getBestLocationFromDebugLoc(
+const llvm::DiagnosticInfoWithDebugLocBase , bool , StringRef ,
+unsigned , unsigned ) const {
   SourceManager  = Context->getSourceManager();
   FileManager  = SourceMgr.getFileManager();
-  StringRef Filename;
-  unsigned Line, Column;
   SourceLocation DILoc;
 
   if (D.isLocationAvailable()) {
@@ -459,26 +463,72 @@
   // source manager, so pass 1 if Column is not set.
   DILoc = SourceMgr.translateFileLineCol(FE, Line, Column ? Column : 1);
 }
+BadDebugInfo = DILoc.isInvalid();
   }
 
   // If a location isn't available, try to approximate it using the associated
   // function definition. We use the definition's right brace to differentiate
   // from diagnostics that genuinely relate to the function itself.
   FullSourceLoc Loc(DILoc, SourceMgr);
   if (Loc.isInvalid())
 if (const Decl *FD = Gen->GetDeclForMangledName(D.getFunction().getName()))
-  Loc = FD->getASTContext().getFullLoc(FD->getBodyRBrace());
+  Loc = FD->getASTContext().getFullLoc(FD->getLocation());
+
+  if (DILoc.isInvalid() && D.isLocationAvailable())
+// If we were not able to translate the file:line:col information
+// back to a SourceLocation, at least emit a note stating that
+// we could not translate this location. This can happen in the
+// case of #line directives.
+Diags.Report(Loc, diag::note_fe_backend_invalid_loc)
+<< Filename << Line;
+
+  return Loc;
+}
+
+void BackendConsumer::UnsupportedDiagHandler(
+const llvm::DiagnosticInfoUnsupported ) {
+  // We only support errors.
+  assert(D.getSeverity() == llvm::DS_Error);
+
+  StringRef Filename;
+  unsigned Line, Column;
+  bool BadDebugInfo;
+  FullSourceLoc Loc = getBestLocationFromDebugLoc(D, BadDebugInfo, Filename,
+  Line, Column);
+
+  Diags.Report(Loc, diag::err_fe_backend_unsupported) << D.getMessage().str();
+
+  if (BadDebugInfo)
+// If we were not able to translate the file:line:col information
+// back to a SourceLocation, at least emit a note stating that
+// we could not translate this location. This can happen in the
+// case of #line directives.
+Diags.Report(Loc, diag::note_fe_backend_invalid_loc)
+<< Filename << Line << Column;
+}
+
+void BackendConsumer::EmitOptimizationMessage(
+const llvm::DiagnosticInfoOptimizationBase , unsigned DiagID) {
+  // We only support warnings and remarks.
+  assert(D.getSeverity() == llvm::DS_Remark ||
+ D.getSeverity() == llvm::DS_Warning);
+
+  StringRef Filename;
+  unsigned Line, Column;
+  bool BadDebugInfo = false;
+  FullSourceLoc Loc = getBestLocationFromDebugLoc(D, BadDebugInfo, Filename,
+  Line, Column);
 
   Diags.Report(Loc, DiagID)
   << AddFlagValue(D.getPassName() ? D.getPassName() : 

Re: [PATCH] D16591: Add backend dignostic printer for unsupported features

[Oliver Stannard via cfe-commits]

olista01 removed rL LLVM as the repository for this revision.
olista01 updated this revision to Diff 46127.
olista01 added a comment.

Added a test for the new diagnostic printer.


http://reviews.llvm.org/D16591

Files:
  include/clang/Basic/DiagnosticFrontendKinds.td
  lib/CodeGen/CodeGenAction.cpp
  test/CodeGen/backend-unsupported-error.ll
  test/Frontend/optimization-remark-analysis.c
  test/Misc/backend-optimization-failure-nodbg.cpp

Index: test/Misc/backend-optimization-failure-nodbg.cpp
===
--- test/Misc/backend-optimization-failure-nodbg.cpp
+++ test/Misc/backend-optimization-failure-nodbg.cpp
@@ -4,7 +4,7 @@
 // Test verifies optimization failures generated by the backend are handled
 // correctly by clang. LLVM tests verify all of the failure conditions.
 
-void test_switch(int *A, int *B, int Length) {
+void test_switch(int *A, int *B, int Length) { /* expected-warning {{loop not vectorized: failed explicitly specified loop vectorization}} */
 #pragma clang loop vectorize(enable) unroll(disable)
   for (int i = 0; i < Length; i++) {
 switch (A[i]) {
@@ -18,4 +18,4 @@
   B[i] = 3;
 }
   }
-/* expected-warning {{loop not vectorized: failed explicitly specified loop vectorization}} */ }
+}
Index: test/Frontend/optimization-remark-analysis.c
===
--- test/Frontend/optimization-remark-analysis.c
+++ test/Frontend/optimization-remark-analysis.c
@@ -1,8 +1,8 @@
 // RUN: %clang -O1 -fvectorize -target x86_64-unknown-unknown -emit-llvm -Rpass-analysis -S %s -o - 2>&1 | FileCheck %s --check-prefix=RPASS
 // RUN: %clang -O1 -fvectorize -target x86_64-unknown-unknown -emit-llvm -S %s -o - 2>&1 | FileCheck %s
 
-// RPASS: {{.*}}:21:1: remark: loop not vectorized: loop contains a switch statement
-// CHECK-NOT: {{.*}}:21:1: remark: loop not vectorized: loop contains a switch statement
+// RPASS: {{.*}}:7:8: remark: loop not vectorized: loop contains a switch statement
+// CHECK-NOT: {{.*}}:7:8: remark: loop not vectorized: loop contains a switch statement
 
 double foo(int N, int *Array) {
   double v = 0.0;
Index: test/CodeGen/backend-unsupported-error.ll
===
--- /dev/null
+++ test/CodeGen/backend-unsupported-error.ll
@@ -0,0 +1,45 @@
+; RUN: not %clang_cc1 -triple r600-unknown-unknown -S -o - %s 2>&1 | FileCheck %s
+; REQUIRES: amdgpu-registered-target
+
+; This is to check that backend errors for unsupported features are formatted correctly
+
+; CHECK: error: test.c:2:20: in function bar i32 (): unsupported call to function foo.2
+
+target triple = "r600-unknown-unknown"
+
+; Function Attrs: nounwind uwtable
+define i32 @bar() #0 !dbg !4 {
+entry:
+  %call = call i32 @foo(), !dbg !12
+  ret i32 %call, !dbg !13
+}
+
+; Function Attrs: nounwind uwtable
+define i32 @foo() #0 !dbg !8 {
+entry:
+  %call = call i32 @bar(), !dbg !14
+  ret i32 %call, !dbg !15
+}
+
+attributes #0 = { nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!9, !10}
+!llvm.ident = !{!11}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.9.0", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, subprograms: !3)
+!1 = !DIFile(filename: "test.c", directory: "")
+!2 = !{}
+!3 = !{!4, !8}
+!4 = distinct !DISubprogram(name: "bar", scope: !1, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true, scopeLine: 2, isOptimized: false, variables: !2)
+!5 = !DISubroutineType(types: !6)
+!6 = !{!7}
+!7 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!8 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 3, type: !5, isLocal: false, isDefinition: true, scopeLine: 3, flags: DIFlagPrototyped, isOptimized: false, variables: !2)
+!9 = !{i32 2, !"Dwarf Version", i32 4}
+!10 = !{i32 2, !"Debug Info Version", i32 3}
+!11 = !{!"clang version 3.9.0"}
+!12 = !DILocation(line: 2, column: 20, scope: !4)
+!13 = !DILocation(line: 2, column: 13, scope: !4)
+!14 = !DILocation(line: 3, column: 20, scope: !8)
+!15 = !DILocation(line: 3, column: 13, scope: !8)
Index: lib/CodeGen/CodeGenAction.cpp
===
--- lib/CodeGen/CodeGenAction.cpp
+++ lib/CodeGen/CodeGenAction.cpp
@@ -238,6 +238,13 @@
   ((BackendConsumer *)Context)->DiagnosticHandlerImpl(DI);
 }
 
+/// Get the best possible source location to represent a diagnostic that
+/// may have associated debug info.
+const FullSourceLoc
+getBestLocationFromDebugLoc(const llvm::DiagnosticInfoWithDebugLocBase ,
+bool , StringRef ,
+ 

[PATCH] D16591: Add backend dignostic printer for unsupported features

[Oliver Stannard via cfe-commits]

olista01 created this revision.
olista01 added reviewers: ast, sunfish, tstellarAMD.
olista01 added a subscriber: cfe-commits.
olista01 set the repository for this revision to rL LLVM.

The related LLVM patch adds a backend diagnostic type for reporting
unsupported features, this adds a printer for them to clang.

In the case where debug location information is not available, I've
changed the printer to report the location as the first line of the
function, rather than the closing brace, as the latter does not give the
user any information. This also affects optimisation remarks.

Repository:
  rL LLVM

http://reviews.llvm.org/D16591

Files:
  include/clang/Basic/DiagnosticFrontendKinds.td
  lib/CodeGen/CodeGenAction.cpp
  test/Frontend/optimization-remark-analysis.c
  test/Misc/backend-optimization-failure-nodbg.cpp

Index: test/Misc/backend-optimization-failure-nodbg.cpp
===
--- test/Misc/backend-optimization-failure-nodbg.cpp
+++ test/Misc/backend-optimization-failure-nodbg.cpp
@@ -4,7 +4,7 @@
 // Test verifies optimization failures generated by the backend are handled
 // correctly by clang. LLVM tests verify all of the failure conditions.
 
-void test_switch(int *A, int *B, int Length) {
+void test_switch(int *A, int *B, int Length) { /* expected-warning {{loop not vectorized: failed explicitly specified loop vectorization}} */
 #pragma clang loop vectorize(enable) unroll(disable)
   for (int i = 0; i < Length; i++) {
 switch (A[i]) {
@@ -18,4 +18,4 @@
   B[i] = 3;
 }
   }
-/* expected-warning {{loop not vectorized: failed explicitly specified loop vectorization}} */ }
+}
Index: test/Frontend/optimization-remark-analysis.c
===
--- test/Frontend/optimization-remark-analysis.c
+++ test/Frontend/optimization-remark-analysis.c
@@ -1,8 +1,8 @@
 // RUN: %clang -O1 -fvectorize -target x86_64-unknown-unknown -emit-llvm -Rpass-analysis -S %s -o - 2>&1 | FileCheck %s --check-prefix=RPASS
 // RUN: %clang -O1 -fvectorize -target x86_64-unknown-unknown -emit-llvm -S %s -o - 2>&1 | FileCheck %s
 
-// RPASS: {{.*}}:21:1: remark: loop not vectorized: loop contains a switch statement
-// CHECK-NOT: {{.*}}:21:1: remark: loop not vectorized: loop contains a switch statement
+// RPASS: {{.*}}:7:8: remark: loop not vectorized: loop contains a switch statement
+// CHECK-NOT: {{.*}}:7:8: remark: loop not vectorized: loop contains a switch statement
 
 double foo(int N, int *Array) {
   double v = 0.0;
Index: lib/CodeGen/CodeGenAction.cpp
===
--- lib/CodeGen/CodeGenAction.cpp
+++ lib/CodeGen/CodeGenAction.cpp
@@ -238,6 +238,13 @@
   ((BackendConsumer *)Context)->DiagnosticHandlerImpl(DI);
 }
 
+/// Get the best possible source location to represent a diagnostic that
+/// may have associated debug info.
+const FullSourceLoc
+getBestLocationFromDebugLoc(const llvm::DiagnosticInfoWithDebugLocBase ,
+bool , StringRef ,
+unsigned , unsigned ) const;
+
 void InlineAsmDiagHandler2(const llvm::SMDiagnostic &,
SourceLocation LocCookie);
 
@@ -250,6 +257,8 @@
 /// \return True if the diagnostic has been successfully reported, false
 /// otherwise.
 bool StackSizeDiagHandler(const llvm::DiagnosticInfoStackSize );
+/// \brief Specialized handler for unsupported backend feature diagnostic.
+void UnsupportedDiagHandler(const llvm::DiagnosticInfoUnsupported );
 /// \brief Specialized handlers for optimization remarks.
 /// Note that these handlers only accept remarks and they always handle
 /// them.
@@ -435,16 +444,11 @@
   return false;
 }
 
-void BackendConsumer::EmitOptimizationMessage(
-const llvm::DiagnosticInfoOptimizationBase , unsigned DiagID) {
-  // We only support warnings and remarks.
-  assert(D.getSeverity() == llvm::DS_Remark ||
- D.getSeverity() == llvm::DS_Warning);
-
+const FullSourceLoc BackendConsumer::getBestLocationFromDebugLoc(
+const llvm::DiagnosticInfoWithDebugLocBase , bool , StringRef ,
+unsigned , unsigned ) const {
   SourceManager  = Context->getSourceManager();
   FileManager  = SourceMgr.getFileManager();
-  StringRef Filename;
-  unsigned Line, Column;
   SourceLocation DILoc;
 
   if (D.isLocationAvailable()) {
@@ -455,26 +459,72 @@
   // source manager, so pass 1 if Column is not set.
   DILoc = SourceMgr.translateFileLineCol(FE, Line, Column ? Column : 1);
 }
+BadDebugInfo = DILoc.isInvalid();
   }
 
   // If a location isn't available, try to approximate it using the associated
   // function definition. We use the definition's right brace to differentiate
   // from diagnostics that genuinely relate to the function itself.
   FullSourceLoc Loc(DILoc, SourceMgr);
   if 

Re: [PATCH] D15040: [ARM] Add command-line options for ARMv8.2-A

[Oliver Stannard via cfe-commits]

olista01 added a comment.

Ping?


http://reviews.llvm.org/D15040



___
cfe-commits mailing list
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[PATCH] D15040: [ARM] Add command-line options for ARMv8.2-A

[Oliver Stannard via cfe-commits]

olista01 created this revision.
olista01 added reviewers: t.p.northover, ab.
olista01 added a subscriber: cfe-commits.
olista01 set the repository for this revision to rL LLVM.
Herald added subscribers: rengolin, aemerson.

This allows ARMv8.2-A to be targeted either by using "armv8.2a" in the
triple, or by using -march=armv8.2-a (or the alias -march=armv8.2a).

The FP16 extension can be enabled with the "+fp16" suffix to the -march
or -mcpu option. This is consistent with the AArch64 option, rather than
the usual ARM option of -mfpu. We have agreed with the team which will
be upstreaming this to GCC that we want to use this new option format
for new architecture extensions for both ARM and AArch64.

Most of the work for this was done by the TargetParser patch in llvm.

Repository:
  rL LLVM

http://reviews.llvm.org/D15040

Files:
  lib/Basic/Targets.cpp
  lib/Driver/Tools.cpp
  test/Driver/arm-cortex-cpus.c

Index: test/Driver/arm-cortex-cpus.c
===
--- test/Driver/arm-cortex-cpus.c
+++ test/Driver/arm-cortex-cpus.c
@@ -230,6 +230,49 @@
 // RUN: %clang -target arm -march=armebv8.1-a -mbig-endian -mthumb -### -c %s 
2>&1 | FileCheck -check-prefix=CHECK-BE-V81A-THUMB %s
 // CHECK-BE-V81A-THUMB: "-cc1"{{.*}} "-triple" "thumbebv8.1a-{{.*}}" 
"-target-cpu" "generic" "-target-feature" "+v8.1a"
 
+// RUN: %clang -target armv8.2a -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-V82A %s
+// RUN: %clang -target arm -march=armv8.2a -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-V82A %s
+// RUN: %clang -target arm -march=armv8.2-a -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-V82A %s
+// RUN: %clang -target arm -march=armv8.2a -mlittle-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-V82A %s
+// RUN: %clang -target armv8.2a -mlittle-endian -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-V82A %s
+// RUN: %clang -target arm -march=armv8.2a -mlittle-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-V82A %s
+// RUN: %clang -target arm -mlittle-endian -march=armv8.2-a -mlittle-endian 
-### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V82A %s
+// CHECK-V82A: "-cc1"{{.*}} "-triple" "armv8.2{{.*}}" "-target-cpu" "generic" 
"-target-feature" "+v8.2a"
+
+// RUN: %clang -target armebv8.2a -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-BE-V82A %s
+// RUN: %clang -target armv8.2a -mbig-endian -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-BE-V82A %s
+// RUN: %clang -target armeb -march=armebv8.2a -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-BE-V82A %s
+// RUN: %clang -target armeb -march=armebv8.2-a -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-BE-V82A %s
+// RUN: %clang -target arm -march=armebv8.2a -mbig-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-BE-V82A %s
+// RUN: %clang -target arm -march=armebv8.2-a -mbig-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-BE-V82A %s
+// CHECK-BE-V82A: "-cc1"{{.*}} "-triple" "armebv8.2{{.*}}" "-target-cpu" 
"generic" "-target-feature" "+v8.2a"
+
+// RUN: %clang -target armv8.2a -mthumb -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-V82A-THUMB %s
+// RUN: %clang -target arm -march=armv8.2a -mthumb -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-V82A-THUMB %s
+// RUN: %clang -target arm -march=armv8.2-a -mthumb -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-V82A-THUMB %s
+// RUN: %clang -target armv8.2a -mlittle-endian -mthumb -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-V82A-THUMB %s
+// RUN: %clang -target arm -march=armv8.2a -mlittle-endian -mthumb -### -c %s 
2>&1 | FileCheck -check-prefix=CHECK-V82A-THUMB %s
+// RUN: %clang -target arm -march=armv8.2-a -mlittle-endian -mthumb -### -c %s 
2>&1 | FileCheck -check-prefix=CHECK-V82A-THUMB %s
+// CHECK-V82A-THUMB: "-cc1"{{.*}} "-triple" "thumbv8.2a-{{.*}}" "-target-cpu" 
"generic" "-target-feature" "+v8.2a"
+
+// RUN: %clang -target armebv8.2a -mthumb -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-BE-V82A-THUMB %s
+// RUN: %clang -target armeb -march=armebv8.2a -mthumb -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-BE-V82A-THUMB %s
+// RUN: %clang -target armeb -march=armebv8.2-a -mthumb -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-BE-V82A-THUMB %s
+// RUN: %clang -target armv8.2a -mbig-endian -mthumb -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-BE-V82A-THUMB %s
+// RUN: %clang -target arm -march=armebv8.2a -mbig-endian -mthumb -### -c %s 
2>&1 | FileCheck -check-prefix=CHECK-BE-V82A-THUMB %s
+// RUN: %clang -target arm -march=armebv8.2-a -mbig-endian -mthumb -### -c %s 
2>&1 | FileCheck -check-prefix=CHECK-BE-V82A-THUMB %s
+// CHECK-BE-V82A-THUMB: "-cc1"{{.*}} "-triple" "thumbebv8.2a-{{.*}}" 
"-target-cpu" "generic" "-target-feature" "+v8.2a"
+
+// RUN: %clang -target armv8a -march=armv8.2-a+fp16 -### -c %s 2>&1 | 
FileCheck --check-prefix CHECK-V82A-FP16 %s
+// CHECK-V82A-FP16: "-cc1"{{.*}} "-triple" "armv8.2{{.*}}" "-target-cpu" 
"generic" {{.*}}"-target-feature" "+v8.2a" {{.*}}"-target-feature" "+fullfp16"
+

Re: [PATCH] D15040: [ARM] Add command-line options for ARMv8.2-A

[Oliver Stannard via cfe-commits]

olista01 removed rL LLVM as the repository for this revision.
olista01 updated this revision to Diff 41302.
olista01 added a comment.

Removed obsolete logic for setting subtarget features, and fixed up v8.1-A 
tests to match.

Also added a missing test for predefined macros.


http://reviews.llvm.org/D15040

Files:
  lib/Basic/Targets.cpp
  lib/Driver/Tools.cpp
  test/Driver/arm-cortex-cpus.c
  test/Preprocessor/arm-target-features.c

Index: test/Preprocessor/arm-target-features.c
===
--- test/Preprocessor/arm-target-features.c
+++ test/Preprocessor/arm-target-features.c
@@ -408,3 +408,9 @@
 // CHECK-V81A: __ARM_ARCH_8_1A__ 1
 // CHECK-V81A: #define __ARM_ARCH_PROFILE 'A'
 // CHECK-V81A: #define __ARM_FP 0xE
+
+// RUN: %clang -target armv8.2a-none-none-eabi -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-V82A %s
+// CHECK-V82A: __ARM_ARCH 8
+// CHECK-V82A: __ARM_ARCH_8_2A__ 1
+// CHECK-V82A: #define __ARM_ARCH_PROFILE 'A'
+// CHECK-V82A: #define __ARM_FP 0xE
Index: test/Driver/arm-cortex-cpus.c
===
--- test/Driver/arm-cortex-cpus.c
+++ test/Driver/arm-cortex-cpus.c
@@ -204,31 +204,74 @@
 // RUN: %clang -mcpu=generic -target armv8.1a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
 // RUN: %clang -mcpu=generic -target arm -march=armv8.1a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
 // RUN: %clang -mcpu=generic -target arm -mlittle-endian -march=armv8.1-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A %s
-// CHECK-V81A: "-cc1"{{.*}} "-triple" "armv8.1a-{{.*}}" "-target-cpu" "generic" "-target-feature" "+v8.1a"
+// CHECK-V81A: "-cc1"{{.*}} "-triple" "armv8.1a-{{.*}}" "-target-cpu" "generic"
 
 // RUN: %clang -target armebv8.1a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V81A %s
 // RUN: %clang -target armeb -march=armebv8.1a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V81A %s
 // RUN: %clang -target armeb -march=armebv8.1-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V81A %s
 // RUN: %clang -target armv8.1a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V81A %s
 // RUN: %clang -target arm -march=armebv8.1a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V81A %s
 // RUN: %clang -target arm -march=armebv8.1-a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V81A %s
-// CHECK-BE-V81A: "-cc1"{{.*}} "-triple" "armebv8.1a-{{.*}}" "-target-cpu" "generic" "-target-feature" "+v8.1a"
+// CHECK-BE-V81A: "-cc1"{{.*}} "-triple" "armebv8.1a-{{.*}}" "-target-cpu" "generic"
 
 // RUN: %clang -target armv8.1a -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A-THUMB %s
 // RUN: %clang -target arm -march=armv8.1a -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A-THUMB %s
 // RUN: %clang -target arm -march=armv8.1-a -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A-THUMB %s
 // RUN: %clang -target armv8.1a -mlittle-endian -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A-THUMB %s
 // RUN: %clang -target arm -march=armv8.1a -mlittle-endian -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A-THUMB %s
 // RUN: %clang -target arm -march=armv8.1-a -mlittle-endian -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A-THUMB %s
-// CHECK-V81A-THUMB: "-cc1"{{.*}} "-triple" "thumbv8.1a-{{.*}}" "-target-cpu" "generic" "-target-feature" "+v8.1a"
+// CHECK-V81A-THUMB: "-cc1"{{.*}} "-triple" "thumbv8.1a-{{.*}}" "-target-cpu" "generic"
 
 // RUN: %clang -target armebv8.1a -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V81A-THUMB %s
 // RUN: %clang -target armeb -march=armebv8.1a -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V81A-THUMB %s
 // RUN: %clang -target armeb -march=armebv8.1-a -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V81A-THUMB %s
 // RUN: %clang -target armv8.1a -mbig-endian -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V81A-THUMB %s
 // RUN: %clang -target arm -march=armebv8.1a -mbig-endian -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V81A-THUMB %s
 // RUN: %clang -target arm -march=armebv8.1-a -mbig-endian -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V81A-THUMB %s
-// CHECK-BE-V81A-THUMB: "-cc1"{{.*}} "-triple" "thumbebv8.1a-{{.*}}" "-target-cpu" "generic" "-target-feature" "+v8.1a"
+// CHECK-BE-V81A-THUMB: "-cc1"{{.*}} "-triple" "thumbebv8.1a-{{.*}}" "-target-cpu" "generic"
+
+// RUN: %clang -target armv8.2a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V82A %s
+// RUN: %clang -target arm -march=armv8.2a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V82A %s
+// RUN: %clang -target arm -march=armv8.2-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V82A %s
+// RUN: %clang -target arm -march=armv8.2a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V82A %s
+// RUN: %clang -target armv8.2a 

[PATCH] D15023: [AArch64] Add command-line options for Statistical

[Oliver Stannard via cfe-commits]

olista01 created this revision.
olista01 added a reviewer: t.p.northover.
olista01 added a subscriber: cfe-commits.
olista01 set the repository for this revision to rL LLVM.
Herald added subscribers: rengolin, aemerson.

This adds the "+profile" and +noprofile" suffixes for the -march and
-mcpu options, to allow enabling or disabling the options Statistical
Profiling Extension to ARMv8.2-A.

Repository:
  rL LLVM

http://reviews.llvm.org/D15023

Files:
  lib/Driver/Tools.cpp
  test/Driver/aarch64-cpus.c

Index: test/Driver/aarch64-cpus.c
===
--- test/Driver/aarch64-cpus.c
+++ test/Driver/aarch64-cpus.c
@@ -126,6 +126,12 @@
 // RUN: %clang -target aarch64 -march=armv8.2-a+fp16 -### -c %s 2>&1 | 
FileCheck -check-prefix=GENERICV82A-FP16 %s
 // GENERICV82A-FP16: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"generic" "-target-feature" "+neon" "-target-feature" "+v8.2a" 
"-target-feature" "+fullfp16"
 
+// RUN: %clang -target aarch64 -march=armv8.2-a+profile -### -c %s 2>&1 | 
FileCheck -check-prefix=GENERICV82A-SPE %s
+// GENERICV82A-SPE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"generic" "-target-feature" "+neon" "-target-feature" "+v8.2a" 
"-target-feature" "+spe"
+//
+// RUN: %clang -target aarch64 -march=armv8.2-a+fp16+profile -### -c %s 2>&1 | 
FileCheck -check-prefix=GENERICV82A-FP16-SPE %s
+// GENERICV82A-FP16-SPE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"generic" "-target-feature" "+neon" "-target-feature" "+v8.2a" 
"-target-feature" "+fullfp16" "-target-feature" "+spe"
+
 // == Check whether -march accepts mixed-case values.
 // RUN: %clang -target aarch64_be -march=ARMV8.1A -### -c %s 2>&1 | FileCheck 
-check-prefix=GENERICV81A-BE %s
 // RUN: %clang -target aarch64_be -march=ARMV8.1-A -### -c %s 2>&1 | FileCheck 
-check-prefix=GENERICV81A-BE %s
Index: lib/Driver/Tools.cpp
===
--- lib/Driver/Tools.cpp
+++ lib/Driver/Tools.cpp
@@ -2032,11 +2032,13 @@
  .Case("crc", "+crc")
  .Case("crypto", "+crypto")
  .Case("fp16", "+fullfp16")
+ .Case("profile", "+spe")
  .Case("nofp", "-fp-armv8")
  .Case("nosimd", "-neon")
  .Case("nocrc", "-crc")
  .Case("nocrypto", "-crypto")
  .Case("nofp16", "-fullfp16")
+ .Case("noprofile", "-spe")
  .Default(nullptr);
 if (result)
   Features.push_back(result);


Index: test/Driver/aarch64-cpus.c
===
--- test/Driver/aarch64-cpus.c
+++ test/Driver/aarch64-cpus.c
@@ -126,6 +126,12 @@
 // RUN: %clang -target aarch64 -march=armv8.2-a+fp16 -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV82A-FP16 %s
 // GENERICV82A-FP16: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v8.2a" "-target-feature" "+fullfp16"
 
+// RUN: %clang -target aarch64 -march=armv8.2-a+profile -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV82A-SPE %s
+// GENERICV82A-SPE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v8.2a" "-target-feature" "+spe"
+//
+// RUN: %clang -target aarch64 -march=armv8.2-a+fp16+profile -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV82A-FP16-SPE %s
+// GENERICV82A-FP16-SPE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v8.2a" "-target-feature" "+fullfp16" "-target-feature" "+spe"
+
 // == Check whether -march accepts mixed-case values.
 // RUN: %clang -target aarch64_be -march=ARMV8.1A -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV81A-BE %s
 // RUN: %clang -target aarch64_be -march=ARMV8.1-A -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV81A-BE %s
Index: lib/Driver/Tools.cpp
===
--- lib/Driver/Tools.cpp
+++ lib/Driver/Tools.cpp
@@ -2032,11 +2032,13 @@
  .Case("crc", "+crc")
  .Case("crypto", "+crypto")
  .Case("fp16", "+fullfp16")
+ .Case("profile", "+spe")
  .Case("nofp", "-fp-armv8")
  .Case("nosimd", "-neon")
  .Case("nocrc", "-crc")
  .Case("nocrypto", "-crypto")
  .Case("nofp16", "-fullfp16")
+ .Case("noprofile", "-spe")
  .Default(nullptr);
 if (result)
   Features.push_back(result);
___
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r254160 - [AArch64] Add command-line options for ARMv8.2-A

[Oliver Stannard via cfe-commits]

Author: olista01
Date: Thu Nov 26 09:36:42 2015
New Revision: 254160

URL: http://llvm.org/viewvc/llvm-project?rev=254160=rev
Log:
[AArch64] Add command-line options for ARMv8.2-A

This adds new values for the -march option (armv8.2a and armv8.2-a,
which are aliases of each other), and new suffixes for the -march and
-mcpu options (+fp16 and +nofp16), to allow targeting the ARMv8.2-A
architecture and it's optional half-precision floating-point extension.

Differential Revision: http://reviews.llvm.org/D15022


Modified:
cfe/trunk/lib/Driver/Tools.cpp
cfe/trunk/test/Driver/aarch64-cpus.c

Modified: cfe/trunk/lib/Driver/Tools.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/Tools.cpp?rev=254160=254159=254160=diff
==
--- cfe/trunk/lib/Driver/Tools.cpp (original)
+++ cfe/trunk/lib/Driver/Tools.cpp Thu Nov 26 09:36:42 2015
@@ -2031,10 +2031,12 @@ static bool DecodeAArch64Features(const
  .Case("simd", "+neon")
  .Case("crc", "+crc")
  .Case("crypto", "+crypto")
+ .Case("fp16", "+fullfp16")
  .Case("nofp", "-fp-armv8")
  .Case("nosimd", "-neon")
  .Case("nocrc", "-crc")
  .Case("nocrypto", "-crypto")
+ .Case("nofp16", "-fullfp16")
  .Default(nullptr);
 if (result)
   Features.push_back(result);
@@ -2080,6 +2082,8 @@ getAArch64ArchFeaturesFromMarch(const Dr
 // ok, no additional features.
   } else if (Split.first == "armv8.1-a" || Split.first == "armv8.1a") {
 Features.push_back("+v8.1a");
+  } else if (Split.first == "armv8.2-a" || Split.first == "armv8.2a" ) {
+Features.push_back("+v8.2a");
   } else {
 return false;
   }

Modified: cfe/trunk/test/Driver/aarch64-cpus.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/aarch64-cpus.c?rev=254160=254159=254160=diff
==
--- cfe/trunk/test/Driver/aarch64-cpus.c (original)
+++ cfe/trunk/test/Driver/aarch64-cpus.c Thu Nov 26 09:36:42 2015
@@ -114,6 +114,18 @@
 // RUN: %clang -target aarch64 -mbig-endian -march=armv8.1-a -### -c %s 2>&1 | 
FileCheck -check-prefix=GENERICV81A-BE %s
 // RUN: %clang -target aarch64_be -mbig-endian -march=armv8.1a -### -c %s 2>&1 
| FileCheck -check-prefix=GENERICV81A-BE %s
 // RUN: %clang -target aarch64_be -mbig-endian -march=armv8.1-a -### -c %s 
2>&1 | FileCheck -check-prefix=GENERICV81A-BE %s
+
+// RUN: %clang -target aarch64 -march=armv8.2a -### -c %s 2>&1 | FileCheck 
-check-prefix=GENERICV82A %s
+// RUN: %clang -target aarch64 -march=armv8.2-a -### -c %s 2>&1 | FileCheck 
-check-prefix=GENERICV82A %s
+// RUN: %clang -target aarch64 -mlittle-endian -march=armv8.2a -### -c %s 2>&1 
| FileCheck -check-prefix=GENERICV82A %s
+// RUN: %clang -target aarch64 -mlittle-endian -march=armv8.2-a -### -c %s 
2>&1 | FileCheck -check-prefix=GENERICV82A %s
+// RUN: %clang -target aarch64_be -mlittle-endian -march=armv8.2a -### -c %s 
2>&1 | FileCheck -check-prefix=GENERICV82A %s
+// RUN: %clang -target aarch64_be -mlittle-endian -march=armv8.2-a -### -c %s 
2>&1 | FileCheck -check-prefix=GENERICV82A %s
+// GENERICV82A: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" 
"-target-feature" "+neon" "-target-feature" "+v8.2a"
+
+// RUN: %clang -target aarch64 -march=armv8.2-a+fp16 -### -c %s 2>&1 | 
FileCheck -check-prefix=GENERICV82A-FP16 %s
+// GENERICV82A-FP16: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"generic" "-target-feature" "+neon" "-target-feature" "+v8.2a" 
"-target-feature" "+fullfp16"
+
 // == Check whether -march accepts mixed-case values.
 // RUN: %clang -target aarch64_be -march=ARMV8.1A -### -c %s 2>&1 | FileCheck 
-check-prefix=GENERICV81A-BE %s
 // RUN: %clang -target aarch64_be -march=ARMV8.1-A -### -c %s 2>&1 | FileCheck 
-check-prefix=GENERICV81A-BE %s


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Re: [PATCH] D15022: [AArch64] Add command-line options for ARMv8.2-A

[Oliver Stannard via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL254160: [AArch64] Add command-line options for ARMv8.2-A 
(authored by olista01).

Changed prior to commit:
  http://reviews.llvm.org/D15022?vs=41243=41257#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D15022

Files:
  cfe/trunk/lib/Driver/Tools.cpp
  cfe/trunk/test/Driver/aarch64-cpus.c

Index: cfe/trunk/lib/Driver/Tools.cpp
===
--- cfe/trunk/lib/Driver/Tools.cpp
+++ cfe/trunk/lib/Driver/Tools.cpp
@@ -2031,10 +2031,12 @@
  .Case("simd", "+neon")
  .Case("crc", "+crc")
  .Case("crypto", "+crypto")
+ .Case("fp16", "+fullfp16")
  .Case("nofp", "-fp-armv8")
  .Case("nosimd", "-neon")
  .Case("nocrc", "-crc")
  .Case("nocrypto", "-crypto")
+ .Case("nofp16", "-fullfp16")
  .Default(nullptr);
 if (result)
   Features.push_back(result);
@@ -2080,6 +2082,8 @@
 // ok, no additional features.
   } else if (Split.first == "armv8.1-a" || Split.first == "armv8.1a") {
 Features.push_back("+v8.1a");
+  } else if (Split.first == "armv8.2-a" || Split.first == "armv8.2a" ) {
+Features.push_back("+v8.2a");
   } else {
 return false;
   }
Index: cfe/trunk/test/Driver/aarch64-cpus.c
===
--- cfe/trunk/test/Driver/aarch64-cpus.c
+++ cfe/trunk/test/Driver/aarch64-cpus.c
@@ -114,6 +114,18 @@
 // RUN: %clang -target aarch64 -mbig-endian -march=armv8.1-a -### -c %s 2>&1 | 
FileCheck -check-prefix=GENERICV81A-BE %s
 // RUN: %clang -target aarch64_be -mbig-endian -march=armv8.1a -### -c %s 2>&1 
| FileCheck -check-prefix=GENERICV81A-BE %s
 // RUN: %clang -target aarch64_be -mbig-endian -march=armv8.1-a -### -c %s 
2>&1 | FileCheck -check-prefix=GENERICV81A-BE %s
+
+// RUN: %clang -target aarch64 -march=armv8.2a -### -c %s 2>&1 | FileCheck 
-check-prefix=GENERICV82A %s
+// RUN: %clang -target aarch64 -march=armv8.2-a -### -c %s 2>&1 | FileCheck 
-check-prefix=GENERICV82A %s
+// RUN: %clang -target aarch64 -mlittle-endian -march=armv8.2a -### -c %s 2>&1 
| FileCheck -check-prefix=GENERICV82A %s
+// RUN: %clang -target aarch64 -mlittle-endian -march=armv8.2-a -### -c %s 
2>&1 | FileCheck -check-prefix=GENERICV82A %s
+// RUN: %clang -target aarch64_be -mlittle-endian -march=armv8.2a -### -c %s 
2>&1 | FileCheck -check-prefix=GENERICV82A %s
+// RUN: %clang -target aarch64_be -mlittle-endian -march=armv8.2-a -### -c %s 
2>&1 | FileCheck -check-prefix=GENERICV82A %s
+// GENERICV82A: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" 
"-target-feature" "+neon" "-target-feature" "+v8.2a"
+
+// RUN: %clang -target aarch64 -march=armv8.2-a+fp16 -### -c %s 2>&1 | 
FileCheck -check-prefix=GENERICV82A-FP16 %s
+// GENERICV82A-FP16: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"generic" "-target-feature" "+neon" "-target-feature" "+v8.2a" 
"-target-feature" "+fullfp16"
+
 // == Check whether -march accepts mixed-case values.
 // RUN: %clang -target aarch64_be -march=ARMV8.1A -### -c %s 2>&1 | FileCheck 
-check-prefix=GENERICV81A-BE %s
 // RUN: %clang -target aarch64_be -march=ARMV8.1-A -### -c %s 2>&1 | FileCheck 
-check-prefix=GENERICV81A-BE %s


Index: cfe/trunk/lib/Driver/Tools.cpp
===
--- cfe/trunk/lib/Driver/Tools.cpp
+++ cfe/trunk/lib/Driver/Tools.cpp
@@ -2031,10 +2031,12 @@
  .Case("simd", "+neon")
  .Case("crc", "+crc")
  .Case("crypto", "+crypto")
+ .Case("fp16", "+fullfp16")
  .Case("nofp", "-fp-armv8")
  .Case("nosimd", "-neon")
  .Case("nocrc", "-crc")
  .Case("nocrypto", "-crypto")
+ .Case("nofp16", "-fullfp16")
  .Default(nullptr);
 if (result)
   Features.push_back(result);
@@ -2080,6 +2082,8 @@
 // ok, no additional features.
   } else if (Split.first == "armv8.1-a" || Split.first == "armv8.1a") {
 Features.push_back("+v8.1a");
+  } else if (Split.first == "armv8.2-a" || Split.first == "armv8.2a" ) {
+Features.push_back("+v8.2a");
   } else {
 return false;
   }
Index: cfe/trunk/test/Driver/aarch64-cpus.c
===
--- cfe/trunk/test/Driver/aarch64-cpus.c
+++ cfe/trunk/test/Driver/aarch64-cpus.c
@@ -114,6 +114,18 @@
 // RUN: %clang -target aarch64 -mbig-endian -march=armv8.1-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV81A-BE %s
 // RUN: %clang -target 

r254161 - [AArch64] Add command-line options for Statistical Profiling Extension

[Oliver Stannard via cfe-commits]

Author: olista01
Date: Thu Nov 26 09:38:54 2015
New Revision: 254161

URL: http://llvm.org/viewvc/llvm-project?rev=254161=rev
Log:
[AArch64] Add command-line options for Statistical Profiling Extension

This adds the "+profile" and +noprofile" suffixes for the -march and
-mcpu options, to allow enabling or disabling the options Statistical
Profiling Extension to ARMv8.2-A.

Differential Revision: http://reviews.llvm.org/D15023


Modified:
cfe/trunk/lib/Driver/Tools.cpp
cfe/trunk/test/Driver/aarch64-cpus.c

Modified: cfe/trunk/lib/Driver/Tools.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/Tools.cpp?rev=254161=254160=254161=diff
==
--- cfe/trunk/lib/Driver/Tools.cpp (original)
+++ cfe/trunk/lib/Driver/Tools.cpp Thu Nov 26 09:38:54 2015
@@ -2032,11 +2032,13 @@ static bool DecodeAArch64Features(const
  .Case("crc", "+crc")
  .Case("crypto", "+crypto")
  .Case("fp16", "+fullfp16")
+ .Case("profile", "+spe")
  .Case("nofp", "-fp-armv8")
  .Case("nosimd", "-neon")
  .Case("nocrc", "-crc")
  .Case("nocrypto", "-crypto")
  .Case("nofp16", "-fullfp16")
+ .Case("noprofile", "-spe")
  .Default(nullptr);
 if (result)
   Features.push_back(result);

Modified: cfe/trunk/test/Driver/aarch64-cpus.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/aarch64-cpus.c?rev=254161=254160=254161=diff
==
--- cfe/trunk/test/Driver/aarch64-cpus.c (original)
+++ cfe/trunk/test/Driver/aarch64-cpus.c Thu Nov 26 09:38:54 2015
@@ -126,6 +126,12 @@
 // RUN: %clang -target aarch64 -march=armv8.2-a+fp16 -### -c %s 2>&1 | 
FileCheck -check-prefix=GENERICV82A-FP16 %s
 // GENERICV82A-FP16: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"generic" "-target-feature" "+neon" "-target-feature" "+v8.2a" 
"-target-feature" "+fullfp16"
 
+// RUN: %clang -target aarch64 -march=armv8.2-a+profile -### -c %s 2>&1 | 
FileCheck -check-prefix=GENERICV82A-SPE %s
+// GENERICV82A-SPE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"generic" "-target-feature" "+neon" "-target-feature" "+v8.2a" 
"-target-feature" "+spe"
+//
+// RUN: %clang -target aarch64 -march=armv8.2-a+fp16+profile -### -c %s 2>&1 | 
FileCheck -check-prefix=GENERICV82A-FP16-SPE %s
+// GENERICV82A-FP16-SPE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"generic" "-target-feature" "+neon" "-target-feature" "+v8.2a" 
"-target-feature" "+fullfp16" "-target-feature" "+spe"
+
 // == Check whether -march accepts mixed-case values.
 // RUN: %clang -target aarch64_be -march=ARMV8.1A -### -c %s 2>&1 | FileCheck 
-check-prefix=GENERICV81A-BE %s
 // RUN: %clang -target aarch64_be -march=ARMV8.1-A -### -c %s 2>&1 | FileCheck 
-check-prefix=GENERICV81A-BE %s


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Re: [PATCH] D15023: [AArch64] Add command-line options for Statistical

[Oliver Stannard via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL254161: [AArch64] Add command-line options for Statistical 
Profiling Extension (authored by olista01).

Changed prior to commit:
  http://reviews.llvm.org/D15023?vs=41244=41258#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D15023

Files:
  cfe/trunk/lib/Driver/Tools.cpp
  cfe/trunk/test/Driver/aarch64-cpus.c

Index: cfe/trunk/test/Driver/aarch64-cpus.c
===
--- cfe/trunk/test/Driver/aarch64-cpus.c
+++ cfe/trunk/test/Driver/aarch64-cpus.c
@@ -126,6 +126,12 @@
 // RUN: %clang -target aarch64 -march=armv8.2-a+fp16 -### -c %s 2>&1 | 
FileCheck -check-prefix=GENERICV82A-FP16 %s
 // GENERICV82A-FP16: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"generic" "-target-feature" "+neon" "-target-feature" "+v8.2a" 
"-target-feature" "+fullfp16"
 
+// RUN: %clang -target aarch64 -march=armv8.2-a+profile -### -c %s 2>&1 | 
FileCheck -check-prefix=GENERICV82A-SPE %s
+// GENERICV82A-SPE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"generic" "-target-feature" "+neon" "-target-feature" "+v8.2a" 
"-target-feature" "+spe"
+//
+// RUN: %clang -target aarch64 -march=armv8.2-a+fp16+profile -### -c %s 2>&1 | 
FileCheck -check-prefix=GENERICV82A-FP16-SPE %s
+// GENERICV82A-FP16-SPE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"generic" "-target-feature" "+neon" "-target-feature" "+v8.2a" 
"-target-feature" "+fullfp16" "-target-feature" "+spe"
+
 // == Check whether -march accepts mixed-case values.
 // RUN: %clang -target aarch64_be -march=ARMV8.1A -### -c %s 2>&1 | FileCheck 
-check-prefix=GENERICV81A-BE %s
 // RUN: %clang -target aarch64_be -march=ARMV8.1-A -### -c %s 2>&1 | FileCheck 
-check-prefix=GENERICV81A-BE %s
Index: cfe/trunk/lib/Driver/Tools.cpp
===
--- cfe/trunk/lib/Driver/Tools.cpp
+++ cfe/trunk/lib/Driver/Tools.cpp
@@ -2032,11 +2032,13 @@
  .Case("crc", "+crc")
  .Case("crypto", "+crypto")
  .Case("fp16", "+fullfp16")
+ .Case("profile", "+spe")
  .Case("nofp", "-fp-armv8")
  .Case("nosimd", "-neon")
  .Case("nocrc", "-crc")
  .Case("nocrypto", "-crypto")
  .Case("nofp16", "-fullfp16")
+ .Case("noprofile", "-spe")
  .Default(nullptr);
 if (result)
   Features.push_back(result);


Index: cfe/trunk/test/Driver/aarch64-cpus.c
===
--- cfe/trunk/test/Driver/aarch64-cpus.c
+++ cfe/trunk/test/Driver/aarch64-cpus.c
@@ -126,6 +126,12 @@
 // RUN: %clang -target aarch64 -march=armv8.2-a+fp16 -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV82A-FP16 %s
 // GENERICV82A-FP16: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v8.2a" "-target-feature" "+fullfp16"
 
+// RUN: %clang -target aarch64 -march=armv8.2-a+profile -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV82A-SPE %s
+// GENERICV82A-SPE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v8.2a" "-target-feature" "+spe"
+//
+// RUN: %clang -target aarch64 -march=armv8.2-a+fp16+profile -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV82A-FP16-SPE %s
+// GENERICV82A-FP16-SPE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v8.2a" "-target-feature" "+fullfp16" "-target-feature" "+spe"
+
 // == Check whether -march accepts mixed-case values.
 // RUN: %clang -target aarch64_be -march=ARMV8.1A -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV81A-BE %s
 // RUN: %clang -target aarch64_be -march=ARMV8.1-A -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV81A-BE %s
Index: cfe/trunk/lib/Driver/Tools.cpp
===
--- cfe/trunk/lib/Driver/Tools.cpp
+++ cfe/trunk/lib/Driver/Tools.cpp
@@ -2032,11 +2032,13 @@
  .Case("crc", "+crc")
  .Case("crypto", "+crypto")
  .Case("fp16", "+fullfp16")
+ .Case("profile", "+spe")
  .Case("nofp", "-fp-armv8")
  .Case("nosimd", "-neon")
  .Case("nocrc", "-crc")
  .Case("nocrypto", "-crypto")
  .Case("nofp16", "-fullfp16")
+ .Case("noprofile", "-spe")
  .Default(nullptr);
 if (result)
   Features.push_back(result);

r253211 - [ARM,AArch64] Fix __rev16l and __rev16ll intrinsics

[Oliver Stannard via cfe-commits]

Author: olista01
Date: Mon Nov 16 08:58:50 2015
New Revision: 253211

URL: http://llvm.org/viewvc/llvm-project?rev=253211=rev
Log:
[ARM,AArch64] Fix __rev16l and __rev16ll intrinsics

These two intrinsics are defined in arm_acle.h.

__rev16l needs to rotate by 16 bits, bit it was actually rotating by 2 bits.
For AArch64, where long is 64 bits, this would still be wrong.

__rev16ll was incorrect, it reversed the bytes in each 32-bit word, rather than
each 16-bit halfword. The correct implementation is to apply __rev16 to the top
and bottom words of the 64-bit value.

For AArch32 targets, these get compiled down to the hardware rev16 instruction
at -O1 and above. For AArch64 targets, the 64-bit ones get compiled to two
32-bit rev16 instructions, because there is not currently a pattern for the
64-bit rev16 instruction.

Differential Revision: http://reviews.llvm.org/D14609

Modified:
cfe/trunk/lib/Headers/arm_acle.h
cfe/trunk/test/CodeGen/arm_acle.c

Modified: cfe/trunk/lib/Headers/arm_acle.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/arm_acle.h?rev=253211=253210=253211=diff
==
--- cfe/trunk/lib/Headers/arm_acle.h (original)
+++ cfe/trunk/lib/Headers/arm_acle.h Mon Nov 16 08:58:50 2015
@@ -175,14 +175,18 @@ static __inline__ uint32_t __attribute__
   return __ror(__rev(t), 16);
 }
 
-static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
-  __rev16l(unsigned long t) {
-return __rorl(__revl(t), sizeof(long) / 2);
-}
-
 static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
   __rev16ll(uint64_t t) {
-  return __rorll(__revll(t), 32);
+  return (((uint64_t)__rev16(t >> 32)) << 32) | __rev16(t);
+}
+
+static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
+  __rev16l(unsigned long t) {
+#if __SIZEOF_LONG__ == 4
+return __rev16(t);
+#else
+return __rev16ll(t);
+#endif
 }
 
 /* REVSH */

Modified: cfe/trunk/test/CodeGen/arm_acle.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm_acle.c?rev=253211=253210=253211=diff
==
--- cfe/trunk/test/CodeGen/arm_acle.c (original)
+++ cfe/trunk/test/CodeGen/arm_acle.c Mon Nov 16 08:58:50 2015
@@ -186,27 +186,53 @@ uint64_t test_revll(uint64_t t) {
 
 // ARM-LABEL: test_rev16
 // ARM: llvm.bswap
-// ARM: lshr
-// ARM: shl
+// ARM: lshr {{.*}}, 16
+// ARM: shl {{.*}}, 16
 // ARM: or
 uint32_t test_rev16(uint32_t t) {
   return __rev16(t);
 }
 
 // ARM-LABEL: test_rev16l
-// ARM: llvm.bswap
-// ARM: lshr
-// ARM: shl
-// ARM: or
+// AArch32: llvm.bswap
+// AArch32: lshr {{.*}}, 16
+// AArch32: shl {{.*}}, 16
+// AArch32: or
+// AArch64: [[T1:%.*]] = lshr i64 [[IN:%.*]], 32
+// AArch64: [[T2:%.*]] = trunc i64 [[T1]] to i32
+// AArch64: [[T3:%.*]] = tail call i32 @llvm.bswap.i32(i32 [[T2]])
+// AArch64: [[T4:%.*]] = lshr i32 [[T3]], 16
+// AArch64: [[T5:%.*]] = shl i32 [[T3]], 16
+// AArch64: [[T6:%.*]] = or i32 [[T5]], [[T4]]
+// AArch64: [[T7:%.*]] = zext i32 [[T6]] to i64
+// AArch64: [[T8:%.*]] = shl nuw i64 [[T7]], 32
+// AArch64: [[T9:%.*]] = trunc i64 [[IN]] to i32
+// AArch64: [[T10:%.*]] = tail call i32 @llvm.bswap.i32(i32 [[T9]])
+// AArch64: [[T11:%.*]] = lshr i32 [[T10]], 16
+// AArch64: [[T12:%.*]] = shl i32 [[T10]], 16
+// AArch64: [[T13:%.*]] = or i32 [[T12]], [[T11]]
+// AArch64: [[T14:%.*]] = zext i32 [[T13]] to i64
+// AArch64: [[T15:%.*]] = or i64 [[T8]], [[T14]]
 long test_rev16l(long t) {
   return __rev16l(t);
 }
 
 // ARM-LABEL: test_rev16ll
-// ARM: llvm.bswap
-// ARM: lshr
-// ARM: shl
-// ARM: or
+// ARM: [[T1:%.*]] = lshr i64 [[IN:%.*]], 32
+// ARM: [[T2:%.*]] = trunc i64 [[T1]] to i32
+// ARM: [[T3:%.*]] = tail call i32 @llvm.bswap.i32(i32 [[T2]])
+// ARM: [[T4:%.*]] = lshr i32 [[T3]], 16
+// ARM: [[T5:%.*]] = shl i32 [[T3]], 16
+// ARM: [[T6:%.*]] = or i32 [[T5]], [[T4]]
+// ARM: [[T7:%.*]] = zext i32 [[T6]] to i64
+// ARM: [[T8:%.*]] = shl nuw i64 [[T7]], 32
+// ARM: [[T9:%.*]] = trunc i64 [[IN]] to i32
+// ARM: [[T10:%.*]] = tail call i32 @llvm.bswap.i32(i32 [[T9]])
+// ARM: [[T11:%.*]] = lshr i32 [[T10]], 16
+// ARM: [[T12:%.*]] = shl i32 [[T10]], 16
+// ARM: [[T13:%.*]] = or i32 [[T12]], [[T11]]
+// ARM: [[T14:%.*]] = zext i32 [[T13]] to i64
+// ARM: [[T15:%.*]] = or i64 [[T8]], [[T14]]
 uint64_t test_rev16ll(uint64_t t) {
   return __rev16ll(t);
 }


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[PATCH] D14119: [libcxxabi] Correctly align fallback heap

[Oliver Stannard via cfe-commits]

olista01 created this revision.
olista01 added reviewers: mclow.lists, compnerd.
olista01 added a subscriber: cfe-commits.
olista01 set the repository for this revision to rL LLVM.

The fallback malloc in libcxxabi (used to allocate space for exception
objects in out-of-memory situations) defines its heap as an array of
chars, but casts it to a struct containing shorts before accessing it.
Sometimes, the heap does not get placed on a 2-byte boundary, so
accesses to it caused unaligned access faults on targets that do not
support unaligned accesses.

The fix is to specify the alignment of the heap array, so that it will
always be sufficient for a heap_node.

This is still technically invoking undefined behaviour, as it is
accessing an object of type "char array" through an lvalue of a
different type. However, I don't think it is possible to write malloc
without violating that rule, and we have tests covering this.

Repository:
  rL LLVM

http://reviews.llvm.org/D14119

Files:
  src/fallback_malloc.ipp

Index: src/fallback_malloc.ipp
===
--- src/fallback_malloc.ipp
+++ src/fallback_malloc.ipp
@@ -51,6 +51,7 @@
 
 
 #define HEAP_SIZE   512
+__attribute((aligned(2)))
 char heap [ HEAP_SIZE ];
 
 typedef unsigned short heap_offset;


Index: src/fallback_malloc.ipp
===
--- src/fallback_malloc.ipp
+++ src/fallback_malloc.ipp
@@ -51,6 +51,7 @@
 
 
 #define HEAP_SIZE   512
+__attribute((aligned(2)))
 char heap [ HEAP_SIZE ];
 
 typedef unsigned short heap_offset;
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r246755 - [ARM] Allow passing/returning of __fp16 arguments

[Oliver Stannard via cfe-commits]

Author: olista01
Date: Thu Sep  3 04:34:53 2015
New Revision: 246755

URL: http://llvm.org/viewvc/llvm-project?rev=246755=rev
Log:
[ARM] Allow passing/returning of __fp16 arguments

The ACLE (ARM C Language Extensions) 2.0 allows the __fp16 type to be
used as a functon argument or return type (ACLE 1.1 did not).

The current public release of the AAPCS (2.09) states that __fp16 values
should be converted to single-precision before being passed or returned,
but AAPCS 2.10 (to be released shortly) changes this, so that they are
passed in the least-significant 16 bits of either a GPR (for base AAPCS)
or a single-precision register (for AAPCS-VFP). This does not change how
arguments are passed if they get passed on the stack.

This patch brings clang up to compliance with the latest versions of
both of these specs.

We can now set the __ARM_FP16_ARGS ACLE predefine, and we have always
been able to set the __ARM_FP16_FORMAT_IEEE predefine (we do not support
the alternative format).

Added:
cfe/trunk/test/CodeGen/arm-fp16-arguments.c
Modified:
cfe/trunk/lib/Basic/Targets.cpp
cfe/trunk/lib/CodeGen/TargetInfo.cpp
cfe/trunk/lib/Driver/Tools.cpp
cfe/trunk/test/Preprocessor/arm-acle-6.5.c
cfe/trunk/test/Preprocessor/arm-target-features.c

Modified: cfe/trunk/lib/Basic/Targets.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=246755=246754=246755=diff
==
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Thu Sep  3 04:34:53 2015
@@ -4568,6 +4568,10 @@ public:
 // ACLE predefines.
 Builder.defineMacro("__ARM_ACLE", "200");
 
+// FP16 support (we currently only support IEEE format).
+Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
+Builder.defineMacro("__ARM_FP16_ARGS", "1");
+
 // Subtarget options.
 
 // FIXME: It's more complicated than this and we don't really support

Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=246755=246754=246755=diff
==
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Thu Sep  3 04:34:53 2015
@@ -4714,6 +4714,15 @@ ABIArgInfo ARMABIInfo::classifyArgumentT
 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
   }
 
+  // __fp16 gets passed as if it were an int or float, but with the top 16 bits
+  // unspecified.
+  if (Ty->isHalfType()) {
+llvm::Type *ResType = IsEffectivelyAAPCS_VFP ?
+  llvm::Type::getFloatTy(getVMContext()) :
+  llvm::Type::getInt32Ty(getVMContext());
+return ABIArgInfo::getDirect(ResType);
+  }
+
   if (!isAggregateTypeForABI(Ty)) {
 // Treat an enum type as its underlying type.
 if (const EnumType *EnumTy = Ty->getAs()) {
@@ -4872,6 +4881,15 @@ ABIArgInfo ARMABIInfo::classifyReturnTyp
 return ABIArgInfo::getIndirect(0);
   }
 
+  // __fp16 gets returned as if it were an int or float, but with the top 16
+  // bits unspecified.
+  if (RetTy->isHalfType()) {
+llvm::Type *ResType = IsEffectivelyAAPCS_VFP ?
+  llvm::Type::getFloatTy(getVMContext()) :
+  llvm::Type::getInt32Ty(getVMContext());
+return ABIArgInfo::getDirect(ResType);
+  }
+
   if (!isAggregateTypeForABI(RetTy)) {
 // Treat an enum type as its underlying type.
 if (const EnumType *EnumTy = RetTy->getAs())

Modified: cfe/trunk/lib/Driver/Tools.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/Tools.cpp?rev=246755=246754=246755=diff
==
--- cfe/trunk/lib/Driver/Tools.cpp (original)
+++ cfe/trunk/lib/Driver/Tools.cpp Thu Sep  3 04:34:53 2015
@@ -4293,9 +4293,19 @@ void Clang::ConstructJob(Compilation ,
   CmdArgs.push_back("-mstack-probe-size=0");
   }
 
-  if (getToolChain().getArch() == llvm::Triple::aarch64 ||
-  getToolChain().getArch() == llvm::Triple::aarch64_be)
+  switch (getToolChain().getArch()) {
+  case llvm::Triple::aarch64:
+  case llvm::Triple::aarch64_be:
+  case llvm::Triple::arm:
+  case llvm::Triple::armeb:
+  case llvm::Triple::thumb:
+  case llvm::Triple::thumbeb:
 CmdArgs.push_back("-fallow-half-arguments-and-returns");
+break;
+
+  default:
+break;
+  }
 
   if (Arg *A = Args.getLastArg(options::OPT_mrestrict_it,
options::OPT_mno_restrict_it)) {

Added: cfe/trunk/test/CodeGen/arm-fp16-arguments.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-fp16-arguments.c?rev=246755=auto
==
--- cfe/trunk/test/CodeGen/arm-fp16-arguments.c (added)
+++ cfe/trunk/test/CodeGen/arm-fp16-arguments.c Thu Sep  3 04:34:53 2015
@@ -0,0 +1,21 @@
+// RUN: %clang_cc1 -triple armv7a--none-eabi -target-abi aapcs -mfloat-abi 
soft 

Re: [PATCH] D12148: [ARM] Allow passing/returning of __fp16 arguments

[Oliver Stannard via cfe-commits]

olista01 closed this revision.
olista01 added a comment.

Thanks, committed as r246755.


http://reviews.llvm.org/D12148



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r246760 - Revert 246755 as it breaks buildbots

[Oliver Stannard via cfe-commits]

Author: olista01
Date: Thu Sep  3 06:46:24 2015
New Revision: 246760

URL: http://llvm.org/viewvc/llvm-project?rev=246760=rev
Log:
Revert 246755 as it breaks buildbots

Original commit message:
[ARM] Allow passing/returning of __fp16 arguments

The ACLE (ARM C Language Extensions) 2.0 allows the __fp16 type to be
used as a functon argument or return type (ACLE 1.1 did not).

The current public release of the AAPCS (2.09) states that __fp16 values
should be converted to single-precision before being passed or returned,
but AAPCS 2.10 (to be released shortly) changes this, so that they are
passed in the least-significant 16 bits of either a GPR (for base AAPCS)
or a single-precision register (for AAPCS-VFP). This does not change how
arguments are passed if they get passed on the stack.

This patch brings clang up to compliance with the latest versions of
both of these specs.

We can now set the __ARM_FP16_ARGS ACLE predefine, and we have always
been able to set the __ARM_FP16_FORMAT_IEEE predefine (we do not support
the alternative format).


Removed:
cfe/trunk/test/CodeGen/arm-fp16-arguments.c
Modified:
cfe/trunk/lib/Basic/Targets.cpp
cfe/trunk/lib/CodeGen/TargetInfo.cpp
cfe/trunk/lib/Driver/Tools.cpp
cfe/trunk/test/Preprocessor/arm-acle-6.5.c
cfe/trunk/test/Preprocessor/arm-target-features.c

Modified: cfe/trunk/lib/Basic/Targets.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=246760=246759=246760=diff
==
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Thu Sep  3 06:46:24 2015
@@ -4568,10 +4568,6 @@ public:
 // ACLE predefines.
 Builder.defineMacro("__ARM_ACLE", "200");
 
-// FP16 support (we currently only support IEEE format).
-Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
-Builder.defineMacro("__ARM_FP16_ARGS", "1");
-
 // Subtarget options.
 
 // FIXME: It's more complicated than this and we don't really support

Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=246760=246759=246760=diff
==
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Thu Sep  3 06:46:24 2015
@@ -4714,15 +4714,6 @@ ABIArgInfo ARMABIInfo::classifyArgumentT
 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
   }
 
-  // __fp16 gets passed as if it were an int or float, but with the top 16 bits
-  // unspecified.
-  if (Ty->isHalfType()) {
-llvm::Type *ResType = IsEffectivelyAAPCS_VFP ?
-  llvm::Type::getFloatTy(getVMContext()) :
-  llvm::Type::getInt32Ty(getVMContext());
-return ABIArgInfo::getDirect(ResType);
-  }
-
   if (!isAggregateTypeForABI(Ty)) {
 // Treat an enum type as its underlying type.
 if (const EnumType *EnumTy = Ty->getAs()) {
@@ -4881,15 +4872,6 @@ ABIArgInfo ARMABIInfo::classifyReturnTyp
 return ABIArgInfo::getIndirect(0);
   }
 
-  // __fp16 gets returned as if it were an int or float, but with the top 16
-  // bits unspecified.
-  if (RetTy->isHalfType()) {
-llvm::Type *ResType = IsEffectivelyAAPCS_VFP ?
-  llvm::Type::getFloatTy(getVMContext()) :
-  llvm::Type::getInt32Ty(getVMContext());
-return ABIArgInfo::getDirect(ResType);
-  }
-
   if (!isAggregateTypeForABI(RetTy)) {
 // Treat an enum type as its underlying type.
 if (const EnumType *EnumTy = RetTy->getAs())

Modified: cfe/trunk/lib/Driver/Tools.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/Tools.cpp?rev=246760=246759=246760=diff
==
--- cfe/trunk/lib/Driver/Tools.cpp (original)
+++ cfe/trunk/lib/Driver/Tools.cpp Thu Sep  3 06:46:24 2015
@@ -4293,19 +4293,9 @@ void Clang::ConstructJob(Compilation ,
   CmdArgs.push_back("-mstack-probe-size=0");
   }
 
-  switch (getToolChain().getArch()) {
-  case llvm::Triple::aarch64:
-  case llvm::Triple::aarch64_be:
-  case llvm::Triple::arm:
-  case llvm::Triple::armeb:
-  case llvm::Triple::thumb:
-  case llvm::Triple::thumbeb:
+  if (getToolChain().getArch() == llvm::Triple::aarch64 ||
+  getToolChain().getArch() == llvm::Triple::aarch64_be)
 CmdArgs.push_back("-fallow-half-arguments-and-returns");
-break;
-
-  default:
-break;
-  }
 
   if (Arg *A = Args.getLastArg(options::OPT_mrestrict_it,
options::OPT_mno_restrict_it)) {

Removed: cfe/trunk/test/CodeGen/arm-fp16-arguments.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-fp16-arguments.c?rev=246759=auto
==
--- cfe/trunk/test/CodeGen/arm-fp16-arguments.c (original)
+++ cfe/trunk/test/CodeGen/arm-fp16-arguments.c (removed)
@@ -1,21 +0,0 @@
-// RUN: %clang_cc1 -triple 

Re: [PATCH] D12148: [ARM] Allow passing/returning of __fp16 arguments

[Oliver Stannard via cfe-commits]

olista01 updated this revision to Diff 33932.
olista01 added a comment.

Don't make this change for OpenCL, which handles the half type natively.


http://reviews.llvm.org/D12148

Files:
  lib/Basic/Targets.cpp
  lib/CodeGen/TargetInfo.cpp
  lib/Driver/Tools.cpp
  test/CodeGen/arm-fp16-arguments.c
  test/Preprocessor/arm-acle-6.5.c
  test/Preprocessor/arm-target-features.c

Index: test/Preprocessor/arm-target-features.c
===
--- test/Preprocessor/arm-target-features.c
+++ test/Preprocessor/arm-target-features.c
@@ -5,6 +5,8 @@
 // CHECK: __ARM_FEATURE_CRC32 1
 // CHECK: __ARM_FEATURE_DIRECTED_ROUNDING 1
 // CHECK: __ARM_FEATURE_NUMERIC_MAXMIN 1
+// CHECK: __ARM_FP16_ARGS 1
+// CHECK: __ARM_FP16_FORMAT_IEEE 1
 
 // RUN: %clang -target armv7a-none-linux-gnu -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-V7 %s
 // CHECK-V7: __ARMEL__ 1
Index: test/Preprocessor/arm-acle-6.5.c
===
--- test/Preprocessor/arm-acle-6.5.c
+++ test/Preprocessor/arm-acle-6.5.c
@@ -1,6 +1,6 @@
 // RUN: %clang -target arm-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-DEFAULT
 
-// CHECK-DEFAULT-NOT: __ARM_FP
+// CHECK-DEFAULT-NOT: __ARM_FP 0x
 
 // RUN: %clang -target arm-eabi -mfpu=vfp -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP
 // RUN: %clang -target arm-eabi -mfpu=vfp3 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP
Index: test/CodeGen/arm-fp16-arguments.c
===
--- /dev/null
+++ test/CodeGen/arm-fp16-arguments.c
@@ -0,0 +1,21 @@
+// RUN: %clang_cc1 -triple armv7a--none-eabi -target-abi aapcs -mfloat-abi soft -fallow-half-arguments-and-returns -emit-llvm -o - -O1 %s | FileCheck %s --check-prefix=CHECK --check-prefix=SOFT
+// RUN: %clang_cc1 -triple armv7a--none-eabi -target-abi aapcs -mfloat-abi hard -fallow-half-arguments-and-returns -emit-llvm -o - -O1 %s | FileCheck %s --check-prefix=CHECK --check-prefix=HARD
+
+__fp16 g;
+
+void t1(__fp16 a) { g = a; }
+// SOFT: define void @t1(i32 [[PARAM:%.*]])
+// SOFT: [[TRUNC:%.*]] = trunc i32 [[PARAM]] to i16
+// HARD: define arm_aapcs_vfpcc void @t1(float [[PARAM:%.*]])
+// HARD: [[BITCAST:%.*]] = bitcast float [[PARAM]] to i32
+// HARD: [[TRUNC:%.*]] = trunc i32 [[BITCAST]] to i16
+// CHECK: store i16 [[TRUNC]], i16* bitcast (half* @g to i16*)
+
+__fp16 t2() { return g; }
+// SOFT: define i32 @t2()
+// HARD: define arm_aapcs_vfpcc float @t2()
+// CHECK: [[LOAD:%.*]] = load i16, i16* bitcast (half* @g to i16*)
+// CHECK: [[ZEXT:%.*]] = zext i16 [[LOAD]] to i32
+// SOFT: ret i32 [[ZEXT]]
+// HARD: [[BITCAST:%.*]] = bitcast i32 [[ZEXT]] to float
+// HARD: ret float [[BITCAST]]
Index: lib/Driver/Tools.cpp
===
--- lib/Driver/Tools.cpp
+++ lib/Driver/Tools.cpp
@@ -4293,9 +4293,19 @@
   CmdArgs.push_back("-mstack-probe-size=0");
   }
 
-  if (getToolChain().getArch() == llvm::Triple::aarch64 ||
-  getToolChain().getArch() == llvm::Triple::aarch64_be)
+  switch (getToolChain().getArch()) {
+  case llvm::Triple::aarch64:
+  case llvm::Triple::aarch64_be:
+  case llvm::Triple::arm:
+  case llvm::Triple::armeb:
+  case llvm::Triple::thumb:
+  case llvm::Triple::thumbeb:
 CmdArgs.push_back("-fallow-half-arguments-and-returns");
+break;
+
+  default:
+break;
+  }
 
   if (Arg *A = Args.getLastArg(options::OPT_mrestrict_it,
options::OPT_mno_restrict_it)) {
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -4714,6 +4714,15 @@
 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
   }
 
+  // __fp16 gets passed as if it were an int or float, but with the top 16 bits
+  // unspecified.
+  if (Ty->isHalfType() && !getContext().getLangOpts().OpenCL) {
+llvm::Type *ResType = IsEffectivelyAAPCS_VFP ?
+  llvm::Type::getFloatTy(getVMContext()) :
+  llvm::Type::getInt32Ty(getVMContext());
+return ABIArgInfo::getDirect(ResType);
+  }
+
   if (!isAggregateTypeForABI(Ty)) {
 // Treat an enum type as its underlying type.
 if (const EnumType *EnumTy = Ty->getAs()) {
@@ -4872,6 +4881,15 @@
 return ABIArgInfo::getIndirect(0);
   }
 
+  // __fp16 gets returned as if it were an int or float, but with the top 16
+  // bits unspecified.
+  if (RetTy->isHalfType() && !getContext().getLangOpts().OpenCL) {
+llvm::Type *ResType = IsEffectivelyAAPCS_VFP ?
+  llvm::Type::getFloatTy(getVMContext()) :
+  llvm::Type::getInt32Ty(getVMContext());
+return ABIArgInfo::getDirect(ResType);
+  }
+
   if (!isAggregateTypeForABI(RetTy)) {
 // Treat an enum type as its underlying type.
 if (const EnumType *EnumTy = RetTy->getAs())
Index: lib/Basic/Targets.cpp

Re: [PATCH] D12148: [ARM] Allow passing/returning of __fp16 arguments

[Oliver Stannard via cfe-commits]

olista01 added a comment.

Committed as r246764, with an additional comment explaining why we don't do 
this for OpenCL.


http://reviews.llvm.org/D12148



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Re: [PATCH] D12148: [ARM] Allow passing/returning of __fp16 arguments

[Oliver Stannard via cfe-commits]

olista01 added a comment.

Ping?


http://reviews.llvm.org/D12148



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Re: [PATCH] D12244: Implement ACLE 2.0 macros of chapters 6.4 and 6.5 for [ARM] and [Aarch64] targets

[Oliver Stannard via cfe-commits]

olista01 added a subscriber: olista01.


Comment at: lib/Basic/Targets.cpp:4685-4686
@@ +4684,4 @@
+// ACLE 6.5.2 Half-precision (16-bit) floating-point format
+if (HW_FP  HW_FP_HP)
+  Builder.defineMacro(__ARM_FP16_FORMAT_IEEE, 1);
+

The __fp16 type is accepted even if it is not supported by the hardware 
(library calls are emitted instead), so this can be defined unconditionally. 
I'm currently working on D12148, which also sets this and _ARM_FP16_ARGS.


http://reviews.llvm.org/D12244



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Re: [PATCH] D12148: [ARM] Allow passing/returning of __fp16 arguments

[Oliver Stannard via cfe-commits]

olista01 removed rL LLVM as the repository for this revision.
olista01 updated this revision to Diff 32967.
olista01 added a comment.

Use a switch statement to check the target architecture.


http://reviews.llvm.org/D12148

Files:
  lib/Basic/Targets.cpp
  lib/CodeGen/TargetInfo.cpp
  lib/Driver/Tools.cpp
  test/CodeGen/arm-fp16-arguments.c
  test/Preprocessor/arm-acle-6.5.c
  test/Preprocessor/arm-target-features.c

Index: test/Preprocessor/arm-target-features.c
===
--- test/Preprocessor/arm-target-features.c
+++ test/Preprocessor/arm-target-features.c
@@ -5,6 +5,8 @@
 // CHECK: __ARM_FEATURE_CRC32 1
 // CHECK: __ARM_FEATURE_DIRECTED_ROUNDING 1
 // CHECK: __ARM_FEATURE_NUMERIC_MAXMIN 1
+// CHECK: __ARM_FP16_ARGS 1
+// CHECK: __ARM_FP16_FORMAT_IEEE 1
 
 // RUN: %clang -target armv7a-none-linux-gnu -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-V7 %s
 // CHECK-V7: __ARMEL__ 1
Index: test/Preprocessor/arm-acle-6.5.c
===
--- test/Preprocessor/arm-acle-6.5.c
+++ test/Preprocessor/arm-acle-6.5.c
@@ -1,6 +1,6 @@
 // RUN: %clang -target arm-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-DEFAULT
 
-// CHECK-DEFAULT-NOT: __ARM_FP
+// CHECK-DEFAULT-NOT: __ARM_FP 0x
 
 // RUN: %clang -target arm-eabi -mfpu=vfp -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP
 // RUN: %clang -target arm-eabi -mfpu=vfp3 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP
Index: test/CodeGen/arm-fp16-arguments.c
===
--- /dev/null
+++ test/CodeGen/arm-fp16-arguments.c
@@ -0,0 +1,21 @@
+// RUN: %clang_cc1 -triple armv7a--none-eabi -target-abi aapcs -mfloat-abi soft -fallow-half-arguments-and-returns -emit-llvm -o - -O1 %s | FileCheck %s --check-prefix=CHECK --check-prefix=SOFT
+// RUN: %clang_cc1 -triple armv7a--none-eabi -target-abi aapcs -mfloat-abi hard -fallow-half-arguments-and-returns -emit-llvm -o - -O1 %s | FileCheck %s --check-prefix=CHECK --check-prefix=HARD
+
+__fp16 g;
+
+void t1(__fp16 a) { g = a; }
+// SOFT: define void @t1(i32 [[PARAM:%.*]])
+// SOFT: [[TRUNC:%.*]] = trunc i32 [[PARAM]] to i16
+// HARD: define arm_aapcs_vfpcc void @t1(float [[PARAM:%.*]])
+// HARD: [[BITCAST:%.*]] = bitcast float [[PARAM]] to i32
+// HARD: [[TRUNC:%.*]] = trunc i32 [[BITCAST]] to i16
+// CHECK: store i16 [[TRUNC]], i16* bitcast (half* @g to i16*)
+
+__fp16 t2() { return g; }
+// SOFT: define i32 @t2()
+// HARD: define arm_aapcs_vfpcc float @t2()
+// CHECK: [[LOAD:%.*]] = load i16, i16* bitcast (half* @g to i16*)
+// CHECK: [[ZEXT:%.*]] = zext i16 [[LOAD]] to i32
+// SOFT: ret i32 [[ZEXT]]
+// HARD: [[BITCAST:%.*]] = bitcast i32 [[ZEXT]] to float
+// HARD: ret float [[BITCAST]]
Index: lib/Driver/Tools.cpp
===
--- lib/Driver/Tools.cpp
+++ lib/Driver/Tools.cpp
@@ -4250,9 +4250,19 @@
   CmdArgs.push_back(-mstack-probe-size=0);
   }
 
-  if (getToolChain().getArch() == llvm::Triple::aarch64 ||
-  getToolChain().getArch() == llvm::Triple::aarch64_be)
+  switch (getToolChain().getArch()) {
+  case llvm::Triple::aarch64:
+  case llvm::Triple::aarch64_be:
+  case llvm::Triple::arm:
+  case llvm::Triple::armeb:
+  case llvm::Triple::thumb:
+  case llvm::Triple::thumbeb:
 CmdArgs.push_back(-fallow-half-arguments-and-returns);
+break;
+
+  default:
+break;
+  }
 
   if (Arg *A = Args.getLastArg(options::OPT_mrestrict_it,
options::OPT_mno_restrict_it)) {
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -4714,6 +4714,15 @@
 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
   }
 
+  // __fp16 gets passed as if it were an int or float, but with the top 16 bits
+  // unspecified.
+  if (Ty-isHalfType()) {
+llvm::Type *ResType = IsEffectivelyAAPCS_VFP ?
+  llvm::Type::getFloatTy(getVMContext()) :
+  llvm::Type::getInt32Ty(getVMContext());
+return ABIArgInfo::getDirect(ResType);
+  }
+
   if (!isAggregateTypeForABI(Ty)) {
 // Treat an enum type as its underlying type.
 if (const EnumType *EnumTy = Ty-getAsEnumType()) {
@@ -4872,6 +4881,15 @@
 return ABIArgInfo::getIndirect(0);
   }
 
+  // __fp16 gets returned as if it were an int or float, but with the top 16
+  // bits unspecified.
+  if (RetTy-isHalfType()) {
+llvm::Type *ResType = IsEffectivelyAAPCS_VFP ?
+  llvm::Type::getFloatTy(getVMContext()) :
+  llvm::Type::getInt32Ty(getVMContext());
+return ABIArgInfo::getDirect(ResType);
+  }
+
   if (!isAggregateTypeForABI(RetTy)) {
 // Treat an enum type as its underlying type.
 if (const EnumType *EnumTy = RetTy-getAsEnumType())
Index: lib/Basic/Targets.cpp
===
--- 

[PATCH] D12148: [ARM] Allow passing/returning of __fp16 arguments

[Oliver Stannard via cfe-commits]

olista01 created this revision.
olista01 added a subscriber: cfe-commits.
olista01 set the repository for this revision to rL LLVM.
Herald added subscribers: rengolin, aemerson.

The ACLE (ARM C Language Extensions) 2.0 allows the __fp16 type to be
used as a functon argument or return type (ACLE 1.1 did not).

The current public release of the AAPCS (2.09) states that __fp16 values
should be converted to single-precision before being passed or returned,
but AAPCS 2.10 (to be released shortly) changes this, so that they are
passed in the least-significant 16 bits of either a GPR (for base AAPCS)
or a single-precision register (for AAPCS-VFP). This does not change how
arguments are passed if they get passed on the stack.

This patch brings clang up to compliance with the latest versions of
both of these specs.

We can now set the __ARM_FP16_ARGS ACLE predefine, and we have always
been able to set the __ARM_FP16_FORMAT_IEEE predefine (we do not support
the alternative format).

Repository:
  rL LLVM

http://reviews.llvm.org/D12148

Files:
  lib/Basic/Targets.cpp
  lib/CodeGen/TargetInfo.cpp
  lib/Driver/Tools.cpp
  test/CodeGen/arm-fp16-arguments.c
  test/Preprocessor/arm-acle-6.5.c
  test/Preprocessor/arm-target-features.c

Index: test/Preprocessor/arm-target-features.c
===
--- test/Preprocessor/arm-target-features.c
+++ test/Preprocessor/arm-target-features.c
@@ -5,6 +5,8 @@
 // CHECK: __ARM_FEATURE_CRC32 1
 // CHECK: __ARM_FEATURE_DIRECTED_ROUNDING 1
 // CHECK: __ARM_FEATURE_NUMERIC_MAXMIN 1
+// CHECK: __ARM_FP16_ARGS 1
+// CHECK: __ARM_FP16_FORMAT_IEEE 1
 
 // RUN: %clang -target armv7a-none-linux-gnu -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-V7 %s
 // CHECK-V7: __ARMEL__ 1
Index: test/Preprocessor/arm-acle-6.5.c
===
--- test/Preprocessor/arm-acle-6.5.c
+++ test/Preprocessor/arm-acle-6.5.c
@@ -1,6 +1,6 @@
 // RUN: %clang -target arm-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-DEFAULT
 
-// CHECK-DEFAULT-NOT: __ARM_FP
+// CHECK-DEFAULT-NOT: __ARM_FP 0x
 
 // RUN: %clang -target arm-eabi -mfpu=vfp -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP
 // RUN: %clang -target arm-eabi -mfpu=vfp3 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP
Index: test/CodeGen/arm-fp16-arguments.c
===
--- /dev/null
+++ test/CodeGen/arm-fp16-arguments.c
@@ -0,0 +1,21 @@
+// RUN: %clang_cc1 -triple armv7a--none-eabi -target-abi aapcs -mfloat-abi soft -fallow-half-arguments-and-returns -emit-llvm -o - -O1 %s | FileCheck %s --check-prefix=CHECK --check-prefix=SOFT
+// RUN: %clang_cc1 -triple armv7a--none-eabi -target-abi aapcs -mfloat-abi hard -fallow-half-arguments-and-returns -emit-llvm -o - -O1 %s | FileCheck %s --check-prefix=CHECK --check-prefix=HARD
+
+__fp16 g;
+
+void t1(__fp16 a) { g = a; }
+// SOFT: define void @t1(i32 [[PARAM:%.*]])
+// SOFT: [[TRUNC:%.*]] = trunc i32 [[PARAM]] to i16
+// HARD: define arm_aapcs_vfpcc void @t1(float [[PARAM:%.*]])
+// HARD: [[BITCAST:%.*]] = bitcast float [[PARAM]] to i32
+// HARD: [[TRUNC:%.*]] = trunc i32 [[BITCAST]] to i16
+// CHECK: store i16 [[TRUNC]], i16* bitcast (half* @g to i16*)
+
+__fp16 t2() { return g; }
+// SOFT: define i32 @t2()
+// HARD: define arm_aapcs_vfpcc float @t2()
+// CHECK: [[LOAD:%.*]] = load i16, i16* bitcast (half* @g to i16*)
+// CHECK: [[ZEXT:%.*]] = zext i16 [[LOAD]] to i32
+// SOFT: ret i32 [[ZEXT]]
+// HARD: [[BITCAST:%.*]] = bitcast i32 [[ZEXT]] to float
+// HARD: ret float [[BITCAST]]
Index: lib/Driver/Tools.cpp
===
--- lib/Driver/Tools.cpp
+++ lib/Driver/Tools.cpp
@@ -4251,7 +4251,11 @@
   }
 
   if (getToolChain().getArch() == llvm::Triple::aarch64 ||
-  getToolChain().getArch() == llvm::Triple::aarch64_be)
+  getToolChain().getArch() == llvm::Triple::aarch64_be ||
+  getToolChain().getArch() == llvm::Triple::arm ||
+  getToolChain().getArch() == llvm::Triple::armeb ||
+  getToolChain().getArch() == llvm::Triple::thumb ||
+  getToolChain().getArch() == llvm::Triple::thumbeb)
 CmdArgs.push_back(-fallow-half-arguments-and-returns);
 
   if (Arg *A = Args.getLastArg(options::OPT_mrestrict_it,
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -4714,6 +4714,15 @@
 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
   }
 
+  // __fp16 gets passed as if it were an int or float, but with the top 32 bits
+  // unspecified.
+  if (Ty-isHalfType()) {
+llvm::Type *ResType = IsEffectivelyAAPCS_VFP ?
+  llvm::Type::getFloatTy(getVMContext()) :
+  llvm::Type::getInt32Ty(getVMContext());
+return ABIArgInfo::getDirect(ResType);
+  }
+
   if (!isAggregateTypeForABI(Ty)) {
 // Treat an enum type as its 

Re: [PATCH] D12148: [ARM] Allow passing/returning of __fp16 arguments

[Oliver Stannard via cfe-commits]

olista01 updated this revision to Diff 32558.
olista01 added a comment.

Fixed typo


Repository:
  rL LLVM

http://reviews.llvm.org/D12148

Files:
  lib/Basic/Targets.cpp
  lib/CodeGen/TargetInfo.cpp
  lib/Driver/Tools.cpp
  test/CodeGen/arm-fp16-arguments.c
  test/Preprocessor/arm-acle-6.5.c
  test/Preprocessor/arm-target-features.c

Index: test/Preprocessor/arm-target-features.c
===
--- test/Preprocessor/arm-target-features.c
+++ test/Preprocessor/arm-target-features.c
@@ -5,6 +5,8 @@
 // CHECK: __ARM_FEATURE_CRC32 1
 // CHECK: __ARM_FEATURE_DIRECTED_ROUNDING 1
 // CHECK: __ARM_FEATURE_NUMERIC_MAXMIN 1
+// CHECK: __ARM_FP16_ARGS 1
+// CHECK: __ARM_FP16_FORMAT_IEEE 1
 
 // RUN: %clang -target armv7a-none-linux-gnu -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-V7 %s
 // CHECK-V7: __ARMEL__ 1
Index: test/Preprocessor/arm-acle-6.5.c
===
--- test/Preprocessor/arm-acle-6.5.c
+++ test/Preprocessor/arm-acle-6.5.c
@@ -1,6 +1,6 @@
 // RUN: %clang -target arm-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-DEFAULT
 
-// CHECK-DEFAULT-NOT: __ARM_FP
+// CHECK-DEFAULT-NOT: __ARM_FP 0x
 
 // RUN: %clang -target arm-eabi -mfpu=vfp -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP
 // RUN: %clang -target arm-eabi -mfpu=vfp3 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-SP-DP
Index: test/CodeGen/arm-fp16-arguments.c
===
--- /dev/null
+++ test/CodeGen/arm-fp16-arguments.c
@@ -0,0 +1,21 @@
+// RUN: %clang_cc1 -triple armv7a--none-eabi -target-abi aapcs -mfloat-abi soft -fallow-half-arguments-and-returns -emit-llvm -o - -O1 %s | FileCheck %s --check-prefix=CHECK --check-prefix=SOFT
+// RUN: %clang_cc1 -triple armv7a--none-eabi -target-abi aapcs -mfloat-abi hard -fallow-half-arguments-and-returns -emit-llvm -o - -O1 %s | FileCheck %s --check-prefix=CHECK --check-prefix=HARD
+
+__fp16 g;
+
+void t1(__fp16 a) { g = a; }
+// SOFT: define void @t1(i32 [[PARAM:%.*]])
+// SOFT: [[TRUNC:%.*]] = trunc i32 [[PARAM]] to i16
+// HARD: define arm_aapcs_vfpcc void @t1(float [[PARAM:%.*]])
+// HARD: [[BITCAST:%.*]] = bitcast float [[PARAM]] to i32
+// HARD: [[TRUNC:%.*]] = trunc i32 [[BITCAST]] to i16
+// CHECK: store i16 [[TRUNC]], i16* bitcast (half* @g to i16*)
+
+__fp16 t2() { return g; }
+// SOFT: define i32 @t2()
+// HARD: define arm_aapcs_vfpcc float @t2()
+// CHECK: [[LOAD:%.*]] = load i16, i16* bitcast (half* @g to i16*)
+// CHECK: [[ZEXT:%.*]] = zext i16 [[LOAD]] to i32
+// SOFT: ret i32 [[ZEXT]]
+// HARD: [[BITCAST:%.*]] = bitcast i32 [[ZEXT]] to float
+// HARD: ret float [[BITCAST]]
Index: lib/Driver/Tools.cpp
===
--- lib/Driver/Tools.cpp
+++ lib/Driver/Tools.cpp
@@ -4251,7 +4251,11 @@
   }
 
   if (getToolChain().getArch() == llvm::Triple::aarch64 ||
-  getToolChain().getArch() == llvm::Triple::aarch64_be)
+  getToolChain().getArch() == llvm::Triple::aarch64_be ||
+  getToolChain().getArch() == llvm::Triple::arm ||
+  getToolChain().getArch() == llvm::Triple::armeb ||
+  getToolChain().getArch() == llvm::Triple::thumb ||
+  getToolChain().getArch() == llvm::Triple::thumbeb)
 CmdArgs.push_back(-fallow-half-arguments-and-returns);
 
   if (Arg *A = Args.getLastArg(options::OPT_mrestrict_it,
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -4714,6 +4714,15 @@
 return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
   }
 
+  // __fp16 gets passed as if it were an int or float, but with the top 16 bits
+  // unspecified.
+  if (Ty-isHalfType()) {
+llvm::Type *ResType = IsEffectivelyAAPCS_VFP ?
+  llvm::Type::getFloatTy(getVMContext()) :
+  llvm::Type::getInt32Ty(getVMContext());
+return ABIArgInfo::getDirect(ResType);
+  }
+
   if (!isAggregateTypeForABI(Ty)) {
 // Treat an enum type as its underlying type.
 if (const EnumType *EnumTy = Ty-getAsEnumType()) {
@@ -4872,6 +4881,15 @@
 return ABIArgInfo::getIndirect(0);
   }
 
+  // __fp16 gets returned as if it were an int or float, but with the top 16
+  // bits unspecified.
+  if (RetTy-isHalfType()) {
+llvm::Type *ResType = IsEffectivelyAAPCS_VFP ?
+  llvm::Type::getFloatTy(getVMContext()) :
+  llvm::Type::getInt32Ty(getVMContext());
+return ABIArgInfo::getDirect(ResType);
+  }
+
   if (!isAggregateTypeForABI(RetTy)) {
 // Treat an enum type as its underlying type.
 if (const EnumType *EnumTy = RetTy-getAsEnumType())
Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -4625,6 +4625,10 @@
 // ACLE predefines.
 Builder.defineMacro(__ARM_ACLE, 200);
 
+// FP16 support (we currently only