[PATCH] D123235: [OpenMP] atomic compare fail : Parser & AST support

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.

Hi, it seems rG086b65340cca2648a2a91a0a47d28c7d9bafd1e5 
 causes 
build failure:

  llvm-project/clang/lib/Basic/OpenMPKinds.cpp:444:13: error: 97 enumeration 
values not handled in switch: 'OMPC_adjust_args', 'OMPC_affinity', 
'OMPC_align'... [-Werror,-Wswitch]
  switch (CK) {
  ^~
  1 error generated.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123235/new/

https://reviews.llvm.org/D123235

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D116016: [Clang] [PowerPC] Emit module flag for current float abi

[Qiu Chaofan via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG3e97db89ae8e: [PowerPC] Emit IR module flag for current 
float abi (authored by qiucf).

Changed prior to commit:
  https://reviews.llvm.org/D116016?vs=530843&id=557298#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116016/new/

https://reviews.llvm.org/D116016

Files:
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/CodeGenTypes.h
  clang/lib/CodeGen/Targets/PPC.cpp
  clang/test/CodeGen/ppc64-float-abi-attr.c

Index: clang/test/CodeGen/ppc64-float-abi-attr.c
===
--- /dev/null
+++ clang/test/CodeGen/ppc64-float-abi-attr.c
@@ -0,0 +1,17 @@
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu %s -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu %s -emit-llvm -mabi=ieeelongdouble -o - | FileCheck %s --check-prefix=IEEE
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu %s -emit-llvm -mlong-double-64 -o - | FileCheck %s --check-prefix=LDBL64
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu %s -emit-llvm -DNOLDBL -o - | FileCheck %s --check-prefix=NOLDBL
+
+#ifndef NOLDBL
+long double foo(long double a, long double b) {
+  return a + b;
+}
+#endif
+
+int bar() { return 1; }
+
+// CHECK: ![[#]] = !{i32 1, !"float-abi", !"doubledouble"}
+// IEEE: ![[#]] = !{i32 1, !"float-abi", !"ieeequad"}
+// LDBL64: ![[#]] = !{i32 1, !"float-abi", !"ieeedouble"}
+// NOLDBL-NOT: ![[#]] = !{i32 1, !"float-abi"
Index: clang/lib/CodeGen/Targets/PPC.cpp
===
--- clang/lib/CodeGen/Targets/PPC.cpp
+++ clang/lib/CodeGen/Targets/PPC.cpp
@@ -620,6 +620,9 @@
 
   bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
llvm::Value *Address) const override;
+  void emitTargetMetadata(CodeGen::CodeGenModule &CGM,
+  const llvm::MapVector
+  &MangledDeclNames) const override;
 };
 
 class PPC64TargetCodeGenInfo : public TargetCodeGenInfo {
@@ -940,6 +943,24 @@
  /*IsAIX*/ false);
 }
 
+void PPC64_SVR4_TargetCodeGenInfo::emitTargetMetadata(
+CodeGen::CodeGenModule &CGM,
+const llvm::MapVector &MangledDeclNames) const {
+  if (CGM.getTypes().isLongDoubleReferenced()) {
+llvm::LLVMContext &Ctx = CGM.getLLVMContext();
+const auto *flt = &CGM.getTarget().getLongDoubleFormat();
+if (flt == &llvm::APFloat::PPCDoubleDouble())
+  CGM.getModule().addModuleFlag(llvm::Module::Error, "float-abi",
+llvm::MDString::get(Ctx, "doubledouble"));
+else if (flt == &llvm::APFloat::IEEEquad())
+  CGM.getModule().addModuleFlag(llvm::Module::Error, "float-abi",
+llvm::MDString::get(Ctx, "ieeequad"));
+else if (flt == &llvm::APFloat::IEEEdouble())
+  CGM.getModule().addModuleFlag(llvm::Module::Error, "float-abi",
+llvm::MDString::get(Ctx, "ieeedouble"));
+  }
+}
+
 bool
 PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
 llvm::Value *Address) const {
Index: clang/lib/CodeGen/CodeGenTypes.h
===
--- clang/lib/CodeGen/CodeGenTypes.h
+++ clang/lib/CodeGen/CodeGenTypes.h
@@ -84,6 +84,9 @@
   /// a recursive struct conversion, set this to true.
   bool SkippedLayout;
 
+  /// True if any instance of long double types are used.
+  bool LongDoubleReferenced;
+
   /// This map keeps cache of llvm::Types and maps clang::Type to
   /// corresponding llvm::Type.
   llvm::DenseMap TypeCache;
@@ -289,6 +292,7 @@
   /// zero-initialized (in the C++ sense) with an LLVM zeroinitializer.
   bool isZeroInitializable(const RecordDecl *RD);
 
+  bool isLongDoubleReferenced() const { return LongDoubleReferenced; }
   bool isRecordLayoutComplete(const Type *Ty) const;
   unsigned getTargetAddressSpace(QualType T) const;
 };
Index: clang/lib/CodeGen/CodeGenTypes.cpp
===
--- clang/lib/CodeGen/CodeGenTypes.cpp
+++ clang/lib/CodeGen/CodeGenTypes.cpp
@@ -34,6 +34,7 @@
 Target(cgm.getTarget()), TheCXXABI(cgm.getCXXABI()),
 TheABIInfo(cgm.getTargetCodeGenInfo().getABIInfo()) {
   SkippedLayout = false;
+  LongDoubleReferenced = false;
 }
 
 CodeGenTypes::~CodeGenTypes() {
@@ -406,10 +407,12 @@
   Context.getLangOpts().NativeHalfType ||
   !Context.getTargetInfo().useFP16ConversionIntrinsics());
   break;
+case BuiltinType::LongDouble:
+  LongDoubleReferenced = true;
+  LLVM_FALLTHROUGH;
 case BuiltinType::BFloat16:
 case BuiltinType::Float:
 case BuiltinType::Double:
-case BuiltinType::LongDouble:
 case BuiltinType::Float128:
 ca

[PATCH] D158066: [PowerPC] Fix use of FPSCR builtins in smmintrin.h

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf abandoned this revision.
qiucf added a comment.

Migrated to https://github.com/llvm/llvm-project/pull/67299


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158066/new/

https://reviews.llvm.org/D158066

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D159159: [PowerPC] Disable float128 on AIX in Clang

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf abandoned this revision.
qiucf added a comment.

Migrated to https://github.com/llvm/llvm-project/pull/67298


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159159/new/

https://reviews.llvm.org/D159159

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D116016: [Clang] [PowerPC] Emit module flag for current float abi

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.

Gentle ping?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116016/new/

https://reviews.llvm.org/D116016

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D117181: [PowerPC] Use IEEE long double in proper toolchain

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf abandoned this revision.
qiucf added a comment.

Determining float ABI by system library without explicit options may cause 
confusion. Since Fedora has successfully switched using ieeelongdouble on 
ppc64le 
(https://developers.redhat.com/articles/2023/05/16/benefits-fedora-38-long-double-transition-ppc64le
 ), this patch is not so relevant.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117181/new/

https://reviews.llvm.org/D117181

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D158066: [PowerPC] Fix use of FPSCR builtins in smmintrin.h

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf updated this revision to Diff 555805.
qiucf added a comment.

- Add macro alias to `mffs` `mffsl` `mtfsf` and `set_fpscr_rn`, although they 
don't work in freestanding mode
- Add C++ run lines to intrinsics tests. To avoid further messing codegen 
checks, make them run under `-fsyntax-only`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158066/new/

https://reviews.llvm.org/D158066

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/ppc_wrappers/smmintrin.h
  clang/test/CodeGen/PowerPC/builtins-ppc.c
  clang/test/CodeGen/PowerPC/ppc-emmintrin.c
  clang/test/CodeGen/PowerPC/ppc-mmintrin.c
  clang/test/CodeGen/PowerPC/ppc-pmmintrin.c
  clang/test/CodeGen/PowerPC/ppc-smmintrin.c
  clang/test/CodeGen/PowerPC/ppc-tmmintrin.c
  clang/test/CodeGen/PowerPC/ppc-x86gprintrin.c

Index: clang/test/CodeGen/PowerPC/ppc-x86gprintrin.c
===
--- clang/test/CodeGen/PowerPC/ppc-x86gprintrin.c
+++ clang/test/CodeGen/PowerPC/ppc-x86gprintrin.c
@@ -12,6 +12,9 @@
 // RUN: %clang -S -emit-llvm -target powerpc64-ibm-aix -mcpu=pwr7 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s
 
+// RUN: %clang -x c++ -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr7 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -fsyntax-only
+
 #include 
 
 unsigned short us;
Index: clang/test/CodeGen/PowerPC/ppc-tmmintrin.c
===
--- clang/test/CodeGen/PowerPC/ppc-tmmintrin.c
+++ clang/test/CodeGen/PowerPC/ppc-tmmintrin.c
@@ -13,6 +13,9 @@
 // RUN: %clang -S -emit-llvm -target powerpc64-ibm-aix -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE
 
+// RUN: %clang -x c++ -S -emit-llvm -target powerpc64le-gnu-linux -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -fsyntax-only
+
 #include 
 
 __m64 res, m1, m2;
Index: clang/test/CodeGen/PowerPC/ppc-smmintrin.c
===
--- clang/test/CodeGen/PowerPC/ppc-smmintrin.c
+++ clang/test/CodeGen/PowerPC/ppc-smmintrin.c
@@ -15,6 +15,11 @@
 // RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefix=P10
 
+// RUN: %clang -x c++ -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -fsyntax-only
+// RUN: %clang -x c++ -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -fsyntax-only
+
 // RUN: %clang -S -emit-llvm -target powerpc64le-unknown-freebsd13.0 -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s
 // RUN: %clang -S -emit-llvm -target powerpc64-unknown-freebsd13.0 -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
@@ -239,44 +244,48 @@
 // CHECK-LABEL: @test_round
 
 // CHECK-LABEL: define available_externally <4 x float> @_mm_round_ps(<4 x float> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef signext %{{[0-9a-zA-Z_.]+}})
-// CHECK: call signext i32 @__builtin_mffs()
-// CHECK: call signext i32 @__builtin_mtfsf(i32 noundef signext 3, double noundef %{{[0-9a-zA-Z_.]+}})
+// CHECK: call double @llvm.ppc.readflm()
+// CHECK: call void @llvm.ppc.mtfsf(i32 3, double %{{[0-9a-zA-Z_.]+}})
 // CHECK: %{{[0-9a-zA-Z_.]+}} = call <4 x float> asm "", "=^wa,0"
-// CHECK: call signext i32 @__builtin_mffsl()
-// CHECK: call signext i32 @__builtin_set_fpscr_rn(i32 noundef signext 0)
+// CHECK: call double @llvm.ppc.readflm()
+// P10: call double @llvm.ppc.mffsl()
+// CHECK: call double @llvm.ppc.setrnd(i32 0)
 // CHECK: %{{[0-9a-zA-Z_.]+}} = call <4 x float> asm "", "=^wa,0"
 // CHECK: call <4 x float> @vec_rint(float vector[4])
 // CHECK: call void asm sideeffect "", "^wa"
-// CHECK: call signext i32 @__builtin_set_fpscr_rn(i64 noundef %{{[0-9a-zA-Z_.]+}})
+// CHECK: call double @llvm.ppc.setrnd(i32 %{{[0-9a-zA-Z_.]+}})
 // CHECK: call <4 x float> @vec_floor(float vector[4])
 // CHECK: call <4 x float> @vec_ceil(float vector[4])
 // CHECK: call <4 x float> @vec_trunc(float vector[4])
 // CHECK: call <4 x float> @vec_rint(float vector[4])
 // CHECK: call void asm sideeffect "", "^wa"
-// CHECK: call signext i32 @__builtin_

[PATCH] D158065: [PowerPC] Implement builtin for mffsl

[Qiu Chaofan via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG082c5d7f63c4: [PowerPC] Implement builtin for mffsl 
(authored by qiucf).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158065/new/

https://reviews.llvm.org/D158065

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/test/CodeGen/PowerPC/builtins-ppc.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/read-set-flm.ll


Index: llvm/test/CodeGen/PowerPC/read-set-flm.ll
===
--- llvm/test/CodeGen/PowerPC/read-set-flm.ll
+++ llvm/test/CodeGen/PowerPC/read-set-flm.ll
@@ -148,8 +148,19 @@
   ret void
 }
 
+define double @mffsl() {
+; CHECK-LABEL: mffsl:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mffsl 1
+; CHECK-NEXT:blr
+entry:
+  %x = call double @llvm.ppc.mffsl()
+  ret double %x
+}
+
 declare void @effect_func()
 declare void @readonly_func() #1
+declare double @llvm.ppc.mffsl()
 declare double @llvm.ppc.readflm()
 declare double @llvm.ppc.setflm(double)
 declare double @llvm.experimental.constrained.fadd.f64(double, double, 
metadata, metadata)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3180,6 +3180,7 @@
   (TCRETURNri CTRRC:$dst, imm:$imm)>;
 
 def : Pat<(int_ppc_readflm), (MFFS)>;
+def : Pat<(int_ppc_mffsl), (MFFSL)>;
 
 // Hi and Lo for Darwin Global Addresses.
 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -33,6 +33,10 @@
   def int_ppc_readflm : ClangBuiltin<"__builtin_readflm">,
 DefaultAttrsIntrinsic<[llvm_double_ty], [],
   [IntrNoMerge, 
IntrHasSideEffects]>;
+  def int_ppc_mffsl : ClangBuiltin<"__builtin_ppc_mffsl">,
+  DefaultAttrsIntrinsic<[llvm_double_ty], [],
+[IntrNoMerge, IntrHasSideEffects]>;
+
   // Set FPSCR register, and return previous content
   def int_ppc_setflm : ClangBuiltin<"__builtin_setflm">,
DefaultAttrsIntrinsic<[llvm_double_ty], 
[llvm_double_ty],
Index: clang/test/CodeGen/PowerPC/builtins-ppc.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc.c
@@ -35,6 +35,11 @@
 
   // CHECK: call double @llvm.ppc.setflm(double %1)
   res = __builtin_setflm(res);
+
+#ifdef _ARCH_PWR9
+  // P9: call double @llvm.ppc.mffsl()
+  res = __builtin_ppc_mffsl();
+#endif
 }
 
 double test_builtin_unpack_ldbl(long double x) {
Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -151,6 +151,7 @@
 TARGET_BUILTIN(__builtin_ppc_extract_sig, "ULLid", "", "power9-vector")
 BUILTIN(__builtin_ppc_mtfsb0, "vUIi", "")
 BUILTIN(__builtin_ppc_mtfsb1, "vUIi", "")
+TARGET_BUILTIN(__builtin_ppc_mffsl, "d", "", "isa-v30-instructions")
 BUILTIN(__builtin_ppc_mtfsf, "vUIiUi", "")
 BUILTIN(__builtin_ppc_mtfsfi, "vUIiUIi", "")
 TARGET_BUILTIN(__builtin_ppc_insert_exp, "ddULLi", "", "power9-vector")


Index: llvm/test/CodeGen/PowerPC/read-set-flm.ll
===
--- llvm/test/CodeGen/PowerPC/read-set-flm.ll
+++ llvm/test/CodeGen/PowerPC/read-set-flm.ll
@@ -148,8 +148,19 @@
   ret void
 }
 
+define double @mffsl() {
+; CHECK-LABEL: mffsl:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mffsl 1
+; CHECK-NEXT:blr
+entry:
+  %x = call double @llvm.ppc.mffsl()
+  ret double %x
+}
+
 declare void @effect_func()
 declare void @readonly_func() #1
+declare double @llvm.ppc.mffsl()
 declare double @llvm.ppc.readflm()
 declare double @llvm.ppc.setflm(double)
 declare double @llvm.experimental.constrained.fadd.f64(double, double, metadata, metadata)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3180,6 +3180,7 @@
   (TCRETURNri CTRRC:$dst, imm:$imm)>;
 
 def : Pat<(int_ppc_readflm), (MFFS)>;
+def : Pat<(int_ppc_mffsl), (MFFSL)>;
 
 // Hi and Lo for Darwin Global Addresses.
 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/l

[PATCH] D156076: [PowerPC][Clang] Remove constraint for initial-exec TLS mode on AIX

[Qiu Chaofan via Phabricator via cfe-commits]

This revision was not accepted when it landed; it landed in state "Needs 
Revision".
This revision was automatically updated to reflect the committed changes.
Closed by commit rG880f39af6115: [Clang] Enable AIX initial-exec TLS mode 
(authored by qiucf).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156076/new/

https://reviews.llvm.org/D156076

Files:
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/PowerPC/aix-tls-model.cpp
  clang/test/Sema/aix-attr-tls_model.c


Index: clang/test/Sema/aix-attr-tls_model.c
===
--- clang/test/Sema/aix-attr-tls_model.c
+++ clang/test/Sema/aix-attr-tls_model.c
@@ -7,5 +7,5 @@
 
 static __thread int y __attribute((tls_model("global-dynamic"))); // no-warning
 static __thread int y __attribute((tls_model("local-dynamic"))); // 
expected-error {{TLS model 'local-dynamic' is not yet supported on AIX}}
-static __thread int y __attribute((tls_model("initial-exec"))); // 
expected-error {{TLS model 'initial-exec' is not yet supported on AIX}}
+static __thread int y __attribute((tls_model("initial-exec"))); // no-warning
 static __thread int y __attribute((tls_model("local-exec"))); // no-warning
Index: clang/test/CodeGen/PowerPC/aix-tls-model.cpp
===
--- clang/test/CodeGen/PowerPC/aix-tls-model.cpp
+++ clang/test/CodeGen/PowerPC/aix-tls-model.cpp
@@ -1,12 +1,12 @@
 // RUN: %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 -emit-llvm 
-o - | FileCheck %s -check-prefix=CHECK-GD
 // RUN: %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 
-ftls-model=global-dynamic -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD
 // RUN: not %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 
-ftls-model=local-dynamic -emit-llvm 2>&1 | FileCheck %s 
-check-prefix=CHECK-LD-ERROR
-// RUN: not %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 
-ftls-model=initial-exec -emit-llvm  2>&1 | FileCheck %s 
-check-prefix=CHECK-IE-ERROR
+// RUN: %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 
-ftls-model=initial-exec -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-IE
 // RUN: %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 
-ftls-model=local-exec -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-LE
 // RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 
-emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD
 // RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 
-ftls-model=global-dynamic -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD
 // RUN: not %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 
-ftls-model=local-dynamic -emit-llvm 2>&1 | FileCheck %s 
-check-prefix=CHECK-LD-ERROR
-// RUN: not %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 
-ftls-model=initial-exec -emit-llvm  2>&1 | FileCheck %s 
-check-prefix=CHECK-IE-ERROR
+// RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 
-ftls-model=initial-exec -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-IE
 // RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 
-ftls-model=local-exec -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-LE
 
 int z1 = 0;
@@ -22,7 +22,10 @@
 // CHECK-GD: @x ={{.*}} thread_local global i32 0
 // CHECK-GD: @_ZZ1fvE1y = internal thread_local global i32 0
 // CHECK-LD-ERROR:  error: TLS model 'local-dynamic' is not yet supported on 
AIX
-// CHECK-IE-ERROR:  error: TLS model 'initial-exec' is not yet supported on AIX
+// CHECK-IE: @z1 ={{.*}} global i32 0
+// CHECK-IE: @z2 ={{.*}} global i32 0
+// CHECK-IE: @x ={{.*}} thread_local(initialexec) global i32 0
+// CHECK-IE: @_ZZ1fvE1y = internal thread_local(initialexec) global i32 0
 // CHECK-LE: @z1 ={{.*}} global i32 0
 // CHECK-LE: @z2 ={{.*}} global i32 0
 // CHECK-LE: @x ={{.*}} thread_local(localexec) global i32 0
Index: clang/lib/Sema/SemaDeclAttr.cpp
===
--- clang/lib/Sema/SemaDeclAttr.cpp
+++ clang/lib/Sema/SemaDeclAttr.cpp
@@ -2054,7 +2054,7 @@
   }
 
   if (S.Context.getTargetInfo().getTriple().isOSAIX() &&
-  Model != "global-dynamic" && Model != "local-exec") {
+  Model == "local-dynamic") {
 S.Diag(LiteralLoc, diag::err_aix_attr_unsupported_tls_model) << Model;
 return;
   }
Index: clang/lib/Frontend/CompilerInvocation.cpp
===
--- clang/lib/Frontend/CompilerInvocation.cpp
+++ clang/lib/Frontend/CompilerInvocation.cpp
@@ -1877,7 +1877,7 @@
   if (Arg *A = Args.getLastArg(OPT_ftlsmodel_EQ)) {
 if (T.isOSAIX()) {
   StringRef Name = A->getValue();
-  if (Name != "global-dynamic" && Name != "local-exec")
+  if (Name == "local-dynamic")
 Diags.Report(diag::err_aix_unsupported_tls_model) << Name;
 }
   }


Index: clang/test/Sema/ai

[PATCH] D156076: [PowerPC][Clang] Remove constraint for initial-exec TLS mode on AIX

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.

Ping


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156076/new/

https://reviews.llvm.org/D156076

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D159159: [PowerPC] Disable float128 on AIX in Clang

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf created this revision.
qiucf added a reviewer: PowerPC.
Herald added subscribers: steven.zhang, shchenz, kbarton, nemanjai.
Herald added a project: All.
qiucf requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

PowerPC AIX backend does not support float128 at all. Diagnose even when 
specifying `-mfloat128` to avoid backend crash.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D159159

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/Sema/128bitfloat.cpp


Index: clang/test/Sema/128bitfloat.cpp
===
--- clang/test/Sema/128bitfloat.cpp
+++ clang/test/Sema/128bitfloat.cpp
@@ -1,6 +1,7 @@
 // RUN: %clang_cc1 -verify -std=gnu++11 %s
 // RUN: %clang_cc1 -verify -std=c++11 %s
 // RUN: %clang_cc1 -triple powerpc64-linux -verify -std=c++11 %s
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix -target-feature +float128 -verify 
-std=c++11 %s
 // RUN: %clang_cc1 -triple i686-windows-gnu -verify -std=c++11 %s
 // RUN: %clang_cc1 -triple x86_64-windows-gnu -verify -std=c++11 %s
 // RUN: %clang_cc1 -triple x86_64-windows-msvc -verify -std=c++11 %s
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -52,7 +52,7 @@
   HasDirectMove = true;
 } else if (Feature == "+htm") {
   HasHTM = true;
-} else if (Feature == "+float128") {
+} else if (Feature == "+float128" && !getTriple().isOSAIX()) {
   HasFloat128 = true;
 } else if (Feature == "+power9-vector") {
   HasP9Vector = true;


Index: clang/test/Sema/128bitfloat.cpp
===
--- clang/test/Sema/128bitfloat.cpp
+++ clang/test/Sema/128bitfloat.cpp
@@ -1,6 +1,7 @@
 // RUN: %clang_cc1 -verify -std=gnu++11 %s
 // RUN: %clang_cc1 -verify -std=c++11 %s
 // RUN: %clang_cc1 -triple powerpc64-linux -verify -std=c++11 %s
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix -target-feature +float128 -verify -std=c++11 %s
 // RUN: %clang_cc1 -triple i686-windows-gnu -verify -std=c++11 %s
 // RUN: %clang_cc1 -triple x86_64-windows-gnu -verify -std=c++11 %s
 // RUN: %clang_cc1 -triple x86_64-windows-msvc -verify -std=c++11 %s
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -52,7 +52,7 @@
   HasDirectMove = true;
 } else if (Feature == "+htm") {
   HasHTM = true;
-} else if (Feature == "+float128") {
+} else if (Feature == "+float128" && !getTriple().isOSAIX()) {
   HasFloat128 = true;
 } else if (Feature == "+power9-vector") {
   HasP9Vector = true;
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D158484: [PowerPC][altivec] Correct modulo number of vec_promote on vector char

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf accepted this revision as: qiucf.
qiucf added a comment.
This revision is now accepted and ready to land.

Thanks for the fix.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158484/new/

https://reviews.llvm.org/D158484

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D158487: [PowerPC][altivec] Optimize codegen of vec_promote

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added inline comments.



Comment at: clang/lib/Headers/altivec.h:14662
+  vector unsigned char __res =
+  __builtin_shufflevector(__zero, __zero, -1, -1, -1, -1, -1, -1, -1, -1,
+  -1, -1, -1, -1, -1, -1, -1, -1);

Could we just define it without initialization? This can also make undefined 
vector.



Comment at: llvm/test/CodeGen/PowerPC/vec-promote.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 2
+; RUN: llc -mtriple=powerpc64-unknown-unknown -verify-machineinstrs -mcpu=pwr8 
\

We don't need this file because (1) no backend codegen changed; (2) further 
changes to `altivec.h` will not change this file.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158487/new/

https://reviews.llvm.org/D158487

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D158066: [PowerPC] Fix use of FPSCR builtins in smmintrin.h

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.

In D158066#4601785 , @nemanjai wrote:

> It should be perfectly fine to provide pre-defined macros for these to match 
> GCC on PowerPC. The reason we went with the macro solution is to avoid 
> polluting the builtins namespace for other targets.
>
> Also, please add some C++ tests for these PPC wrappers so that we aren't 
> surprised again when someone tries to use these in their C++ code.

It seems these macros do not always work for all PowerPC targets:

  // -target=ppc64le -mcpu=power9 do not work
  // -target=ppc64le-unknown-linux-gnu -mcpu=power9 work
  long calldarn(void) { return __darn(); }


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158066/new/

https://reviews.llvm.org/D158066

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D158066: [PowerPC] Fix use of FPSCR builtins in smmintrin.h

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added subscribers: quinnp, amyk.
qiucf added a comment.

CC @amyk @quinnp Any comments about the naming?

I see some `__builtin_ppc_xxx` are aliased into `__builtin_xxx` by 
`defineXLCompatMacros`. But these are not XL-compatible builtins, and the 
macros do not always work.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158066/new/

https://reviews.llvm.org/D158066

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D119407: [PowerPC] [Clang] Add SSE4 and BMI compatible intrinsics implementation for PowerPC

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf marked 2 inline comments as done.
qiucf added a comment.

Thanks, fixed by rG2459ed67805c 
. 
`nmmintrin.h` just includes `smmintrin.h` so it's not critical.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119407/new/

https://reviews.llvm.org/D119407

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D158066: [PowerPC] Fix use of FPSCR builtins in smmintrin.h

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf created this revision.
qiucf added reviewers: nemanjai, shchenz, stefanp, PowerPC.
Herald added a subscriber: kbarton.
Herald added a project: All.
qiucf requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

`smmintrin.h` uses `__builtin_mffs`, `__builtin_mffsl`, `__builtin_mtfsf` and 
`__builtin_set_fpscr_rn`. This patch replaces the uses with `ppc` prefix and 
implement the missing ones.

This fixes issue 64664.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D158066

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/ppc_wrappers/smmintrin.h
  clang/test/CodeGen/PowerPC/builtins-ppc.c
  clang/test/CodeGen/PowerPC/ppc-smmintrin.c

Index: clang/test/CodeGen/PowerPC/ppc-smmintrin.c
===
--- clang/test/CodeGen/PowerPC/ppc-smmintrin.c
+++ clang/test/CodeGen/PowerPC/ppc-smmintrin.c
@@ -239,44 +239,48 @@
 // CHECK-LABEL: @test_round
 
 // CHECK-LABEL: define available_externally <4 x float> @_mm_round_ps(<4 x float> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef signext %{{[0-9a-zA-Z_.]+}})
-// CHECK: call signext i32 @__builtin_mffs()
-// CHECK: call signext i32 @__builtin_mtfsf(i32 noundef signext 3, double noundef %{{[0-9a-zA-Z_.]+}})
+// CHECK: call double @llvm.ppc.readflm()
+// CHECK: call void @llvm.ppc.mtfsf(i32 3, double %{{[0-9a-zA-Z_.]+}})
 // CHECK: %{{[0-9a-zA-Z_.]+}} = call <4 x float> asm "", "=^wa,0"
-// CHECK: call signext i32 @__builtin_mffsl()
-// CHECK: call signext i32 @__builtin_set_fpscr_rn(i32 noundef signext 0)
+// CHECK: call double @llvm.ppc.readflm()
+// P10: call double @llvm.ppc.mffsl()
+// CHECK: call double @llvm.ppc.setrnd(i32 0)
 // CHECK: %{{[0-9a-zA-Z_.]+}} = call <4 x float> asm "", "=^wa,0"
 // CHECK: call <4 x float> @vec_rint(float vector[4])
 // CHECK: call void asm sideeffect "", "^wa"
-// CHECK: call signext i32 @__builtin_set_fpscr_rn(i64 noundef %{{[0-9a-zA-Z_.]+}})
+// CHECK: call double @llvm.ppc.setrnd(i32 %{{[0-9a-zA-Z_.]+}})
 // CHECK: call <4 x float> @vec_floor(float vector[4])
 // CHECK: call <4 x float> @vec_ceil(float vector[4])
 // CHECK: call <4 x float> @vec_trunc(float vector[4])
 // CHECK: call <4 x float> @vec_rint(float vector[4])
 // CHECK: call void asm sideeffect "", "^wa"
-// CHECK: call signext i32 @__builtin_mffsl()
-// CHECK: call signext i32 @__builtin_mtfsf(i32 noundef signext 3, double noundef %{{[0-9a-zA-Z_.]+}})
+// CHECK: call double @llvm.ppc.readflm()
+// P10: call double @llvm.ppc.mffsl()
+// CHECK: call void @llvm.ppc.mtfsf(i32 3, double %{{[0-9a-zA-Z_.]+}})
 
 // CHECK-LABEL: define available_externally <4 x float> @_mm_round_ss(<4 x float> noundef %{{[0-9a-zA-Z_.]+}}, <4 x float> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef signext %{{[0-9a-zA-Z_.]+}})
 // CHECK: call <4 x float> @_mm_round_ps(<4 x float> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef signext %{{[0-9a-zA-Z_.]+}})
 // CHECK: extractelement <4 x float> %{{[0-9a-zA-Z_.]+}}, i32 0
 
 // CHECK-LABEL: define available_externally <2 x double> @_mm_round_pd(<2 x double> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef signext %{{[0-9a-zA-Z_.]+}})
-// CHECK: call signext i32 @__builtin_mffs()
-// CHECK: call signext i32 @__builtin_mtfsf(i32 noundef signext 3, double noundef %{{[0-9a-zA-Z_.]+}})
+// CHECK: call double @llvm.ppc.readflm()
+// CHECK: call void @llvm.ppc.mtfsf(i32 3, double %{{[0-9a-zA-Z_.]+}})
 // CHECK: %{{[0-9a-zA-Z_.]+}} = call <2 x double> asm "", "=^wa,0"
-// CHECK: call signext i32 @__builtin_mffsl()
-// CHECK: call signext i32 @__builtin_set_fpscr_rn(i32 noundef signext 0)
+// CHECK: call double @llvm.ppc.readflm()
+// P10: call double @llvm.ppc.mffsl()
+// CHECK: call double @llvm.ppc.setrnd(i32 0)
 // CHECK: %{{[0-9a-zA-Z_.]+}} = call <2 x double> asm "", "=^wa,0"
 // CHECK: call <2 x double> @vec_rint(double vector[2])
 // CHECK: call void asm sideeffect "", "^wa"
-// CHECK: call signext i32 @__builtin_set_fpscr_rn(i64 noundef %{{[0-9a-zA-Z_.]+}})
+// CHECK: call double @llvm.ppc.setrnd(i32 %{{[0-9a-zA-Z_.]+}})
 // CHECK: call <2 x double> @vec_floor(double vector[2])
 // CHECK: call <2 x double> @vec_ceil(double vector[2])
 // CHECK: call <2 x double> @vec_trunc(double vector[2])
 // CHECK: call <2 x double> @vec_rint(double vector[2])
 // CHECK: call void asm sideeffect "", "^wa"
-// CHECK: call signext i32 @__builtin_mffsl()
-// CHECK: call signext i32 @__builtin_mtfsf(i32 noundef signext 3, double noundef %{{[0-9a-zA-Z_.]+}})
+// CHECK: call double @llvm.ppc.readflm()
+// P10: call double @llvm.ppc.mffsl()
+// CHECK: call void @llvm.ppc.mtfsf(i32 3, double %{{[0-9a-zA-Z_.]+}})
 
 // CHECK-LABEL: define available_externally <2 x double> @_mm_round_sd(<2 x double> noundef %{{[0-9a-zA-Z_.]+}}, <2 x double> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef signext %{{[0-9a-zA-Z_.]+}})
 // CHECK: call <2 x double> @_mm_round_pd(<2 x double> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef signext %{{

[PATCH] D158065: [PowerPC] Implement builtin for mffsl

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf created this revision.
qiucf added reviewers: nemanjai, stefanp, shchenz, PowerPC.
Herald added subscribers: kbarton, hiraditya.
Herald added a project: All.
qiucf requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

`mffsl` is available since ISA 3.0.

GCC emits extra code to support `__builtin_mffsl` on targets earlier than 
Power9, while this patch doesn't do it. In this patch it is actually named 
`__builtin_ppc_mffsl` to follow our convention.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D158065

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/test/CodeGen/PowerPC/builtins-ppc.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/read-set-flm.ll


Index: llvm/test/CodeGen/PowerPC/read-set-flm.ll
===
--- llvm/test/CodeGen/PowerPC/read-set-flm.ll
+++ llvm/test/CodeGen/PowerPC/read-set-flm.ll
@@ -148,8 +148,19 @@
   ret void
 }
 
+define double @mffsl() {
+; CHECK-LABEL: mffsl:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mffsl 1
+; CHECK-NEXT:blr
+entry:
+  %x = call double @llvm.ppc.mffsl()
+  ret double %x
+}
+
 declare void @effect_func()
 declare void @readonly_func() #1
+declare double @llvm.ppc.mffsl()
 declare double @llvm.ppc.readflm()
 declare double @llvm.ppc.setflm(double)
 declare double @llvm.experimental.constrained.fadd.f64(double, double, 
metadata, metadata)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3180,6 +3180,7 @@
   (TCRETURNri CTRRC:$dst, imm:$imm)>;
 
 def : Pat<(int_ppc_readflm), (MFFS)>;
+def : Pat<(int_ppc_mffsl), (MFFSL)>;
 
 // Hi and Lo for Darwin Global Addresses.
 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -33,6 +33,10 @@
   def int_ppc_readflm : ClangBuiltin<"__builtin_readflm">,
 DefaultAttrsIntrinsic<[llvm_double_ty], [],
   [IntrNoMerge, 
IntrHasSideEffects]>;
+  def int_ppc_mffsl : ClangBuiltin<"__builtin_ppc_mffsl">,
+  DefaultAttrsIntrinsic<[llvm_double_ty], [],
+[IntrNoMerge, IntrHasSideEffects]>;
+
   // Set FPSCR register, and return previous content
   def int_ppc_setflm : ClangBuiltin<"__builtin_setflm">,
DefaultAttrsIntrinsic<[llvm_double_ty], 
[llvm_double_ty],
Index: clang/test/CodeGen/PowerPC/builtins-ppc.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc.c
@@ -35,6 +35,11 @@
 
   // CHECK: call double @llvm.ppc.setflm(double %1)
   res = __builtin_setflm(res);
+
+#ifdef _ARCH_PWR9
+  // P9: call double @llvm.ppc.mffsl()
+  res = __builtin_ppc_mffsl();
+#endif
 }
 
 double test_builtin_unpack_ldbl(long double x) {
Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -151,6 +151,7 @@
 TARGET_BUILTIN(__builtin_ppc_extract_sig, "ULLid", "", "power9-vector")
 BUILTIN(__builtin_ppc_mtfsb0, "vUIi", "")
 BUILTIN(__builtin_ppc_mtfsb1, "vUIi", "")
+TARGET_BUILTIN(__builtin_ppc_mffsl, "d", "", "isa-v30-instructions")
 BUILTIN(__builtin_ppc_mtfsf, "vUIiUi", "")
 BUILTIN(__builtin_ppc_mtfsfi, "vUIiUIi", "")
 TARGET_BUILTIN(__builtin_ppc_insert_exp, "ddULLi", "", "power9-vector")


Index: llvm/test/CodeGen/PowerPC/read-set-flm.ll
===
--- llvm/test/CodeGen/PowerPC/read-set-flm.ll
+++ llvm/test/CodeGen/PowerPC/read-set-flm.ll
@@ -148,8 +148,19 @@
   ret void
 }
 
+define double @mffsl() {
+; CHECK-LABEL: mffsl:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mffsl 1
+; CHECK-NEXT:blr
+entry:
+  %x = call double @llvm.ppc.mffsl()
+  ret double %x
+}
+
 declare void @effect_func()
 declare void @readonly_func() #1
+declare double @llvm.ppc.mffsl()
 declare double @llvm.ppc.readflm()
 declare double @llvm.ppc.setflm(double)
 declare double @llvm.experimental.constrained.fadd.f64(double, double, metadata, metadata)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3180,6 +3180,7 @@
   (TCRETURNri CTRRC:$dst, imm:$imm)>;
 
 def : Pat<(int_ppc_readflm), (MFFS)>;
+def : Pat<(int_ppc_mffsl), (

[PATCH] D156076: [PowerPC][Clang] Remove constraint for initial-exec TLS mode on AIX

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf created this revision.
qiucf added reviewers: stefanp, shchenz, amyk, tingwang, PowerPC.
Herald added a subscriber: nemanjai.
Herald added a reviewer: aaron.ballman.
Herald added a project: All.
qiucf requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D156076

Files:
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/PowerPC/aix-tls-model.cpp
  clang/test/Sema/aix-attr-tls_model.c


Index: clang/test/Sema/aix-attr-tls_model.c
===
--- clang/test/Sema/aix-attr-tls_model.c
+++ clang/test/Sema/aix-attr-tls_model.c
@@ -7,5 +7,5 @@
 
 static __thread int y __attribute((tls_model("global-dynamic"))); // no-warning
 static __thread int y __attribute((tls_model("local-dynamic"))); // 
expected-error {{TLS model 'local-dynamic' is not yet supported on AIX}}
-static __thread int y __attribute((tls_model("initial-exec"))); // 
expected-error {{TLS model 'initial-exec' is not yet supported on AIX}}
+static __thread int y __attribute((tls_model("initial-exec"))); // no-warning
 static __thread int y __attribute((tls_model("local-exec"))); // no-warning
Index: clang/test/CodeGen/PowerPC/aix-tls-model.cpp
===
--- clang/test/CodeGen/PowerPC/aix-tls-model.cpp
+++ clang/test/CodeGen/PowerPC/aix-tls-model.cpp
@@ -1,12 +1,12 @@
 // RUN: %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 -emit-llvm 
-o - | FileCheck %s -check-prefix=CHECK-GD
 // RUN: %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 
-ftls-model=global-dynamic -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD
 // RUN: not %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 
-ftls-model=local-dynamic -emit-llvm 2>&1 | FileCheck %s 
-check-prefix=CHECK-LD-ERROR
-// RUN: not %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 
-ftls-model=initial-exec -emit-llvm  2>&1 | FileCheck %s 
-check-prefix=CHECK-IE-ERROR
+// RUN: %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 
-ftls-model=initial-exec -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-IE
 // RUN: %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 
-ftls-model=local-exec -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-LE
 // RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 
-emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD
 // RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 
-ftls-model=global-dynamic -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD
 // RUN: not %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 
-ftls-model=local-dynamic -emit-llvm 2>&1 | FileCheck %s 
-check-prefix=CHECK-LD-ERROR
-// RUN: not %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 
-ftls-model=initial-exec -emit-llvm  2>&1 | FileCheck %s 
-check-prefix=CHECK-IE-ERROR
+// RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 
-ftls-model=initial-exec -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-IE
 // RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 
-ftls-model=local-exec -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-LE
 
 int z1 = 0;
@@ -22,7 +22,10 @@
 // CHECK-GD: @x ={{.*}} thread_local global i32 0
 // CHECK-GD: @_ZZ1fvE1y = internal thread_local global i32 0
 // CHECK-LD-ERROR:  error: TLS model 'local-dynamic' is not yet supported on 
AIX
-// CHECK-IE-ERROR:  error: TLS model 'initial-exec' is not yet supported on AIX
+// CHECK-IE: @z1 ={{.*}} global i32 0
+// CHECK-IE: @z2 ={{.*}} global i32 0
+// CHECK-IE: @x ={{.*}} thread_local(initialexec) global i32 0
+// CHECK-IE: @_ZZ1fvE1y = internal thread_local(initialexec) global i32 0
 // CHECK-LE: @z1 ={{.*}} global i32 0
 // CHECK-LE: @z2 ={{.*}} global i32 0
 // CHECK-LE: @x ={{.*}} thread_local(localexec) global i32 0
Index: clang/lib/Sema/SemaDeclAttr.cpp
===
--- clang/lib/Sema/SemaDeclAttr.cpp
+++ clang/lib/Sema/SemaDeclAttr.cpp
@@ -2039,7 +2039,7 @@
   }
 
   if (S.Context.getTargetInfo().getTriple().isOSAIX() &&
-  Model != "global-dynamic" && Model != "local-exec") {
+  Model == "local-dynamic") {
 S.Diag(LiteralLoc, diag::err_aix_attr_unsupported_tls_model) << Model;
 return;
   }
Index: clang/lib/Frontend/CompilerInvocation.cpp
===
--- clang/lib/Frontend/CompilerInvocation.cpp
+++ clang/lib/Frontend/CompilerInvocation.cpp
@@ -1887,7 +1887,7 @@
   if (Arg *A = Args.getLastArg(OPT_ftlsmodel_EQ)) {
 if (T.isOSAIX()) {
   StringRef Name = A->getValue();
-  if (Name != "global-dynamic" && Name != "local-exec")
+  if (Name == "local-dynamic")
 Diags.Report(diag::err_aix_unsupported_tls_model) << Name;
 }
   }


Index: clang/test/Sema/aix-attr-tl

[PATCH] D112932: Use llvm.is_fpclass to implement FP classification functions

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.

Is there any blocker for this to land?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112932/new/

https://reviews.llvm.org/D112932

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D109751: [Clang] Support conversion between PPC double-double and IEEE float128

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf abandoned this revision.
qiucf added a subscriber: tuliom.
qiucf added a comment.

There's a glibc patch in review to fix the motivation error in math.h (thanks 
to @tuliom ): 
https://patchwork.sourceware.org/project/glibc/patch/20230613215633.3179708-1-tul...@ascii.art.br/
 I think this revision can be closed.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109751/new/

https://reviews.llvm.org/D109751

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D116016: [Clang] [PowerPC] Emit module flag for current float abi

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf updated this revision to Diff 530843.
qiucf marked an inline comment as done.
qiucf edited the summary of this revision.
qiucf removed a reviewer: jsji.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116016/new/

https://reviews.llvm.org/D116016

Files:
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/CodeGenTypes.h
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/ppc64-float-abi-attr.c

Index: clang/test/CodeGen/ppc64-float-abi-attr.c
===
--- /dev/null
+++ clang/test/CodeGen/ppc64-float-abi-attr.c
@@ -0,0 +1,17 @@
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu %s -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu %s -emit-llvm -mabi=ieeelongdouble -o - | FileCheck %s --check-prefix=IEEE
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu %s -emit-llvm -mlong-double-64 -o - | FileCheck %s --check-prefix=LDBL64
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu %s -emit-llvm -DNOLDBL -o - | FileCheck %s --check-prefix=NOLDBL
+
+#ifndef NOLDBL
+long double foo(long double a, long double b) {
+  return a + b;
+}
+#endif
+
+int bar() { return 1; }
+
+// CHECK: ![[#]] = !{i32 1, !"float-abi", !"doubledouble"}
+// IEEE: ![[#]] = !{i32 1, !"float-abi", !"ieeequad"}
+// LDBL64: ![[#]] = !{i32 1, !"float-abi", !"ieeedouble"}
+// NOLDBL-NOT: ![[#]] = !{i32 1, !"float-abi"
Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -5045,6 +5045,10 @@
 
   bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
llvm::Value *Address) const override;
+
+  void emitTargetMetadata(CodeGen::CodeGenModule &CGM,
+  const llvm::MapVector
+  &MangledDeclNames) const override;
 };
 
 class PPC64TargetCodeGenInfo : public TargetCodeGenInfo {
@@ -5470,6 +5474,24 @@
  /*IsAIX*/ false);
 }
 
+void PPC64_SVR4_TargetCodeGenInfo::emitTargetMetadata(
+CodeGen::CodeGenModule &CGM,
+const llvm::MapVector &MangledDeclNames) const {
+  if (CGM.getTypes().isLongDoubleReferenced()) {
+llvm::LLVMContext &Ctx = CGM.getLLVMContext();
+const auto *flt = &CGM.getTarget().getLongDoubleFormat();
+if (flt == &llvm::APFloat::PPCDoubleDouble())
+  CGM.getModule().addModuleFlag(llvm::Module::Error, "float-abi",
+llvm::MDString::get(Ctx, "doubledouble"));
+else if (flt == &llvm::APFloat::IEEEquad())
+  CGM.getModule().addModuleFlag(llvm::Module::Error, "float-abi",
+llvm::MDString::get(Ctx, "ieeequad"));
+else if (flt == &llvm::APFloat::IEEEdouble())
+  CGM.getModule().addModuleFlag(llvm::Module::Error, "float-abi",
+llvm::MDString::get(Ctx, "ieeedouble"));
+  }
+}
+
 bool
 PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
 llvm::Value *Address) const {
Index: clang/lib/CodeGen/CodeGenTypes.h
===
--- clang/lib/CodeGen/CodeGenTypes.h
+++ clang/lib/CodeGen/CodeGenTypes.h
@@ -90,6 +90,9 @@
   /// a recursive struct conversion, set this to true.
   bool SkippedLayout;
 
+  /// True if any instance of long double types are used.
+  bool LongDoubleReferenced;
+
   SmallVector DeferredRecords;
 
   /// This map keeps cache of llvm::Types and maps clang::Type to
@@ -306,6 +309,7 @@
   bool isRecordBeingLaidOut(const Type *Ty) const {
 return RecordsBeingLaidOut.count(Ty);
   }
+  bool isLongDoubleReferenced() const { return LongDoubleReferenced; }
   unsigned getTargetAddressSpace(QualType T) const;
 };
 
Index: clang/lib/CodeGen/CodeGenTypes.cpp
===
--- clang/lib/CodeGen/CodeGenTypes.cpp
+++ clang/lib/CodeGen/CodeGenTypes.cpp
@@ -34,6 +34,7 @@
 Target(cgm.getTarget()), TheCXXABI(cgm.getCXXABI()),
 TheABIInfo(cgm.getTargetCodeGenInfo().getABIInfo()) {
   SkippedLayout = false;
+  LongDoubleReferenced = false;
 }
 
 CodeGenTypes::~CodeGenTypes() {
@@ -529,10 +530,12 @@
   Context.getLangOpts().NativeHalfType ||
   !Context.getTargetInfo().useFP16ConversionIntrinsics());
   break;
+case BuiltinType::LongDouble:
+  LongDoubleReferenced = true;
+  LLVM_FALLTHROUGH;
 case BuiltinType::BFloat16:
 case BuiltinType::Float:
 case BuiltinType::Double:
-case BuiltinType::LongDouble:
 case BuiltinType::Float128:
 case BuiltinType::Ibm128:
   ResultType = getTypeForFormat(getLLVMContext(),
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin

[PATCH] D149548: [IR] Update to use new shufflevector semantics

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added subscribers: jonpa, uweigand.
qiucf added a comment.

Why this changes IR output of following case?

  // RUN: clang vecpromote.c -S -o - -O0 -target s390x-linux-gnu -fzvector 
-emit-llvm
  #include 
  
  vector int si;
  int g;
  int i;
  
  void foo() {
si = vec_promote(g, i);
  }
  
  // store <4 x i32> undef, ptr %__vec.i, align 16, !noalias !6  ; this undef 
becomes poison after this patch
  // %2 = load i32, ptr %__scalar.addr.i, align 4, !noalias !6
  // %3 = load i32, ptr %__index.addr.i, align 4, !noalias !6
  // %4 = load <4 x i32>, ptr %__vec.i, align 16, !noalias !6
  // %vecins.i = insertelement <4 x i32> %4, i32 %2, i32 %and.i

I see no PowerPC related case changes. Maybe adding SystemZ folks for comments 
@uweigand @jonpa


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149548/new/

https://reviews.llvm.org/D149548

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D152351: [clang] Add __builtin_isfpclass

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.

It's necessary to check range of first argument in `SemaChecking.cpp` using 
`SemaBuiltinConstantArgRange`.

  _Bool check_isfpclass_1(float x) { return __builtin_isfpclass(123456, x); } 
// ICE
  
  int g;
  // error: cannot compile this builtin function yet
  // there's better diagnostics when 1st argument is not constant
  _Bool check_isfpclass_2(float x) { return __builtin_isfpclass(g, x); }




Comment at: clang/include/clang/Basic/Builtins.def:491
 BUILTIN(__builtin_isnormal,   "i.", "FnctE")
+BUILTIN(__builtin_isfpclass,  "iCi.", "nctE")
 

Why these intrinsics' type spec end with dot? I thought they are for vaargs.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152351/new/

https://reviews.llvm.org/D152351

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D148490: [AIX] use system assembler for assembly files

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf accepted this revision as: qiucf.
qiucf added a comment.
This revision is now accepted and ready to land.

This looks reasonable to me, thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148490/new/

https://reviews.llvm.org/D148490

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D150087: [Clang] Support more stdio builtins

[Qiu Chaofan via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
qiucf marked an inline comment as done.
Closed by commit rGbaeb85b5a997: [Clang] Support more stdio builtins (authored 
by qiucf).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150087/new/

https://reviews.llvm.org/D150087

Files:
  clang/include/clang/Basic/Builtins.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/PowerPC/ppc64-f128-builtins.c

Index: clang/test/CodeGen/PowerPC/ppc64-f128-builtins.c
===
--- clang/test/CodeGen/PowerPC/ppc64-f128-builtins.c
+++ clang/test/CodeGen/PowerPC/ppc64-f128-builtins.c
@@ -52,6 +52,63 @@
   __builtin_snprintf(buf, 20, "%.Lf", x);
 }
 
+// IEEE128-LABEL: define dso_local void @test_scanf
+// IEEE128: call signext i32 (ptr, ...) @__scanfieee128
+// PPC128-LABEL: define dso_local void @test_scanf
+// PPC128: call signext i32 (ptr, ...) @scanf
+void test_scanf(int *x) {
+  __builtin_scanf("%d", x);
+}
+
+// IEEE128-LABEL: define dso_local void @test_sscanf
+// IEEE128: call signext i32 (ptr, ptr, ...) @__sscanfieee128
+// PPC128-LABEL: define dso_local void @test_sscanf
+// PPC128: call signext i32 (ptr, ptr, ...) @sscanf
+void test_sscanf(int *x) {
+  __builtin_sscanf(buf, "%d", x);
+}
+
+// IEEE128-LABEL: define dso_local void @test_vprintf
+// IEEE128: call signext i32 @__vprintfieee128
+// PPC128-LABEL: define dso_local void @test_vprintf
+// PPC128: call signext i32 @vprintf
+void test_vprintf(const char *fmt, ...) {
+  __builtin_va_list args;
+  __builtin_va_start(args, fmt);
+  __builtin_vprintf(fmt, args);
+  __builtin_va_end(args);
+}
+
+// IEEE128-LABEL: define dso_local void @test_vscanf
+// IEEE128: call signext i32 @__vscanfieee128
+// PPC128-LABEL: define dso_local void @test_vscanf
+// PPC128: call signext i32 @vscanf
+void test_vscanf(const char *fmt, ...) {
+  __builtin_va_list args;
+  __builtin_va_start(args, fmt);
+  __builtin_vscanf(fmt, args);
+  __builtin_va_end(args);
+}
+
+// IEEE128-LABEL: define dso_local void @test_vsscanf
+// IEEE128: call signext i32 @__vsscanfieee128
+// PPC128-LABEL: define dso_local void @test_vsscanf
+// PPC128: call signext i32 @vsscanf
+void test_vsscanf(const char *fmt, ...) {
+  __builtin_va_list args;
+  __builtin_va_start(args, fmt);
+  __builtin_vsscanf(buf, fmt, args);
+  __builtin_va_end(args);
+}
+
+// IEEE128-LABEL: define dso_local void @test_snprintf_chk
+// IEEE128: call signext i32 (ptr, i64, i32, i64, ptr, ...) @__snprintf_chkieee128
+// PPC128-LABEL: define dso_local void @test_snprintf_chk
+// PPC128: call signext i32 (ptr, i64, i32, i64, ptr, ...) @__snprintf_chk
+void test_snprintf_chk(long double x) {
+  __builtin___snprintf_chk(buf, 20, 1, 20, "%.Lf", x);
+}
+
 // GLIBC has special handling of 'nexttoward'
 
 // IEEE128-LABEL: define dso_local fp128 @test_nexttoward
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -99,13 +99,29 @@
 
   // TODO: This list should be expanded or refactored after all GCC-compatible
   // std libcall builtins are implemented.
-  static SmallDenseMap F128Builtins{
+  static SmallDenseMap F128Builtins{
+  {Builtin::BI__builtin___fprintf_chk, "__fprintf_chkieee128"},
+  {Builtin::BI__builtin___printf_chk, "__printf_chkieee128"},
+  {Builtin::BI__builtin___snprintf_chk, "__snprintf_chkieee128"},
+  {Builtin::BI__builtin___sprintf_chk, "__sprintf_chkieee128"},
+  {Builtin::BI__builtin___vfprintf_chk, "__vfprintf_chkieee128"},
+  {Builtin::BI__builtin___vprintf_chk, "__vprintf_chkieee128"},
+  {Builtin::BI__builtin___vsnprintf_chk, "__vsnprintf_chkieee128"},
+  {Builtin::BI__builtin___vsprintf_chk, "__vsprintf_chkieee128"},
+  {Builtin::BI__builtin_fprintf, "__fprintfieee128"},
   {Builtin::BI__builtin_printf, "__printfieee128"},
+  {Builtin::BI__builtin_snprintf, "__snprintfieee128"},
+  {Builtin::BI__builtin_sprintf, "__sprintfieee128"},
+  {Builtin::BI__builtin_vfprintf, "__vfprintfieee128"},
+  {Builtin::BI__builtin_vprintf, "__vprintfieee128"},
   {Builtin::BI__builtin_vsnprintf, "__vsnprintfieee128"},
   {Builtin::BI__builtin_vsprintf, "__vsprintfieee128"},
-  {Builtin::BI__builtin_sprintf, "__sprintfieee128"},
-  {Builtin::BI__builtin_snprintf, "__snprintfieee128"},
-  {Builtin::BI__builtin_fprintf, "__fprintfieee128"},
+  {Builtin::BI__builtin_fscanf, "__fscanfieee128"},
+  {Builtin::BI__builtin_scanf, "__scanfieee128"},
+  {Builtin::BI__builtin_sscanf, "__sscanfieee128"},
+  {Builtin::BI__builtin_vfscanf, "__vfscanfieee128"},
+  {Builtin::BI__builtin_vscanf, "__vscanfieee128"},
+  {Builtin::BI__builtin_vsscanf, "__vsscanfieee128"},
   {Builtin::BI__builtin_nexttowardf128, "__nexttowardieee128"},
   };
 
Index: clang/include/clang/Basic/Builtin

[PATCH] D150087: [Clang] Support more stdio builtins

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf marked an inline comment as done.
qiucf added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:109
+  {Builtin::BI__builtin___vsnprintf_chk, "__vsnprintfieee128"},
+  {Builtin::BI__builtin___vsprintf_chk, "__vsprintfieee128"},
+  {Builtin::BI__builtin_fprintf, "__fprintfieee128"},

tuliom wrote:
> Any reasons to not map these built-ins to their respective `_chkieee128` 
> counterparts? e.g. `__fprintf_chkieee128`.
Updated.

I just saw GCC in some cases emits no-chk version when calling 
`__builtin_*printf_chk`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150087/new/

https://reviews.llvm.org/D150087

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D150087: [Clang] Support more stdio builtins

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf updated this revision to Diff 523305.
qiucf marked an inline comment as done.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150087/new/

https://reviews.llvm.org/D150087

Files:
  clang/include/clang/Basic/Builtins.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/PowerPC/ppc64-f128-builtins.c

Index: clang/test/CodeGen/PowerPC/ppc64-f128-builtins.c
===
--- clang/test/CodeGen/PowerPC/ppc64-f128-builtins.c
+++ clang/test/CodeGen/PowerPC/ppc64-f128-builtins.c
@@ -52,6 +52,63 @@
   __builtin_snprintf(buf, 20, "%.Lf", x);
 }
 
+// IEEE128-LABEL: define dso_local void @test_scanf
+// IEEE128: call signext i32 (ptr, ...) @__scanfieee128
+// PPC128-LABEL: define dso_local void @test_scanf
+// PPC128: call signext i32 (ptr, ...) @scanf
+void test_scanf(int *x) {
+  __builtin_scanf("%d", x);
+}
+
+// IEEE128-LABEL: define dso_local void @test_sscanf
+// IEEE128: call signext i32 (ptr, ptr, ...) @__sscanfieee128
+// PPC128-LABEL: define dso_local void @test_sscanf
+// PPC128: call signext i32 (ptr, ptr, ...) @sscanf
+void test_sscanf(int *x) {
+  __builtin_sscanf(buf, "%d", x);
+}
+
+// IEEE128-LABEL: define dso_local void @test_vprintf
+// IEEE128: call signext i32 @__vprintfieee128
+// PPC128-LABEL: define dso_local void @test_vprintf
+// PPC128: call signext i32 @vprintf
+void test_vprintf(const char *fmt, ...) {
+  __builtin_va_list args;
+  __builtin_va_start(args, fmt);
+  __builtin_vprintf(fmt, args);
+  __builtin_va_end(args);
+}
+
+// IEEE128-LABEL: define dso_local void @test_vscanf
+// IEEE128: call signext i32 @__vscanfieee128
+// PPC128-LABEL: define dso_local void @test_vscanf
+// PPC128: call signext i32 @vscanf
+void test_vscanf(const char *fmt, ...) {
+  __builtin_va_list args;
+  __builtin_va_start(args, fmt);
+  __builtin_vscanf(fmt, args);
+  __builtin_va_end(args);
+}
+
+// IEEE128-LABEL: define dso_local void @test_vsscanf
+// IEEE128: call signext i32 @__vsscanfieee128
+// PPC128-LABEL: define dso_local void @test_vsscanf
+// PPC128: call signext i32 @vsscanf
+void test_vsscanf(const char *fmt, ...) {
+  __builtin_va_list args;
+  __builtin_va_start(args, fmt);
+  __builtin_vsscanf(buf, fmt, args);
+  __builtin_va_end(args);
+}
+
+// IEEE128-LABEL: define dso_local void @test_snprintf_chk
+// IEEE128: call signext i32 (ptr, i64, i32, i64, ptr, ...) @__snprintf_chkieee128
+// PPC128-LABEL: define dso_local void @test_snprintf_chk
+// PPC128: call signext i32 (ptr, i64, i32, i64, ptr, ...) @__snprintf_chk
+void test_snprintf_chk(long double x) {
+  __builtin___snprintf_chk(buf, 20, 1, 20, "%.Lf", x);
+}
+
 // GLIBC has special handling of 'nexttoward'
 
 // IEEE128-LABEL: define dso_local fp128 @test_nexttoward
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -99,13 +99,29 @@
 
   // TODO: This list should be expanded or refactored after all GCC-compatible
   // std libcall builtins are implemented.
-  static SmallDenseMap F128Builtins{
+  static SmallDenseMap F128Builtins{
+  {Builtin::BI__builtin___fprintf_chk, "__fprintf_chkieee128"},
+  {Builtin::BI__builtin___printf_chk, "__printf_chkieee128"},
+  {Builtin::BI__builtin___snprintf_chk, "__snprintf_chkieee128"},
+  {Builtin::BI__builtin___sprintf_chk, "__sprintf_chkieee128"},
+  {Builtin::BI__builtin___vfprintf_chk, "__vfprintf_chkieee128"},
+  {Builtin::BI__builtin___vprintf_chk, "__vprintf_chkieee128"},
+  {Builtin::BI__builtin___vsnprintf_chk, "__vsnprintf_chkieee128"},
+  {Builtin::BI__builtin___vsprintf_chk, "__vsprintf_chkieee128"},
+  {Builtin::BI__builtin_fprintf, "__fprintfieee128"},
   {Builtin::BI__builtin_printf, "__printfieee128"},
+  {Builtin::BI__builtin_snprintf, "__snprintfieee128"},
+  {Builtin::BI__builtin_sprintf, "__sprintfieee128"},
+  {Builtin::BI__builtin_vfprintf, "__vfprintfieee128"},
+  {Builtin::BI__builtin_vprintf, "__vprintfieee128"},
   {Builtin::BI__builtin_vsnprintf, "__vsnprintfieee128"},
   {Builtin::BI__builtin_vsprintf, "__vsprintfieee128"},
-  {Builtin::BI__builtin_sprintf, "__sprintfieee128"},
-  {Builtin::BI__builtin_snprintf, "__snprintfieee128"},
-  {Builtin::BI__builtin_fprintf, "__fprintfieee128"},
+  {Builtin::BI__builtin_fscanf, "__fscanfieee128"},
+  {Builtin::BI__builtin_scanf, "__scanfieee128"},
+  {Builtin::BI__builtin_sscanf, "__sscanfieee128"},
+  {Builtin::BI__builtin_vfscanf, "__vfscanfieee128"},
+  {Builtin::BI__builtin_vscanf, "__vscanfieee128"},
+  {Builtin::BI__builtin_vsscanf, "__vsscanfieee128"},
   {Builtin::BI__builtin_nexttowardf128, "__nexttowardieee128"},
   };
 
Index: clang/include/clang/Basic/Builtins.def
===
--- clang/include/clang/Basic/Builtins.def
+++ 

[PATCH] D150087: [Clang] Support more stdio builtins

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf created this revision.
qiucf added reviewers: nemanjai, craig.topper, PowerPC, tuliom, tstellar.
Herald added a subscriber: kbarton.
Herald added a project: All.
qiucf requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Add more builtins for stdio functions as in GCC ( 
https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html ), along with their 
mutations under IEEE float128 ABI.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D150087

Files:
  clang/include/clang/Basic/Builtins.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/PowerPC/ppc64-f128-builtins.c

Index: clang/test/CodeGen/PowerPC/ppc64-f128-builtins.c
===
--- clang/test/CodeGen/PowerPC/ppc64-f128-builtins.c
+++ clang/test/CodeGen/PowerPC/ppc64-f128-builtins.c
@@ -61,3 +61,52 @@
 long double test_nexttoward(long double a, long double b) {
   return __builtin_nexttowardl(a, b);
 }
+
+// IEEE128-LABEL: define dso_local void @test_scanf
+// IEEE128: call signext i32 (ptr, ...) @__scanfieee128
+// PPC128-LABEL: define dso_local void @test_scanf
+// PPC128: call signext i32 (ptr, ...) @scanf
+void test_scanf(int *x) {
+  __builtin_scanf("%d", x);
+}
+
+// IEEE128-LABEL: define dso_local void @test_sscanf
+// IEEE128: call signext i32 (ptr, ptr, ...) @__sscanfieee128
+// PPC128-LABEL: define dso_local void @test_sscanf
+// PPC128: call signext i32 (ptr, ptr, ...) @sscanf
+void test_sscanf(int *x) {
+  __builtin_sscanf(buf, "%d", x);
+}
+
+// IEEE128-LABEL: define dso_local void @test_vprintf
+// IEEE128: call signext i32 @__vprintfieee128
+// PPC128-LABEL: define dso_local void @test_vprintf
+// PPC128: call signext i32 @vprintf
+void test_vprintf(const char *fmt, ...) {
+  __builtin_va_list args;
+  __builtin_va_start(args, fmt);
+  __builtin_vprintf(fmt, args);
+  __builtin_va_end(args);
+}
+
+// IEEE128-LABEL: define dso_local void @test_vscanf
+// IEEE128: call signext i32 @__vscanfieee128
+// PPC128-LABEL: define dso_local void @test_vscanf
+// PPC128: call signext i32 @vscanf
+void test_vscanf(const char *fmt, ...) {
+  __builtin_va_list args;
+  __builtin_va_start(args, fmt);
+  __builtin_vscanf(fmt, args);
+  __builtin_va_end(args);
+}
+
+// IEEE128-LABEL: define dso_local void @test_vsscanf
+// IEEE128: call signext i32 @__vsscanfieee128
+// PPC128-LABEL: define dso_local void @test_vsscanf
+// PPC128: call signext i32 @vsscanf
+void test_vsscanf(const char *fmt, ...) {
+  __builtin_va_list args;
+  __builtin_va_start(args, fmt);
+  __builtin_vsscanf(buf, fmt, args);
+  __builtin_va_end(args);
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -100,12 +100,27 @@
   // TODO: This list should be expanded or refactored after all GCC-compatible
   // std libcall builtins are implemented.
   static SmallDenseMap F128Builtins{
+  {Builtin::BI__builtin___fprintf_chk, "__fprintfieee128"},
+  {Builtin::BI__builtin___printf_chk, "__printfieee128"},
+  {Builtin::BI__builtin___snprintf_chk, "__snprintfieee128"},
+  {Builtin::BI__builtin___sprintf_chk, "__sprintfieee128"},
+  {Builtin::BI__builtin___vfprintf_chk, "__vfprintfieee128"},
+  {Builtin::BI__builtin___vsnprintf_chk, "__vsnprintfieee128"},
+  {Builtin::BI__builtin___vsprintf_chk, "__vsprintfieee128"},
+  {Builtin::BI__builtin_fprintf, "__fprintfieee128"},
+  {Builtin::BI__builtin_fscanf, "__fscanfieee128"},
   {Builtin::BI__builtin_printf, "__printfieee128"},
+  {Builtin::BI__builtin_scanf, "__scanfieee128"},
+  {Builtin::BI__builtin_snprintf, "__snprintfieee128"},
+  {Builtin::BI__builtin_sprintf, "__sprintfieee128"},
+  {Builtin::BI__builtin_sscanf, "__sscanfieee128"},
+  {Builtin::BI__builtin_vfprintf, "__vfprintfieee128"},
+  {Builtin::BI__builtin_vfscanf, "__vfscanfieee128"},
+  {Builtin::BI__builtin_vprintf, "__vprintfieee128"},
+  {Builtin::BI__builtin_vscanf, "__vscanfieee128"},
   {Builtin::BI__builtin_vsnprintf, "__vsnprintfieee128"},
   {Builtin::BI__builtin_vsprintf, "__vsprintfieee128"},
-  {Builtin::BI__builtin_sprintf, "__sprintfieee128"},
-  {Builtin::BI__builtin_snprintf, "__snprintfieee128"},
-  {Builtin::BI__builtin_fprintf, "__fprintfieee128"},
+  {Builtin::BI__builtin_vsscanf, "__vsscanfieee128"},
   {Builtin::BI__builtin_nexttowardf128, "__nexttowardieee128"},
   };
 
Index: clang/include/clang/Basic/Builtins.def
===
--- clang/include/clang/Basic/Builtins.def
+++ clang/include/clang/Basic/Builtins.def
@@ -559,6 +559,7 @@
 BUILTIN(__builtin_bzero, "vv*z", "nF")
 BUILTIN(__builtin_fprintf, "iP*cC*.", "Fp:1:")
 BUILTIN(__builtin_free, "vv*", "nF")
+BUILTIN(__builtin_fscanf, "iP*RcC*R.", "Fs:1:")
 BUILTIN(__builtin_malloc, "v*z", "nF")
 B

[PATCH] D148490: [AIX] use system assembler for assembly files

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added inline comments.



Comment at: clang/lib/Driver/ToolChains/AIX.cpp:427
+  Assembler.reset(buildAssembler());
+return Assembler.get();
+  }

I saw we have a `ToolChain::getAssemble()` method. Can we use that directly?



Comment at: clang/test/Driver/aix-assembler.s:1
+
+// Check powerpc64-ibm-aix7.1.0.0, 64-bit.

Empty line?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148490/new/

https://reviews.llvm.org/D148490

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D143467: [PowerPC] Add target feature requirement to builtins

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.

Gentle ping .. @kamaub


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143467/new/

https://reviews.llvm.org/D143467

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D143467: [PowerPC] Add target feature requirement to builtins

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.

In D143467#4258380 , @kamaub wrote:

> Sorry I should have requested changes before for this comment below, but I do 
> want these test moved to codegen and expanded, please let me know if anything 
> is unclear.
>
> In D143467#4241667 , @kamaub wrote:
>
>> Can you add a PowerPC codegen test case for `__attribute__((target(`? All of 
>> the updated test cases seem to only test `-target-feature`.
>> The only test case we have for `__attribute((target(` is a sema test 
>> `./clang/test/Sema/ppc-attr-target-inline.c`.
>>
>> Converting the deleted `clang/test/Sema/ppc-mma-builtins.c` and 
>> `clang/test/Sema/ppc-paired-vector-builtins.c` to a codegen test cases
>> like `clang/test/CodeGen/PowerPC/builtins-ppc-htm.c` using FileCheck seems 
>> like a nice solution since it would reintroduce the testing
>> for `+paired-vector-memops,-mma` situations, as well as a for 
>> `__attribute__((target("no-mma")))`

Hi, I updated the case to test builtins used in previous Sema tests when both 
no-mma and no-paired-vector-memops. There's limitation that such codegen error 
message only diagnose one function, so I wrapped them into a single function. 
Not sure if that's the full meaning.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143467/new/

https://reviews.llvm.org/D143467

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D143467: [PowerPC] Add target feature requirement to builtins

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added inline comments.



Comment at: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.c:47
 
-int test_test_data_class_f() {
-// CHECK-LABEL:   @test_test_data_class_f
-// CHECK: [[TMP:%.*]] = call i32 
@llvm.ppc.test.data.class.f32(float %0, i32 127)
-// CHECK-NEXT:ret i32 [[TMP]]
-// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs
-// CHECK-NOVSX-ERR: error: this builtin requires VSX to be enabled
-  return __test_data_class(f, 127);
+// CHECK-NOVSX-ERR: error: '__builtin_ppc_compare_exp_uo' needs target feature 
isa-v30-instructions,vsx
+// CHECK-NOVSX-ERR: error: '__builtin_ppc_compare_exp_lt' needs target feature 
isa-v30-instructions,vsx

qiucf wrote:
> stefanp wrote:
> > nit:
> > Should this be 
> > ```
> > ... needs target feature vsx
> > ```
> > Instead of listing them both?
> > 
> > Fixing this might be more trouble than it's worth because you would have to 
> > edit `CodeGenFunction::checkTargetFeatures`. I just thought I would mention 
> > it.
> Yes. That can be done in another patch.
After checking the source code, I found it might be too complex to filter 
existing features out. Because it actually has a syntax to support 'and'/'or' 
of feature requirements: 
https://github.com/llvm/llvm-project/blob/4016e5d/clang/lib/Basic/BuiltinTargetFeatures.h#L22_L31


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143467/new/

https://reviews.llvm.org/D143467

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D143467: [PowerPC] Add target feature requirement to builtins

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added inline comments.



Comment at: clang/include/clang/Basic/BuiltinsPPC.def:444
+TARGET_BUILTIN(__builtin_altivec_vcmpnew_p, "iiV4iV4i", "", "power9-vector")
+TARGET_BUILTIN(__builtin_altivec_vcmpned_p, "iiV2LLiV2LLi", "", "altivec")
+

maryammo wrote:
> amyk wrote:
> > Does this need to be `vsx`?
> How do we find the appropriate FEATURE for the above 4 builtins?  (first 3 
> are p9 and the 4th one is altivec)
`vcmpneb` `vcmpneh` `vcmpnew` debute in ISA 3.0. `vcmpned` does not exist, so 
it's keeped as-is. (but `vector long long` requires vsx, so it's reasonable to 
require vsx)



Comment at: clang/include/clang/Basic/BuiltinsPPC.def:987
+
+UNALIASED_CUSTOM_BUILTIN(mma_assemble_acc, "vW512*", false, "mma")
+UNALIASED_CUSTOM_BUILTIN(mma_disassemble_acc, "vv*W512*", false, "mma")

kamaub wrote:
> stefanp wrote:
> > Based on the original implementation in `SemaBuiltinPPCMMACall` all of the 
> > `mma` builtins also require `paired-vector-memops`. 
> > Is this something that we still need?
> since we are able to supply a comma separated list as done with 
> `TARGET_BUILTIN(__builtin_ppc_compare_exp_uo, "idd", "", 
> "isa-v30-instructions,vsx")` @ 
> `clang/include/clang/Basic/BuiltinsPPC.def:105`we should definitely also 
> specify `paired-vector-memops,mma` for the `[UNALIASED_]CUSTOM_BUILTIN`s 
> previously covered under the default case of `SemaBuiltinPPCMMACall()` 
Since `mma` and `paired-vector-memops` are independent from each other, I think 
only assemble/disassemble builtins should require `paired-vector-memops`?



Comment at: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.c:47
 
-int test_test_data_class_f() {
-// CHECK-LABEL:   @test_test_data_class_f
-// CHECK: [[TMP:%.*]] = call i32 
@llvm.ppc.test.data.class.f32(float %0, i32 127)
-// CHECK-NEXT:ret i32 [[TMP]]
-// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs
-// CHECK-NOVSX-ERR: error: this builtin requires VSX to be enabled
-  return __test_data_class(f, 127);
+// CHECK-NOVSX-ERR: error: '__builtin_ppc_compare_exp_uo' needs target feature 
isa-v30-instructions,vsx
+// CHECK-NOVSX-ERR: error: '__builtin_ppc_compare_exp_lt' needs target feature 
isa-v30-instructions,vsx

stefanp wrote:
> nit:
> Should this be 
> ```
> ... needs target feature vsx
> ```
> Instead of listing them both?
> 
> Fixing this might be more trouble than it's worth because you would have to 
> edit `CodeGenFunction::checkTargetFeatures`. I just thought I would mention 
> it.
Yes. That can be done in another patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143467/new/

https://reviews.llvm.org/D143467

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D143479: [Clang] Emit error when caller cannot meet target feature requirement from always-inlining callee

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.

In D143479#4243143 , @erichkeane 
wrote:

> Based on GCC's behavior: https://godbolt.org/z/fxWzPTT9P  I suspect our 
> behavior is consistent/correct now, and the 'regressions' are to be expected, 
> since GCC diagnoses the same things we do (just nicer, albeit, less 
> informative).

This is expected. But we can do better like GCC to find 'real target 
requirements from called intrinsics' of a function, which may be a larger 
change though.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143479/new/

https://reviews.llvm.org/D143479

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D143479: [Clang] Emit error when caller cannot meet target feature requirement from always-inlining callee

[Qiu Chaofan via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG608212a0ff2f: [Clang] Check feature requirement from inlined 
callee (authored by qiucf).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143479/new/

https://reviews.llvm.org/D143479

Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/lib/CodeGen/CodeGenFunction.cpp
  clang/test/Sema/ppc-attr-target-inline.c


Index: clang/test/Sema/ppc-attr-target-inline.c
===
--- /dev/null
+++ clang/test/Sema/ppc-attr-target-inline.c
@@ -0,0 +1,14 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64le -target-feature +htm -fsyntax-only 
-emit-llvm %s -verify
+
+__attribute__((always_inline))
+int test1(int *x) {
+  *x = __builtin_ttest();
+  return *x;
+}
+
+__attribute__((target("no-htm")))
+int test2(int *x) {
+  *x = test1(x); // expected-error {{always_inline function 'test1' requires 
target feature 'htm', but would be inlined into function 'test2' that is 
compiled without support for 'htm'}}
+  return 0;
+}
Index: clang/lib/CodeGen/CodeGenFunction.cpp
===
--- clang/lib/CodeGen/CodeGenFunction.cpp
+++ clang/lib/CodeGen/CodeGenFunction.cpp
@@ -2612,6 +2612,16 @@
 }))
   CGM.getDiags().Report(Loc, diag::err_function_needs_feature)
   << FD->getDeclName() << TargetDecl->getDeclName() << MissingFeature;
+  } else if (!FD->isMultiVersion() && FD->hasAttr()) {
+llvm::StringMap CalleeFeatureMap;
+CGM.getContext().getFunctionFeatureMap(CalleeFeatureMap, TargetDecl);
+
+for (const auto &F : CalleeFeatureMap) {
+  if (F.getValue() && (!CallerFeatureMap.lookup(F.getKey()) ||
+   !CallerFeatureMap.find(F.getKey())->getValue()))
+CGM.getDiags().Report(Loc, diag::err_function_needs_feature)
+<< FD->getDeclName() << TargetDecl->getDeclName() << F.getKey();
+}
   }
 }
 
Index: clang/lib/CodeGen/CGCall.cpp
===
--- clang/lib/CodeGen/CGCall.cpp
+++ clang/lib/CodeGen/CGCall.cpp
@@ -4802,7 +4802,8 @@
 // the proper cpu features (and it won't cause code generation issues due 
to
 // function based code generation).
 if (TargetDecl->hasAttr() &&
-TargetDecl->hasAttr())
+(TargetDecl->hasAttr() ||
+ (CurFuncDecl && CurFuncDecl->hasAttr(
   checkTargetFeatures(Loc, FD);
 
 // Some architectures (such as x86-64) have the ABI changed based on


Index: clang/test/Sema/ppc-attr-target-inline.c
===
--- /dev/null
+++ clang/test/Sema/ppc-attr-target-inline.c
@@ -0,0 +1,14 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64le -target-feature +htm -fsyntax-only -emit-llvm %s -verify
+
+__attribute__((always_inline))
+int test1(int *x) {
+  *x = __builtin_ttest();
+  return *x;
+}
+
+__attribute__((target("no-htm")))
+int test2(int *x) {
+  *x = test1(x); // expected-error {{always_inline function 'test1' requires target feature 'htm', but would be inlined into function 'test2' that is compiled without support for 'htm'}}
+  return 0;
+}
Index: clang/lib/CodeGen/CodeGenFunction.cpp
===
--- clang/lib/CodeGen/CodeGenFunction.cpp
+++ clang/lib/CodeGen/CodeGenFunction.cpp
@@ -2612,6 +2612,16 @@
 }))
   CGM.getDiags().Report(Loc, diag::err_function_needs_feature)
   << FD->getDeclName() << TargetDecl->getDeclName() << MissingFeature;
+  } else if (!FD->isMultiVersion() && FD->hasAttr()) {
+llvm::StringMap CalleeFeatureMap;
+CGM.getContext().getFunctionFeatureMap(CalleeFeatureMap, TargetDecl);
+
+for (const auto &F : CalleeFeatureMap) {
+  if (F.getValue() && (!CallerFeatureMap.lookup(F.getKey()) ||
+   !CallerFeatureMap.find(F.getKey())->getValue()))
+CGM.getDiags().Report(Loc, diag::err_function_needs_feature)
+<< FD->getDeclName() << TargetDecl->getDeclName() << F.getKey();
+}
   }
 }
 
Index: clang/lib/CodeGen/CGCall.cpp
===
--- clang/lib/CodeGen/CGCall.cpp
+++ clang/lib/CodeGen/CGCall.cpp
@@ -4802,7 +4802,8 @@
 // the proper cpu features (and it won't cause code generation issues due to
 // function based code generation).
 if (TargetDecl->hasAttr() &&
-TargetDecl->hasAttr())
+(TargetDecl->hasAttr() ||
+ (CurFuncDecl && CurFuncDecl->hasAttr(
   checkTargetFeatures(Loc, FD);
 
 // Some architectures (such as x86-64) have the ABI changed based on
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D143479: [Clang] Emit error when caller cannot meet target feature requirement from always-inlining callee

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.

Gentle ping


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143479/new/

https://reviews.llvm.org/D143479

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D143467: [PowerPC] Add target feature requirement to builtins

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.

In D143467#4182457 , @nemanjai wrote:

> Another note regarding the motivating test case:
> Use of `vector double` should require VSX. We don't really seem to have the 
> ability to turn this off early enough to catch this though. It would seem 
> that in the front end, the target features depend on the compilation options 
> and not the function itself.

Thanks for reminding me of `vector double` exception! I have D143479 
 to make target feature check respect target 
attributes.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143467/new/

https://reviews.llvm.org/D143467

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D143467: [PowerPC] Add target feature requirement to builtins

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.

> However, manually adding the required target feature seems a little 
> mistakable, like the one below. I guess we can not get the required feature 
> in the LLVM instruction TDs(if the builtin is mapped to a IR intrinsic and 
> the intrinsic is selected inside the instruction TD) because this is done in 
> CLANG?

Yes, this is how clang builtin definitions work. They are independent from LLVM 
definitions in tablegen files.

> Really need to way to make sure that the instruction are marked with the 
> accurate target feature, if not possible to do this inside the compiler, an 
> offline script maybe? Checking the instruction one by one is a little 
> time-consuming.

I actually don't think we need extra script to maintain this. They're rather 
static (not willing to change after written), independent (one changed won't 
affect another) and human-readable.




Comment at: clang/include/clang/Basic/BuiltinsPPC.def:491
+TARGET_BUILTIN(__builtin_altivec_vabsduh, "V8UsV8UsV8Us", "", "altivec")
+TARGET_BUILTIN(__builtin_altivec_vabsduw, "V4UiV4UiV4Ui", "", "altivec")
 

shchenz wrote:
> These builtins `vabsdub`, `vabsduh`, `vabsduw`  should require ISA3.0 which 
> is not altivec or vsx. Do we have a reasonable feature for Power9 
> instructions, `power9-vector` maybe?
Thanks. I'll update then. `power9-vector` is good option. But I'm curious 
what's the different pratical usages from `power9-vector` and 
`isa-v30-instructions`. Maybe cc @nemanjai 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143467/new/

https://reviews.llvm.org/D143467

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D143467: [PowerPC] Add target feature requirement to builtins

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.

Ping


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143467/new/

https://reviews.llvm.org/D143467

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D143736: [PowerPC] Specify the dynamic loader prefix in ppc-float-abi-warning

[Qiu Chaofan via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGcb90bb986611: [PowerPC] Specify the dynamic loader prefix in 
ppc-float-abi-warning (authored by tuliom, committed by qiucf).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143736/new/

https://reviews.llvm.org/D143736

Files:
  clang/test/Driver/ppc-float-abi-warning.cpp


Index: clang/test/Driver/ppc-float-abi-warning.cpp
===
--- clang/test/Driver/ppc-float-abi-warning.cpp
+++ clang/test/Driver/ppc-float-abi-warning.cpp
@@ -17,10 +17,12 @@
 // RUN:  -mabi=ieeelongdouble -stdlib=libc++ -Wno-unsupported-abi 2>&1 | \
 // RUN:  FileCheck %s --check-prefix=NOWARN
 // RUN: %clang -### --driver-mode=g++ -target powerpc64le-linux-gnu %s\
+// RUN:  --dyld-prefix=%S/Inputs/powerpc64le-linux-gnu-tree/gcc-12 \
 // RUN:  -mabi=%if ppc_linux_default_ieeelongdouble %{ieeelongdouble%} \
 // RUN:  %else %{ibmlongdouble%} -stdlib=libc++ 2>&1 | \
 // RUN:  FileCheck %s --check-prefix=NOWARN
 // RUN: %clang -### --driver-mode=g++ -target powerpc64le-linux-gnu %s\
+// RUN:  --dyld-prefix=%S/Inputs/powerpc64le-linux-gnu-tree/gcc-12 \
 // RUN:  -mabi=%if ppc_linux_default_ieeelongdouble %{ibmlongdouble%} \
 // RUN:  %else %{ieeelongdouble%} -stdlib=libc++ 2>&1 | FileCheck %s
 


Index: clang/test/Driver/ppc-float-abi-warning.cpp
===
--- clang/test/Driver/ppc-float-abi-warning.cpp
+++ clang/test/Driver/ppc-float-abi-warning.cpp
@@ -17,10 +17,12 @@
 // RUN:  -mabi=ieeelongdouble -stdlib=libc++ -Wno-unsupported-abi 2>&1 | \
 // RUN:  FileCheck %s --check-prefix=NOWARN
 // RUN: %clang -### --driver-mode=g++ -target powerpc64le-linux-gnu %s\
+// RUN:  --dyld-prefix=%S/Inputs/powerpc64le-linux-gnu-tree/gcc-12 \
 // RUN:  -mabi=%if ppc_linux_default_ieeelongdouble %{ieeelongdouble%} \
 // RUN:  %else %{ibmlongdouble%} -stdlib=libc++ 2>&1 | \
 // RUN:  FileCheck %s --check-prefix=NOWARN
 // RUN: %clang -### --driver-mode=g++ -target powerpc64le-linux-gnu %s\
+// RUN:  --dyld-prefix=%S/Inputs/powerpc64le-linux-gnu-tree/gcc-12 \
 // RUN:  -mabi=%if ppc_linux_default_ieeelongdouble %{ibmlongdouble%} \
 // RUN:  %else %{ieeelongdouble%} -stdlib=libc++ 2>&1 | FileCheck %s
 
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D143736: [PowerPC] Specify the dynamic loader prefix in ppc-float-abi-warning

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf accepted this revision.
qiucf added a comment.
This revision is now accepted and ready to land.

LGTM, thanks for catching this.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143736/new/

https://reviews.llvm.org/D143736

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D143479: [Clang] Emit error when caller cannot meet target feature requirement from always-inlining callee

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf created this revision.
qiucf added reviewers: echristo, LiuChen3, erichkeane, GBuella.
Herald added subscribers: steven.zhang, kbarton, nemanjai.
Herald added a project: All.
qiucf requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Currently clang emits error when both `always_inline` and `target` attributes 
are on callee, but caller doesn't have some feature:

  // RUN: %clang_cc1 -triple powerpc64le -target-feature -htm
  
  __attribute__((always_inline))
  __attribute__((target("htm")))
  void foo() {}
  
  void bar() { foo(); }
  
  // error: always_inline function 'foo' requires target feature 'htm', but 
would be inlined into function 'bar' that is compiled without support for 'htm'

But when the `always_inline` attribute is on caller, clang has no diagnose. If 
any builtin or inline asm really need the feature, backend will crash.

  // RUN: %clang_cc1 -triple powerpc64le -target-feature +htm
  
  __attribute__((always_inline))
  void foo() {
// No error, but uncommenting line below triggers ICE
// __builtin_ttest();
  }
  
  __attribute__((target("no-htm")))
  void bar() { foo(); }

This patch will fix the second case.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D143479

Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/lib/CodeGen/CodeGenFunction.cpp
  clang/test/Sema/ppc-attr-target-inline.c


Index: clang/test/Sema/ppc-attr-target-inline.c
===
--- /dev/null
+++ clang/test/Sema/ppc-attr-target-inline.c
@@ -0,0 +1,14 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64le -target-feature +htm -fsyntax-only 
-emit-llvm %s -verify
+
+__attribute__((always_inline))
+int test1(int *x) {
+  *x = __builtin_ttest();
+  return *x;
+}
+
+__attribute__((target("no-htm")))
+int test2(int *x) {
+  *x = test1(x); // expected-error {{always_inline function 'test1' requires 
target feature 'htm', but would be inlined into function 'test2' that is 
compiled without support for 'htm'}}
+  return 0;
+}
Index: clang/lib/CodeGen/CodeGenFunction.cpp
===
--- clang/lib/CodeGen/CodeGenFunction.cpp
+++ clang/lib/CodeGen/CodeGenFunction.cpp
@@ -2611,6 +2611,16 @@
 }))
   CGM.getDiags().Report(Loc, diag::err_function_needs_feature)
   << FD->getDeclName() << TargetDecl->getDeclName() << MissingFeature;
+  } else if (!FD->isMultiVersion() && FD->hasAttr()) {
+llvm::StringMap CalleeFeatureMap;
+CGM.getContext().getFunctionFeatureMap(CalleeFeatureMap, TargetDecl);
+
+for (const auto &F : CalleeFeatureMap) {
+  if (F.getValue() && (!CallerFeatureMap.lookup(F.getKey()) ||
+   !CallerFeatureMap.find(F.getKey())->getValue()))
+CGM.getDiags().Report(Loc, diag::err_function_needs_feature)
+<< FD->getDeclName() << TargetDecl->getDeclName() << F.getKey();
+}
   }
 }
 
Index: clang/lib/CodeGen/CGCall.cpp
===
--- clang/lib/CodeGen/CGCall.cpp
+++ clang/lib/CodeGen/CGCall.cpp
@@ -4761,7 +4761,8 @@
 // the proper cpu features (and it won't cause code generation issues due 
to
 // function based code generation).
 if (TargetDecl->hasAttr() &&
-TargetDecl->hasAttr())
+(TargetDecl->hasAttr() ||
+ (CurFuncDecl && CurFuncDecl->hasAttr(
   checkTargetFeatures(Loc, FD);
 
 // Some architectures (such as x86-64) have the ABI changed based on


Index: clang/test/Sema/ppc-attr-target-inline.c
===
--- /dev/null
+++ clang/test/Sema/ppc-attr-target-inline.c
@@ -0,0 +1,14 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64le -target-feature +htm -fsyntax-only -emit-llvm %s -verify
+
+__attribute__((always_inline))
+int test1(int *x) {
+  *x = __builtin_ttest();
+  return *x;
+}
+
+__attribute__((target("no-htm")))
+int test2(int *x) {
+  *x = test1(x); // expected-error {{always_inline function 'test1' requires target feature 'htm', but would be inlined into function 'test2' that is compiled without support for 'htm'}}
+  return 0;
+}
Index: clang/lib/CodeGen/CodeGenFunction.cpp
===
--- clang/lib/CodeGen/CodeGenFunction.cpp
+++ clang/lib/CodeGen/CodeGenFunction.cpp
@@ -2611,6 +2611,16 @@
 }))
   CGM.getDiags().Report(Loc, diag::err_function_needs_feature)
   << FD->getDeclName() << TargetDecl->getDeclName() << MissingFeature;
+  } else if (!FD->isMultiVersion() && FD->hasAttr()) {
+llvm::StringMap CalleeFeatureMap;
+CGM.getContext().getFunctionFeatureMap(CalleeFeatureMap, TargetDecl);
+
+for (const auto &F : CalleeFeatureMap) {
+  if (F.getValue() && (!CallerFeatureMap.lookup(F.getKey()) ||
+   !CallerFeatureMap.find

[PATCH] D143467: [PowerPC] Add target feature requirement to builtins

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf created this revision.
qiucf added reviewers: nemanjai, sfertile, amyk, shchenz, lkail, PowerPC.
Herald added a subscriber: kbarton.
Herald added a project: All.
qiucf requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Clang has mechanism to specify required target features of a built-in function. 
This patch adds such definitions to Altivec, VSX, HTM, PairedVec and MMA 
builtins.

This will help frontend to detect incompatible target features of bulitin when 
using `__attribute__((target("feature")))` syntax. For example,

  __attribute__((target("no-vsx")))
  void foo(vector double* d) {
vector double a, b;
*d = __builtin_vsx_xvmaxdp(a, b); // This would crash without this patch.
  }


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D143467

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-altivec.c
  clang/test/CodeGen/PowerPC/builtins-ppc-fma.c
  clang/test/CodeGen/PowerPC/builtins-ppc-fpconstrained.c
  clang/test/CodeGen/PowerPC/builtins-ppc-htm.c
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.c

Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.c
@@ -16,110 +16,47 @@
 extern double d;
 extern float f;
 
-int test_builtin_ppc_compare_exp_uo() {
-// CHECK-LABEL:   @test_builtin_ppc_compare_exp_uo
-// CHECK: [[TMP:%.*]] = call i32 @llvm.ppc.compare.exp.uo(double %0, double %1)
-// CHECK-NEXT:ret i32 [[TMP]]
-// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs
-// CHECK-NOVSX-ERR: error: this builtin requires VSX to be enabled
-  return __builtin_ppc_compare_exp_uo(d, d);
-}
-
-int test_builtin_ppc_compare_exp_lt() {
-// CHECK-LABEL:   @test_builtin_ppc_compare_exp_lt
-// CHECK: [[TMP:%.*]] = call i32 @llvm.ppc.compare.exp.lt(double %0, double %1)
-// CHECK-NEXT:ret i32 [[TMP]]
-// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs
-// CHECK-NOVSX-ERR: error: this builtin requires VSX to be enabled
-  return __builtin_ppc_compare_exp_lt(d, d);
-}
-
-int test_builtin_ppc_compare_exp_gt() {
-// CHECK-LABEL:   @test_builtin_ppc_compare_exp_gt
-// CHECK: [[TMP:%.*]] = call i32 @llvm.ppc.compare.exp.gt(double %0, double %1)
-// CHECK-NEXT:ret i32 [[TMP]]
-// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs
-// CHECK-NOVSX-ERR: error: this builtin requires VSX to be enabled
-  return __builtin_ppc_compare_exp_gt(d, d);
-}
-
-int test_builtin_ppc_compare_exp_eq() {
-// CHECK-LABEL:   @test_builtin_ppc_compare_exp_eq
-// CHECK: [[TMP:%.*]] = call i32 @llvm.ppc.compare.exp.eq(double %0, double %1)
-// CHECK-NEXT:ret i32 [[TMP]]
-// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs
-// CHECK-NOVSX-ERR: error: this builtin requires VSX to be enabled
-  return __builtin_ppc_compare_exp_eq(d, d);
-}
-
-int test_builtin_ppc_test_data_class_d() {
-// CHECK-LABEL:   @test_builtin_ppc_test_data_class_d
-// CHECK: [[TMP:%.*]] = call i32 @llvm.ppc.test.data.class.f64(double %0, i32 0)
-// CHECK-NEXT:ret i32 [[TMP]]
-// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs
-// CHECK-NOVSX-ERR: error: this builtin requires VSX to be enabled
-  return __builtin_ppc_test_data_class(d, 0);
-}
-
-int test_builtin_ppc_test_data_class_f() {
-// CHECK-LABEL:   @test_builtin_ppc_test_data_class_f
-// CHECK: [[TMP:%.*]] = call i32 @llvm.ppc.test.data.class.f32(float %0, i32 0)
-// CHECK-NEXT:ret i32 [[TMP]]
-// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs
-// CHECK-NOVSX-ERR: error: this builtin requires VSX to be enabled
-  return __builtin_ppc_test_data_class(f, 0);
-}
-
-int test_compare_exp_uo() {
-// CHECK-LABEL:   @test_compare_exp_uo
-// CHECK: [[TMP:%.*]] = call i32 @llvm.ppc.compare.exp.uo(double %0, double %1)
-// CHECK-NEXT:ret i32 [[TMP]]
-// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs
-// CHECK-NOVSX-ERR: error: this builtin requires VSX to be enabled
-  return __compare_exp_uo(d, d);
-}
-
-int test_compare_exp_lt() {
-// CHECK-LABEL:   @test_compare_exp_lt
-// CHECK: [[TMP:%.*]] = call i32 @llvm.ppc.compare.exp.lt(double %0, double %1)
-// CHECK-NEXT:ret i32 [[TMP]]
-// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later CPUs
-// CHECK-NOVSX-ERR: error: this builtin requires VSX to be enabl

[PATCH] D139507: [Intrinsic] Rename flt.rounds intrinsic to get.rounding

[Qiu Chaofan via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa40ef656d812: [Intrinsic] Rename flt.rounds intrinsic to 
get.rounding (authored by qiucf).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139507/new/

https://reviews.llvm.org/D139507

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-msp430.c
  clang/test/CodeGen/builtins.c
  llvm/docs/LangRef.rst
  llvm/include/llvm/CodeGen/ISDOpcodes.h
  llvm/include/llvm/IR/Intrinsics.td
  llvm/lib/CodeGen/IntrinsicLowering.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  llvm/lib/IR/AutoUpgrade.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/test/Bitcode/Inputs/auto_upgrade_flt_rounds.bc
  llvm/test/Bitcode/auto_upgrade_flt_rounds.test
  llvm/test/CodeGen/AArch64/arm64-fpcr.ll
  llvm/test/CodeGen/AArch64/strict-fp-opt.ll
  llvm/test/CodeGen/ARM/2012-03-05-FPSCR-bug.ll
  llvm/test/CodeGen/ARM/fpscr-intrinsics.ll
  llvm/test/CodeGen/ARM/no-fpscr-liveness.ll
  llvm/test/CodeGen/MSP430/flt_rounds.ll
  llvm/test/CodeGen/PowerPC/frounds.ll
  llvm/test/CodeGen/RISCV/flt-rounds.ll
  llvm/test/CodeGen/RISCV/fpenv.ll
  llvm/test/CodeGen/X86/flt-rounds.ll

Index: llvm/test/CodeGen/X86/flt-rounds.ll
===
--- llvm/test/CodeGen/X86/flt-rounds.ll
+++ llvm/test/CodeGen/X86/flt-rounds.ll
@@ -3,7 +3,7 @@
 ; RUN: llc -mtriple=i686-unknown-linux-gnu -mattr=-sse2 -verify-machineinstrs < %s | FileCheck %s --check-prefix=X86
 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=X64
 
-declare i32 @llvm.flt.rounds()
+declare i32 @llvm.get.rounding()
 
 define i32 @test_flt_rounds() nounwind {
 ; X86-LABEL: test_flt_rounds:
@@ -31,7 +31,7 @@
 ; X64-NEXT:shrl %cl, %eax
 ; X64-NEXT:andl $3, %eax
 ; X64-NEXT:retq
-  %1 = call i32 @llvm.flt.rounds()
+  %1 = call i32 @llvm.get.rounding()
   ret i32 %1
 }
 
@@ -172,21 +172,21 @@
 ; X64-NEXT:retq
 entry:
   %call = tail call i32 @fesetround(i32 1024)
-  %0 = tail call i32 @llvm.flt.rounds()
+  %0 = tail call i32 @llvm.get.rounding()
   %cmp = icmp ne i32 %0, 3
   %spec.select = zext i1 %cmp to i32
   %call1 = tail call i32 @fesetround(i32 0)
-  %1 = tail call i32 @llvm.flt.rounds()
+  %1 = tail call i32 @llvm.get.rounding()
   %cmp2 = icmp eq i32 %1, 1
   %inc4 = select i1 %cmp, i32 2, i32 1
   %errs.1 = select i1 %cmp2, i32 %spec.select, i32 %inc4
   %call6 = tail call i32 @fesetround(i32 3072)
-  %2 = tail call i32 @llvm.flt.rounds()
+  %2 = tail call i32 @llvm.get.rounding()
   %cmp7 = icmp ne i32 %2, 0
   %inc9 = zext i1 %cmp7 to i32
   %spec.select22 = add nuw nsw i32 %errs.1, %inc9
   %call11 = tail call i32 @fesetround(i32 2048)
-  %3 = tail call i32 @llvm.flt.rounds()
+  %3 = tail call i32 @llvm.get.rounding()
   %cmp12 = icmp ne i32 %3, 2
   %inc14.neg = sext i1 %cmp12 to i32
   %cmp16 = icmp ne i32 %spec.select22, %inc14.neg
Index: llvm/test/CodeGen/RISCV/fpenv.ll
===
--- llvm/test/CodeGen/RISCV/fpenv.ll
+++ llvm/test/CodeGen/RISCV/fpenv.ll
@@ -22,7 +22,7 @@
 ; RV64IF-NEXT:srl a0, a1, a0
 ; RV64IF-NEXT:andi a0, a0, 7
 ; RV64IF-NEXT:ret
-  %rm = call i32 @llvm.flt.rounds()
+  %rm = call i32 @llvm.get.rounding()
   ret i32 %rm
 }
 
@@ -122,4 +122,4 @@
 }
 
 declare void @llvm.set.rounding(i32)
-declare i32 @llvm.flt.rounds()
+declare i32 @llvm.get.rounding()
Index: llvm/test/CodeGen/RISCV/flt-rounds.ll
===
--- llvm/test/CodeGen/RISCV/flt-rounds.ll
+++ llvm/test/CodeGen/RISCV/flt-rounds.ll
@@ -4,7 +4,7 @@
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
-declare i32 @llvm.flt.rounds()
+declare i32 @llvm.get.rounding()
 
 define i32 @test_flt_rounds() nounwind {
 ; RV32I-LABEL: test_flt_rounds:
@@ -16,6 +16,6 @@
 ; RV64I:   # %bb.0:
 ; RV64I-NEXT:li a0, 1
 ; RV64I-NEXT:ret
-  %1 = call i32 @llvm.flt.rounds()
+  %1 = call i32 @llvm.get.rounding()
   ret i32 %1
 }
Index: llvm/test/CodeGen/PowerPC/frounds.ll
===
--- llvm/test/CodeGen/PowerPC/frounds.ll
+++ llvm/test/CodeGen/PowerPC/frounds.ll
@@ -66,7 +66,7 @@
 	%retval

[PATCH] D139507: [Intrinsic] Rename flt.rounds intrinsic to get.rounding

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf updated this revision to Diff 483434.
qiucf marked 3 inline comments as done.
qiucf removed a reviewer: libc++abi.
qiucf removed a project: libc++abi.
qiucf removed a subscriber: libcxx-commits.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139507/new/

https://reviews.llvm.org/D139507

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-msp430.c
  clang/test/CodeGen/builtins.c
  llvm/docs/LangRef.rst
  llvm/include/llvm/CodeGen/ISDOpcodes.h
  llvm/include/llvm/IR/Intrinsics.td
  llvm/lib/CodeGen/IntrinsicLowering.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  llvm/lib/IR/AutoUpgrade.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/test/Bitcode/Inputs/auto_upgrade_flt_rounds.bc
  llvm/test/Bitcode/auto_upgrade_flt_rounds.test
  llvm/test/CodeGen/AArch64/arm64-fpcr.ll
  llvm/test/CodeGen/AArch64/strict-fp-opt.ll
  llvm/test/CodeGen/ARM/2012-03-05-FPSCR-bug.ll
  llvm/test/CodeGen/ARM/fpscr-intrinsics.ll
  llvm/test/CodeGen/ARM/no-fpscr-liveness.ll
  llvm/test/CodeGen/MSP430/flt_rounds.ll
  llvm/test/CodeGen/PowerPC/frounds.ll
  llvm/test/CodeGen/RISCV/flt-rounds.ll
  llvm/test/CodeGen/RISCV/fpenv.ll
  llvm/test/CodeGen/X86/flt-rounds.ll

Index: llvm/test/CodeGen/X86/flt-rounds.ll
===
--- llvm/test/CodeGen/X86/flt-rounds.ll
+++ llvm/test/CodeGen/X86/flt-rounds.ll
@@ -3,7 +3,7 @@
 ; RUN: llc -mtriple=i686-unknown-linux-gnu -mattr=-sse2 -verify-machineinstrs < %s | FileCheck %s --check-prefix=X86
 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=X64
 
-declare i32 @llvm.flt.rounds()
+declare i32 @llvm.get.rounding()
 
 define i32 @test_flt_rounds() nounwind {
 ; X86-LABEL: test_flt_rounds:
@@ -31,7 +31,7 @@
 ; X64-NEXT:shrl %cl, %eax
 ; X64-NEXT:andl $3, %eax
 ; X64-NEXT:retq
-  %1 = call i32 @llvm.flt.rounds()
+  %1 = call i32 @llvm.get.rounding()
   ret i32 %1
 }
 
@@ -172,21 +172,21 @@
 ; X64-NEXT:retq
 entry:
   %call = tail call i32 @fesetround(i32 1024)
-  %0 = tail call i32 @llvm.flt.rounds()
+  %0 = tail call i32 @llvm.get.rounding()
   %cmp = icmp ne i32 %0, 3
   %spec.select = zext i1 %cmp to i32
   %call1 = tail call i32 @fesetround(i32 0)
-  %1 = tail call i32 @llvm.flt.rounds()
+  %1 = tail call i32 @llvm.get.rounding()
   %cmp2 = icmp eq i32 %1, 1
   %inc4 = select i1 %cmp, i32 2, i32 1
   %errs.1 = select i1 %cmp2, i32 %spec.select, i32 %inc4
   %call6 = tail call i32 @fesetround(i32 3072)
-  %2 = tail call i32 @llvm.flt.rounds()
+  %2 = tail call i32 @llvm.get.rounding()
   %cmp7 = icmp ne i32 %2, 0
   %inc9 = zext i1 %cmp7 to i32
   %spec.select22 = add nuw nsw i32 %errs.1, %inc9
   %call11 = tail call i32 @fesetround(i32 2048)
-  %3 = tail call i32 @llvm.flt.rounds()
+  %3 = tail call i32 @llvm.get.rounding()
   %cmp12 = icmp ne i32 %3, 2
   %inc14.neg = sext i1 %cmp12 to i32
   %cmp16 = icmp ne i32 %spec.select22, %inc14.neg
Index: llvm/test/CodeGen/RISCV/fpenv.ll
===
--- llvm/test/CodeGen/RISCV/fpenv.ll
+++ llvm/test/CodeGen/RISCV/fpenv.ll
@@ -22,7 +22,7 @@
 ; RV64IF-NEXT:srl a0, a1, a0
 ; RV64IF-NEXT:andi a0, a0, 7
 ; RV64IF-NEXT:ret
-  %rm = call i32 @llvm.flt.rounds()
+  %rm = call i32 @llvm.get.rounding()
   ret i32 %rm
 }
 
@@ -122,4 +122,4 @@
 }
 
 declare void @llvm.set.rounding(i32)
-declare i32 @llvm.flt.rounds()
+declare i32 @llvm.get.rounding()
Index: llvm/test/CodeGen/RISCV/flt-rounds.ll
===
--- llvm/test/CodeGen/RISCV/flt-rounds.ll
+++ llvm/test/CodeGen/RISCV/flt-rounds.ll
@@ -4,7 +4,7 @@
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
-declare i32 @llvm.flt.rounds()
+declare i32 @llvm.get.rounding()
 
 define i32 @test_flt_rounds() nounwind {
 ; RV32I-LABEL: test_flt_rounds:
@@ -16,6 +16,6 @@
 ; RV64I:   # %bb.0:
 ; RV64I-NEXT:li a0, 1
 ; RV64I-NEXT:ret
-  %1 = call i32 @llvm.flt.rounds()
+  %1 = call i32 @llvm.get.rounding()
   ret i32 %1
 }
Index: llvm/test/CodeGen/PowerPC/frounds.ll
===
--- llvm/test/CodeGen/PowerPC/frounds.ll
+++ llvm/test/CodeGen/PowerPC/frounds.ll
@@ -66,7 +66,7 @@
 	%retval = alloca i32		;  [#uses=2]
 	%tmp = all

[PATCH] D139450: Warn about unsupported ibmlongdouble

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.

Committed as 
https://github.com/llvm/llvm-project/commit/5f68c4111ab9c79b902723df3986dd1033813c01

`ppc-float-abi-warning.cpp` would fail when testing on machine with glibc older 
than 2.32 but `PPC_LINUX_DEFAULT_IEEELONGDOUBLE` enabled, which is known 
failure even before this patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139450/new/

https://reviews.llvm.org/D139450

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D139450: Warn about unsupported ibmlongdouble

[Qiu Chaofan via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG5f68c4111ab9: Warn about unsupported ibmlongdouble (authored 
by tuliom, committed by qiucf).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139450/new/

https://reviews.llvm.org/D139450

Files:
  clang/lib/Driver/ToolChains/PPCLinux.cpp
  clang/lib/Driver/ToolChains/PPCLinux.h
  clang/test/CMakeLists.txt
  clang/test/Driver/lit.local.cfg
  clang/test/Driver/ppc-float-abi-warning.cpp
  clang/test/lit.site.cfg.py.in

Index: clang/test/lit.site.cfg.py.in
===
--- clang/test/lit.site.cfg.py.in
+++ clang/test/lit.site.cfg.py.in
@@ -38,6 +38,7 @@
 config.clang_vendor_uti = "@CLANG_VENDOR_UTI@"
 config.llvm_external_lit = path(r"@LLVM_EXTERNAL_LIT@")
 config.standalone_build = @CLANG_BUILT_STANDALONE@
+config.ppc_linux_default_ieeelongdouble = @PPC_LINUX_DEFAULT_IEEELONGDOUBLE@
 
 import lit.llvm
 lit.llvm.initialize(lit_config, config)
Index: clang/test/Driver/ppc-float-abi-warning.cpp
===
--- clang/test/Driver/ppc-float-abi-warning.cpp
+++ clang/test/Driver/ppc-float-abi-warning.cpp
@@ -7,12 +7,23 @@
 // RUN:  --dyld-prefix=%S/Inputs/powerpc64le-linux-gnu-tree/gcc-12 \
 // RUN:  -mabi=ieeelongdouble -stdlib=libstdc++ 2>&1 | \
 // RUN:  FileCheck %s --check-prefix=NOWARN
-// RUN: %clang -### --driver-mode=g++ -target powerpc64le-linux-gnu %s \
-// RUN:  -mabi=ieeelongdouble -stdlib=libc++ 2>&1 | FileCheck %s
+// RUN: %clang -### --driver-mode=g++ -target powerpc64le-linux-gnu %s\
+// RUN:  -stdlib=libc++ 2>&1 | \
+// RUN:  FileCheck %s --check-prefix=NOWARN
+// RUN: %clang -### --driver-mode=g++ -target powerpc64le-linux-gnu %s\
+// RUN:  -mabi=ibmlongdouble -stdlib=libc++ -Wno-unsupported-abi 2>&1 | \
+// RUN:  FileCheck %s --check-prefix=NOWARN
 // RUN: %clang -### --driver-mode=g++ -target powerpc64le-linux-gnu %s\
 // RUN:  -mabi=ieeelongdouble -stdlib=libc++ -Wno-unsupported-abi 2>&1 | \
 // RUN:  FileCheck %s --check-prefix=NOWARN
+// RUN: %clang -### --driver-mode=g++ -target powerpc64le-linux-gnu %s\
+// RUN:  -mabi=%if ppc_linux_default_ieeelongdouble %{ieeelongdouble%} \
+// RUN:  %else %{ibmlongdouble%} -stdlib=libc++ 2>&1 | \
+// RUN:  FileCheck %s --check-prefix=NOWARN
+// RUN: %clang -### --driver-mode=g++ -target powerpc64le-linux-gnu %s\
+// RUN:  -mabi=%if ppc_linux_default_ieeelongdouble %{ibmlongdouble%} \
+// RUN:  %else %{ieeelongdouble%} -stdlib=libc++ 2>&1 | FileCheck %s
 
-// CHECK: warning: float ABI 'ieeelongdouble' is not supported by current library
-// NOWARN-NOT: warning: float ABI 'ieeelongdouble' is not supported by current library
+// CHECK: warning: float ABI '{{.*}}' is not supported by current library
+// NOWARN-NOT: warning: float ABI '{{.*}}' is not supported by current library
 long double foo(long double x) { return x; }
Index: clang/test/Driver/lit.local.cfg
===
--- clang/test/Driver/lit.local.cfg
+++ clang/test/Driver/lit.local.cfg
@@ -21,3 +21,6 @@
 
 if llvm_config.use_lld(required=False):
 config.available_features.add('lld')
+
+if config.ppc_linux_default_ieeelongdouble:
+  config.available_features.add('ppc_linux_default_ieeelongdouble')
Index: clang/test/CMakeLists.txt
===
--- clang/test/CMakeLists.txt
+++ clang/test/CMakeLists.txt
@@ -15,6 +15,7 @@
   LLVM_ENABLE_PER_TARGET_RUNTIME_DIR
   LLVM_ENABLE_THREADS
   LLVM_WITH_Z3
+  PPC_LINUX_DEFAULT_IEEELONGDOUBLE
   )
 
 configure_lit_site_cfg(
Index: clang/lib/Driver/ToolChains/PPCLinux.h
===
--- clang/lib/Driver/ToolChains/PPCLinux.h
+++ clang/lib/Driver/ToolChains/PPCLinux.h
@@ -27,6 +27,8 @@
 private:
   bool SupportIEEEFloat128(const Driver &D, const llvm::Triple &Triple,
const llvm::opt::ArgList &Args) const;
+  bool supportIBMLongDouble(const Driver &D,
+const llvm::opt::ArgList &Args) const;
 };
 
 } // end namespace toolchains
Index: clang/lib/Driver/ToolChains/PPCLinux.cpp
===
--- clang/lib/Driver/ToolChains/PPCLinux.cpp
+++ clang/lib/Driver/ToolChains/PPCLinux.cpp
@@ -49,7 +49,10 @@
 : Linux(D, Triple, Args) {
   if (Arg *A = Args.getLastArg(options::OPT_mabi_EQ)) {
 StringRef ABIName = A->getValue();
-if (ABIName == "ieeelongdouble" && !SupportIEEEFloat128(D, Triple, Args))
+
+if ((ABIName == "ieeelongdouble" &&
+ !SupportIEEEFloat128(D, Triple, Args)) ||
+(ABIName == "ibmlongdouble" && !supportIBMLongDouble(D, Args)))
   D.Diag(diag::warn_drv_unsupported_float_abi_by_lib) << ABIName;
   }
 }
@@ -67,6 +70,18 @@
   Linux::AddClangSystemIncludeArgs(DriverArgs, CC1Args);
 }
 
+bool PPCLinuxToolChain::

[PATCH] D139507: [Intrinsic] Rename flt.rounds intrinsic to get.rounding

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf updated this revision to Diff 482381.
qiucf retitled this revision from "[Intrinsic] Add get.rounding as alias to 
flt.rounds and rename related DAG nodes" to "[Intrinsic] Rename flt.rounds 
intrinsic to get.rounding".
qiucf edited the summary of this revision.
qiucf added a comment.

Use AutoUpgrade to rename flt.rounds to get.rounding.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139507/new/

https://reviews.llvm.org/D139507

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-msp430.c
  clang/test/CodeGen/builtins.c
  libcxxabi/test/test_demangle.pass.cpp
  llvm/docs/LangRef.rst
  llvm/include/llvm/CodeGen/ISDOpcodes.h
  llvm/include/llvm/IR/Intrinsics.td
  llvm/lib/CodeGen/IntrinsicLowering.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  llvm/lib/IR/AutoUpgrade.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/test/CodeGen/AArch64/arm64-fpcr.ll
  llvm/test/CodeGen/AArch64/strict-fp-opt.ll
  llvm/test/CodeGen/ARM/2012-03-05-FPSCR-bug.ll
  llvm/test/CodeGen/ARM/fpscr-intrinsics.ll
  llvm/test/CodeGen/ARM/no-fpscr-liveness.ll
  llvm/test/CodeGen/MSP430/flt_rounds.ll
  llvm/test/CodeGen/PowerPC/frounds.ll
  llvm/test/CodeGen/RISCV/flt-rounds.ll
  llvm/test/CodeGen/RISCV/fpenv.ll
  llvm/test/CodeGen/X86/flt-rounds.ll

Index: llvm/test/CodeGen/X86/flt-rounds.ll
===
--- llvm/test/CodeGen/X86/flt-rounds.ll
+++ llvm/test/CodeGen/X86/flt-rounds.ll
@@ -3,7 +3,7 @@
 ; RUN: llc -mtriple=i686-unknown-linux-gnu -mattr=-sse2 -verify-machineinstrs < %s | FileCheck %s --check-prefix=X86
 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=X64
 
-declare i32 @llvm.flt.rounds()
+declare i32 @llvm.get.rounding()
 
 define i32 @test_flt_rounds() nounwind {
 ; X86-LABEL: test_flt_rounds:
@@ -31,7 +31,7 @@
 ; X64-NEXT:shrl %cl, %eax
 ; X64-NEXT:andl $3, %eax
 ; X64-NEXT:retq
-  %1 = call i32 @llvm.flt.rounds()
+  %1 = call i32 @llvm.get.rounding()
   ret i32 %1
 }
 
@@ -172,21 +172,21 @@
 ; X64-NEXT:retq
 entry:
   %call = tail call i32 @fesetround(i32 1024)
-  %0 = tail call i32 @llvm.flt.rounds()
+  %0 = tail call i32 @llvm.get.rounding()
   %cmp = icmp ne i32 %0, 3
   %spec.select = zext i1 %cmp to i32
   %call1 = tail call i32 @fesetround(i32 0)
-  %1 = tail call i32 @llvm.flt.rounds()
+  %1 = tail call i32 @llvm.get.rounding()
   %cmp2 = icmp eq i32 %1, 1
   %inc4 = select i1 %cmp, i32 2, i32 1
   %errs.1 = select i1 %cmp2, i32 %spec.select, i32 %inc4
   %call6 = tail call i32 @fesetround(i32 3072)
-  %2 = tail call i32 @llvm.flt.rounds()
+  %2 = tail call i32 @llvm.get.rounding()
   %cmp7 = icmp ne i32 %2, 0
   %inc9 = zext i1 %cmp7 to i32
   %spec.select22 = add nuw nsw i32 %errs.1, %inc9
   %call11 = tail call i32 @fesetround(i32 2048)
-  %3 = tail call i32 @llvm.flt.rounds()
+  %3 = tail call i32 @llvm.get.rounding()
   %cmp12 = icmp ne i32 %3, 2
   %inc14.neg = sext i1 %cmp12 to i32
   %cmp16 = icmp ne i32 %spec.select22, %inc14.neg
Index: llvm/test/CodeGen/RISCV/fpenv.ll
===
--- llvm/test/CodeGen/RISCV/fpenv.ll
+++ llvm/test/CodeGen/RISCV/fpenv.ll
@@ -22,7 +22,7 @@
 ; RV64IF-NEXT:srl a0, a1, a0
 ; RV64IF-NEXT:andi a0, a0, 7
 ; RV64IF-NEXT:ret
-  %rm = call i32 @llvm.flt.rounds()
+  %rm = call i32 @llvm.get.rounding()
   ret i32 %rm
 }
 
@@ -122,4 +122,4 @@
 }
 
 declare void @llvm.set.rounding(i32)
-declare i32 @llvm.flt.rounds()
+declare i32 @llvm.get.rounding()
Index: llvm/test/CodeGen/RISCV/flt-rounds.ll
===
--- llvm/test/CodeGen/RISCV/flt-rounds.ll
+++ llvm/test/CodeGen/RISCV/flt-rounds.ll
@@ -4,7 +4,7 @@
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
-declare i32 @llvm.flt.rounds()
+declare i32 @llvm.get.rounding()
 
 define i32 @test_flt_rounds() nounwind {
 ; RV32I-LABEL: test_flt_rounds:
@@ -16,6 +16,6 @@
 ; RV64I:   # %bb.0:
 ; RV64I-NEXT:li a0, 1
 ; RV64I-NEXT:ret
-  %1 = call i32 @llvm.flt.rounds()
+  %1 = call i32 @llvm.get.rounding()
   ret i32 %1
 }
Index: llvm/test/CodeGen/PowerPC/frounds.ll
===
--- llvm/test/CodeGen/PowerPC/frounds.ll
+++ llvm/test/CodeGen/Pow

[PATCH] D139450: Warn about unsupported ibmlongdouble

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added inline comments.



Comment at: clang/test/Driver/lit.local.cfg:26
+if config.ppc_linux_default_ieeelongdouble == "ON":
+  config.available_features.add('ppc_linux_default_ieeelongdouble')

tuliom wrote:
> qiucf wrote:
> > Can we assume if we are compiling with `-mabi=ieeelongdouble`, then libc++ 
> > 'must' be built with the same long double ABI? If I understand correctly, 
> > they're unrelated.
> @qiucf I didn't understand this part. Are you suggesting to remove the long 
> double warnings because the way the compiler was built is unrelated to the 
> way libc++ was built?
Ah, I misunderstood meaning of 'defaults to IEEE long double' in last review. 
We can assume 'how the compiler was built' is the same as 'how the libc++ was 
built'.

But when 'how the libc++ was built' conflicts with 'how the compiler compiles 
current program', we expect a warning, right? If so, this looks reasonable.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139450/new/

https://reviews.llvm.org/D139450

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D139450: Warn about unsupported ibmlongdouble

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.

Thanks for the patch! But does libc++ support to be built with 
`-mabi=ieeelongdouble` now? (like libstdc++, if it works correctly, it should 
co-exist and be linked with different long double ABIs)




Comment at: clang/lib/Driver/ToolChains/PPCLinux.cpp:96
   bool HasUnsupportedCXXLib =
-  StdLib == CST_Libcxx ||
+  (StdLib == CST_Libcxx && !defaultToIEEELongDouble()) ||
   (StdLib == CST_Libstdcxx &&

`SupportIEEEFloat128` checks the library version:

* If using libstdc++, then libstdc++ (GCC) >= 12.1.0 is okay.
* If using libc++, then sorry, no libc++ supports `-mabi=ieeelongdouble` now.
* Glibc should >= 2.32

If the assumptions are still right, this changes its meaning (and 
`supportIBMLongDouble` has different meaning from it).



Comment at: clang/test/Driver/lit.local.cfg:26
+if config.ppc_linux_default_ieeelongdouble == "ON":
+  config.available_features.add('ppc_linux_default_ieeelongdouble')

Can we assume if we are compiling with `-mabi=ieeelongdouble`, then libc++ 
'must' be built with the same long double ABI? If I understand correctly, 
they're unrelated.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139450/new/

https://reviews.llvm.org/D139450

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D112932: [WIP] Use llvm.is_fpclass to implement FP classification functions

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.
Herald added a project: All.

This patch looks good and `llvm.is.fpclass` will by default be expanded (except 
SystemZ which has their own lowering). Is there any blocker for this?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112932/new/

https://reviews.llvm.org/D112932

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D139507: [Intrinsic] Add get.rounding as alias to flt.rounds and rename related DAG nodes

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.

In D139507#3978449 , @sepavloff wrote:

> Thank you for working on this!
>
> Is there any reason why we should keep the old intrinsic?

In case any user outside of clang references it (although I believe no), we can 
deprecate it and remove after a few releases.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139507/new/

https://reviews.llvm.org/D139507

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D138105: [PowerPC] Support test data class intrinsic of 128-bit float

[Qiu Chaofan via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG62f20f51ce39: [PowerPC] Support test data class intrinsic of 
128-bit float (authored by qiucf).

Changed prior to commit:
  https://reviews.llvm.org/D138105?vs=477375&id=480797#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138105/new/

https://reviews.llvm.org/D138105

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-p9-f128.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
@@ -77,11 +77,11 @@
 ; CHECK-NEXT:iseleq 3, 4, 3
 ; CHECK-NEXT:blr
 entry:
-  %test_data_class = tail call i32 @llvm.ppc.test.data.class.d(double %d, i32 0)
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f64(double %d, i32 0)
   ret i32 %test_data_class
 }
 
-declare i32 @llvm.ppc.test.data.class.d(double, i32 immarg)
+declare i32 @llvm.ppc.test.data.class.f64(double, i32 immarg)
 
 define i32 @test_builtin_ppc_test_data_class_f(float %f) {
 ; CHECK-LABEL: test_builtin_ppc_test_data_class_f:
@@ -92,8 +92,8 @@
 ; CHECK-NEXT:iseleq 3, 4, 3
 ; CHECK-NEXT:blr
 entry:
-  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f(float %f, i32 127)
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f32(float %f, i32 127)
   ret i32 %test_data_class
 }
 
-declare i32 @llvm.ppc.test.data.class.f(float, i32 immarg)
+declare i32 @llvm.ppc.test.data.class.f32(float, i32 immarg)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
@@ -136,3 +136,16 @@
 ; Function Attrs: nounwind readnone
 declare i64 @llvm.ppc.scalar.extract.expq(fp128)
 
+define i32 @test_data_class_f128(fp128 %d) {
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f128(fp128 %d, i32 0)
+  ret i32 %test_data_class
+; CHECK-LABEL: test_data_class_f128:
+; CHECK: xststdcqp cr0, v2, 0
+; CHECK-NEXT: li r3, 0
+; CHECK-NEXT: li r4, 1
+; CHECK-NEXT: iseleq r3, r4, r3
+; CHECK-NEXT: blr
+}
+
+declare i32 @llvm.ppc.test.data.class.f128(fp128, i32 immarg)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10689,11 +10689,11 @@
  DAG.getTargetConstant(Pred, dl, MVT::i32)}),
 0);
   }
-  case Intrinsic::ppc_test_data_class_d:
-  case Intrinsic::ppc_test_data_class_f: {
-unsigned CmprOpc = PPC::XSTSTDCDP;
-if (IntrinsicID == Intrinsic::ppc_test_data_class_f)
-  CmprOpc = PPC::XSTSTDCSP;
+  case Intrinsic::ppc_test_data_class: {
+EVT OpVT = Op.getOperand(1).getValueType();
+unsigned CmprOpc = OpVT == MVT::f128 ? PPC::XSTSTDCQP
+ : (OpVT == MVT::f64 ? PPC::XSTSTDCDP
+ : PPC::XSTSTDCSP);
 return SDValue(
 DAG.getMachineNode(
 PPC::SELECT_CC_I4, dl, MVT::i32,
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1893,12 +1893,9 @@
   DefaultAttrsIntrinsic<[llvm_i32_ty], 
 [llvm_double_ty, llvm_double_ty],
 [IntrNoMem]>;
-  def int_ppc_test_data_class_d : DefaultAttrsIntrinsic<[llvm_i32_ty],
-[llvm_double_ty, llvm_i32_ty],
-[IntrNoMem, ImmArg>]>;
-  def int_ppc_test_data_class_f : DefaultAttrsIntrinsic<[llvm_i32_ty],
-[llvm_float_ty, llvm_i32_ty],
-[IntrNoMem, ImmArg>]>;
+  def int_ppc_test_data_class : Intrinsic<[llvm_i32_ty],
+  [llvm_anyfloat_ty, llvm_i32_ty],
+  [IntrNoMem, ImmArg>]>;
   def int_ppc_fnabs
   : ClangBuiltin<"__builtin_ppc_fnabs">,
 DefaultAttrsIntrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
In

[PATCH] D139507: [Intrinsic] Add get.rounding as alias to flt.rounds and rename related DAG nodes

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf created this revision.
qiucf added reviewers: andrew.w.kaylor, sepavloff, kpn, RKSimon, craig.topper, 
nemanjai, cameron.mcinally.
Herald added subscribers: jeroen.dobbelaere, StephenFan, frasercrmck, 
jdoerfert, luismarques, apazos, sameer.abuasal, pengfei, s.egerton, Jim, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, kbarton, 
hiraditya, arichardson.
Herald added a project: All.
qiucf requested review of this revision.
Herald added subscribers: llvm-commits, libcxx-commits, cfe-commits, 
pcwang-thead, MaskRay.
Herald added projects: clang, libc++abi, LLVM.
Herald added a reviewer: libc++abi.

This is to address the inconsistency between `FLT_ROUNDS_` and `SET_ROUNDING` 
SDAG node. Rename `FLT_ROUNDS_` to `GET_ROUNDING` and add new 
`llvm.get.rounding` intrinsic. For compatibility, `@llvm.flt.rounds` is kept.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139507

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-msp430.c
  clang/test/CodeGen/builtins.c
  libcxxabi/test/test_demangle.pass.cpp
  llvm/docs/LangRef.rst
  llvm/include/llvm/CodeGen/ISDOpcodes.h
  llvm/include/llvm/IR/Intrinsics.td
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/test/CodeGen/AArch64/arm64-fpcr.ll
  llvm/test/CodeGen/AArch64/strict-fp-opt.ll
  llvm/test/CodeGen/ARM/2012-03-05-FPSCR-bug.ll
  llvm/test/CodeGen/ARM/fpscr-intrinsics.ll
  llvm/test/CodeGen/ARM/no-fpscr-liveness.ll
  llvm/test/CodeGen/MSP430/flt_rounds.ll
  llvm/test/CodeGen/PowerPC/frounds.ll
  llvm/test/CodeGen/RISCV/flt-rounds.ll
  llvm/test/CodeGen/RISCV/fpenv.ll
  llvm/test/CodeGen/X86/flt-rounds.ll

Index: llvm/test/CodeGen/X86/flt-rounds.ll
===
--- llvm/test/CodeGen/X86/flt-rounds.ll
+++ llvm/test/CodeGen/X86/flt-rounds.ll
@@ -3,7 +3,7 @@
 ; RUN: llc -mtriple=i686-unknown-linux-gnu -mattr=-sse2 -verify-machineinstrs < %s | FileCheck %s --check-prefix=X86
 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=X64
 
-declare i32 @llvm.flt.rounds()
+declare i32 @llvm.get.rounding()
 
 define i32 @test_flt_rounds() nounwind {
 ; X86-LABEL: test_flt_rounds:
@@ -31,7 +31,7 @@
 ; X64-NEXT:shrl %cl, %eax
 ; X64-NEXT:andl $3, %eax
 ; X64-NEXT:retq
-  %1 = call i32 @llvm.flt.rounds()
+  %1 = call i32 @llvm.get.rounding()
   ret i32 %1
 }
 
@@ -172,21 +172,21 @@
 ; X64-NEXT:retq
 entry:
   %call = tail call i32 @fesetround(i32 1024)
-  %0 = tail call i32 @llvm.flt.rounds()
+  %0 = tail call i32 @llvm.get.rounding()
   %cmp = icmp ne i32 %0, 3
   %spec.select = zext i1 %cmp to i32
   %call1 = tail call i32 @fesetround(i32 0)
-  %1 = tail call i32 @llvm.flt.rounds()
+  %1 = tail call i32 @llvm.get.rounding()
   %cmp2 = icmp eq i32 %1, 1
   %inc4 = select i1 %cmp, i32 2, i32 1
   %errs.1 = select i1 %cmp2, i32 %spec.select, i32 %inc4
   %call6 = tail call i32 @fesetround(i32 3072)
-  %2 = tail call i32 @llvm.flt.rounds()
+  %2 = tail call i32 @llvm.get.rounding()
   %cmp7 = icmp ne i32 %2, 0
   %inc9 = zext i1 %cmp7 to i32
   %spec.select22 = add nuw nsw i32 %errs.1, %inc9
   %call11 = tail call i32 @fesetround(i32 2048)
-  %3 = tail call i32 @llvm.flt.rounds()
+  %3 = tail call i32 @llvm.get.rounding()
   %cmp12 = icmp ne i32 %3, 2
   %inc14.neg = sext i1 %cmp12 to i32
   %cmp16 = icmp ne i32 %spec.select22, %inc14.neg
Index: llvm/test/CodeGen/RISCV/fpenv.ll
===
--- llvm/test/CodeGen/RISCV/fpenv.ll
+++ llvm/test/CodeGen/RISCV/fpenv.ll
@@ -22,7 +22,7 @@
 ; RV64IF-NEXT:srl a0, a1, a0
 ; RV64IF-NEXT:andi a0, a0, 7
 ; RV64IF-NEXT:ret
-  %rm = call i32 @llvm.flt.rounds()
+  %rm = call i32 @llvm.get.rounding()
   ret i32 %rm
 }
 
@@ -122,4 +122,4 @@
 }
 
 declare void @llvm.set.rounding(i32)
-declare i32 @llvm.flt.rounds()
+declare i32 @llvm.get.rounding()
Index: llvm/test/CodeGen/RISCV/flt-rounds.ll
===
--- llvm/test/CodeGen/RISCV/flt-rounds.ll
+++ llvm/test/CodeGen/RISCV/flt-rounds.ll
@@ -4,7 +4,7 @@
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
-declare i32 @llvm.flt.rounds()
+declare i32 @llvm.get.rounding(

[PATCH] D138105: [PowerPC] Support test data class intrinsic of 128-bit float

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf updated this revision to Diff 477375.
qiucf added a comment.

Change error message regarding `__float128`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138105/new/

https://reviews.llvm.org/D138105

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-p9-f128.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-error.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
@@ -77,11 +77,11 @@
 ; CHECK-NEXT:iseleq 3, 4, 3
 ; CHECK-NEXT:blr
 entry:
-  %test_data_class = tail call i32 @llvm.ppc.test.data.class.d(double %d, i32 0)
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f64(double %d, i32 0)
   ret i32 %test_data_class
 }
 
-declare i32 @llvm.ppc.test.data.class.d(double, i32 immarg)
+declare i32 @llvm.ppc.test.data.class.f64(double, i32 immarg)
 
 define i32 @test_builtin_ppc_test_data_class_f(float %f) {
 ; CHECK-LABEL: test_builtin_ppc_test_data_class_f:
@@ -92,8 +92,8 @@
 ; CHECK-NEXT:iseleq 3, 4, 3
 ; CHECK-NEXT:blr
 entry:
-  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f(float %f, i32 127)
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f32(float %f, i32 127)
   ret i32 %test_data_class
 }
 
-declare i32 @llvm.ppc.test.data.class.f(float, i32 immarg)
+declare i32 @llvm.ppc.test.data.class.f32(float, i32 immarg)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
@@ -136,3 +136,16 @@
 ; Function Attrs: nounwind readnone
 declare i64 @llvm.ppc.scalar.extract.expq(fp128)
 
+define i32 @test_data_class_f128(fp128 %d) {
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f128(fp128 %d, i32 0)
+  ret i32 %test_data_class
+; CHECK-LABEL: test_data_class_f128:
+; CHECK: xststdcqp cr0, v2, 0
+; CHECK-NEXT: li r3, 0
+; CHECK-NEXT: li r4, 1
+; CHECK-NEXT: iseleq r3, r4, r3
+; CHECK-NEXT: blr
+}
+
+declare i32 @llvm.ppc.test.data.class.f128(fp128, i32 immarg)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10590,11 +10590,11 @@
  DAG.getTargetConstant(Pred, dl, MVT::i32)}),
 0);
   }
-  case Intrinsic::ppc_test_data_class_d:
-  case Intrinsic::ppc_test_data_class_f: {
-unsigned CmprOpc = PPC::XSTSTDCDP;
-if (IntrinsicID == Intrinsic::ppc_test_data_class_f)
-  CmprOpc = PPC::XSTSTDCSP;
+  case Intrinsic::ppc_test_data_class: {
+EVT OpVT = Op.getOperand(1).getValueType();
+unsigned CmprOpc = OpVT == MVT::f128 ? PPC::XSTSTDCQP
+ : (OpVT == MVT::f64 ? PPC::XSTSTDCDP
+ : PPC::XSTSTDCSP);
 return SDValue(
 DAG.getMachineNode(
 PPC::SELECT_CC_I4, dl, MVT::i32,
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1803,12 +1803,9 @@
Intrinsic<[llvm_i32_ty], 
  [llvm_double_ty, llvm_double_ty], 
  [IntrNoMem]>;
-  def int_ppc_test_data_class_d : Intrinsic<[llvm_i32_ty],
-[llvm_double_ty, llvm_i32_ty],
-[IntrNoMem, ImmArg>]>;
-  def int_ppc_test_data_class_f : Intrinsic<[llvm_i32_ty],
-[llvm_float_ty, llvm_i32_ty],
-[IntrNoMem, ImmArg>]>;
+  def int_ppc_test_data_class : Intrinsic<[llvm_i32_ty],
+  [llvm_anyfloat_ty, llvm_i32_ty],
+  [IntrNoMem, ImmArg>]>;
   def int_ppc_fnabs
   : ClangBuiltin<"__builtin_ppc_fnabs">,
 Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.c
+++ clang/test/CodeGen/

[PATCH] D137618: [Clang] Fix behavior of -ffp-model option when overriden

[Qiu Chaofan via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGcab9c02bd97f: [Clang] Fix behavior of -ffp-model option when 
overriden (authored by qiucf).

Changed prior to commit:
  https://reviews.llvm.org/D137618?vs=475981&id=476309#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137618/new/

https://reviews.llvm.org/D137618

Files:
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/CodeGen/ffp-model.c
  clang/test/Driver/fp-model.c


Index: clang/test/Driver/fp-model.c
===
--- clang/test/Driver/fp-model.c
+++ clang/test/Driver/fp-model.c
@@ -66,6 +66,17 @@
 // RUN:   | FileCheck --check-prefix=WARN10 %s
 // WARN10: warning: overriding '-ffp-model=strict' option with 
'-fdenormal-fp-math=preserve-sign,preserve-sign' [-Woverriding-t-option]
 
+// RUN: %clang -### -ffp-model=fast -ffp-model=strict -c %s 2>&1 | FileCheck \
+// RUN:   --check-prefix=WARN11 %s
+// WARN11: warning: overriding '-ffp-model=fast' option with 
'-ffp-model=strict' [-Woverriding-t-option]
+// WARN11-NOT: warning: overriding '-ffp-model=strict' option with 
'-ffp-model=strict' [-Woverriding-t-option]
+
+// RUN: %clang -### -Ofast -ffp-model=strict -c %s 2>&1 | FileCheck \
+// RUN:   --check-prefix=WARN12 %s
+// RUN: %clang -### -ffast-math -ffp-model=strict -c %s 2>&1 | FileCheck \
+// RUN:   --check-prefix=WARN12 %s
+// WARN12-NOT: warning: overriding '-ffp-model=strict' option with 
'-ffp-model=strict' [-Woverriding-t-option]
+
 // RUN: %clang -### -c %s 2>&1 \
 // RUN:   | FileCheck --check-prefix=CHECK-NOROUND %s
 // CHECK-NOROUND: "-cc1"
@@ -107,6 +118,13 @@
 // CHECK-FPM-STRICT: "-frounding-math"
 // CHECK-FPM-STRICT: "-ffp-exception-behavior=strict"
 
+// RUN: %clang -### -nostdinc -ffp-model=strict -ffp-model=fast -c %s 2>&1 \
+// RUN:   | FileCheck --check-prefix=CHECK-NO-EXCEPT %s
+// RUN: %clang -### -nostdinc -ffp-model=strict -ffast-math -c %s 2>&1 \
+// RUN:   | FileCheck --check-prefix=CHECK-NO-EXCEPT %s
+// RUN: %clang -### -nostdinc -ffp-model=strict -Ofast -c %s 2>&1 \
+// RUN:   | FileCheck --check-prefix=CHECK-NO-EXCEPT %s
+// CHECK-NO-EXCEPT-NOT: "-ffp-exception-behavior=strict"
 
 // RUN: %clang -### -nostdinc -ffp-exception-behavior=strict -c %s 2>&1 \
 // RUN:   | FileCheck --check-prefix=CHECK-FEB-STRICT %s
Index: clang/test/CodeGen/ffp-model.c
===
--- clang/test/CodeGen/ffp-model.c
+++ clang/test/CodeGen/ffp-model.c
@@ -36,9 +36,9 @@
 
   // CHECK-STRICT-FAST: load float, ptr
   // CHECK-STRICT-FAST: load float, ptr
-  // CHECK-STRICT-FAST: call fast float 
@llvm.experimental.constrained.fmul.f32(float {{.*}}, float {{.*}}, {{.*}})
+  // CHECK-STRICT-FAST: fmul fast float {{.*}}, {{.*}}
   // CHECK-STRICT-FAST: load float, ptr
-  // CHECK-STRICT-FAST: call fast float 
@llvm.experimental.constrained.fadd.f32(float {{.*}}, float {{.*}}, {{.*}}
+  // CHECK-STRICT-FAST: fadd fast float {{.*}}, {{.*}}
 
   // CHECK-FAST1: load float, ptr
   // CHECK-FAST1: load float, ptr
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -3041,6 +3041,7 @@
   SignedZeros = false;
   TrappingMath = false;
   RoundingFPMath = false;
+  FPExceptionBehavior = "";
   // If fast-math is set then set the fp-contract mode to fast.
   FPContract = "fast";
   SeenUnsafeMathModeOption = true;
@@ -3081,10 +3082,12 @@
   else {
 StrictFPModel = false;
 FPModel = "";
-D.Diag(clang::diag::warn_drv_overriding_flag_option)
-<< "-ffp-model=strict" <<
-((A->getNumValues() == 0) ?  A->getSpelling()
-: Args.MakeArgString(A->getSpelling() + A->getValue()));
+auto RHS = (A->getNumValues() == 0)
+   ? A->getSpelling()
+   : Args.MakeArgString(A->getSpelling() + A->getValue());
+if (RHS != "-ffp-model=strict")
+  D.Diag(clang::diag::warn_drv_overriding_flag_option)
+  << "-ffp-model=strict" << RHS;
   }
 }
 


Index: clang/test/Driver/fp-model.c
===
--- clang/test/Driver/fp-model.c
+++ clang/test/Driver/fp-model.c
@@ -66,6 +66,17 @@
 // RUN:   | FileCheck --check-prefix=WARN10 %s
 // WARN10: warning: overriding '-ffp-model=strict' option with '-fdenormal-fp-math=preserve-sign,preserve-sign' [-Woverriding-t-option]
 
+// RUN: %clang -### -ffp-model=fast -ffp-model=strict -c %s 2>&1 | FileCheck \
+// RUN:   --check-prefix=WARN11 %s
+// WARN11: warning: overriding '-ffp-model=fast' option with '-ffp-model=strict' [-Woverriding-t-option]
+// WARN11-NOT: warning: overriding '-ffp-model=strict' option with '-ffp-model=strict' [-Woverriding-t-option]
+
+// RUN: %clang -#

[PATCH] D137618: [Clang] Fix behavior of -ffp-model option when overriden

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf marked an inline comment as done.
qiucf added a comment.

Thanks!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137618/new/

https://reviews.llvm.org/D137618

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D137618: [Clang] Fix behavior of -ffp-model option when overriden

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added inline comments.



Comment at: clang/lib/Driver/ToolChains/Clang.cpp:3034
   RoundingFPMath = false;
+  FPExceptionBehavior = "";
   // If fast-math is set then set the fp-contract mode to fast.

zahiraam wrote:
>  FPExceptionBehavior should be set here and in case options::OPT_ffp_model_EQ:
Here's the case when `FPExceptionBehavior` was set and `-ffp-model=fast` or 
`-Ofast` or -ffast-math` takes effect. Exception behavior needs to be reset.

`OptID` was changed so `OPT_ffp_model_EQ` will not be matched in the 
switch-case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137618/new/

https://reviews.llvm.org/D137618

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D137618: [Clang] Fix behavior of -ffp-model option when overriden

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf updated this revision to Diff 475981.
qiucf marked an inline comment as done.
qiucf added a comment.

Update test case


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137618/new/

https://reviews.llvm.org/D137618

Files:
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/CodeGen/ffp-model.c
  clang/test/Driver/fp-model.c


Index: clang/test/Driver/fp-model.c
===
--- clang/test/Driver/fp-model.c
+++ clang/test/Driver/fp-model.c
@@ -66,6 +66,15 @@
 // RUN:   | FileCheck --check-prefix=WARN10 %s
 // WARN10: warning: overriding '-ffp-model=strict' option with 
'-fdenormal-fp-math=preserve-sign,preserve-sign' [-Woverriding-t-option]
 
+// RUN: %clang -### -ffp-model=fast -ffp-model=strict -c %s 2>&1 | FileCheck \
+// RUN:   --check-prefix=WARN11 %s
+// WARN11: warning: overriding '-ffp-model=fast' option with 
'-ffp-model=strict' [-Woverriding-t-option]
+// WARN11-NOT: warning: overriding '-ffp-model=strict' option with 
'-ffp-model=strict' [-Woverriding-t-option]
+
+// RUN: %clang -### -ffast-math -ffp-model=strict -c %s 2>&1 | FileCheck \
+// RUN:   --check-prefix=WARN12 %s
+// WARN12-NOT: warning: overriding '-ffp-model=strict' option with 
'-ffp-model=strict' [-Woverriding-t-option]
+
 // RUN: %clang -### -c %s 2>&1 \
 // RUN:   | FileCheck --check-prefix=CHECK-NOROUND %s
 // CHECK-NOROUND: "-cc1"
@@ -107,6 +116,13 @@
 // CHECK-FPM-STRICT: "-frounding-math"
 // CHECK-FPM-STRICT: "-ffp-exception-behavior=strict"
 
+// RUN: %clang -### -nostdinc -ffp-model=strict -ffp-model=fast -c %s 2>&1 \
+// RUN:   | FileCheck --check-prefix=CHECK-NO-EXCEPT %s
+// RUN: %clang -### -nostdinc -ffp-model=strict -ffast-math -c %s 2>&1 \
+// RUN:   | FileCheck --check-prefix=CHECK-NO-EXCEPT %s
+// RUN: %clang -### -nostdinc -ffp-model=strict -Ofast -c %s 2>&1 \
+// RUN:   | FileCheck --check-prefix=CHECK-NO-EXCEPT %s
+// CHECK-NO-EXCEPT-NOT: "-ffp-exception-behavior=strict"
 
 // RUN: %clang -### -nostdinc -ffp-exception-behavior=strict -c %s 2>&1 \
 // RUN:   | FileCheck --check-prefix=CHECK-FEB-STRICT %s
Index: clang/test/CodeGen/ffp-model.c
===
--- clang/test/CodeGen/ffp-model.c
+++ clang/test/CodeGen/ffp-model.c
@@ -36,9 +36,9 @@
 
   // CHECK-STRICT-FAST: load float, ptr
   // CHECK-STRICT-FAST: load float, ptr
-  // CHECK-STRICT-FAST: call fast float 
@llvm.experimental.constrained.fmul.f32(float {{.*}}, float {{.*}}, {{.*}})
+  // CHECK-STRICT-FAST: fmul fast float {{.*}}, {{.*}}
   // CHECK-STRICT-FAST: load float, ptr
-  // CHECK-STRICT-FAST: call fast float 
@llvm.experimental.constrained.fadd.f32(float {{.*}}, float {{.*}}, {{.*}}
+  // CHECK-STRICT-FAST: fadd fast float {{.*}}, {{.*}}
 
   // CHECK-FAST1: load float, ptr
   // CHECK-FAST1: load float, ptr
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -3041,6 +3041,7 @@
   SignedZeros = false;
   TrappingMath = false;
   RoundingFPMath = false;
+  FPExceptionBehavior = "";
   // If fast-math is set then set the fp-contract mode to fast.
   FPContract = "fast";
   SeenUnsafeMathModeOption = true;
@@ -3081,10 +3082,12 @@
   else {
 StrictFPModel = false;
 FPModel = "";
-D.Diag(clang::diag::warn_drv_overriding_flag_option)
-<< "-ffp-model=strict" <<
-((A->getNumValues() == 0) ?  A->getSpelling()
-: Args.MakeArgString(A->getSpelling() + A->getValue()));
+auto RHS = (A->getNumValues() == 0)
+   ? A->getSpelling()
+   : Args.MakeArgString(A->getSpelling() + A->getValue());
+if (RHS != "-ffp-model=strict")
+  D.Diag(clang::diag::warn_drv_overriding_flag_option)
+  << "-ffp-model=strict" << RHS;
   }
 }
 


Index: clang/test/Driver/fp-model.c
===
--- clang/test/Driver/fp-model.c
+++ clang/test/Driver/fp-model.c
@@ -66,6 +66,15 @@
 // RUN:   | FileCheck --check-prefix=WARN10 %s
 // WARN10: warning: overriding '-ffp-model=strict' option with '-fdenormal-fp-math=preserve-sign,preserve-sign' [-Woverriding-t-option]
 
+// RUN: %clang -### -ffp-model=fast -ffp-model=strict -c %s 2>&1 | FileCheck \
+// RUN:   --check-prefix=WARN11 %s
+// WARN11: warning: overriding '-ffp-model=fast' option with '-ffp-model=strict' [-Woverriding-t-option]
+// WARN11-NOT: warning: overriding '-ffp-model=strict' option with '-ffp-model=strict' [-Woverriding-t-option]
+
+// RUN: %clang -### -ffast-math -ffp-model=strict -c %s 2>&1 | FileCheck \
+// RUN:   --check-prefix=WARN12 %s
+// WARN12-NOT: warning: overriding '-ffp-model=strict' option with '-ffp-model=strict' [-Woverriding-t-option]
+
 // RUN: %clang -### -c %s 2>&1 \
 // RUN:  

[PATCH] D138105: [PowerPC] Support test data class intrinsic of 128-bit float

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf created this revision.
qiucf added reviewers: nemanjai, shchenz, PowerPC, quinnp, stefanp.
Herald added subscribers: kbarton, hiraditya.
Herald added a project: All.
qiucf requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

We've exploited test data class instructions for `f32` `f64` v2f64` and 
`v4f32`. This patch unifies the LLVM intrinsic into the same 
`ppc_test_data_class` and add support for 128-bit precision float values using 
`xststdcqp`.

Vector versions of the intrinsic can't be unified because they return vector 
int instead of int.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D138105

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-p9-f128.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-test.ll
@@ -77,11 +77,11 @@
 ; CHECK-NEXT:iseleq 3, 4, 3
 ; CHECK-NEXT:blr
 entry:
-  %test_data_class = tail call i32 @llvm.ppc.test.data.class.d(double %d, i32 0)
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f64(double %d, i32 0)
   ret i32 %test_data_class
 }
 
-declare i32 @llvm.ppc.test.data.class.d(double, i32 immarg)
+declare i32 @llvm.ppc.test.data.class.f64(double, i32 immarg)
 
 define i32 @test_builtin_ppc_test_data_class_f(float %f) {
 ; CHECK-LABEL: test_builtin_ppc_test_data_class_f:
@@ -92,8 +92,8 @@
 ; CHECK-NEXT:iseleq 3, 4, 3
 ; CHECK-NEXT:blr
 entry:
-  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f(float %f, i32 127)
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f32(float %f, i32 127)
   ret i32 %test_data_class
 }
 
-declare i32 @llvm.ppc.test.data.class.f(float, i32 immarg)
+declare i32 @llvm.ppc.test.data.class.f32(float, i32 immarg)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
@@ -136,3 +136,16 @@
 ; Function Attrs: nounwind readnone
 declare i64 @llvm.ppc.scalar.extract.expq(fp128)
 
+define i32 @test_data_class_f128(fp128 %d) {
+entry:
+  %test_data_class = tail call i32 @llvm.ppc.test.data.class.f128(fp128 %d, i32 0)
+  ret i32 %test_data_class
+; CHECK-LABEL: test_data_class_f128:
+; CHECK: xststdcqp cr0, v2, 0
+; CHECK-NEXT: li r3, 0
+; CHECK-NEXT: li r4, 1
+; CHECK-NEXT: iseleq r3, r4, r3
+; CHECK-NEXT: blr
+}
+
+declare i32 @llvm.ppc.test.data.class.f128(fp128, i32 immarg)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10548,11 +10548,11 @@
  DAG.getTargetConstant(Pred, dl, MVT::i32)}),
 0);
   }
-  case Intrinsic::ppc_test_data_class_d:
-  case Intrinsic::ppc_test_data_class_f: {
-unsigned CmprOpc = PPC::XSTSTDCDP;
-if (IntrinsicID == Intrinsic::ppc_test_data_class_f)
-  CmprOpc = PPC::XSTSTDCSP;
+  case Intrinsic::ppc_test_data_class: {
+EVT OpVT = Op.getOperand(1).getValueType();
+unsigned CmprOpc = OpVT == MVT::f128 ? PPC::XSTSTDCQP
+ : (OpVT == MVT::f64 ? PPC::XSTSTDCDP
+ : PPC::XSTSTDCSP);
 return SDValue(
 DAG.getMachineNode(
 PPC::SELECT_CC_I4, dl, MVT::i32,
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1803,12 +1803,9 @@
Intrinsic<[llvm_i32_ty], 
  [llvm_double_ty, llvm_double_ty], 
  [IntrNoMem]>;
-  def int_ppc_test_data_class_d : Intrinsic<[llvm_i32_ty],
-[llvm_double_ty, llvm_i32_ty],
-[IntrNoMem, ImmArg>]>;
-  def int_ppc_test_data_class_f : Intrinsic<[llvm_i32_ty],
-[llvm_float_ty, llvm_i32_ty],
-[IntrNoMem, ImmArg>]>;
+  def int_ppc_test_data_class : Intrinsic<[llvm_i32_ty],
+  [llvm_anyfloat_ty, llvm_i32_ty],
+  [IntrNoMem, ImmArg>]>;
   def int_ppc_f

[PATCH] D137618: [Clang] Fix behavior of -ffp-model option when overriden

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf updated this revision to Diff 474142.
qiucf marked an inline comment as done.
qiucf added a reviewer: michele.scandale.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137618/new/

https://reviews.llvm.org/D137618

Files:
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/CodeGen/ffp-model.c
  clang/test/Driver/fp-model.c


Index: clang/test/Driver/fp-model.c
===
--- clang/test/Driver/fp-model.c
+++ clang/test/Driver/fp-model.c
@@ -66,6 +66,11 @@
 // RUN:   | FileCheck --check-prefix=WARN10 %s
 // WARN10: warning: overriding '-ffp-model=strict' option with 
'-fdenormal-fp-math=preserve-sign,preserve-sign' [-Woverriding-t-option]
 
+// RUN: %clang -### -ffp-model=fast -ffp-model=strict -c %s 2>&1 | FileCheck \
+// RUN:   --check-prefix=WARN11 %s
+// WARN11: warning: overriding '-ffp-model=fast' option with 
'-ffp-model=strict' [-Woverriding-t-option]
+// WARN11-NOT: warning: overriding '-ffp-model=strict' option with 
'-ffp-model=strict' [-Woverriding-t-option]
+
 // RUN: %clang -### -c %s 2>&1 \
 // RUN:   | FileCheck --check-prefix=CHECK-NOROUND %s
 // CHECK-NOROUND: "-cc1"
@@ -107,6 +112,13 @@
 // CHECK-FPM-STRICT: "-frounding-math"
 // CHECK-FPM-STRICT: "-ffp-exception-behavior=strict"
 
+// RUN: %clang -### -nostdinc -ffp-model=strict -ffp-model=fast -c %s 2>&1 \
+// RUN:   | FileCheck --check-prefix=CHECK-NO-EXCEPT %s
+// RUN: %clang -### -nostdinc -ffp-model=strict -ffast-math -c %s 2>&1 \
+// RUN:   | FileCheck --check-prefix=CHECK-NO-EXCEPT %s
+// RUN: %clang -### -nostdinc -ffp-model=strict -Ofast -c %s 2>&1 \
+// RUN:   | FileCheck --check-prefix=CHECK-NO-EXCEPT %s
+// CHECK-NO-EXCEPT-NOT: "-ffp-exception-behavior=strict"
 
 // RUN: %clang -### -nostdinc -ffp-exception-behavior=strict -c %s 2>&1 \
 // RUN:   | FileCheck --check-prefix=CHECK-FEB-STRICT %s
Index: clang/test/CodeGen/ffp-model.c
===
--- clang/test/CodeGen/ffp-model.c
+++ clang/test/CodeGen/ffp-model.c
@@ -36,9 +36,9 @@
 
   // CHECK-STRICT-FAST: load float, ptr
   // CHECK-STRICT-FAST: load float, ptr
-  // CHECK-STRICT-FAST: call fast float 
@llvm.experimental.constrained.fmul.f32(float {{.*}}, float {{.*}}, {{.*}})
+  // CHECK-STRICT-FAST: fmul fast float {{.*}}, {{.*}}
   // CHECK-STRICT-FAST: load float, ptr
-  // CHECK-STRICT-FAST: call fast float 
@llvm.experimental.constrained.fadd.f32(float {{.*}}, float {{.*}}, {{.*}}
+  // CHECK-STRICT-FAST: fadd fast float {{.*}}, {{.*}}
 
   // CHECK-FAST1: load float, ptr
   // CHECK-FAST1: load float, ptr
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -3031,6 +3031,7 @@
   SignedZeros = false;
   TrappingMath = false;
   RoundingFPMath = false;
+  FPExceptionBehavior = "";
   // If fast-math is set then set the fp-contract mode to fast.
   FPContract = "fast";
   SeenFfastMathOption = true;
@@ -3071,10 +3072,12 @@
   else {
 StrictFPModel = false;
 FPModel = "";
-D.Diag(clang::diag::warn_drv_overriding_flag_option)
-<< "-ffp-model=strict" <<
-((A->getNumValues() == 0) ?  A->getSpelling()
-: Args.MakeArgString(A->getSpelling() + A->getValue()));
+auto RHS = (A->getNumValues() == 0)
+   ? A->getSpelling()
+   : Args.MakeArgString(A->getSpelling() + A->getValue());
+if (RHS != "-ffp-model=strict")
+  D.Diag(clang::diag::warn_drv_overriding_flag_option)
+  << "-ffp-model=strict" << RHS;
   }
 }
 


Index: clang/test/Driver/fp-model.c
===
--- clang/test/Driver/fp-model.c
+++ clang/test/Driver/fp-model.c
@@ -66,6 +66,11 @@
 // RUN:   | FileCheck --check-prefix=WARN10 %s
 // WARN10: warning: overriding '-ffp-model=strict' option with '-fdenormal-fp-math=preserve-sign,preserve-sign' [-Woverriding-t-option]
 
+// RUN: %clang -### -ffp-model=fast -ffp-model=strict -c %s 2>&1 | FileCheck \
+// RUN:   --check-prefix=WARN11 %s
+// WARN11: warning: overriding '-ffp-model=fast' option with '-ffp-model=strict' [-Woverriding-t-option]
+// WARN11-NOT: warning: overriding '-ffp-model=strict' option with '-ffp-model=strict' [-Woverriding-t-option]
+
 // RUN: %clang -### -c %s 2>&1 \
 // RUN:   | FileCheck --check-prefix=CHECK-NOROUND %s
 // CHECK-NOROUND: "-cc1"
@@ -107,6 +112,13 @@
 // CHECK-FPM-STRICT: "-frounding-math"
 // CHECK-FPM-STRICT: "-ffp-exception-behavior=strict"
 
+// RUN: %clang -### -nostdinc -ffp-model=strict -ffp-model=fast -c %s 2>&1 \
+// RUN:   | FileCheck --check-prefix=CHECK-NO-EXCEPT %s
+// RUN: %clang -### -nostdinc -ffp-model=strict -ffast-math -c %s 2>&1 \
+// RUN:   | FileCheck --check-prefix=CHECK-NO-EXCEPT %s
+//

[PATCH] D137536: [NFC] Replace use of PPC64 macro into powerpc64 in intrinsic headers

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf abandoned this revision.
qiucf added a comment.

I think rG7aa90b21b453d1ca52fdfccfd7e01e61d9e5b1f1 
 has 
already done that.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137536/new/

https://reviews.llvm.org/D137536

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D137618: [Clang] Fix behavior of -ffp-model option when overriden

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf created this revision.
qiucf added reviewers: aaron.ballman, mibintc, andrew.w.kaylor, masoud.ataei, 
zahiraam.
Herald added a project: All.
qiucf requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

`-ffp-model=strict -ffp-model=fast` will still enable strict exception handling 
behavior, therefore clang still emits constrained FP operations in IR.

`-ffp-model=fast -ffp-model=strict` emits two warnings: one for `strict` 
overriding `fast`, the other for `strict` overriding `strict`, which is 
confusing.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137618

Files:
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/Driver/fp-model.c


Index: clang/test/Driver/fp-model.c
===
--- clang/test/Driver/fp-model.c
+++ clang/test/Driver/fp-model.c
@@ -66,6 +66,11 @@
 // RUN:   | FileCheck --check-prefix=WARN10 %s
 // WARN10: warning: overriding '-ffp-model=strict' option with 
'-fdenormal-fp-math=preserve-sign,preserve-sign' [-Woverriding-t-option]
 
+// RUN: %clang -### -ffp-model=fast -ffp-model=strict -c %s 2>&1 | FileCheck \
+// RUN:   --check-prefix=WARN11 %s
+// WARN11: warning: overriding '-ffp-model=fast' option with 
'-ffp-model=strict' [-Woverriding-t-option]
+// WARN11-NOT: warning: overriding '-ffp-model=strict' option with 
'-ffp-model=strict' [-Woverriding-t-option]
+
 // RUN: %clang -### -c %s 2>&1 \
 // RUN:   | FileCheck --check-prefix=CHECK-NOROUND %s
 // CHECK-NOROUND: "-cc1"
@@ -107,6 +112,9 @@
 // CHECK-FPM-STRICT: "-frounding-math"
 // CHECK-FPM-STRICT: "-ffp-exception-behavior=strict"
 
+// RUN: %clang -### -nostdinc -ffp-model=strict -ffp-model=fast -c %s 2>&1 \
+// RUN:   | FileCheck --check-prefix=CHECK-NO-EXCEPT %s
+// CHECK-NO-EXCEPT-NOT: "-ffp-exception-behavior=strict"
 
 // RUN: %clang -### -nostdinc -ffp-exception-behavior=strict -c %s 2>&1 \
 // RUN:   | FileCheck --check-prefix=CHECK-FEB-STRICT %s
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -2841,6 +2841,7 @@
 optID = options::OPT_ffast_math;
 FPModel = Val;
 FPContract = "fast";
+FPExceptionBehavior = "";
   } else if (Val.equals("precise")) {
 optID = options::OPT_ffp_contract;
 FPModel = Val;
@@ -3071,10 +3072,12 @@
   else {
 StrictFPModel = false;
 FPModel = "";
-D.Diag(clang::diag::warn_drv_overriding_flag_option)
-<< "-ffp-model=strict" <<
-((A->getNumValues() == 0) ?  A->getSpelling()
-: Args.MakeArgString(A->getSpelling() + A->getValue()));
+auto RHS = (A->getNumValues() == 0)
+   ? A->getSpelling()
+   : Args.MakeArgString(A->getSpelling() + A->getValue());
+if (RHS != "-ffp-model=strict")
+  D.Diag(clang::diag::warn_drv_overriding_flag_option)
+  << "-ffp-model=strict" << RHS;
   }
 }
 


Index: clang/test/Driver/fp-model.c
===
--- clang/test/Driver/fp-model.c
+++ clang/test/Driver/fp-model.c
@@ -66,6 +66,11 @@
 // RUN:   | FileCheck --check-prefix=WARN10 %s
 // WARN10: warning: overriding '-ffp-model=strict' option with '-fdenormal-fp-math=preserve-sign,preserve-sign' [-Woverriding-t-option]
 
+// RUN: %clang -### -ffp-model=fast -ffp-model=strict -c %s 2>&1 | FileCheck \
+// RUN:   --check-prefix=WARN11 %s
+// WARN11: warning: overriding '-ffp-model=fast' option with '-ffp-model=strict' [-Woverriding-t-option]
+// WARN11-NOT: warning: overriding '-ffp-model=strict' option with '-ffp-model=strict' [-Woverriding-t-option]
+
 // RUN: %clang -### -c %s 2>&1 \
 // RUN:   | FileCheck --check-prefix=CHECK-NOROUND %s
 // CHECK-NOROUND: "-cc1"
@@ -107,6 +112,9 @@
 // CHECK-FPM-STRICT: "-frounding-math"
 // CHECK-FPM-STRICT: "-ffp-exception-behavior=strict"
 
+// RUN: %clang -### -nostdinc -ffp-model=strict -ffp-model=fast -c %s 2>&1 \
+// RUN:   | FileCheck --check-prefix=CHECK-NO-EXCEPT %s
+// CHECK-NO-EXCEPT-NOT: "-ffp-exception-behavior=strict"
 
 // RUN: %clang -### -nostdinc -ffp-exception-behavior=strict -c %s 2>&1 \
 // RUN:   | FileCheck --check-prefix=CHECK-FEB-STRICT %s
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -2841,6 +2841,7 @@
 optID = options::OPT_ffast_math;
 FPModel = Val;
 FPContract = "fast";
+FPExceptionBehavior = "";
   } else if (Val.equals("precise")) {
 optID = options::OPT_ffp_contract;
 FPModel = Val;
@@ -3071,10 +3072,12 @@
   else {
 StrictFPModel = false;
 FPModel = "";
-D.Diag(clang::diag::warn_drv_ove

[PATCH] D137536: [NFC] Replace use of PPC64 macro into powerpc64 in intrinsic headers

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf created this revision.
qiucf added reviewers: nemanjai, lkail, shchenz, PowerPC.
Herald added a subscriber: kbarton.
Herald added a project: All.
qiucf requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137536

Files:
  clang/lib/Headers/ppc_wrappers/bmi2intrin.h
  clang/lib/Headers/ppc_wrappers/bmiintrin.h
  clang/lib/Headers/ppc_wrappers/emmintrin.h
  clang/lib/Headers/ppc_wrappers/mm_malloc.h
  clang/lib/Headers/ppc_wrappers/mmintrin.h
  clang/lib/Headers/ppc_wrappers/pmmintrin.h
  clang/lib/Headers/ppc_wrappers/smmintrin.h
  clang/lib/Headers/ppc_wrappers/tmmintrin.h
  clang/lib/Headers/ppc_wrappers/xmmintrin.h

Index: clang/lib/Headers/ppc_wrappers/xmmintrin.h
===
--- clang/lib/Headers/ppc_wrappers/xmmintrin.h
+++ clang/lib/Headers/ppc_wrappers/xmmintrin.h
@@ -35,7 +35,7 @@
 #ifndef XMMINTRIN_H_
 #define XMMINTRIN_H_
 
-#if defined(__ppc64__) &&  \
+#if defined(__powerpc64__) &&  \
 (defined(__linux__) || defined(__FreeBSD__) || defined(_AIX))
 
 /* Define four value permute mask */
@@ -1821,7 +1821,7 @@
 
 #else
 #include_next 
-#endif /* defined(__ppc64__) &&
+#endif /* defined(__powerpc64__) &&
 *   (defined(__linux__) || defined(__FreeBSD__) || defined(_AIX)) */
 
 #endif /* XMMINTRIN_H_ */
Index: clang/lib/Headers/ppc_wrappers/tmmintrin.h
===
--- clang/lib/Headers/ppc_wrappers/tmmintrin.h
+++ clang/lib/Headers/ppc_wrappers/tmmintrin.h
@@ -25,7 +25,7 @@
 #ifndef TMMINTRIN_H_
 #define TMMINTRIN_H_
 
-#if defined(__ppc64__) &&  \
+#if defined(__powerpc64__) &&  \
 (defined(__linux__) || defined(__FreeBSD__) || defined(_AIX))
 
 #include 
@@ -447,7 +447,7 @@
 
 #else
 #include_next 
-#endif /* defined(__ppc64__) &&
+#endif /* defined(__powerpc64__) &&
 *   (defined(__linux__) || defined(__FreeBSD__) || defined(_AIX)) */
 
 #endif /* TMMINTRIN_H_ */
Index: clang/lib/Headers/ppc_wrappers/smmintrin.h
===
--- clang/lib/Headers/ppc_wrappers/smmintrin.h
+++ clang/lib/Headers/ppc_wrappers/smmintrin.h
@@ -29,7 +29,7 @@
 #ifndef SMMINTRIN_H_
 #define SMMINTRIN_H_
 
-#if defined(__ppc64__) &&  \
+#if defined(__powerpc64__) &&  \
 (defined(__linux__) || defined(__FreeBSD__) || defined(_AIX))
 
 #include 
@@ -657,7 +657,7 @@
 
 #else
 #include_next 
-#endif /* defined(__ppc64__) &&
+#endif /* defined(__powerpc64__) &&
 *   (defined(__linux__) || defined(__FreeBSD__) || defined(_AIX)) */
 
 #endif /* SMMINTRIN_H_ */
Index: clang/lib/Headers/ppc_wrappers/pmmintrin.h
===
--- clang/lib/Headers/ppc_wrappers/pmmintrin.h
+++ clang/lib/Headers/ppc_wrappers/pmmintrin.h
@@ -39,7 +39,7 @@
 #ifndef PMMINTRIN_H_
 #define PMMINTRIN_H_
 
-#if defined(__ppc64__) &&  \
+#if defined(__powerpc64__) &&  \
 (defined(__linux__) || defined(__FreeBSD__) || defined(_AIX))
 
 /* We need definitions from the SSE2 and SSE header files*/
@@ -139,7 +139,7 @@
 
 #else
 #include_next 
-#endif /* defined(__ppc64__) &&
+#endif /* defined(__powerpc64__) &&
 *   (defined(__linux__) || defined(__FreeBSD__) || defined(_AIX)) */
 
 #endif /* PMMINTRIN_H_ */
Index: clang/lib/Headers/ppc_wrappers/mmintrin.h
===
--- clang/lib/Headers/ppc_wrappers/mmintrin.h
+++ clang/lib/Headers/ppc_wrappers/mmintrin.h
@@ -35,7 +35,7 @@
 #ifndef _MMINTRIN_H_INCLUDED
 #define _MMINTRIN_H_INCLUDED
 
-#if defined(__ppc64__) &&  \
+#if defined(__powerpc64__) &&  \
 (defined(__linux__) || defined(__FreeBSD__) || defined(_AIX))
 
 #include 
@@ -1447,7 +1447,7 @@
 
 #else
 #include_next 
-#endif /* defined(__ppc64__) &&
+#endif /* defined(__powerpc64__) &&
 *   (defined(__linux__) || defined(__FreeBSD__) || defined(_AIX)) */
 
 #endif /* _MMINTRIN_H_INCLUDED */
Index: clang/lib/Headers/ppc_wrappers/mm_malloc.h
===
--- clang/lib/Headers/ppc_wrappers/mm_malloc.h
+++ clang/lib/Headers/ppc_wrappers/mm_malloc.h
@@ -10,7 +10,7 @@
 #ifndef _MM_MALLOC_H_INCLUDED
 #define _MM_MALLOC_H_INCLUDED
 
-#if defined(__ppc64__) &&  \
+#if defined(__powerpc64__) &&  

[PATCH] D129461: [PowerPC] Support x86 compatible intrinsics on AIX

[Qiu Chaofan via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG708084ec379e: [PowerPC] Support x86 compatible intrinsics on 
AIX (authored by qiucf).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129461/new/

https://reviews.llvm.org/D129461

Files:
  clang/lib/Driver/ToolChains/AIX.cpp
  clang/lib/Headers/ppc_wrappers/emmintrin.h
  clang/lib/Headers/ppc_wrappers/mm_malloc.h
  clang/lib/Headers/ppc_wrappers/mmintrin.h
  clang/lib/Headers/ppc_wrappers/pmmintrin.h
  clang/lib/Headers/ppc_wrappers/smmintrin.h
  clang/lib/Headers/ppc_wrappers/tmmintrin.h
  clang/lib/Headers/ppc_wrappers/xmmintrin.h
  clang/test/CodeGen/PowerPC/ppc-emmintrin.c
  clang/test/CodeGen/PowerPC/ppc-mm-malloc.c
  clang/test/CodeGen/PowerPC/ppc-mmintrin.c
  clang/test/CodeGen/PowerPC/ppc-pmmintrin.c
  clang/test/CodeGen/PowerPC/ppc-smmintrin.c
  clang/test/CodeGen/PowerPC/ppc-tmmintrin.c
  clang/test/CodeGen/PowerPC/ppc-x86gprintrin.c
  clang/test/CodeGen/PowerPC/ppc-xmmintrin.c

Index: clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
===
--- clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
+++ clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
@@ -10,7 +10,7 @@
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns
 
 // RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
-// RUN:   -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-P10
+// RUN:   -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-P10-LE
 
 // RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64-unknown-freebsd13.0 -mcpu=pwr8 -ffreestanding -nostdlibinc -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE
@@ -21,6 +21,13 @@
 // RUN: %clang -Xclang -no-opaque-pointers -x c++ -fsyntax-only -target powerpc64le-unknown-freebsd13.0 -mcpu=pwr8 -ffreestanding -nostdlibinc -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns
 
+// RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64-ibm-aix -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: %clang -Xclang -no-opaque-pointers -x c++ -fsyntax-only -target powerpc64-ibm-aix -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns
+// RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64-ibm-aix -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-P10-BE
+
 #include 
 
 __m128 res, m1, m2;
@@ -388,7 +395,8 @@
 // CHECK-LABEL: define available_externally signext i32 @_mm_cvtss_si32
 // CHECK-LE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xxsldwi ${0:x},${0:x},${0:x},3;\0Axscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
 // CHECK-BE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
-// CHECK-P10: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xxsldwi ${0:x},${0:x},${0:x},3;\0Axscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
+// CHECK-P10-LE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xxsldwi ${0:x},${0:x},${0:x},3;\0Axscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
+// CHECK-P10-BE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
 // CHECK: extractvalue { <4 x float>, i32, double } %[[VEC]], 0
 // CHECK: extractvalue { <4 x float>, i32, double } %[[VEC]], 1
 // CHECK: extractvalue { <4 x float>, i32, double } %[[VEC]], 2
@@ -688,7 +696,8 @@
 // CHECK-BE: call <2 x i64> @vec_vbpermq(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef %{{[0-9a-zA-Z_.]+}}, <16 x i8> noundef bitcast (<4 x i32>  to <16 x i8>))
 // CHECK-BE: %[[EXT:[0-9a-zA-Z_.]+]] = extractelement <2 x i64> %{{[0-9a-zA-Z_.]+}}, i32 0
 // CHECK-BE: trunc i64 %[[EXT]] to i32
-// CHECK-P10: call zeroext i32 @vec_extractm(unsigned int vector[4])(<4 x i32> noundef %{{[0-9a-zA-Z_.]+}})
+// CHECK-P10-LE: call zeroext i32 @vec_extractm(unsigned int vector[4])(<4 x i32> noundef %{{[0-9a-

[PATCH] D129461: [PowerPC] Support x86 compatible intrinsics on AIX

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf updated this revision to Diff 446335.
qiucf marked an inline comment as done.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129461/new/

https://reviews.llvm.org/D129461

Files:
  clang/lib/Driver/ToolChains/AIX.cpp
  clang/lib/Headers/ppc_wrappers/emmintrin.h
  clang/lib/Headers/ppc_wrappers/mm_malloc.h
  clang/lib/Headers/ppc_wrappers/mmintrin.h
  clang/lib/Headers/ppc_wrappers/pmmintrin.h
  clang/lib/Headers/ppc_wrappers/smmintrin.h
  clang/lib/Headers/ppc_wrappers/tmmintrin.h
  clang/lib/Headers/ppc_wrappers/xmmintrin.h
  clang/test/CodeGen/PowerPC/ppc-emmintrin.c
  clang/test/CodeGen/PowerPC/ppc-mm-malloc.c
  clang/test/CodeGen/PowerPC/ppc-mmintrin.c
  clang/test/CodeGen/PowerPC/ppc-pmmintrin.c
  clang/test/CodeGen/PowerPC/ppc-smmintrin.c
  clang/test/CodeGen/PowerPC/ppc-tmmintrin.c
  clang/test/CodeGen/PowerPC/ppc-x86gprintrin.c
  clang/test/CodeGen/PowerPC/ppc-xmmintrin.c

Index: clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
===
--- clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
+++ clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
@@ -10,7 +10,7 @@
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns
 
 // RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
-// RUN:   -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-P10
+// RUN:   -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-P10-LE
 
 // RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64-unknown-freebsd13.0 -mcpu=pwr8 -ffreestanding -nostdlibinc -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE
@@ -21,6 +21,13 @@
 // RUN: %clang -Xclang -no-opaque-pointers -x c++ -fsyntax-only -target powerpc64le-unknown-freebsd13.0 -mcpu=pwr8 -ffreestanding -nostdlibinc -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns
 
+// RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64-ibm-aix -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: %clang -Xclang -no-opaque-pointers -x c++ -fsyntax-only -target powerpc64-ibm-aix -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns
+// RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64-ibm-aix -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-P10-BE
+
 #include 
 
 __m128 res, m1, m2;
@@ -388,7 +395,8 @@
 // CHECK-LABEL: define available_externally signext i32 @_mm_cvtss_si32
 // CHECK-LE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xxsldwi ${0:x},${0:x},${0:x},3;\0Axscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
 // CHECK-BE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
-// CHECK-P10: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xxsldwi ${0:x},${0:x},${0:x},3;\0Axscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
+// CHECK-P10-LE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xxsldwi ${0:x},${0:x},${0:x},3;\0Axscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
+// CHECK-P10-BE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
 // CHECK: extractvalue { <4 x float>, i32, double } %[[VEC]], 0
 // CHECK: extractvalue { <4 x float>, i32, double } %[[VEC]], 1
 // CHECK: extractvalue { <4 x float>, i32, double } %[[VEC]], 2
@@ -688,7 +696,8 @@
 // CHECK-BE: call <2 x i64> @vec_vbpermq(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef %{{[0-9a-zA-Z_.]+}}, <16 x i8> noundef bitcast (<4 x i32>  to <16 x i8>))
 // CHECK-BE: %[[EXT:[0-9a-zA-Z_.]+]] = extractelement <2 x i64> %{{[0-9a-zA-Z_.]+}}, i32 0
 // CHECK-BE: trunc i64 %[[EXT]] to i32
-// CHECK-P10: call zeroext i32 @vec_extractm(unsigned int vector[4])(<4 x i32> noundef %{{[0-9a-zA-Z_.]+}})
+// CHECK-P10-LE: call zeroext i32 @vec_extractm(unsigned int vector[4])(<4 x i32> noundef %{{[0-9a-zA-Z_.]+}})
+// CHECK-P10-BE: call zeroext i32 @vec_extractm(unsigned int vector[4])(<4 x i32> noundef %{{[0-9a-zA-Z_.]+}})
 
 void __attribute__((noinl

[PATCH] D129461: [PowerPC] Support x86 compatible intrinsics on AIX

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added inline comments.



Comment at: clang/lib/Driver/ToolChains/AIX.cpp:232
+path::remove_filename(P);
+addSystemInclude(DriverArgs, CC1Args, P);
   }

shchenz wrote:
> Can we use `path::parent_path(P)` directly in `addSystemInclude()`? 
> `remove_filename()` sounds like `ppc_wrappers` is a file.
It just wraps `parent_path`, and `parent_path` only accepts (and returns) 
`StringRef`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129461/new/

https://reviews.llvm.org/D129461

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D129461: [PowerPC] Support x86 compatible intrinsics on AIX

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added inline comments.



Comment at: clang/test/CodeGen/PowerPC/ppc-emmintrin.c:631
 // CHECK: %[[ADDR:[0-9a-zA-Z_.]+]] = load double*, double** 
%{{[0-9a-zA-Z_.]+}}, align 8
-// CHECK: %[[VAL:[0-9a-zA-Z_.]+]] = load double, double* %[[ADDR]], align 8
+// CHECK: %[[VAL:[0-9a-zA-Z_.]+]] = load double, double* %[[ADDR]]
 // CHECK: call <2 x double> @vec_splats(double)(double noundef %[[VAL]])

shchenz wrote:
> Maybe worth investigating here why loading a double on AIX64 is not aligned 
> to 8. This should be separated from this patch
It's from D79719


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129461/new/

https://reviews.llvm.org/D129461

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D129461: [PowerPC] Support x86 compatible intrinsics on AIX

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf updated this revision to Diff 444182.
qiucf added a comment.
Herald added a subscriber: ormris.

Merge conditions.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129461/new/

https://reviews.llvm.org/D129461

Files:
  clang/lib/Driver/ToolChains/AIX.cpp
  clang/lib/Headers/ppc_wrappers/emmintrin.h
  clang/lib/Headers/ppc_wrappers/mm_malloc.h
  clang/lib/Headers/ppc_wrappers/mmintrin.h
  clang/lib/Headers/ppc_wrappers/pmmintrin.h
  clang/lib/Headers/ppc_wrappers/smmintrin.h
  clang/lib/Headers/ppc_wrappers/tmmintrin.h
  clang/lib/Headers/ppc_wrappers/xmmintrin.h
  clang/test/CodeGen/PowerPC/ppc-emmintrin.c
  clang/test/CodeGen/PowerPC/ppc-mm-malloc.c
  clang/test/CodeGen/PowerPC/ppc-mmintrin.c
  clang/test/CodeGen/PowerPC/ppc-pmmintrin.c
  clang/test/CodeGen/PowerPC/ppc-smmintrin.c
  clang/test/CodeGen/PowerPC/ppc-tmmintrin.c
  clang/test/CodeGen/PowerPC/ppc-x86gprintrin.c
  clang/test/CodeGen/PowerPC/ppc-xmmintrin.c

Index: clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
===
--- clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
+++ clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
@@ -10,7 +10,7 @@
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns
 
 // RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
-// RUN:   -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-P10
+// RUN:   -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-P10-LE
 
 // RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64-unknown-freebsd13.0 -mcpu=pwr8 -ffreestanding -nostdlibinc -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE
@@ -21,6 +21,13 @@
 // RUN: %clang -Xclang -no-opaque-pointers -x c++ -fsyntax-only -target powerpc64le-unknown-freebsd13.0 -mcpu=pwr8 -ffreestanding -nostdlibinc -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns
 
+// RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64-ibm-aix -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: %clang -Xclang -no-opaque-pointers -x c++ -fsyntax-only -target powerpc64-ibm-aix -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns
+// RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64-ibm-aix -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-P10-BE
+
 #include 
 
 __m128 res, m1, m2;
@@ -388,7 +395,8 @@
 // CHECK-LABEL: define available_externally signext i32 @_mm_cvtss_si32
 // CHECK-LE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xxsldwi ${0:x},${0:x},${0:x},3;\0Axscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
 // CHECK-BE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
-// CHECK-P10: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xxsldwi ${0:x},${0:x},${0:x},3;\0Axscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
+// CHECK-P10-LE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xxsldwi ${0:x},${0:x},${0:x},3;\0Axscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
+// CHECK-P10-BE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
 // CHECK: extractvalue { <4 x float>, i32, double } %[[VEC]], 0
 // CHECK: extractvalue { <4 x float>, i32, double } %[[VEC]], 1
 // CHECK: extractvalue { <4 x float>, i32, double } %[[VEC]], 2
@@ -688,7 +696,8 @@
 // CHECK-BE: call <2 x i64> @vec_vbpermq(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef %{{[0-9a-zA-Z_.]+}}, <16 x i8> noundef bitcast (<4 x i32>  to <16 x i8>))
 // CHECK-BE: %[[EXT:[0-9a-zA-Z_.]+]] = extractelement <2 x i64> %{{[0-9a-zA-Z_.]+}}, i32 0
 // CHECK-BE: trunc i64 %[[EXT]] to i32
-// CHECK-P10: call zeroext i32 @vec_extractm(unsigned int vector[4])(<4 x i32> noundef %{{[0-9a-zA-Z_.]+}})
+// CHECK-P10-LE: call zeroext i32 @vec_extractm(unsigned int vector[4])(<4 x i32> noundef %{{[0-9a-zA-Z_.]+}})
+// CHECK-P10-BE: call zeroext i32 @vec_extractm(unsigned int vector[4])(<4 x i32> noundef %{{[0-9a-zA

[PATCH] D129461: [PowerPC] Support x86 compatible intrinsics on AIX

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf updated this revision to Diff 444175.
qiucf marked an inline comment as done.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129461/new/

https://reviews.llvm.org/D129461

Files:
  clang/lib/Driver/ToolChains/AIX.cpp
  clang/lib/Headers/ppc_wrappers/emmintrin.h
  clang/lib/Headers/ppc_wrappers/mm_malloc.h
  clang/lib/Headers/ppc_wrappers/mmintrin.h
  clang/lib/Headers/ppc_wrappers/pmmintrin.h
  clang/lib/Headers/ppc_wrappers/smmintrin.h
  clang/lib/Headers/ppc_wrappers/tmmintrin.h
  clang/lib/Headers/ppc_wrappers/xmmintrin.h
  clang/test/CodeGen/PowerPC/ppc-emmintrin.c
  clang/test/CodeGen/PowerPC/ppc-mm-malloc.c
  clang/test/CodeGen/PowerPC/ppc-mmintrin.c
  clang/test/CodeGen/PowerPC/ppc-pmmintrin.c
  clang/test/CodeGen/PowerPC/ppc-smmintrin.c
  clang/test/CodeGen/PowerPC/ppc-tmmintrin.c
  clang/test/CodeGen/PowerPC/ppc-x86gprintrin.c
  clang/test/CodeGen/PowerPC/ppc-xmmintrin.c

Index: clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
===
--- clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
+++ clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
@@ -10,7 +10,7 @@
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns
 
 // RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
-// RUN:   -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-P10
+// RUN:   -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-P10-LE
 
 // RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64-unknown-freebsd13.0 -mcpu=pwr8 -ffreestanding -nostdlibinc -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE
@@ -21,6 +21,13 @@
 // RUN: %clang -Xclang -no-opaque-pointers -x c++ -fsyntax-only -target powerpc64le-unknown-freebsd13.0 -mcpu=pwr8 -ffreestanding -nostdlibinc -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns
 
+// RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64-ibm-aix -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: %clang -Xclang -no-opaque-pointers -x c++ -fsyntax-only -target powerpc64-ibm-aix -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns
+// RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64-ibm-aix -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-P10-BE
+
 #include 
 
 __m128 res, m1, m2;
@@ -388,7 +395,8 @@
 // CHECK-LABEL: define available_externally signext i32 @_mm_cvtss_si32
 // CHECK-LE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xxsldwi ${0:x},${0:x},${0:x},3;\0Axscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
 // CHECK-BE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
-// CHECK-P10: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xxsldwi ${0:x},${0:x},${0:x},3;\0Axscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
+// CHECK-P10-LE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xxsldwi ${0:x},${0:x},${0:x},3;\0Axscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
+// CHECK-P10-BE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
 // CHECK: extractvalue { <4 x float>, i32, double } %[[VEC]], 0
 // CHECK: extractvalue { <4 x float>, i32, double } %[[VEC]], 1
 // CHECK: extractvalue { <4 x float>, i32, double } %[[VEC]], 2
@@ -688,7 +696,8 @@
 // CHECK-BE: call <2 x i64> @vec_vbpermq(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef %{{[0-9a-zA-Z_.]+}}, <16 x i8> noundef bitcast (<4 x i32>  to <16 x i8>))
 // CHECK-BE: %[[EXT:[0-9a-zA-Z_.]+]] = extractelement <2 x i64> %{{[0-9a-zA-Z_.]+}}, i32 0
 // CHECK-BE: trunc i64 %[[EXT]] to i32
-// CHECK-P10: call zeroext i32 @vec_extractm(unsigned int vector[4])(<4 x i32> noundef %{{[0-9a-zA-Z_.]+}})
+// CHECK-P10-LE: call zeroext i32 @vec_extractm(unsigned int vector[4])(<4 x i32> noundef %{{[0-9a-zA-Z_.]+}})
+// CHECK-P10-BE: call zeroext i32 @vec_extractm(unsigned int vector[4])(<4 x i32> noundef %{{[0-9a-zA-Z_.]+}})
 
 void __attribute__((noinl

[PATCH] D129461: [PowerPC] Support x86 compatible intrinsics on AIX

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf created this revision.
qiucf added reviewers: nemanjai, shchenz, hubert.reinterpretcast, PowerPC.
Herald added subscribers: jsji, steven.zhang, kbarton, krytarowski, 
arichardson, emaste.
Herald added a project: All.
qiucf requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

These headers used to be guarded only on PowerPC64 Linux or FreeBSD.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D129461

Files:
  clang/lib/Driver/ToolChains/AIX.cpp
  clang/lib/Headers/ppc_wrappers/emmintrin.h
  clang/lib/Headers/ppc_wrappers/mm_malloc.h
  clang/lib/Headers/ppc_wrappers/mmintrin.h
  clang/lib/Headers/ppc_wrappers/pmmintrin.h
  clang/lib/Headers/ppc_wrappers/smmintrin.h
  clang/lib/Headers/ppc_wrappers/tmmintrin.h
  clang/lib/Headers/ppc_wrappers/xmmintrin.h
  clang/test/CodeGen/PowerPC/ppc-emmintrin.c
  clang/test/CodeGen/PowerPC/ppc-mm-malloc.c
  clang/test/CodeGen/PowerPC/ppc-mmintrin.c
  clang/test/CodeGen/PowerPC/ppc-pmmintrin.c
  clang/test/CodeGen/PowerPC/ppc-smmintrin.c
  clang/test/CodeGen/PowerPC/ppc-tmmintrin.c
  clang/test/CodeGen/PowerPC/ppc-x86gprintrin.c
  clang/test/CodeGen/PowerPC/ppc-xmmintrin.c

Index: clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
===
--- clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
+++ clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
@@ -10,7 +10,7 @@
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns
 
 // RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
-// RUN:   -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-P10
+// RUN:   -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-P10-LE
 
 // RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64-unknown-freebsd13.0 -mcpu=pwr8 -ffreestanding -nostdlibinc -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE
@@ -21,6 +21,13 @@
 // RUN: %clang -Xclang -no-opaque-pointers -x c++ -fsyntax-only -target powerpc64le-unknown-freebsd13.0 -mcpu=pwr8 -ffreestanding -nostdlibinc -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns
 
+// RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64-ibm-aix -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: %clang -Xclang -no-opaque-pointers -x c++ -fsyntax-only -target powerpc64-ibm-aix -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns
+// RUN: %clang -Xclang -no-opaque-pointers -S -emit-llvm -target powerpc64-ibm-aix -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-P10-BE
+
 #include 
 
 __m128 res, m1, m2;
@@ -388,7 +395,8 @@
 // CHECK-LABEL: define available_externally signext i32 @_mm_cvtss_si32
 // CHECK-LE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xxsldwi ${0:x},${0:x},${0:x},3;\0Axscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
 // CHECK-BE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
-// CHECK-P10: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xxsldwi ${0:x},${0:x},${0:x},3;\0Axscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
+// CHECK-P10-LE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xxsldwi ${0:x},${0:x},${0:x},3;\0Axscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
+// CHECK-P10-BE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
 // CHECK: extractvalue { <4 x float>, i32, double } %[[VEC]], 0
 // CHECK: extractvalue { <4 x float>, i32, double } %[[VEC]], 1
 // CHECK: extractvalue { <4 x float>, i32, double } %[[VEC]], 2
@@ -688,7 +696,8 @@
 // CHECK-BE: call <2 x i64> @vec_vbpermq(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef %{{[0-9a-zA-Z_.]+}}, <16 x i8> noundef bitcast (<4 x i32>  to <16 x i8>))
 // CHECK-BE: %[[EXT:[0-9a-zA-Z_.]+]] = extractelement <2 x i64> %{{[0-9a-zA-Z_.]+}}, i32 0
 // CHECK-BE: trunc i64 %[[EXT]] to i32
-// CHECK-P10: call zeroext i32 @vec_extractm(unsigned int vector[4])(<4 x i32> noundef %{{[0-9a-z

[PATCH] D116395: [Clang] Emit warning for -x option without effects

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.
Herald added a subscriber: MaskRay.
Herald added a project: All.

Abandon this since we have rGe2a1f8ec27b88be670cd867c43588f24516d2bbf 
.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116395/new/

https://reviews.llvm.org/D116395

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D126302: [PowerPC] Diagnose invalid combination with Altivec, VSX and soft-float

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added inline comments.



Comment at: clang/lib/Basic/Targets/PPC.cpp:450
 
+  // Cannot allow VSX with no Altivec.
+  if (llvm::is_contained(FeaturesVec, "-hard-float") &&

Comments in reverse order?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126302/new/

https://reviews.llvm.org/D126302

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D122478: [PowerPC] Add max/min intrinsics to Clang and PPC backend

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf accepted this revision as: qiucf.
qiucf added a comment.
This revision is now accepted and ready to land.

Looks good to me in my side. Thanks for implementing it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122478/new/

https://reviews.llvm.org/D122478

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D122478: [PowerPC] Add max/min intrinsics to Clang and PPC backend

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added inline comments.



Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:9897
+def err_ppc_unsupported_argument_type : Error<
+  "unsupported argument type %0 for target %1">;
 def err_x86_builtin_invalid_rounding : Error<

Use `err_target_unsupported_type`?



Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:192
+  [llvm_float_ty, llvm_float_ty, llvm_float_ty, 
llvm_vararg_ty],
+  [IntrNoMem]>;
 }

tingwang wrote:
> qiucf wrote:
> > Will we support `llvm_f128_ty`?
> I'm afraid not at this moment. Document mentions only three types: float, 
> double, or long double.
Can we at least leave a TODO comment here for `llvm_f128_ty` support?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122478/new/

https://reviews.llvm.org/D122478

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D121992: [Clang] [Driver] Add option to set alternative toolchain path

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.

In D121992#3418443 , @MaskRay wrote:

> To add more why I think the current semantics may need more discussion before 
> we quickly commit to such a driver option:
>
> - interaction with --dyld-prefix: --sysroot does not affect the fallback 
> --dyld-prefix. It seems even less appropriate for 
> --overlay-platform-toolchain to affect the fallback --dyld-prefix.
>
> If you intend to overlay ld.so, you'll necessarily overlay libc, then 
> --sysroot seems just unneeded at all.
>
> - interaction with --gcc-toolchain: I am a bit unclear we still want the 
> tricky GCC installation detection after --overlay-platform-toolchain is 
> specified. Do you propose that both will add include and library search paths?
> - -B: in gcc, when -B prefix specifies a directory, GCC adds $prefix/include 
> to the include search directory. Clang does not do this right now. I think 
> adding it may be an alternative approach to introducing the new option.
>
> The currently picked rules may be suitable for 
> https://github.com/advancetoolchain/advance-toolchain, but could be arbitrary 
> for many other use cases.
> Have you considered putting some options into a configuration file 
>  and using 
> `--config`?
>
> I understand that you probably have some short-term goal to make somethings 
> done, but as I mentioned, there might be some process issue here.
> This significant new feature very quickly landed without other driver folks 
> possibly had a chance to chime in.
> (FWIW I decided to subscribe all `clang/lib/Driver` patches since I care 
> about this area.)
> I very rarely do this but I think it is probably cleaner to revert this patch 
> and discuss it more carefully. I am happy to help you achieve your goal. It's 
> possible that we may still need a driver option.

Thanks for further information. I agree that we should not change to break the 
consistent behavior in such short period of time. It's reasonable for 
`--gcc-toolchain` to not add `include` into path (since driver only expects it 
to have GCC). I also saw GCC's different behavior on `-B`. We may need to fix 
it, but that's beyond this patch's scope.

It's okay to me to compose 'orthogonal' options into config file when 
available. Anyway, I'd like to revert this commit since there're comments not 
addressed.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121992/new/

https://reviews.llvm.org/D121992

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D122478: [PowerPC] Add max/min intrinsics to Clang and PPC backend

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added inline comments.



Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:9899
+def err_ppc_unsupported_argument_type : Error<
+  "unsupported argument type %0 for target %1">;
 def err_x86_builtin_invalid_rounding : Error<

Can we re-use `err_typecheck_convert_incompatible`?



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:16290-16310
+  case PPC::BI__builtin_ppc_maxfe:
+  case PPC::BI__builtin_ppc_maxfl:
+  case PPC::BI__builtin_ppc_maxfs:
+  case PPC::BI__builtin_ppc_minfe:
+  case PPC::BI__builtin_ppc_minfl:
+  case PPC::BI__builtin_ppc_minfs: {
+if (BuiltinID == PPC::BI__builtin_ppc_maxfe)





Comment at: clang/lib/Sema/SemaChecking.cpp:3913
+  case PPC::BI__builtin_ppc_minfs: {
+// FIXME: remove below check once -mlong-double-128 is supported on AIX.
+if (Context.getTargetInfo().getTriple().isOSAIX() &&

I think we don't need this fixme.



Comment at: clang/test/CodeGen/PowerPC/builtins-ppc.c:65
+  // CHECK: call double (double, double, double, ...) @llvm.ppc.maxfl(double 
%0,
+  // double %1, double %2, double %3)
+  res = __builtin_ppc_maxfl(a, b, c, d);

Don't break CHECK lines.



Comment at: clang/test/Sema/builtins-ppc.c:13-17
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -DTEST_MAXMIN 
-fsyntax-only \
+// RUN: -verify %s
+
+// RUN: %clang_cc1 -triple powerpc64-ibm-aix-xcoff -DTEST_MAXMINFE_AIX 
-fsyntax-only \
+// RUN: -verify %s





Comment at: clang/test/Sema/builtins-ppc.c:63-83
+#ifdef TEST_MAXMIN
+void test_maxmin() {
+  long double fe;
+  double fl;
+  float fs;
+  __builtin_ppc_maxfe(fl, fl, fl, fl); // expected-error-re {{requires 
argument of {{.*}} type (passed in {{.*}})}}
+  __builtin_ppc_minfe(fl, fl, fl, fl); // expected-error-re {{requires 
argument of {{.*}} type (passed in {{.*}})}}

I don't know if it's convention in tests, but looks simpler.



Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:192
+  [llvm_float_ty, llvm_float_ty, llvm_float_ty, 
llvm_vararg_ty],
+  [IntrNoMem]>;
 }

Will we support `llvm_f128_ty`?



Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10583-10587
+for (unsigned i = 4, e = Op.getNumOperands(); i < e; ++i) {
+  if (Op.getOperand(i).getValueType() != Op.getValueType())
+report_fatal_error("Intrinsic::ppc_[max|min]f[e|l|s] must have uniform 
"
+   "type arguments");
+}

We can make it even simpler.



Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10594
+// Below selection order follows XLC behavior: start from the last but one
+// operand, move towards the first operand, end with the last operand.
+unsigned I, Cnt;

We don't need to mention old behavior.



Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10595-10596
+// operand, move towards the first operand, end with the last operand.
+unsigned I, Cnt;
+I = Cnt = Op.getNumOperands() - 2;
+SDValue Res = Op.getOperand(I);





Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10598-10602
+for (--I; Cnt != 0; --Cnt, I = (--I == 0 ? (Op.getNumOperands() - 1) : I)) 
{
+  Res = LowerSELECT_CC(
+  DAG.getSelectCC(dl, Res, Op.getOperand(I), Res, Op.getOperand(I), 
CC),
+  DAG);
+}

I don't think we need to manually call `LowerSELECT_CC` here. SelectionDAG 
knows `ppc_fp128` should not be custom lowered.

This also makes the case pass. Thus D122462 is not needed.



Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:11266
+case Intrinsic::ppc_maxfe:
+case Intrinsic::ppc_minfe:
 case Intrinsic::ppc_fnmsub:

Why only two `fe`?



Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-maxmin.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux < %s | FileCheck %s
+

Can we add `pwr8` run line?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122478/new/

https://reviews.llvm.org/D122478

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D121992: [Clang] [Driver] Add option to set alternative toolchain path

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.

Hi,

> Why is --overlay-platform-toolchain added instead of using -isystem and -L?
>
> The functionality overlaps with -B. Unsure why introduce a new mechanism.

We may want to use an extra toolchain like the Advance Toolchain 
(https://github.com/advancetoolchain/advance-toolchain) which includes 
Glibc/GCC/GDB/LD/etc. but is not a complete OS distribution. So we should not 
simply change `sysroot` here.

Using `-isystem` and `-L` is okay in principle, but (1) it breaks expected 
include order (`-isystem` just inserts it in the top); (2) we have to manually 
insert many `-isystem` paths; (3) we want to reuse the logic in clang driver 
code. `-B` changes search path of crt runtime files, but 
include/library/dynamic linker paths are the same.

What this option does is to insert the extra toolchain in all search paths but 
with higher priority than system default.




Comment at: clang/include/clang/Driver/Options.td:4184
+def _overlay_platform_toolchain_EQ : Joined<["--"], 
"overlay-platform-toolchain=">;
+def _overlay_platform_toolchain : Separate<["--"], 
"overlay-platform-toolchain">, Alias<_overlay_platform_toolchain_EQ>;
 def _param : Separate<["--"], "param">, Group;

MaskRay wrote:
> Separate-form driver options are not conventional. New driver options should 
> just avoid them.
Thanks for the reminder!



Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:1870
 
+  if (const Arg *X = Args.getLastArg(
+  clang::driver::options::OPT__overlay_platform_toolchain_EQ))

MaskRay wrote:
> Why was this  rule added?
Linker and other paths relies on location of specified GCC toolchain. And the 
toolchain specified by `overlay-platform-toolchain` is expected to have GCC 
installation included. But for sure, it has lower priority than `gcc-toolchain`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121992/new/

https://reviews.llvm.org/D121992

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D119407: [PowerPC] [Clang] Add SSE4 and BMI compatible intrinsics implementation for PowerPC

[Qiu Chaofan via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG406bde9a1513: [PowerPC] [Clang] Add SSE4 and BMI intrinsics 
implementation (authored by qiucf).

Changed prior to commit:
  https://reviews.llvm.org/D119407?vs=413336&id=417887#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119407/new/

https://reviews.llvm.org/D119407

Files:
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/ppc_wrappers/bmi2intrin.h
  clang/lib/Headers/ppc_wrappers/bmiintrin.h
  clang/lib/Headers/ppc_wrappers/emmintrin.h
  clang/lib/Headers/ppc_wrappers/immintrin.h
  clang/lib/Headers/ppc_wrappers/nmmintrin.h
  clang/lib/Headers/ppc_wrappers/pmmintrin.h
  clang/lib/Headers/ppc_wrappers/smmintrin.h
  clang/lib/Headers/ppc_wrappers/tmmintrin.h
  clang/lib/Headers/ppc_wrappers/x86gprintrin.h
  clang/lib/Headers/ppc_wrappers/x86intrin.h
  clang/lib/Headers/ppc_wrappers/xmmintrin.h
  clang/test/CodeGen/PowerPC/ppc-emmintrin.c
  clang/test/CodeGen/PowerPC/ppc-smmintrin.c
  clang/test/CodeGen/PowerPC/ppc-x86gprintrin.c
  clang/test/CodeGen/PowerPC/ppc-xmmintrin.c

Index: clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
===
--- clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
+++ clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
@@ -9,6 +9,9 @@
 // RUN: %clang -x c++ -fsyntax-only -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns
 
+// RUN: %clang -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr10 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-P10
+
 // RUN: %clang -S -emit-llvm -target powerpc64-unknown-freebsd13.0 -mcpu=pwr8 -ffreestanding -nostdlibinc -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE
 // RUN: %clang -x c++ -fsyntax-only -target powerpc64-unknown-freebsd13.0 -mcpu=pwr8 -ffreestanding -nostdlibinc -DNO_WARN_X86_INTRINSICS %s \
@@ -383,12 +386,12 @@
 // CHECK: extractelement <4 x float> %{{[0-9a-zA-Z_.]+}}, i32 0
 
 // CHECK-LABEL: define available_externally signext i32 @_mm_cvtss_si32
-// CHECK-LE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i64, double } asm "xxsldwi ${0:x},${0:x},${0:x},3;\0Axscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
-// CHECK-BE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i64, double } asm "xscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
-// CHECK: extractvalue { <4 x float>, i64, double } %[[VEC]], 0
-// CHECK: extractvalue { <4 x float>, i64, double } %[[VEC]], 1
-// CHECK: extractvalue { <4 x float>, i64, double } %[[VEC]], 2
-// CHECK: trunc i64 %{{[0-9a-zA-Z_.]+}} to i32
+// CHECK-LE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xxsldwi ${0:x},${0:x},${0:x},3;\0Axscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
+// CHECK-BE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
+// CHECK-P10: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xxsldwi ${0:x},${0:x},${0:x},3;\0Axscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
+// CHECK: extractvalue { <4 x float>, i32, double } %[[VEC]], 0
+// CHECK: extractvalue { <4 x float>, i32, double } %[[VEC]], 1
+// CHECK: extractvalue { <4 x float>, i32, double } %[[VEC]], 2
 
 // CHECK-LABEL: define available_externally i64 @_mm_cvtss_si64
 // CHECK-LE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i64, double } asm "xxsldwi ${0:x},${0:x},${0:x},3;\0Axscvspdp ${2:x},${0:x};\0Afctid  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
@@ -681,9 +684,11 @@
 // CHECK-LABEL: define available_externally signext i32 @_mm_movemask_ps
 // CHECK-LE: call <2 x i64> @vec_vbpermq(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef %{{[0-9a-zA-Z_.]+}}, <16 x i8> noundef bitcast (<4 x i32>  to <16 x i8>))
 // CHECK-LE: extractelement <2 x i64> %{{[0-9a-zA-Z_.]+}}, i32 1
+// CHECK-LE: trunc i64 %[[EXT]] to i32
 // CHECK-BE: call <2 x i64> @vec_vbpermq(unsigned char vector[16], unsigned char vector[16])(<16 x i8> noundef %{{[0-9a-zA-Z_.]+}}, <16 x i8> noundef bitcast (<4 x i32>  to <16 x i8>))
 // CHECK-BE: %[[EXT:[0-9a-zA-Z_.]+]] = extractelement <2 x i64> %{{[0-9a-zA-Z_.]+}}, i32 0
-// CHECK: trunc i64 %[[EXT]] to i32
+// CHECK-BE: trunc i64 %[[EXT]] to i32
+// CHECK-P10: call zeroext i32 @vec_extractm(unsigned int vector[4])(<4 x i32> noundef %{{[0-9a-zA-Z_.]+}})
 
 void __attribute__((noinline))
 test_alt_name_move() {
Index: cl

[PATCH] D121992: [Clang] [Driver] Add option to set alternative toolchain path

[Qiu Chaofan via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGd00e8400e2e3: [Clang] Add option to set alternative 
toolchain path (authored by qiucf).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121992/new/

https://reviews.llvm.org/D121992

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Driver/Driver.h
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/Driver.cpp
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/test/Driver/Inputs/powerpc64le-linux-gnu-tree/gcc-11.2.0/include/.keep
  clang/test/Driver/Inputs/powerpc64le-linux-gnu-tree/gcc-11.2.0/lib64/.keep
  clang/test/Driver/Inputs/powerpc64le-linux-gnu-tree/gcc-8.3.0/include/.keep
  
clang/test/Driver/Inputs/powerpc64le-linux-gnu-tree/gcc-8.3.0/lib/gcc/powerpc64le-linux-gnu/8.3.0/.keep
  clang/test/Driver/Inputs/powerpc64le-linux-gnu-tree/gcc-8.3.0/lib64/.keep
  clang/test/Driver/overlay-toolchain.cpp

Index: clang/test/Driver/overlay-toolchain.cpp
===
--- /dev/null
+++ clang/test/Driver/overlay-toolchain.cpp
@@ -0,0 +1,18 @@
+// RUN: %clangxx %s -### --target=powerpc64le-linux-gnu \
+// RUN:   --overlay-platform-toolchain=%S/Inputs/powerpc64le-linux-gnu-tree/gcc-11.2.0 \
+// RUN:   2>&1 | FileCheck %s --check-prefix=OVERLAY
+// RUN: %clangxx %s -### --target=powerpc64le-linux-gnu \
+// RUN:   --sysroot=%S/Inputs/powerpc64le-linux-gnu-tree/gcc-8.3.0 \
+// RUN:   --overlay-platform-toolchain=%S/Inputs/powerpc64le-linux-gnu-tree/gcc-11.2.0 \
+// RUN:   2>&1 | FileCheck %s --check-prefixes=OVERLAY,ROOT
+
+// OVERLAY: "-internal-externc-isystem"
+// OVERLAY: "[[TOOLCHAIN:[^"]+]]/powerpc64le-linux-gnu-tree/gcc-11.2.0/include"
+// ROOT: "-internal-externc-isystem"
+// ROOT: "[[TOOLCHAIN]]/powerpc64le-linux-gnu-tree/gcc-8.3.0/include"
+// OVERLAY: "-dynamic-linker"
+// OVERLAY: "[[TOOLCHAIN]]/powerpc64le-linux-gnu-tree/gcc-11.2.0/lib64/ld64.so.2"
+// OVERLAY: "-L[[TOOLCHAIN]]/powerpc64le-linux-gnu-tree/gcc-11.2.0/lib/../lib64"
+// ROOT: "-L[[TOOLCHAIN]]/powerpc64le-linux-gnu-tree/gcc-8.3.0/lib/../lib64"
+// OVERLAY: "-L[[TOOLCHAIN]]/powerpc64le-linux-gnu-tree/gcc-11.2.0/lib"
+// ROOT: "-L[[TOOLCHAIN]]/powerpc64le-linux-gnu-tree/gcc-8.3.0/lib"
Index: clang/lib/Driver/ToolChains/Linux.cpp
===
--- clang/lib/Driver/ToolChains/Linux.cpp
+++ clang/lib/Driver/ToolChains/Linux.cpp
@@ -260,6 +260,14 @@
 
   const std::string OSLibDir = std::string(getOSLibDir(Triple, Args));
   const std::string MultiarchTriple = getMultiarchTriple(D, Triple, SysRoot);
+  const std::string &ExtraPath = D.OverlayToolChainPath;
+
+  if (!D.OverlayToolChainPath.empty()) {
+addPathIfExists(D, ExtraPath + "/lib/" + MultiarchTriple, Paths);
+addPathIfExists(D, ExtraPath + "/lib/../" + OSLibDir, Paths);
+addPathIfExists(D, ExtraPath + "/usr/lib/" + MultiarchTriple, Paths);
+addPathIfExists(D, ExtraPath + "/usr/lib/../" + OSLibDir, Paths);
+  }
 
   // mips32: Debian multilib, we use /libo32, while in other case, /lib is
   // used. We need add both libo32 and /lib.
@@ -314,6 +322,11 @@
   addPathIfExists(D, D.Dir + "/../" + OSLibDir, Paths);
   }
 
+  if (!D.OverlayToolChainPath.empty()) {
+addPathIfExists(D, ExtraPath + "/lib", Paths);
+addPathIfExists(D, ExtraPath + "/usr/lib", Paths);
+  }
+
   addPathIfExists(D, SysRoot + "/lib", Paths);
   addPathIfExists(D, SysRoot + "/usr/lib", Paths);
 }
@@ -567,6 +580,10 @@
   if (DriverArgs.hasArg(options::OPT_nostdlibinc))
 return;
 
+  if (!D.OverlayToolChainPath.empty())
+addExternCSystemInclude(DriverArgs, CC1Args,
+D.OverlayToolChainPath + "/include");
+
   // LOCAL_INCLUDE_DIR
   addSystemInclude(DriverArgs, CC1Args, SysRoot + "/usr/local/include");
   // TOOL_INCLUDE_DIR
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -1867,6 +1867,10 @@
   if (A)
 return A->getValue();
 
+  if (const Arg *X = Args.getLastArg(
+  clang::driver::options::OPT__overlay_platform_toolchain_EQ))
+return X->getValue();
+
   // If we have a SysRoot, ignore GCC_INSTALL_PREFIX.
   // GCC_INSTALL_PREFIX specifies the gcc installation for the default
   // sysroot and is likely not valid with a different sysroot.
Index: clang/lib/Driver/Driver.cpp
===
--- clang/lib/Driver/Driver.cpp
+++ clang/lib/Driver/Driver.cpp
@@ -1208,6 +1208,11 @@
   CompilerPath = Split.second;
 }
   }
+  if (const Arg *A =
+  Args.getLastArg(options::OPT__overlay_platform_toolchain_EQ)) {
+OverlayToolChainPath = A->getValue();
+DyldPrefix = A->getValue();
+  }
   if (const Arg *A = Args.getLastArg(options::OPT__sys

[PATCH] D121992: [Clang] [Driver] Add option to set alternative toolchain path

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf updated this revision to Diff 417566.
qiucf marked 3 inline comments as done.
qiucf added a comment.

- Move test to another file
- Add documentation on option


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121992/new/

https://reviews.llvm.org/D121992

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Driver/Driver.h
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/Driver.cpp
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/test/Driver/Inputs/powerpc64le-linux-gnu-tree/gcc-11.2.0/include/.keep
  clang/test/Driver/Inputs/powerpc64le-linux-gnu-tree/gcc-11.2.0/lib64/.keep
  clang/test/Driver/Inputs/powerpc64le-linux-gnu-tree/gcc-8.3.0/include/.keep
  
clang/test/Driver/Inputs/powerpc64le-linux-gnu-tree/gcc-8.3.0/lib/gcc/powerpc64le-linux-gnu/8.3.0/.keep
  clang/test/Driver/Inputs/powerpc64le-linux-gnu-tree/gcc-8.3.0/lib64/.keep
  clang/test/Driver/overlay-toolchain.cpp

Index: clang/test/Driver/overlay-toolchain.cpp
===
--- /dev/null
+++ clang/test/Driver/overlay-toolchain.cpp
@@ -0,0 +1,18 @@
+// RUN: %clangxx %s -### --target=powerpc64le-linux-gnu \
+// RUN:   --overlay-platform-toolchain=%S/Inputs/powerpc64le-linux-gnu-tree/gcc-11.2.0 \
+// RUN:   2>&1 | FileCheck %s --check-prefix=OVERLAY
+// RUN: %clangxx %s -### --target=powerpc64le-linux-gnu \
+// RUN:   --sysroot=%S/Inputs/powerpc64le-linux-gnu-tree/gcc-8.3.0 \
+// RUN:   --overlay-platform-toolchain=%S/Inputs/powerpc64le-linux-gnu-tree/gcc-11.2.0 \
+// RUN:   2>&1 | FileCheck %s --check-prefixes=OVERLAY,ROOT
+
+// OVERLAY: "-internal-externc-isystem"
+// OVERLAY: "[[TOOLCHAIN:[^"]+]]/powerpc64le-linux-gnu-tree/gcc-11.2.0/include"
+// ROOT: "-internal-externc-isystem"
+// ROOT: "[[TOOLCHAIN]]/powerpc64le-linux-gnu-tree/gcc-8.3.0/include"
+// OVERLAY: "-dynamic-linker"
+// OVERLAY: "[[TOOLCHAIN]]/powerpc64le-linux-gnu-tree/gcc-11.2.0/lib64/ld64.so.2"
+// OVERLAY: "-L[[TOOLCHAIN]]/powerpc64le-linux-gnu-tree/gcc-11.2.0/lib/../lib64"
+// ROOT: "-L[[TOOLCHAIN]]/powerpc64le-linux-gnu-tree/gcc-8.3.0/lib/../lib64"
+// OVERLAY: "-L[[TOOLCHAIN]]/powerpc64le-linux-gnu-tree/gcc-11.2.0/lib"
+// ROOT: "-L[[TOOLCHAIN]]/powerpc64le-linux-gnu-tree/gcc-8.3.0/lib"
Index: clang/lib/Driver/ToolChains/Linux.cpp
===
--- clang/lib/Driver/ToolChains/Linux.cpp
+++ clang/lib/Driver/ToolChains/Linux.cpp
@@ -260,6 +260,14 @@
 
   const std::string OSLibDir = std::string(getOSLibDir(Triple, Args));
   const std::string MultiarchTriple = getMultiarchTriple(D, Triple, SysRoot);
+  const std::string &ExtraPath = D.OverlayToolChainPath;
+
+  if (!D.OverlayToolChainPath.empty()) {
+addPathIfExists(D, ExtraPath + "/lib/" + MultiarchTriple, Paths);
+addPathIfExists(D, ExtraPath + "/lib/../" + OSLibDir, Paths);
+addPathIfExists(D, ExtraPath + "/usr/lib/" + MultiarchTriple, Paths);
+addPathIfExists(D, ExtraPath + "/usr/lib/../" + OSLibDir, Paths);
+  }
 
   // mips32: Debian multilib, we use /libo32, while in other case, /lib is
   // used. We need add both libo32 and /lib.
@@ -314,6 +322,11 @@
   addPathIfExists(D, D.Dir + "/../" + OSLibDir, Paths);
   }
 
+  if (!D.OverlayToolChainPath.empty()) {
+addPathIfExists(D, ExtraPath + "/lib", Paths);
+addPathIfExists(D, ExtraPath + "/usr/lib", Paths);
+  }
+
   addPathIfExists(D, SysRoot + "/lib", Paths);
   addPathIfExists(D, SysRoot + "/usr/lib", Paths);
 }
@@ -567,6 +580,10 @@
   if (DriverArgs.hasArg(options::OPT_nostdlibinc))
 return;
 
+  if (!D.OverlayToolChainPath.empty())
+addExternCSystemInclude(DriverArgs, CC1Args,
+D.OverlayToolChainPath + "/include");
+
   // LOCAL_INCLUDE_DIR
   addSystemInclude(DriverArgs, CC1Args, SysRoot + "/usr/local/include");
   // TOOL_INCLUDE_DIR
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -1867,6 +1867,10 @@
   if (A)
 return A->getValue();
 
+  if (const Arg *X = Args.getLastArg(
+  clang::driver::options::OPT__overlay_platform_toolchain_EQ))
+return X->getValue();
+
   // If we have a SysRoot, ignore GCC_INSTALL_PREFIX.
   // GCC_INSTALL_PREFIX specifies the gcc installation for the default
   // sysroot and is likely not valid with a different sysroot.
Index: clang/lib/Driver/Driver.cpp
===
--- clang/lib/Driver/Driver.cpp
+++ clang/lib/Driver/Driver.cpp
@@ -1208,6 +1208,11 @@
   CompilerPath = Split.second;
 }
   }
+  if (const Arg *A =
+  Args.getLastArg(options::OPT__overlay_platform_toolchain_EQ)) {
+OverlayToolChainPath = A->getValue();
+DyldPrefix = A->getValue();
+  }
   if (const Arg *A = Args.getLastArg(options::OPT__sysroot_EQ))
 

[PATCH] D121992: [Clang] [Driver] Add option to set alternative toolchain path

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf created this revision.
qiucf added reviewers: hubert.reinterpretcast, jsji, nemanjai, collinbaker, 
rpenacob.
Herald added a project: All.
qiucf requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

In some cases, we need to set alternative toolchain path other than the default 
with system (headers, libraries, dynamic linker prefix, `ld` path, etc.), but 
keep `sysroot` at the same time.

This patch introduces a new option `--overlay-platform-toolchain` to set up 
such alternative toolchain path.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D121992

Files:
  clang/include/clang/Driver/Driver.h
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/Driver.cpp
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/test/Driver/Inputs/powerpc64le-linux-gnu-tree/gcc-11.2.0/include/.keep
  clang/test/Driver/Inputs/powerpc64le-linux-gnu-tree/gcc-11.2.0/lib64/.keep
  clang/test/Driver/gcc-toolchain.cpp

Index: clang/test/Driver/gcc-toolchain.cpp
===
--- clang/test/Driver/gcc-toolchain.cpp
+++ clang/test/Driver/gcc-toolchain.cpp
@@ -37,3 +37,15 @@
 
 // AARCH64:Inputs{{[^"]+}}aarch64-suse-linux/{{[^"]+}}crt1.o"
 // NO_AARCH64-NOT: Inputs{{[^"]+}}aarch64-suse-linux/{{[^"]+}}crt1.o"
+
+/// Test option to add 'overlay platform toolchain'
+// RUN: %clangxx %s -### --target=powerpc64le-linux-gnu \
+// RUN:   --overlay-platform-toolchain=%S/Inputs/powerpc64le-linux-gnu-tree/gcc-11.2.0 \
+// RUN:   2>&1 | FileCheck %s --check-prefix=OVERLAY
+
+// OVERLAY: "-internal-externc-isystem"
+// OVERLAY: "[[TOOLCHAIN:[^"]+]]/powerpc64le-linux-gnu-tree/gcc-11.2.0/include"
+// OVERLAY: "-dynamic-linker"
+// OVERLAY: "[[TOOLCHAIN]]/powerpc64le-linux-gnu-tree/gcc-11.2.0/lib64/ld64.so.2"
+// OVERLAY: "-L[[TOOLCHAIN]]/powerpc64le-linux-gnu-tree/gcc-11.2.0/lib/../lib64"
+// OVERLAY: "-L[[TOOLCHAIN]]/powerpc64le-linux-gnu-tree/gcc-11.2.0/lib"
Index: clang/lib/Driver/ToolChains/Linux.cpp
===
--- clang/lib/Driver/ToolChains/Linux.cpp
+++ clang/lib/Driver/ToolChains/Linux.cpp
@@ -261,6 +261,16 @@
   const std::string OSLibDir = std::string(getOSLibDir(Triple, Args));
   const std::string MultiarchTriple = getMultiarchTriple(D, Triple, SysRoot);
 
+  if (!D.OverlayToolChainPath.empty()) {
+const std::string &ExtraPath = D.OverlayToolChainPath;
+addPathIfExists(D, ExtraPath + "/lib/" + MultiarchTriple, Paths);
+addPathIfExists(D, ExtraPath + "/lib/../" + OSLibDir, Paths);
+addPathIfExists(D, ExtraPath + "/usr/lib/" + MultiarchTriple, Paths);
+addPathIfExists(D, ExtraPath + "/usr/lib/../" + OSLibDir, Paths);
+addPathIfExists(D, ExtraPath + "/lib", Paths);
+addPathIfExists(D, ExtraPath + "/usr/lib", Paths);
+  }
+
   // mips32: Debian multilib, we use /libo32, while in other case, /lib is
   // used. We need add both libo32 and /lib.
   if (Arch == llvm::Triple::mips || Arch == llvm::Triple::mipsel) {
@@ -567,6 +577,10 @@
   if (DriverArgs.hasArg(options::OPT_nostdlibinc))
 return;
 
+  if (!D.OverlayToolChainPath.empty())
+addExternCSystemInclude(DriverArgs, CC1Args,
+D.OverlayToolChainPath + "/include");
+
   // LOCAL_INCLUDE_DIR
   addSystemInclude(DriverArgs, CC1Args, SysRoot + "/usr/local/include");
   // TOOL_INCLUDE_DIR
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -1867,6 +1867,10 @@
   if (A)
 return A->getValue();
 
+  if (const Arg *X = Args.getLastArg(
+  clang::driver::options::OPT__overlay_platform_toolchain_EQ))
+return X->getValue();
+
   // If we have a SysRoot, ignore GCC_INSTALL_PREFIX.
   // GCC_INSTALL_PREFIX specifies the gcc installation for the default
   // sysroot and is likely not valid with a different sysroot.
Index: clang/lib/Driver/Driver.cpp
===
--- clang/lib/Driver/Driver.cpp
+++ clang/lib/Driver/Driver.cpp
@@ -1208,6 +1208,11 @@
   CompilerPath = Split.second;
 }
   }
+  if (const Arg *A =
+  Args.getLastArg(options::OPT__overlay_platform_toolchain_EQ)) {
+OverlayToolChainPath = A->getValue();
+DyldPrefix = A->getValue();
+  }
   if (const Arg *A = Args.getLastArg(options::OPT__sysroot_EQ))
 SysRoot = A->getValue();
   if (const Arg *A = Args.getLastArg(options::OPT__dyld_prefix_EQ))
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -4178,6 +4178,8 @@
 def _output_class_directory : Separate<["--"], "output-class-directory">, Alias;
 def _output_EQ : Joined<["--"], "output=">, Alias;
 def _output : Separa

[PATCH] D121209: [clang][driver] Fix float128 diagnostics with glibc >= 2.32

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf accepted this revision.
qiucf added a comment.
This revision is now accepted and ready to land.

LGTM, thanks for the catch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121209/new/

https://reviews.llvm.org/D121209

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D119407: [PowerPC] [Clang] Add SSE4 and BMI compatible intrinsics implementation for PowerPC

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf updated this revision to Diff 413336.
qiucf added a comment.
Herald added a project: All.

Add P10  tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119407/new/

https://reviews.llvm.org/D119407

Files:
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/ppc_wrappers/bmi2intrin.h
  clang/lib/Headers/ppc_wrappers/bmiintrin.h
  clang/lib/Headers/ppc_wrappers/emmintrin.h
  clang/lib/Headers/ppc_wrappers/immintrin.h
  clang/lib/Headers/ppc_wrappers/nmmintrin.h
  clang/lib/Headers/ppc_wrappers/pmmintrin.h
  clang/lib/Headers/ppc_wrappers/smmintrin.h
  clang/lib/Headers/ppc_wrappers/tmmintrin.h
  clang/lib/Headers/ppc_wrappers/x86gprintrin.h
  clang/lib/Headers/ppc_wrappers/x86intrin.h
  clang/lib/Headers/ppc_wrappers/xmmintrin.h
  clang/test/CodeGen/PowerPC/ppc-emmintrin.c
  clang/test/CodeGen/PowerPC/ppc-smmintrin.c
  clang/test/CodeGen/PowerPC/ppc-x86gprintrin.c
  clang/test/CodeGen/PowerPC/ppc-xmmintrin.c

Index: clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
===
--- clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
+++ clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
@@ -383,12 +383,11 @@
 // CHECK: extractelement <4 x float> %{{[0-9a-zA-Z_.]+}}, i32 0
 
 // CHECK-LABEL: define available_externally signext i32 @_mm_cvtss_si32
-// CHECK-LE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i64, double } asm "xxsldwi ${0:x},${0:x},${0:x},3;\0Axscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
-// CHECK-BE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i64, double } asm "xscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
-// CHECK: extractvalue { <4 x float>, i64, double } %[[VEC]], 0
-// CHECK: extractvalue { <4 x float>, i64, double } %[[VEC]], 1
-// CHECK: extractvalue { <4 x float>, i64, double } %[[VEC]], 2
-// CHECK: trunc i64 %{{[0-9a-zA-Z_.]+}} to i32
+// CHECK-LE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xxsldwi ${0:x},${0:x},${0:x},3;\0Axscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
+// CHECK-BE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
+// CHECK: extractvalue { <4 x float>, i32, double } %[[VEC]], 0
+// CHECK: extractvalue { <4 x float>, i32, double } %[[VEC]], 1
+// CHECK: extractvalue { <4 x float>, i32, double } %[[VEC]], 2
 
 // CHECK-LABEL: define available_externally i64 @_mm_cvtss_si64
 // CHECK-LE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i64, double } asm "xxsldwi ${0:x},${0:x},${0:x},3;\0Axscvspdp ${2:x},${0:x};\0Afctid  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
Index: clang/test/CodeGen/PowerPC/ppc-x86gprintrin.c
===
--- /dev/null
+++ clang/test/CodeGen/PowerPC/ppc-x86gprintrin.c
@@ -0,0 +1,239 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr7 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s
+// RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr7 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s
+
+// RUN: %clang -S -emit-llvm -target powerpc64le-unknown-freebsd13.0 -mcpu=pwr7 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s
+// RUN: %clang -S -emit-llvm -target powerpc64-unknown-freebsd13.0 -mcpu=pwr7 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s
+
+#include 
+
+unsigned short us;
+unsigned ui;
+unsigned long long ul;
+
+void __attribute__((noinline))
+test_bmiintrin() {
+  __tzcnt_u16(us);
+  __andn_u32(ui, ui);
+  _bextr_u32(ui, ui, ui);
+  __bextr_u32(ui, ui);
+  __blsi_u32(ui);
+  _blsi_u32(ui);
+  __blsmsk_u32(ui);
+  _blsmsk_u32(ui);
+  __blsr_u32(ui);
+  _blsr_u32(ui);
+  __tzcnt_u32(ui);
+  _tzcnt_u32(ui);
+  __andn_u64(ul, ul);
+  _bextr_u64(ul, ui, ui);
+  __bextr_u64(ul, ul);
+  __blsi_u64(ul);
+  _blsi_u64(ul);
+  __blsmsk_u64(ul);
+  _blsmsk_u64(ul);
+  __blsr_u64(ul);
+  _blsr_u64(ul);
+  __tzcnt_u64(ul);
+  _tzcnt_u64(ul);
+}
+
+// CHECK-LABEL: @test_bmiintrin
+
+// CHECK-LABEL: define available_externally zeroext i16 @__tzcnt_u16(i16 noundef zeroext %{{[0-9a-zA-Z._]+}})
+// CHECK: %[[CONV:[0-9a-zA-Z._]+]] = zext i16 %{{[0-9a-zA-Z._]+}} to i32
+// CHECK: %[[CALL:[0-9a-zA-Z._]+]] = call i32 @llvm.cttz.i32(i32 %[[CONV]], i1 false)
+// CHECK: trunc i32 %[[CALL]] to i16
+
+// CHECK-LABEL: define available_externally zeroext i32 @__andn_u32(i32 noundef zeroext %{{[0-9a-zA-Z._

[PATCH] D116015: [PowerPC] Add generic fnmsub intrinsic

[Qiu Chaofan via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGb2497e54356d: [PowerPC] Add generic fnmsub intrinsic 
(authored by qiucf).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116015/new/

https://reviews.llvm.org/D116015

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-fma.c
  clang/test/CodeGen/PowerPC/builtins-ppc-fpconstrained.c
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
@@ -98,49 +98,104 @@
 
 declare float @llvm.ppc.fnmadds(float, float, float)
 
-define dso_local double @fnmsub_t0(double %d, double %d2, double %d3) {
-; CHECK-PWR8-LABEL: fnmsub_t0:
+define dso_local float @fnmsub_f32(float %f, float %f2, float %f3) {
+; CHECK-PWR8-LABEL: fnmsub_f32:
 ; CHECK-PWR8:   # %bb.0: # %entry
-; CHECK-PWR8-NEXT:xsnmsubmdp 1, 2, 3
+; CHECK-PWR8-NEXT:xsnmsubasp 3, 1, 2
+; CHECK-PWR8-NEXT:fmr 1, 3
 ; CHECK-PWR8-NEXT:blr
 ;
-; CHECK-NOVSX-LABEL: fnmsub_t0:
+; CHECK-NOVSX-LABEL: fnmsub_f32:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fnmsubs 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:blr
+;
+; CHECK-PWR7-LABEL: fnmsub_f32:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:fnmsubs 1, 1, 2, 3
+; CHECK-PWR7-NEXT:blr
+entry:
+  %0 = tail call float @llvm.ppc.fnmsub.f32(float %f, float %f2, float %f3)
+  ret float %0
+}
+
+declare float @llvm.ppc.fnmsub.f32(float, float, float)
+
+define dso_local double @fnmsub_f64(double %f, double %f2, double %f3) {
+; CHECK-PWR8-LABEL: fnmsub_f64:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xsnmsubadp 3, 1, 2
+; CHECK-PWR8-NEXT:fmr 1, 3
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: fnmsub_f64:
 ; CHECK-NOVSX:   # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:fnmsub 1, 1, 2, 3
 ; CHECK-NOVSX-NEXT:blr
 ;
-; CHECK-PWR7-LABEL: fnmsub_t0:
+; CHECK-PWR7-LABEL: fnmsub_f64:
 ; CHECK-PWR7:   # %bb.0: # %entry
-; CHECK-PWR7-NEXT:xsnmsubmdp 1, 2, 3
+; CHECK-PWR7-NEXT:xsnmsubadp 3, 1, 2
+; CHECK-PWR7-NEXT:fmr 1, 3
 ; CHECK-PWR7-NEXT:blr
 entry:
-  %0 = tail call double @llvm.ppc.fnmsub(double %d, double %d2, double %d3)
+  %0 = tail call double @llvm.ppc.fnmsub.f64(double %f, double %f2, double %f3)
   ret double %0
 }
 
-declare double @llvm.ppc.fnmsub(double, double, double)
+declare double @llvm.ppc.fnmsub.f64(double, double, double)
 
-define dso_local float @fnmsubs_t0(float %f, float %f2, float %f3) {
-; CHECK-PWR8-LABEL: fnmsubs_t0:
+define dso_local <4 x float> @fnmsub_v4f32(<4 x float> %f, <4 x float> %f2, <4 x float> %f3) {
+; CHECK-PWR8-LABEL: fnmsub_v4f32:
 ; CHECK-PWR8:   # %bb.0: # %entry
-; CHECK-PWR8-NEXT:xsnmsubmsp 1, 2, 3
+; CHECK-PWR8-NEXT:xvnmsubasp 36, 34, 35
+; CHECK-PWR8-NEXT:vmr 2, 4
 ; CHECK-PWR8-NEXT:blr
 ;
-; CHECK-NOVSX-LABEL: fnmsubs_t0:
+; CHECK-NOVSX-LABEL: fnmsub_v4f32:
 ; CHECK-NOVSX:   # %bb.0: # %entry
-; CHECK-NOVSX-NEXT:fnmsubs 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:fnmsubs 1, 1, 5, 9
+; CHECK-NOVSX-NEXT:fnmsubs 2, 2, 6, 10
+; CHECK-NOVSX-NEXT:fnmsubs 3, 3, 7, 11
+; CHECK-NOVSX-NEXT:fnmsubs 4, 4, 8, 12
 ; CHECK-NOVSX-NEXT:blr
 ;
-; CHECK-PWR7-LABEL: fnmsubs_t0:
+; CHECK-PWR7-LABEL: fnmsub_v4f32:
 ; CHECK-PWR7:   # %bb.0: # %entry
-; CHECK-PWR7-NEXT:fnmsubs 1, 1, 2, 3
+; CHECK-PWR7-NEXT:xvnmsubasp 36, 34, 35
+; CHECK-PWR7-NEXT:vmr 2, 4
 ; CHECK-PWR7-NEXT:blr
 entry:
-  %0 = tail call float @llvm.ppc.fnmsubs(float %f, float %f2, float %f3)
-  ret float %0
+  %0 = tail call <4 x float> @llvm.ppc.fnmsub.v4f32(<4 x float> %f, <4 x float> %f2, <4 x float> %f3)
+  ret <4 x float> %0
+}
+
+declare <4 x float> @llvm.ppc.fnmsub.v4f32(<4 x float>, <4 x float>, <4 x float>)
+
+define dso_local <2 x double> @fnmsub_v2f64(<2 x double> %f, <2 x double> %f2, <2 x double> %f3) {
+; CHECK-PWR8-LABEL: fnmsub_v2f64:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xvnmsubadp 36, 34, 35
+; CHECK-PWR8-NEXT:vmr 2, 4
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: fnmsub_v2f64:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fnmsub 1, 1, 3, 5
+; CHECK-NOVSX-NEXT:fnmsub 2, 2, 4, 6
+; CHECK-NOVSX-NEXT:blr
+;
+; CHECK-PWR7-LABEL: fnmsub_v2f64:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:xvnmsubadp 36, 34, 35
+; CHECK-PWR7-NEXT:vmr 2, 4
+; CHECK-PWR7-NEX

[PATCH] D116015: [PowerPC] Add generic fnmsub intrinsic

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added inline comments.



Comment at: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.c:98
 // CHECK-NEXT:store double [[D:%.*]], double* [[D_ADDR]], align 8
+// CHECK-COUNT-3:load double, double* [[D_ADDR]], align 8
 // CHECK-NEXT:[[TMP0:%.*]] = load double, double* [[D_ADDR]], align 8

shchenz wrote:
> If we improve the check lines to CHECK-COUNT, do we still need the original 
> CHECKs?
Yes, otherwise we can't capture the right operands of `llvm.ppc.fnmsub.f64`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116015/new/

https://reviews.llvm.org/D116015

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D116015: [PowerPC] Add generic fnmsub intrinsic

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf updated this revision to Diff 41.
qiucf marked an inline comment as done.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116015/new/

https://reviews.llvm.org/D116015

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-fma.c
  clang/test/CodeGen/PowerPC/builtins-ppc-fpconstrained.c
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
@@ -98,49 +98,104 @@
 
 declare float @llvm.ppc.fnmadds(float, float, float)
 
-define dso_local double @fnmsub_t0(double %d, double %d2, double %d3) {
-; CHECK-PWR8-LABEL: fnmsub_t0:
+define dso_local float @fnmsub_f32(float %f, float %f2, float %f3) {
+; CHECK-PWR8-LABEL: fnmsub_f32:
 ; CHECK-PWR8:   # %bb.0: # %entry
-; CHECK-PWR8-NEXT:xsnmsubmdp 1, 2, 3
+; CHECK-PWR8-NEXT:xsnmsubasp 3, 1, 2
+; CHECK-PWR8-NEXT:fmr 1, 3
 ; CHECK-PWR8-NEXT:blr
 ;
-; CHECK-NOVSX-LABEL: fnmsub_t0:
+; CHECK-NOVSX-LABEL: fnmsub_f32:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fnmsubs 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:blr
+;
+; CHECK-PWR7-LABEL: fnmsub_f32:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:fnmsubs 1, 1, 2, 3
+; CHECK-PWR7-NEXT:blr
+entry:
+  %0 = tail call float @llvm.ppc.fnmsub.f32(float %f, float %f2, float %f3)
+  ret float %0
+}
+
+declare float @llvm.ppc.fnmsub.f32(float, float, float)
+
+define dso_local double @fnmsub_f64(double %f, double %f2, double %f3) {
+; CHECK-PWR8-LABEL: fnmsub_f64:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xsnmsubadp 3, 1, 2
+; CHECK-PWR8-NEXT:fmr 1, 3
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: fnmsub_f64:
 ; CHECK-NOVSX:   # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:fnmsub 1, 1, 2, 3
 ; CHECK-NOVSX-NEXT:blr
 ;
-; CHECK-PWR7-LABEL: fnmsub_t0:
+; CHECK-PWR7-LABEL: fnmsub_f64:
 ; CHECK-PWR7:   # %bb.0: # %entry
-; CHECK-PWR7-NEXT:xsnmsubmdp 1, 2, 3
+; CHECK-PWR7-NEXT:xsnmsubadp 3, 1, 2
+; CHECK-PWR7-NEXT:fmr 1, 3
 ; CHECK-PWR7-NEXT:blr
 entry:
-  %0 = tail call double @llvm.ppc.fnmsub(double %d, double %d2, double %d3)
+  %0 = tail call double @llvm.ppc.fnmsub.f64(double %f, double %f2, double %f3)
   ret double %0
 }
 
-declare double @llvm.ppc.fnmsub(double, double, double)
+declare double @llvm.ppc.fnmsub.f64(double, double, double)
 
-define dso_local float @fnmsubs_t0(float %f, float %f2, float %f3) {
-; CHECK-PWR8-LABEL: fnmsubs_t0:
+define dso_local <4 x float> @fnmsub_v4f32(<4 x float> %f, <4 x float> %f2, <4 x float> %f3) {
+; CHECK-PWR8-LABEL: fnmsub_v4f32:
 ; CHECK-PWR8:   # %bb.0: # %entry
-; CHECK-PWR8-NEXT:xsnmsubmsp 1, 2, 3
+; CHECK-PWR8-NEXT:xvnmsubasp 36, 34, 35
+; CHECK-PWR8-NEXT:vmr 2, 4
 ; CHECK-PWR8-NEXT:blr
 ;
-; CHECK-NOVSX-LABEL: fnmsubs_t0:
+; CHECK-NOVSX-LABEL: fnmsub_v4f32:
 ; CHECK-NOVSX:   # %bb.0: # %entry
-; CHECK-NOVSX-NEXT:fnmsubs 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:fnmsubs 1, 1, 5, 9
+; CHECK-NOVSX-NEXT:fnmsubs 2, 2, 6, 10
+; CHECK-NOVSX-NEXT:fnmsubs 3, 3, 7, 11
+; CHECK-NOVSX-NEXT:fnmsubs 4, 4, 8, 12
 ; CHECK-NOVSX-NEXT:blr
 ;
-; CHECK-PWR7-LABEL: fnmsubs_t0:
+; CHECK-PWR7-LABEL: fnmsub_v4f32:
 ; CHECK-PWR7:   # %bb.0: # %entry
-; CHECK-PWR7-NEXT:fnmsubs 1, 1, 2, 3
+; CHECK-PWR7-NEXT:xvnmsubasp 36, 34, 35
+; CHECK-PWR7-NEXT:vmr 2, 4
 ; CHECK-PWR7-NEXT:blr
 entry:
-  %0 = tail call float @llvm.ppc.fnmsubs(float %f, float %f2, float %f3)
-  ret float %0
+  %0 = tail call <4 x float> @llvm.ppc.fnmsub.v4f32(<4 x float> %f, <4 x float> %f2, <4 x float> %f3)
+  ret <4 x float> %0
+}
+
+declare <4 x float> @llvm.ppc.fnmsub.v4f32(<4 x float>, <4 x float>, <4 x float>)
+
+define dso_local <2 x double> @fnmsub_v2f64(<2 x double> %f, <2 x double> %f2, <2 x double> %f3) {
+; CHECK-PWR8-LABEL: fnmsub_v2f64:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xvnmsubadp 36, 34, 35
+; CHECK-PWR8-NEXT:vmr 2, 4
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: fnmsub_v2f64:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fnmsub 1, 1, 3, 5
+; CHECK-NOVSX-NEXT:fnmsub 2, 2, 4, 6
+; CHECK-NOVSX-NEXT:blr
+;
+; CHECK-PWR7-LABEL: fnmsub_v2f64:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:xvnmsubadp 36, 34, 35
+; CHECK-PWR7-NEXT:vmr 2, 4
+; CHECK-PWR7-NEXT:blr
+entry:
+  %0 = tail call <2 x double> @llvm.ppc.fnmsub.v2f64(<2 x double> %f, <2 x double> %f2, <2 x double> %f3)
+  ret <2 x dou

[PATCH] D116015: [PowerPC] Add generic fnmsub intrinsic

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf updated this revision to Diff 411046.
qiucf marked an inline comment as done.
qiucf edited the summary of this revision.
qiucf added a comment.

Replace existing `ppc.fnmsub` and `ppc.fnmsubs`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116015/new/

https://reviews.llvm.org/D116015

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-fma.c
  clang/test/CodeGen/PowerPC/builtins-ppc-fpconstrained.c
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
@@ -98,49 +98,104 @@
 
 declare float @llvm.ppc.fnmadds(float, float, float)
 
-define dso_local double @fnmsub_t0(double %d, double %d2, double %d3) {
-; CHECK-PWR8-LABEL: fnmsub_t0:
+define dso_local float @fnmsub_f32(float %f, float %f2, float %f3) {
+; CHECK-PWR8-LABEL: fnmsub_f32:
 ; CHECK-PWR8:   # %bb.0: # %entry
-; CHECK-PWR8-NEXT:xsnmsubmdp 1, 2, 3
+; CHECK-PWR8-NEXT:xsnmsubasp 3, 1, 2
+; CHECK-PWR8-NEXT:fmr 1, 3
 ; CHECK-PWR8-NEXT:blr
 ;
-; CHECK-NOVSX-LABEL: fnmsub_t0:
+; CHECK-NOVSX-LABEL: fnmsub_f32:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fnmsubs 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:blr
+;
+; CHECK-PWR7-LABEL: fnmsub_f32:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:fnmsubs 1, 1, 2, 3
+; CHECK-PWR7-NEXT:blr
+entry:
+  %0 = tail call float @llvm.ppc.fnmsub.f32(float %f, float %f2, float %f3)
+  ret float %0
+}
+
+declare float @llvm.ppc.fnmsub.f32(float, float, float)
+
+define dso_local double @fnmsub_f64(double %f, double %f2, double %f3) {
+; CHECK-PWR8-LABEL: fnmsub_f64:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xsnmsubadp 3, 1, 2
+; CHECK-PWR8-NEXT:fmr 1, 3
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: fnmsub_f64:
 ; CHECK-NOVSX:   # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:fnmsub 1, 1, 2, 3
 ; CHECK-NOVSX-NEXT:blr
 ;
-; CHECK-PWR7-LABEL: fnmsub_t0:
+; CHECK-PWR7-LABEL: fnmsub_f64:
 ; CHECK-PWR7:   # %bb.0: # %entry
-; CHECK-PWR7-NEXT:xsnmsubmdp 1, 2, 3
+; CHECK-PWR7-NEXT:xsnmsubadp 3, 1, 2
+; CHECK-PWR7-NEXT:fmr 1, 3
 ; CHECK-PWR7-NEXT:blr
 entry:
-  %0 = tail call double @llvm.ppc.fnmsub(double %d, double %d2, double %d3)
+  %0 = tail call double @llvm.ppc.fnmsub.f64(double %f, double %f2, double %f3)
   ret double %0
 }
 
-declare double @llvm.ppc.fnmsub(double, double, double)
+declare double @llvm.ppc.fnmsub.f64(double, double, double)
 
-define dso_local float @fnmsubs_t0(float %f, float %f2, float %f3) {
-; CHECK-PWR8-LABEL: fnmsubs_t0:
+define dso_local <4 x float> @fnmsub_v4f32(<4 x float> %f, <4 x float> %f2, <4 x float> %f3) {
+; CHECK-PWR8-LABEL: fnmsub_v4f32:
 ; CHECK-PWR8:   # %bb.0: # %entry
-; CHECK-PWR8-NEXT:xsnmsubmsp 1, 2, 3
+; CHECK-PWR8-NEXT:xvnmsubasp 36, 34, 35
+; CHECK-PWR8-NEXT:vmr 2, 4
 ; CHECK-PWR8-NEXT:blr
 ;
-; CHECK-NOVSX-LABEL: fnmsubs_t0:
+; CHECK-NOVSX-LABEL: fnmsub_v4f32:
 ; CHECK-NOVSX:   # %bb.0: # %entry
-; CHECK-NOVSX-NEXT:fnmsubs 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:fnmsubs 1, 1, 5, 9
+; CHECK-NOVSX-NEXT:fnmsubs 2, 2, 6, 10
+; CHECK-NOVSX-NEXT:fnmsubs 3, 3, 7, 11
+; CHECK-NOVSX-NEXT:fnmsubs 4, 4, 8, 12
 ; CHECK-NOVSX-NEXT:blr
 ;
-; CHECK-PWR7-LABEL: fnmsubs_t0:
+; CHECK-PWR7-LABEL: fnmsub_v4f32:
 ; CHECK-PWR7:   # %bb.0: # %entry
-; CHECK-PWR7-NEXT:fnmsubs 1, 1, 2, 3
+; CHECK-PWR7-NEXT:xvnmsubasp 36, 34, 35
+; CHECK-PWR7-NEXT:vmr 2, 4
 ; CHECK-PWR7-NEXT:blr
 entry:
-  %0 = tail call float @llvm.ppc.fnmsubs(float %f, float %f2, float %f3)
-  ret float %0
+  %0 = tail call <4 x float> @llvm.ppc.fnmsub.v4f32(<4 x float> %f, <4 x float> %f2, <4 x float> %f3)
+  ret <4 x float> %0
+}
+
+declare <4 x float> @llvm.ppc.fnmsub.v4f32(<4 x float>, <4 x float>, <4 x float>)
+
+define dso_local <2 x double> @fnmsub_v2f64(<2 x double> %f, <2 x double> %f2, <2 x double> %f3) {
+; CHECK-PWR8-LABEL: fnmsub_v2f64:
+; CHECK-PWR8:   # %bb.0: # %entry
+; CHECK-PWR8-NEXT:xvnmsubadp 36, 34, 35
+; CHECK-PWR8-NEXT:vmr 2, 4
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: fnmsub_v2f64:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fnmsub 1, 1, 3, 5
+; CHECK-NOVSX-NEXT:fnmsub 2, 2, 4, 6
+; CHECK-NOVSX-NEXT:blr
+;
+; CHECK-PWR7-LABEL: fnmsub_v2f64:
+; CHECK-PWR7:   # %bb.0: # %entry
+; CHECK-PWR7-NEXT:xvnmsubadp 36, 34, 35
+; CHECK-PWR7-NEXT:vmr 2, 4
+; CHECK-PWR7-NEXT:blr
+entry:
+  %0

[PATCH] D116015: [PowerPC] Add generic fnmsub intrinsic

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.

In D116015#3326148 , @shchenz wrote:

>> hiding the semantics from the optimizer is sometimes a good thing and 
>> sometimes a bad thing).
>
> Agree. Imagining a case when the neg and fma (from fnmsub) can both be CSE-ed 
> with another neg and fma, so we can totally eliminate the fnmsub. But after 
> we convert it to an intrinsic, we may lose the opportunity to CSE the fnmsub.
>
>> Here's a pretty simple case: vector float foo(vector float a, vector float 
>> b, vector float c, vector float d) { return __builtin_vsx_xvnmsubasp(c, d, 
>> a*b); }
>> It current produces xvnegsp+xvmulsp+xvnmaddasp, after this patch it produces 
>> xvmulsp+xvnmsubasp. In some complicated cases, we can see much more 
>> unexpected instructions generated.
>
> This is narrowed down from a real-world case. After CSE some part of the 
> fnmsub, it is hard to optimize it back to a single hardware fnmsub 
> instruction as normally we check the use number of a register and if the user 
> number is not 1, we may exit the combine.
>
> Is it possible to get some perf data for some float workloads with this 
> patch? @qiucf

Thanks. I did not see performance change in some common benchmarks.




Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1737
+  [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
+  [IntrNoMem]>;
   def int_ppc_fre

shchenz wrote:
> When `llvm_anyfloat_ty` is `f32` or `f64`, we will generate two intrinsics 
> with same semantic. `llvm.ppc.nmsub.f32` + `llvm.ppc.fnmsubs` and 
> `llvm.ppc.nmsub.f64` + `llvm.ppc.fnmsub`. At first glance, we seems can not 
> delete the `int_ppc_fnmsub` and `int_ppc_fnmsubs`, because they are for XL 
> compatibility and XL has seperated fnmsub for float and double and we need to 
> map them 1 by 1. Better to check if it is possible to replace 
> `int_ppc_fnmsub` and `int_ppc_fnmsubs` with `int_ppc_nmsub`. And if it can be 
> replaced, we can use a meaningful name like `int_ppc_fnmsub` for the new 
> intrinsic.
We can do that, but that requires more work and seems beyond this patch's 
scope. See D105930, we'll need to handle the builtin in Clang. And the builtin 
explicitly generates type-M VSX instructions (I guess to reduce copy in simple 
cases).


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116015/new/

https://reviews.llvm.org/D116015

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D119407: [PowerPC] [Clang] Add SSE4 and BMI compatible intrinsics implementation for PowerPC

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf updated this revision to Diff 409167.
qiucf edited the summary of this revision.
qiucf added a comment.

Rebase the fix.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119407/new/

https://reviews.llvm.org/D119407

Files:
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/ppc_wrappers/bmi2intrin.h
  clang/lib/Headers/ppc_wrappers/bmiintrin.h
  clang/lib/Headers/ppc_wrappers/emmintrin.h
  clang/lib/Headers/ppc_wrappers/immintrin.h
  clang/lib/Headers/ppc_wrappers/nmmintrin.h
  clang/lib/Headers/ppc_wrappers/pmmintrin.h
  clang/lib/Headers/ppc_wrappers/smmintrin.h
  clang/lib/Headers/ppc_wrappers/tmmintrin.h
  clang/lib/Headers/ppc_wrappers/x86gprintrin.h
  clang/lib/Headers/ppc_wrappers/x86intrin.h
  clang/lib/Headers/ppc_wrappers/xmmintrin.h
  clang/test/CodeGen/PowerPC/ppc-emmintrin.c
  clang/test/CodeGen/PowerPC/ppc-smmintrin.c
  clang/test/CodeGen/PowerPC/ppc-x86gprintrin.c
  clang/test/CodeGen/PowerPC/ppc-xmmintrin.c

Index: clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
===
--- clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
+++ clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
@@ -383,12 +383,11 @@
 // CHECK: extractelement <4 x float> %{{[0-9a-zA-Z_.]+}}, i32 0
 
 // CHECK-LABEL: define available_externally signext i32 @_mm_cvtss_si32
-// CHECK-LE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i64, double } asm "xxsldwi ${0:x},${0:x},${0:x},3;\0Axscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
-// CHECK-BE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i64, double } asm "xscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
-// CHECK: extractvalue { <4 x float>, i64, double } %[[VEC]], 0
-// CHECK: extractvalue { <4 x float>, i64, double } %[[VEC]], 1
-// CHECK: extractvalue { <4 x float>, i64, double } %[[VEC]], 2
-// CHECK: trunc i64 %{{[0-9a-zA-Z_.]+}} to i32
+// CHECK-LE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xxsldwi ${0:x},${0:x},${0:x},3;\0Axscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
+// CHECK-BE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i32, double } asm "xscvspdp ${2:x},${0:x};\0Afctiw  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
+// CHECK: extractvalue { <4 x float>, i32, double } %[[VEC]], 0
+// CHECK: extractvalue { <4 x float>, i32, double } %[[VEC]], 1
+// CHECK: extractvalue { <4 x float>, i32, double } %[[VEC]], 2
 
 // CHECK-LABEL: define available_externally i64 @_mm_cvtss_si64
 // CHECK-LE: %[[VEC:[0-9a-zA-Z_.]+]] = call { <4 x float>, i64, double } asm "xxsldwi ${0:x},${0:x},${0:x},3;\0Axscvspdp ${2:x},${0:x};\0Afctid  $2,$2;\0Amfvsrd  $1,${2:x};\0A", "=^wa,=r,=f,0"
Index: clang/test/CodeGen/PowerPC/ppc-x86gprintrin.c
===
--- /dev/null
+++ clang/test/CodeGen/PowerPC/ppc-x86gprintrin.c
@@ -0,0 +1,239 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr7 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s
+// RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr7 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s
+
+// RUN: %clang -S -emit-llvm -target powerpc64le-unknown-freebsd13.0 -mcpu=pwr7 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s
+// RUN: %clang -S -emit-llvm -target powerpc64-unknown-freebsd13.0 -mcpu=pwr7 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s
+
+#include 
+
+unsigned short us;
+unsigned ui;
+unsigned long long ul;
+
+void __attribute__((noinline))
+test_bmiintrin() {
+  __tzcnt_u16(us);
+  __andn_u32(ui, ui);
+  _bextr_u32(ui, ui, ui);
+  __bextr_u32(ui, ui);
+  __blsi_u32(ui);
+  _blsi_u32(ui);
+  __blsmsk_u32(ui);
+  _blsmsk_u32(ui);
+  __blsr_u32(ui);
+  _blsr_u32(ui);
+  __tzcnt_u32(ui);
+  _tzcnt_u32(ui);
+  __andn_u64(ul, ul);
+  _bextr_u64(ul, ui, ui);
+  __bextr_u64(ul, ul);
+  __blsi_u64(ul);
+  _blsi_u64(ul);
+  __blsmsk_u64(ul);
+  _blsmsk_u64(ul);
+  __blsr_u64(ul);
+  _blsr_u64(ul);
+  __tzcnt_u64(ul);
+  _tzcnt_u64(ul);
+}
+
+// CHECK-LABEL: @test_bmiintrin
+
+// CHECK-LABEL: define available_externally zeroext i16 @__tzcnt_u16(i16 noundef zeroext %{{[0-9a-zA-Z._]+}})
+// CHECK: %[[CONV:[0-9a-zA-Z._]+]] = zext i16 %{{[0-9a-zA-Z._]+}} to i32
+// CHECK: %[[CALL:[0-9a-zA-Z._]+]] = call i32 @llvm.cttz.i32(i32 %[[CONV]], i1 false)
+// CHECK: trunc i32 %[[CALL]] to i16
+
+// CHECK-LABEL: define available_externally zeroext i32 @__andn_u32(i32 noundef zeroext %{{[0-9a-zA-Z._]+}}, i32 nounde

[PATCH] D119407: [PowerPC] [Clang] Add SSE4 and BMI compatible intrinsics implementation for PowerPC

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf planned changes to this revision.
qiucf added a comment.

This breaks existing smm/tmm tests, will update/clean-up them before this.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119407/new/

https://reviews.llvm.org/D119407

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D119407: [PowerPC] [Clang] Add SSE4 and BMI compatible intrinsics implementation for PowerPC

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf updated this revision to Diff 407444.
Herald added a subscriber: mgorny.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119407/new/

https://reviews.llvm.org/D119407

Files:
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/ppc_wrappers/bmi2intrin.h
  clang/lib/Headers/ppc_wrappers/bmiintrin.h
  clang/lib/Headers/ppc_wrappers/emmintrin.h
  clang/lib/Headers/ppc_wrappers/immintrin.h
  clang/lib/Headers/ppc_wrappers/nmmintrin.h
  clang/lib/Headers/ppc_wrappers/pmmintrin.h
  clang/lib/Headers/ppc_wrappers/smmintrin.h
  clang/lib/Headers/ppc_wrappers/tmmintrin.h
  clang/lib/Headers/ppc_wrappers/x86gprintrin.h
  clang/lib/Headers/ppc_wrappers/x86intrin.h
  clang/lib/Headers/ppc_wrappers/xmmintrin.h
  clang/test/CodeGen/PowerPC/ppc-smmintrin.c
  clang/test/CodeGen/PowerPC/ppc-x86gprintrin.c

Index: clang/test/CodeGen/PowerPC/ppc-x86gprintrin.c
===
--- /dev/null
+++ clang/test/CodeGen/PowerPC/ppc-x86gprintrin.c
@@ -0,0 +1,239 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr7 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s
+// RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr7 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s
+
+// RUN: %clang -S -emit-llvm -target powerpc64le-unknown-freebsd13.0 -mcpu=pwr7 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s
+// RUN: %clang -S -emit-llvm -target powerpc64-unknown-freebsd13.0 -mcpu=pwr7 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
+// RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s
+
+#include 
+
+unsigned short us;
+unsigned ui;
+unsigned long long ul;
+
+void __attribute__((noinline))
+test_bmiintrin() {
+  __tzcnt_u16(us);
+  __andn_u32(ui, ui);
+  _bextr_u32(ui, ui, ui);
+  __bextr_u32(ui, ui);
+  __blsi_u32(ui);
+  _blsi_u32(ui);
+  __blsmsk_u32(ui);
+  _blsmsk_u32(ui);
+  __blsr_u32(ui);
+  _blsr_u32(ui);
+  __tzcnt_u32(ui);
+  _tzcnt_u32(ui);
+  __andn_u64(ul, ul);
+  _bextr_u64(ul, ui, ui);
+  __bextr_u64(ul, ul);
+  __blsi_u64(ul);
+  _blsi_u64(ul);
+  __blsmsk_u64(ul);
+  _blsmsk_u64(ul);
+  __blsr_u64(ul);
+  _blsr_u64(ul);
+  __tzcnt_u64(ul);
+  _tzcnt_u64(ul);
+}
+
+// CHECK-LABEL: @test_bmiintrin
+
+// CHECK-LABEL: define available_externally zeroext i16 @__tzcnt_u16(i16 noundef zeroext %{{[0-9a-zA-Z._]+}})
+// CHECK: %[[CONV:[0-9a-zA-Z._]+]] = zext i16 %{{[0-9a-zA-Z._]+}} to i32
+// CHECK: %[[CALL:[0-9a-zA-Z._]+]] = call i32 @llvm.cttz.i32(i32 %[[CONV]], i1 false)
+// CHECK: trunc i32 %[[CALL]] to i16
+
+// CHECK-LABEL: define available_externally zeroext i32 @__andn_u32(i32 noundef zeroext %{{[0-9a-zA-Z._]+}}, i32 noundef zeroext %{{[0-9a-zA-Z._]+}})
+// CHECK: %[[NEG:[0-9a-zA-Z._]+]] = xor i32 %{{[0-9a-zA-Z._]+}}, -1
+// CHECK: and i32 %[[NEG]], %1
+
+// CHECK-LABEL: define available_externally zeroext i32 @_bextr_u32(i32 noundef zeroext %{{[0-9a-zA-Z._]+}}, i32 noundef zeroext %{{[0-9a-zA-Z._]+}}, i32 noundef zeroext %{{[0-9a-zA-Z._]+}})
+// CHECK: %[[ADD:[0-9a-zA-Z._]+]] = add i32 %{{[0-9a-zA-Z._]+}}, %{{[0-9a-zA-Z._]+}}
+// CHECK: %[[SUB:[0-9a-zA-Z._]+]] = sub i32 32, %[[ADD]]
+// CHECK: %[[SHL:[0-9a-zA-Z._]+]] = shl i32 %{{[0-9a-zA-Z._]+}}, %[[SUB]]
+// CHECK: %[[SUB]]1 = sub i32 32, %{{[0-9a-zA-Z._]+}}
+// CHECK: lshr i32 %[[SHL]], %[[SUB]]1
+
+// CHECK-LABEL: define available_externally zeroext i32 @__bextr_u32(i32 noundef zeroext %{{[0-9a-zA-Z._]+}}, i32 noundef zeroext %{{[0-9a-zA-Z._]+}})
+// CHECK: %[[AND:[0-9a-zA-Z._]+]] = and i32 %{{[0-9a-zA-Z._]+}}, 255
+// CHECK: %[[SHR:[0-9a-zA-Z._]+]] = lshr i32 %{{[0-9a-zA-Z._]+}}, 8
+// CHECK: and i32 %[[SHR]], 255
+// CHECK: call zeroext i32 @_bextr_u32
+
+// CHECK-LABEL: define available_externally zeroext i32 @__blsi_u32(i32 noundef zeroext %{{[0-9a-zA-Z._]+}})
+// CHECK: %[[SUB:[0-9a-zA-Z._]+]] = sub i32 0, %1
+// CHECK: and i32 %0, %[[SUB]]
+
+// CHECK-LABEL: define available_externally zeroext i32 @_blsi_u32(i32 noundef zeroext %{{[0-9a-zA-Z._]+}})
+// CHECK: call zeroext i32 @__blsi_u32
+
+// CHECK-LABEL: define available_externally zeroext i32 @__blsmsk_u32(i32 noundef zeroext %{{[0-9a-zA-Z._]+}})
+// CHECK: %[[SUB:[0-9a-zA-Z._]+]] = sub i32 %{{[0-9a-zA-Z._]+}}, 1
+// CHECK: xor i32 %{{[0-9a-zA-Z._]+}}, %[[SUB]]
+
+// CHECK-LABEL: define available_externally zeroext i32 @_blsmsk_u32(i32 noundef zeroext %{{[0-9a-zA-Z._]+}})
+// CHECK: call zeroext i32 @__blsmsk_u32
+
+// CHECK-LABEL: define available_externally zeroext i32 @__blsr_u32(i32 noundef zeroext %{{[0-9a-zA-Z._]+}})
+// CHECK: %[[SUB:[0-9a-zA-Z._]+]] = sub i32 %{{[0-9a-zA-Z._]+}}, 1
+/

[PATCH] D116015: [PowerPC] Add generic fnmsub intrinsic

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.

gentle ping


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116015/new/

https://reviews.llvm.org/D116015

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D119407: [PowerPC] [Clang] Add SSE4 and BMI compatible intrinsics implementation for PowerPC

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf created this revision.
qiucf added reviewers: jsji, nemanjai, PowerPC, shchenz.
Herald added subscribers: kbarton, krytarowski.
qiucf requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D119407

Files:
  clang/lib/Headers/ppc_wrappers/bmi2intrin.h
  clang/lib/Headers/ppc_wrappers/bmiintrin.h
  clang/lib/Headers/ppc_wrappers/emmintrin.h
  clang/lib/Headers/ppc_wrappers/immintrin.h
  clang/lib/Headers/ppc_wrappers/nmmintrin.h
  clang/lib/Headers/ppc_wrappers/pmmintrin.h
  clang/lib/Headers/ppc_wrappers/smmintrin.h
  clang/lib/Headers/ppc_wrappers/tmmintrin.h
  clang/lib/Headers/ppc_wrappers/x86gprintrin.h
  clang/lib/Headers/ppc_wrappers/x86intrin.h
  clang/lib/Headers/ppc_wrappers/xmmintrin.h

Index: clang/lib/Headers/ppc_wrappers/xmmintrin.h
===
--- clang/lib/Headers/ppc_wrappers/xmmintrin.h
+++ clang/lib/Headers/ppc_wrappers/xmmintrin.h
@@ -31,10 +31,8 @@
 #error "Please read comment above. Use -DNO_WARN_X86_INTRINSICS to disable this error."
 #endif
 
-#ifndef _XMMINTRIN_H_INCLUDED
-#define _XMMINTRIN_H_INCLUDED
-
-#if defined(__ppc64__) && (defined(__linux__) || defined(__FreeBSD__))
+#ifndef XMMINTRIN_H_
+#define XMMINTRIN_H_
 
 /* Define four value permute mask */
 #define _MM_SHUFFLE(w,x,y,z) (((w) << 6) | ((x) << 4) | ((y) << 2) | (z))
@@ -52,6 +50,8 @@
 #undef bool
 #endif
 
+#include 
+
 /* We need type definitions from the MMX header file.  */
 #include 
 
@@ -62,13 +62,14 @@
 
 /* The Intel API is flexible enough that we must allow aliasing with other
vector types, and their scalar components.  */
-typedef vector float __m128 __attribute__((__may_alias__));
+typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__));
 
 /* Unaligned version of the same type.  */
-typedef vector float __m128_u __attribute__((__may_alias__, __aligned__(1)));
+typedef float __m128_u __attribute__ ((__vector_size__ (16), __may_alias__,
+   __aligned__ (1)));
 
 /* Internal data types for implementing the intrinsics.  */
-typedef vector float __v4sf;
+typedef float __v4sf __attribute__ ((__vector_size__ (16)));
 
 /* Create an undefined vector.  */
 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
@@ -89,6 +90,7 @@
 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 _mm_load_ps (float const *__P)
 {
+  assert(((unsigned long)__P & 0xfUL) == 0UL);
   return ((__m128)vec_ld(0, (__v4sf*)__P));
 }
 
@@ -145,6 +147,7 @@
 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 _mm_store_ps (float *__P, __m128 __A)
 {
+  assert(((unsigned long)__P & 0xfUL) == 0UL);
   vec_st((__v4sf)__A, 0, (__v4sf*)__P);
 }
 
@@ -881,7 +884,7 @@
 extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 _mm_cvtss_si32 (__m128 __A)
 {
-  __m64 res = 0;
+  int res;
 #ifdef _ARCH_PWR8
   double dtmp;
   __asm__(
@@ -914,8 +917,8 @@
 extern __inline long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 _mm_cvtss_si64 (__m128 __A)
 {
-  __m64 res = 0;
-#ifdef _ARCH_PWR8
+  long long res;
+#if defined (_ARCH_PWR8) && defined (__powerpc64__)
   double dtmp;
   __asm__(
 #ifdef __LITTLE_ENDIAN__
@@ -1328,6 +1331,9 @@
 extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 _mm_movemask_ps (__m128  __A)
 {
+#ifdef _ARCH_PWR10
+  return vec_extractm ((__vector unsigned int) __A);
+#else
   __vector unsigned long long result;
   static const __vector unsigned int perm_mask =
 {
@@ -1347,6 +1353,7 @@
 #else
   return result[0];
 #endif
+#endif /* !_ARCH_PWR10 */
 }
 #endif /* _ARCH_PWR8 */
 
@@ -1553,6 +1560,7 @@
 extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 _mm_movemask_pi8 (__m64 __A)
 {
+#ifdef __powerpc64__
   unsigned long long p =
 #ifdef __LITTLE_ENDIAN__
  0x0008101820283038UL; // permute control for sign bits
@@ -1560,6 +1568,18 @@
  0x3830282018100800UL; // permute control for sign bits
 #endif
   return __builtin_bpermd (p, __A);
+#else
+#ifdef __LITTLE_ENDIAN__
+  unsigned int mask = 0x20283038UL;
+  unsigned int r1 = __builtin_bpermd (mask, __A) & 0xf;
+  unsigned int r2 = __builtin_bpermd (mask, __A >> 32) & 0xf;
+#else
+  unsigned int mask = 0x38302820UL;
+  unsigned int r1 = __builtin_bpermd (mask, __A >> 32) & 0xf;
+  unsigned int r2 = __builtin_bpermd (mask, __A) & 0xf;
+#endif
+  return (r2 << 4) | r1;
+#endif
 }
 
 extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
@@ -1841,4 +1861,4 @@
 #endif /* defined(__ppc64__) && (defined(__linux__) || defined(__FreeBSD__))   \
 */
 
-#endif /* _XMMINTRIN_H_INCLUDED */
+#endif /* XMMINTRIN_H_ */
Index: clang/lib/Headers/ppc_wrappers/x86intrin.h
==

[PATCH] D112906: [PowerPC] Emit warning for ieeelongdouble on older GNU toolchain

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.

In D112906#3305014 , @jwakely wrote:

> In D112906#3304925 , @qiucf wrote:
>
>> Is that because clang lacks something required by this feature? (for 
>> example. clang-12 doesn't have `__ibm128` and many builtins) If so, clang-14 
>> should have these fixed.
>
> When I implemented the libstdc++ changes Clang didn't have any of your work 
> yet. Now that everything seems to be present, and `__LONG_DOUBLE_IEEE128__` 
> and `__LONG_DOUBLE_IBM128__` are defined as appropriate, I think I can enable 
> it for clang. I'll look into that tomorrow.

Thanks! I verified latest LLVM/Clang with latest libstdc++ in some programs and 
they look okay. If you found any more issues, I still have time to get them 
fixed in clang 14 rc2.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112906/new/

https://reviews.llvm.org/D112906

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D112906: [PowerPC] Emit warning for ieeelongdouble on older GNU toolchain

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.

In D112906#3304340 , @jwakely wrote:

>> GCC 12 should have proper support for IEEE-754 compliant 128-bit floating 
>> point in libstdc++.
>
> Yes, but it's unconditionally disabled when including the headers with Clang.

Is that because clang lacks something required by this feature? (for example. 
clang-12 doesn't have `__ibm128` and many builtins) If so, clang-14 should have 
these fixed.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112906/new/

https://reviews.llvm.org/D112906

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D117972: [PowerPC] Fix SSE translation on FreeBSD

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.

In D117972#3287553 , @pkubaj wrote:

> Since I'm not a LLVM committer, can you commit it and merge to 14 branch?

Sure. Sorry for late response, I'm on vacation these days.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117972/new/

https://reviews.llvm.org/D117972

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D116395: [Clang] Emit warning for -x option without effects

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf added a comment.

gentle ping


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116395/new/

https://reviews.llvm.org/D116395

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D118110: [CMake] [Clang] Add CMake build option to specify long double format on PowerPC

[Qiu Chaofan via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGb797d5e6b21b: [CMake] [Clang] Add option to specify PowerPC 
long double format (authored by qiucf).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118110/new/

https://reviews.llvm.org/D118110

Files:
  clang/CMakeLists.txt
  clang/include/clang/Config/config.h.cmake
  clang/include/clang/Driver/ToolChain.h
  clang/lib/Driver/ToolChain.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/Analysis/builtin_signbit.cpp
  clang/test/Driver/ppc-abi.c

Index: clang/test/Driver/ppc-abi.c
===
--- clang/test/Driver/ppc-abi.c
+++ clang/test/Driver/ppc-abi.c
@@ -63,9 +63,6 @@
 // CHECK-ELFv1-IEEE: "-mabi=ieeelongdouble"
 // CHECK-ELFv1-IEEE: "-target-abi" "elfv1"
 
-// Check -mabi=ibmlongdouble is the default.
-// RUN: %clang -target powerpc64le-linux-gnu %s -### 2>&1 \
-// RUN:   | FileCheck -check-prefix=CHECK-ELFv2-IBM128 %s
 // RUN: %clang -target powerpc64le-linux-gnu %s -mabi=ibmlongdouble -### 2>&1 \
 // RUN:   | FileCheck -check-prefix=CHECK-ELFv2-IBM128 %s
 
Index: clang/test/Analysis/builtin_signbit.cpp
===
--- clang/test/Analysis/builtin_signbit.cpp
+++ clang/test/Analysis/builtin_signbit.cpp
@@ -1,6 +1,9 @@
-// RUN: %clang -target powerpc-linux-gnu -emit-llvm -S -O0 %s -o - | FileCheck %s --check-prefix=CHECK-BE --check-prefix=CHECK
-// RUN: %clang -target powerpc64-linux-gnu   -emit-llvm -S -O0 %s -o - | FileCheck %s --check-prefix=CHECK-BE --check-prefix=CHECK
-// RUN: %clang -target powerpc64le-linux-gnu -emit-llvm -S -O0 %s -o - | FileCheck %s --check-prefix=CHECK-LE --check-prefix=CHECK
+// RUN: %clang -target powerpc-linux-gnu -emit-llvm -S -mabi=ibmlongdouble \
+// RUN:   -O0 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: %clang -target powerpc64-linux-gnu -emit-llvm -S -mabi=ibmlongdouble \
+// RUN:   -O0 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: %clang -target powerpc64le-linux-gnu -emit-llvm -S -mabi=ibmlongdouble \
+// RUN:   -O0 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LE
 
 bool b;
 double d = -1.0;
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -2061,7 +2061,7 @@
 }
   }
 
-  bool IEEELongDouble = false;
+  bool IEEELongDouble = getToolChain().defaultToIEEELongDouble();
   for (const Arg *A : Args.filtered(options::OPT_mabi_EQ)) {
 StringRef V = A->getValue();
 if (V == "ieeelongdouble")
Index: clang/lib/Driver/ToolChain.cpp
===
--- clang/lib/Driver/ToolChain.cpp
+++ clang/lib/Driver/ToolChain.cpp
@@ -109,6 +109,10 @@
   return ENABLE_X86_RELAX_RELOCATIONS;
 }
 
+bool ToolChain::defaultToIEEELongDouble() const {
+  return PPC_LINUX_DEFAULT_IEEELONGDOUBLE && getTriple().isOSLinux();
+}
+
 SanitizerArgs
 ToolChain::getSanitizerArgs(const llvm::opt::ArgList &JobArgs) const {
   SanitizerArgs SanArgs(*this, JobArgs, !SanitizerArgsChecked);
Index: clang/include/clang/Driver/ToolChain.h
===
--- clang/include/clang/Driver/ToolChain.h
+++ clang/include/clang/Driver/ToolChain.h
@@ -409,6 +409,9 @@
   /// Check whether to enable x86 relax relocations by default.
   virtual bool useRelaxRelocations() const;
 
+  /// Check whether use IEEE binary128 as long double format by default.
+  bool defaultToIEEELongDouble() const;
+
   /// GetDefaultStackProtectorLevel - Get the default stack protector level for
   /// this tool chain.
   virtual LangOptions::StackProtectorMode
Index: clang/include/clang/Config/config.h.cmake
===
--- clang/include/clang/Config/config.h.cmake
+++ clang/include/clang/Config/config.h.cmake
@@ -78,6 +78,9 @@
 /* enable x86 relax relocations by default */
 #cmakedefine01 ENABLE_X86_RELAX_RELOCATIONS
 
+/* Enable IEEE binary128 as default long double format on PowerPC Linux. */
+#cmakedefine01 PPC_LINUX_DEFAULT_IEEELONGDOUBLE
+
 /* Enable each functionality of modules */
 #cmakedefine01 CLANG_ENABLE_ARCMT
 #cmakedefine01 CLANG_ENABLE_OBJC_REWRITER
Index: clang/CMakeLists.txt
===
--- clang/CMakeLists.txt
+++ clang/CMakeLists.txt
@@ -237,6 +237,9 @@
 set(ENABLE_X86_RELAX_RELOCATIONS ON CACHE BOOL
 "enable x86 relax relocations by default")
 
+set(PPC_LINUX_DEFAULT_IEEELONGDOUBLE OFF CACHE BOOL
+"Enable IEEE binary128 as default long double format on PowerPC Linux.")
+
 set(CLANG_SPAWN_CC1 OFF CACHE BOOL
 "Whether clang should use a new process for the CC1 invocation")
 
___