[PATCH] D147525: [X86] Add AMX_COMPLEX to Graniterapids

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm accepted this revision.
xiangzhangllvm added a comment.

LGTM


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[PATCH] D147420: [X86] Support AMX Complex instructions

[Xiang Zhang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG038b7e6b761c: [X86] Support AMX Complex instructions 
(authored by xiangzhangllvm).
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Changed prior to commit:
  https://reviews.llvm.org/D147420?vs=510426=510660#toc

Repository:
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Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86_64.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/amxcomplexintrin.h
  clang/lib/Headers/immintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/X86/amx_complex_api.c
  clang/test/CodeGen/X86/amxcomplex-builtins.c
  clang/test/CodeGen/X86/amxcomplex-errors.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86ExpandPseudo.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86InstrAMX.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86LowerAMXType.cpp
  llvm/lib/Target/X86/X86RegisterInfo.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/AMX/amx-tile-complex-internals.ll
  llvm/test/CodeGen/X86/AMX/amxcomplex-intrinsics.ll
  llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-complex-att.txt
  llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-complex-intel.txt
  llvm/test/MC/X86/AMX/x86-64-amx-complex-att.s
  llvm/test/MC/X86/AMX/x86-64-amx-complex-intel.s

Index: llvm/test/MC/X86/AMX/x86-64-amx-complex-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/AMX/x86-64-amx-complex-intel.s
@@ -0,0 +1,17 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  tcmmimfp16ps tmm6, tmm5, tmm4
+// CHECK: encoding: [0xc4,0xe2,0x59,0x6c,0xf5]
+   tcmmimfp16ps tmm6, tmm5, tmm4
+
+// CHECK:  tcmmimfp16ps tmm3, tmm2, tmm1
+// CHECK: encoding: [0xc4,0xe2,0x71,0x6c,0xda]
+   tcmmimfp16ps tmm3, tmm2, tmm1
+
+// CHECK:  tcmmrlfp16ps tmm6, tmm5, tmm4
+// CHECK: encoding: [0xc4,0xe2,0x58,0x6c,0xf5]
+   tcmmrlfp16ps tmm6, tmm5, tmm4
+
+// CHECK:  tcmmrlfp16ps tmm3, tmm2, tmm1
+// CHECK: encoding: [0xc4,0xe2,0x70,0x6c,0xda]
+   tcmmrlfp16ps tmm3, tmm2, tmm1
Index: llvm/test/MC/X86/AMX/x86-64-amx-complex-att.s
===
--- /dev/null
+++ llvm/test/MC/X86/AMX/x86-64-amx-complex-att.s
@@ -0,0 +1,17 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding < %s  | FileCheck %s
+
+// CHECK:  tcmmimfp16ps %tmm4, %tmm5, %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x59,0x6c,0xf5]
+   tcmmimfp16ps %tmm4, %tmm5, %tmm6
+
+// CHECK:  tcmmimfp16ps %tmm1, %tmm2, %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x71,0x6c,0xda]
+   tcmmimfp16ps %tmm1, %tmm2, %tmm3
+
+// CHECK:  tcmmrlfp16ps %tmm4, %tmm5, %tmm6
+// CHECK: encoding: [0xc4,0xe2,0x58,0x6c,0xf5]
+   tcmmrlfp16ps %tmm4, %tmm5, %tmm6
+
+// CHECK:  tcmmrlfp16ps %tmm1, %tmm2, %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x70,0x6c,0xda]
+   tcmmrlfp16ps %tmm1, %tmm2, %tmm3
Index: llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-complex-intel.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-complex-intel.txt
@@ -0,0 +1,13 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s
+
+# CHECK:  tcmmimfp16ps tmm6, tmm5, tmm4
+0xc4,0xe2,0x59,0x6c,0xf5
+
+# CHECK:  tcmmimfp16ps tmm3, tmm2, tmm1
+0xc4,0xe2,0x71,0x6c,0xda
+
+# CHECK:  tcmmrlfp16ps tmm6, tmm5, tmm4
+0xc4,0xe2,0x58,0x6c,0xf5
+
+# CHECK:  tcmmrlfp16ps tmm3, tmm2, tmm1
+0xc4,0xe2,0x70,0x6c,0xda
Index: llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-complex-att.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-complex-att.txt
@@ -0,0 +1,13 @@
+# RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding --disassemble < %s  | FileCheck %s
+
+# CHECK:  tcmmimfp16ps %tmm4, %tmm5, %tmm6
+0xc4,0xe2,0x59,0x6c,0xf5
+
+# CHECK:  tcmmimfp16ps %tmm1, %tmm2, %tmm3
+0xc4,0xe2,0x71,0x6c,0xda
+
+# CHECK:  tcmmrlfp16ps %tmm4, %tmm5, %tmm6
+0xc4,0xe2,0x58,0x6c,0xf5
+
+# CHECK:  tcmmrlfp16ps %tmm1, %tmm2, %tmm3
+0xc4,0xe2,0x70,0x6c,0xda
Index: llvm/test/CodeGen/X86/AMX/amxcomplex-intrinsics.ll

[PATCH] D138547: [X86][AMX] Fix typo of the headerfile.

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm accepted this revision.
xiangzhangllvm added a comment.
This revision is now accepted and ready to land.

LGTM， thanks


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[PATCH] D135941: [X86] Support AMX-FP16

[Xiang Zhang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG661881d43633: [X86] Add AMX-FP16 instructions. (authored by 
xiangzhangllvm).
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Changed prior to commit:
  https://reviews.llvm.org/D135941?vs=469499=469828#toc

Repository:
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Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86_64.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/amxfp16intrin.h
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/immintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/X86/amx_errors.c
  clang/test/CodeGen/amx_fp16.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86InstrAMX.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/test/CodeGen/X86/amx_fp16_intrinsics.ll
  llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-tile-fp16.txt
  llvm/test/MC/X86/AMX/x86-64-amx-fp16-att.s
  llvm/test/MC/X86/AMX/x86-64-amx-fp16-intel.s

Index: llvm/test/MC/X86/AMX/x86-64-amx-fp16-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/AMX/x86-64-amx-fp16-intel.s
@@ -0,0 +1,5 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  tdpfp16ps   tmm3, tmm4, tmm5
+// CHECK: encoding: [0xc4,0xe2,0x53,0x5c,0xdc]
+   tdpfp16ps   tmm3, tmm4, tmm5
Index: llvm/test/MC/X86/AMX/x86-64-amx-fp16-att.s
===
--- /dev/null
+++ llvm/test/MC/X86/AMX/x86-64-amx-fp16-att.s
@@ -0,0 +1,5 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
+
+// CHECK:  tdpfp16ps   %tmm5, %tmm4, %tmm3
+// CHECK: encoding: [0xc4,0xe2,0x53,0x5c,0xdc]
+   tdpfp16ps   %tmm5, %tmm4, %tmm3
Index: llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-tile-fp16.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-tile-fp16.txt
@@ -0,0 +1,6 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck -check-prefix=ATT %s
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck -check-prefix=INTEL %s
+
+# ATT:   tdpfp16ps %tmm5, %tmm4, %tmm3
+# INTEL: tdpfp16ps tmm3, tmm4, tmm5
+0xc4,0xe2,0x53,0x5c,0xdc
Index: llvm/test/CodeGen/X86/amx_fp16_intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/amx_fp16_intrinsics.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-tile,+amx-fp16 | FileCheck %s
+
+; CHECK-LABEL: test_amx:
+; CHECK:   # %bb.0:
+; CHECK:tdpfp16ps   %tmm1, %tmm2, %tmm3
+
+define void @test_amx() {
+call void @llvm.x86.tdpfp16ps(i8 3, i8 2, i8 1)
+
+ret void
+}
+;;;
+declare void @llvm.x86.tdpfp16ps(i8 %tile3, i8 %tile2, i8 %tile1)
Index: llvm/lib/Target/X86/X86InstrInfo.td
===
--- llvm/lib/Target/X86/X86InstrInfo.td
+++ llvm/lib/Target/X86/X86InstrInfo.td
@@ -980,6 +980,7 @@
 def HasCX16  : Predicate<"Subtarget->hasCX16()">;
 def HasPCONFIG   : Predicate<"Subtarget->hasPCONFIG()">;
 def HasENQCMD: Predicate<"Subtarget->hasENQCMD()">;
+def HasAMXFP16   : Predicate<"Subtarget->hasAMXFP16()">;
 def HasKL: Predicate<"Subtarget->hasKL()">;
 def HasWIDEKL: Predicate<"Subtarget->hasWIDEKL()">;
 def HasHRESET: Predicate<"Subtarget->hasHRESET()">;
Index: llvm/lib/Target/X86/X86InstrAMX.td
===
--- llvm/lib/Target/X86/X86InstrAMX.td
+++ llvm/lib/Target/X86/X86InstrAMX.td
@@ -185,3 +185,21 @@
 }
   }
 } // HasAMXTILE, HasAMXBF16
+
+//AMX-FP16
+let Predicates = [HasAMXFP16, In64BitMode] in {
+  let SchedRW = [WriteSystem] in {
+let Constraints = "$src1 = $dst" in {
+  def TDPFP16PS : I<0x5c, MRMSrcReg4VOp3, (outs TILE:$dst),
+(ins TILE:$src1, TILE:$src2, TILE:$src3),
+"tdpfp16ps\t{$src3, $src2, $src1|$src1, $src2, $src3}",
+[]>, VEX_4V, T8XD;
+}
+let  usesCustomInserter = 1 in {
+  def PTDPFP16PS : PseudoI<(outs), (ins u8imm:$src1,
+  

[PATCH] D132636: [X86][bugfix] redefine __SSC_MARK to escape cpp string literal concatenation problem

[Xiang Zhang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG2da0df5e7cac: [X86][bugfix] redefine __SSC_MARK to escape 
cpp string literal concatenation… (authored by xiangzhangllvm).
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Files:
  clang/lib/Headers/x86gprintrin.h


Index: clang/lib/Headers/x86gprintrin.h
===
--- clang/lib/Headers/x86gprintrin.h
+++ clang/lib/Headers/x86gprintrin.h
@@ -26,22 +26,19 @@
 #endif
 
 #if defined(__i386__)
-#define __FULLBX "ebx"
+#define __SAVE_GPRBX "mov {%%ebx, %%eax |eax, ebx};"
+#define __RESTORE_GPRBX "mov {%%eax, %%ebx |ebx, eax};"
 #define __TMPGPR "eax"
 #else
 // When in 64-bit target, the 32-bit operands generate a 32-bit result,
 // zero-extended to a 64-bit result in the destination general-purpose,
 // It means "mov x %ebx" will clobber the higher 32 bits of rbx, so we
 // should preserve the 64-bit register rbx.
-#define __FULLBX "rbx"
+#define __SAVE_GPRBX "mov {%%rbx, %%rax |rax, rbx};"
+#define __RESTORE_GPRBX "mov {%%rax, %%rbx |rbx, rax};"
 #define __TMPGPR "rax"
 #endif
 
-#define __MOVEGPR(__r1, __r2) "mov {%%"__r1 ", %%"__r2 "|"__r2 ", "__r1"};"
-
-#define __SAVE_GPRBX __MOVEGPR(__FULLBX, __TMPGPR)
-#define __RESTORE_GPRBX __MOVEGPR(__TMPGPR, __FULLBX)
-
 #define __SSC_MARK(__Tag)  
\
   __asm__ __volatile__( __SAVE_GPRBX   
\
"mov {%0, %%ebx|ebx, %0}; " 
\


Index: clang/lib/Headers/x86gprintrin.h
===
--- clang/lib/Headers/x86gprintrin.h
+++ clang/lib/Headers/x86gprintrin.h
@@ -26,22 +26,19 @@
 #endif
 
 #if defined(__i386__)
-#define __FULLBX "ebx"
+#define __SAVE_GPRBX "mov {%%ebx, %%eax |eax, ebx};"
+#define __RESTORE_GPRBX "mov {%%eax, %%ebx |ebx, eax};"
 #define __TMPGPR "eax"
 #else
 // When in 64-bit target, the 32-bit operands generate a 32-bit result,
 // zero-extended to a 64-bit result in the destination general-purpose,
 // It means "mov x %ebx" will clobber the higher 32 bits of rbx, so we
 // should preserve the 64-bit register rbx.
-#define __FULLBX "rbx"
+#define __SAVE_GPRBX "mov {%%rbx, %%rax |rax, rbx};"
+#define __RESTORE_GPRBX "mov {%%rax, %%rbx |rbx, rax};"
 #define __TMPGPR "rax"
 #endif
 
-#define __MOVEGPR(__r1, __r2) "mov {%%"__r1 ", %%"__r2 "|"__r2 ", "__r1"};"
-
-#define __SAVE_GPRBX __MOVEGPR(__FULLBX, __TMPGPR)
-#define __RESTORE_GPRBX __MOVEGPR(__TMPGPR, __FULLBX)
-
 #define __SSC_MARK(__Tag)  \
   __asm__ __volatile__( __SAVE_GPRBX   \
"mov {%0, %%ebx|ebx, %0}; " \
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[PATCH] D130065: [X86] Use Min behavior for cf-protection-{return,branch}/ibt-seal module flags

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added inline comments.



Comment at: clang/lib/CodeGen/CodeGenModule.cpp:746
 // Indicate that we want to instrument return control flow protection.
-getModule().addModuleFlag(llvm::Module::Override, "cf-protection-return",
+getModule().addModuleFlag(llvm::Module::Min, "cf-protection-return",
   1);

xiangzhangllvm wrote:
> Take "cf-protection-return" for example:
> I pass  the "-fcf-protection=**none**" for following test x86-cf-protection.c
> It doesn't has "!{i32 Module::Min, !"cf-protection-return", i32 **0**}".
ah! I got it at https://reviews.llvm.org/D129911 line 1489, thanks


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[PATCH] D130065: [X86] Use Min behavior for cf-protection-{return,branch}/ibt-seal module flags

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added inline comments.



Comment at: clang/lib/CodeGen/CodeGenModule.cpp:746
 // Indicate that we want to instrument return control flow protection.
-getModule().addModuleFlag(llvm::Module::Override, "cf-protection-return",
+getModule().addModuleFlag(llvm::Module::Min, "cf-protection-return",
   1);

Take "cf-protection-return" for example:
I pass  the "-fcf-protection=**none**" for following test x86-cf-protection.c
It doesn't has "!{i32 Module::Min, !"cf-protection-return", i32 **0**}".



Comment at: clang/test/CodeGen/X86/x86-cf-protection.c:11
 // FULL: #define __CET__ 3
-// CFPROT: "cf-protection-branch", i32 1
-// IBTSEAL: "ibt-seal", i32 1
+// CFPROT: !{i32 8, !"cf-protection-branch", i32 1}
+// IBTSEAL: !{i32 8, !"ibt-seal", i32 1}

Seems we miss check the "llvm::Module::Override" (4) before, now is better.


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[PATCH] D129826: [X86] [BugFix] Add 64 bit implement for __SSC_MARK

[Xiang Zhang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG4bb19de4b6cb: [X86] Add 64 bit implement for __SSC_MARK 
(authored by xiangzhangllvm).
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Files:
  clang/lib/Headers/x86gprintrin.h
  clang/test/CodeGen/X86/x86-ssc-mark.c


Index: clang/test/CodeGen/X86/x86-ssc-mark.c
===
--- clang/test/CodeGen/X86/x86-ssc-mark.c
+++ clang/test/CodeGen/X86/x86-ssc-mark.c
@@ -1,20 +1,29 @@
 // REQUIRES: x86-registered-target
-// RUN: %clang_cc1 %s -triple=x86_64-unknown-unknown -S -ffreestanding -o - | 
FileCheck %s
-// RUN: %clang_cc1 %s -triple=i386-unknown-unknown -S -ffreestanding -o - | 
FileCheck %s
+// RUN: %clang_cc1 %s -triple=i386-unknown-unknown -S -ffreestanding -o - | 
FileCheck %s --check-prefix=X86
+// RUN: %clang_cc1 %s -triple=x86_64-unknown-unknown -S -ffreestanding -o - | 
FileCheck %s --check-prefix=X64
 
 #include 
 
 // The ebx may be use for base pointer, we need to restore it in time.
 void ssc_mark(void) {
-// CHECK-LABEL: ssc_mark
-// CHECK: #APP
-// CHECK: movl%ebx, %eax
-// CHECK: movl$0, %ebx
-// CHECK: .byte   100
-// CHECK: .byte   103
-// CHECK: .byte   144
-// CHECK: movl%eax, %ebx
-// CHECK: #NO_APP
+// X86-LABEL: ssc_mark
+// X86: #APP
+// X86: movl%ebx, %eax
+// X86: movl$9, %ebx
+// X86: .byte   100
+// X86: .byte   103
+// X86: .byte   144
+// X86: movl%eax, %ebx
+// X86: #NO_APP
 
-  __SSC_MARK(0x0);
+// X64-LABEL: ssc_mark
+// X64: #APP
+// X64: movq%rbx, %rax
+// X64: movl$9, %ebx
+// X64: .byte   100
+// X64: .byte   103
+// X64: .byte   144
+// X64: movq%rax, %rbx
+// X64: #NO_APP
+  __SSC_MARK(0x9);
 }
Index: clang/lib/Headers/x86gprintrin.h
===
--- clang/lib/Headers/x86gprintrin.h
+++ clang/lib/Headers/x86gprintrin.h
@@ -25,11 +25,29 @@
 #include 
 #endif
 
-#define __SSC_MARK(Tag)
\
-  __asm__ __volatile__("mov {%%ebx, %%eax|eax, ebx}; "  \
-   "mov {%0, %%ebx|ebx, %0}; "  \
+#if defined(__i386__)
+#define __FULLBX "ebx"
+#define __TMPGPR "eax"
+#else
+// When in 64-bit target, the 32-bit operands generate a 32-bit result,
+// zero-extended to a 64-bit result in the destination general-purpose,
+// It means "mov x %ebx" will clobber the higher 32 bits of rbx, so we
+// should preserve the 64-bit register rbx.
+#define __FULLBX "rbx"
+#define __TMPGPR "rax"
+#endif
+
+#define __MOVEGPR(__r1, __r2) "mov {%%"__r1 ", %%"__r2 "|"__r2 ", "__r1"};"
+
+#define __SAVE_GPRBX __MOVEGPR(__FULLBX, __TMPGPR)
+#define __RESTORE_GPRBX __MOVEGPR(__TMPGPR, __FULLBX)
+
+#define __SSC_MARK(__Tag)  
\
+  __asm__ __volatile__( __SAVE_GPRBX   
\
+   "mov {%0, %%ebx|ebx, %0}; " 
\
".byte 0x64, 0x67, 0x90; "  
\
-   "mov {%%eax, %%ebx|ebx, eax};" ::"i"(Tag)\
-   : "%eax");
+__RESTORE_GPRBX
\
+   ::"i"(__Tag)
\
+   :  __TMPGPR );
 
 #endif /* __X86GPRINTRIN_H */


Index: clang/test/CodeGen/X86/x86-ssc-mark.c
===
--- clang/test/CodeGen/X86/x86-ssc-mark.c
+++ clang/test/CodeGen/X86/x86-ssc-mark.c
@@ -1,20 +1,29 @@
 // REQUIRES: x86-registered-target
-// RUN: %clang_cc1 %s -triple=x86_64-unknown-unknown -S -ffreestanding -o - | FileCheck %s
-// RUN: %clang_cc1 %s -triple=i386-unknown-unknown -S -ffreestanding -o - | FileCheck %s
+// RUN: %clang_cc1 %s -triple=i386-unknown-unknown -S -ffreestanding -o - | FileCheck %s --check-prefix=X86
+// RUN: %clang_cc1 %s -triple=x86_64-unknown-unknown -S -ffreestanding -o - | FileCheck %s --check-prefix=X64
 
 #include 
 
 // The ebx may be use for base pointer, we need to restore it in time.
 void ssc_mark(void) {
-// CHECK-LABEL: ssc_mark
-// CHECK: #APP
-// CHECK: movl%ebx, %eax
-// CHECK: movl$0, %ebx
-// CHECK: .byte   100
-// CHECK: .byte   103
-// CHECK: .byte   144
-// CHECK: movl%eax, %ebx
-// CHECK: #NO_APP
+// X86-LABEL: ssc_mark
+// X86: #APP
+// X86: movl%ebx, %eax
+// X86: movl$9, %ebx
+// X86: .byte   100
+// X86: .byte   103
+// X86: .byte   144
+// X86: movl%eax, %ebx
+// X86: #NO_APP
 
-  __SSC_MARK(0x0);
+// X64-LABEL: ssc_mark
+// X64: #APP
+// X64: movq%rbx, %rax
+// X64: movl$9, %ebx
+// 

[PATCH] D129346: [X86] [Linux build][Stack Protector] Support for -mstack-protector-guard-symbol

[Xiang Zhang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa45dd3d8140e: [X86] Support -mstack-protector-guard-symbol 
(authored by xiangzhangllvm).
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Changed prior to commit:
  https://reviews.llvm.org/D129346?vs=443583=443816#toc

Repository:
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Files:
  clang/docs/ClangCommandLineReference.rst
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/CodeGenOptions.h
  clang/include/clang/Driver/Options.td
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/Driver/stack-protector-guard.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/Module.h
  llvm/lib/IR/Module.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/stack-protector-3.ll

Index: llvm/test/CodeGen/X86/stack-protector-3.ll
===
--- llvm/test/CodeGen/X86/stack-protector-3.ll
+++ llvm/test/CodeGen/X86/stack-protector-3.ll
@@ -6,6 +6,8 @@
 ; RUN: cat %t/main.ll %t/e.ll > %t/e2.ll
 ; RUN: cat %t/main.ll %t/f.ll > %t/f2.ll
 ; RUN: cat %t/main.ll %t/g.ll > %t/g2.ll
+; RUN: cat %t/main.ll %t/h.ll > %t/h2.ll
+; RUN: cat %t/existedGV.ll %t/main.ll %t/h.ll > %t/i2.ll
 ; RUN: llc -mtriple=x86_64-pc-linux-gnu -o - < %t/a2.ll | FileCheck --check-prefix=CHECK-TLS-FS-40 %s
 ; RUN: llc -mtriple=x86_64-pc-linux-gnu -o - < %t/b2.ll | FileCheck --check-prefix=CHECK-TLS-FS-40 %s
 ; RUN: llc -mtriple=x86_64-pc-linux-gnu -o - < %t/c2.ll | FileCheck --check-prefix=CHECK-GLOBAL %s
@@ -13,8 +15,8 @@
 ; RUN: llc -mtriple=x86_64-pc-linux-gnu -o - < %t/e2.ll | FileCheck --check-prefix=CHECK-GS %s
 ; RUN: llc -mtriple=x86_64-pc-linux-gnu -o - < %t/f2.ll | FileCheck --check-prefix=CHECK-OFFSET %s
 ; RUN: llc -mtriple=x86_64-pc-linux-gnu -o - < %t/g2.ll | FileCheck --check-prefix=CHECK-NEGATIVE-OFFSET %s
-
-;--- main.ll
+; RUN: llc -mtriple=x86_64-pc-linux-gnu -o - < %t/h2.ll | FileCheck --check-prefix=CHECK-SYM %s
+; RUN: llc -mtriple=x86_64-pc-linux-gnu -o - < %t/i2.ll | FileCheck --check-prefix=CHECK-SYMGV %s
 
 ; CHECK-TLS-FS-40:   movq%fs:40, %rax
 ; CHECK-TLS-FS-40:   movq%fs:40, %rax
@@ -57,7 +59,31 @@
 ; CHECK-GLOBAL-NEXT:  .cfi_def_cfa_offset 32
 ; CHECK-GLOBAL-NEXT:  callq   __stack_chk_fail
 
+; CHECK-SYM: movq__woof@GOTPCREL(%rip), %rax
+; CHECK-SYM-NEXT:movq%fs:(%rax), %rcx
+; CHECK-SYM-NEXT:movq%rcx, 16(%rsp)
+; CHECK-SYM: movq%fs:(%rax), %rax
+; CHECK-SYM-NEXT:cmpq16(%rsp), %rax
+; CHECK-SYM-NEXT:jne .LBB0_2
+; CHECK-SYM: .LBB0_2:
+; CHECK-SYM-NEXT:.cfi_def_cfa_offset 32
+; CHECK-SYM-NEXT:callq   __stack_chk_fai
+
+; CHECK-SYMGV:   movq__woof(%rip), %rax
+; CHECK-SYMGV-NEXT:  movq%rax, 16(%rsp)
+; CHECK-SYMGV:   cmpq16(%rsp), %rax
+; CHECK-SYMGV-NEXT:  jne .LBB0_2
+; CHECK-SYMGV:   .LBB0_2:
+; CHECK-SYMGV-NEXT:  .cfi_def_cfa_offset 32
+; CHECK-SYMGV-NEXT:  callq   __stack_chk_fail
+
 ; ModuleID = 't.c'
+;--- existedGV.ll
+
+@__woof = dso_local local_unnamed_addr global ptr null, align 8
+
+;--- main.ll
+
 @.str = private unnamed_addr constant [14 x i8] c"stackoverflow\00", align 1
 @a = dso_local local_unnamed_addr global ptr null, align 8
 
@@ -104,3 +130,6 @@
 ;--- g.ll
 !llvm.module.flags = !{!1}
 !1 = !{i32 2, !"stack-protector-guard-offset", i32 -20}
+;--- h.ll
+!llvm.module.flags = !{!1}
+!1 = !{i32 2, !"stack-protector-guard-symbol", !"__woof"}
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -2845,6 +2845,21 @@
 AddressSpace = X86AS::FS;
   else if (GuardReg == "gs")
 AddressSpace = X86AS::GS;
+
+  // Use symbol guard if user specify.
+  StringRef GuardSymb = M->getStackProtectorGuardSymbol();
+  if (!GuardSymb.empty()) {
+GlobalVariable *GV = M->getGlobalVariable(GuardSymb);
+if (!GV) {
+  Type *Ty = Subtarget.is64Bit() ? Type::getInt64Ty(M->getContext())
+ : Type::getInt32Ty(M->getContext());
+  GV = new GlobalVariable(*M, Ty, false, GlobalValue::ExternalLinkage,
+  nullptr, GuardSymb, nullptr,
+  GlobalValue::NotThreadLocal, AddressSpace);
+}
+return GV;
+  }
+
   return SegmentOffset(IRB, Offset, AddressSpace);
 }
   }
Index: llvm/lib/IR/Module.cpp
===
--- llvm/lib/IR/Module.cpp
+++ llvm/lib/IR/Module.cpp
@@ -714,6 +714,18 @@
   addModuleFlag(ModFlagBehavior::Error, "stack-protector-guard-reg", ID);
 }
 
+StringRef 

[PATCH] D118355: Add -mmanual-endbr switch to allow manual selection of control-flow protection

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added inline comments.



Comment at: llvm/lib/Target/X86/X86IndirectBranchTracking.cpp:156-161
   if (needsPrologueENDBR(MF, M)) {
-auto MBB = MF.begin();
-Changed |= addENDBR(*MBB, MBB->begin());
+if (!ManualENDBR || MF.getFunction().doesCfCheck()) {
+  auto MBB = MF.begin();
+  Changed |= addENDBR(*MBB, MBB->begin());
+} else {
+  // When -mmanual-endbr is in effect, the compiler does not

joaomoreira wrote:
> xiangzhangllvm wrote:
> > I am a little puzzle here. Let me copy your patch description here:
> > 
> > ```
> > >When -mmanual-endbr is set, llvm refrains from automatically adding
> > >ENDBR instructions to functions' prologues, which would have been
> > >automatically added by -fcf-protection=branch. Although this works
> > >correctly, missing ENDBR instructions where they are actually needed
> > >could lead to broken binaries, which would fail only in running time.
> > ```
> > I think the purpose of "-mmanual-endbr" should be "Supplementary Way" for 
> > the cases which the CET can't correctly insert endbr in automatic way.
> > Here (in if (needsPrologueENDBR(MF, M)) ) the automatic way will insert the 
> > endbr. So I think the job for "-mmanual-endbr" should be done in parallel 
> > with the old condition. Some like:
> > ```
> > if (ManualENDBR ){
> >   do something
> > }else { // automatic
> >   if (needsPrologueENDBR(MF, M)) {insert endbr}
> >  }
> > }
> > ```
> I don't think the idea of -mmanual-endbr is to have a supplementary way for 
> corner cases where CET misses automatic placement. In my understanding the 
> goal is to set the compiler to not emit ENDBRs unless the attribute cf_check 
> is used, thus providing a way to manually reduce the number of valid targets.
> 
> For reference, here is a link for -mmanual-endbr on gcc, 
> https://gcc.gnu.org/legacy-ml/gcc-patches/2018-12/msg00713.html and here are 
> patches on xen that use the feature (and that also mention this review): 
> https://www.mail-archive.com/xen-devel@lists.xenproject.org/msg114160.html
Thanks! Ok, for  "limit number of ENDBR instructions to reduce program size" 
here the code logic is make sense.


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[PATCH] D118355: Add -mmanual-endbr switch to allow manual selection of control-flow protection

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added inline comments.



Comment at: llvm/lib/Target/X86/X86IndirectBranchTracking.cpp:156-161
   if (needsPrologueENDBR(MF, M)) {
-auto MBB = MF.begin();
-Changed |= addENDBR(*MBB, MBB->begin());
+if (!ManualENDBR || MF.getFunction().doesCfCheck()) {
+  auto MBB = MF.begin();
+  Changed |= addENDBR(*MBB, MBB->begin());
+} else {
+  // When -mmanual-endbr is in effect, the compiler does not

I am a little puzzle here. Let me copy your patch description here:

```
>When -mmanual-endbr is set, llvm refrains from automatically adding
>ENDBR instructions to functions' prologues, which would have been
>automatically added by -fcf-protection=branch. Although this works
>correctly, missing ENDBR instructions where they are actually needed
>could lead to broken binaries, which would fail only in running time.
```
I think the purpose of "-mmanual-endbr" should be "Supplementary Way" for the 
cases which the CET can't correctly insert endbr in automatic way.
Here (in if (needsPrologueENDBR(MF, M)) ) the automatic way will insert the 
endbr. So I think the job for "-mmanual-endbr" should be done in parallel with 
the old condition. Some like:
```
if (ManualENDBR ){
  do something
}else { // automatic
  if (needsPrologueENDBR(MF, M)) {insert endbr}
 }
}
```


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[PATCH] D124067: [x86] Support 3 builtin functions for 32-bits targets

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added a comment.

close with clang format at
 commit 6454ff35e0e7b0c0762c640031aa6c2b5d1f16ec 

 [Clang Format] emmintrin.h smmintrin.h (NFC)


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[PATCH] D124067: [x86] Support 3 builtin functions for 32-bits targets

[Xiang Zhang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGafa536e33e10: [x86] Support 3 builtin functions for 32-bits 
mode (authored by xiangzhangllvm).
Herald added a project: clang.

Changed prior to commit:
  https://reviews.llvm.org/D124067?vs=424113=424363#toc

Repository:
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Files:
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Basic/BuiltinsX86_64.def
  clang/lib/Headers/emmintrin.h
  clang/lib/Headers/smmintrin.h
  clang/test/CodeGen/X86/sse2-builtins.c
  clang/test/CodeGen/X86/sse41-builtins.c

Index: clang/test/CodeGen/X86/sse41-builtins.c
===
--- clang/test/CodeGen/X86/sse41-builtins.c
+++ clang/test/CodeGen/X86/sse41-builtins.c
@@ -184,13 +184,11 @@
   return _mm_extract_epi32(x, 1);
 }
 
-#ifdef __x86_64__
 long long test_mm_extract_epi64(__m128i x) {
-  // X64-LABEL: test_mm_extract_epi64
-  // X64: extractelement <2 x i64> %{{.*}}, {{i32|i64}} 1
+  // CHECK-LABEL: test_mm_extract_epi64
+  // CHECK: extractelement <2 x i64> %{{.*}}, {{i32|i64}} 1
   return _mm_extract_epi64(x, 1);
 }
-#endif
 
 int test_mm_extract_ps(__m128 x) {
   // CHECK-LABEL: test_mm_extract_ps
Index: clang/test/CodeGen/X86/sse2-builtins.c
===
--- clang/test/CodeGen/X86/sse2-builtins.c
+++ clang/test/CodeGen/X86/sse2-builtins.c
@@ -510,13 +510,11 @@
   return _mm_cvtsi128_si32(A);
 }
 
-#ifdef __x86_64__
 long long test_mm_cvtsi128_si64(__m128i A) {
-  // X64-LABEL: test_mm_cvtsi128_si64
-  // X64: extractelement <2 x i64> %{{.*}}, i32 0
+  // CHECK-LABEL: test_mm_cvtsi128_si64
+  // CHECK: extractelement <2 x i64> %{{.*}}, i32 0
   return _mm_cvtsi128_si64(A);
 }
-#endif
 
 __m128d test_mm_cvtsi32_sd(__m128d A, int B) {
   // CHECK-LABEL: test_mm_cvtsi32_sd
@@ -541,14 +539,14 @@
   // X64: insertelement <2 x double> %{{.*}}, double %{{.*}}, i32 0
   return _mm_cvtsi64_sd(A, B);
 }
+#endif
 
 __m128i test_mm_cvtsi64_si128(long long A) {
-  // X64-LABEL: test_mm_cvtsi64_si128
-  // X64: insertelement <2 x i64> undef, i64 %{{.*}}, i32 0
-  // X64: insertelement <2 x i64> %{{.*}}, i64 0, i32 1
+  // CHECK-LABEL: test_mm_cvtsi64_si128
+  // CHECK: insertelement <2 x i64> undef, i64 %{{.*}}, i32 0
+  // CHECK: insertelement <2 x i64> %{{.*}}, i64 0, i32 1
   return _mm_cvtsi64_si128(A);
 }
-#endif
 
 __m128d test_mm_cvtss_sd(__m128d A, __m128 B) {
   // CHECK-LABEL: test_mm_cvtss_sd
Index: clang/lib/Headers/smmintrin.h
===
--- clang/lib/Headers/smmintrin.h
+++ clang/lib/Headers/smmintrin.h
@@ -1054,7 +1054,6 @@
 #define _mm_extract_epi32(X, N)\
   ((int)__builtin_ia32_vec_ext_v4si((__v4si)(__m128i)(X), (int)(N)))
 
-#ifdef __x86_64__
 /// Extracts a 64-bit element from the 128-bit integer vector of
 ///[2 x i64], using the immediate value parameter \a N as a selector.
 ///
@@ -1064,7 +1063,8 @@
 /// long long _mm_extract_epi64(__m128i X, const int N);
 /// \endcode
 ///
-/// This intrinsic corresponds to the  VPEXTRQ / PEXTRQ  instruction.
+/// This intrinsic corresponds to the  VPEXTRQ / PEXTRQ  instruction
+/// in 64-bit mode.
 ///
 /// \param X
 ///A 128-bit integer vector.
@@ -1076,7 +1076,6 @@
 /// \returns  A 64-bit integer.
 #define _mm_extract_epi64(X, N)\
   ((long long)__builtin_ia32_vec_ext_v2di((__v2di)(__m128i)(X), (int)(N)))
-#endif /* __x86_64 */
 
 /* SSE4 128-bit Packed Integer Comparisons.  */
 /// Tests whether the specified bits in a 128-bit integer vector are all
Index: clang/lib/Headers/emmintrin.h
===
--- clang/lib/Headers/emmintrin.h
+++ clang/lib/Headers/emmintrin.h
@@ -3284,13 +3284,13 @@
   return __extension__(__m128i)(__v4si){__a, 0, 0, 0};
 }
 
-#ifdef __x86_64__
 /// Returns a vector of [2 x i64] where the lower element is the input
 ///operand and the upper element is zero.
 ///
 /// \headerfile 
 ///
-/// This intrinsic corresponds to the  VMOVQ / MOVQ  instruction.
+/// This intrinsic corresponds to the  VMOVQ / MOVQ  instruction
+/// in 64-bit mode.
 ///
 /// \param __a
 ///A 64-bit signed integer operand containing the value to be converted.
@@ -3298,7 +3298,6 @@
 static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_cvtsi64_si128(long long __a) {
   return __extension__(__m128i)(__v2di){__a, 0};
 }
-#endif
 
 /// Moves the least significant 32 bits of a vector of [4 x i32] to a
 ///32-bit signed integer value.
@@ -3316,7 +3315,6 @@
   return __b[0];
 }
 
-#ifdef __x86_64__
 /// Moves the least significant 64 bits of a vector of [2 x i64] to a
 ///64-bit signed integer value.
 ///
@@ -3331,7 

[PATCH] D124067: [x86] Support 3 builtin functions for 32-bits targets

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm marked an inline comment as done.
xiangzhangllvm added inline comments.



Comment at: clang/lib/Headers/emmintrin.h:3476
+/// This intrinsic corresponds to the  VMOVQ / MOVQ  instruction
+/// in 64 bits.
 ///

RKSimon wrote:
> xiangzhangllvm wrote:
> > craig.topper wrote:
> > > craig.topper wrote:
> > > > 64 bits -> 64-bit mode
> > > 64 bits -> 64-bit
> > Thank you!
> 64-bit (missing hypen)
Let me directly add it when push.
And I see a test failed duo to clang-format. I'll commit a patch only do clang 
format for this 2 tests. (NFC)
Thank you !


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[PATCH] D124067: [x86] Support 3 builtin functions for 32-bits targets

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm marked an inline comment as done.
xiangzhangllvm added inline comments.



Comment at: clang/lib/Headers/emmintrin.h:3476
+/// This intrinsic corresponds to the  VMOVQ / MOVQ  instruction
+/// in 64 bits.
 ///

craig.topper wrote:
> craig.topper wrote:
> > 64 bits -> 64-bit mode
> 64 bits -> 64-bit
Thank you!


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[PATCH] D124067: [x86] Support 3 builtin functions for 32-bits targets

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm updated this revision to Diff 424113.

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Files:
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Basic/BuiltinsX86_64.def
  clang/lib/Headers/emmintrin.h
  clang/lib/Headers/smmintrin.h
  clang/test/CodeGen/X86/sse2-builtins.c
  clang/test/CodeGen/X86/sse41-builtins.c

Index: clang/test/CodeGen/X86/sse41-builtins.c
===
--- clang/test/CodeGen/X86/sse41-builtins.c
+++ clang/test/CodeGen/X86/sse41-builtins.c
@@ -184,13 +184,11 @@
   return _mm_extract_epi32(x, 1);
 }
 
-#ifdef __x86_64__
 long long test_mm_extract_epi64(__m128i x) {
-  // X64-LABEL: test_mm_extract_epi64
-  // X64: extractelement <2 x i64> %{{.*}}, {{i32|i64}} 1
+  // CHECK-LABEL: test_mm_extract_epi64
+  // CHECK: extractelement <2 x i64> %{{.*}}, {{i32|i64}} 1
   return _mm_extract_epi64(x, 1);
 }
-#endif
 
 int test_mm_extract_ps(__m128 x) {
   // CHECK-LABEL: test_mm_extract_ps
Index: clang/test/CodeGen/X86/sse2-builtins.c
===
--- clang/test/CodeGen/X86/sse2-builtins.c
+++ clang/test/CodeGen/X86/sse2-builtins.c
@@ -510,13 +510,11 @@
   return _mm_cvtsi128_si32(A);
 }
 
-#ifdef __x86_64__
 long long test_mm_cvtsi128_si64(__m128i A) {
-  // X64-LABEL: test_mm_cvtsi128_si64
-  // X64: extractelement <2 x i64> %{{.*}}, i32 0
+  // CHECK-LABEL: test_mm_cvtsi128_si64
+  // CHECK: extractelement <2 x i64> %{{.*}}, i32 0
   return _mm_cvtsi128_si64(A);
 }
-#endif
 
 __m128d test_mm_cvtsi32_sd(__m128d A, int B) {
   // CHECK-LABEL: test_mm_cvtsi32_sd
@@ -541,14 +539,14 @@
   // X64: insertelement <2 x double> %{{.*}}, double %{{.*}}, i32 0
   return _mm_cvtsi64_sd(A, B);
 }
+#endif
 
 __m128i test_mm_cvtsi64_si128(long long A) {
-  // X64-LABEL: test_mm_cvtsi64_si128
-  // X64: insertelement <2 x i64> undef, i64 %{{.*}}, i32 0
-  // X64: insertelement <2 x i64> %{{.*}}, i64 0, i32 1
+  // CHECK-LABEL: test_mm_cvtsi64_si128
+  // CHECK: insertelement <2 x i64> undef, i64 %{{.*}}, i32 0
+  // CHECK: insertelement <2 x i64> %{{.*}}, i64 0, i32 1
   return _mm_cvtsi64_si128(A);
 }
-#endif
 
 __m128d test_mm_cvtss_sd(__m128d A, __m128 B) {
   // CHECK-LABEL: test_mm_cvtss_sd
Index: clang/lib/Headers/smmintrin.h
===
--- clang/lib/Headers/smmintrin.h
+++ clang/lib/Headers/smmintrin.h
@@ -1061,7 +1061,6 @@
 #define _mm_extract_epi32(X, N) \
   ((int)__builtin_ia32_vec_ext_v4si((__v4si)(__m128i)(X), (int)(N)))
 
-#ifdef __x86_64__
 /// Extracts a 64-bit element from the 128-bit integer vector of
 ///[2 x i64], using the immediate value parameter \a N as a selector.
 ///
@@ -1071,7 +1070,8 @@
 /// long long _mm_extract_epi64(__m128i X, const int N);
 /// \endcode
 ///
-/// This intrinsic corresponds to the  VPEXTRQ / PEXTRQ  instruction.
+/// This intrinsic corresponds to the  VPEXTRQ / PEXTRQ  instruction
+/// in 64-bit mode.
 ///
 /// \param X
 ///A 128-bit integer vector.
@@ -1083,7 +1083,6 @@
 /// \returns  A 64-bit integer.
 #define _mm_extract_epi64(X, N) \
   ((long long)__builtin_ia32_vec_ext_v2di((__v2di)(__m128i)(X), (int)(N)))
-#endif /* __x86_64 */
 
 /* SSE4 128-bit Packed Integer Comparisons.  */
 /// Tests whether the specified bits in a 128-bit integer vector are all
Index: clang/lib/Headers/emmintrin.h
===
--- clang/lib/Headers/emmintrin.h
+++ clang/lib/Headers/emmintrin.h
@@ -3467,13 +3467,13 @@
   return __extension__ (__m128i)(__v4si){ __a, 0, 0, 0 };
 }
 
-#ifdef __x86_64__
 /// Returns a vector of [2 x i64] where the lower element is the input
 ///operand and the upper element is zero.
 ///
 /// \headerfile 
 ///
-/// This intrinsic corresponds to the  VMOVQ / MOVQ  instruction.
+/// This intrinsic corresponds to the  VMOVQ / MOVQ  instruction
+/// in 64 bit mode.
 ///
 /// \param __a
 ///A 64-bit signed integer operand containing the value to be converted.
@@ -3483,7 +3483,6 @@
 {
   return __extension__ (__m128i)(__v2di){ __a, 0 };
 }
-#endif
 
 /// Moves the least significant 32 bits of a vector of [4 x i32] to a
 ///32-bit signed integer value.
@@ -3503,7 +3502,6 @@
   return __b[0];
 }
 
-#ifdef __x86_64__
 /// Moves the least significant 64 bits of a vector of [2 x i64] to a
 ///64-bit signed integer value.
 ///
@@ -3520,7 +3518,6 @@
 {
   return __a[0];
 }
-#endif
 
 /// Moves packed integer values from an aligned 128-bit memory location
 ///to elements in a 128-bit integer vector.
Index: clang/include/clang/Basic/BuiltinsX86_64.def
===
--- clang/include/clang/Basic/BuiltinsX86_64.def
+++ clang/include/clang/Basic/BuiltinsX86_64.def
@@ -42,7 +42,6 @@
 TARGET_BUILTIN(__builtin_ia32_cvtsd2si64, "OiV2d", "ncV:128:", "sse2")
 

[PATCH] D124067: [x86] Support 3 builtin functions for 32-bits targets

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm updated this revision to Diff 424070.

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Files:
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Basic/BuiltinsX86_64.def
  clang/lib/Headers/emmintrin.h
  clang/lib/Headers/smmintrin.h
  clang/test/CodeGen/X86/sse2-builtins.c
  clang/test/CodeGen/X86/sse41-builtins.c

Index: clang/test/CodeGen/X86/sse41-builtins.c
===
--- clang/test/CodeGen/X86/sse41-builtins.c
+++ clang/test/CodeGen/X86/sse41-builtins.c
@@ -184,13 +184,11 @@
   return _mm_extract_epi32(x, 1);
 }
 
-#ifdef __x86_64__
 long long test_mm_extract_epi64(__m128i x) {
-  // X64-LABEL: test_mm_extract_epi64
-  // X64: extractelement <2 x i64> %{{.*}}, {{i32|i64}} 1
+  // CHECK-LABEL: test_mm_extract_epi64
+  // CHECK: extractelement <2 x i64> %{{.*}}, {{i32|i64}} 1
   return _mm_extract_epi64(x, 1);
 }
-#endif
 
 int test_mm_extract_ps(__m128 x) {
   // CHECK-LABEL: test_mm_extract_ps
Index: clang/test/CodeGen/X86/sse2-builtins.c
===
--- clang/test/CodeGen/X86/sse2-builtins.c
+++ clang/test/CodeGen/X86/sse2-builtins.c
@@ -510,13 +510,11 @@
   return _mm_cvtsi128_si32(A);
 }
 
-#ifdef __x86_64__
 long long test_mm_cvtsi128_si64(__m128i A) {
-  // X64-LABEL: test_mm_cvtsi128_si64
-  // X64: extractelement <2 x i64> %{{.*}}, i32 0
+  // CHECK-LABEL: test_mm_cvtsi128_si64
+  // CHECK: extractelement <2 x i64> %{{.*}}, i32 0
   return _mm_cvtsi128_si64(A);
 }
-#endif
 
 __m128d test_mm_cvtsi32_sd(__m128d A, int B) {
   // CHECK-LABEL: test_mm_cvtsi32_sd
@@ -541,14 +539,14 @@
   // X64: insertelement <2 x double> %{{.*}}, double %{{.*}}, i32 0
   return _mm_cvtsi64_sd(A, B);
 }
+#endif
 
 __m128i test_mm_cvtsi64_si128(long long A) {
-  // X64-LABEL: test_mm_cvtsi64_si128
-  // X64: insertelement <2 x i64> undef, i64 %{{.*}}, i32 0
-  // X64: insertelement <2 x i64> %{{.*}}, i64 0, i32 1
+  // CHECK-LABEL: test_mm_cvtsi64_si128
+  // CHECK: insertelement <2 x i64> undef, i64 %{{.*}}, i32 0
+  // CHECK: insertelement <2 x i64> %{{.*}}, i64 0, i32 1
   return _mm_cvtsi64_si128(A);
 }
-#endif
 
 __m128d test_mm_cvtss_sd(__m128d A, __m128 B) {
   // CHECK-LABEL: test_mm_cvtss_sd
Index: clang/lib/Headers/smmintrin.h
===
--- clang/lib/Headers/smmintrin.h
+++ clang/lib/Headers/smmintrin.h
@@ -1061,7 +1061,6 @@
 #define _mm_extract_epi32(X, N) \
   ((int)__builtin_ia32_vec_ext_v4si((__v4si)(__m128i)(X), (int)(N)))
 
-#ifdef __x86_64__
 /// Extracts a 64-bit element from the 128-bit integer vector of
 ///[2 x i64], using the immediate value parameter \a N as a selector.
 ///
@@ -1071,7 +1070,8 @@
 /// long long _mm_extract_epi64(__m128i X, const int N);
 /// \endcode
 ///
-/// This intrinsic corresponds to the  VPEXTRQ / PEXTRQ  instruction.
+/// This intrinsic corresponds to the  VPEXTRQ / PEXTRQ  instruction
+/// in 64-bit mode.
 ///
 /// \param X
 ///A 128-bit integer vector.
@@ -1083,7 +1083,6 @@
 /// \returns  A 64-bit integer.
 #define _mm_extract_epi64(X, N) \
   ((long long)__builtin_ia32_vec_ext_v2di((__v2di)(__m128i)(X), (int)(N)))
-#endif /* __x86_64 */
 
 /* SSE4 128-bit Packed Integer Comparisons.  */
 /// Tests whether the specified bits in a 128-bit integer vector are all
Index: clang/lib/Headers/emmintrin.h
===
--- clang/lib/Headers/emmintrin.h
+++ clang/lib/Headers/emmintrin.h
@@ -3467,13 +3467,13 @@
   return __extension__ (__m128i)(__v4si){ __a, 0, 0, 0 };
 }
 
-#ifdef __x86_64__
 /// Returns a vector of [2 x i64] where the lower element is the input
 ///operand and the upper element is zero.
 ///
 /// \headerfile 
 ///
-/// This intrinsic corresponds to the  VMOVQ / MOVQ  instruction.
+/// This intrinsic corresponds to the  VMOVQ / MOVQ  instruction
+/// in 64 bits mode.
 ///
 /// \param __a
 ///A 64-bit signed integer operand containing the value to be converted.
@@ -3483,7 +3483,6 @@
 {
   return __extension__ (__m128i)(__v2di){ __a, 0 };
 }
-#endif
 
 /// Moves the least significant 32 bits of a vector of [4 x i32] to a
 ///32-bit signed integer value.
@@ -3503,7 +3502,6 @@
   return __b[0];
 }
 
-#ifdef __x86_64__
 /// Moves the least significant 64 bits of a vector of [2 x i64] to a
 ///64-bit signed integer value.
 ///
@@ -3520,7 +3518,6 @@
 {
   return __a[0];
 }
-#endif
 
 /// Moves packed integer values from an aligned 128-bit memory location
 ///to elements in a 128-bit integer vector.
Index: clang/include/clang/Basic/BuiltinsX86_64.def
===
--- clang/include/clang/Basic/BuiltinsX86_64.def
+++ clang/include/clang/Basic/BuiltinsX86_64.def
@@ -42,7 +42,6 @@
 TARGET_BUILTIN(__builtin_ia32_cvtsd2si64, "OiV2d", "ncV:128:", "sse2")
 

[PATCH] D124067: [x86] Support 3 builtin functions for 32-bits targets

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm marked an inline comment as done.
xiangzhangllvm added inline comments.



Comment at: clang/test/CodeGen/X86/sse2-builtins.c:547
   // X64: insertelement <2 x i64> undef, i64 %{{.*}}, i32 0
   // X64: insertelement <2 x i64> %{{.*}}, i64 0, i32 1
   return _mm_cvtsi64_si128(A);

Sorry I need to update it to "CHECK", let me update.


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[PATCH] D124067: [x86] Support 3 builtin functions for 32-bits targets

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm updated this revision to Diff 424067.

CHANGES SINCE LAST ACTION
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Files:
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Basic/BuiltinsX86_64.def
  clang/lib/Headers/emmintrin.h
  clang/lib/Headers/smmintrin.h
  clang/test/CodeGen/X86/sse2-builtins.c
  clang/test/CodeGen/X86/sse41-builtins.c

Index: clang/test/CodeGen/X86/sse41-builtins.c
===
--- clang/test/CodeGen/X86/sse41-builtins.c
+++ clang/test/CodeGen/X86/sse41-builtins.c
@@ -184,13 +184,11 @@
   return _mm_extract_epi32(x, 1);
 }
 
-#ifdef __x86_64__
 long long test_mm_extract_epi64(__m128i x) {
   // X64-LABEL: test_mm_extract_epi64
   // X64: extractelement <2 x i64> %{{.*}}, {{i32|i64}} 1
   return _mm_extract_epi64(x, 1);
 }
-#endif
 
 int test_mm_extract_ps(__m128 x) {
   // CHECK-LABEL: test_mm_extract_ps
Index: clang/test/CodeGen/X86/sse2-builtins.c
===
--- clang/test/CodeGen/X86/sse2-builtins.c
+++ clang/test/CodeGen/X86/sse2-builtins.c
@@ -510,13 +510,11 @@
   return _mm_cvtsi128_si32(A);
 }
 
-#ifdef __x86_64__
 long long test_mm_cvtsi128_si64(__m128i A) {
   // X64-LABEL: test_mm_cvtsi128_si64
   // X64: extractelement <2 x i64> %{{.*}}, i32 0
   return _mm_cvtsi128_si64(A);
 }
-#endif
 
 __m128d test_mm_cvtsi32_sd(__m128d A, int B) {
   // CHECK-LABEL: test_mm_cvtsi32_sd
@@ -541,6 +539,7 @@
   // X64: insertelement <2 x double> %{{.*}}, double %{{.*}}, i32 0
   return _mm_cvtsi64_sd(A, B);
 }
+#endif
 
 __m128i test_mm_cvtsi64_si128(long long A) {
   // X64-LABEL: test_mm_cvtsi64_si128
@@ -548,7 +547,6 @@
   // X64: insertelement <2 x i64> %{{.*}}, i64 0, i32 1
   return _mm_cvtsi64_si128(A);
 }
-#endif
 
 __m128d test_mm_cvtss_sd(__m128d A, __m128 B) {
   // CHECK-LABEL: test_mm_cvtss_sd
Index: clang/lib/Headers/smmintrin.h
===
--- clang/lib/Headers/smmintrin.h
+++ clang/lib/Headers/smmintrin.h
@@ -1061,7 +1061,6 @@
 #define _mm_extract_epi32(X, N) \
   ((int)__builtin_ia32_vec_ext_v4si((__v4si)(__m128i)(X), (int)(N)))
 
-#ifdef __x86_64__
 /// Extracts a 64-bit element from the 128-bit integer vector of
 ///[2 x i64], using the immediate value parameter \a N as a selector.
 ///
@@ -1071,7 +1070,8 @@
 /// long long _mm_extract_epi64(__m128i X, const int N);
 /// \endcode
 ///
-/// This intrinsic corresponds to the  VPEXTRQ / PEXTRQ  instruction.
+/// This intrinsic corresponds to the  VPEXTRQ / PEXTRQ  instruction
+/// in 64-bit mode.
 ///
 /// \param X
 ///A 128-bit integer vector.
@@ -1083,7 +1083,6 @@
 /// \returns  A 64-bit integer.
 #define _mm_extract_epi64(X, N) \
   ((long long)__builtin_ia32_vec_ext_v2di((__v2di)(__m128i)(X), (int)(N)))
-#endif /* __x86_64 */
 
 /* SSE4 128-bit Packed Integer Comparisons.  */
 /// Tests whether the specified bits in a 128-bit integer vector are all
Index: clang/lib/Headers/emmintrin.h
===
--- clang/lib/Headers/emmintrin.h
+++ clang/lib/Headers/emmintrin.h
@@ -3467,13 +3467,13 @@
   return __extension__ (__m128i)(__v4si){ __a, 0, 0, 0 };
 }
 
-#ifdef __x86_64__
 /// Returns a vector of [2 x i64] where the lower element is the input
 ///operand and the upper element is zero.
 ///
 /// \headerfile 
 ///
-/// This intrinsic corresponds to the  VMOVQ / MOVQ  instruction.
+/// This intrinsic corresponds to the  VMOVQ / MOVQ  instruction
+/// in 64 bits mode.
 ///
 /// \param __a
 ///A 64-bit signed integer operand containing the value to be converted.
@@ -3483,7 +3483,6 @@
 {
   return __extension__ (__m128i)(__v2di){ __a, 0 };
 }
-#endif
 
 /// Moves the least significant 32 bits of a vector of [4 x i32] to a
 ///32-bit signed integer value.
@@ -3503,7 +3502,6 @@
   return __b[0];
 }
 
-#ifdef __x86_64__
 /// Moves the least significant 64 bits of a vector of [2 x i64] to a
 ///64-bit signed integer value.
 ///
@@ -3520,7 +3518,6 @@
 {
   return __a[0];
 }
-#endif
 
 /// Moves packed integer values from an aligned 128-bit memory location
 ///to elements in a 128-bit integer vector.
Index: clang/include/clang/Basic/BuiltinsX86_64.def
===
--- clang/include/clang/Basic/BuiltinsX86_64.def
+++ clang/include/clang/Basic/BuiltinsX86_64.def
@@ -42,7 +42,6 @@
 TARGET_BUILTIN(__builtin_ia32_cvtsd2si64, "OiV2d", "ncV:128:", "sse2")
 TARGET_BUILTIN(__builtin_ia32_cvttsd2si64, "OiV2d", "ncV:128:", "sse2")
 TARGET_BUILTIN(__builtin_ia32_movnti64, "vOi*Oi", "n", "sse2")
-TARGET_BUILTIN(__builtin_ia32_vec_ext_v2di, "OiV2OiIi", "ncV:128:", "sse2")
 TARGET_BUILTIN(__builtin_ia32_vec_set_v2di, "V2OiV2OiOiIi", "ncV:128:", "sse4.1")
 TARGET_BUILTIN(__builtin_ia32_crc32di, "UOiUOiUOi", "nc", "crc32")
 TARGET_BUILTIN(__builtin_ia32_vec_ext_v4di, "OiV4OiIi", "ncV:256:", 

[PATCH] D124067: [x86] Support 3 builtin functions for 32-bits targets

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added a comment.

In D124067#3461551 , @RKSimon wrote:

> OK - SSE2/SSE41 now have i386 coverage - please can you rebase and update the 
> checks to use CHECK/X64/X86 ?

Hi @RKSimon, I very appreciate your help to update the test! You are very kind! 
In fact, I should do it before this patch. Thank you very much!


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[PATCH] D124067: [x86] Support 3 builtin functions for 32-bits targets

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added inline comments.



Comment at: clang/test/CodeGen/X86/sse2-builtins.c:560
   // CHECK: insertelement <2 x i64> %{{.*}}, i64 0, i32 1
+  // X86-LABEL: test_mm_cvtsi64_si128
+  // X86: insertelement <2 x i64> undef, i64 %{{.*}}, i32 0

LiuChen3 wrote:
> xiangzhangllvm wrote:
> > xiangzhangllvm wrote:
> > > RKSimon wrote:
> > > > xiangzhangllvm wrote:
> > > > > craig.topper wrote:
> > > > > > Do we need the X86 prefix because of the x86-64 #ifdefs? Or are 
> > > > > > there other differences?
> > > > > > 
> > > > > > If it's just the x86-64, can we add -check-prefixes=CHECK,X64 to 
> > > > > > the x86-64 run lines and use X64 for the x86-64 only functions. 
> > > > > > That way CHECK can be used for all the common tests.
> > > > > Before I change the test, it only build with "-triple=x86_64", So all 
> > > > > the CHECK should be X64 prefix. 
> > > > > So I add X86 prefix to just let "RUN ... -triple=i386" only check the 
> > > > > updated 3 builtins. (let the change be small).
> > > > > 
> > > > I'd much prefer we have complete test check prefix coverage for every 
> > > > RUN - and tbh we should be properly testing 32-bit on every x86 
> > > > intrinsic test file.
> > > Yes, testing 32-bit on every x86 intrinsic test file is make sense. I 
> > > also confuse why this test not testing the 32-bit mode before. I think it 
> > > is "defect" for the test.
> > > But how can I well update the test by on checking the 3 updated 
> > > intrinsics. Because it is strange to update the other intrinsics checking 
> > > when I only update 3 intrinsics in clang.
> > Hi @craig.topper , @RKSimon, if the 32 and 64 has common prefix "CHECK", it 
> > means the line 4 (32 bits) need to check all other intrinsics. That means I 
> > need to updated a lot check string for the 32 bit mode. 
> > What's more, currently we have no tools to auto generate the checking code 
> > for clang test. 
> > 
> Actually we have 'update_cc_test_checks.py', but little use.
I do "./llvm/utils/update_cc_test_checks.py 
clang/test/CodeGen/X86/sse41-builtins.c"
It generate nothing.


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[PATCH] D124067: [x86] Support 3 builtin functions for 32-bits targets

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added inline comments.



Comment at: clang/test/CodeGen/X86/sse2-builtins.c:560
   // CHECK: insertelement <2 x i64> %{{.*}}, i64 0, i32 1
+  // X86-LABEL: test_mm_cvtsi64_si128
+  // X86: insertelement <2 x i64> undef, i64 %{{.*}}, i32 0

xiangzhangllvm wrote:
> RKSimon wrote:
> > xiangzhangllvm wrote:
> > > craig.topper wrote:
> > > > Do we need the X86 prefix because of the x86-64 #ifdefs? Or are there 
> > > > other differences?
> > > > 
> > > > If it's just the x86-64, can we add -check-prefixes=CHECK,X64 to the 
> > > > x86-64 run lines and use X64 for the x86-64 only functions. That way 
> > > > CHECK can be used for all the common tests.
> > > Before I change the test, it only build with "-triple=x86_64", So all the 
> > > CHECK should be X64 prefix. 
> > > So I add X86 prefix to just let "RUN ... -triple=i386" only check the 
> > > updated 3 builtins. (let the change be small).
> > > 
> > I'd much prefer we have complete test check prefix coverage for every RUN - 
> > and tbh we should be properly testing 32-bit on every x86 intrinsic test 
> > file.
> Yes, testing 32-bit on every x86 intrinsic test file is make sense. I also 
> confuse why this test not testing the 32-bit mode before. I think it is 
> "defect" for the test.
> But how can I well update the test by on checking the 3 updated intrinsics. 
> Because it is strange to update the other intrinsics checking when I only 
> update 3 intrinsics in clang.
Hi @craig.topper , @RKSimon, if the 32 and 64 has common prefix "CHECK", it 
means the line 4 (32 bits) need to check all other intrinsics. That means I 
need to updated a lot check string for the 32 bit mode. 
What's more, currently we have no tools to auto generate the checking code for 
clang test. 



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[PATCH] D124067: [x86] Support 3 builtin functions for 32-bits targets

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added inline comments.



Comment at: clang/test/CodeGen/X86/sse2-builtins.c:560
   // CHECK: insertelement <2 x i64> %{{.*}}, i64 0, i32 1
+  // X86-LABEL: test_mm_cvtsi64_si128
+  // X86: insertelement <2 x i64> undef, i64 %{{.*}}, i32 0

RKSimon wrote:
> xiangzhangllvm wrote:
> > craig.topper wrote:
> > > Do we need the X86 prefix because of the x86-64 #ifdefs? Or are there 
> > > other differences?
> > > 
> > > If it's just the x86-64, can we add -check-prefixes=CHECK,X64 to the 
> > > x86-64 run lines and use X64 for the x86-64 only functions. That way 
> > > CHECK can be used for all the common tests.
> > Before I change the test, it only build with "-triple=x86_64", So all the 
> > CHECK should be X64 prefix. 
> > So I add X86 prefix to just let "RUN ... -triple=i386" only check the 
> > updated 3 builtins. (let the change be small).
> > 
> I'd much prefer we have complete test check prefix coverage for every RUN - 
> and tbh we should be properly testing 32-bit on every x86 intrinsic test file.
Yes, testing 32-bit on every x86 intrinsic test file is make sense. I also 
confuse why this test not testing the 32-bit mode before. I think it is 
"defect" for the test.
But how can I well update the test by on checking the 3 updated intrinsics. 
Because it is strange to update the other intrinsics checking when I only 
update 3 intrinsics in clang.


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[PATCH] D122567: [X86][AMX] enable amx cast intrinsics in FE.

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm accepted this revision.
xiangzhangllvm added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D122567: [X86][AMX] enable amx cast intrinsics in FE.

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:5413-5415
+if (PTy->isX86_AMXTy())
+  ArgValue = 
Builder.CreateIntrinsic(Intrinsic::x86_cast_vector_to_tile,
+ {ArgValue->getType()}, 
{ArgValue});

LuoYuanke wrote:
> xiangzhangllvm wrote:
> > Can we fold it in CreateBitCast(ArgValue, PTy) function ?
> I don't think so. We have amx specific cast to avoid some unexpected 
> optimization for bitcast.
That is not big issue. 
If nobody objected, I'll accept it soon.


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[PATCH] D122567: [X86][AMX] enable amx cast intrinsics in FE.

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:5413-5415
+if (PTy->isX86_AMXTy())
+  ArgValue = 
Builder.CreateIntrinsic(Intrinsic::x86_cast_vector_to_tile,
+ {ArgValue->getType()}, 
{ArgValue});

Can we fold it in CreateBitCast(ArgValue, PTy) function ?


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[PATCH] D120887: The [2/3] Fix mangle problem when variable used in inline asm （Add modifier P for ARR[BaseReg+IndexReg+..]）

[Xiang Zhang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG287dad13abba: [InlineAsm] Fix mangle problem when global 
variable used in inline asm (authored by xiangzhangllvm).
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Files:
  clang/test/CodeGen/ms-inline-asm-variables.c
  llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h
  llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
  llvm/lib/MC/MCParser/AsmParser.cpp
  llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
  llvm/lib/Target/X86/AsmParser/X86Operand.h

Index: llvm/lib/Target/X86/AsmParser/X86Operand.h
===
--- llvm/lib/Target/X86/AsmParser/X86Operand.h
+++ llvm/lib/Target/X86/AsmParser/X86Operand.h
@@ -68,6 +68,10 @@
 /// If the memory operand is unsized and there are multiple instruction
 /// matches, prefer the one with this size.
 unsigned FrontendSize;
+
+/// This used for inline asm which may specify base reg and index reg for
+/// MemOp. e.g. ARR[eax + ecx*4], so no extra reg can be used for MemOp.
+bool UseUpRegs;
   };
 
   union {
@@ -380,6 +384,10 @@
 return isAbsMem() && Mem.ModeSize == 16;
   }
 
+  bool isMemUseUpRegs() const {
+return Mem.UseUpRegs;
+  }
+
   bool isSrcIdx() const {
 return !getMemIndexReg() && getMemScale() == 1 &&
   (getMemBaseReg() == X86::RSI || getMemBaseReg() == X86::ESI ||
@@ -665,7 +673,8 @@
   static std::unique_ptr
   CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc,
 unsigned Size = 0, StringRef SymName = StringRef(),
-void *OpDecl = nullptr, unsigned FrontendSize = 0) {
+void *OpDecl = nullptr, unsigned FrontendSize = 0,
+bool UseUpRegs = false) {
 auto Res = std::make_unique(Memory, StartLoc, EndLoc);
 Res->Mem.SegReg   = 0;
 Res->Mem.Disp = Disp;
@@ -676,6 +685,7 @@
 Res->Mem.Size = Size;
 Res->Mem.ModeSize = ModeSize;
 Res->Mem.FrontendSize = FrontendSize;
+Res->Mem.UseUpRegs = UseUpRegs;
 Res->SymName  = SymName;
 Res->OpDecl   = OpDecl;
 Res->AddressOf= false;
@@ -689,7 +699,7 @@
 SMLoc EndLoc, unsigned Size = 0,
 unsigned DefaultBaseReg = X86::NoRegister,
 StringRef SymName = StringRef(), void *OpDecl = nullptr,
-unsigned FrontendSize = 0) {
+unsigned FrontendSize = 0, bool UseUpRegs = false) {
 // We should never just have a displacement, that should be parsed as an
 // absolute memory operand.
 assert((SegReg || BaseReg || IndexReg || DefaultBaseReg) &&
@@ -708,6 +718,7 @@
 Res->Mem.Size = Size;
 Res->Mem.ModeSize = ModeSize;
 Res->Mem.FrontendSize = FrontendSize;
+Res->Mem.UseUpRegs = UseUpRegs;
 Res->SymName  = SymName;
 Res->OpDecl   = OpDecl;
 Res->AddressOf= false;
Index: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
===
--- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1759,7 +1759,8 @@
   // registers in a mmory expression, and though unaccessible via rip/eip.
   if (IsGlobalLV && (BaseReg || IndexReg)) {
 Operands.push_back(X86Operand::CreateMem(getPointerWidth(), Disp, Start,
- End, Size, Identifier, Decl));
+ End, Size, Identifier, Decl, 0,
+ BaseReg && IndexReg));
 return false;
   }
   // Otherwise, we set the base register to a non-zero value
Index: llvm/lib/MC/MCParser/AsmParser.cpp
===
--- llvm/lib/MC/MCParser/AsmParser.cpp
+++ llvm/lib/MC/MCParser/AsmParser.cpp
@@ -6021,21 +6021,25 @@
   }
 
   bool isOutput = (i == 1) && Desc.mayStore();
+  bool Restricted = Operand.isMemUseUpRegs();
   SMLoc Start = SMLoc::getFromPointer(SymName.data());
   if (isOutput) {
 ++InputIdx;
 OutputDecls.push_back(OpDecl);
 OutputDeclsAddressOf.push_back(Operand.needAddressOf());
 OutputConstraints.push_back(("=" + Constraint).str());
-AsmStrRewrites.emplace_back(AOK_Output, Start, SymName.size());
+AsmStrRewrites.emplace_back(AOK_Output, Start, SymName.size(), 0,
+Restricted);
   } else {
 InputDecls.push_back(OpDecl);
 InputDeclsAddressOf.push_back(Operand.needAddressOf());
 InputConstraints.push_back(Constraint.str());
 if (Desc.OpInfo[i - 1].isBranchTarget())
-  AsmStrRewrites.emplace_back(AOK_CallInput, Start, 

[PATCH] D120886: [Inline asm][1/3] Fix mangle problem when variable used in inline asm (Revert 2 history bugfix patch)

[Xiang Zhang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG8a6b644c7923: [Inline asm] Fix mangle problem when variable 
used in inline asm. (authored by xiangzhangllvm).
Herald added subscribers: cfe-commits, StephenFan.
Herald added a project: clang.

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Files:
  clang/test/CodeGen/X86/ms_fmul.c
  clang/test/CodeGen/ms-inline-asm-static-variable.c
  clang/test/CodeGen/ms-inline-asm-variables.c
  llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h
  llvm/lib/MC/MCParser/AsmParser.cpp
  llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
  llvm/lib/Target/X86/AsmParser/X86Operand.h
  llvm/test/CodeGen/X86/ms-inline-asm-array.ll

Index: llvm/test/CodeGen/X86/ms-inline-asm-array.ll
===
--- llvm/test/CodeGen/X86/ms-inline-asm-array.ll
+++ llvm/test/CodeGen/X86/ms-inline-asm-array.ll
@@ -5,7 +5,7 @@
 ; CHECK: movl%edx, arr(,%rdx,4)
 define dso_local i32 @main() #0 {
 entry:
-  call void asm sideeffect inteldialect "mov dword ptr arr[rdx * $$4],edx", "=*m,~{dirflag},~{fpsr},~{flags}"([10 x i32]* elementtype([10 x i32]) @arr) #1, !srcloc !4
+  call void asm sideeffect inteldialect "mov dword ptr $0[rdx * $$4],edx", "=*m,~{dirflag},~{fpsr},~{flags}"([10 x i32]* elementtype([10 x i32]) @arr) #1, !srcloc !4
   ret i32 0
 }
 
Index: llvm/lib/Target/X86/AsmParser/X86Operand.h
===
--- llvm/lib/Target/X86/AsmParser/X86Operand.h
+++ llvm/lib/Target/X86/AsmParser/X86Operand.h
@@ -287,12 +287,6 @@
 
   bool isOffsetOfLocal() const override { return isImm() && Imm.LocalRef; }
 
-  bool isMemPlaceholder(const MCInstrDesc ) const override {
-// Only MS InlineAsm uses global variables with registers rather than
-// rip/eip.
-return isMem() && !Mem.DefaultBaseReg && Mem.FrontendSize;
-  }
-
   bool needAddressOf() const override { return AddressOf; }
 
   bool isMem() const override { return Kind == Memory; }
Index: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
===
--- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1759,8 +1759,7 @@
   // registers in a mmory expression, and though unaccessible via rip/eip.
   if (IsGlobalLV && (BaseReg || IndexReg)) {
 Operands.push_back(X86Operand::CreateMem(getPointerWidth(), Disp, Start,
- End, Size, Identifier, Decl,
- FrontendSize));
+ End, Size, Identifier, Decl));
 return false;
   }
   // Otherwise, we set the base register to a non-zero value
@@ -2552,6 +2551,8 @@
   StringRef ErrMsg;
   unsigned BaseReg = SM.getBaseReg();
   unsigned IndexReg = SM.getIndexReg();
+  if (IndexReg && BaseReg == X86::RIP)
+BaseReg = 0;
   unsigned Scale = SM.getScale();
   if (!PtrInOperand)
 Size = SM.getElementSize() << 3;
Index: llvm/lib/MC/MCParser/AsmParser.cpp
===
--- llvm/lib/MC/MCParser/AsmParser.cpp
+++ llvm/lib/MC/MCParser/AsmParser.cpp
@@ -6022,13 +6022,12 @@
 
   bool isOutput = (i == 1) && Desc.mayStore();
   SMLoc Start = SMLoc::getFromPointer(SymName.data());
-  int64_t Size = Operand.isMemPlaceholder(Desc) ? 0 : SymName.size();
   if (isOutput) {
 ++InputIdx;
 OutputDecls.push_back(OpDecl);
 OutputDeclsAddressOf.push_back(Operand.needAddressOf());
 OutputConstraints.push_back(("=" + Constraint).str());
-AsmStrRewrites.emplace_back(AOK_Output, Start, Size);
+AsmStrRewrites.emplace_back(AOK_Output, Start, SymName.size());
   } else {
 InputDecls.push_back(OpDecl);
 InputDeclsAddressOf.push_back(Operand.needAddressOf());
@@ -6036,7 +6035,7 @@
 if (Desc.OpInfo[i - 1].isBranchTarget())
   AsmStrRewrites.emplace_back(AOK_CallInput, Start, SymName.size());
 else
-  AsmStrRewrites.emplace_back(AOK_Input, Start, Size);
+  AsmStrRewrites.emplace_back(AOK_Input, Start, SymName.size());
   }
 }
 
@@ -6151,17 +6150,13 @@
   OS << Ctx.getAsmInfo()->getPrivateLabelPrefix() << AR.Label;
   break;
 case AOK_Input:
-  if (AR.Len)
-OS << '$' << InputIdx;
-  ++InputIdx;
+  OS << '$' << InputIdx++;
   break;
 case AOK_CallInput:
   OS << "${" << InputIdx++ << ":P}";
   break;
 case AOK_Output:
-  if (AR.Len)
-OS << '$' << OutputIdx;
-  ++OutputIdx;
+  OS << '$' << OutputIdx++;
   break;
 case AOK_SizeDirective:
   switch (AR.Val) {
Index: llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h

[PATCH] D118052: [X86] Fix CodeGen Module Flag for -mibt-seal

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added inline comments.



Comment at: clang/test/CodeGen/X86/x86-cf-protection.c:4
 // RUN: %clang -target i386-unknown-unknown -x c -E -dM -o - 
-fcf-protection=full %s   | FileCheck %s --check-prefix=FULL
+// RUN: %clang -target i386-unknown-unknown -o - -emit-llvm -S 
-fcf-protection=branch -mibt-seal -flto %s | FileCheck %s --check-prefix=IBTSEAL
 

joaomoreira wrote:
> pengfei wrote:
> > Is `-flto` is required?
> Yes, we can only suppress ENDBR if we are sure the given function is not 
> address taken in all other translation units.
Sorry, let me make sure here. what is the "translation units" here mean? Does 
it means another binary file (e.g. *.so , *.a)?
Using -flto seems here want more compile units (source files) to be one 
"translation units"?


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[PATCH] D113096: [X86][MS-InlineAsm] Add constraint *m for memory access w/ global var

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added inline comments.



Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:1759
   // It is widely common for MS InlineAsm to use a global variable and one/two
   // registers in a mmory expression, and though unaccessible via rip/eip.
   if (IsGlobalLV && (BaseReg || IndexReg)) {

skan wrote:
> xiangzhangllvm wrote:
> > Let me generally tell out my understand here, (If wrong PLS correct me)
> > Here from the comments we can see, the old code want to keep the origin 
> > symbol of global variable to let linker (relocation) handle it.  Here you 
> > describe it with a  pointer (with decl), it change to form of $ID <--> 
> > (decl), So which need constrain it with "*m". But if the pointer can not be 
> > access from BaseReg(Rip) + Index(Ip) how do you descript the pointer you 
> > generate out ?
> > 
> I think you may misunderstand this code.
> 
> This code handles the memory that can not be represented by Disp(RIP) b/c 
> there is already a BaseReg or IndexReg there.
> 
> Before this patch, the memory is represented like `arr[edx*4]` and there is 
> no identifer bound to it.  And after this patch, we bind the memory to 
> identifer arr.
Yes, that is why I mean t change ( arr[edx*4] ) to form of $ID <--> (decl). So 
what the problem if we let the old form ( arr[edx*4] ) being ?



Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:2554-2555
   unsigned IndexReg = SM.getIndexReg();
+  if (IndexReg && BaseReg == X86::RIP)
+BaseReg = 0;
   unsigned Scale = SM.getScale();

skan wrote:
> xiangzhangllvm wrote:
> > The change here looks too arbitrary. For global address it is ok to drop 
> > the base, it mainly fetch from offset. but if here not global variable?
> RIP and IndexReg can never be used together according to design of X86 
> instruction. The BaseReg is set to RIP b/c we add the constaint "*m" in the 
> MS-inline assembly. So we can drop it safely.
> 
> I acknowledge it's not the best way to do it, but it's simplest. Similary, 
> you can see the line 2560-2562.  RSP can never be a IndexReg, but we just 
> swap the BaseReg w/ IndexReg b/c it is not handled well in previous phases.
> 
> RIP and IndexReg can never be used together according to design of X86 
> instruction. 
Good answer!


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[PATCH] D113096: [X86][MS-InlineAsm] Add constraint *m for memory access w/ global var

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added inline comments.



Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:1759
   // It is widely common for MS InlineAsm to use a global variable and one/two
   // registers in a mmory expression, and though unaccessible via rip/eip.
   if (IsGlobalLV && (BaseReg || IndexReg)) {

Let me generally tell out my understand here, (If wrong PLS correct me)
Here from the comments we can see, the old code want to keep the origin symbol 
of global variable to let linker (relocation) handle it.  Here you describe it 
with a  pointer (with decl), it change to form of $ID <--> (decl), So which 
need constrain it with "*m". But if the pointer can not be access from 
BaseReg(Rip) + Index(Ip) how do you descript the pointer you generate out ?




Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:2554-2555
   unsigned IndexReg = SM.getIndexReg();
+  if (IndexReg && BaseReg == X86::RIP)
+BaseReg = 0;
   unsigned Scale = SM.getScale();

The change here looks too arbitrary. For global address it is ok to drop the 
base, it mainly fetch from offset. but if here not global variable?


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[PATCH] D109739: [X86][InlineAsm][Bugfix] Use mem size information (*word ptr) for "global variable + registers" memory expression in inline asm.

[Xiang Zhang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG1f1c71aeacc1: [X86][InlineAsm] Use mem size information 
(*word ptr) for global variable +… (authored by xiangzhangllvm).
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Files:
  clang/test/CodeGen/X86/ms_fmul.c
  llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp


Index: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
===
--- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1759,7 +1759,7 @@
   // registers in a mmory expression, and though unaccessible via rip/eip.
   if (IsGlobalLV && (BaseReg || IndexReg)) {
 Operands.push_back(
-X86Operand::CreateMem(getPointerWidth(), Disp, Start, End));
+X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size));
 return false;
   }
   // Otherwise, we set the base register to a non-zero value
Index: clang/test/CodeGen/X86/ms_fmul.c
===
--- /dev/null
+++ clang/test/CodeGen/X86/ms_fmul.c
@@ -0,0 +1,21 @@
+// REQUIRES: x86-registered-target
+
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -fasm-blocks -emit-llvm %s 
-o - | FileCheck %s
+// RUN: %clang_cc1 -triple i386-unknown-unknown -fasm-blocks -emit-llvm %s -o 
- | FileCheck %s
+
+// This test is designed to check if we use the mem size info for parsing MS
+// InlineAsm which use a global variable and one/two registers in a memory
+// expression. If we not use this mem size info, there will be error of
+// ambiguous operand size for some instructions. (e.g. 'fmul')
+__attribute__((aligned (16)))
+static const unsigned int static_const_table[] = { 0x0080, };
+
+
+void __attribute__ ((naked)) foo(void)
+{__asm{
+fmul qword ptr [static_const_table + 0x00f0 +edx]
+ret
+}}
+
+// CHECK-LABEL: foo
+// CHECK: call void asm sideeffect inteldialect "fmul qword ptr 
static_const_table[edx + $$240]\0A\09ret"


Index: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
===
--- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1759,7 +1759,7 @@
   // registers in a mmory expression, and though unaccessible via rip/eip.
   if (IsGlobalLV && (BaseReg || IndexReg)) {
 Operands.push_back(
-X86Operand::CreateMem(getPointerWidth(), Disp, Start, End));
+X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size));
 return false;
   }
   // Otherwise, we set the base register to a non-zero value
Index: clang/test/CodeGen/X86/ms_fmul.c
===
--- /dev/null
+++ clang/test/CodeGen/X86/ms_fmul.c
@@ -0,0 +1,21 @@
+// REQUIRES: x86-registered-target
+
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -fasm-blocks -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple i386-unknown-unknown -fasm-blocks -emit-llvm %s -o - | FileCheck %s
+
+// This test is designed to check if we use the mem size info for parsing MS
+// InlineAsm which use a global variable and one/two registers in a memory
+// expression. If we not use this mem size info, there will be error of
+// ambiguous operand size for some instructions. (e.g. 'fmul')
+__attribute__((aligned (16)))
+static const unsigned int static_const_table[] = { 0x0080, };
+
+
+void __attribute__ ((naked)) foo(void)
+{__asm{
+fmul qword ptr [static_const_table + 0x00f0 +edx]
+ret
+}}
+
+// CHECK-LABEL: foo
+// CHECK: call void asm sideeffect inteldialect "fmul qword ptr static_const_table[edx + $$240]\0A\09ret"
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[PATCH] D109488: [X86] Adjust Keylocker store register num for encodekey128/256

[Xiang Zhang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGc81d6ab87582: [X86] Adjust Keylocker handle mem size 
(authored by xiangzhangllvm).
Herald added a project: clang.
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Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/keylockerintrin.h
  clang/test/CodeGen/X86/keylocker.c
  llvm/test/CodeGen/X86/keylocker-intrinsics.ll

Index: llvm/test/CodeGen/X86/keylocker-intrinsics.ll
===
--- llvm/test/CodeGen/X86/keylocker-intrinsics.ll
+++ llvm/test/CodeGen/X86/keylocker-intrinsics.ll
@@ -36,40 +36,24 @@
 define i32 @test_encodekey128_u32(i32 %htype, <2 x i64> %key, <2 x i64>* nocapture %h0, <2 x i64>* nocapture %h1, <2 x i64>* nocapture %h2, <2 x i64>* nocapture %h3, <2 x i64>* nocapture %h4, <2 x i64>* nocapture %h5) nounwind {
 ; X64-LABEL: test_encodekey128_u32:
 ; X64:   # %bb.0: # %entry
-; X64-NEXT:movq {{[0-9]+}}(%rsp), %r10
 ; X64-NEXT:encodekey128 %edi, %eax
 ; X64-NEXT:movaps %xmm0, (%rsi)
 ; X64-NEXT:movaps %xmm1, (%rdx)
 ; X64-NEXT:movaps %xmm2, (%rcx)
-; X64-NEXT:movaps %xmm4, (%r8)
-; X64-NEXT:movaps %xmm5, (%r9)
-; X64-NEXT:movaps %xmm6, (%r10)
 ; X64-NEXT:retq
 ;
 ; X32-LABEL: test_encodekey128_u32:
 ; X32:   # %bb.0: # %entry
-; X32-NEXT:pushl %ebp
-; X32-NEXT:pushl %ebx
-; X32-NEXT:pushl %edi
 ; X32-NEXT:pushl %esi
 ; X32-NEXT:movl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:movl {{[0-9]+}}(%esp), %edx
 ; X32-NEXT:movl {{[0-9]+}}(%esp), %esi
-; X32-NEXT:movl {{[0-9]+}}(%esp), %edi
-; X32-NEXT:movl {{[0-9]+}}(%esp), %ebx
-; X32-NEXT:movl {{[0-9]+}}(%esp), %ebp
 ; X32-NEXT:movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:encodekey128 %eax, %eax
-; X32-NEXT:vmovaps %xmm0, (%ebp)
-; X32-NEXT:vmovaps %xmm1, (%ebx)
-; X32-NEXT:vmovaps %xmm2, (%edi)
-; X32-NEXT:vmovaps %xmm4, (%esi)
-; X32-NEXT:vmovaps %xmm5, (%edx)
-; X32-NEXT:vmovaps %xmm6, (%ecx)
+; X32-NEXT:vmovaps %xmm0, (%esi)
+; X32-NEXT:vmovaps %xmm1, (%edx)
+; X32-NEXT:vmovaps %xmm2, (%ecx)
 ; X32-NEXT:popl %esi
-; X32-NEXT:popl %edi
-; X32-NEXT:popl %ebx
-; X32-NEXT:popl %ebp
 ; X32-NEXT:retl
 entry:
   %0 = tail call { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.encodekey128(i32 %htype, <2 x i64> %key)
@@ -79,53 +63,36 @@
   store <2 x i64> %2, <2 x i64>* %h1, align 16
   %3 = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %0, 3
   store <2 x i64> %3, <2 x i64>* %h2, align 16
-  %4 = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %0, 4
-  store <2 x i64> %4, <2 x i64>* %h3, align 16
-  %5 = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %0, 5
-  store <2 x i64> %5, <2 x i64>* %h4, align 16
-  %6 = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %0, 6
-  store <2 x i64> %6, <2 x i64>* %h5, align 16
-  %7 = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %0, 0
-  ret i32 %7
+  %4 = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %0, 0
+  ret i32 %4
 }
 
 define i32 @test_encodekey256_u32(i32 %htype, <2 x i64> %key_lo, <2 x i64> %key_hi, <2 x i64>* nocapture %h0, <2 x i64>* nocapture %h1, <2 x i64>* nocapture %h2, <2 x i64>* nocapture %h3, <2 x i64>* nocapture %h4, <2 x i64>* nocapture %h5, <2 x  i64>* nocapture readnone %h6) nounwind {
 ; X64-LABEL: test_encodekey256_u32:
 ; X64:   # %bb.0: # %entry
-; X64-NEXT:movq {{[0-9]+}}(%rsp), %r10
 ; X64-NEXT:encodekey256 %edi, %eax
 ; X64-NEXT:movaps %xmm0, (%rsi)
 ; X64-NEXT:movaps %xmm1, (%rdx)
 ; X64-NEXT:movaps %xmm2, (%rcx)
 ; X64-NEXT:movaps %xmm3, (%r8)
-; X64-NEXT:movaps %xmm4, (%r9)
-; X64-NEXT:movaps %xmm5, (%r10)
 ; X64-NEXT:retq
 ;
 ; X32-LABEL: test_encodekey256_u32:
 ; X32:   # %bb.0: # %entry
-; X32-NEXT:pushl %ebp
-; X32-NEXT:pushl %ebx
 ; X32-NEXT:pushl %edi
 ; X32-NEXT:pushl %esi
 ; X32-NEXT:movl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:movl {{[0-9]+}}(%esp), %edx
 ; X32-NEXT:movl {{[0-9]+}}(%esp), %esi
 ; X32-NEXT:movl {{[0-9]+}}(%esp), %edi
-; X32-NEXT:movl {{[0-9]+}}(%esp), %ebx
-; X32-NEXT:movl {{[0-9]+}}(%esp), %ebp
 ; X32-NEXT:movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:encodekey256 %eax, %eax
-; X32-NEXT:vmovaps %xmm0, (%ebp)
-; X32-NEXT:vmovaps %xmm1, (%ebx)
-; X32-NEXT:vmovaps %xmm2, (%edi)
-; X32-NEXT:vmovaps %xmm3, (%esi)
-; X32-NEXT:vmovaps %xmm4, (%edx)
-; X32-NEXT:vmovaps %xmm5, (%ecx)
+; X32-NEXT:vmovaps %xmm0, 

[PATCH] D108682: [X86] Support __SSC_MARK(const int id) in x86gprintrin.h

[Xiang Zhang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG83e82ff76753: [X86] Support __SSC_MARK(const int id) 
(authored by xiangzhangllvm).
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Files:
  clang/lib/Headers/x86gprintrin.h
  clang/test/CodeGen/X86/x86-ssc-mark.c


Index: clang/test/CodeGen/X86/x86-ssc-mark.c
===
--- /dev/null
+++ clang/test/CodeGen/X86/x86-ssc-mark.c
@@ -0,0 +1,19 @@
+// RUN: %clang_cc1 %s -triple=x86_64-unknow-unknow -S -ffreestanding -o - | 
FileCheck %s
+// RUN: %clang_cc1 %s -triple=i386-unknow-unknow -S -ffreestanding -o - | 
FileCheck %s
+
+#include 
+
+// The ebx may be use for base pointer, we need to restore it in time.
+void ssc_mark() {
+// CHECK-LABEL: ssc_mark
+// CHECK: #APP
+// CHECK: movl%ebx, %eax
+// CHECK: movl$0, %ebx
+// CHECK: .byte   100
+// CHECK: .byte   103
+// CHECK: .byte   144
+// CHECK: movl%eax, %ebx
+// CHECK: #NO_APP
+
+  __SSC_MARK(0x0);
+}
Index: clang/lib/Headers/x86gprintrin.h
===
--- clang/lib/Headers/x86gprintrin.h
+++ clang/lib/Headers/x86gprintrin.h
@@ -20,4 +20,9 @@
 #include 
 #endif
 
+#define __SSC_MARK(Tag)
\
+  __asm__ __volatile__("movl %%ebx, %%eax; movl %0, %%ebx; .byte 0x64, 0x67, " 
\
+   "0x90; movl %%eax, %%ebx;" ::"i"(Tag)   
\
+   : "%eax");
+
 #endif /* __X86GPRINTRIN_H */


Index: clang/test/CodeGen/X86/x86-ssc-mark.c
===
--- /dev/null
+++ clang/test/CodeGen/X86/x86-ssc-mark.c
@@ -0,0 +1,19 @@
+// RUN: %clang_cc1 %s -triple=x86_64-unknow-unknow -S -ffreestanding -o - | FileCheck %s
+// RUN: %clang_cc1 %s -triple=i386-unknow-unknow -S -ffreestanding -o - | FileCheck %s
+
+#include 
+
+// The ebx may be use for base pointer, we need to restore it in time.
+void ssc_mark() {
+// CHECK-LABEL: ssc_mark
+// CHECK: #APP
+// CHECK: movl%ebx, %eax
+// CHECK: movl$0, %ebx
+// CHECK: .byte   100
+// CHECK: .byte   103
+// CHECK: .byte   144
+// CHECK: movl%eax, %ebx
+// CHECK: #NO_APP
+
+  __SSC_MARK(0x0);
+}
Index: clang/lib/Headers/x86gprintrin.h
===
--- clang/lib/Headers/x86gprintrin.h
+++ clang/lib/Headers/x86gprintrin.h
@@ -20,4 +20,9 @@
 #include 
 #endif
 
+#define __SSC_MARK(Tag)\
+  __asm__ __volatile__("movl %%ebx, %%eax; movl %0, %%ebx; .byte 0x64, 0x67, " \
+   "0x90; movl %%eax, %%ebx;" ::"i"(Tag)   \
+   : "%eax");
+
 #endif /* __X86GPRINTRIN_H */
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[PATCH] D105336: [X86] Refine code of generating BB labels in Keylocker

[Xiang Zhang via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa39bb960fc1e: [X86] Refine code of generating BB labels in 
Keylocker (authored by xiangzhangllvm).
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Files:
  clang/lib/CodeGen/CGBuiltin.cpp

Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -14758,40 +14758,34 @@
   case X86::BI__builtin_ia32_aesenc256kl_u8:
   case X86::BI__builtin_ia32_aesdec256kl_u8: {
 Intrinsic::ID IID;
-StringRef StrNoErr, StrErr, StrEnd;
+StringRef BlockName;
 switch (BuiltinID) {
-default: llvm_unreachable("Unexpected builtin");
+default:
+  llvm_unreachable("Unexpected builtin");
 case X86::BI__builtin_ia32_aesenc128kl_u8:
   IID = Intrinsic::x86_aesenc128kl;
-  StrNoErr = "aesenc128kl_no_error";
-  StrErr = "aesenc128kl_error";
-  StrEnd = "aesenc128kl_end";
+  BlockName = "aesenc128kl";
   break;
 case X86::BI__builtin_ia32_aesdec128kl_u8:
   IID = Intrinsic::x86_aesdec128kl;
-  StrNoErr = "aesdec128kl_no_error";
-  StrErr = "aesdec128kl_error";
-  StrEnd = "aesdec128kl_end";
+  BlockName = "aesdec128kl";
   break;
 case X86::BI__builtin_ia32_aesenc256kl_u8:
   IID = Intrinsic::x86_aesenc256kl;
-  StrNoErr = "aesenc256kl_no_error";
-  StrErr = "aesenc256kl_error";
-  StrEnd = "aesenc256kl_end";
+  BlockName = "aesenc256kl";
   break;
 case X86::BI__builtin_ia32_aesdec256kl_u8:
   IID = Intrinsic::x86_aesdec256kl;
-  StrNoErr = "aesdec256kl_no_error";
-  StrErr = "aesdec256kl_error";
-  StrEnd = "aesdec256kl_end";
+  BlockName = "aesdec256kl";
   break;
 }
 
 Value *Call = Builder.CreateCall(CGM.getIntrinsic(IID), {Ops[1], Ops[2]});
 
-BasicBlock *NoError = createBasicBlock(StrNoErr, this->CurFn);
-BasicBlock *Error = createBasicBlock(StrErr, this->CurFn);
-BasicBlock *End = createBasicBlock(StrEnd, this->CurFn);
+BasicBlock *NoError =
+createBasicBlock(BlockName + "_no_error", this->CurFn);
+BasicBlock *Error = createBasicBlock(BlockName + "_error", this->CurFn);
+BasicBlock *End = createBasicBlock(BlockName + "_end", this->CurFn);
 
 Value *Ret = Builder.CreateExtractValue(Call, 0);
 Value *Succ = Builder.CreateTrunc(Ret, Builder.getInt1Ty());
@@ -14815,31 +14809,23 @@
   case X86::BI__builtin_ia32_aesencwide256kl_u8:
   case X86::BI__builtin_ia32_aesdecwide256kl_u8: {
 Intrinsic::ID IID;
-StringRef StrNoErr, StrErr, StrEnd;
+StringRef BlockName;
 switch (BuiltinID) {
 case X86::BI__builtin_ia32_aesencwide128kl_u8:
   IID = Intrinsic::x86_aesencwide128kl;
-  StrNoErr = "aesencwide128kl_no_error";
-  StrErr = "aesencwide128kl_error";
-  StrEnd = "aesencwide128kl_end";
+  BlockName = "aesencwide128kl";
   break;
 case X86::BI__builtin_ia32_aesdecwide128kl_u8:
   IID = Intrinsic::x86_aesdecwide128kl;
-  StrNoErr = "aesdecwide128kl_no_error";
-  StrErr = "aesdecwide128kl_error";
-  StrEnd = "aesdecwide128kl_end";
+  BlockName = "aesdecwide128kl";
   break;
 case X86::BI__builtin_ia32_aesencwide256kl_u8:
   IID = Intrinsic::x86_aesencwide256kl;
-  StrNoErr = "aesencwide256kl_no_error";
-  StrErr = "aesencwide256kl_error";
-  StrEnd = "aesencwide256kl_end";
+  BlockName = "aesencwide256kl";
   break;
 case X86::BI__builtin_ia32_aesdecwide256kl_u8:
   IID = Intrinsic::x86_aesdecwide256kl;
-  StrNoErr = "aesdecwide256kl_no_error";
-  StrErr = "aesdecwide256kl_error";
-  StrEnd = "aesdecwide256kl_end";
+  BlockName = "aesdecwide256kl";
   break;
 }
 
@@ -14853,9 +14839,10 @@
 
 Value *Call = Builder.CreateCall(CGM.getIntrinsic(IID), InOps);
 
-BasicBlock *NoError = createBasicBlock(StrNoErr, this->CurFn);
-BasicBlock *Error = createBasicBlock(StrErr, this->CurFn);
-BasicBlock *End = createBasicBlock(StrEnd, this->CurFn);
+BasicBlock *NoError =
+createBasicBlock(BlockName + "_no_error", this->CurFn);
+BasicBlock *Error = createBasicBlock(BlockName + "_error", this->CurFn);
+BasicBlock *End = createBasicBlock(BlockName + "_end", this->CurFn);
 
 Value *Ret = Builder.CreateExtractValue(Call, 0);
 Value *Succ = Builder.CreateTrunc(Ret, Builder.getInt1Ty());
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[PATCH] D88398: [X86] Support Intel Key Locker

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added a comment.

I'll use the old patch to recover it, thanks!


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[PATCH] D88398: [X86] Support Intel Key Locker

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added a comment.

Oh, sorry, It is a mistake, I planned to update to 
https://reviews.llvm.org/D105336
How can I revert this update ?


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[PATCH] D88398: [X86] Support Intel Key Locker

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm updated this revision to Diff 356413.
xiangzhangllvm added a comment.

Refine Clang format


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Files:
  clang/lib/CodeGen/CGBuiltin.cpp

Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -14758,40 +14758,34 @@
   case X86::BI__builtin_ia32_aesenc256kl_u8:
   case X86::BI__builtin_ia32_aesdec256kl_u8: {
 Intrinsic::ID IID;
-StringRef StrNoErr, StrErr, StrEnd;
+StringRef BlockName;
 switch (BuiltinID) {
-default: llvm_unreachable("Unexpected builtin");
+default:
+  llvm_unreachable("Unexpected builtin");
 case X86::BI__builtin_ia32_aesenc128kl_u8:
   IID = Intrinsic::x86_aesenc128kl;
-  StrNoErr = "aesenc128kl_no_error";
-  StrErr = "aesenc128kl_error";
-  StrEnd = "aesenc128kl_end";
+  BlockName = "aesenc128kl";
   break;
 case X86::BI__builtin_ia32_aesdec128kl_u8:
   IID = Intrinsic::x86_aesdec128kl;
-  StrNoErr = "aesdec128kl_no_error";
-  StrErr = "aesdec128kl_error";
-  StrEnd = "aesdec128kl_end";
+  BlockName = "aesdec128kl";
   break;
 case X86::BI__builtin_ia32_aesenc256kl_u8:
   IID = Intrinsic::x86_aesenc256kl;
-  StrNoErr = "aesenc256kl_no_error";
-  StrErr = "aesenc256kl_error";
-  StrEnd = "aesenc256kl_end";
+  BlockName = "aesenc256kl";
   break;
 case X86::BI__builtin_ia32_aesdec256kl_u8:
   IID = Intrinsic::x86_aesdec256kl;
-  StrNoErr = "aesdec256kl_no_error";
-  StrErr = "aesdec256kl_error";
-  StrEnd = "aesdec256kl_end";
+  BlockName = "aesdec256kl";
   break;
 }
 
 Value *Call = Builder.CreateCall(CGM.getIntrinsic(IID), {Ops[1], Ops[2]});
 
-BasicBlock *NoError = createBasicBlock(StrNoErr, this->CurFn);
-BasicBlock *Error = createBasicBlock(StrErr, this->CurFn);
-BasicBlock *End = createBasicBlock(StrEnd, this->CurFn);
+BasicBlock *NoError =
+createBasicBlock(BlockName + "_no_error", this->CurFn);
+BasicBlock *Error = createBasicBlock(BlockName + "_error", this->CurFn);
+BasicBlock *End = createBasicBlock(BlockName + "_end", this->CurFn);
 
 Value *Ret = Builder.CreateExtractValue(Call, 0);
 Value *Succ = Builder.CreateTrunc(Ret, Builder.getInt1Ty());
@@ -14815,31 +14809,23 @@
   case X86::BI__builtin_ia32_aesencwide256kl_u8:
   case X86::BI__builtin_ia32_aesdecwide256kl_u8: {
 Intrinsic::ID IID;
-StringRef StrNoErr, StrErr, StrEnd;
+StringRef BlockName;
 switch (BuiltinID) {
 case X86::BI__builtin_ia32_aesencwide128kl_u8:
   IID = Intrinsic::x86_aesencwide128kl;
-  StrNoErr = "aesencwide128kl_no_error";
-  StrErr = "aesencwide128kl_error";
-  StrEnd = "aesencwide128kl_end";
+  BlockName = "aesencwide128kl";
   break;
 case X86::BI__builtin_ia32_aesdecwide128kl_u8:
   IID = Intrinsic::x86_aesdecwide128kl;
-  StrNoErr = "aesdecwide128kl_no_error";
-  StrErr = "aesdecwide128kl_error";
-  StrEnd = "aesdecwide128kl_end";
+  BlockName = "aesdecwide128kl";
   break;
 case X86::BI__builtin_ia32_aesencwide256kl_u8:
   IID = Intrinsic::x86_aesencwide256kl;
-  StrNoErr = "aesencwide256kl_no_error";
-  StrErr = "aesencwide256kl_error";
-  StrEnd = "aesencwide256kl_end";
+  BlockName = "aesencwide256kl";
   break;
 case X86::BI__builtin_ia32_aesdecwide256kl_u8:
   IID = Intrinsic::x86_aesdecwide256kl;
-  StrNoErr = "aesdecwide256kl_no_error";
-  StrErr = "aesdecwide256kl_error";
-  StrEnd = "aesdecwide256kl_end";
+  BlockName = "aesdecwide256kl";
   break;
 }
 
@@ -14853,9 +14839,10 @@
 
 Value *Call = Builder.CreateCall(CGM.getIntrinsic(IID), InOps);
 
-BasicBlock *NoError = createBasicBlock(StrNoErr, this->CurFn);
-BasicBlock *Error = createBasicBlock(StrErr, this->CurFn);
-BasicBlock *End = createBasicBlock(StrEnd, this->CurFn);
+BasicBlock *NoError =
+createBasicBlock(BlockName + "_no_error", this->CurFn);
+BasicBlock *Error = createBasicBlock(BlockName + "_error", this->CurFn);
+BasicBlock *End = createBasicBlock(BlockName + "_end", this->CurFn);
 
 Value *Ret = Builder.CreateExtractValue(Call, 0);
 Value *Succ = Builder.CreateTrunc(Ret, Builder.getInt1Ty());
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[PATCH] D104766: [X86] Zero some outputs of Keylocker intrinsics in error case

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added a comment.

Done at https://reviews.llvm.org/D105336, thanks again!


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[PATCH] D104766: [X86] Zero some outputs of Keylocker intrinsics in error case

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:14834
 
+BasicBlock *NoError = createBasicBlock(StrNoErr, this->CurFn);
+BasicBlock *Error = createBasicBlock(StrErr, this->CurFn);

craig.topper wrote:
> Sorry I'm late here. Instead of having 3 separate strings for each intrinsic 
> can you do something like `createBasicBlock(BaseName + "_no_error"...)` here. 
> I believe createBasicBlock takes a Twine.
Hello Craig! Nice to meet you again :) , Sorry for not noticing you this patch 
before. I planned  not to disturb you if not necessary.

Yes, using Twine will more clear, let me refine it. Thanks a lot!


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[PATCH] D102288: [HWASan] Add -fsanitize=lam flag and enable HWASan to use it.

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added inline comments.



Comment at: compiler-rt/test/hwasan/TestCases/Linux/vfork.c:7
-// Aliasing mode does not support stack tagging.
-// XFAIL: x86_64
 

What does here XFAIL mean, do not test in x86_64 ?


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[PATCH] D101059: [X86][AMX] Add description for AMX new interface.

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xiangzhangllvm added a comment.

+1


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[PATCH] D100919: [AArch64] Support customizing stack protector guard

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm accepted this revision.
xiangzhangllvm added a comment.
This revision is now accepted and ready to land.

I didn't find any problem in the main context of the patch, +1 first.


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[PATCH] D98757: [AMX] Not fold constant bitcast into amx intrisic

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added a comment.

In D98757#2631042 , @lebedev.ri wrote:

> The ongoing special-casing of `X86_AMXTy` through the llvm due to the 
> inability of the existing backend passes to handle certain llvm ir constructs.

We have bring up it to llvm-dev.
BTW,** All the Type should see as target independent.** (Even it support by 
less targets or 1 target)

Current we see  “ if (Ty.isVectorTy()) {…}” is make sense in Mid-End. 
Why we can’t see “if (Ty.isX86_AMXTy()){…}” is make sense ?

**Just because more targets support the VectorTy, less target (only x86) 
support the AMXTy ?
The logic is not make sense.**


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[PATCH] D98757: [AMX] Not fold constant bitcast into amx intrisic

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added a comment.

In D98757#2631019 , @lebedev.ri wrote:

> Once again, i suggest to bring this up on llvm-dev.

That is obvious,
Discuss what, can you point it out clearly ?
The topic is do it in mid-end or back-end ?


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[PATCH] D98757: [AMX] Not fold constant bitcast into amx intrisic

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added a comment.

In D98757#2630968 , @lebedev.ri wrote:

> I think that is a traditional backend problem that the pass will just have to 
> be updated to deal with.

Hi @lebedev.ri , seems there is some mistakes, let me first point out the 
problem:

1. All AMX operation should use AMX intrinsic,

So we need specially handle the bitcast from Constant vector to AMX type. (Not 
use normal load / store)
This work is done at Back-End pass "Lower AMX type for Load/Store" by checking 
the bitcast instruction.

2. If Mid-End fold this bitcast into a instruction, currently, the Back-End 
pass "Lower AMX type for Load/Store" will no find it.

(of course, we can check every operands of every instruction to find out the 
amx bitcast, but it not good job, directly let it not folding in mid-end is 
better)


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[PATCH] D98757: [AMX] Not fold constant bitcast into amx intrisic

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added a comment.

In D98757#2630942 , @lebedev.ri wrote:

> I strongly suggest you bring up this ongoing creep of `if 
> (DestTy->isX86_AMXTy()) return false;` on llvm-dev.
> I strongly supsect you are covering up bugs in you backend/pass with them.

Sorry, I don't much understand your idea, I happen to find this bug when I 
supporting fast reg allocation for AMX.
It fold the Constant bitcast of tile type into a amx instruction, which will 
escape the BackEnd pass "Lower AMX type for Load/Store"


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[PATCH] D98757: [AMX] Not fold constant bitcast into amx intrisic

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added inline comments.



Comment at: llvm/lib/Analysis/ConstantFolding.cpp:101
 /// Constant fold bitcast, symbolically evaluating it with DataLayout.
 /// This always returns a non-null constant, but it may be a
 /// ConstantExpr if unfoldable.

clin1 wrote:
> xiangzhangllvm wrote:
> > clin1 wrote:
> > > API for this function always returns non-null: can we return 
> > > ConstantExpr::getBitCast(C,DestTy) instead? Then the change in SCCP is 
> > > not needed either.
> > I tried, the SCCP will also fold the bitcast into the following instruction.
> I see, that makes sense. But are we sure that all callers of FoldBitCast are 
> doing a null check: for example, FoldReinterpretLoadFromConstPtr calls 
> FoldBitCast several times, and null is not checked before dereference. Maybe 
> the AMX type cannot happen in this case?
> Alternative: can AMX be checked in SCCP?
Right! let me check the callers of FoldBitCast,
Luckly, there is only several callers of FoldBitCast, and almost all in this 
file ConstantFolding.cpp.


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[PATCH] D98757: [AMX] Not fold constant bitcast into amx intrisic

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added a comment.

In D98757#2630844 , @LuoYuanke wrote:

> Probably we need a .ll test case to for constant folding.

Fold constant is done in CSE and SCCP which are both passes run in Clang (O2 
)




Comment at: llvm/lib/Analysis/ConstantFolding.cpp:101
 /// Constant fold bitcast, symbolically evaluating it with DataLayout.
 /// This always returns a non-null constant, but it may be a
 /// ConstantExpr if unfoldable.

clin1 wrote:
> API for this function always returns non-null: can we return 
> ConstantExpr::getBitCast(C,DestTy) instead? Then the change in SCCP is not 
> needed either.
I tried, the SCCP will also fold the bitcast into the following instruction.


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[PATCH] D98757: [AMX] Not fold constant bitcast into amx intrisic

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added a comment.

In D98757#2630764 , @LuoYuanke wrote:

> Would you add a test case for it?

at  clang/test/CodeGen/X86/amx_api.c


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[PATCH] D98757: [AMX] Not fold constant bitcast into amx intrisic

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added inline comments.



Comment at: clang/test/CodeGen/X86/amx_api.c:39
+void test_tile_init(short row, short col) {
+  __tile1024i c = {row, col, {1, 2, 3}};
+  __tile_stored(buf, STRIDE, c);

we usually write like this __tile1024i c = {row, col};
rm {1,2,3} will also see as {row, col, {0,...}}


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[PATCH] D98757: [AMX] Not fold constant bitcast into amx intrisic

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm created this revision.
xiangzhangllvm added reviewers: LuoYuanke, pengfei, LiuChen3, yubing.
Herald added a subscriber: hiraditya.
xiangzhangllvm requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

We won't fold bitcast for tile type, becasue there is no way to
assignee a tmm reg from a constant. We manually generate tilestore
and tileload at pass "Lower AMX type".


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Files:
  clang/test/CodeGen/X86/amx_api.c
  llvm/lib/Analysis/ConstantFolding.cpp
  llvm/lib/Transforms/Scalar/SCCP.cpp


Index: llvm/lib/Transforms/Scalar/SCCP.cpp
===
--- llvm/lib/Transforms/Scalar/SCCP.cpp
+++ llvm/lib/Transforms/Scalar/SCCP.cpp
@@ -826,7 +826,7 @@
   if (Constant *OpC = getConstant(OpSt)) {
 // Fold the constant as we build.
 Constant *C = ConstantFoldCastOperand(I.getOpcode(), OpC, I.getType(), DL);
-if (isa(C))
+if (!C || isa(C))
   return;
 // Propagate constant value
 markConstant(, C);
Index: llvm/lib/Analysis/ConstantFolding.cpp
===
--- llvm/lib/Analysis/ConstantFolding.cpp
+++ llvm/lib/Analysis/ConstantFolding.cpp
@@ -104,10 +104,16 @@
   assert(CastInst::castIsValid(Instruction::BitCast, C, DestTy) &&
  "Invalid constantexpr bitcast!");
 
+  // We won't fold bitcast for tile type, becasue there is no way to
+  // assigne a tmm reg from a constant. We manually generate tilestore
+  // and tileload at pass "Lower AMX type".
+  if (DestTy->isX86_AMXTy())
+return nullptr;
+
   // Catch the obvious splat cases.
-  if (C->isNullValue() && !DestTy->isX86_MMXTy() && !DestTy->isX86_AMXTy())
+  if (C->isNullValue() && !DestTy->isX86_MMXTy())
 return Constant::getNullValue(DestTy);
-  if (C->isAllOnesValue() && !DestTy->isX86_MMXTy() && !DestTy->isX86_AMXTy() 
&&
+  if (C->isAllOnesValue() && !DestTy->isX86_MMXTy() &&
   !DestTy->isPtrOrPtrVectorTy()) // Don't get ones for ptr types!
 return Constant::getAllOnesValue(DestTy);
 
Index: clang/test/CodeGen/X86/amx_api.c
===
--- clang/test/CodeGen/X86/amx_api.c
+++ clang/test/CodeGen/X86/amx_api.c
@@ -1,6 +1,9 @@
 // RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding 
-triple=x86_64-unknown-unknown  -target-feature +avx512f  -target-feature 
+amx-int8  \
 // RUN: -target-feature +amx-bf16 -emit-llvm -o - -Werror -pedantic | 
FileCheck %s --check-prefixes=CHECK
 
+// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding 
-triple=x86_64-unknown-unknown  -target-feature +avx512f  -target-feature 
+amx-int8  \
+// RUN: -target-feature +amx-bf16 -O2 -emit-llvm -o - -Werror -pedantic | 
FileCheck %s --check-prefixes=CHECK2
+
 #include 
 
 char buf[1024];
@@ -31,6 +34,15 @@
   __tile_stored(buf, STRIDE, c);
 }
 
+// Not fold the bitcast const vector into amx intrisic.
+void test_tile_init(short row, short col) {
+  __tile1024i c = {row, col, {1, 2, 3}};
+  __tile_stored(buf, STRIDE, c);
+  //CHECK2-LABEL: @test_tile_init
+  //CHECK2: {{%.*}} = bitcast <256 x i32> Index: llvm/lib/Transforms/Scalar/SCCP.cpp
===
--- llvm/lib/Transforms/Scalar/SCCP.cpp
+++ llvm/lib/Transforms/Scalar/SCCP.cpp
@@ -826,7 +826,7 @@
   if (Constant *OpC = getConstant(OpSt)) {
 // Fold the constant as we build.
 Constant *C = ConstantFoldCastOperand(I.getOpcode(), OpC, I.getType(), DL);
-if (isa(C))
+if (!C || isa(C))
   return;
 // Propagate constant value
 markConstant(, C);
Index: llvm/lib/Analysis/ConstantFolding.cpp
===
--- llvm/lib/Analysis/ConstantFolding.cpp
+++ llvm/lib/Analysis/ConstantFolding.cpp
@@ -104,10 +104,16 @@
   assert(CastInst::castIsValid(Instruction::BitCast, C, DestTy) &&
  "Invalid constantexpr bitcast!");
 
+  // We won't fold bitcast for tile type, becasue there is no way to
+  // assigne a tmm reg from a constant. We manually generate tilestore
+  // and tileload at pass "Lower AMX type".
+  if (DestTy->isX86_AMXTy())
+return nullptr;
+
   // Catch the obvious splat cases.
-  if (C->isNullValue() && !DestTy->isX86_MMXTy() && !DestTy->isX86_AMXTy())
+  if (C->isNullValue() && !DestTy->isX86_MMXTy())
 return Constant::getNullValue(DestTy);
-  if (C->isAllOnesValue() && !DestTy->isX86_MMXTy() && !DestTy->isX86_AMXTy() &&
+  if (C->isAllOnesValue() && !DestTy->isX86_MMXTy() &&
   !DestTy->isPtrOrPtrVectorTy()) // Don't get ones for ptr types!
 return Constant::getAllOnesValue(DestTy);
 
Index: clang/test/CodeGen/X86/amx_api.c
===
--- clang/test/CodeGen/X86/amx_api.c
+++ clang/test/CodeGen/X86/amx_api.c
@@ -1,6 +1,9 @@
 // RUN: 

[PATCH] D97358: [X86] Support amx-bf16 intrinsic.

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added a comment.

+1 first, didn't see key problems.




Comment at: clang/lib/Headers/amxintrin.h:326
+__DEFAULT_FN_ATTRS_BF16
+static void __tile_tdpbf16ps(__tile1024i *dst, __tile1024i src1,
+ __tile1024i src2) {

yubing wrote:
> Should we align this with "tile_dpbssd" by renaming it wth "tile_dpbf16ps"?
Yes, "t" already means "tile"


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[PATCH] D93594: [X86] Pass to transform amx intrinsics to scalar operation.

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added inline comments.



Comment at: llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp:211-212
+IRBuilderBase , DomTreeUpdater ,
+LoopInfo , Value *Row, Value *Col,
+Value *K, Value *Acc, Value *LHS,
+Value *RHS) {

In fact, no need handle Row, Col, K here, just use fix size 16x16, the result 
of calculation is some in effective area. (just need tileload "keep" the 
"unused" area is 0). 
Then can use vector to handle all of the them, let type legalization to split 
the type.


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[PATCH] D93594: [X86] Pass to transform amx intrinsics to scalar operation.

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xiangzhangllvm added inline comments.



Comment at: llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp:356
+  I->eraseFromParent();
+}
+  }

I see you need force match bitcast then replace, add assert for no bitcast case



Comment at: llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp:471
+  for (auto *Inst : TileLoads) {
+C |= lowerTileLoad(Inst);
+  }

'|' is bits or, use logic ||


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[PATCH] D63908: hwasan: Improve precision of checks using short granule tags.

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added inline comments.



Comment at: compiler-rt/trunk/lib/hwasan/hwasan_checks.h:76
+#endif
+  return *(u8 *)(ptr | (kShadowAlignment - 1)) == ptr_tag;
+}

Hello @pcc I think here seems some problem, the ptr is user passing point,
*(ptr + n) should have the user's real data. it shouldn't  "== ptr_tag".


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[PATCH] D88631: [X86] Support customizing stack protector guard

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xiangzhangllvm added a comment.

TKS all review!!


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[PATCH] D88631: [X86] Support customizing stack protector guard

[Xiang Zhang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG7c3fea7721e4: [X86] Support customizing stack protector 
guard (authored by xiangzhangllvm).
Herald added a project: clang.
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Changed prior to commit:
  https://reviews.llvm.org/D88631?vs=299535=299843#toc

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Files:
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Basic/CodeGenOptions.h
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Driver/Options.td
  clang/lib/CodeGen/BackendUtil.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/Driver/stack-protector-guard.c
  llvm/include/llvm/CodeGen/CommandFlags.h
  llvm/include/llvm/Target/TargetOptions.h
  llvm/lib/CodeGen/CommandFlags.cpp
  llvm/lib/CodeGen/StackProtector.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/stack-protector-3.ll

Index: llvm/test/CodeGen/X86/stack-protector-3.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/stack-protector-3.ll
@@ -0,0 +1,67 @@
+; RUN: llc -mtriple=x86_64-pc-linux-gnu -o - < %s | FileCheck --check-prefix=CHECK-TLS-FS-40 %s
+; RUN: llc -mtriple=x86_64-pc-linux-gnu -stack-protector-guard=tls -o - < %s | FileCheck --check-prefix=CHECK-TLS-FS-40 %s
+; RUN: llc -mtriple=x86_64-pc-linux-gnu -stack-protector-guard=global -o - < %s | FileCheck --check-prefix=CHECK-GLOBAL %s
+; RUN: llc -mtriple=x86_64-pc-linux-gnu -stack-protector-guard-reg=fs -o - < %s | FileCheck --check-prefix=CHECK-TLS-FS-40 %s
+; RUN: llc -mtriple=x86_64-pc-linux-gnu -stack-protector-guard-reg=gs -o - < %s | FileCheck --check-prefix=CHECK-GS %s
+; RUN: llc -mtriple=x86_64-pc-linux-gnu -stack-protector-guard-offset=20 -o - < %s | FileCheck --check-prefix=CHECK-OFFSET %s
+
+; CHECK-TLS-FS-40:   movq%fs:40, %rax
+; CHECK-TLS-FS-40:   movq%fs:40, %rax
+; CHECK-TLS-FS-40-NEXT:  cmpq16(%rsp), %rax
+; CHECK-TLS-FS-40-NEXT:  jne .LBB0_2
+; CHECK-TLS-FS-40:   .LBB0_2:
+; CHECK-TLS-FS-40-NEXT:  .cfi_def_cfa_offset 32
+; CHECK-TLS-FS-40-NEXT:  callq   __stack_chk_fail
+
+; CHECK-GS:   movq%gs:40, %rax
+; CHECK-GS:   movq%gs:40, %rax
+; CHECK-GS-NEXT:  cmpq16(%rsp), %rax
+; CHECK-GS-NEXT:  jne .LBB0_2
+; CHECK-GS:   .LBB0_2:
+; CHECK-GS-NEXT:  .cfi_def_cfa_offset 32
+; CHECK-GS-NEXT:  callq   __stack_chk_fail
+
+; CHECK-OFFSET:   movq%fs:20, %rax
+; CHECK-OFFSET:   movq%fs:20, %rax
+; CHECK-OFFSET-NEXT:  cmpq16(%rsp), %rax
+; CHECK-OFFSET-NEXT:  jne .LBB0_2
+; CHECK-OFFSET:   .LBB0_2:
+; CHECK-OFFSET-NEXT:  .cfi_def_cfa_offset 32
+; CHECK-OFFSET-NEXT:  callq   __stack_chk_fail
+
+; CHECK-GLOBAL:   movq__stack_chk_guard(%rip), %rax
+; CHECK-GLOBAL:   movq__stack_chk_guard(%rip), %rax
+; CHECK-GLOBAL-NEXT:  cmpq16(%rsp), %rax
+; CHECK-GLOBAL-NEXT:  jne .LBB0_2
+; CHECK-GLOBAL:   .LBB0_2:
+; CHECK-GLOBAL-NEXT:  .cfi_def_cfa_offset 32
+; CHECK-GLOBAL-NEXT:  callq   __stack_chk_fail
+
+; ModuleID = 't.c'
+@.str = private unnamed_addr constant [14 x i8] c"stackoverflow\00", align 1
+@a = dso_local local_unnamed_addr global i8* null, align 8
+
+; Function Attrs: nounwind sspreq uwtable writeonly
+define dso_local i32 @main() local_unnamed_addr #0 {
+entry:
+  %array = alloca [5 x i8], align 1
+  %0 = getelementptr inbounds [5 x i8], [5 x i8]* %array, i64 0, i64 0
+  call void @llvm.lifetime.start.p0i8(i64 5, i8* nonnull %0) #2
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull align 1 dereferenceable(14) %0, i8* nonnull align 1 dereferenceable(14) getelementptr inbounds ([14 x i8], [14 x i8]* @.str, i64 0, i64 0), i64 14, i1 false) #2
+  store i8* %0, i8** @a, align 8
+  call void @llvm.lifetime.end.p0i8(i64 5, i8* nonnull %0) #2
+  ret i32 0
+}
+
+; Function Attrs: argmemonly nounwind willreturn
+declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) #1
+
+; Function Attrs: argmemonly nounwind willreturn
+declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) #1
+
+; Function Attrs: argmemonly nounwind willreturn
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i64, i1 immarg) #1
+
+attributes #0 = { nounwind sspreq uwtable writeonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { argmemonly nounwind 

[PATCH] D83111: [X86-64] Support Intel AMX Intrinsic

[Xiang Zhang via Phabricator via cfe-commits]

This revision was not accepted when it landed; it landed in state "Needs 
Review".
This revision was automatically updated to reflect the committed changes.
Closed by commit rG939d8309dbd4: [X86-64] Support Intel AMX Intrinsic (authored 
by xiangzhangllvm).
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Changed prior to commit:
  https://reviews.llvm.org/D83111?vs=275537=275644#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83111/new/

https://reviews.llvm.org/D83111

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/BuiltinsX86_64.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Driver/Options.td
  clang/include/clang/Sema/Sema.h
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/amxintrin.h
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/immintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/AMX/amx.c
  clang/test/CodeGen/AMX/amx_errors.c
  clang/test/CodeGen/AMX/amx_inline_asm.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_amx_target_features.c
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86InstrAMX.td
  llvm/test/CodeGen/X86/AMX/amx-bf16-intrinsics.ll
  llvm/test/CodeGen/X86/AMX/amx-int8-intrinsics.ll
  llvm/test/CodeGen/X86/AMX/amx-tile-intrinsics.ll

Index: llvm/test/CodeGen/X86/AMX/amx-tile-intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/AMX/amx-tile-intrinsics.ll
@@ -0,0 +1,36 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-tile -verify-machineinstrs | FileCheck %s
+
+define void @test_amx(i8* %pointer, i8* %base, i64 %stride) {
+; CHECK-LABEL: test_amx:
+; CHECK:   # %bb.0:
+  call void @llvm.x86.ldtilecfg(i8* %pointer)
+; CHECK-NEXT:ldtilecfg (%rdi)
+
+  call void @llvm.x86.sttilecfg(i8* %pointer)
+; CHECK-NEXT:sttilecfg (%rdi)
+
+  call void @llvm.x86.tilerelease()
+; CHECK-NEXT:tilerelease
+
+  call void @llvm.x86.tilezero(i8 3)
+; CHECK-NEXT:tilezero %tmm3
+
+  call void @llvm.x86.tileloadd64(i8 3, i8* %base, i64 %stride)
+; CHECK-NEXT:tileloadd (%rsi,%rdx), %tmm3
+
+  call void @llvm.x86.tileloaddt164(i8 3, i8* %base, i64 %stride)
+; CHECK-NEXT:tileloaddt1 (%rsi,%rdx), %tmm3
+
+  call void @llvm.x86.tilestored64(i8 3, i8* %base, i64 %stride)
+; CHECK-NEXT:tilestored %tmm3, (%rsi,%rdx)
+  ret void
+}
+
+declare void @llvm.x86.tileloadd64(i8 %tile, i8* %base, i64 %stride)
+declare void @llvm.x86.tileloaddt164(i8 %tile, i8* %base, i64 %stride)
+declare void @llvm.x86.tilestored64(i8 %tile, i8* %base, i64 %stride)
+declare void @llvm.x86.ldtilecfg(i8* %pointer)
+declare void @llvm.x86.sttilecfg(i8* %pointer)
+declare void @llvm.x86.tilerelease()
+declare void @llvm.x86.tilezero(i8 %tile)
Index: llvm/test/CodeGen/X86/AMX/amx-int8-intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/AMX/amx-int8-intrinsics.ll
@@ -0,0 +1,24 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -verify-machineinstrs | FileCheck %s
+
+define void @test_amx() {
+; CHECK-LABEL: test_amx:
+; CHECK:   # %bb.0:
+  call void @llvm.x86.tdpbssd(i8 3, i8 4, i8 7)
+; CHECK-NEXT:tdpbssd %tmm7, %tmm4, %tmm3
+
+  call void @llvm.x86.tdpbsud(i8 3, i8 4, i8 7)
+; CHECK-NEXT:tdpbsud %tmm7, %tmm4, %tmm3
+
+  call void @llvm.x86.tdpbusd(i8 3, i8 0, i8 7)
+; CHECK-NEXT:tdpbusd %tmm7, %tmm0, %tmm3
+
+  call void @llvm.x86.tdpbuud(i8 3, i8 4, i8 1)
+; CHECK-NEXT:tdpbuud %tmm1, %tmm4, %tmm3
+  ret void
+}
+
+declare void @llvm.x86.tdpbssd(i8 %tile0, i8 %tile1, i8 %tile2)
+declare void @llvm.x86.tdpbsud(i8 %tile0, i8 %tile1, i8 %tile2)
+declare void @llvm.x86.tdpbusd(i8 %tile0, i8 %tile1, i8 %tile2)
+declare void @llvm.x86.tdpbuud(i8 %tile0, i8 %tile1, i8 %tile2)
Index: llvm/test/CodeGen/X86/AMX/amx-bf16-intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/AMX/amx-bf16-intrinsics.ll
@@ -0,0 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-tile -mattr=+amx-bf16 -verify-machineinstrs | FileCheck %s
+
+define void @test_amx() {
+; CHECK-LABEL: test_amx:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tdpbf16ps %tmm7, %tmm4, %tmm3
+; CHECK-NEXT:retq
+  call void @llvm.x86.tdpbf16ps(i8 3, i8 4, i8 7)
+  ret void
+}
+
+declare void @llvm.x86.tdpbf16ps(i8 %tile0, i8 %tile1, i8 %tile2)
Index: llvm/lib/Target/X86/X86InstrAMX.td

[PATCH] D83111: [X86-64] Support Intel AMX Intrinsic

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added a comment.

In D83111#2134747 , @craig.topper 
wrote:

> LGTM with all instances of "pointer point" replace with just "pointer"


Done it in commit. Thank you!


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[PATCH] D83111: [X86-64] Support Intel AMX Intrinsic

[Xiang Zhang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG939d8309dbd4: [X86-64] Support Intel AMX Intrinsic (authored 
by xiangzhangllvm).
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Changed prior to commit:
  https://reviews.llvm.org/D83111?vs=275878=275888#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/BuiltinsX86_64.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Driver/Options.td
  clang/include/clang/Sema/Sema.h
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/amxintrin.h
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/immintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/AMX/amx.c
  clang/test/CodeGen/AMX/amx_errors.c
  clang/test/CodeGen/AMX/amx_inline_asm.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_amx_target_features.c
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86InstrAMX.td
  llvm/test/CodeGen/X86/AMX/amx-bf16-intrinsics.ll
  llvm/test/CodeGen/X86/AMX/amx-int8-intrinsics.ll
  llvm/test/CodeGen/X86/AMX/amx-tile-intrinsics.ll

Index: llvm/test/CodeGen/X86/AMX/amx-tile-intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/AMX/amx-tile-intrinsics.ll
@@ -0,0 +1,36 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-tile -verify-machineinstrs | FileCheck %s
+
+define void @test_amx(i8* %pointer, i8* %base, i64 %stride) {
+; CHECK-LABEL: test_amx:
+; CHECK:   # %bb.0:
+  call void @llvm.x86.ldtilecfg(i8* %pointer)
+; CHECK-NEXT:ldtilecfg (%rdi)
+
+  call void @llvm.x86.sttilecfg(i8* %pointer)
+; CHECK-NEXT:sttilecfg (%rdi)
+
+  call void @llvm.x86.tilerelease()
+; CHECK-NEXT:tilerelease
+
+  call void @llvm.x86.tilezero(i8 3)
+; CHECK-NEXT:tilezero %tmm3
+
+  call void @llvm.x86.tileloadd64(i8 3, i8* %base, i64 %stride)
+; CHECK-NEXT:tileloadd (%rsi,%rdx), %tmm3
+
+  call void @llvm.x86.tileloaddt164(i8 3, i8* %base, i64 %stride)
+; CHECK-NEXT:tileloaddt1 (%rsi,%rdx), %tmm3
+
+  call void @llvm.x86.tilestored64(i8 3, i8* %base, i64 %stride)
+; CHECK-NEXT:tilestored %tmm3, (%rsi,%rdx)
+  ret void
+}
+
+declare void @llvm.x86.tileloadd64(i8 %tile, i8* %base, i64 %stride)
+declare void @llvm.x86.tileloaddt164(i8 %tile, i8* %base, i64 %stride)
+declare void @llvm.x86.tilestored64(i8 %tile, i8* %base, i64 %stride)
+declare void @llvm.x86.ldtilecfg(i8* %pointer)
+declare void @llvm.x86.sttilecfg(i8* %pointer)
+declare void @llvm.x86.tilerelease()
+declare void @llvm.x86.tilezero(i8 %tile)
Index: llvm/test/CodeGen/X86/AMX/amx-int8-intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/AMX/amx-int8-intrinsics.ll
@@ -0,0 +1,24 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -verify-machineinstrs | FileCheck %s
+
+define void @test_amx() {
+; CHECK-LABEL: test_amx:
+; CHECK:   # %bb.0:
+  call void @llvm.x86.tdpbssd(i8 3, i8 4, i8 7)
+; CHECK-NEXT:tdpbssd %tmm7, %tmm4, %tmm3
+
+  call void @llvm.x86.tdpbsud(i8 3, i8 4, i8 7)
+; CHECK-NEXT:tdpbsud %tmm7, %tmm4, %tmm3
+
+  call void @llvm.x86.tdpbusd(i8 3, i8 0, i8 7)
+; CHECK-NEXT:tdpbusd %tmm7, %tmm0, %tmm3
+
+  call void @llvm.x86.tdpbuud(i8 3, i8 4, i8 1)
+; CHECK-NEXT:tdpbuud %tmm1, %tmm4, %tmm3
+  ret void
+}
+
+declare void @llvm.x86.tdpbssd(i8 %tile0, i8 %tile1, i8 %tile2)
+declare void @llvm.x86.tdpbsud(i8 %tile0, i8 %tile1, i8 %tile2)
+declare void @llvm.x86.tdpbusd(i8 %tile0, i8 %tile1, i8 %tile2)
+declare void @llvm.x86.tdpbuud(i8 %tile0, i8 %tile1, i8 %tile2)
Index: llvm/test/CodeGen/X86/AMX/amx-bf16-intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/AMX/amx-bf16-intrinsics.ll
@@ -0,0 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-tile -mattr=+amx-bf16 -verify-machineinstrs | FileCheck %s
+
+define void @test_amx() {
+; CHECK-LABEL: test_amx:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tdpbf16ps %tmm7, %tmm4, %tmm3
+; CHECK-NEXT:retq
+  call void @llvm.x86.tdpbf16ps(i8 3, i8 4, i8 7)
+  ret void
+}
+
+declare void @llvm.x86.tdpbf16ps(i8 %tile0, i8 %tile1, i8 %tile2)
Index: llvm/lib/Target/X86/X86InstrAMX.td
===
--- llvm/lib/Target/X86/X86InstrAMX.td
+++ 

[PATCH] D79617: Add cet.h for writing CET-enabled assembly code

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added a comment.

Hello rsmith, 
first, very sorry for have committed this patch before your reply, I waited 10 
days, I thought you have agreed it. 
I think the  linux-ABI can be the specification of this head file. The context 
of this cet.h is according to the linux ABI about CET.
We explained in which case we should use this cet.h file. (line 2-4)
tks


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[PATCH] D79617: Add cet.h for writing CET-enabled assembly code

[Xiang Zhang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGbcc0c894f38f: Add cet.h for writing CET-enabled assembly 
code (authored by xiangzhangllvm).

Changed prior to commit:
  https://reviews.llvm.org/D79617?vs=264772=264799#toc

Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/cet.h
  clang/test/CodeGen/asm-cet.S

Index: clang/test/CodeGen/asm-cet.S
===
--- /dev/null
+++ clang/test/CodeGen/asm-cet.S
@@ -0,0 +1,27 @@
+// REQUIRES: x86-registered-target
+// RUN: %clang --target=x86_64-pc-linux -fcf-protection  -include cet.h -c %s -o - | llvm-readelf -n | FileCheck %s
+// RUN: %clang --target=x86_64-pc-linux -include cet.h -c %s -o - | llvm-readelf -S | FileCheck %s --check-prefixes=NOCET
+// RUN: %clang --target=x86_64-pc-linux -include cet.h -S %s -o - | FileCheck %s --check-prefixes=NOENDBR
+// RUN: %clang --target=x86_64-pc-linux -fcf-protection  -include cet.h -S %s -o - | FileCheck %s --check-prefixes=ENDBR64
+
+// RUN: %clang --target=i386-pc-linux -fcf-protection  -include cet.h -c %s -o - | llvm-readelf -n | FileCheck %s
+// RUN: %clang --target=i386-pc-linux -include cet.h -c %s -o - | llvm-readelf -S | FileCheck %s --check-prefixes=NOCET
+// RUN: %clang --target=i386-pc-linux -include cet.h -S %s -o - | FileCheck %s --check-prefixes=NOENDBR
+// RUN: %clang --target=i386-pc-linux -fcf-protection  -include cet.h -S %s -o - | FileCheck %s --check-prefixes=ENDBR32
+
+// CHECK: IBT, SHSTK
+
+// NOCET: Section Headers
+// NOCET-NOT: .note.gnu.property
+
+// NOENDBR:   foo
+// NOENDBR-NOT: endbr
+
+// ENDBR64: endbr64
+// ENDBR32: endbr32
+.text
+.globl  foo
+.type   foo, @function
+foo:
+_CET_ENDBR
+ret
Index: clang/lib/Headers/cet.h
===
--- /dev/null
+++ clang/lib/Headers/cet.h
@@ -0,0 +1,66 @@
+/*===-- cet.h -Control-flow Enforcement Technology  feature ===
+ * Add x86 feature with IBT and/or SHSTK bits to ELF program property if they
+ * are enabled. Otherwise, contents in this header file are unused. This file
+ * is mainly design for assembly source code which want to enable CET.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+#ifndef __CET_H
+#define __CET_H
+
+#ifdef __ASSEMBLER__
+
+#ifndef __CET__
+# define _CET_ENDBR
+#endif
+
+#ifdef __CET__
+
+# ifdef __LP64__
+#  if __CET__ & 0x1
+#define _CET_ENDBR endbr64
+#  else
+#define _CET_ENDBR
+#  endif
+# else
+#  if __CET__ & 0x1
+#define _CET_ENDBR endbr32
+#  else
+#define _CET_ENDBR
+#  endif
+# endif
+
+
+#  ifdef __LP64__
+#   define __PROPERTY_ALIGN 3
+#  else
+#   define __PROPERTY_ALIGN 2
+#  endif
+
+	.pushsection ".note.gnu.property", "a"
+	.p2align __PROPERTY_ALIGN
+	.long 1f - 0f		/* name length.  */
+	.long 4f - 1f		/* data length.  */
+	/* NT_GNU_PROPERTY_TYPE_0.   */
+	.long 5			/* note type.  */
+0:
+	.asciz "GNU"		/* vendor name.  */
+1:
+	.p2align __PROPERTY_ALIGN
+	/* GNU_PROPERTY_X86_FEATURE_1_AND.  */
+	.long 0xc002	/* pr_type.  */
+	.long 3f - 2f		/* pr_datasz.  */
+2:
+	/* GNU_PROPERTY_X86_FEATURE_1_XXX.  */
+	.long __CET__
+3:
+	.p2align __PROPERTY_ALIGN
+4:
+	.popsection
+#endif
+#endif
+#endif
Index: clang/lib/Headers/CMakeLists.txt
===
--- clang/lib/Headers/CMakeLists.txt
+++ clang/lib/Headers/CMakeLists.txt
@@ -46,6 +46,7 @@
   __clang_cuda_math_forward_declares.h
   __clang_cuda_runtime_wrapper.h
   cetintrin.h
+  cet.h
   cldemoteintrin.h
   clzerointrin.h
   cpuid.h
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[PATCH] D79617: Add cet.h for writing CET-enabled assembly code

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added a comment.

@rsmith


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[PATCH] D79617: Add cet.h for writing CET-enabled assembly code

[Xiang Zhang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGe7e84ff24a5f: Add cet.h for writing CET-enabled assembly 
code (authored by xiangzhangllvm).
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
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Files:
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/cet.h
  clang/test/CodeGen/asm-cet.S

Index: clang/test/CodeGen/asm-cet.S
===
--- /dev/null
+++ clang/test/CodeGen/asm-cet.S
@@ -0,0 +1,26 @@
+// RUN: %clang --target=x86_64-pc-linux -fcf-protection  -include cet.h -c %s -o - | llvm-readelf -n | FileCheck %s
+// RUN: %clang --target=x86_64-pc-linux -include cet.h -c %s -o - | llvm-readelf -S | FileCheck %s --check-prefixes=NOCET
+// RUN: %clang --target=x86_64-pc-linux -include cet.h -S %s -o - | FileCheck %s --check-prefixes=NOENDBR
+// RUN: %clang --target=x86_64-pc-linux -fcf-protection  -include cet.h -S %s -o - | FileCheck %s --check-prefixes=ENDBR64
+
+// RUN: %clang --target=i386-pc-linux -fcf-protection  -include cet.h -c %s -o - | llvm-readelf -n | FileCheck %s
+// RUN: %clang --target=i386-pc-linux -include cet.h -c %s -o - | llvm-readelf -S | FileCheck %s --check-prefixes=NOCET
+// RUN: %clang --target=i386-pc-linux -include cet.h -S %s -o - | FileCheck %s --check-prefixes=NOENDBR
+// RUN: %clang --target=i386-pc-linux -fcf-protection  -include cet.h -S %s -o - | FileCheck %s --check-prefixes=ENDBR32
+
+// CHECK: IBT, SHSTK
+
+// NOCET: Section Headers
+// NOCET-NOT: .note.gnu.property
+
+// NOENDBR:   foo
+// NOENDBR-NOT: endbr
+
+// ENDBR64: endbr64
+// ENDBR32: endbr32
+.text
+.globl  foo
+.type   foo, @function
+foo:
+_CET_ENDBR
+ret
Index: clang/lib/Headers/cet.h
===
--- /dev/null
+++ clang/lib/Headers/cet.h
@@ -0,0 +1,66 @@
+/*===-- cet.h -Control-flow Enforcement Technology  feature ===
+ * Add x86 feature with IBT and/or SHSTK bits to ELF program property if they
+ * are enabled. Otherwise, contents in this header file are unused. This file
+ * is mainly design for assembly source code which want to enable CET.
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+#ifndef __CET_H
+#define __CET_H
+
+#ifdef __ASSEMBLER__
+
+#ifndef __CET__
+# define _CET_ENDBR
+#endif
+
+#ifdef __CET__
+
+# ifdef __LP64__
+#  if __CET__ & 0x1
+#define _CET_ENDBR endbr64
+#  else
+#define _CET_ENDBR
+#  endif
+# else
+#  if __CET__ & 0x1
+#define _CET_ENDBR endbr32
+#  else
+#define _CET_ENDBR
+#  endif
+# endif
+
+
+#  ifdef __LP64__
+#   define __PROPERTY_ALIGN 3
+#  else
+#   define __PROPERTY_ALIGN 2
+#  endif
+
+	.pushsection ".note.gnu.property", "a"
+	.p2align __PROPERTY_ALIGN
+	.long 1f - 0f		/* name length.  */
+	.long 4f - 1f		/* data length.  */
+	/* NT_GNU_PROPERTY_TYPE_0.   */
+	.long 5			/* note type.  */
+0:
+	.asciz "GNU"		/* vendor name.  */
+1:
+	.p2align __PROPERTY_ALIGN
+	/* GNU_PROPERTY_X86_FEATURE_1_AND.  */
+	.long 0xc002	/* pr_type.  */
+	.long 3f - 2f		/* pr_datasz.  */
+2:
+	/* GNU_PROPERTY_X86_FEATURE_1_XXX.  */
+	.long __CET__
+3:
+	.p2align __PROPERTY_ALIGN
+4:
+	.popsection
+#endif
+#endif
+#endif
Index: clang/lib/Headers/CMakeLists.txt
===
--- clang/lib/Headers/CMakeLists.txt
+++ clang/lib/Headers/CMakeLists.txt
@@ -46,6 +46,7 @@
   __clang_cuda_math_forward_declares.h
   __clang_cuda_runtime_wrapper.h
   cetintrin.h
+  cet.h
   cldemoteintrin.h
   clzerointrin.h
   cpuid.h
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[PATCH] D77205: [X86] Add TSXLDTRK instructions.

[Xiang Zhang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGa3dc9490004c: [X86] Add TSXLDTRK instructions. (authored by 
tianqing, committed by xiangzhangllvm).

Changed prior to commit:
  https://reviews.llvm.org/D77205?vs=256170=256189#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77205/new/

https://reviews.llvm.org/D77205

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/tsxldtrkintrin.h
  clang/test/CodeGen/x86-tsxldtrk-builtins.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/lib/Support/Host.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
  llvm/test/MC/Disassembler/X86/x86-16.txt
  llvm/test/MC/Disassembler/X86/x86-32.txt
  llvm/test/MC/Disassembler/X86/x86-64.txt
  llvm/test/MC/X86/x86-16.s
  llvm/test/MC/X86/x86-32-coverage.s
  llvm/test/MC/X86/x86-64.s

Index: llvm/test/MC/X86/x86-64.s
===
--- llvm/test/MC/X86/x86-64.s
+++ llvm/test/MC/X86/x86-64.s
@@ -1881,3 +1881,11 @@
 // CHECK: serialize
 // CHECK: encoding: [0x0f,0x01,0xe8]
 serialize
+
+// CHECK: xsusldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: xresldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/X86/x86-32-coverage.s
===
--- llvm/test/MC/X86/x86-32-coverage.s
+++ llvm/test/MC/X86/x86-32-coverage.s
@@ -10880,3 +10880,11 @@
 // CHECK: serialize
 // CHECK: encoding: [0x0f,0x01,0xe8]
 serialize
+
+// CHECK: xsusldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: xresldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/X86/x86-16.s
===
--- llvm/test/MC/X86/x86-16.s
+++ llvm/test/MC/X86/x86-16.s
@@ -1033,3 +1033,11 @@
 // CHECK: serialize
 // CHECK: encoding: [0x0f,0x01,0xe8]
 serialize
+
+// CHECK: xsusldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: xresldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/Disassembler/X86/x86-64.txt
===
--- llvm/test/MC/Disassembler/X86/x86-64.txt
+++ llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -694,3 +694,9 @@
 
 # CHECK: serialize
 0x0f 0x01 0xe8
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/MC/Disassembler/X86/x86-32.txt
===
--- llvm/test/MC/Disassembler/X86/x86-32.txt
+++ llvm/test/MC/Disassembler/X86/x86-32.txt
@@ -946,3 +946,9 @@
 
 # CHECK: serialize
 0x0f 0x01 0xe8
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/MC/Disassembler/X86/x86-16.txt
===
--- llvm/test/MC/Disassembler/X86/x86-16.txt
+++ llvm/test/MC/Disassembler/X86/x86-16.txt
@@ -839,3 +839,9 @@
 
 # CHECK: serialize
 0x0f 0x01 0xe8
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+tsxldtrk | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+tsxldtrk | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mattr=+tsxldtrk | FileCheck %s --check-prefix=X32
+
+define void @test_tsxldtrk() {
+; X64-LABEL: test_tsxldtrk:
+; X64:   # %bb.0: # %entry
+; X64-NEXT:xsusldtrk
+; X64-NEXT:xresldtrk
+; X64-NEXT:retq
+;
+; X86-LABEL: test_tsxldtrk:
+; X86:   # %bb.0: # %entry
+; X86-NEXT:xsusldtrk
+; X86-NEXT:xresldtrk
+; X86-NEXT:retl
+;
+; X32-LABEL: test_tsxldtrk:
+; X32:   # %bb.0: # %entry
+; X32-NEXT:xsusldtrk
+; X32-NEXT:xresldtrk
+; X32-NEXT:retq
+entry:
+   call void @llvm.x86.xsusldtrk()
+   call void @llvm.x86.xresldtrk()
+   ret void
+}
+
+declare void @llvm.x86.xsusldtrk()
+declare void @llvm.x86.xresldtrk()
+
Index: llvm/lib/Target/X86/X86Subtarget.h
===
--- llvm/lib/Target/X86/X86Subtarget.h
+++ llvm/lib/Target/X86/X86Subtarget.h

[PATCH] D77193: [X86] Add SERIALIZE instruction.

[Xiang Zhang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGd08fadd6628a: [X86] Add SERIALIZE instruction. (authored by 
tianqing, committed by xiangzhangllvm).

Changed prior to commit:
  https://reviews.llvm.org/D77193?vs=254114=254447#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77193/new/

https://reviews.llvm.org/D77193

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/serializeintrin.h
  clang/test/CodeGen/x86-serialize-intrin.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/lib/Support/Host.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/X86/serialize-intrinsic.ll
  llvm/test/MC/Disassembler/X86/x86-16.txt
  llvm/test/MC/Disassembler/X86/x86-32.txt
  llvm/test/MC/Disassembler/X86/x86-64.txt
  llvm/test/MC/X86/x86-16.s
  llvm/test/MC/X86/x86-32-coverage.s
  llvm/test/MC/X86/x86-64.s

Index: llvm/test/MC/X86/x86-64.s
===
--- llvm/test/MC/X86/x86-64.s
+++ llvm/test/MC/X86/x86-64.s
@@ -1877,3 +1877,7 @@
 // CHECK: enqcmds 485498096, %rax
 // CHECK: encoding: [0xf3,0x0f,0x38,0xf8,0x04,0x25,0xf0,0x1c,0xf0,0x1c]
 enqcmds 485498096, %rax
+
+// CHECK: serialize
+// CHECK: encoding: [0x0f,0x01,0xe8]
+serialize
Index: llvm/test/MC/X86/x86-32-coverage.s
===
--- llvm/test/MC/X86/x86-32-coverage.s
+++ llvm/test/MC/X86/x86-32-coverage.s
@@ -10876,3 +10876,7 @@
 // CHECK: enqcmds 8128(%bx,%di), %ax
 // CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xf8,0x81,0xc0,0x1f]
 enqcmds 8128(%bx,%di), %ax
+
+// CHECK: serialize
+// CHECK: encoding: [0x0f,0x01,0xe8]
+serialize
Index: llvm/test/MC/X86/x86-16.s
===
--- llvm/test/MC/X86/x86-16.s
+++ llvm/test/MC/X86/x86-16.s
@@ -1029,3 +1029,7 @@
 // CHECK: enqcmds (%edi), %edi
 // CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xf8,0x3f]
 enqcmds (%edi), %edi
+
+// CHECK: serialize
+// CHECK: encoding: [0x0f,0x01,0xe8]
+serialize
Index: llvm/test/MC/Disassembler/X86/x86-64.txt
===
--- llvm/test/MC/Disassembler/X86/x86-64.txt
+++ llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -691,3 +691,6 @@
 
 # CHECK: enqcmds 485498096, %rax
 0xf3,0x0f,0x38,0xf8,0x04,0x25,0xf0,0x1c,0xf0,0x1c
+
+# CHECK: serialize
+0x0f 0x01 0xe8
Index: llvm/test/MC/Disassembler/X86/x86-32.txt
===
--- llvm/test/MC/Disassembler/X86/x86-32.txt
+++ llvm/test/MC/Disassembler/X86/x86-32.txt
@@ -943,3 +943,6 @@
 
 # CHECK: enqcmds 8128(%bx,%di), %ax
 0x67,0xf3,0x0f,0x38,0xf8,0x81,0xc0,0x1f
+
+# CHECK: serialize
+0x0f 0x01 0xe8
Index: llvm/test/MC/Disassembler/X86/x86-16.txt
===
--- llvm/test/MC/Disassembler/X86/x86-16.txt
+++ llvm/test/MC/Disassembler/X86/x86-16.txt
@@ -836,3 +836,6 @@
 
 # CHECK: enqcmds (%edi), %edi
 0x67,0xf3,0x0f,0x38,0xf8,0x3f
+
+# CHECK: serialize
+0x0f 0x01 0xe8
Index: llvm/test/CodeGen/X86/serialize-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/serialize-intrinsic.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+serialize | FileCheck %s --check-prefix=X86_64
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+serialize | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mattr=+serialize | FileCheck %s --check-prefix=X32
+
+define void @test_serialize() {
+; X86_64-LABEL: test_serialize:
+; X86_64:   # %bb.0: # %entry
+; X86_64-NEXT:serialize
+; X86_64-NEXT:retq
+;
+; X86-LABEL: test_serialize:
+; X86:   # %bb.0: # %entry
+; X86-NEXT:serialize
+; X86-NEXT:retl
+;
+; X32-LABEL: test_serialize:
+; X32:   # %bb.0: # %entry
+; X32-NEXT:serialize
+; X32-NEXT:retq
+entry:
+  call void @llvm.x86.serialize()
+  ret void
+}
+
+declare void @llvm.x86.serialize()
Index: llvm/lib/Target/X86/X86Subtarget.h
===
--- llvm/lib/Target/X86/X86Subtarget.h
+++ llvm/lib/Target/X86/X86Subtarget.h
@@ -397,6 +397,9 @@
   /// Processor supports PCONFIG instruction
   bool HasPCONFIG = false;
 
+  /// Processor supports SERIALIZE instruction
+  bool HasSERIALIZE = false;
+
   /// Processor has a single uop BEXTR implementation.
   bool 

[PATCH] D70157: Align branches within 32-Byte boundary

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added a comment.

In D70157#1746793 , @MaskRay wrote:

> On x86, the preferred function alignment is 16 
> (https://github.com/llvm/llvm-project/blob/arcpatch-D70157/llvm/lib/Target/X86/X86ISelLowering.cpp#L1893),
>  which is the default function alignment in text sections. If the 
> cross-boundary decision is made with alignment=32 
> (--x86-align-branch-boundary=32) in mind, and the section alignment is still 
> 16 (not increased to 32 or higher), the linker may place the section at an 
> address which equals 16 modulo 32, the section contents will thus shift by 
> 16. The instructions that do not cross the boundary in the object files may 
> cross the boundary in the linker output. Have you considered increasing the 
> section alignment to 32?
>
> Shall we default to -mbranches-within-32B-boundaries if the specified -march= 
> or -mtune= may be affected by the erratum?


Hi Fangrui, Here will set the section alignment to 32, 
llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp:658


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[PATCH] D70157: Align branches within 32-Byte boundary

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added inline comments.



Comment at: llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h:134
+  /// macro-fusion.
+  inline FirstMFInstKind classifyFirstOpcode(unsigned Opcode) {
+switch (Opcode) {

xiangzhangllvm wrote:
> We rarely put function definition at *.h,  if putting it into 
> X86MacroFusion.cpp will cause compile problem, X86AsmBackend.cpp maybe a good 
> place to put it.
Seems not big function, just many "case", it is fine for me if you don't want 
to change it.


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[PATCH] D70157: Align branches within 32-Byte boundary

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added inline comments.



Comment at: llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h:134
+  /// macro-fusion.
+  inline FirstMFInstKind classifyFirstOpcode(unsigned Opcode) {
+switch (Opcode) {

We rarely put function definition at *.h,  if putting it into 
X86MacroFusion.cpp will cause compile problem, X86AsmBackend.cpp maybe a good 
place to put it.


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[PATCH] D62367: [X86] VP2INTERSECT clang

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm marked 3 inline comments as done.
xiangzhangllvm added a comment.

Done, Thank you very much!


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[PATCH] D62367: [X86] VP2INTERSECT clang

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm updated this revision to Diff 202359.

Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62367/new/

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Files:
  docs/ClangCommandLineReference.rst
  include/clang/Basic/BuiltinsX86.def
  include/clang/Driver/Options.td
  lib/Basic/Targets/X86.cpp
  lib/Basic/Targets/X86.h
  lib/CodeGen/CGBuiltin.cpp
  lib/Headers/CMakeLists.txt
  lib/Headers/avx512vlvp2intersectintrin.h
  lib/Headers/avx512vp2intersectintrin.h
  lib/Headers/immintrin.h
  test/CodeGen/attr-target-x86.c
  test/CodeGen/intel-avx512vlvp2intersect.c
  test/CodeGen/intel-avx512vp2intersect.c
  test/Driver/x86-target-features.c
  test/Preprocessor/x86_target_features.c

Index: test/Preprocessor/x86_target_features.c
===
--- test/Preprocessor/x86_target_features.c
+++ test/Preprocessor/x86_target_features.c
@@ -458,3 +458,13 @@
 
 // AVX512BF16_NOAVX512VL: #define __AVX512BF16__ 1
 
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mavx512vp2intersect -x c -E -dM -o - %s | FileCheck  -check-prefix=VP2INTERSECT %s
+
+// VP2INTERSECT: #define __AVX512F__ 1
+// VP2INTERSECT: #define __AVX512VP2INTERSECT__ 1
+
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-avx512vp2intersect -x c -E -dM -o - %s | FileCheck  -check-prefix=NOVP2INTERSECT %s
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mavx512vp2intersect -mno-avx512f -x c -E -dM -o - %s | FileCheck  -check-prefix=NOVP2INTERSECT %s
+
+// NOVP2INTERSECT-NOT: #define __AVX512VP2INTERSECT__ 1
+
Index: test/Driver/x86-target-features.c
===
--- test/Driver/x86-target-features.c
+++ test/Driver/x86-target-features.c
@@ -125,6 +125,11 @@
 // VBMI2: "-target-feature" "+avx512vbmi2"
 // NO-VBMI2: "-target-feature" "-avx512vbmi2"
 
+// RUN: %clang -target i386-linux-gnu -mavx512vp2intersect %s -### -o %t.o 2>&1 | FileCheck -check-prefix=VP2INTERSECT %s
+// RUN: %clang -target i386-linux-gnu -mno-avx512vp2intersect %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-VP2INTERSECT %s
+// VP2INTERSECT: "-target-feature" "+avx512vp2intersect"
+// NO-VP2INTERSECT: "-target-feature" "-avx512vp2intersect"
+
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mrdpid %s -### -o %t.o 2>&1 | FileCheck -check-prefix=RDPID %s
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-rdpid %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-RDPID %s
 // RDPID: "-target-feature" "+rdpid"
Index: test/CodeGen/intel-avx512vp2intersect.c
===
--- /dev/null
+++ test/CodeGen/intel-avx512vp2intersect.c
@@ -0,0 +1,20 @@
+// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx512vp2intersect -emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 %s -ffreestanding -triple=i386-unknown-unknown -target-feature +avx512vp2intersect -emit-llvm -o - -Wall -Werror | FileCheck %s
+
+#include 
+
+void test_mm512_2intersect_epi32(__m512i a, __m512i b, __mmask16 *m0, __mmask16 *m1) {
+// CHECK-LABEL: test_mm512_2intersect_epi32
+// CHECK: call { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32> %{{.*}}, <16 x i32> %{{.*}})
+// CHECK: extractvalue { <16 x i1>, <16 x i1> } %{{.*}}, 0
+// CHECK: extractvalue { <16 x i1>, <16 x i1> } %{{.*}}, 1
+  _mm512_2intersect_epi32(a, b, m0, m1);
+}
+
+void test_mm512_2intersect_epi64(__m512i a, __m512i b, __mmask8 *m0, __mmask8 *m1) {
+// CHECK-LABEL: test_mm512_2intersect_epi64
+// CHECK: call { <8 x i1>, <8 x i1> } @llvm.x86.avx512.vp2intersect.q.512(<8 x i64> %{{.*}}, <8 x i64> %{{.*}})
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 0
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 1
+  _mm512_2intersect_epi64(a, b, m0, m1);
+}
Index: test/CodeGen/intel-avx512vlvp2intersect.c
===
--- /dev/null
+++ test/CodeGen/intel-avx512vlvp2intersect.c
@@ -0,0 +1,36 @@
+// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx512vp2intersect -target-feature +avx512vl -emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 %s -ffreestanding -triple=i386-unknown-unknown -target-feature +avx512vp2intersect -target-feature +avx512vl -emit-llvm -o - -Wall -Werror | FileCheck %s
+
+#include 
+
+void test_mm256_2intersect_epi32(__m256i a, __m256i b, __mmask8 *m0, __mmask8 *m1) {
+// CHECK-LABEL: test_mm256_2intersect_epi32
+// CHECK: call { <8 x i1>, <8 x i1> } @llvm.x86.avx512.vp2intersect.d.256(<8 x i32> %{{.*}}, <8 x i32> %{{.*}})
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 0
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 1
+  _mm256_2intersect_epi32(a, b, m0, m1);
+}
+
+void test_mm256_2intersect_epi64(__m256i a, __m256i b, __mmask8 *m0, __mmask8 *m1) {
+// CHECK-LABEL: test_mm256_2intersect_epi64
+// CHECK: call { 

[PATCH] D62367: [X86] VP2INTERSECT clang

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added a comment.

Hi Dear friends, could you help merge this patch? Thank you very much!


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[PATCH] D62367: [X86] VP2INTERSECT clang

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm updated this revision to Diff 202350.
xiangzhangllvm added a comment.

rebase


Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62367/new/

https://reviews.llvm.org/D62367

Files:
  docs/ClangCommandLineReference.rst
  include/clang/Basic/BuiltinsX86.def
  include/clang/Driver/Options.td
  lib/Basic/Targets/X86.cpp
  lib/Basic/Targets/X86.h
  lib/CodeGen/CGBuiltin.cpp
  lib/Headers/CMakeLists.txt
  lib/Headers/avx512vlvp2intersectintrin.h
  lib/Headers/avx512vp2intersectintrin.h
  lib/Headers/immintrin.h
  test/CodeGen/attr-target-x86.c
  test/CodeGen/intel-avx512vlvp2intersect.c
  test/CodeGen/intel-avx512vp2intersect.c
  test/Driver/x86-target-features.c
  test/Preprocessor/x86_target_features.c

Index: test/Preprocessor/x86_target_features.c
===
--- test/Preprocessor/x86_target_features.c
+++ test/Preprocessor/x86_target_features.c
@@ -458,3 +458,13 @@
 
 // AVX512BF16_NOAVX512VL: #define __AVX512BF16__ 1
 
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mavx512vp2intersect -x c -E -dM -o - %s | FileCheck  -check-prefix=VP2INTERSECT %s
+
+// VP2INTERSECT: #define __AVX512F__ 1
+// VP2INTERSECT: #define __AVX512VP2INTERSECT__ 1
+
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-avx512vp2intersect -x c -E -dM -o - %s | FileCheck  -check-prefix=NOVP2INTERSECT %s
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mavx512vp2intersect -mno-avx512f -x c -E -dM -o - %s | FileCheck  -check-prefix=NOVP2INTERSECT %s
+
+// NOVP2INTERSECT-NOT: #define __AVX512VP2INTERSECT__ 1
+
Index: test/Driver/x86-target-features.c
===
--- test/Driver/x86-target-features.c
+++ test/Driver/x86-target-features.c
@@ -125,6 +125,11 @@
 // VBMI2: "-target-feature" "+avx512vbmi2"
 // NO-VBMI2: "-target-feature" "-avx512vbmi2"
 
+// RUN: %clang -target i386-linux-gnu -mavx512vp2intersect %s -### -o %t.o 2>&1 | FileCheck -check-prefix=VP2INTERSECT %s
+// RUN: %clang -target i386-linux-gnu -mno-avx512vp2intersect %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-VP2INTERSECT %s
+// VP2INTERSECT: "-target-feature" "+avx512vp2intersect"
+// NO-VP2INTERSECT: "-target-feature" "-avx512vp2intersect"
+
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mrdpid %s -### -o %t.o 2>&1 | FileCheck -check-prefix=RDPID %s
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-rdpid %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-RDPID %s
 // RDPID: "-target-feature" "+rdpid"
Index: test/CodeGen/intel-avx512vp2intersect.c
===
--- /dev/null
+++ test/CodeGen/intel-avx512vp2intersect.c
@@ -0,0 +1,20 @@
+// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx512vp2intersect -emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 %s -ffreestanding -triple=i386-unknown-unknown -target-feature +avx512vp2intersect -emit-llvm -o - -Wall -Werror | FileCheck %s
+
+#include 
+
+void test_mm512_2intersect_epi32(__m512i a, __m512i b, __mmask16 *m0, __mmask16 *m1) {
+// CHECK-LABEL: test_mm512_2intersect_epi32
+// CHECK: call { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32> %{{.*}}, <16 x i32> %{{.*}})
+// CHECK: extractvalue { <16 x i1>, <16 x i1> } %{{.*}}, 0
+// CHECK: extractvalue { <16 x i1>, <16 x i1> } %{{.*}}, 1
+  _mm512_2intersect_epi32(a, b, m0, m1);
+}
+
+void test_mm512_2intersect_epi64(__m512i a, __m512i b, __mmask8 *m0, __mmask8 *m1) {
+// CHECK-LABEL: test_mm512_2intersect_epi64
+// CHECK: call { <8 x i1>, <8 x i1> } @llvm.x86.avx512.vp2intersect.q.512(<8 x i64> %{{.*}}, <8 x i64> %{{.*}})
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 0
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 1
+  _mm512_2intersect_epi64(a, b, m0, m1);
+}
Index: test/CodeGen/intel-avx512vlvp2intersect.c
===
--- /dev/null
+++ test/CodeGen/intel-avx512vlvp2intersect.c
@@ -0,0 +1,36 @@
+// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx512vp2intersect -target-feature +avx512vl -emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 %s -ffreestanding -triple=i386-unknown-unknown -target-feature +avx512vp2intersect -target-feature +avx512vl -emit-llvm -o - -Wall -Werror | FileCheck %s
+
+#include 
+
+void test_mm256_2intersect_epi32(__m256i a, __m256i b, __mmask8 *m0, __mmask8 *m1) {
+// CHECK-LABEL: test_mm256_2intersect_epi32
+// CHECK: call { <8 x i1>, <8 x i1> } @llvm.x86.avx512.vp2intersect.d.256(<8 x i32> %{{.*}}, <8 x i32> %{{.*}})
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 0
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 1
+  _mm256_2intersect_epi32(a, b, m0, m1);
+}
+
+void test_mm256_2intersect_epi64(__m256i a, __m256i b, __mmask8 *m0, __mmask8 *m1) {
+// CHECK-LABEL: 

[PATCH] D62367: [X86] VP2INTERSECT clang

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm updated this revision to Diff 201805.
xiangzhangllvm added a comment.

rebase


Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62367/new/

https://reviews.llvm.org/D62367

Files:
  docs/ClangCommandLineReference.rst
  include/clang/Basic/BuiltinsX86.def
  include/clang/Driver/Options.td
  lib/Basic/Targets/X86.cpp
  lib/Basic/Targets/X86.h
  lib/CodeGen/CGBuiltin.cpp
  lib/Headers/CMakeLists.txt
  lib/Headers/avx512vlvp2intersectintrin.h
  lib/Headers/avx512vp2intersectintrin.h
  lib/Headers/immintrin.h
  test/CodeGen/attr-target-x86.c
  test/CodeGen/intel-avx512vlvp2intersect.c
  test/CodeGen/intel-avx512vp2intersect.c
  test/Driver/x86-target-features.c
  test/Preprocessor/x86_target_features.c

Index: test/Preprocessor/x86_target_features.c
===
--- test/Preprocessor/x86_target_features.c
+++ test/Preprocessor/x86_target_features.c
@@ -458,3 +458,13 @@
 
 // AVX512BF16_NOAVX512VL: #define __AVX512BF16__ 1
 
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mavx512vp2intersect -x c -E -dM -o - %s | FileCheck  -check-prefix=VP2INTERSECT %s
+
+// VP2INTERSECT: #define __AVX512F__ 1
+// VP2INTERSECT: #define __AVX512VP2INTERSECT__ 1
+
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-avx512vp2intersect -x c -E -dM -o - %s | FileCheck  -check-prefix=NOVP2INTERSECT %s
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mavx512vp2intersect -mno-avx512f -x c -E -dM -o - %s | FileCheck  -check-prefix=NOVP2INTERSECT %s
+
+// NOVP2INTERSECT-NOT: #define __AVX512VP2INTERSECT__ 1
+
Index: test/Driver/x86-target-features.c
===
--- test/Driver/x86-target-features.c
+++ test/Driver/x86-target-features.c
@@ -125,6 +125,11 @@
 // VBMI2: "-target-feature" "+avx512vbmi2"
 // NO-VBMI2: "-target-feature" "-avx512vbmi2"
 
+// RUN: %clang -target i386-linux-gnu -mavx512vp2intersect %s -### -o %t.o 2>&1 | FileCheck -check-prefix=VP2INTERSECT %s
+// RUN: %clang -target i386-linux-gnu -mno-avx512vp2intersect %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-VP2INTERSECT %s
+// VP2INTERSECT: "-target-feature" "+avx512vp2intersect"
+// NO-VP2INTERSECT: "-target-feature" "-avx512vp2intersect"
+
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mrdpid %s -### -o %t.o 2>&1 | FileCheck -check-prefix=RDPID %s
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-rdpid %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-RDPID %s
 // RDPID: "-target-feature" "+rdpid"
Index: test/CodeGen/intel-avx512vp2intersect.c
===
--- /dev/null
+++ test/CodeGen/intel-avx512vp2intersect.c
@@ -0,0 +1,20 @@
+// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx512vp2intersect -emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 %s -ffreestanding -triple=i386-unknown-unknown -target-feature +avx512vp2intersect -emit-llvm -o - -Wall -Werror | FileCheck %s
+
+#include 
+
+void test_mm512_2intersect_epi32(__m512i a, __m512i b, __mmask16 *m0, __mmask16 *m1) {
+// CHECK-LABEL: test_mm512_2intersect_epi32
+// CHECK: call { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32> %{{.*}}, <16 x i32> %{{.*}})
+// CHECK: extractvalue { <16 x i1>, <16 x i1> } %{{.*}}, 0
+// CHECK: extractvalue { <16 x i1>, <16 x i1> } %{{.*}}, 1
+  _mm512_2intersect_epi32(a, b, m0, m1);
+}
+
+void test_mm512_2intersect_epi64(__m512i a, __m512i b, __mmask8 *m0, __mmask8 *m1) {
+// CHECK-LABEL: test_mm512_2intersect_epi64
+// CHECK: call { <8 x i1>, <8 x i1> } @llvm.x86.avx512.vp2intersect.q.512(<8 x i64> %{{.*}}, <8 x i64> %{{.*}})
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 0
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 1
+  _mm512_2intersect_epi64(a, b, m0, m1);
+}
Index: test/CodeGen/intel-avx512vlvp2intersect.c
===
--- /dev/null
+++ test/CodeGen/intel-avx512vlvp2intersect.c
@@ -0,0 +1,36 @@
+// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx512vp2intersect -target-feature +avx512vl -emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 %s -ffreestanding -triple=i386-unknown-unknown -target-feature +avx512vp2intersect -target-feature +avx512vl -emit-llvm -o - -Wall -Werror | FileCheck %s
+
+#include 
+
+void test_mm256_2intersect_epi32(__m256i a, __m256i b, __mmask8 *m0, __mmask8 *m1) {
+// CHECK-LABEL: test_mm256_2intersect_epi32
+// CHECK: call { <8 x i1>, <8 x i1> } @llvm.x86.avx512.vp2intersect.d.256(<8 x i32> %{{.*}}, <8 x i32> %{{.*}})
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 0
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 1
+  _mm256_2intersect_epi32(a, b, m0, m1);
+}
+
+void test_mm256_2intersect_epi64(__m256i a, __m256i b, __mmask8 *m0, __mmask8 *m1) {
+// CHECK-LABEL: 

[PATCH] D62367: [X86] VP2INTERSECT clang

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm marked an inline comment as done.
xiangzhangllvm added inline comments.



Comment at: lib/Headers/avx512vlvp2intersectintrin.h:39
+
+static __inline__ void __DEFAULT_FN_ATTRS256
+_mm256_2intersect_epi32(__m256i __a, __m256i __b, __mmask8 *__m0, __mmask8 
*__m1) {

RKSimon wrote:
> craig.topper wrote:
> > xiangzhangllvm wrote:
> > > craig.topper wrote:
> > > > Can you add doxygen comments for the new intrinsics? @RKSimon has been 
> > > > asking for it on other reviews. I forgot to say something in our 
> > > > internal review.
> > > OK! But I really find many ntrinsicxxx.h have no doxygen comments, Is it 
> > > like this format: ?
> > > 
> > > 
> > > ```
> > > /// Rounds up each element of the 128-bit vector of [4 x float] to an
> > > ///integer and returns the rounded values in a 128-bit vector of
> > > ///[4 x float].
> > > ///
> > > /// \headerfile 
> > > ///
> > > /// \code
> > > /// __m128 _mm_ceil_ps(__m128 X);
> > > /// \endcode
> > > ///
> > > /// This intrinsic corresponds to the  VROUNDPS / ROUNDPS  
> > > instruction.
> > > ///
> > > /// \param X
> > > ///A 128-bit vector of [4 x float] values to be rounded up.
> > > /// \returns A 128-bit vector of [4 x float] containing the rounded 
> > > values.
> > > #define _mm_ceil_ps(X)   _mm_round_ps((X), _MM_FROUND_CEIL)
> > > ```
> > > 
> > Yeah that looks right. Someone was kind enough to provide comments for some 
> > of the header files a few years ago, but it wasn't complete. I know avx512* 
> > especially are missing comments.
> The hope is that these will get added as time goes on - usually it just 
> requires a copy + paste of existing comments and tweak for ymm/zmm/whatever.
> 
> New intrinsics should always include documentation since the person adding it 
> is the most likely to be able to correct describe it.
Yes, That make sense!


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[PATCH] D62367: [X86] VP2INTERSECT clang

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm updated this revision to Diff 201618.

Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62367/new/

https://reviews.llvm.org/D62367

Files:
  docs/ClangCommandLineReference.rst
  include/clang/Basic/BuiltinsX86.def
  include/clang/Driver/Options.td
  lib/Basic/Targets/X86.cpp
  lib/Basic/Targets/X86.h
  lib/CodeGen/CGBuiltin.cpp
  lib/Headers/CMakeLists.txt
  lib/Headers/avx512vlvp2intersectintrin.h
  lib/Headers/avx512vp2intersectintrin.h
  lib/Headers/immintrin.h
  test/CodeGen/attr-target-x86.c
  test/CodeGen/intel-avx512vlvp2intersect.c
  test/CodeGen/intel-avx512vp2intersect.c
  test/Driver/x86-target-features.c
  test/Preprocessor/x86_target_features.c

Index: test/Preprocessor/x86_target_features.c
===
--- test/Preprocessor/x86_target_features.c
+++ test/Preprocessor/x86_target_features.c
@@ -458,3 +458,13 @@
 
 // AVX512BF16_NOAVX512VL: #define __AVX512BF16__ 1
 
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mavx512vp2intersect -x c -E -dM -o - %s | FileCheck  -check-prefix=VP2INTERSECT %s
+
+// VP2INTERSECT: #define __AVX512F__ 1
+// VP2INTERSECT: #define __AVX512VP2INTERSECT__ 1
+
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-avx512vp2intersect -x c -E -dM -o - %s | FileCheck  -check-prefix=NOVP2INTERSECT %s
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mavx512vp2intersect -mno-avx512f -x c -E -dM -o - %s | FileCheck  -check-prefix=NOVP2INTERSECT %s
+
+// NOVP2INTERSECT-NOT: #define __AVX512VP2INTERSECT__ 1
+
Index: test/Driver/x86-target-features.c
===
--- test/Driver/x86-target-features.c
+++ test/Driver/x86-target-features.c
@@ -125,6 +125,11 @@
 // VBMI2: "-target-feature" "+avx512vbmi2"
 // NO-VBMI2: "-target-feature" "-avx512vbmi2"
 
+// RUN: %clang -target i386-linux-gnu -mavx512vp2intersect %s -### -o %t.o 2>&1 | FileCheck -check-prefix=VP2INTERSECT %s
+// RUN: %clang -target i386-linux-gnu -mno-avx512vp2intersect %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-VP2INTERSECT %s
+// VP2INTERSECT: "-target-feature" "+avx512vp2intersect"
+// NO-VP2INTERSECT: "-target-feature" "-avx512vp2intersect"
+
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mrdpid %s -### -o %t.o 2>&1 | FileCheck -check-prefix=RDPID %s
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-rdpid %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-RDPID %s
 // RDPID: "-target-feature" "+rdpid"
Index: test/CodeGen/intel-avx512vp2intersect.c
===
--- /dev/null
+++ test/CodeGen/intel-avx512vp2intersect.c
@@ -0,0 +1,20 @@
+// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx512vp2intersect -emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 %s -ffreestanding -triple=i386-unknown-unknown -target-feature +avx512vp2intersect -emit-llvm -o - -Wall -Werror | FileCheck %s
+
+#include 
+
+void test_mm512_2intersect_epi32(__m512i a, __m512i b, __mmask16 *m0, __mmask16 *m1) {
+// CHECK-LABEL: test_mm512_2intersect_epi32
+// CHECK: call { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32> %{{.*}}, <16 x i32> %{{.*}})
+// CHECK: extractvalue { <16 x i1>, <16 x i1> } %{{.*}}, 0
+// CHECK: extractvalue { <16 x i1>, <16 x i1> } %{{.*}}, 1
+  _mm512_2intersect_epi32(a, b, m0, m1);
+}
+
+void test_mm512_2intersect_epi64(__m512i a, __m512i b, __mmask8 *m0, __mmask8 *m1) {
+// CHECK-LABEL: test_mm512_2intersect_epi64
+// CHECK: call { <8 x i1>, <8 x i1> } @llvm.x86.avx512.vp2intersect.q.512(<8 x i64> %{{.*}}, <8 x i64> %{{.*}})
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 0
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 1
+  _mm512_2intersect_epi64(a, b, m0, m1);
+}
Index: test/CodeGen/intel-avx512vlvp2intersect.c
===
--- /dev/null
+++ test/CodeGen/intel-avx512vlvp2intersect.c
@@ -0,0 +1,36 @@
+// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx512vp2intersect -target-feature +avx512vl -emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 %s -ffreestanding -triple=i386-unknown-unknown -target-feature +avx512vp2intersect -target-feature +avx512vl -emit-llvm -o - -Wall -Werror | FileCheck %s
+
+#include 
+
+void test_mm256_2intersect_epi32(__m256i a, __m256i b, __mmask8 *m0, __mmask8 *m1) {
+// CHECK-LABEL: test_mm256_2intersect_epi32
+// CHECK: call { <8 x i1>, <8 x i1> } @llvm.x86.avx512.vp2intersect.d.256(<8 x i32> %{{.*}}, <8 x i32> %{{.*}})
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 0
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 1
+  _mm256_2intersect_epi32(a, b, m0, m1);
+}
+
+void test_mm256_2intersect_epi64(__m256i a, __m256i b, __mmask8 *m0, __mmask8 *m1) {
+// CHECK-LABEL: test_mm256_2intersect_epi64
+// CHECK: call { 

[PATCH] D62367: [X86] VP2INTERSECT clang

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm marked an inline comment as done.
xiangzhangllvm added inline comments.



Comment at: lib/Headers/avx512vlvp2intersectintrin.h:39
+
+static __inline__ void __DEFAULT_FN_ATTRS256
+_mm256_2intersect_epi32(__m256i __a, __m256i __b, __mmask8 *__m0, __mmask8 
*__m1) {

craig.topper wrote:
> Can you add doxygen comments for the new intrinsics? @RKSimon has been asking 
> for it on other reviews. I forgot to say something in our internal review.
OK! But I really find many ntrinsicxxx.h have no doxygen comments, Is it like 
this format: ?


```
/// Rounds up each element of the 128-bit vector of [4 x float] to an
///integer and returns the rounded values in a 128-bit vector of
///[4 x float].
///
/// \headerfile 
///
/// \code
/// __m128 _mm_ceil_ps(__m128 X);
/// \endcode
///
/// This intrinsic corresponds to the  VROUNDPS / ROUNDPS  instruction.
///
/// \param X
///A 128-bit vector of [4 x float] values to be rounded up.
/// \returns A 128-bit vector of [4 x float] containing the rounded values.
#define _mm_ceil_ps(X)   _mm_round_ps((X), _MM_FROUND_CEIL)
```



Repository:
  rC Clang

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[PATCH] D62367: [X86] VP2INTERSECT clang

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm updated this revision to Diff 201611.

Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62367/new/

https://reviews.llvm.org/D62367

Files:
  docs/ClangCommandLineReference.rst
  include/clang/Basic/BuiltinsX86.def
  include/clang/Driver/Options.td
  lib/Basic/Targets/X86.cpp
  lib/Basic/Targets/X86.h
  lib/CodeGen/CGBuiltin.cpp
  lib/Headers/CMakeLists.txt
  lib/Headers/avx512vlvp2intersectintrin.h
  lib/Headers/avx512vp2intersectintrin.h
  lib/Headers/immintrin.h
  test/CodeGen/attr-target-x86.c
  test/CodeGen/intel-avx512vlvp2intersect.c
  test/CodeGen/intel-avx512vp2intersect.c
  test/Driver/x86-target-features.c
  test/Preprocessor/x86_target_features.c

Index: test/Preprocessor/x86_target_features.c
===
--- test/Preprocessor/x86_target_features.c
+++ test/Preprocessor/x86_target_features.c
@@ -458,3 +458,13 @@
 
 // AVX512BF16_NOAVX512VL: #define __AVX512BF16__ 1
 
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mavx512vp2intersect -x c -E -dM -o - %s | FileCheck  -check-prefix=VP2INTERSECT %s
+
+// VP2INTERSECT: #define __AVX512F__ 1
+// VP2INTERSECT: #define __AVX512VP2INTERSECT__ 1
+
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-avx512vp2intersect -x c -E -dM -o - %s | FileCheck  -check-prefix=NOVP2INTERSECT %s
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mavx512vp2intersect -mno-avx512f -x c -E -dM -o - %s | FileCheck  -check-prefix=NOVP2INTERSECT %s
+
+// NOVP2INTERSECT-NOT: #define __AVX512VP2INTERSECT__ 1
+
Index: test/Driver/x86-target-features.c
===
--- test/Driver/x86-target-features.c
+++ test/Driver/x86-target-features.c
@@ -125,6 +125,11 @@
 // VBMI2: "-target-feature" "+avx512vbmi2"
 // NO-VBMI2: "-target-feature" "-avx512vbmi2"
 
+// RUN: %clang -target i386-linux-gnu -mavx512vp2intersect %s -### -o %t.o 2>&1 | FileCheck -check-prefix=VP2INTERSECT %s
+// RUN: %clang -target i386-linux-gnu -mno-avx512vp2intersect %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-VP2INTERSECT %s
+// VP2INTERSECT: "-target-feature" "+avx512vp2intersect"
+// NO-VP2INTERSECT: "-target-feature" "-avx512vp2intersect"
+
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mrdpid %s -### -o %t.o 2>&1 | FileCheck -check-prefix=RDPID %s
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-rdpid %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-RDPID %s
 // RDPID: "-target-feature" "+rdpid"
Index: test/CodeGen/intel-avx512vp2intersect.c
===
--- /dev/null
+++ test/CodeGen/intel-avx512vp2intersect.c
@@ -0,0 +1,20 @@
+// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx512vp2intersect -emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 %s -ffreestanding -triple=i386-unknown-unknown -target-feature +avx512vp2intersect -emit-llvm -o - -Wall -Werror | FileCheck %s
+
+#include 
+
+void test_mm512_2intersect_epi32(__m512i a, __m512i b, __mmask16 *m0, __mmask16 *m1) {
+// CHECK-LABEL: test_mm512_2intersect_epi32
+// CHECK: call { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32> %{{.*}}, <16 x i32> %{{.*}})
+// CHECK: extractvalue { <16 x i1>, <16 x i1> } %{{.*}}, 0
+// CHECK: extractvalue { <16 x i1>, <16 x i1> } %{{.*}}, 1
+  _mm512_2intersect_epi32(a, b, m0, m1);
+}
+
+void test_mm512_2intersect_epi64(__m512i a, __m512i b, __mmask8 *m0, __mmask8 *m1) {
+// CHECK-LABEL: test_mm512_2intersect_epi64
+// CHECK: call { <8 x i1>, <8 x i1> } @llvm.x86.avx512.vp2intersect.q.512(<8 x i64> %{{.*}}, <8 x i64> %{{.*}})
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 0
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 1
+  _mm512_2intersect_epi64(a, b, m0, m1);
+}
Index: test/CodeGen/intel-avx512vlvp2intersect.c
===
--- /dev/null
+++ test/CodeGen/intel-avx512vlvp2intersect.c
@@ -0,0 +1,36 @@
+// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx512vp2intersect -target-feature +avx512vl -emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 %s -ffreestanding -triple=i386-unknown-unknown -target-feature +avx512vp2intersect -target-feature +avx512vl -emit-llvm -o - -Wall -Werror | FileCheck %s
+
+#include 
+
+void test_mm256_2intersect_epi32(__m256i a, __m256i b, __mmask8 *m0, __mmask8 *m1) {
+// CHECK-LABEL: test_mm256_2intersect_epi32
+// CHECK: call { <8 x i1>, <8 x i1> } @llvm.x86.avx512.vp2intersect.d.256(<8 x i32> %{{.*}}, <8 x i32> %{{.*}})
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 0
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 1
+  _mm256_2intersect_epi32(a, b, m0, m1);
+}
+
+void test_mm256_2intersect_epi64(__m256i a, __m256i b, __mmask8 *m0, __mmask8 *m1) {
+// CHECK-LABEL: test_mm256_2intersect_epi64
+// CHECK: call { 

[PATCH] D62367: [X86] VP2INTERSECT clang

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm updated this revision to Diff 201137.
xiangzhangllvm added a comment.

rebase


Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62367/new/

https://reviews.llvm.org/D62367

Files:
  docs/ClangCommandLineReference.rst
  include/clang/Basic/BuiltinsX86.def
  include/clang/Driver/Options.td
  lib/Basic/Targets/X86.cpp
  lib/Basic/Targets/X86.h
  lib/CodeGen/CGBuiltin.cpp
  lib/Headers/CMakeLists.txt
  lib/Headers/avx512vlvp2intersectintrin.h
  lib/Headers/avx512vp2intersectintrin.h
  lib/Headers/immintrin.h
  test/CodeGen/attr-target-x86.c
  test/CodeGen/intel-avx512vlvp2intersect.c
  test/CodeGen/intel-avx512vp2intersect.c
  test/Driver/x86-target-features.c
  test/Preprocessor/x86_target_features.c

Index: test/Preprocessor/x86_target_features.c
===
--- test/Preprocessor/x86_target_features.c
+++ test/Preprocessor/x86_target_features.c
@@ -458,3 +458,13 @@
 
 // AVX512BF16_NOAVX512VL: #define __AVX512BF16__ 1
 
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mavx512vp2intersect -x c -E -dM -o - %s | FileCheck  -check-prefix=VP2INTERSECT %s
+
+// VP2INTERSECT: #define __AVX512F__ 1
+// VP2INTERSECT: #define __AVX512VP2INTERSECT__ 1
+
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-avx512vp2intersect -x c -E -dM -o - %s | FileCheck  -check-prefix=NOVP2INTERSECT %s
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mavx512vp2intersect -mno-avx512f -x c -E -dM -o - %s | FileCheck  -check-prefix=NOVP2INTERSECT %s
+
+// NOVP2INTERSECT-NOT: #define __AVX512VP2INTERSECT__ 1
+
Index: test/Driver/x86-target-features.c
===
--- test/Driver/x86-target-features.c
+++ test/Driver/x86-target-features.c
@@ -125,6 +125,11 @@
 // VBMI2: "-target-feature" "+avx512vbmi2"
 // NO-VBMI2: "-target-feature" "-avx512vbmi2"
 
+// RUN: %clang -target i386-linux-gnu -mavx512vp2intersect %s -### -o %t.o 2>&1 | FileCheck -check-prefix=VP2INTERSECT %s
+// RUN: %clang -target i386-linux-gnu -mno-avx512vp2intersect %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-VP2INTERSECT %s
+// VP2INTERSECT: "-target-feature" "+avx512vp2intersect"
+// NO-VP2INTERSECT: "-target-feature" "-avx512vp2intersect"
+
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mrdpid %s -### -o %t.o 2>&1 | FileCheck -check-prefix=RDPID %s
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-rdpid %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-RDPID %s
 // RDPID: "-target-feature" "+rdpid"
Index: test/CodeGen/intel-avx512vp2intersect.c
===
--- /dev/null
+++ test/CodeGen/intel-avx512vp2intersect.c
@@ -0,0 +1,20 @@
+// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx512vp2intersect -emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 %s -ffreestanding -triple=i386-unknown-unknown -target-feature +avx512vp2intersect -emit-llvm -o - -Wall -Werror | FileCheck %s
+
+#include 
+
+void test_mm512_2intersect_epi32(__m512i a, __m512i b, __mmask16 *m0, __mmask16 *m1) {
+// CHECK-LABEL: test_mm512_2intersect_epi32
+// CHECK: call { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32> %{{.*}}, <16 x i32> %{{.*}})
+// CHECK: extractvalue { <16 x i1>, <16 x i1> } %{{.*}}, 0
+// CHECK: extractvalue { <16 x i1>, <16 x i1> } %{{.*}}, 1
+  _mm512_2intersect_epi32(a, b, m0, m1);
+}
+
+void test_mm512_2intersect_epi64(__m512i a, __m512i b, __mmask8 *m0, __mmask8 *m1) {
+// CHECK-LABEL: test_mm512_2intersect_epi64
+// CHECK: call { <8 x i1>, <8 x i1> } @llvm.x86.avx512.vp2intersect.q.512(<8 x i64> %{{.*}}, <8 x i64> %{{.*}})
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 0
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 1
+  _mm512_2intersect_epi64(a, b, m0, m1);
+}
Index: test/CodeGen/intel-avx512vlvp2intersect.c
===
--- /dev/null
+++ test/CodeGen/intel-avx512vlvp2intersect.c
@@ -0,0 +1,36 @@
+// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx512vp2intersect -target-feature +avx512vl -emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 %s -ffreestanding -triple=i386-unknown-unknown -target-feature +avx512vp2intersect -target-feature +avx512vl -emit-llvm -o - -Wall -Werror | FileCheck %s
+
+#include 
+
+void test_mm256_2intersect_epi32(__m256i a, __m256i b, __mmask8 *m0, __mmask8 *m1) {
+// CHECK-LABEL: test_mm256_2intersect_epi32
+// CHECK: call { <8 x i1>, <8 x i1> } @llvm.x86.avx512.vp2intersect.d.256(<8 x i32> %{{.*}}, <8 x i32> %{{.*}})
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 0
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 1
+  _mm256_2intersect_epi32(a, b, m0, m1);
+}
+
+void test_mm256_2intersect_epi64(__m256i a, __m256i b, __mmask8 *m0, __mmask8 *m1) {
+// CHECK-LABEL: 

[PATCH] D62367: VP2INTERSECT clang

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm created this revision.
xiangzhangllvm added reviewers: craig.topper, LuoYuanke, annita.zhang, pengfei.
Herald added subscribers: cfe-commits, mgorny.
Herald added a project: clang.

Support intel AVX512 VP2INTERSECT instructions in clang


Repository:
  rC Clang

https://reviews.llvm.org/D62367

Files:
  docs/ClangCommandLineReference.rst
  include/clang/Basic/BuiltinsX86.def
  include/clang/Driver/Options.td
  lib/Basic/Targets/X86.cpp
  lib/Basic/Targets/X86.h
  lib/CodeGen/CGBuiltin.cpp
  lib/Headers/CMakeLists.txt
  lib/Headers/avx512vlvp2intersectintrin.h
  lib/Headers/avx512vp2intersectintrin.h
  lib/Headers/immintrin.h
  test/CodeGen/attr-target-x86.c
  test/CodeGen/intel-avx512vlvp2intersect.c
  test/CodeGen/intel-avx512vp2intersect.c
  test/Driver/x86-target-features.c
  test/Preprocessor/x86_target_features.c

Index: test/Preprocessor/x86_target_features.c
===
--- test/Preprocessor/x86_target_features.c
+++ test/Preprocessor/x86_target_features.c
@@ -458,3 +458,13 @@
 
 // AVX512BF16_NOAVX512VL: #define __AVX512BF16__ 1
 
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mavx512vp2intersect -x c -E -dM -o - %s | FileCheck  -check-prefix=VP2INTERSECT %s
+
+// VP2INTERSECT: #define __AVX512F__ 1
+// VP2INTERSECT: #define __AVX512VP2INTERSECT__ 1
+
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-avx512vp2intersect -x c -E -dM -o - %s | FileCheck  -check-prefix=NOVP2INTERSECT %s
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mavx512vp2intersect -mno-avx512f -x c -E -dM -o - %s | FileCheck  -check-prefix=NOVP2INTERSECT %s
+
+// NOVP2INTERSECT-NOT: #define __AVX512VP2INTERSECT__ 1
+
Index: test/Driver/x86-target-features.c
===
--- test/Driver/x86-target-features.c
+++ test/Driver/x86-target-features.c
@@ -125,6 +125,11 @@
 // VBMI2: "-target-feature" "+avx512vbmi2"
 // NO-VBMI2: "-target-feature" "-avx512vbmi2"
 
+// RUN: %clang -target i386-linux-gnu -mavx512vp2intersect %s -### -o %t.o 2>&1 | FileCheck -check-prefix=VP2INTERSECT %s
+// RUN: %clang -target i386-linux-gnu -mno-avx512vp2intersect %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-VP2INTERSECT %s
+// VP2INTERSECT: "-target-feature" "+avx512vp2intersect"
+// NO-VP2INTERSECT: "-target-feature" "-avx512vp2intersect"
+
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mrdpid %s -### -o %t.o 2>&1 | FileCheck -check-prefix=RDPID %s
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-rdpid %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-RDPID %s
 // RDPID: "-target-feature" "+rdpid"
Index: test/CodeGen/intel-avx512vp2intersect.c
===
--- /dev/null
+++ test/CodeGen/intel-avx512vp2intersect.c
@@ -0,0 +1,20 @@
+// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx512vp2intersect -emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 %s -ffreestanding -triple=i386-unknown-unknown -target-feature +avx512vp2intersect -emit-llvm -o - -Wall -Werror | FileCheck %s
+
+#include 
+
+void test_mm512_2intersect_epi32(__m512i a, __m512i b, __mmask16 *m0, __mmask16 *m1) {
+// CHECK-LABEL: test_mm512_2intersect_epi32
+// CHECK: call { <16 x i1>, <16 x i1> } @llvm.x86.avx512.vp2intersect.d.512(<16 x i32> %{{.*}}, <16 x i32> %{{.*}})
+// CHECK: extractvalue { <16 x i1>, <16 x i1> } %{{.*}}, 0
+// CHECK: extractvalue { <16 x i1>, <16 x i1> } %{{.*}}, 1
+  _mm512_2intersect_epi32(a, b, m0, m1);
+}
+
+void test_mm512_2intersect_epi64(__m512i a, __m512i b, __mmask8 *m0, __mmask8 *m1) {
+// CHECK-LABEL: test_mm512_2intersect_epi64
+// CHECK: call { <8 x i1>, <8 x i1> } @llvm.x86.avx512.vp2intersect.q.512(<8 x i64> %{{.*}}, <8 x i64> %{{.*}})
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 0
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 1
+  _mm512_2intersect_epi64(a, b, m0, m1);
+}
Index: test/CodeGen/intel-avx512vlvp2intersect.c
===
--- /dev/null
+++ test/CodeGen/intel-avx512vlvp2intersect.c
@@ -0,0 +1,36 @@
+// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx512vp2intersect -target-feature +avx512vl -emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 %s -ffreestanding -triple=i386-unknown-unknown -target-feature +avx512vp2intersect -target-feature +avx512vl -emit-llvm -o - -Wall -Werror | FileCheck %s
+
+#include 
+
+void test_mm256_2intersect_epi32(__m256i a, __m256i b, __mmask8 *m0, __mmask8 *m1) {
+// CHECK-LABEL: test_mm256_2intersect_epi32
+// CHECK: call { <8 x i1>, <8 x i1> } @llvm.x86.avx512.vp2intersect.d.256(<8 x i32> %{{.*}}, <8 x i32> %{{.*}})
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 0
+// CHECK: extractvalue { <8 x i1>, <8 x i1> } %{{.*}}, 1
+  _mm256_2intersect_epi32(a, b, m0, m1);
+}
+
+void 

[PATCH] D62115: fix a issue that clang is incompatible with gcc with -H option.

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added inline comments.



Comment at: lib/Frontend/HeaderIncludeGen.cpp:55
+  // Simplify Filename that starts with "./"
+  if (Filename.startswith("./"));
+Filename=Filename.substr(2);

Need remove ";" ? 


Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62115/new/

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[PATCH] D56990: Bugfix for Replacement of tied operand of inline asm

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added a comment.

In D56990#1426977 , @efriedma wrote:

> LGTM; I'll merge it tonight or tomorrow.


Thank you very much!


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[PATCH] D56990: Bugfix for Replacement of tied operand of inline asm

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added a comment.

We found may tests failed about this issue.
I hope It can be committed.
Thank you very much!


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[PATCH] D56990: Bugfix for Replacement of tied operand of inline asm

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added a comment.

Hi, efriedma
could you help he commit this patch?
Thank you very much!


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[PATCH] D56990: Bugfix for Replacement of tied operand of inline asm

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm updated this revision to Diff 189979.

Repository:
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Files:
  lib/CodeGen/CGStmt.cpp
  test/CodeGen/asm-inout.c


Index: test/CodeGen/asm-inout.c
===
--- test/CodeGen/asm-inout.c
+++ test/CodeGen/asm-inout.c
@@ -46,3 +46,12 @@
   asm ("pmulhuw %1, %0\n\t" : "+y" (__A) : "y" (__B));
   return __A;
 }
+
+// CHECK: @test6
+int test6(void) {
+  typedef unsigned char __attribute__((vector_size(8))) _m64u8;
+  _m64u8 __attribute__((aligned(16))) Mu8_0, __attribute__((aligned(16))) 
Mu8_1;
+  // CHECK: call x86_mmx asm "nop", "=y,0,~{dirflag},~{fpsr},~{flags}"(x86_mmx 
%1)
+  asm ("nop" : "=y"(Mu8_1 ) : "0"(Mu8_0 ));
+  return 0;
+}
Index: lib/CodeGen/CGStmt.cpp
===
--- lib/CodeGen/CGStmt.cpp
+++ lib/CodeGen/CGStmt.cpp
@@ -1932,6 +1932,9 @@
   std::vector InOutArgs;
   std::vector InOutArgTypes;
 
+  // Keep track of out constraints for tied input operand.
+  std::vector OutputConstraints;
+
   // An inline asm can be marked readonly if it meets the following conditions:
   //  - it doesn't have any sideeffects
   //  - it doesn't clobber memory
@@ -1954,7 +1957,7 @@
 OutputConstraint = AddVariableConstraints(OutputConstraint, *OutExpr,
   getTarget(), CGM, S,
   Info.earlyClobber());
-
+OutputConstraints.push_back(OutputConstraint);
 LValue Dest = EmitLValue(OutExpr);
 if (!Constraints.empty())
   Constraints += ',';
@@ -2072,6 +2075,7 @@
 InputConstraint, *InputExpr->IgnoreParenNoopCasts(getContext()),
 getTarget(), CGM, S, false /* No EarlyClobber */);
 
+std::string ReplaceConstraint (InputConstraint);
 llvm::Value *Arg = EmitAsmInput(Info, InputExpr, Constraints);
 
 // If this input argument is tied to a larger output result, extend the
@@ -2099,9 +2103,11 @@
   Arg = Builder.CreateFPExt(Arg, OutputTy);
 }
   }
+  // Deal with the tied operands' constraint code in adjustInlineAsmType.
+  ReplaceConstraint = OutputConstraints[Output];
 }
 if (llvm::Type* AdjTy =
-  getTargetHooks().adjustInlineAsmType(*this, InputConstraint,
+  getTargetHooks().adjustInlineAsmType(*this, ReplaceConstraint,
Arg->getType()))
   Arg = Builder.CreateBitCast(Arg, AdjTy);
 else


Index: test/CodeGen/asm-inout.c
===
--- test/CodeGen/asm-inout.c
+++ test/CodeGen/asm-inout.c
@@ -46,3 +46,12 @@
   asm ("pmulhuw %1, %0\n\t" : "+y" (__A) : "y" (__B));
   return __A;
 }
+
+// CHECK: @test6
+int test6(void) {
+  typedef unsigned char __attribute__((vector_size(8))) _m64u8;
+  _m64u8 __attribute__((aligned(16))) Mu8_0, __attribute__((aligned(16))) Mu8_1;
+  // CHECK: call x86_mmx asm "nop", "=y,0,~{dirflag},~{fpsr},~{flags}"(x86_mmx %1)
+  asm ("nop" : "=y"(Mu8_1 ) : "0"(Mu8_0 ));
+  return 0;
+}
Index: lib/CodeGen/CGStmt.cpp
===
--- lib/CodeGen/CGStmt.cpp
+++ lib/CodeGen/CGStmt.cpp
@@ -1932,6 +1932,9 @@
   std::vector InOutArgs;
   std::vector InOutArgTypes;
 
+  // Keep track of out constraints for tied input operand.
+  std::vector OutputConstraints;
+
   // An inline asm can be marked readonly if it meets the following conditions:
   //  - it doesn't have any sideeffects
   //  - it doesn't clobber memory
@@ -1954,7 +1957,7 @@
 OutputConstraint = AddVariableConstraints(OutputConstraint, *OutExpr,
   getTarget(), CGM, S,
   Info.earlyClobber());
-
+OutputConstraints.push_back(OutputConstraint);
 LValue Dest = EmitLValue(OutExpr);
 if (!Constraints.empty())
   Constraints += ',';
@@ -2072,6 +2075,7 @@
 InputConstraint, *InputExpr->IgnoreParenNoopCasts(getContext()),
 getTarget(), CGM, S, false /* No EarlyClobber */);
 
+std::string ReplaceConstraint (InputConstraint);
 llvm::Value *Arg = EmitAsmInput(Info, InputExpr, Constraints);
 
 // If this input argument is tied to a larger output result, extend the
@@ -2099,9 +2103,11 @@
   Arg = Builder.CreateFPExt(Arg, OutputTy);
 }
   }
+  // Deal with the tied operands' constraint code in adjustInlineAsmType.
+  ReplaceConstraint = OutputConstraints[Output];
 }
 if (llvm::Type* AdjTy =
-  getTargetHooks().adjustInlineAsmType(*this, InputConstraint,
+  getTargetHooks().adjustInlineAsmType(*this, ReplaceConstraint,
Arg->getType()))
   Arg = Builder.CreateBitCast(Arg, AdjTy);
 else
___

[PATCH] D56990: Bugfix for Replacement of tied operand of inline asm

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added a comment.

Thank you, efriedma
But but the LLVM and Clang are different projects, I can commit the change at 
one time.
I 'll update the patch for clang first.


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[PATCH] D56990: Bugfix for Replacement of tied operand of inline asm

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added a comment.

!!! Hi, dear efriedma, very sorry! I just saw your reply.
line 2093: getTargetHooks().adjustInlineAsmType(... InputConstraint,...)  will 
just deal with the constrain string,  and it can't check the TiedOperand in the 
function.
So, this will make inconsistent adjust for the operand and its tied operand.
The error will not be found in the IR files, it will cause back end error. like:
"error in backend: Unsupported asm: input constraint with a matching output 
constraint of incompatible type!"

Please refer the adjustInlineAsmType() function, it will call the following 
function

  static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction ,
StringRef Constraint,
llvm::Type* Ty) {
bool IsMMXCons = llvm::StringSwitch(Constraint)
   .Cases("y", "", "^Ym", true)
   .Default(false);
if (IsMMXCons && Ty->isVectorTy()) {
  if (cast(Ty)->getBitWidth() != 64) {
// Invalid MMX constraint
return nullptr;
  }
  return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
}
// No operation needed
return Ty;
  }




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[PATCH] D56990: Bugfix for Replacement of tied operand of inline asm

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm added a comment.

Hi dears,  Could you please help me merge the patch. Thank you!


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[PATCH] D56990: Bugfix for Replacement of tied operand of inline asm

[Xiang Zhang via Phabricator via cfe-commits]

xiangzhangllvm created this revision.
xiangzhangllvm added reviewers: craig.topper, smaslov, LuoYuanke.
xiangzhangllvm added a project: clang.
Herald added subscribers: cfe-commits, eraman.

The constraint "0" in the following asm did not consider the its relationship 
with "=y" when try to replace the type of the operands.

asm ("nop" : "=y"(Mu8_1 ) : "0"(Mu8_0 ));

test case:

typedef unsigned char _attribute_((vector_size(8))) _m64u8;
static int _isFailed = 0;

int main(void){
 _m64u8 __attribute__((aligned(16))) Mu8_0, __attribute__((aligned(16))) Mu8_1;
 asm ("nop" : "=y"(Mu8_1 ) : "0"(Mu8_0 ));
 return 0;
 }


Repository:
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Files:
  lib/CodeGen/CGStmt.cpp
  test/Sema/inline-asm-x86-constraint.c


Index: test/Sema/inline-asm-x86-constraint.c
===
--- /dev/null
+++ test/Sema/inline-asm-x86-constraint.c
@@ -0,0 +1,9 @@
+// REQUIRES: x86-registered-target
+// RUN: %clang_cc1  %s -o %t
+typedef unsigned char __attribute__((vector_size(8))) _m64u8;
+
+int main(void) {
+  _m64u8 __attribute__((aligned(16))) Mu8_0, __attribute__((aligned(16))) 
Mu8_1;
+  asm ("nop" : "=y"(Mu8_1 ) : "0"(Mu8_0 ));
+  return 0;
+}
Index: lib/CodeGen/CGStmt.cpp
===
--- lib/CodeGen/CGStmt.cpp
+++ lib/CodeGen/CGStmt.cpp
@@ -1915,6 +1915,9 @@
   std::vector InOutArgs;
   std::vector InOutArgTypes;
 
+  // Keep track of out constraints for tied input operand.
+  std::vector OutputConstraints;
+
   // An inline asm can be marked readonly if it meets the following conditions:
   //  - it doesn't have any sideeffects
   //  - it doesn't clobber memory
@@ -1937,7 +1940,7 @@
 OutputConstraint = AddVariableConstraints(OutputConstraint, *OutExpr,
   getTarget(), CGM, S,
   Info.earlyClobber());
-
+OutputConstraints.push_back(OutputConstraint);
 LValue Dest = EmitLValue(OutExpr);
 if (!Constraints.empty())
   Constraints += ',';
@@ -2055,6 +2058,7 @@
 InputConstraint, *InputExpr->IgnoreParenNoopCasts(getContext()),
 getTarget(), CGM, S, false /* No EarlyClobber */);
 
+std::string ReplaceConstraint (InputConstraint);
 llvm::Value *Arg = EmitAsmInput(Info, InputExpr, Constraints);
 
 // If this input argument is tied to a larger output result, extend the
@@ -2082,9 +2086,11 @@
   Arg = Builder.CreateFPExt(Arg, OutputTy);
 }
   }
+  // Deal with the tied operands' constraint code in adjustInlineAsmType.
+  ReplaceConstraint = OutputConstraints[Output];
 }
 if (llvm::Type* AdjTy =
-  getTargetHooks().adjustInlineAsmType(*this, InputConstraint,
+  getTargetHooks().adjustInlineAsmType(*this, ReplaceConstraint,
Arg->getType()))
   Arg = Builder.CreateBitCast(Arg, AdjTy);
 else


Index: test/Sema/inline-asm-x86-constraint.c
===
--- /dev/null
+++ test/Sema/inline-asm-x86-constraint.c
@@ -0,0 +1,9 @@
+// REQUIRES: x86-registered-target
+// RUN: %clang_cc1  %s -o %t
+typedef unsigned char __attribute__((vector_size(8))) _m64u8;
+
+int main(void) {
+  _m64u8 __attribute__((aligned(16))) Mu8_0, __attribute__((aligned(16))) Mu8_1;
+  asm ("nop" : "=y"(Mu8_1 ) : "0"(Mu8_0 ));
+  return 0;
+}
Index: lib/CodeGen/CGStmt.cpp
===
--- lib/CodeGen/CGStmt.cpp
+++ lib/CodeGen/CGStmt.cpp
@@ -1915,6 +1915,9 @@
   std::vector InOutArgs;
   std::vector InOutArgTypes;
 
+  // Keep track of out constraints for tied input operand.
+  std::vector OutputConstraints;
+
   // An inline asm can be marked readonly if it meets the following conditions:
   //  - it doesn't have any sideeffects
   //  - it doesn't clobber memory
@@ -1937,7 +1940,7 @@
 OutputConstraint = AddVariableConstraints(OutputConstraint, *OutExpr,
   getTarget(), CGM, S,
   Info.earlyClobber());
-
+OutputConstraints.push_back(OutputConstraint);
 LValue Dest = EmitLValue(OutExpr);
 if (!Constraints.empty())
   Constraints += ',';
@@ -2055,6 +2058,7 @@
 InputConstraint, *InputExpr->IgnoreParenNoopCasts(getContext()),
 getTarget(), CGM, S, false /* No EarlyClobber */);
 
+std::string ReplaceConstraint (InputConstraint);
 llvm::Value *Arg = EmitAsmInput(Info, InputExpr, Constraints);
 
 // If this input argument is tied to a larger output result, extend the
@@ -2082,9 +2086,11 @@
   Arg = Builder.CreateFPExt(Arg, OutputTy);
 }
   }
+  // Deal with the tied operands' constraint code in adjustInlineAsmType.
+  ReplaceConstraint = OutputConstraints[Output];
 }
 if (llvm::Type* AdjTy =
-