[PATCH] D119530: [RISCV] Add combination crypto extensions in ISAInfo

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added a comment.

Friendly ping @VincentWu ;)
Any comments to the latest response?


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[PATCH] D119530: [RISCV] Add combination crypto extensions in ISAInfo

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 411014.
eopXD added a comment.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Add test for clang.


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Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/CodeGen/RISCV/attributes.ll

Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -33,6 +33,9 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zks %s -o - | FileCheck --check-prefix=RV32ZKS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zkt %s -o - | FileCheck --check-prefix=RV32ZKT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zk %s -o - | FileCheck --check-prefix=RV32ZK %s
+; RUN: llc -mtriple=riscv32 -mattr=+zkn,+zkr,+zkt %s -o - | FileCheck --check-prefix=RV32COMBINEINTOZK %s
+; RUN: llc -mtriple=riscv32 -mattr=+zbkb,+zbkc,+zbkx,+zkne,+zknd,+zknh %s -o - | FileCheck --check-prefix=RV32COMBINEINTOZKN %s
+; RUN: llc -mtriple=riscv32 -mattr=+zbkb,+zbkc,+zbkx,+zksed,+zksh %s -o - | FileCheck --check-prefix=RV32COMBINEINTOZKS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
@@ -66,6 +69,9 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zks %s -o - | FileCheck --check-prefix=RV64ZKS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zkt %s -o - | FileCheck --check-prefix=RV64ZKT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zk %s -o - | FileCheck --check-prefix=RV64ZK %s
+; RUN: llc -mtriple=riscv64 -mattr=+zkn,+zkr,+zkt %s -o - | FileCheck --check-prefix=RV64COMBINEINTOZK %s
+; RUN: llc -mtriple=riscv64 -mattr=+zbkb,+zbkc,+zbkx,+zkne,+zknd,+zknh %s -o - | FileCheck --check-prefix=RV64COMBINEINTOZKN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zbkb,+zbkc,+zbkx,+zksed,+zksh %s -o - | FileCheck --check-prefix=RV64COMBINEINTOZKS %s
 
 ; RV32M: .attribute 5, "rv32i2p0_m2p0"
 ; RV32A: .attribute 5, "rv32i2p0_a2p0"
@@ -100,6 +106,9 @@
 ; RV32ZKS: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
 ; RV32ZKT: .attribute 5, "rv32i2p0_zkt1p0"
 ; RV32ZK: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
+; RV32COMBINEINTOZK: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
+; RV32COMBINEINTOZKN: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
+; RV32COMBINEINTOZKS: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
@@ -134,6 +143,9 @@
 ; RV64ZKS: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
 ; RV64ZKT: .attribute 5, "rv64i2p0_zkt1p0"
 ; RV64ZK: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
+; RV64COMBINEINTOZK: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
+; RV64COMBINEINTOZKN: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
+; RV64COMBINEINTOZKS: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -828,6 +828,38 @@
   }
 }
 
+struct CombinedExtsEntry {
+  StringLiteral CombineExt;
+  ArrayRef RequiredExts;
+};
+
+static constexpr CombinedExtsEntry CombineIntoExts[] = {
+{{"zk"}, {ImpliedExtsZk}},
+{{"zkn"}, {ImpliedExtsZkn}},
+{{"zks"}, {ImpliedExtsZks}},
+};
+
+void RISCVISAInfo::updateCombination() {
+  bool IsNewCombine = false;
+  do {
+IsNewCombine = false;
+for (CombinedExtsEntry CombineIntoExt : CombineIntoExts) {
+  auto CombineExt = CombineIntoExt.CombineExt;
+  auto RequiredExts = CombineIntoExt.RequiredExts;
+  if (hasExtension(CombineExt))
+continue;
+  bool IsAllRequiredFeatureExist = true;
+  for (const char *Ext : RequiredExts)
+IsAllRequiredFeatureExist &= hasExtension(Ext);
+  if (IsAllRequiredFeatureExist) {
+auto Version = findDefaultVersion(CombineExt);
+addExtension(CombineExt, Version->Major, Version->Minor);
+IsNewCombine = true;
+  }
+}
+  } while (IsNewCombine);
+}
+
 void RISCVISAInfo::updateFLen() {
   FLen = 0;
   // TODO: Handle q extension.
@@ -906,6 +938,7 @@
 llvm::Expected>
 RISCVISAInfo::postProcessAndChecking(std::unique_ptr &) {
   ISAInfo->updateImplication();
+  

[PATCH] D117989: [RISCV] Add the passthru operand for RVV nomask binary intrinsics.

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:180
 
+  // The nomask intrinsic IR have the passthru operand.
+  bit HasNoMaskPassThru = false;

eopXD wrote:
> Nit: V-spec prefers to call instructions without masking operands "unmasked 
> instructions"? Maybe a RFC patch later?
I mean an NFC patch.


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[PATCH] D117989: [RISCV] Add the passthru operand for RVV nomask binary intrinsics.

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:180
 
+  // The nomask intrinsic IR have the passthru operand.
+  bit HasNoMaskPassThru = false;

Nit: V-spec prefers to call instructions without masking operands "unmasked 
instructions"? Maybe a RFC patch later?


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[PATCH] D120297: [Driver][RISCV] Add missing rv64 test case

[Yueh-Ting Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG8b62f19f27d4: [Driver][RISCV] Add missing rv64 test case 
(authored by eopXD).

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Files:
  clang/test/Driver/riscv-default-features.c


Index: clang/test/Driver/riscv-default-features.c
===
--- clang/test/Driver/riscv-default-features.c
+++ clang/test/Driver/riscv-default-features.c
@@ -1,4 +1,5 @@
 // RUN: %clang -target riscv32-unknown-elf -S -emit-llvm %s -o - | FileCheck 
%s -check-prefix=RV32
+// RUN: %clang -target riscv64-unknown-elf -S -emit-llvm %s -o - | FileCheck 
%s -check-prefix=RV64
 
 // RV32: "target-features"="+a,+c,+m,+relax,-save-restore"
 // RV64: "target-features"="+64bit,+a,+c,+m,+relax,-save-restore"


Index: clang/test/Driver/riscv-default-features.c
===
--- clang/test/Driver/riscv-default-features.c
+++ clang/test/Driver/riscv-default-features.c
@@ -1,4 +1,5 @@
 // RUN: %clang -target riscv32-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32
+// RUN: %clang -target riscv64-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64
 
 // RV32: "target-features"="+a,+c,+m,+relax,-save-restore"
 // RV64: "target-features"="+64bit,+a,+c,+m,+relax,-save-restore"
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[PATCH] D119541: [RISCV] Fix RISCVTargetInfo::initFeatureMap, add non-ISA features back after implication

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD marked an inline comment as done.
eopXD added inline comments.



Comment at: clang/test/Driver/riscv-default-features.c:4
+// RV32: "target-features"="+a,+c,+m,+relax,-save-restore"
+// RV64: "target-features"="+64bit,+a,+c,+m,+relax,-save-restore"
+

rogfer01 wrote:
> I think we may be missing are missing a `RUN` line for this case, right?
Created patch D120297, thanks!


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[PATCH] D120297: [Driver][RISCV] Add missing rv64 test case

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD created this revision.
eopXD added a reviewer: rogfer01.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, 
Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, 
edward-jones, zzheng, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, 
johnrusso, rbar, asb.
eopXD requested review of this revision.
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Herald added a project: clang.

Add missing test case. Thanks @rogfer01 for spotting this out.


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Files:
  clang/test/Driver/riscv-default-features.c


Index: clang/test/Driver/riscv-default-features.c
===
--- clang/test/Driver/riscv-default-features.c
+++ clang/test/Driver/riscv-default-features.c
@@ -1,4 +1,5 @@
 // RUN: %clang -target riscv32-unknown-elf -S -emit-llvm %s -o - | FileCheck 
%s -check-prefix=RV32
+// RUN: %clang -target riscv64-unknown-elf -S -emit-llvm %s -o - | FileCheck 
%s -check-prefix=RV64
 
 // RV32: "target-features"="+a,+c,+m,+relax,-save-restore"
 // RV64: "target-features"="+64bit,+a,+c,+m,+relax,-save-restore"


Index: clang/test/Driver/riscv-default-features.c
===
--- clang/test/Driver/riscv-default-features.c
+++ clang/test/Driver/riscv-default-features.c
@@ -1,4 +1,5 @@
 // RUN: %clang -target riscv32-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32
+// RUN: %clang -target riscv64-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64
 
 // RV32: "target-features"="+a,+c,+m,+relax,-save-restore"
 // RV64: "target-features"="+64bit,+a,+c,+m,+relax,-save-restore"
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[PATCH] D119210: [RISCV] Recover the implication between Zve* extensions and the V extension.

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added a comment.

Thanks!


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[PATCH] D119210: [RISCV] Recover the implication between Zve* extensions and the V extension.

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added a comment.

Kindly reverse ping.
May you land this change?


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[PATCH] D119541: [RISCV] Fix RISCVTargetInfo::initFeatureMap, add non-ISA features back after implication

[Yueh-Ting Chen via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG7f51a9e2730e: [RISCV] Fix RISCVTargetInfo::initFeatureMap, 
add non-ISA features back after… (authored by eopXD).

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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-default-features.c


Index: clang/test/Driver/riscv-default-features.c
===
--- /dev/null
+++ clang/test/Driver/riscv-default-features.c
@@ -0,0 +1,9 @@
+// RUN: %clang -target riscv32-unknown-elf -S -emit-llvm %s -o - | FileCheck 
%s -check-prefix=RV32
+
+// RV32: "target-features"="+a,+c,+m,+relax,-save-restore"
+// RV64: "target-features"="+64bit,+a,+c,+m,+relax,-save-restore"
+
+// Dummy function
+int foo(){
+  return  3;
+}
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -232,8 +232,16 @@
 return false;
   }
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU,
-(*ParseResult)->toFeatureVector());
+  // RISCVISAInfo makes implications for ISA features
+  std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+  // Add non-ISA features like `relax` and `save-restore` back
+  for (std::string Feature : FeaturesVec) {
+if (std::find(begin(ImpliedFeatures), end(ImpliedFeatures), Feature) ==
+end(ImpliedFeatures))
+  ImpliedFeatures.push_back(Feature);
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: clang/test/Driver/riscv-default-features.c
===
--- /dev/null
+++ clang/test/Driver/riscv-default-features.c
@@ -0,0 +1,9 @@
+// RUN: %clang -target riscv32-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32
+
+// RV32: "target-features"="+a,+c,+m,+relax,-save-restore"
+// RV64: "target-features"="+64bit,+a,+c,+m,+relax,-save-restore"
+
+// Dummy function
+int foo(){
+  return  3;
+}
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -232,8 +232,16 @@
 return false;
   }
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU,
-(*ParseResult)->toFeatureVector());
+  // RISCVISAInfo makes implications for ISA features
+  std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+  // Add non-ISA features like `relax` and `save-restore` back
+  for (std::string Feature : FeaturesVec) {
+if (std::find(begin(ImpliedFeatures), end(ImpliedFeatures), Feature) ==
+end(ImpliedFeatures))
+  ImpliedFeatures.push_back(Feature);
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
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[PATCH] D119541: [RISCV] Fix RISCVTargetInfo::initFeatureMap, add non-ISA features back after implication

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 407852.
eopXD added a comment.

Add testcase.


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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-default-features.c


Index: clang/test/Driver/riscv-default-features.c
===
--- /dev/null
+++ clang/test/Driver/riscv-default-features.c
@@ -0,0 +1,9 @@
+// RUN: %clang -target riscv32-unknown-elf -S -emit-llvm %s -o - | FileCheck 
%s -check-prefix=RV32
+
+// RV32: "target-features"="+a,+c,+m,+relax,-save-restore"
+// RV64: "target-features"="+64bit,+a,+c,+m,+relax,-save-restore"
+
+// Dummy function
+int foo(){
+  return  3;
+}
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -232,8 +232,16 @@
 return false;
   }
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU,
-(*ParseResult)->toFeatureVector());
+  // RISCVISAInfo makes implications for ISA features
+  std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+  // Add non-ISA features like `relax` and `save-restore` back
+  for (std::string Feature : FeaturesVec) {
+if (std::find(begin(ImpliedFeatures), end(ImpliedFeatures), Feature) ==
+end(ImpliedFeatures))
+  ImpliedFeatures.push_back(Feature);
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: clang/test/Driver/riscv-default-features.c
===
--- /dev/null
+++ clang/test/Driver/riscv-default-features.c
@@ -0,0 +1,9 @@
+// RUN: %clang -target riscv32-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32
+
+// RV32: "target-features"="+a,+c,+m,+relax,-save-restore"
+// RV64: "target-features"="+64bit,+a,+c,+m,+relax,-save-restore"
+
+// Dummy function
+int foo(){
+  return  3;
+}
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -232,8 +232,16 @@
 return false;
   }
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU,
-(*ParseResult)->toFeatureVector());
+  // RISCVISAInfo makes implications for ISA features
+  std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+  // Add non-ISA features like `relax` and `save-restore` back
+  for (std::string Feature : FeaturesVec) {
+if (std::find(begin(ImpliedFeatures), end(ImpliedFeatures), Feature) ==
+end(ImpliedFeatures))
+  ImpliedFeatures.push_back(Feature);
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
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[PATCH] D119541: [RISCV] Fix RISCVTargetInfo::initFeatureMap, add non-isa features back after implication

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD created this revision.
eopXD added reviewers: junparser, craig.topper, asb, frasercrmck.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, 
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edward-jones, zzheng, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, 
johnrusso, rbar.
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Herald added a project: clang.

Previously D113336  makes 
RISCVTargetInfo::initFeatureMap return the results
processed by RISCVISAInfo, which only consists of ISA features and misses
non-ISA features like `relax` and `save-restore`.

This patch fixes the problem.


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Files:
  clang/lib/Basic/Targets/RISCV.cpp


Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -232,8 +232,16 @@
 return false;
   }
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU,
-(*ParseResult)->toFeatureVector());
+  // RISCVISAInfo makes implications for ISA features
+  std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+  // Add non-ISA features like `relax` and `save-restore` back
+  for (std::string Feature : FeaturesVec) {
+if (std::find(begin(ImpliedFeatures), end(ImpliedFeatures), Feature) ==
+end(ImpliedFeatures))
+  ImpliedFeatures.push_back(Feature);
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -232,8 +232,16 @@
 return false;
   }
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU,
-(*ParseResult)->toFeatureVector());
+  // RISCVISAInfo makes implications for ISA features
+  std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+  // Add non-ISA features like `relax` and `save-restore` back
+  for (std::string Feature : FeaturesVec) {
+if (std::find(begin(ImpliedFeatures), end(ImpliedFeatures), Feature) ==
+end(ImpliedFeatures))
+  ImpliedFeatures.push_back(Feature);
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
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[PATCH] D113336: [RISCV] Imply extensions in RISCVTargetInfo::initFeatureMap

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added a comment.

In D113336#3313909 , @junparser wrote:

> @eopXD, hi, this patch make us lost +relax and  -save-restore  by default, 
> would you please fix it?

Sure, let me look into it.
Do you have an existing test case for your situation? (Or I will make one while 
fixing)


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[PATCH] D119210: [RISCV] Recover the implication between Zve* extensions and the V extension.

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD accepted this revision.
eopXD added a comment.
This revision is now accepted and ready to land.

LGTM.
For the record the implication in this patch correspond to the note under 
v-spec 
:

> As is the case with other RISC-V extensions, it is valid to include 
> overlapping extensions in the same ISA string. For example, RV64GCV and 
> RV64GCV_Zve64f are both valid and equivalent ISA strings, as is 
> RV64GCV_Zve64f_Zve32x_Zvl128b.


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[PATCH] D118225: [RISCV] Decouple Zve* extensions.

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added a comment.

Not sure if this simplifies things. Users and the compiler  can use the macro 
__riscv_v_elen and __riscv_v_elen_fp to do things to the vector-related target 
feature.

Other than that I dont hold any strong objection to this refactoring.


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[PATCH] D117860: [RISCV] Remove experimental prefix from rvv-related extensions.

[Yueh-Ting Chen via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG3cf15af2daa9: [RISCV] Remove experimental prefix from 
rvv-related extensions. (authored by eopXD).

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Files:
  clang/test/CodeGen/RISCV/riscv-attr-builtin-alias-err.c
  clang/test/CodeGen/RISCV/riscv-attr-builtin-alias.c
  clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
  clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
  clang/test/CodeGen/RISCV/riscv-v-lifetime.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcpop.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfabs.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfirst.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vget.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c
  

[PATCH] D117913: [Clang][RISCV] Guard vmulh, vsmul correctly

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added a comment.

In D117913#3263493 , @khchen wrote:

> why the new test filename extension is `.c.c`?

Thanks for the reminder.


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[PATCH] D117860: [RISCV] Remove experimental prefix from rvv-related extensions.

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 402192.
eopXD added a comment.

Rebase.
Resolve conflict due to addition of zbkc.


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Files:
  clang/test/CodeGen/RISCV/riscv-attr-builtin-alias-err.c
  clang/test/CodeGen/RISCV/riscv-attr-builtin-alias.c
  clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
  clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
  clang/test/CodeGen/RISCV/riscv-v-lifetime.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcpop.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfabs.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfirst.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vget.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c
  

[PATCH] D117854: [RISCV] Refactor Zve* extensions.

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added a comment.

Maybe change the title to address more specifically of what this patch does?


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[PATCH] D117920: [RISCV] Decouple V and Zve64*

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD abandoned this revision.
eopXD added a comment.

In D117920#3263202 , @jacquesguan 
wrote:

> I did some similar change in my revision https://reviews.llvm.org/D117854.

Yeah I guess we can do that all in one commit.
Thank you for doing it.


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[PATCH] D117920: [RISCV] Decouple V and Zve64*

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 402172.
eopXD added a comment.

Update code.


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Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/MC/RISCV/attribute-arch.s


Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -36,7 +36,7 @@
 ## Experimental extensions require version string to be explicitly specified
 
 .attribute arch, "rv32iv1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -75,43 +75,43 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0"
 
 .attribute arch, "rv32iv1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl32b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl64b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl128b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl256b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl512b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl1024b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl2048b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl4096b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl8192b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
 
 .attribute arch, "rv32iv1p0zvl16384b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
 
 .attribute arch, "rv32iv1p0zvl32768b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, 

[PATCH] D117920: [RISCV] Decouple V and Zve64*

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 402170.
eopXD added a comment.

Update code: adjust testcase due to change of implication.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117920/new/

https://reviews.llvm.org/D117920

Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/MC/RISCV/attribute-arch.s


Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -36,7 +36,7 @@
 ## Experimental extensions require version string to be explicitly specified
 
 .attribute arch, "rv32iv1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -75,43 +75,43 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0"
 
 .attribute arch, "rv32iv1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl32b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl64b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl128b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl256b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl512b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl1024b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl2048b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl4096b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32iv1p0zvl8192b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
 
 .attribute arch, "rv32iv1p0zvl16384b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
 
 .attribute arch, "rv32iv1p0zvl32768b1p0"
-# CHECK: attribute  5, 
"rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, 

[PATCH] D117920: [RISCV] Decouple V and Zve64*

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 402085.
eopXD added a comment.

Update code.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117920/new/

https://reviews.llvm.org/D117920

Files:
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -732,7 +732,7 @@
   return Error::success();
 }
 
-static const char *ImpliedExtsV[] = {"zvl128b", "zve64d", "f", "d"};
+static const char *ImpliedExtsV[] = {"zvl128b", "zve32x", "f", "d"};
 static const char *ImpliedExtsZfh[] = {"zfhmin"};
 static const char *ImpliedExtsZve64d[] = {"zve64f"};
 static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
@@ -844,6 +844,9 @@
   // handles EEW restriction by sub-extension zve
   for (auto Ext : Exts) {
 StringRef ExtName = Ext.first;
+if (ExtName == "v") {
+  MaxELen = MaxELenFp = 64;
+}
 bool IsZveExt = ExtName.consume_front("zve");
 if (IsZveExt) {
   if (ExtName.back() == 'f')


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -732,7 +732,7 @@
   return Error::success();
 }
 
-static const char *ImpliedExtsV[] = {"zvl128b", "zve64d", "f", "d"};
+static const char *ImpliedExtsV[] = {"zvl128b", "zve32x", "f", "d"};
 static const char *ImpliedExtsZfh[] = {"zfhmin"};
 static const char *ImpliedExtsZve64d[] = {"zve64f"};
 static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
@@ -844,6 +844,9 @@
   // handles EEW restriction by sub-extension zve
   for (auto Ext : Exts) {
 StringRef ExtName = Ext.first;
+if (ExtName == "v") {
+  MaxELen = MaxELenFp = 64;
+}
 bool IsZveExt = ExtName.consume_front("zve");
 if (IsZveExt) {
   if (ExtName.back() == 'f')
___
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cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D117920: [RISCV] Decouple V and Zve64*

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 402080.
eopXD added a comment.

Update code.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117920/new/

https://reviews.llvm.org/D117920

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -732,7 +732,7 @@
   return Error::success();
 }
 
-static const char *ImpliedExtsV[] = {"zvl128b", "zve64d", "f", "d"};
+static const char *ImpliedExtsV[] = {"zvl128b", "zve32x", "f", "d"};
 static const char *ImpliedExtsZfh[] = {"zfhmin"};
 static const char *ImpliedExtsZve64d[] = {"zve64f"};
 static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
@@ -844,6 +844,9 @@
   // handles EEW restriction by sub-extension zve
   for (auto Ext : Exts) {
 StringRef ExtName = Ext.first;
+if (ExtName == "v") {
+  MaxELen = MaxELenFp = 64;
+}
 bool IsZveExt = ExtName.consume_front("zve");
 if (IsZveExt) {
   if (ExtName.back() == 'f')
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -188,7 +188,7 @@
   if (ISAInfo->hasExtension("c"))
 Builder.defineMacro("__riscv_compressed");
 
-  if (ISAInfo->hasExtension("zve32x"))
+  if (ISAInfo->hasExtension("zve32x") || ISAInfo->hasExtension("v"))
 Builder.defineMacro("__riscv_vector");
 }
 


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -732,7 +732,7 @@
   return Error::success();
 }
 
-static const char *ImpliedExtsV[] = {"zvl128b", "zve64d", "f", "d"};
+static const char *ImpliedExtsV[] = {"zvl128b", "zve32x", "f", "d"};
 static const char *ImpliedExtsZfh[] = {"zfhmin"};
 static const char *ImpliedExtsZve64d[] = {"zve64f"};
 static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
@@ -844,6 +844,9 @@
   // handles EEW restriction by sub-extension zve
   for (auto Ext : Exts) {
 StringRef ExtName = Ext.first;
+if (ExtName == "v") {
+  MaxELen = MaxELenFp = 64;
+}
 bool IsZveExt = ExtName.consume_front("zve");
 if (IsZveExt) {
   if (ExtName.back() == 'f')
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -188,7 +188,7 @@
   if (ISAInfo->hasExtension("c"))
 Builder.defineMacro("__riscv_compressed");
 
-  if (ISAInfo->hasExtension("zve32x"))
+  if (ISAInfo->hasExtension("zve32x") || ISAInfo->hasExtension("v"))
 Builder.defineMacro("__riscv_vector");
 }
 
___
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[PATCH] D117920: [RISCV] Decouple V and Zve64*

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD created this revision.
eopXD added reviewers: craig.topper, asb.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, 
Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, 
johnrusso, rbar, hiraditya.
eopXD requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.
Herald added projects: clang, LLVM.

Now with existing macros to imply elen and elen_fp for rvv, we should decouple
the implication between V and Zve*.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117920

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -690,7 +690,7 @@
   bool HasE = Exts.count("e") == 1;
   bool HasD = Exts.count("d") == 1;
   bool HasF = Exts.count("f") == 1;
-  bool HasVector = Exts.count("zve32x") == 1;
+  bool HasVector = Exts.count("v") == 1 || Exts.count("zve32x") == 1;
   bool HasZve32f = Exts.count("zve32f") == 1;
   bool HasZve64d = Exts.count("zve64d") == 1;
   bool HasZvl = MinVLen != 0;
@@ -732,7 +732,7 @@
   return Error::success();
 }
 
-static const char *ImpliedExtsV[] = {"zvl128b", "zve64d", "f", "d"};
+static const char *ImpliedExtsV[] = {"zvl128b", "f", "d"};
 static const char *ImpliedExtsZfh[] = {"zfhmin"};
 static const char *ImpliedExtsZve64d[] = {"zve64f"};
 static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
@@ -844,6 +844,9 @@
   // handles EEW restriction by sub-extension zve
   for (auto Ext : Exts) {
 StringRef ExtName = Ext.first;
+if (ExtName == "v") {
+  MaxELen = MaxELenFp = 64;
+}
 bool IsZveExt = ExtName.consume_front("zve");
 if (IsZveExt) {
   if (ExtName.back() == 'f')
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1034,7 +1034,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-zve32x\")\n";
+"ATTRS, \"experimental-zve32x|v\")\n";
   OS << "#endif\n";
   for (auto  : Defs) {
 auto P =
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -188,7 +188,7 @@
   if (ISAInfo->hasExtension("c"))
 Builder.defineMacro("__riscv_compressed");
 
-  if (ISAInfo->hasExtension("zve32x"))
+  if (ISAInfo->hasExtension("zve32x") || ISAInfo->hasExtension("v"))
 Builder.defineMacro("__riscv_vector");
 }
 


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -690,7 +690,7 @@
   bool HasE = Exts.count("e") == 1;
   bool HasD = Exts.count("d") == 1;
   bool HasF = Exts.count("f") == 1;
-  bool HasVector = Exts.count("zve32x") == 1;
+  bool HasVector = Exts.count("v") == 1 || Exts.count("zve32x") == 1;
   bool HasZve32f = Exts.count("zve32f") == 1;
   bool HasZve64d = Exts.count("zve64d") == 1;
   bool HasZvl = MinVLen != 0;
@@ -732,7 +732,7 @@
   return Error::success();
 }
 
-static const char *ImpliedExtsV[] = {"zvl128b", "zve64d", "f", "d"};
+static const char *ImpliedExtsV[] = {"zvl128b", "f", "d"};
 static const char *ImpliedExtsZfh[] = {"zfhmin"};
 static const char *ImpliedExtsZve64d[] = {"zve64f"};
 static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
@@ -844,6 +844,9 @@
   // handles EEW restriction by sub-extension zve
   for (auto Ext : Exts) {
 StringRef ExtName = Ext.first;
+if (ExtName == "v") {
+  MaxELen = MaxELenFp = 64;
+}
 bool IsZveExt = ExtName.consume_front("zve");
 if (IsZveExt) {
   if (ExtName.back() == 'f')
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1034,7 +1034,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-zve32x\")\n";
+"ATTRS, \"experimental-zve32x|v\")\n";
   OS << "#endif\n";
   for (auto  : Defs) {
 auto P =
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -188,7 +188,7 @@
 

[PATCH] D117913: [Clang][RISCV] Guard vmulh, vsmul correctly

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added a comment.

I changed the test commands in `vmul.c` and `vsmul.c` to use `zve64d` to make 
sure I don't miss anything I should move to the created files - `vmul-eew64.c` 
and `vsmul-eew64.c`


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[PATCH] D117860: [RISCV] Remove experimental prefix from rvv-related extensions.

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added a comment.

In D117860#3261453 , @frasercrmck 
wrote:

> Thanks for the patch! Not sure the best way to review this. The tests are 
> passing, which is a good sign. One option could be to split the "meaningful" 
> changes into a separate diff for easier viewing? We probably don't need to 
> see all the test RUN line changes, for example.

Non-testcase file changes are:

  M   clang/utils/TableGen/RISCVVEmitter.cpp
  M   llvm/lib/Support/RISCVISAInfo.cpp
  M   llvm/lib/Target/RISCV/RISCV.td

Do you mean creating separate this patch into two? Won't that cause build 
failure?


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[PATCH] D112986: [Clang][RISCV] Restrict rvv builtins with zve macros

[Yueh-Ting Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGe6ceec9c1d19: [Clang][RISCV] Restrict rvv builtins with zve 
macros (authored by eopXD).

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Files:
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -100,6 +100,9 @@
   bool isValid() const { return Valid; }
   bool isScalar() const { return Scale.hasValue() && Scale.getValue() == 0; }
   bool isVector() const { return Scale.hasValue() && Scale.getValue() != 0; }
+  bool isVector(unsigned Width) const {
+return isVector() && ElementBitwidth == Width;
+  }
   bool isFloat() const { return ScalarType == ScalarTypeKind::Float; }
   bool isSignedInteger() const {
 return ScalarType == ScalarTypeKind::SignedInteger;
@@ -134,13 +137,15 @@
 
 using RVVTypePtr = RVVType *;
 using RVVTypes = std::vector;
+using RISCVPredefinedMacroT = uint8_t;
 
-enum RISCVExtension : uint8_t {
+enum RISCVPredefinedMacro : RISCVPredefinedMacroT {
   Basic = 0,
-  F = 1 << 1,
-  D = 1 << 2,
-  Zfh = 1 << 3,
-  RV64 = 1 << 4,
+  Zfh = 1 << 1,
+  RV64 = 1 << 2,
+  VectorMaxELen64 = 1 << 3,
+  VectorMaxELenFp32 = 1 << 4,
+  VectorMaxELenFp64 = 1 << 5,
 };
 
 // TODO refactor RVVIntrinsic class design after support all intrinsic
@@ -164,7 +169,7 @@
   // The types we use to obtain the specific LLVM intrinsic. They are index of
   // InputTypes. -1 means the return type.
   std::vector IntrinsicTypes;
-  uint8_t RISCVExtensions = 0;
+  RISCVPredefinedMacroT RISCVPredefinedMacros = 0;
   unsigned NF = 1;
 
 public:
@@ -188,7 +193,9 @@
   bool isMask() const { return IsMask; }
   StringRef getIRName() const { return IRName; }
   StringRef getManualCodegen() const { return ManualCodegen; }
-  uint8_t getRISCVExtensions() const { return RISCVExtensions; }
+  RISCVPredefinedMacroT getRISCVPredefinedMacros() const {
+return RISCVPredefinedMacros;
+  }
   unsigned getNF() const { return NF; }
   const std::vector () const {
 return IntrinsicTypes;
@@ -251,7 +258,8 @@
 
   // Emit the architecture preprocessor definitions. Return true when emits
   // non-empty string.
-  bool emitExtDefStr(uint8_t Extensions, raw_ostream );
+  bool emitMacroRestrictionStr(RISCVPredefinedMacroT PredefinedMacros,
+   raw_ostream );
   // Slice Prototypes string into sub prototype string and process each sub
   // prototype string individually in the Handler.
   void parsePrototypes(StringRef Prototypes,
@@ -789,15 +797,17 @@
   // Init RISC-V extensions
   for (const auto  : OutInTypes) {
 if (T->isFloatVector(16) || T->isFloat(16))
-  RISCVExtensions |= RISCVExtension::Zfh;
-else if (T->isFloatVector(32) || T->isFloat(32))
-  RISCVExtensions |= RISCVExtension::F;
-else if (T->isFloatVector(64) || T->isFloat(64))
-  RISCVExtensions |= RISCVExtension::D;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::Zfh;
+if (T->isFloatVector(32))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELenFp32;
+if (T->isFloatVector(64))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELenFp64;
+if (T->isVector(64))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELen64;
   }
   for (auto Extension : RequiredExtensions) {
 if (Extension == "RV64")
-  RISCVExtensions |= RISCVExtension::RV64;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::RV64;
   }
 
   // Init OutputType and InputTypes
@@ -981,7 +991,7 @@
   // The same extension include in the same arch guard marco.
   llvm::stable_sort(Defs, [](const std::unique_ptr ,
  const std::unique_ptr ) {
-return A->getRISCVExtensions() < B->getRISCVExtensions();
+return A->getRISCVPredefinedMacros() < B->getRISCVPredefinedMacros();
   });
 
   OS << "#define __rvv_ai static __inline__\n";
@@ -1280,15 +1290,16 @@
 void RVVEmitter::emitArchMacroAndBody(
 std::vector> , raw_ostream ,
 std::function PrintBody) {
-  uint8_t PrevExt = (*Defs.begin())->getRISCVExtensions();
-  bool NeedEndif = emitExtDefStr(PrevExt, OS);
+  RISCVPredefinedMacroT PrevMacros =
+  (*Defs.begin())->getRISCVPredefinedMacros();
+  bool NeedEndif = emitMacroRestrictionStr(PrevMacros, OS);
   for (auto  : Defs) {
-uint8_t CurExt = Def->getRISCVExtensions();
-if (CurExt != PrevExt) {
+RISCVPredefinedMacroT CurMacros = Def->getRISCVPredefinedMacros();
+if (CurMacros != PrevMacros) {
   if (NeedEndif)
 OS << "#endif\n\n";
-  NeedEndif = emitExtDefStr(CurExt, OS);
-  PrevExt = CurExt;
+  NeedEndif = emitMacroRestrictionStr(CurMacros, OS);
+  PrevMacros = CurMacros;
 

[PATCH] D112986: [Clang][RISCV] Restrict rvv builtins with zve macros

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added a comment.

In D112986#3261933 , @frasercrmck 
wrote:

> LGTM too. Though the commit title and message has hyphens in places I 
> wouldn't expect them. `macros` and `builtins` is fine.

Thank you to also drop by and take a look :)




Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:797
 
   // Init RISC-V extensions
   for (const auto  : OutInTypes) {

frasercrmck wrote:
> nit: This still says "extensions"
Yeah I thought of not changing the variable name, however as other enums are 
added in keeping it as "extensions" is a bit strange to me.


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[PATCH] D112986: [Clang][RISCV] Restrict rvv builtin-s with zve macro-s

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 402036.
eopXD marked an inline comment as done.
eopXD added a comment.

Cleanup unused enum.


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Files:
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -100,6 +100,9 @@
   bool isValid() const { return Valid; }
   bool isScalar() const { return Scale.hasValue() && Scale.getValue() == 0; }
   bool isVector() const { return Scale.hasValue() && Scale.getValue() != 0; }
+  bool isVector(unsigned Width) const {
+return isVector() && ElementBitwidth == Width;
+  }
   bool isFloat() const { return ScalarType == ScalarTypeKind::Float; }
   bool isSignedInteger() const {
 return ScalarType == ScalarTypeKind::SignedInteger;
@@ -134,13 +137,15 @@
 
 using RVVTypePtr = RVVType *;
 using RVVTypes = std::vector;
+using RISCVPredefinedMacroT = uint8_t;
 
-enum RISCVExtension : uint8_t {
+enum RISCVPredefinedMacro : RISCVPredefinedMacroT {
   Basic = 0,
-  F = 1 << 1,
-  D = 1 << 2,
-  Zfh = 1 << 3,
-  RV64 = 1 << 4,
+  Zfh = 1 << 1,
+  RV64 = 1 << 2,
+  VectorMaxELen64 = 1 << 3,
+  VectorMaxELenFp32 = 1 << 4,
+  VectorMaxELenFp64 = 1 << 5,
 };
 
 // TODO refactor RVVIntrinsic class design after support all intrinsic
@@ -164,7 +169,7 @@
   // The types we use to obtain the specific LLVM intrinsic. They are index of
   // InputTypes. -1 means the return type.
   std::vector IntrinsicTypes;
-  uint8_t RISCVExtensions = 0;
+  RISCVPredefinedMacroT RISCVPredefinedMacros = 0;
   unsigned NF = 1;
 
 public:
@@ -188,7 +193,9 @@
   bool isMask() const { return IsMask; }
   StringRef getIRName() const { return IRName; }
   StringRef getManualCodegen() const { return ManualCodegen; }
-  uint8_t getRISCVExtensions() const { return RISCVExtensions; }
+  RISCVPredefinedMacroT getRISCVPredefinedMacros() const {
+return RISCVPredefinedMacros;
+  }
   unsigned getNF() const { return NF; }
   const std::vector () const {
 return IntrinsicTypes;
@@ -251,7 +258,8 @@
 
   // Emit the architecture preprocessor definitions. Return true when emits
   // non-empty string.
-  bool emitExtDefStr(uint8_t Extensions, raw_ostream );
+  bool emitMacroRestrictionStr(RISCVPredefinedMacroT PredefinedMacros,
+   raw_ostream );
   // Slice Prototypes string into sub prototype string and process each sub
   // prototype string individually in the Handler.
   void parsePrototypes(StringRef Prototypes,
@@ -789,15 +797,17 @@
   // Init RISC-V extensions
   for (const auto  : OutInTypes) {
 if (T->isFloatVector(16) || T->isFloat(16))
-  RISCVExtensions |= RISCVExtension::Zfh;
-else if (T->isFloatVector(32) || T->isFloat(32))
-  RISCVExtensions |= RISCVExtension::F;
-else if (T->isFloatVector(64) || T->isFloat(64))
-  RISCVExtensions |= RISCVExtension::D;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::Zfh;
+if (T->isFloatVector(32))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELenFp32;
+if (T->isFloatVector(64))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELenFp64;
+if (T->isVector(64))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELen64;
   }
   for (auto Extension : RequiredExtensions) {
 if (Extension == "RV64")
-  RISCVExtensions |= RISCVExtension::RV64;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::RV64;
   }
 
   // Init OutputType and InputTypes
@@ -981,7 +991,7 @@
   // The same extension include in the same arch guard marco.
   llvm::stable_sort(Defs, [](const std::unique_ptr ,
  const std::unique_ptr ) {
-return A->getRISCVExtensions() < B->getRISCVExtensions();
+return A->getRISCVPredefinedMacros() < B->getRISCVPredefinedMacros();
   });
 
   OS << "#define __rvv_ai static __inline__\n";
@@ -1280,15 +1290,16 @@
 void RVVEmitter::emitArchMacroAndBody(
 std::vector> , raw_ostream ,
 std::function PrintBody) {
-  uint8_t PrevExt = (*Defs.begin())->getRISCVExtensions();
-  bool NeedEndif = emitExtDefStr(PrevExt, OS);
+  RISCVPredefinedMacroT PrevMacros =
+  (*Defs.begin())->getRISCVPredefinedMacros();
+  bool NeedEndif = emitMacroRestrictionStr(PrevMacros, OS);
   for (auto  : Defs) {
-uint8_t CurExt = Def->getRISCVExtensions();
-if (CurExt != PrevExt) {
+RISCVPredefinedMacroT CurMacros = Def->getRISCVPredefinedMacros();
+if (CurMacros != PrevMacros) {
   if (NeedEndif)
 OS << "#endif\n\n";
-  NeedEndif = emitExtDefStr(CurExt, OS);
-  PrevExt = CurExt;
+  NeedEndif = emitMacroRestrictionStr(CurMacros, OS);
+  PrevMacros = CurMacros;
 }
 if (Def->hasAutoDef())
   PrintBody(OS, *Def);
@@ -1297,19 +1308,22 @@
 OS << "#endif\n\n";
 

[PATCH] D117860: [RISCV] Remove experimental prefix from rvv-related extensions.

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 402034.
eopXD added a comment.

Cleanup redundant code.


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  clang/test/CodeGen/RISCV/riscv-attr-builtin-alias-err.c
  clang/test/CodeGen/RISCV/riscv-attr-builtin-alias.c
  clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
  clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
  clang/test/CodeGen/RISCV/riscv-v-lifetime.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcpop.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfabs.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfirst.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vget.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c
  

[PATCH] D117860: [RISCV] Remove experimental prefix from rvv-related extensions.

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD created this revision.
eopXD added reviewers: craig.topper, asb, frasercrmck.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
armkevincheng, eric-k256, vkmr, jdoerfert, evandro, luismarques, apazos, 
sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, arphaman, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, kito-cheng, 
niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya, qcolombet, MatzeB.
Herald added a reviewer: sjarus.
eopXD requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.
Herald added projects: clang, LLVM.

Extensions affected: +v, +zve*, +zvl*


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117860

Files:
  clang/test/CodeGen/RISCV/riscv-attr-builtin-alias-err.c
  clang/test/CodeGen/RISCV/riscv-attr-builtin-alias.c
  clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
  clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
  clang/test/CodeGen/RISCV/riscv-v-lifetime.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcpop.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfabs.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfirst.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vget.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
  

[PATCH] D112987: [RISCV] Bump rvv-related extensions from 0.10 to 1.0

[Yueh-Ting Chen via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGe6de53b4de4a: [RISCV] Bump rvv-related extensions from 0.10 
to 1.0 (authored by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112987/new/

https://reviews.llvm.org/D112987

Files:
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -35,8 +35,8 @@
 
 ## Experimental extensions require version string to be explicitly specified
 
-.attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -74,59 +74,59 @@
 .attribute arch, "rv32ifzfh1p0"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0"
 
-.attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl32b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl32b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl64b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl128b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl128b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl256b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl256b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl512b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl512b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl1024b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl1024b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl2048b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl2048b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl4096b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl4096b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
 
-.attribute arch, 

[PATCH] D112986: [Clang][RISCV] Restrict rvv builtin-s with zve macro-s

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 401870.
eopXD added a comment.

Follow clang-format.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112986/new/

https://reviews.llvm.org/D112986

Files:
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -100,6 +100,9 @@
   bool isValid() const { return Valid; }
   bool isScalar() const { return Scale.hasValue() && Scale.getValue() == 0; }
   bool isVector() const { return Scale.hasValue() && Scale.getValue() != 0; }
+  bool isVector(unsigned Width) const {
+return isVector() && ElementBitwidth == Width;
+  }
   bool isFloat() const { return ScalarType == ScalarTypeKind::Float; }
   bool isSignedInteger() const {
 return ScalarType == ScalarTypeKind::SignedInteger;
@@ -134,13 +137,17 @@
 
 using RVVTypePtr = RVVType *;
 using RVVTypes = std::vector;
+using RISCVPredefinedMacroT = uint8_t;
 
-enum RISCVExtension : uint8_t {
+enum RISCVPredefinedMacro : RISCVPredefinedMacroT {
   Basic = 0,
   F = 1 << 1,
   D = 1 << 2,
   Zfh = 1 << 3,
   RV64 = 1 << 4,
+  VectorMaxELen64 = 1 << 5,
+  VectorMaxELenFp32 = 1 << 6,
+  VectorMaxELenFp64 = 1 << 7,
 };
 
 // TODO refactor RVVIntrinsic class design after support all intrinsic
@@ -164,7 +171,7 @@
   // The types we use to obtain the specific LLVM intrinsic. They are index of
   // InputTypes. -1 means the return type.
   std::vector IntrinsicTypes;
-  uint8_t RISCVExtensions = 0;
+  RISCVPredefinedMacroT RISCVPredefinedMacros = 0;
   unsigned NF = 1;
 
 public:
@@ -188,7 +195,9 @@
   bool isMask() const { return IsMask; }
   StringRef getIRName() const { return IRName; }
   StringRef getManualCodegen() const { return ManualCodegen; }
-  uint8_t getRISCVExtensions() const { return RISCVExtensions; }
+  RISCVPredefinedMacroT getRISCVPredefinedMacros() const {
+return RISCVPredefinedMacros;
+  }
   unsigned getNF() const { return NF; }
   const std::vector () const {
 return IntrinsicTypes;
@@ -251,7 +260,8 @@
 
   // Emit the architecture preprocessor definitions. Return true when emits
   // non-empty string.
-  bool emitExtDefStr(uint8_t Extensions, raw_ostream );
+  bool emitMacroRestrictionStr(RISCVPredefinedMacroT PredefinedMacros,
+   raw_ostream );
   // Slice Prototypes string into sub prototype string and process each sub
   // prototype string individually in the Handler.
   void parsePrototypes(StringRef Prototypes,
@@ -789,15 +799,17 @@
   // Init RISC-V extensions
   for (const auto  : OutInTypes) {
 if (T->isFloatVector(16) || T->isFloat(16))
-  RISCVExtensions |= RISCVExtension::Zfh;
-else if (T->isFloatVector(32) || T->isFloat(32))
-  RISCVExtensions |= RISCVExtension::F;
-else if (T->isFloatVector(64) || T->isFloat(64))
-  RISCVExtensions |= RISCVExtension::D;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::Zfh;
+if (T->isFloatVector(32))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELenFp32;
+if (T->isFloatVector(64))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELenFp64;
+if (T->isVector(64))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELen64;
   }
   for (auto Extension : RequiredExtensions) {
 if (Extension == "RV64")
-  RISCVExtensions |= RISCVExtension::RV64;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::RV64;
   }
 
   // Init OutputType and InputTypes
@@ -981,7 +993,7 @@
   // The same extension include in the same arch guard marco.
   llvm::stable_sort(Defs, [](const std::unique_ptr ,
  const std::unique_ptr ) {
-return A->getRISCVExtensions() < B->getRISCVExtensions();
+return A->getRISCVPredefinedMacros() < B->getRISCVPredefinedMacros();
   });
 
   OS << "#define __rvv_ai static __inline__\n";
@@ -1280,15 +1292,16 @@
 void RVVEmitter::emitArchMacroAndBody(
 std::vector> , raw_ostream ,
 std::function PrintBody) {
-  uint8_t PrevExt = (*Defs.begin())->getRISCVExtensions();
-  bool NeedEndif = emitExtDefStr(PrevExt, OS);
+  RISCVPredefinedMacroT PrevMacros =
+  (*Defs.begin())->getRISCVPredefinedMacros();
+  bool NeedEndif = emitMacroRestrictionStr(PrevMacros, OS);
   for (auto  : Defs) {
-uint8_t CurExt = Def->getRISCVExtensions();
-if (CurExt != PrevExt) {
+RISCVPredefinedMacroT CurMacros = Def->getRISCVPredefinedMacros();
+if (CurMacros != PrevMacros) {
   if (NeedEndif)
 OS << "#endif\n\n";
-  NeedEndif = emitExtDefStr(CurExt, OS);
-  PrevExt = CurExt;
+  NeedEndif = emitMacroRestrictionStr(CurMacros, OS);
+  PrevMacros = CurMacros;
 }
 if (Def->hasAutoDef())
   PrintBody(OS, *Def);
@@ -1297,19 +1310,26 @@
 OS << "#endif\n\n";
 }
 
-bool RVVEmitter::emitExtDefStr(uint8_t Extents, raw_ostream ) {
-  if 

[PATCH] D112986: [Clang][RISCV] Restrict rvv builtin-s with zve macro-s

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:149
   RV64 = 1 << 5,
+  VectorMaxELen32 = 1 << 6,
+  VectorMaxELen64 = 1 << 7,

craig.topper wrote:
> Do we need VectorMaxELen32 isn't that the minimum?
Yes you are correct. We don't need it.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:804
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::Zfh;
 else if (T->isFloatVector(32) || T->isFloat(32))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::F;

craig.topper wrote:
> Can D and F go away?
Done.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112986/new/

https://reviews.llvm.org/D112986

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[PATCH] D112986: [Clang][RISCV] Restrict rvv builtin-s with zve macro-s

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 401862.
eopXD marked 2 inline comments as done.
eopXD added a comment.

Rebase and addres comments.
Resolve conflcits due to zvlsseg removal.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112986/new/

https://reviews.llvm.org/D112986

Files:
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -100,6 +100,9 @@
   bool isValid() const { return Valid; }
   bool isScalar() const { return Scale.hasValue() && Scale.getValue() == 0; }
   bool isVector() const { return Scale.hasValue() && Scale.getValue() != 0; }
+  bool isVector(unsigned Width) const {
+return isVector() && ElementBitwidth == Width;
+  }
   bool isFloat() const { return ScalarType == ScalarTypeKind::Float; }
   bool isSignedInteger() const {
 return ScalarType == ScalarTypeKind::SignedInteger;
@@ -134,13 +137,17 @@
 
 using RVVTypePtr = RVVType *;
 using RVVTypes = std::vector;
+using RISCVPredefinedMacroT = uint8_t;
 
-enum RISCVExtension : uint8_t {
+enum RISCVPredefinedMacro : RISCVPredefinedMacroT {
   Basic = 0,
   F = 1 << 1,
   D = 1 << 2,
   Zfh = 1 << 3,
   RV64 = 1 << 4,
+  VectorMaxELen64 = 1 << 5,
+  VectorMaxELenFp32 = 1 << 6,
+  VectorMaxELenFp64 = 1 << 7,
 };
 
 // TODO refactor RVVIntrinsic class design after support all intrinsic
@@ -164,7 +171,7 @@
   // The types we use to obtain the specific LLVM intrinsic. They are index of
   // InputTypes. -1 means the return type.
   std::vector IntrinsicTypes;
-  uint8_t RISCVExtensions = 0;
+  RISCVPredefinedMacroT RISCVPredefinedMacros = 0;
   unsigned NF = 1;
 
 public:
@@ -188,7 +195,9 @@
   bool isMask() const { return IsMask; }
   StringRef getIRName() const { return IRName; }
   StringRef getManualCodegen() const { return ManualCodegen; }
-  uint8_t getRISCVExtensions() const { return RISCVExtensions; }
+  RISCVPredefinedMacroT getRISCVPredefinedMacros() const {
+return RISCVPredefinedMacros;
+  }
   unsigned getNF() const { return NF; }
   const std::vector () const {
 return IntrinsicTypes;
@@ -251,7 +260,7 @@
 
   // Emit the architecture preprocessor definitions. Return true when emits
   // non-empty string.
-  bool emitExtDefStr(uint8_t Extensions, raw_ostream );
+  bool emitMacroRestrictionStr(RISCVPredefinedMacroT PredefinedMacros, raw_ostream );
   // Slice Prototypes string into sub prototype string and process each sub
   // prototype string individually in the Handler.
   void parsePrototypes(StringRef Prototypes,
@@ -789,15 +798,17 @@
   // Init RISC-V extensions
   for (const auto  : OutInTypes) {
 if (T->isFloatVector(16) || T->isFloat(16))
-  RISCVExtensions |= RISCVExtension::Zfh;
-else if (T->isFloatVector(32) || T->isFloat(32))
-  RISCVExtensions |= RISCVExtension::F;
-else if (T->isFloatVector(64) || T->isFloat(64))
-  RISCVExtensions |= RISCVExtension::D;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::Zfh;
+if (T->isFloatVector(32))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELenFp32;
+if (T->isFloatVector(64))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELenFp64;
+if (T->isVector(64))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELen64;
   }
   for (auto Extension : RequiredExtensions) {
 if (Extension == "RV64")
-  RISCVExtensions |= RISCVExtension::RV64;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::RV64;
   }
 
   // Init OutputType and InputTypes
@@ -981,7 +992,7 @@
   // The same extension include in the same arch guard marco.
   llvm::stable_sort(Defs, [](const std::unique_ptr ,
  const std::unique_ptr ) {
-return A->getRISCVExtensions() < B->getRISCVExtensions();
+return A->getRISCVPredefinedMacros() < B->getRISCVPredefinedMacros();
   });
 
   OS << "#define __rvv_ai static __inline__\n";
@@ -1280,15 +1291,15 @@
 void RVVEmitter::emitArchMacroAndBody(
 std::vector> , raw_ostream ,
 std::function PrintBody) {
-  uint8_t PrevExt = (*Defs.begin())->getRISCVExtensions();
-  bool NeedEndif = emitExtDefStr(PrevExt, OS);
+  RISCVPredefinedMacroT PrevMacros = (*Defs.begin())->getRISCVPredefinedMacros();
+  bool NeedEndif = emitMacroRestrictionStr(PrevMacros, OS);
   for (auto  : Defs) {
-uint8_t CurExt = Def->getRISCVExtensions();
-if (CurExt != PrevExt) {
+RISCVPredefinedMacroT CurMacros = Def->getRISCVPredefinedMacros();
+if (CurMacros != PrevMacros) {
   if (NeedEndif)
 OS << "#endif\n\n";
-  NeedEndif = emitExtDefStr(CurExt, OS);
-  PrevExt = CurExt;
+  NeedEndif = emitMacroRestrictionStr(CurMacros, OS);
+  PrevMacros = CurMacros;
 }
 if (Def->hasAutoDef())
   PrintBody(OS, *Def);
@@ -1297,19 +1308,26 @@
 OS << "#endif\n\n";
 }
 
-bool 

[PATCH] D112987: [RISCV] Bump rvv-related extensions from 0.10 to 1.0

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 401861.
eopXD added a comment.

Rebase.
Resolve conflict due to zvlsseg removal.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112987/new/

https://reviews.llvm.org/D112987

Files:
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -35,8 +35,8 @@
 
 ## Experimental extensions require version string to be explicitly specified
 
-.attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -74,59 +74,59 @@
 .attribute arch, "rv32ifzfh1p0"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0"
 
-.attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl32b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl32b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl64b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl128b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl128b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl256b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl256b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl512b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl512b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl1024b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl1024b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl2048b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl2048b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl4096b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10"
+.attribute arch, "rv32iv1p0zvl4096b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
 
-.attribute arch, "rv32iv0p10zvl8192b0p10"
-# CHECK: attribute  5, 

[PATCH] D112987: [RISCV] Bump rvv-related extensions from 0.10 to 1.0

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 401700.
eopXD marked an inline comment as done.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112987/new/

https://reviews.llvm.org/D112987

Files:
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -35,8 +35,8 @@
 
 ## Experimental extensions require version string to be explicitly specified
 
-.attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -74,56 +74,56 @@
 .attribute arch, "rv32ifzfh1p0"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0"
 
-.attribute arch, "rv32iv0p10zvlsseg0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvlsseg1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl32b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl32b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl64b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl128b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl128b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl256b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl256b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl512b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl512b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl1024b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl1024b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl2048b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl2048b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl4096b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl4096b1p0"
+# CHECK: attribute  5, 

[PATCH] D117808: [NFC][RISCV] Add end-of-line symbol in target-feature testcases

[Yueh-Ting Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGb58cc9fb2348: [NFC][RISCV] Add end-of-line symbol in 
target-feature testcases (authored by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117808/new/

https://reviews.llvm.org/D117808

Files:
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -7,14 +7,14 @@
 // CHECK-NOT: __riscv_m
 // CHECK-NOT: __riscv_mul
 // CHECK-NOT: __riscv_muldiv
-// CHECK-NOT: __riscv_a 200
+// CHECK-NOT: __riscv_a 200{{$}}
 // CHECK-NOT: __riscv_atomic
-// CHECK-NOT: __riscv_f 200
+// CHECK-NOT: __riscv_f 200{{$}}
 // CHECK-NOT: __riscv_d
 // CHECK-NOT: __riscv_flen
 // CHECK-NOT: __riscv_fdiv
 // CHECK-NOT: __riscv_fsqrt
-// CHECK-NOT: __riscv_c 200
+// CHECK-NOT: __riscv_c 200{{$}}
 // CHECK-NOT: __riscv_compressed
 // CHECK-NOT: __riscv_b
 // CHECK-NOT: __riscv_bitmanip
@@ -38,7 +38,7 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
 // CHECK-M-EXT: __riscv_div 1
-// CHECK-M-EXT: __riscv_m 200
+// CHECK-M-EXT: __riscv_m 200{{$}}
 // CHECK-M-EXT: __riscv_mul 1
 // CHECK-M-EXT: __riscv_muldiv 1
 
@@ -46,14 +46,14 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ia -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
-// CHECK-A-EXT: __riscv_a 200
+// CHECK-A-EXT: __riscv_a 200{{$}}
 // CHECK-A-EXT: __riscv_atomic 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32if -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64if -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
-// CHECK-F-EXT: __riscv_f 200
+// CHECK-F-EXT: __riscv_f 200{{$}}
 // CHECK-F-EXT: __riscv_fdiv 1
 // CHECK-F-EXT: __riscv_flen 32
 // CHECK-F-EXT: __riscv_fsqrt 1
@@ -62,7 +62,7 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
-// CHECK-D-EXT: __riscv_d 200
+// CHECK-D-EXT: __riscv_d 200{{$}}
 // CHECK-D-EXT: __riscv_fdiv 1
 // CHECK-D-EXT: __riscv_flen 64
 // CHECK-D-EXT: __riscv_fsqrt 1
@@ -95,7 +95,7 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ic -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
-// CHECK-C-EXT: __riscv_c 200
+// CHECK-C-EXT: __riscv_c 200{{$}}
 // CHECK-C-EXT: __riscv_compressed 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -150,7 +150,7 @@
 // RUN: -march=rv64izbe0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBE-EXT %s
 // CHECK-ZBE-NOT: __riscv_b
-// CHECK-ZBE-EXT: __riscv_zbe 93000
+// CHECK-ZBE-EXT: __riscv_zbe 93000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32izbf0p93 -x c -E -dM %s \
@@ -159,7 +159,7 @@
 // RUN: -march=rv64izbf0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBF-EXT %s
 // CHECK-ZBF-NOT: __riscv_b
-// CHECK-ZBF-EXT: __riscv_zbf 93000
+// CHECK-ZBF-EXT: __riscv_zbf 93000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32izbm0p93 -x c -E -dM %s \
@@ -168,7 +168,7 @@
 // RUN: -march=rv64izbm0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBM-EXT %s
 // CHECK-ZBM-NOT: __riscv_b
-// CHECK-ZBM-EXT: __riscv_zbm 93000
+// CHECK-ZBM-EXT: __riscv_zbm 93000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32izbp0p93 -x c -E -dM %s \
@@ -177,7 +177,7 @@
 // RUN: -march=rv64izbp0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBP-EXT %s
 // CHECK-ZBP-NOT: __riscv_b
-// CHECK-ZBP-EXT: __riscv_zbp 93000
+// CHECK-ZBP-EXT: __riscv_zbp 93000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32izbr0p93 -x c -E -dM %s \
@@ -186,7 +186,7 @@
 // RUN: -march=rv64izbr0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBR-EXT %s
 // CHECK-ZBR-NOT: __riscv_b
-// CHECK-ZBR-EXT: __riscv_zbr 93000
+// CHECK-ZBR-EXT: __riscv_zbr 93000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
 // RUN: -march=rv32izbs1p0 -x c -E -dM %s \
@@ -210,7 +210,7 @@
 // RUN: -march=rv64izbt0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBT-EXT %s
 

[PATCH] D117808: [NFC][RISCV] Add end-of-line symbol in target-feature testcases

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added a comment.

Missed test case for zfh is found by adding end-of-lines ;)


Repository:
  rG LLVM Github Monorepo

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[PATCH] D112987: [RISCV] Bump rvv-related extensions from 0.10 to 1.0

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD marked an inline comment as done.
eopXD added inline comments.



Comment at: clang/test/Preprocessor/riscv-target-features.c:221
 // RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
-// CHECK-V-EXT: __riscv_v 1
+// CHECK-V-EXT: __riscv_v 100
 // CHECK-V-EXT: __riscv_vector 1

craig.topper wrote:
> Does this line pass even if you don't change it since we don't match to the 
> end of the line? I might suggest we go through this file and put `{{{$}}` on 
> the end of lines, but that can be a separate change. Or we add the `#define` 
> to each line and pass --match-full-lines to FileCheck.
Created D117808


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  rG LLVM Github Monorepo

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[PATCH] D117808: [NFC][RISCV] Add end-of-line symbol in target-feature testcases

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD created this revision.
eopXD added a reviewer: craig.topper.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, 
Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, 
johnrusso, rbar, asb.
eopXD requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117808

Files:
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -7,14 +7,14 @@
 // CHECK-NOT: __riscv_m
 // CHECK-NOT: __riscv_mul
 // CHECK-NOT: __riscv_muldiv
-// CHECK-NOT: __riscv_a 200
+// CHECK-NOT: __riscv_a 200{{$}}
 // CHECK-NOT: __riscv_atomic
-// CHECK-NOT: __riscv_f 200
+// CHECK-NOT: __riscv_f 200{{$}}
 // CHECK-NOT: __riscv_d
 // CHECK-NOT: __riscv_flen
 // CHECK-NOT: __riscv_fdiv
 // CHECK-NOT: __riscv_fsqrt
-// CHECK-NOT: __riscv_c 200
+// CHECK-NOT: __riscv_c 200{{$}}
 // CHECK-NOT: __riscv_compressed
 // CHECK-NOT: __riscv_b
 // CHECK-NOT: __riscv_bitmanip
@@ -38,7 +38,7 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
 // CHECK-M-EXT: __riscv_div 1
-// CHECK-M-EXT: __riscv_m 200
+// CHECK-M-EXT: __riscv_m 200{{$}}
 // CHECK-M-EXT: __riscv_mul 1
 // CHECK-M-EXT: __riscv_muldiv 1
 
@@ -46,14 +46,14 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ia -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
-// CHECK-A-EXT: __riscv_a 200
+// CHECK-A-EXT: __riscv_a 200{{$}}
 // CHECK-A-EXT: __riscv_atomic 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32if -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64if -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
-// CHECK-F-EXT: __riscv_f 200
+// CHECK-F-EXT: __riscv_f 200{{$}}
 // CHECK-F-EXT: __riscv_fdiv 1
 // CHECK-F-EXT: __riscv_flen 32
 // CHECK-F-EXT: __riscv_fsqrt 1
@@ -62,7 +62,7 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
-// CHECK-D-EXT: __riscv_d 200
+// CHECK-D-EXT: __riscv_d 200{{$}}
 // CHECK-D-EXT: __riscv_fdiv 1
 // CHECK-D-EXT: __riscv_flen 64
 // CHECK-D-EXT: __riscv_fsqrt 1
@@ -95,7 +95,7 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ic -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
-// CHECK-C-EXT: __riscv_c 200
+// CHECK-C-EXT: __riscv_c 200{{$}}
 // CHECK-C-EXT: __riscv_compressed 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -150,7 +150,7 @@
 // RUN: -march=rv64izbe0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBE-EXT %s
 // CHECK-ZBE-NOT: __riscv_b
-// CHECK-ZBE-EXT: __riscv_zbe 93000
+// CHECK-ZBE-EXT: __riscv_zbe 93000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32izbf0p93 -x c -E -dM %s \
@@ -159,7 +159,7 @@
 // RUN: -march=rv64izbf0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBF-EXT %s
 // CHECK-ZBF-NOT: __riscv_b
-// CHECK-ZBF-EXT: __riscv_zbf 93000
+// CHECK-ZBF-EXT: __riscv_zbf 93000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32izbm0p93 -x c -E -dM %s \
@@ -168,7 +168,7 @@
 // RUN: -march=rv64izbm0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBM-EXT %s
 // CHECK-ZBM-NOT: __riscv_b
-// CHECK-ZBM-EXT: __riscv_zbm 93000
+// CHECK-ZBM-EXT: __riscv_zbm 93000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32izbp0p93 -x c -E -dM %s \
@@ -177,7 +177,7 @@
 // RUN: -march=rv64izbp0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBP-EXT %s
 // CHECK-ZBP-NOT: __riscv_b
-// CHECK-ZBP-EXT: __riscv_zbp 93000
+// CHECK-ZBP-EXT: __riscv_zbp 93000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32izbr0p93 -x c -E -dM %s \
@@ -186,7 +186,7 @@
 // RUN: -march=rv64izbr0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBR-EXT %s
 // CHECK-ZBR-NOT: __riscv_b
-// CHECK-ZBR-EXT: __riscv_zbr 93000
+// CHECK-ZBR-EXT: __riscv_zbr 93000{{$}}
 
 // RUN: %clang -target 

[PATCH] D112986: [Clang][RISCV] Restrict rvv builtin-s with zve macro-s

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 401687.
eopXD added a comment.

Update code.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112986/new/

https://reviews.llvm.org/D112986

Files:
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -100,6 +100,9 @@
   bool isValid() const { return Valid; }
   bool isScalar() const { return Scale.hasValue() && Scale.getValue() == 0; }
   bool isVector() const { return Scale.hasValue() && Scale.getValue() != 0; }
+  bool isVector(unsigned Width) const {
+return isVector() && ElementBitwidth == Width;
+  }
   bool isFloat() const { return ScalarType == ScalarTypeKind::Float; }
   bool isSignedInteger() const {
 return ScalarType == ScalarTypeKind::SignedInteger;
@@ -134,14 +137,19 @@
 
 using RVVTypePtr = RVVType *;
 using RVVTypes = std::vector;
+using RISCVPredefinedMacroT = uint16_t;
 
-enum RISCVExtension : uint8_t {
+enum RISCVPredefinedMacro : uint16_t {
   Basic = 0,
   F = 1 << 1,
   D = 1 << 2,
   Zfh = 1 << 3,
   Zvlsseg = 1 << 4,
   RV64 = 1 << 5,
+  VectorMaxELen32 = 1 << 6,
+  VectorMaxELen64 = 1 << 7,
+  VectorMaxELenFp32 = 1 << 8,
+  VectorMaxELenFp64 = 1 << 9,
 };
 
 // TODO refactor RVVIntrinsic class design after support all intrinsic
@@ -165,7 +173,7 @@
   // The types we use to obtain the specific LLVM intrinsic. They are index of
   // InputTypes. -1 means the return type.
   std::vector IntrinsicTypes;
-  uint8_t RISCVExtensions = 0;
+  RISCVPredefinedMacroT RISCVPredefinedMacros = 0;
   unsigned NF = 1;
 
 public:
@@ -189,7 +197,9 @@
   bool isMask() const { return IsMask; }
   StringRef getIRName() const { return IRName; }
   StringRef getManualCodegen() const { return ManualCodegen; }
-  uint8_t getRISCVExtensions() const { return RISCVExtensions; }
+  RISCVPredefinedMacroT getRISCVPredefinedMacros() const {
+return RISCVPredefinedMacros;
+  }
   unsigned getNF() const { return NF; }
   const std::vector () const {
 return IntrinsicTypes;
@@ -252,7 +262,7 @@
 
   // Emit the architecture preprocessor definitions. Return true when emits
   // non-empty string.
-  bool emitExtDefStr(uint8_t Extensions, raw_ostream );
+  bool emitMacroRestrictionStr(RISCVPredefinedMacroT PredefinedMacros, raw_ostream );
   // Slice Prototypes string into sub prototype string and process each sub
   // prototype string individually in the Handler.
   void parsePrototypes(StringRef Prototypes,
@@ -790,17 +800,26 @@
   // Init RISC-V extensions
   for (const auto  : OutInTypes) {
 if (T->isFloatVector(16) || T->isFloat(16))
-  RISCVExtensions |= RISCVExtension::Zfh;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::Zfh;
 else if (T->isFloatVector(32) || T->isFloat(32))
-  RISCVExtensions |= RISCVExtension::F;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::F;
 else if (T->isFloatVector(64) || T->isFloat(64))
-  RISCVExtensions |= RISCVExtension::D;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::D;
+
+if (T->isVector(32))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELen32;
+else if (T->isVector(64))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELen64;
+if (T->isFloatVector(32))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELenFp32;
+else if (T->isFloatVector(64))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELenFp64;
   }
   for (auto Extension : RequiredExtensions) {
 if (Extension == "Zvlsseg")
-  RISCVExtensions |= RISCVExtension::Zvlsseg;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::Zvlsseg;
 if (Extension == "RV64")
-  RISCVExtensions |= RISCVExtension::RV64;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::RV64;
   }
 
   // Init OutputType and InputTypes
@@ -984,7 +1003,7 @@
   // The same extension include in the same arch guard marco.
   llvm::stable_sort(Defs, [](const std::unique_ptr ,
  const std::unique_ptr ) {
-return A->getRISCVExtensions() < B->getRISCVExtensions();
+return A->getRISCVPredefinedMacros() < B->getRISCVPredefinedMacros();
   });
 
   OS << "#define __rvv_ai static __inline__\n";
@@ -1283,15 +1302,15 @@
 void RVVEmitter::emitArchMacroAndBody(
 std::vector> , raw_ostream ,
 std::function PrintBody) {
-  uint8_t PrevExt = (*Defs.begin())->getRISCVExtensions();
-  bool NeedEndif = emitExtDefStr(PrevExt, OS);
+  RISCVPredefinedMacroT PrevMacros = (*Defs.begin())->getRISCVPredefinedMacros();
+  bool NeedEndif = emitMacroRestrictionStr(PrevMacros, OS);
   for (auto  : Defs) {
-uint8_t CurExt = Def->getRISCVExtensions();
-if (CurExt != PrevExt) {
+RISCVPredefinedMacroT CurMacros = Def->getRISCVPredefinedMacros();
+if (CurMacros != PrevMacros) {
   if (NeedEndif)
 OS << 

[PATCH] D112986: [Clang][RISCV] Restrict rvv builtin-s with zve macro-s

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 401684.
eopXD added a comment.

Update code.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112986/new/

https://reviews.llvm.org/D112986

Files:
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -100,6 +100,9 @@
   bool isValid() const { return Valid; }
   bool isScalar() const { return Scale.hasValue() && Scale.getValue() == 0; }
   bool isVector() const { return Scale.hasValue() && Scale.getValue() != 0; }
+  bool isVector(unsigned Width) const {
+return isVector() && ElementBitwidth == Width;
+  }
   bool isFloat() const { return ScalarType == ScalarTypeKind::Float; }
   bool isSignedInteger() const {
 return ScalarType == ScalarTypeKind::SignedInteger;
@@ -134,14 +137,19 @@
 
 using RVVTypePtr = RVVType *;
 using RVVTypes = std::vector;
+using RISCVPredefinedMacroT = uint16_t;
 
-enum RISCVExtension : uint8_t {
+enum RISCVPredefinedMacro : uint16_t {
   Basic = 0,
   F = 1 << 1,
   D = 1 << 2,
   Zfh = 1 << 3,
   Zvlsseg = 1 << 4,
   RV64 = 1 << 5,
+  VectorMaxELen32 = 1 << 6,
+  VectorMaxELen64 = 1 << 7,
+  VectorMaxELenFp32 = 1 << 8,
+  VectorMaxELenFp64 = 1 << 9,
 };
 
 // TODO refactor RVVIntrinsic class design after support all intrinsic
@@ -165,7 +173,7 @@
   // The types we use to obtain the specific LLVM intrinsic. They are index of
   // InputTypes. -1 means the return type.
   std::vector IntrinsicTypes;
-  uint8_t RISCVExtensions = 0;
+  RISCVPredefinedMacroT RISCVPredefinedMacros = 0;
   unsigned NF = 1;
 
 public:
@@ -189,7 +197,9 @@
   bool isMask() const { return IsMask; }
   StringRef getIRName() const { return IRName; }
   StringRef getManualCodegen() const { return ManualCodegen; }
-  uint8_t getRISCVExtensions() const { return RISCVExtensions; }
+  RISCVPredefinedMacroT getRISCVPredefinedMacros() const {
+return RISCVPredefinedMacros;
+  }
   unsigned getNF() const { return NF; }
   const std::vector () const {
 return IntrinsicTypes;
@@ -252,7 +262,7 @@
 
   // Emit the architecture preprocessor definitions. Return true when emits
   // non-empty string.
-  bool emitExtDefStr(uint8_t Extensions, raw_ostream );
+  bool emitMacroRestrictionStr(RISCVPredefinedMacroT PredefinedMacros, raw_ostream );
   // Slice Prototypes string into sub prototype string and process each sub
   // prototype string individually in the Handler.
   void parsePrototypes(StringRef Prototypes,
@@ -790,17 +800,26 @@
   // Init RISC-V extensions
   for (const auto  : OutInTypes) {
 if (T->isFloatVector(16) || T->isFloat(16))
-  RISCVExtensions |= RISCVExtension::Zfh;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::Zfh;
 else if (T->isFloatVector(32) || T->isFloat(32))
-  RISCVExtensions |= RISCVExtension::F;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::F;
 else if (T->isFloatVector(64) || T->isFloat(64))
-  RISCVExtensions |= RISCVExtension::D;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::D;
+
+if (T->isVector(32))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELen32;
+else if (T->isVector(64))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELen64;
+if (T->isFloatVector(32))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELenFp32;
+else if (T->isFloatVector(64))
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELenFp64;
   }
   for (auto Extension : RequiredExtensions) {
 if (Extension == "Zvlsseg")
-  RISCVExtensions |= RISCVExtension::Zvlsseg;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::Zvlsseg;
 if (Extension == "RV64")
-  RISCVExtensions |= RISCVExtension::RV64;
+  RISCVPredefinedMacros |= RISCVPredefinedMacro::RV64;
   }
 
   // Init OutputType and InputTypes
@@ -984,7 +1003,7 @@
   // The same extension include in the same arch guard marco.
   llvm::stable_sort(Defs, [](const std::unique_ptr ,
  const std::unique_ptr ) {
-return A->getRISCVExtensions() < B->getRISCVExtensions();
+return A->getRISCVPredefinedMacros() < B->getRISCVPredefinedMacros();
   });
 
   OS << "#define __rvv_ai static __inline__\n";
@@ -1283,15 +1302,15 @@
 void RVVEmitter::emitArchMacroAndBody(
 std::vector> , raw_ostream ,
 std::function PrintBody) {
-  uint8_t PrevExt = (*Defs.begin())->getRISCVExtensions();
-  bool NeedEndif = emitExtDefStr(PrevExt, OS);
+  RISCVPredefinedMacroT PrevMacros = (*Defs.begin())->getRISCVPredefinedMacros();
+  bool NeedEndif = emitMacroRestrictionStr(PrevMacros, OS);
   for (auto  : Defs) {
-uint8_t CurExt = Def->getRISCVExtensions();
-if (CurExt != PrevExt) {
+RISCVPredefinedMacroT CurMacros = Def->getRISCVPredefinedMacros();
+if (CurMacros != PrevMacros) {
   if (NeedEndif)
 OS << 

[PATCH] D112613: [Clang][RISCV] Change TARGET_BUILTIN to require zve32x for vector instruction

[Yueh-Ting Chen via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG14c5fd920b0e: [Clang][RISCV] Change TARGET_BUILTIN to 
require zve32x for vector instruction (authored by eopXD).

Repository:
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Files:
  clang/utils/TableGen/RISCVVEmitter.cpp


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1027,7 +1027,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-v\")\n";
+"ATTRS, \"experimental-zve32x\")\n";
   OS << "#endif\n";
   for (auto  : Defs) {
 auto P =


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1027,7 +1027,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-v\")\n";
+"ATTRS, \"experimental-zve32x\")\n";
   OS << "#endif\n";
   for (auto  : Defs) {
 auto P =
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[PATCH] D112986: [RISCV] Restrict zvamo, zvlsseg with zve macro-s

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD reclaimed this revision.
eopXD added a comment.

This was closed by my misunderstanding.
For clang we still need to do some restrictions based on ELEN.
Reopening.


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[PATCH] D112613: [RISCV] Change TARGET_BUILTIN to require zve32x for vector instruction

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added a comment.

Apply @frasercrmck 's suggested title, thanks!


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[PATCH] D112987: [RISCV] Bump rvv-related extensions from 0.10 to 1.0

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 401564.
eopXD added a comment.

Update code.


Repository:
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Files:
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -35,8 +35,8 @@
 
 ## Experimental extensions require version string to be explicitly specified
 
-.attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -74,56 +74,56 @@
 .attribute arch, "rv32ifzfh1p0"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0"
 
-.attribute arch, "rv32iv0p10zvlsseg0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvlsseg1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl32b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl32b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl64b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl128b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl128b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl256b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl256b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl512b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl512b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl1024b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl1024b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl2048b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl2048b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl4096b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl4096b1p0"
+# CHECK: attribute  5, 

[PATCH] D112613: [RISCV] Change TARGET_BUILTIN require to zve32x for vector instruction

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 401554.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112613/new/

https://reviews.llvm.org/D112613

Files:
  clang/utils/TableGen/RISCVVEmitter.cpp


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1027,7 +1027,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-v\")\n";
+"ATTRS, \"experimental-zve32x\")\n";
   OS << "#endif\n";
   for (auto  : Defs) {
 auto P =


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1027,7 +1027,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-v\")\n";
+"ATTRS, \"experimental-zve32x\")\n";
   OS << "#endif\n";
   for (auto  : Defs) {
 auto P =
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[PATCH] D113336: [RISCV] Imply extensions in RISCVTargetInfo::initFeatureMap

[Yueh-Ting Chen via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG60b6e73769f8: [RISCV] Imply extensions in 
RISCVTargetInfo::initFeatureMap (authored by eopXD).

Repository:
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  https://reviews.llvm.org/D113336/new/

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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -881,3 +881,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -214,10 +214,26 @@
 llvm::StringMap , DiagnosticsEngine , StringRef CPU,
 const std::vector ) const {
 
-  if (getTriple().getArch() == llvm::Triple::riscv64)
+  unsigned XLen = 32;
+
+  if (getTriple().getArch() == llvm::Triple::riscv64) {
 Features["64bit"] = true;
+XLen = 64;
+  }
+
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError ) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -881,3 +881,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -214,10 +214,26 @@
 llvm::StringMap , DiagnosticsEngine , StringRef CPU,
 const std::vector ) const {
 
-  if (getTriple().getArch() == llvm::Triple::riscv64)
+  unsigned XLen = 32;
+
+  if (getTriple().getArch() == llvm::Triple::riscv64) {
 Features["64bit"] = true;
+XLen = 64;
+  }
+
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError ) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+

[PATCH] D112613: [RISCV] Change TARGET_BUILTIN require to zve32x for vector instruction

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 401549.
eopXD added a comment.

Rebase.


Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/utils/TableGen/RISCVVEmitter.cpp


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1027,7 +1027,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-v\")\n";
+"ATTRS, \"experimental-zve32x\")\n";
   OS << "#endif\n";
   for (auto  : Defs) {
 auto P =


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1027,7 +1027,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-v\")\n";
+"ATTRS, \"experimental-zve32x\")\n";
   OS << "#endif\n";
   for (auto  : Defs) {
 auto P =
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[PATCH] D112987: [RISCV] Bump rvv-related extensions from 0.10 to 1.0

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 401546.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112987/new/

https://reviews.llvm.org/D112987

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -881,3 +881,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1027,7 +1027,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-v\")\n";
+"ATTRS, \"experimental-zve32x\")\n";
   OS << "#endif\n";
   for (auto  : Defs) {
 auto P =
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -214,10 +214,26 @@
 llvm::StringMap , DiagnosticsEngine , StringRef CPU,
 const std::vector ) const {
 
-  if (getTriple().getArch() == llvm::Triple::riscv64)
+  unsigned XLen = 32;
+
+  if (getTriple().getArch() == llvm::Triple::riscv64) {
 Features["64bit"] = true;
+XLen = 64;
+  }
+
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError ) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -881,3 +881,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1027,7 +1027,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-v\")\n";
+"ATTRS, \"experimental-zve32x\")\n";
   OS << "#endif\n";
   for (auto  : Defs) {
 auto P =
Index: clang/lib/Basic/Targets/RISCV.cpp

[PATCH] D113336: [RISCV] Imply extensions in RISCVTargetInfo::initFeatureMap

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 401541.
eopXD marked an inline comment as done.
eopXD added a comment.

Update code based on @kito-cheng 's comment.


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  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -881,3 +881,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -214,10 +214,26 @@
 llvm::StringMap , DiagnosticsEngine , StringRef CPU,
 const std::vector ) const {
 
-  if (getTriple().getArch() == llvm::Triple::riscv64)
+  unsigned XLen = 32;
+
+  if (getTriple().getArch() == llvm::Triple::riscv64) {
 Features["64bit"] = true;
+XLen = 64;
+  }
+
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError ) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -881,3 +881,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -214,10 +214,26 @@
 llvm::StringMap , DiagnosticsEngine , StringRef CPU,
 const std::vector ) const {
 
-  if (getTriple().getArch() == llvm::Triple::riscv64)
+  unsigned XLen = 32;
+
+  if (getTriple().getArch() == llvm::Triple::riscv64) {
 Features["64bit"] = true;
+XLen = 64;
+  }
+
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError ) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+

[PATCH] D113336: [RISCV] Imply extensions in RISCVTargetInfo::initFeatureMap

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added a comment.

This patch needs to be landed before D112613  
because clang_cc1 needs to do correct implication from `v`, `zve32f`, `zve64f` 
and `zve64d` and this patch fixes the issue.


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[PATCH] D113336: [RISCV] Imply extensions in RISCVTargetInfo::initFeatureMap

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 401525.
eopXD added a comment.

Rebase to latest main.


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  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -881,3 +881,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -217,7 +217,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError ) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -881,3 +881,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -217,7 +217,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError ) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
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[PATCH] D112986: [RISCV] Restrict zvamo, zvlsseg with zve macro-s

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD abandoned this revision.
eopXD added a comment.

This revision is no longer needed as zvamo and zvlsseg will be removed from 
arch string.


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[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added inline comments.



Comment at: llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll:2
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+zfh \
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zve64d,+f,+d,+zfh \
 ; RUN: -verify-machineinstrs < %s | FileCheck %s

achieveartificialintelligence wrote:
> Do we need `+f` here?
Yes. D should imply F now. Let me create a another patch for it as the current 
patch is for zve.


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[PATCH] D117724: [RISCV] Remove Zvlsseg extension.

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added a comment.

Thank you for doing this patch, I was about to do it after I land zve.


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[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:1499
   foreach nf=2-8 in {
+// Vector Unit-strided Segment Instructions
+def VLSEG#nf#E64_V :

craig.topper wrote:
> The unit-stride and strided with EEW=64 don't require RV64. Just the indexed 
> versions.
Thank you for catching this.


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[PATCH] D112408: [RISCV][MC] Add the zve extension according to the v1.0 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.cpp:184
 Builder.defineMacro("__riscv_v_min_vlen", Twine(MinVLen));
+Builder.defineMacro("__riscv_v_max_eew", Twine(MaxEew));
+Builder.defineMacro("__riscv_v_max_eew_fp", Twine(MaxEewFp));

eopXD wrote:
> craig.topper wrote:
> > eopXD wrote:
> > > craig.topper wrote:
> > > > khchen wrote:
> > > > > craig.topper wrote:
> > > > > > Would't ELEN be the correct term here? Not EEW.
> > > > > https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#182-zve-vector-extensions-for-embedded-processors
> > > > >  shows zve* extensions have `Supported EEW`, I guess it's why the 
> > > > > term is `EEW`.
> > > > > 
> > > > > 
> > > > Is that because that section talks about them as a set of values rather 
> > > > than a single maximum?
> > > I think Zve is restricting the EEW, not ELEN.
> > The spec defines ELEN as "The maximum size in bits of a vector element that 
> > any operation can produce or consume" That sounds like maximum EEW to me.
> > 
> > This statement appears in section 3.4.2
> > 
> > "For standard vector extensions with
> > ELEN=32, fractional LMULs of 1/2 and 1/4 must be supported. For standard 
> > vector extensions with ELEN=64, fractional
> > LMULs of 1/2, 1/4, and 1/8 must be supported."
> > 
> > I take "standard vector extensions with ELEN=32" to mean Zve32x, Zve32f.
> > 
> > And "standard vector extensions with ELEN=64" to mean Zve64x, Zve64f, 
> > Zve64d, and V.
> > 
> > Am I interpreting that incorrectly?
> Yes I think you are correct. Maximum EEW is an alias of ELEN.
> 
> I see that the discussion in 
> https://github.com/riscv-non-isa/riscv-c-api-doc/pull/21 hasn't conclude on 
> whether changing the name into `elen` and `elen_fp`. 
> 
> Should this patch pend until conclusions are drawn?
I see that the discussion has now concluded.
Thank you @craig.topper for pinging at the c-api PR.
Changing macro to `__riscv_v_elen` and `__riscv_v_elen_fp`



Comment at: llvm/include/llvm/Support/RISCVISAInfo.h:65
+  unsigned getMinVLen() const { return MinVLen; }
+  unsigned getMaxEew() const { return MaxEew; }
+  unsigned getMaxEewFp() const { return MaxEewFp; }

eopXD wrote:
> frasercrmck wrote:
> > Aside from the discussion about EEW vs. ELEN, something about the 
> > capitalization irks me. I realise we already have `XLen` but `Eew` looks... 
> > wrong. If other people disagree then that's fine.
> Hi Fraser,
> FYI, I think there is a discussion happening 
> [here](https://github.com/riscv-non-isa/riscv-c-api-doc/pull/21#issuecomment-952307965).
> 
Since we are changing to ELEN now I hope its less disturbing to you and I can 
resolve this ;)


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[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added a comment.

We can land non-macro related code for zve first and continue on proceeding 
patches.


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[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD marked an inline comment as not done.
eopXD added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.cpp:184
 Builder.defineMacro("__riscv_v_min_vlen", Twine(MinVLen));
+Builder.defineMacro("__riscv_v_max_eew", Twine(MaxEew));
+Builder.defineMacro("__riscv_v_max_eew_fp", Twine(MaxEewFp));

craig.topper wrote:
> eopXD wrote:
> > craig.topper wrote:
> > > khchen wrote:
> > > > craig.topper wrote:
> > > > > Would't ELEN be the correct term here? Not EEW.
> > > > https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#182-zve-vector-extensions-for-embedded-processors
> > > >  shows zve* extensions have `Supported EEW`, I guess it's why the term 
> > > > is `EEW`.
> > > > 
> > > > 
> > > Is that because that section talks about them as a set of values rather 
> > > than a single maximum?
> > I think Zve is restricting the EEW, not ELEN.
> The spec defines ELEN as "The maximum size in bits of a vector element that 
> any operation can produce or consume" That sounds like maximum EEW to me.
> 
> This statement appears in section 3.4.2
> 
> "For standard vector extensions with
> ELEN=32, fractional LMULs of 1/2 and 1/4 must be supported. For standard 
> vector extensions with ELEN=64, fractional
> LMULs of 1/2, 1/4, and 1/8 must be supported."
> 
> I take "standard vector extensions with ELEN=32" to mean Zve32x, Zve32f.
> 
> And "standard vector extensions with ELEN=64" to mean Zve64x, Zve64f, Zve64d, 
> and V.
> 
> Am I interpreting that incorrectly?
Yes I think you are correct. Maximum EEW is an alias of ELEN.

I see that the discussion in 
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/21 hasn't conclude on 
whether changing the name into `elen` and `elen_fp`. 

Should this patch pend until conclusions are drawn?


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[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD marked 7 inline comments as done.
eopXD added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.cpp:184
 Builder.defineMacro("__riscv_v_min_vlen", Twine(MinVLen));
+Builder.defineMacro("__riscv_v_max_eew", Twine(MaxEew));
+Builder.defineMacro("__riscv_v_max_eew_fp", Twine(MaxEewFp));

craig.topper wrote:
> khchen wrote:
> > craig.topper wrote:
> > > Would't ELEN be the correct term here? Not EEW.
> > https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#182-zve-vector-extensions-for-embedded-processors
> >  shows zve* extensions have `Supported EEW`, I guess it's why the term is 
> > `EEW`.
> > 
> > 
> Is that because that section talks about them as a set of values rather than 
> a single maximum?
I think Zve is restricting the EEW, not ELEN.


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[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG26bb1b1dab8b: [RISCV] Add the zvl extension according to the 
v1.0 spec (authored by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -36,7 +36,7 @@
 ## Experimental extensions require version string to be explicitly specified
 
 .attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -74,5 +74,41 @@
 .attribute arch, "rv32ifzfh1p0"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0"
 
-.attribute arch, "rv32iv0p10zvlsseg0p10"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+.attribute arch, "rv32iv0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl32b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl128b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl256b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl512b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl1024b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl2048b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl4096b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl8192b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl16384b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl32768b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl65536b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -40,7 +40,7 @@
 ; RV32F: .attribute 5, "rv32i2p0_f2p0"
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
-; RV32V: .attribute 5, "rv32i2p0_v0p10_zvlsseg0p10"
+; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 ; RV32ZFHMIN: .attribute 5, "rv32i2p0_f2p0_zfhmin1p0"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0"
@@ -53,7 +53,7 @@
 ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
 ; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0"
 ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
-; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zvlsseg0p10"
+; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
@@ -72,8 

[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 400238.
eopXD added a comment.

Rebase to latest main.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -36,7 +36,7 @@
 ## Experimental extensions require version string to be explicitly specified
 
 .attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -74,5 +74,41 @@
 .attribute arch, "rv32ifzfh1p0"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0"
 
-.attribute arch, "rv32iv0p10zvlsseg0p10"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+.attribute arch, "rv32iv0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl32b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl128b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl256b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl512b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl1024b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl2048b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl4096b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl8192b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl16384b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl32768b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl65536b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -40,7 +40,7 @@
 ; RV32F: .attribute 5, "rv32i2p0_f2p0"
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
-; RV32V: .attribute 5, "rv32i2p0_v0p10_zvlsseg0p10"
+; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 ; RV32ZFHMIN: .attribute 5, "rv32i2p0_f2p0_zfhmin1p0"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0"
@@ -53,7 +53,7 @@
 ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
 ; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0"
 ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
-; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zvlsseg0p10"
+; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
@@ -72,8 +72,8 @@
 ; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
 ; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0"
 ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
-; RV64V: 

[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 400111.
eopXD added a comment.

Rebase to latest main.
Resolve test case conflicts due to Zvamo removal.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -36,7 +36,7 @@
 ## Experimental extensions require version string to be explicitly specified
 
 .attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -74,5 +74,41 @@
 .attribute arch, "rv32ifzfh0p1"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1_zfhmin0p1"
 
-.attribute arch, "rv32iv0p10zvlsseg0p10"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+.attribute arch, "rv32iv0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl32b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl128b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl256b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl512b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl1024b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl2048b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl4096b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl8192b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl16384b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl32768b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl65536b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -40,7 +40,7 @@
 ; RV32F: .attribute 5, "rv32i2p0_f2p0"
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
-; RV32V: .attribute 5, "rv32i2p0_v0p10_zvlsseg0p10"
+; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 ; RV32ZFHMIN: .attribute 5, "rv32i2p0_f2p0_zfhmin0p1"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1_zfhmin0p1"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0"
@@ -53,7 +53,7 @@
 ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
 ; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0"
 ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
-; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zfhmin0p1_zbb1p0_zvlsseg0p10"
+; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zfhmin0p1_zbb1p0_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
@@ -72,8 +72,8 @@
 ; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
 ; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0"
 ; 

[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCV.td:155-187
+def FeatureStdExtZvl64b : SubtargetFeature<"experimental-zvl64b", "ZvlLen", 
"ExtZvl::Zvl64b",
+   "'Zvl' (Minimum Vector Length) 64",
+   [FeatureStdExtZvl32b]>;
+def FeatureStdExtZvl128b : SubtargetFeature<"experimental-zvl128b", "ZvlLen", 
"ExtZvl::Zvl128b",
+   "'Zvl' (Minimum Vector Length) 128",
+   [FeatureStdExtZvl64b]>;
+def FeatureStdExtZvl256b : SubtargetFeature<"experimental-zvl256b", "ZvlLen", 
"ExtZvl::Zvl256b",

achieveartificialintelligence wrote:
> I think we can write in this way:
> ```
> foreach i = { 5-15 } in {
>   defvar I = !shl(2, i);
>   def FeatureStdExtZvl#I#b
>   : SubtargetFeature<"experimental-zvl"#I#"b", "ZvlLen", 
> "ExtZvl::Zvl"#I#"b",
> "'Zvl' (Minimum Vector Length) "#I,
> [!cast("FeatureStdExtZvl"#!srl(I, 
> 1)#"b")]>;
> }
> ```
Thank you for the tip! I previously don't know TableGen can compute values like 
bit-shift left and do value type casting.

Adapted your code snippet. I modified a bit because `Zvl32b` don't imply 
anything.



Comment at: llvm/lib/Target/RISCV/RISCV.td:188
+   [FeatureStdExtZvl32768b]>;
+def HasStdExtZvl : Predicate<"Subtarget->hasStdExtZvl()">;
+

craig.topper wrote:
> Is this used?
No it is not, deleted.


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[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 400098.
eopXD marked 8 inline comments as done.
eopXD added a comment.

Address comments.
Thanks for reviewing!


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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -36,7 +36,7 @@
 ## Experimental extensions require version string to be explicitly specified
 
 .attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -75,4 +75,40 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1_zfhmin0p1"
 
 .attribute arch, "rv32iv0p10zvamo0p10_zvlsseg0p10"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl32b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl128b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl256b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl512b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl1024b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl2048b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl4096b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl8192b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl16384b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl32768b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl65536b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -18,7 +18,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
@@ -37,14 +37,14 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV64ZBR %s
 ; 

[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added a comment.

ping again, thank you.


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[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added inline comments.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:741-751
+{{"zvl1024b"}, {ImpliedExtsZvl1024b}},
+{{"zvl128b"}, {ImpliedExtsZvl128b}},
+{{"zvl16384b"}, {ImpliedExtsZvl16384b}},
+{{"zvl2048b"}, {ImpliedExtsZvl2048b}},
+{{"zvl256b"}, {ImpliedExtsZvl256b}},
+{{"zvl32768b"}, {ImpliedExtsZvl32768b}},
+{{"zvl4096b"}, {ImpliedExtsZvl4096b}},

achieveartificialintelligence wrote:
> Can we compress the code?
Hi,

Thank you for leaving a comment. Do you mean to embed the list of implied 
extensions into the declaration of `ImpliedExts`? Like:

```
static constexpr ImpliedExtsEntry ImpliedExts[] = {
{{"v"}, {{"zvlsseg", "zvl128b"}}},
   ...
```

In my opinion I think compressing here may not help because the indirection is 
intended to have the implications be in more sorted order that is more human 
readable since `ImpliedExts` are required to be in lexicographical order.

I am just stating my opinion on my current implementation since I think this is 
a coding style problem. What do you think?


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[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 396505.
eopXD added a comment.

Rebase.


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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -36,7 +36,7 @@
 ## Experimental extensions require version string to be explicitly specified
 
 .attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -75,4 +75,40 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1_zfhmin0p1"
 
 .attribute arch, "rv32iv0p10zvamo0p10_zvlsseg0p10"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl32b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl128b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl256b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl512b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl1024b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl2048b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl4096b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl8192b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl16384b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl32768b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl65536b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -18,7 +18,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
@@ -37,14 +37,14 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV64ZBR %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs %s -o - | FileCheck 

[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added a comment.

Ping, thank you.


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[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 394739.
eopXD marked 2 inline comments as done.
eopXD added a comment.

Address comments from Craig.


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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -36,7 +36,7 @@
 ## Experimental extensions require version string to be explicitly specified
 
 .attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -75,4 +75,40 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1_zfhmin0p1"
 
 .attribute arch, "rv32iv0p10zvamo0p10_zvlsseg0p10"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl32b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl128b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl256b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl512b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl1024b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl2048b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl4096b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl8192b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl16384b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl32768b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl65536b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -18,7 +18,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
@@ -37,14 +37,14 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV64ZBR %s
 ; RUN: llc 

[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 394471.
eopXD added a comment.

Rebase to latest main.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -36,7 +36,7 @@
 ## Experimental extensions require version string to be explicitly specified
 
 .attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -75,4 +75,40 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1_zfhmin0p1"
 
 .attribute arch, "rv32iv0p10zvamo0p10_zvlsseg0p10"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl32b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl128b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl256b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl512b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl1024b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl2048b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl4096b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl8192b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl16384b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl32768b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl65536b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -18,7 +18,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
@@ -37,14 +37,14 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV64ZBR %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs %s -o - | 

[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added inline comments.



Comment at: clang/test/Preprocessor/riscv-target-features.c:230
+// RUN: | FileCheck --check-prefix=CHECK-V-MINVLEN %s
+// CHECK-V-MINVLEN: __riscv_v_min_vlen 128

frasercrmck wrote:
> Are we able to test non-default values of `__riscv_v_min_vlen` here?
Yes we shall, thank you for the reminder.



Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.cpp:119
+  if (ZvlLen > RVVVectorBitsMax)
+return 0;
+  // FIXME: Change to >= 32 when VLEN = 32 is supported

frasercrmck wrote:
> Is this intuitive behaviour? If the user supplies `RVVVectorBitsMax` and it's 
> less than `ZvlLen`, should it silently return? Or do we instead see 
> `RVVVectorBitsMax` as a user-guided limit //on top// of the architecture? 
> Which means it can be less but not more? I'm not sure.
Added report_fatal_error here.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 394454.
eopXD marked 3 inline comments as done.
eopXD added a comment.

Rebase and address comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -36,7 +36,7 @@
 ## Experimental extensions require version string to be explicitly specified
 
 .attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -75,4 +75,40 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1_zfhmin0p1"
 
 .attribute arch, "rv32iv0p10zvamo0p10_zvlsseg0p10"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl32b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl128b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl256b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl512b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl1024b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl2048b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl4096b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl8192b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl16384b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl32768b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl65536b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -18,7 +18,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
@@ -37,14 +37,14 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV64ZBR %s
 ; RUN: llc 

[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.cpp:134
  "maximum!");
+  assert(RVVVectorBitsMin >= ZvlLen &&
+ "Minimum V extension vector length should be at least the length "

eopXD wrote:
> eopXD wrote:
> > craig.topper wrote:
> > > eopXD wrote:
> > > > craig.topper wrote:
> > > > > HsiangKai wrote:
> > > > > > Should it be `RVVVectorBitsMin < ZvlLen`?
> > > > > > 
> > > > > > I suggest to return 0 and print a warning message for users.
> > > > > This isn't a good place to print warnings. It would just be a random 
> > > > > message printed to stderr without going through any of clang's 
> > > > > diagnostic infrastructure.
> > > > I think moving the check to `initializeSubtargetDependencies` and use 
> > > > `report_fatal_error` will be a more appropriate approach?
> > > I think that causes clang to generate a crash report and telling the user 
> > > to file a bug.
> > > 
> > > Forgot to mention, all this code is also being modified by D107290
> > I see, then my proposal is invalid.
> > 
> > I am not yet that familiar with the code base. I see 
> > `RISCVFrameLowering.cpp` using `LLVMContext::diagnose`, but 
> > `RISCVSubtarget` here doesn't seem to have access to `LLVMContext`. 
> > 
> > May you recommend a pointer to some diagnose function I can use to tell the 
> > user this is an invalid setting between `RVVVectorBitsMin`(from 
> > `riscv-v-vector-bits-min`) and `ZvlLen` (from `-march=zvl*b`)?
> I see code under `RISCVSubtarget::initializeSubtargetDependencies` also using 
> `report_fatal_error`:
> 
I am marking this thread as done since there are no further comments.

This patch currently uses `report_fatal_error` for it. Although as Craig 
mentioned it may not be ideal.


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[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 394119.
eopXD marked 8 inline comments as done.
eopXD added a comment.

Rebase and address comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -36,7 +36,7 @@
 ## Experimental extensions require version string to be explicitly specified
 
 .attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -75,4 +75,40 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1_zfhmin0p1"
 
 .attribute arch, "rv32iv0p10zvamo0p10_zvlsseg0p10"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl32b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl128b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl256b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl512b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl1024b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl2048b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl4096b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl8192b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl16384b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl32768b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl65536b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -18,7 +18,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
@@ -37,14 +37,14 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV64ZBR %s
 ; RUN: llc 

[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added inline comments.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:782
+if (IsZvlExt) {
+  ExtName.consume_back("b");
+  unsigned ZvlLen;

craig.topper wrote:
> craig.topper wrote:
> > I think we should check the return value from consume_back and getAsInteger 
> > to make sure we really parsed what we think we parsed. That will prevent 
> > surprises if a new extension comes along that also starts with "zvl"
> This would match for "zvlsseg" right now wouldn't it?
> This would match for "zvlsseg" right now wouldn't it?

Yes, you have a point.

`IsZvlExt` should be `ExtName.consume_front("zvl") && 
ExtName.consume_back("b")`.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D112359: [RISCV] Unify depedency check and extension implication parsing logics

[Yueh-Ting Chen via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGa4bf1b449dc0: [RISCV] Unify depedency check and extension 
implication parsing logics (authored by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112359/new/

https://reviews.llvm.org/D112359

Files:
  clang/test/CodeGen/RISCV/riscv-metadata.c
  clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64f-lp64d-abi.c
  clang/test/CodeGen/riscv32-ilp32d-abi.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/test/MC/RISCV/attribute-arch-invalid.s
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -33,47 +33,46 @@
 .attribute arch, "rv32ima2p0_fdc"
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
-.attribute arch, "rv32iv"
+## Experimental extensions require version string to be explicitly specified
+
+.attribute arch, "rv32iv0p10"
 # CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
 
-.attribute arch, "rv32izba"
+.attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
 
-.attribute arch, "rv32izbb"
+.attribute arch, "rv32izbb1p0"
 # CHECK: attribute  5, "rv32i2p0_zbb1p0"
 
-.attribute arch, "rv32izbc"
+.attribute arch, "rv32izbc1p0"
 # CHECK: attribute  5, "rv32i2p0_zbc1p0"
 
-.attribute arch, "rv32izbe"
+.attribute arch, "rv32izbe0p93"
 # CHECK: attribute  5, "rv32i2p0_zbe0p93"
 
-.attribute arch, "rv32izbf"
+.attribute arch, "rv32izbf0p93"
 # CHECK: attribute  5, "rv32i2p0_zbf0p93"
 
-.attribute arch, "rv32izbm"
+.attribute arch, "rv32izbm0p93"
 # CHECK: attribute  5, "rv32i2p0_zbm0p93"
 
-.attribute arch, "rv32izbp"
+.attribute arch, "rv32izbp0p93"
 # CHECK: attribute  5, "rv32i2p0_zbp0p93"
 
-.attribute arch, "rv32izbr"
+.attribute arch, "rv32izbr0p93"
 # CHECK: attribute  5, "rv32i2p0_zbr0p93"
 
-.attribute arch, "rv32izbs"
+.attribute arch, "rv32izbs1p0"
 # CHECK: attribute  5, "rv32i2p0_zbs1p0"
 
-.attribute arch, "rv32izbt"
+.attribute arch, "rv32izbt0p93"
 # CHECK: attribute  5, "rv32i2p0_zbt0p93"
 
-.attribute arch, "rv32ifzfhmin"
+.attribute arch, "rv32ifzfhmin0p1"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfhmin0p1"
 
-.attribute arch, "rv32ifzfh"
+.attribute arch, "rv32ifzfh0p1"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1_zfhmin0p1"
 
-.attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
-
-.attribute arch, "rv32iv_zvamo0p10_zvlsseg"
+.attribute arch, "rv32iv0p10zvamo0p10_zvlsseg0p10"
 # CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
Index: llvm/test/MC/RISCV/attribute-arch-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/attribute-arch-invalid.s
@@ -0,0 +1,48 @@
+## Invalid arch string
+
+# RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 < %s 2>&1 | FileCheck %s
+
+## Version strings are required for experimental extensions
+
+.attribute arch, "rv32iv"
+# CHECK: error: invalid arch name 'rv32iv', experimental extension requires explicit version number `v`
+
+.attribute arch, "rv32izba"
+# CHECK: error: invalid arch name 'rv32izba', experimental extension requires explicit version number `zba`
+
+.attribute arch, "rv32izbb"
+# CHECK: error: invalid arch name 'rv32izbb', experimental extension requires explicit version number `zbb`
+
+.attribute arch, "rv32izbc"
+# CHECK: error: invalid arch name 'rv32izbc', experimental extension requires explicit version number `zbc`
+
+.attribute arch, "rv32izbe"
+# CHECK:  error: invalid arch name 'rv32izbe', experimental extension requires explicit version number `zbe`
+
+.attribute arch, "rv32izbf"
+# CHECK: error: invalid arch name 'rv32izbf', experimental extension requires explicit version number `zbf`
+
+.attribute arch, "rv32izbm"
+# CHECK: error: invalid arch name 'rv32izbm', experimental extension requires explicit version number `zbm`
+
+.attribute arch, "rv32izbp"
+# CHECK: error: invalid arch name 'rv32izbp', experimental extension requires explicit version number `zbp`
+
+.attribute arch, "rv32izbr"
+# CHECK: error: invalid arch name 'rv32izbr', experimental extension requires explicit version number `zbr`
+
+.attribute arch, "rv32izbs"
+# CHECK: error: invalid arch name 'rv32izbs', experimental extension requires explicit version number `zbs`
+
+.attribute arch, "rv32izbt"
+# CHECK: error: invalid arch name 'rv32izbt', 

[PATCH] D109215: [RISCV] Fix arch string parsing for multi-character extensions

[Yueh-Ting Chen via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGe308b8e0c71b: [RISCV] Fix arch string parsing for 
multi-character extensions (authored by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109215/new/

https://reviews.llvm.org/D109215

Files:
  clang/test/Driver/riscv-arch.c
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -72,6 +72,28 @@
   return Ext.consume_front("experimental-");
 }
 
+// This function finds the first character that doesn't belong to a version
+// (e.g. zbe0p93 is extension 'zbe' of version '0p93'). So the function will
+// consume [0-9]*p[0-9]* starting from the backward. An extension name will not
+// end with a digit or the letter 'p', so this function will parse correctly.
+// NOTE: This function is NOT able to take empty strings or strings that only
+// have version numbers and no extension name. It assumes the extension name
+// will be at least more than one character.
+static size_t findFirstNonVersionCharacter(const StringRef ) {
+  if (Ext.size() == 0)
+llvm_unreachable("Already guarded by if-statement in ::parseArchString");
+
+  int Pos = Ext.size() - 1;
+  while (Pos > 0 && isDigit(Ext[Pos]))
+Pos--;
+  if (Pos > 0 && Ext[Pos] == 'p' && isDigit(Ext[Pos - 1])) {
+Pos--;
+while (Pos > 0 && isDigit(Ext[Pos]))
+  Pos--;
+  }
+  return Pos;
+}
+
 struct FindByName {
   FindByName(StringRef Ext) : Ext(Ext){};
   StringRef Ext;
@@ -638,7 +660,7 @@
 
 StringRef Type = getExtensionType(Ext);
 StringRef Desc = getExtensionTypeDesc(Ext);
-auto Pos = Ext.find_if(isDigit);
+size_t Pos = findFirstNonVersionCharacter(Ext) + 1;
 StringRef Name(Ext.substr(0, Pos));
 StringRef Vers(Ext.substr(Pos));
 
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -392,7 +392,7 @@
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0zbp0p93 
-menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck 
-check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s
-// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 
'rv32izbb1p0zbp0p93', multi-character extensions must be separated by 
underscores
+// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 
'rv32izbb1p0zbp0p93', unsupported version number 0.93 for extension 'zbb1p0zbp'
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izba1p0 
-menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -72,6 +72,28 @@
   return Ext.consume_front("experimental-");
 }
 
+// This function finds the first character that doesn't belong to a version
+// (e.g. zbe0p93 is extension 'zbe' of version '0p93'). So the function will
+// consume [0-9]*p[0-9]* starting from the backward. An extension name will not
+// end with a digit or the letter 'p', so this function will parse correctly.
+// NOTE: This function is NOT able to take empty strings or strings that only
+// have version numbers and no extension name. It assumes the extension name
+// will be at least more than one character.
+static size_t findFirstNonVersionCharacter(const StringRef ) {
+  if (Ext.size() == 0)
+llvm_unreachable("Already guarded by if-statement in ::parseArchString");
+
+  int Pos = Ext.size() - 1;
+  while (Pos > 0 && isDigit(Ext[Pos]))
+Pos--;
+  if (Pos > 0 && Ext[Pos] == 'p' && isDigit(Ext[Pos - 1])) {
+Pos--;
+while (Pos > 0 && isDigit(Ext[Pos]))
+  Pos--;
+  }
+  return Pos;
+}
+
 struct FindByName {
   FindByName(StringRef Ext) : Ext(Ext){};
   StringRef Ext;
@@ -638,7 +660,7 @@
 
 StringRef Type = getExtensionType(Ext);
 StringRef Desc = getExtensionTypeDesc(Ext);
-auto Pos = Ext.find_if(isDigit);
+size_t Pos = findFirstNonVersionCharacter(Ext) + 1;
 StringRef Name(Ext.substr(0, Pos));
 StringRef Vers(Ext.substr(Pos));
 
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -392,7 +392,7 @@
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0zbp0p93 -menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s
-// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 'rv32izbb1p0zbp0p93', multi-character extensions must be separated by underscores
+// 

[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 393185.
eopXD added a comment.

Rebase now since the preceeding patches are accepted.
This patch is ready for review.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -36,7 +36,7 @@
 ## Experimental extensions require version string to be explicitly specified
 
 .attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -75,4 +75,40 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1_zfhmin0p1"
 
 .attribute arch, "rv32iv0p10zvamo0p10_zvlsseg0p10"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl32b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl128b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl256b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl512b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl1024b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl2048b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl4096b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl8192b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl16384b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl32768b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl65536b0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -18,7 +18,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
@@ -37,14 +37,14 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV64ZBR %s
 

[PATCH] D112359: [RISCV] Unify depedency check and extension implication parsing logics

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 393181.
eopXD added a comment.

One last rebase before landing.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112359/new/

https://reviews.llvm.org/D112359

Files:
  clang/test/CodeGen/RISCV/riscv-metadata.c
  clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64f-lp64d-abi.c
  clang/test/CodeGen/riscv32-ilp32d-abi.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/test/MC/RISCV/attribute-arch-invalid.s
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -33,47 +33,46 @@
 .attribute arch, "rv32ima2p0_fdc"
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
-.attribute arch, "rv32iv"
+## Experimental extensions require version string to be explicitly specified
+
+.attribute arch, "rv32iv0p10"
 # CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
 
-.attribute arch, "rv32izba"
+.attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
 
-.attribute arch, "rv32izbb"
+.attribute arch, "rv32izbb1p0"
 # CHECK: attribute  5, "rv32i2p0_zbb1p0"
 
-.attribute arch, "rv32izbc"
+.attribute arch, "rv32izbc1p0"
 # CHECK: attribute  5, "rv32i2p0_zbc1p0"
 
-.attribute arch, "rv32izbe"
+.attribute arch, "rv32izbe0p93"
 # CHECK: attribute  5, "rv32i2p0_zbe0p93"
 
-.attribute arch, "rv32izbf"
+.attribute arch, "rv32izbf0p93"
 # CHECK: attribute  5, "rv32i2p0_zbf0p93"
 
-.attribute arch, "rv32izbm"
+.attribute arch, "rv32izbm0p93"
 # CHECK: attribute  5, "rv32i2p0_zbm0p93"
 
-.attribute arch, "rv32izbp"
+.attribute arch, "rv32izbp0p93"
 # CHECK: attribute  5, "rv32i2p0_zbp0p93"
 
-.attribute arch, "rv32izbr"
+.attribute arch, "rv32izbr0p93"
 # CHECK: attribute  5, "rv32i2p0_zbr0p93"
 
-.attribute arch, "rv32izbs"
+.attribute arch, "rv32izbs1p0"
 # CHECK: attribute  5, "rv32i2p0_zbs1p0"
 
-.attribute arch, "rv32izbt"
+.attribute arch, "rv32izbt0p93"
 # CHECK: attribute  5, "rv32i2p0_zbt0p93"
 
-.attribute arch, "rv32ifzfhmin"
+.attribute arch, "rv32ifzfhmin0p1"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfhmin0p1"
 
-.attribute arch, "rv32ifzfh"
+.attribute arch, "rv32ifzfh0p1"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1_zfhmin0p1"
 
-.attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
-
-.attribute arch, "rv32iv_zvamo0p10_zvlsseg"
+.attribute arch, "rv32iv0p10zvamo0p10_zvlsseg0p10"
 # CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
Index: llvm/test/MC/RISCV/attribute-arch-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/attribute-arch-invalid.s
@@ -0,0 +1,48 @@
+## Invalid arch string
+
+# RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 < %s 2>&1 | FileCheck %s
+
+## Version strings are required for experimental extensions
+
+.attribute arch, "rv32iv"
+# CHECK: error: invalid arch name 'rv32iv', experimental extension requires explicit version number `v`
+
+.attribute arch, "rv32izba"
+# CHECK: error: invalid arch name 'rv32izba', experimental extension requires explicit version number `zba`
+
+.attribute arch, "rv32izbb"
+# CHECK: error: invalid arch name 'rv32izbb', experimental extension requires explicit version number `zbb`
+
+.attribute arch, "rv32izbc"
+# CHECK: error: invalid arch name 'rv32izbc', experimental extension requires explicit version number `zbc`
+
+.attribute arch, "rv32izbe"
+# CHECK:  error: invalid arch name 'rv32izbe', experimental extension requires explicit version number `zbe`
+
+.attribute arch, "rv32izbf"
+# CHECK: error: invalid arch name 'rv32izbf', experimental extension requires explicit version number `zbf`
+
+.attribute arch, "rv32izbm"
+# CHECK: error: invalid arch name 'rv32izbm', experimental extension requires explicit version number `zbm`
+
+.attribute arch, "rv32izbp"
+# CHECK: error: invalid arch name 'rv32izbp', experimental extension requires explicit version number `zbp`
+
+.attribute arch, "rv32izbr"
+# CHECK: error: invalid arch name 'rv32izbr', experimental extension requires explicit version number `zbr`
+
+.attribute arch, "rv32izbs"
+# CHECK: error: invalid arch name 'rv32izbs', experimental extension requires explicit version number `zbs`
+
+.attribute arch, "rv32izbt"
+# CHECK: error: invalid arch name 'rv32izbt', experimental extension requires explicit version number `zbt`
+
+.attribute arch, "rv32ifzfhmin"
+# 

[PATCH] D109215: [RISCV] Fix arch string parsing for multi-character extensions

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 393174.
eopXD added a comment.

One last rebase before landing.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109215/new/

https://reviews.llvm.org/D109215

Files:
  clang/test/Driver/riscv-arch.c
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -72,6 +72,28 @@
   return Ext.consume_front("experimental-");
 }
 
+// This function finds the first character that doesn't belong to a version
+// (e.g. zbe0p93 is extension 'zbe' of version '0p93'). So the function will
+// consume [0-9]*p[0-9]* starting from the backward. An extension name will not
+// end with a digit or the letter 'p', so this function will parse correctly.
+// NOTE: This function is NOT able to take empty strings or strings that only
+// have version numbers and no extension name. It assumes the extension name
+// will be at least more than one character.
+static size_t findFirstNonVersionCharacter(const StringRef ) {
+  if (Ext.size() == 0)
+llvm_unreachable("Already guarded by if-statement in ::parseArchString");
+
+  int Pos = Ext.size() - 1;
+  while (Pos > 0 && isDigit(Ext[Pos]))
+Pos--;
+  if (Pos > 0 && Ext[Pos] == 'p' && isDigit(Ext[Pos - 1])) {
+Pos--;
+while (Pos > 0 && isDigit(Ext[Pos]))
+  Pos--;
+  }
+  return Pos;
+}
+
 struct FindByName {
   FindByName(StringRef Ext) : Ext(Ext){};
   StringRef Ext;
@@ -638,7 +660,7 @@
 
 StringRef Type = getExtensionType(Ext);
 StringRef Desc = getExtensionTypeDesc(Ext);
-auto Pos = Ext.find_if(isDigit);
+size_t Pos = findFirstNonVersionCharacter(Ext) + 1;
 StringRef Name(Ext.substr(0, Pos));
 StringRef Vers(Ext.substr(Pos));
 
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -392,7 +392,7 @@
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0zbp0p93 
-menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck 
-check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s
-// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 
'rv32izbb1p0zbp0p93', multi-character extensions must be separated by 
underscores
+// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 
'rv32izbb1p0zbp0p93', unsupported version number 0.93 for extension 'zbb1p0zbp'
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izba1p0 
-menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -72,6 +72,28 @@
   return Ext.consume_front("experimental-");
 }
 
+// This function finds the first character that doesn't belong to a version
+// (e.g. zbe0p93 is extension 'zbe' of version '0p93'). So the function will
+// consume [0-9]*p[0-9]* starting from the backward. An extension name will not
+// end with a digit or the letter 'p', so this function will parse correctly.
+// NOTE: This function is NOT able to take empty strings or strings that only
+// have version numbers and no extension name. It assumes the extension name
+// will be at least more than one character.
+static size_t findFirstNonVersionCharacter(const StringRef ) {
+  if (Ext.size() == 0)
+llvm_unreachable("Already guarded by if-statement in ::parseArchString");
+
+  int Pos = Ext.size() - 1;
+  while (Pos > 0 && isDigit(Ext[Pos]))
+Pos--;
+  if (Pos > 0 && Ext[Pos] == 'p' && isDigit(Ext[Pos - 1])) {
+Pos--;
+while (Pos > 0 && isDigit(Ext[Pos]))
+  Pos--;
+  }
+  return Pos;
+}
+
 struct FindByName {
   FindByName(StringRef Ext) : Ext(Ext){};
   StringRef Ext;
@@ -638,7 +660,7 @@
 
 StringRef Type = getExtensionType(Ext);
 StringRef Desc = getExtensionTypeDesc(Ext);
-auto Pos = Ext.find_if(isDigit);
+size_t Pos = findFirstNonVersionCharacter(Ext) + 1;
 StringRef Name(Ext.substr(0, Pos));
 StringRef Vers(Ext.substr(Pos));
 
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -392,7 +392,7 @@
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0zbp0p93 -menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s
-// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 'rv32izbb1p0zbp0p93', multi-character extensions must be separated by underscores
+// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 'rv32izbb1p0zbp0p93', unsupported version number 0.93 for 

[PATCH] D112359: [RISCV] Unify depedency check and extension implication parsing logics

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 390187.
eopXD added a comment.

- Update code (zfh have been added recently.
- Added test case `attribute-arch-invalid.s` to show that experimental 
extensions need to specify the version explicitly.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112359/new/

https://reviews.llvm.org/D112359

Files:
  clang/test/CodeGen/RISCV/riscv-metadata.c
  clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64f-lp64d-abi.c
  clang/test/CodeGen/riscv32-ilp32d-abi.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/test/MC/RISCV/attribute-arch-invalid.s
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -33,47 +33,46 @@
 .attribute arch, "rv32ima2p0_fdc"
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
-.attribute arch, "rv32iv"
+## Experimental extensions require version string to be explicitly specified
+
+.attribute arch, "rv32iv0p10"
 # CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
 
-.attribute arch, "rv32izba"
+.attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
 
-.attribute arch, "rv32izbb"
+.attribute arch, "rv32izbb1p0"
 # CHECK: attribute  5, "rv32i2p0_zbb1p0"
 
-.attribute arch, "rv32izbc"
+.attribute arch, "rv32izbc1p0"
 # CHECK: attribute  5, "rv32i2p0_zbc1p0"
 
-.attribute arch, "rv32izbe"
+.attribute arch, "rv32izbe0p93"
 # CHECK: attribute  5, "rv32i2p0_zbe0p93"
 
-.attribute arch, "rv32izbf"
+.attribute arch, "rv32izbf0p93"
 # CHECK: attribute  5, "rv32i2p0_zbf0p93"
 
-.attribute arch, "rv32izbm"
+.attribute arch, "rv32izbm0p93"
 # CHECK: attribute  5, "rv32i2p0_zbm0p93"
 
-.attribute arch, "rv32izbp"
+.attribute arch, "rv32izbp0p93"
 # CHECK: attribute  5, "rv32i2p0_zbp0p93"
 
-.attribute arch, "rv32izbr"
+.attribute arch, "rv32izbr0p93"
 # CHECK: attribute  5, "rv32i2p0_zbr0p93"
 
-.attribute arch, "rv32izbs"
+.attribute arch, "rv32izbs1p0"
 # CHECK: attribute  5, "rv32i2p0_zbs1p0"
 
-.attribute arch, "rv32izbt"
+.attribute arch, "rv32izbt0p93"
 # CHECK: attribute  5, "rv32i2p0_zbt0p93"
 
-.attribute arch, "rv32ifzfhmin"
+.attribute arch, "rv32ifzfhmin0p1"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfhmin0p1"
 
-.attribute arch, "rv32ifzfh"
+.attribute arch, "rv32ifzfh0p1"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1_zfhmin0p1"
 
-.attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
-
-.attribute arch, "rv32iv_zvamo0p10_zvlsseg"
+.attribute arch, "rv32iv0p10zvamo0p10_zvlsseg0p10"
 # CHECK: attribute  5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
Index: llvm/test/MC/RISCV/attribute-arch-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/attribute-arch-invalid.s
@@ -0,0 +1,48 @@
+## Invalid arch string
+
+# RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 < %s 2>&1 | FileCheck %s
+
+## Version strings are required for experimental extensions
+
+.attribute arch, "rv32iv"
+# CHECK: error: invalid arch name 'rv32iv', experimental extension requires explicit version number `v`
+
+.attribute arch, "rv32izba"
+# CHECK: error: invalid arch name 'rv32izba', experimental extension requires explicit version number `zba`
+
+.attribute arch, "rv32izbb"
+# CHECK: error: invalid arch name 'rv32izbb', experimental extension requires explicit version number `zbb`
+
+.attribute arch, "rv32izbc"
+# CHECK: error: invalid arch name 'rv32izbc', experimental extension requires explicit version number `zbc`
+
+.attribute arch, "rv32izbe"
+# CHECK:  error: invalid arch name 'rv32izbe', experimental extension requires explicit version number `zbe`
+
+.attribute arch, "rv32izbf"
+# CHECK: error: invalid arch name 'rv32izbf', experimental extension requires explicit version number `zbf`
+
+.attribute arch, "rv32izbm"
+# CHECK: error: invalid arch name 'rv32izbm', experimental extension requires explicit version number `zbm`
+
+.attribute arch, "rv32izbp"
+# CHECK: error: invalid arch name 'rv32izbp', experimental extension requires explicit version number `zbp`
+
+.attribute arch, "rv32izbr"
+# CHECK: error: invalid arch name 'rv32izbr', experimental extension requires explicit version number `zbr`
+
+.attribute arch, "rv32izbs"
+# CHECK: error: invalid arch name 'rv32izbs', experimental extension requires explicit version number `zbs`
+
+.attribute arch, "rv32izbt"
+# CHECK: error: 

[PATCH] D112359: [RISCV] Unify depedency check and extension implication parsing logics

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added a comment.

ping, thank you.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112359/new/

https://reviews.llvm.org/D112359

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[PATCH] D109215: [RISCV] Fix arch string parsing for multi-character extensions

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 385329.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109215/new/

https://reviews.llvm.org/D109215

Files:
  clang/test/Driver/riscv-arch.c
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -72,6 +72,28 @@
   return Ext.consume_front("experimental-");
 }
 
+// This function finds the first character that doesn't belong to a version
+// (e.g. zbe0p93 is extension 'zbe' of version '0p93'). So the function will
+// consume [0-9]*p[0-9]* starting from the backward. An extension name will not
+// end with a digit or the letter 'p', so this function will parse correctly.
+// NOTE: This function is NOT able to take empty strings or strings that only
+// have version numbers and no extension name. It assumes the extension name
+// will be at least more than one character.
+static size_t findFirstNonVersionCharacter(const StringRef ) {
+  if (Ext.size() == 0)
+llvm_unreachable("Already guarded by if-statement in ::parseArchString");
+
+  int Pos = Ext.size() - 1;
+  while (Pos > 0 && isDigit(Ext[Pos]))
+Pos--;
+  if (Pos > 0 && Ext[Pos] == 'p' && isDigit(Ext[Pos - 1])) {
+Pos--;
+while (Pos > 0 && isDigit(Ext[Pos]))
+  Pos--;
+  }
+  return Pos;
+}
+
 struct FindByName {
   FindByName(StringRef Ext) : Ext(Ext){};
   StringRef Ext;
@@ -638,7 +660,7 @@
 
 StringRef Type = getExtensionType(Ext);
 StringRef Desc = getExtensionTypeDesc(Ext);
-auto Pos = Ext.find_if(isDigit);
+size_t Pos = findFirstNonVersionCharacter(Ext) + 1;
 StringRef Name(Ext.substr(0, Pos));
 StringRef Vers(Ext.substr(Pos));
 
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -392,7 +392,7 @@
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0zbp0p93 
-menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck 
-check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s
-// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 
'rv32izbb1p0zbp0p93', multi-character extensions must be separated by 
underscores
+// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 
'rv32izbb1p0zbp0p93', unsupported version number 0.93 for extension 'zbb1p0zbp'
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izba1p0 
-menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -72,6 +72,28 @@
   return Ext.consume_front("experimental-");
 }
 
+// This function finds the first character that doesn't belong to a version
+// (e.g. zbe0p93 is extension 'zbe' of version '0p93'). So the function will
+// consume [0-9]*p[0-9]* starting from the backward. An extension name will not
+// end with a digit or the letter 'p', so this function will parse correctly.
+// NOTE: This function is NOT able to take empty strings or strings that only
+// have version numbers and no extension name. It assumes the extension name
+// will be at least more than one character.
+static size_t findFirstNonVersionCharacter(const StringRef ) {
+  if (Ext.size() == 0)
+llvm_unreachable("Already guarded by if-statement in ::parseArchString");
+
+  int Pos = Ext.size() - 1;
+  while (Pos > 0 && isDigit(Ext[Pos]))
+Pos--;
+  if (Pos > 0 && Ext[Pos] == 'p' && isDigit(Ext[Pos - 1])) {
+Pos--;
+while (Pos > 0 && isDigit(Ext[Pos]))
+  Pos--;
+  }
+  return Pos;
+}
+
 struct FindByName {
   FindByName(StringRef Ext) : Ext(Ext){};
   StringRef Ext;
@@ -638,7 +660,7 @@
 
 StringRef Type = getExtensionType(Ext);
 StringRef Desc = getExtensionTypeDesc(Ext);
-auto Pos = Ext.find_if(isDigit);
+size_t Pos = findFirstNonVersionCharacter(Ext) + 1;
 StringRef Name(Ext.substr(0, Pos));
 StringRef Vers(Ext.substr(Pos));
 
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -392,7 +392,7 @@
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0zbp0p93 -menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s
-// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 'rv32izbb1p0zbp0p93', multi-character extensions must be separated by underscores
+// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 'rv32izbb1p0zbp0p93', unsupported version number 0.93 for extension 'zbb1p0zbp'
 

[PATCH] D112613: [RISCV] Change TARGET_BUILTIN require to zve32x for vector instruction

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD marked an inline comment as done.
eopXD added inline comments.



Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c:3
 // REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v 
-disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck 
--check-prefix=CHECK-RV64 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x 
-target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - | 
opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 

eopXD wrote:
> craig.topper wrote:
> > Why do we need to add zve32x and zve64x to the command line? Doesn't zve64x 
> > imply zve32x?
> Just added D113336 to resolve this. I will rebase this patch and change test 
> cases.
Rebased.


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[PATCH] D112613: [RISCV] Change TARGET_BUILTIN require to zve32x for vector instruction

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 385278.
eopXD added a comment.

Update code.


Repository:
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Files:
  clang/utils/TableGen/RISCVVEmitter.cpp


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1021,7 +1021,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-v\")\n";
+"ATTRS, \"experimental-zve32x\")\n";
   OS << "#endif\n";
   for (auto  : Defs) {
 auto P =


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1021,7 +1021,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-v\")\n";
+"ATTRS, \"experimental-zve32x\")\n";
   OS << "#endif\n";
   for (auto  : Defs) {
 auto P =
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[PATCH] D113336: [RISCV] Let clang_cc1 be able to imply features

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 385277.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113336/new/

https://reviews.llvm.org/D113336

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -846,3 +846,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -217,7 +217,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError ) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -846,3 +846,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -217,7 +217,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError ) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
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[PATCH] D112613: [RISCV] Change TARGET_BUILTIN require to zve32x for vector instruction

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 385276.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112613/new/

https://reviews.llvm.org/D112613

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -846,3 +846,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1021,7 +1021,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-v\")\n";
+"ATTRS, \"experimental-zve32x\")\n";
   OS << "#endif\n";
   for (auto  : Defs) {
 auto P =
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -217,7 +217,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError ) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -846,3 +846,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1021,7 +1021,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-"ATTRS, \"experimental-v\")\n";
+"ATTRS, \"experimental-zve32x\")\n";
   OS << "#endif\n";
   for (auto  : Defs) {
 auto P =
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -217,7 +217,20 @@
   if 

[PATCH] D113336: [RISCV] Let clang_cc1 be able to imply features

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 385275.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113336/new/

https://reviews.llvm.org/D113336

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -846,3 +846,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -217,7 +217,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError ) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -846,3 +846,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -217,7 +217,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError ) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
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[PATCH] D113336: [RISCV] Let clang_cc1 be able to imply features

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 385258.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113336/new/

https://reviews.llvm.org/D113336

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -846,3 +846,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -217,7 +217,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError ) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -846,3 +846,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -217,7 +217,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError ) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
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[PATCH] D113336: [RISCV] Let clang_cc1 be able to imply features

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 385256.
eopXD added a comment.

Rebase.


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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -826,3 +826,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -217,7 +217,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError ) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -826,3 +826,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -67,6 +67,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -217,7 +217,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError ) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
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[PATCH] D112613: [RISCV] Change TARGET_BUILTIN require to zve32x for vector instruction

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added inline comments.



Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c:3
 // REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v 
-disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck 
--check-prefix=CHECK-RV64 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zve32x 
-target-feature +experimental-zve64x -disable-O0-optnone -emit-llvm %s -o - | 
opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 

craig.topper wrote:
> Why do we need to add zve32x and zve64x to the command line? Doesn't zve64x 
> imply zve32x?
Just added D113336 to resolve this. I will rebase this patch and change test 
cases.


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[PATCH] D113336: [Clang][RISCV] Let clang_cc1 be able to imply feautes

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD created this revision.
eopXD added a reviewer: craig.topper.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, 
Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, 
johnrusso, rbar, asb, hiraditya.
eopXD requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.
Herald added projects: clang, LLVM.

Under ASTContext, clang only copies the features from the options with
Target->initFeatureMap, and no implications is done there. Add implication
using RISCVISAInfo.


Repository:
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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -796,3 +796,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -65,6 +65,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -212,7 +212,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError ) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
+return false;
+  }
+
+  return TargetInfo::initFeatureMap(Features, Diags, CPU,
+(*ParseResult)->toFeatureVector());
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.


Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -796,3 +796,17 @@
 
   return Arch.str();
 }
+
+std::vector RISCVISAInfo::toFeatureVector() const {
+  std::vector FeatureVector;
+  for (auto Ext : Exts) {
+std::string ExtName = Ext.first;
+if (ExtName == "i") // i is not recognized in clang -cc1
+  continue;
+std::string Feature = isExperimentalExtension(ExtName)
+  ? "+experimental-" + ExtName
+  : "+" + ExtName;
+FeatureVector.push_back(Feature);
+  }
+  return FeatureVector;
+}
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -65,6 +65,7 @@
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
+  std::vector toFeatureVector() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -212,7 +212,20 @@
   if (getTriple().getArch() == llvm::Triple::riscv64)
 Features["64bit"] = true;
 
-  return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
+  unsigned XLen = Features["64bit"] ? 64 : 32;
+  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+  if (!ParseResult) {
+std::string Buffer;
+llvm::raw_string_ostream OutputErrMsg(Buffer);
+handleAllErrors(ParseResult.takeError(), [&](llvm::StringError ) {
+  OutputErrMsg << ErrMsg.getMessage();
+});
+

[PATCH] D112359: [RISCV] Unify depedency check and extension implication parsing logics

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added a comment.

@asb Thanks for the reply.

To clarify the question, the 2 inconsistencies are:

- Test cases with `clang -cc1` originally don't do dependency check to target 
feature specified (handled by `parseFeatures`)
- Clang driver's -march enforces version to be specified, while llvm allows 
`.attribute` arch to not specify version (and picks the default one)

What this patch tries to do, letting the 2 actions (`parseFeatures` and 
`parseArchString`) rely on the same function call will mean to alter the 
behavior on one of them.
In my humble opinion, it is rather awkward to make this patch an NFC will 
unifying the logics of them.
Maybe we can first come to a conclusion on how do we unify and then implement 
them in this patch.

The main intentions of unifying them is that there will be some implications 
and dependency checks on the addition of zve and zvl,
so unifying the logics will make the addition have less code duplication.


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[PATCH] D109215: [RISCV] Fix arch string parsing for multi-character extensions

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD added a reviewer: asb.
eopXD added a comment.

@asb @jrtc27 
Hi Alex and Jessica,

Although the issue on relaxing naming rules aren't resolved in riscv-isa-manual 
[1], the v-spec v1.0 had come out including `zve` and `zvl` extensions and is 
frozen [2].
I have just finished a series of patch for adding extension `zve`, `zvl` 
support onto LLVM. (Please check the related revisions)
The patches rely on this patch to land, may you share your thought on this.

Thank you.

[1] https://github.com/riscv/riscv-isa-manual/pull/718
[2] https://github.com/riscv/riscv-v-spec/releases/tag/v1.0


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[PATCH] D112987: [RISCV] Bump rvv-related extensions from 0.10 to 1.0

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 383987.
eopXD added a comment.

Rebase.


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Files:
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -33,8 +33,8 @@
 .attribute arch, "rv32ima2p0_fdc"
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
-.attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -69,56 +69,56 @@
 .attribute arch, "rv32ifzfh0p1"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
-.attribute arch, "rv32iv0p10zvamo0p10_zvlsseg0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvamo0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvamo1p0_zvlsseg1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvamo1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl32b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl32b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl64b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl128b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl128b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl256b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl256b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl512b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl512b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl1024b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl1024b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl2048b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl2048b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl4096b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl4096b1p0"
+# CHECK: attribute  5, 

[PATCH] D112987: [RISCV] Bump rvv-related extensions from 0.10 to 1.0

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD created this revision.
eopXD added reviewers: kito.cheng, craig.topper.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, frasercrmck, jdoerfert, evandro, luismarques, apazos, sameer.abuasal, 
s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, 
rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, 
sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
eopXD requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.
Herald added projects: clang, LLVM.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D112987

Files:
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -33,8 +33,8 @@
 .attribute arch, "rv32ima2p0_fdc"
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
-.attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -69,56 +69,56 @@
 .attribute arch, "rv32ifzfh0p1"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
-.attribute arch, "rv32iv0p10zvamo0p10_zvlsseg0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvamo0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvamo1p0_zvlsseg1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvamo1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl32b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl32b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl64b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl128b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl128b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl256b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl256b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl512b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl512b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl1024b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl1024b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv0p10zvl2048b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv1p0zvl2048b1p0"
+# CHECK: attribute  5,