[PATCH] D105926: [PowerPC] Extra test case for LDARX

[Albion Fung via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG2a7711f33a04: [PowerPC] Extra test case for LDARX (authored 
by Conanap).

Repository:
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Files:
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-check-ldarx-opt.ll


Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-check-ldarx-opt.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-check-ldarx-opt.ll
@@ -0,0 +1,88 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX
+
+; Function Attrs: nounwind uwtable
+define dso_local signext i32 @main() local_unnamed_addr {
+; CHECK-LABEL: main:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:li 3, -1
+; CHECK-NEXT:li 4, 0
+; CHECK-NEXT:std 3, -8(1)
+; CHECK-NEXT:addi 3, 1, -8
+; CHECK-NEXT:.p2align 5
+; CHECK-NEXT:  .LBB0_1: # %do.body
+; CHECK-NEXT:#
+; CHECK-NEXT:#APP
+; CHECK-NEXT:ldarx 5, 0, 3
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:stdcx. 4, 0, 3
+; CHECK-NEXT:mfocrf 5, 128
+; CHECK-NEXT:srwi 5, 5, 28
+; CHECK-NEXT:cmplwi 5, 0
+; CHECK-NEXT:beq 0, .LBB0_1
+; CHECK-NEXT:  # %bb.2: # %do.end
+; CHECK-NEXT:ld 3, -8(1)
+; CHECK-NEXT:li 4, 55
+; CHECK-NEXT:cmpldi 3, 0
+; CHECK-NEXT:li 3, 66
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: main:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:li 3, -1
+; CHECK-AIX-NEXT:li 4, 0
+; CHECK-AIX-NEXT:std 3, -8(1)
+; CHECK-AIX-NEXT:addi 3, 1, -8
+; CHECK-AIX-NEXT:.align 5
+; CHECK-AIX-NEXT:  L..BB0_1: # %do.body
+; CHECK-AIX-NEXT:#
+; CHECK-AIX-NEXT:#APP
+; CHECK-AIX-NEXT:ldarx 5, 0, 3
+; CHECK-AIX-NEXT:#NO_APP
+; CHECK-AIX-NEXT:stdcx. 4, 0, 3
+; CHECK-AIX-NEXT:mfocrf 5, 128
+; CHECK-AIX-NEXT:srwi 5, 5, 28
+; CHECK-AIX-NEXT:cmplwi 5, 0
+; CHECK-AIX-NEXT:beq 0, L..BB0_1
+; CHECK-AIX-NEXT:  # %bb.2: # %do.end
+; CHECK-AIX-NEXT:ld 3, -8(1)
+; CHECK-AIX-NEXT:li 4, 55
+; CHECK-AIX-NEXT:cmpldi 3, 0
+; CHECK-AIX-NEXT:li 3, 66
+; CHECK-AIX-NEXT:iseleq 3, 4, 3
+; CHECK-AIX-NEXT:blr
+entry:
+  %x64 = alloca i64, align 8
+  %0 = bitcast i64* %x64 to i8*
+  call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0)
+  store i64 -1, i64* %x64, align 8
+  br label %do.body
+
+do.body:  ; preds = %do.body, %entry
+  %1 = call i64 asm sideeffect "ldarx $0, ${1:y}", "=r,*Z,~{memory}"(i64* 
nonnull %x64)
+  %2 = call i32 @llvm.ppc.stdcx(i8* nonnull %0, i64 0)
+  %tobool.not = icmp eq i32 %2, 0
+  br i1 %tobool.not, label %do.body, label %do.end
+
+do.end:   ; preds = %do.body
+  %3 = load i64, i64* %x64, align 8
+  %cmp = icmp eq i64 %3, 0
+  %. = select i1 %cmp, i32 55, i32 66
+  call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %0)
+  ret i32 %.
+}
+
+; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
+declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
+
+; Function Attrs: nounwind writeonly
+declare i32 @llvm.ppc.stdcx(i8*, i64)
+
+; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
+declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)


Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-check-ldarx-opt.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-check-ldarx-opt.ll
@@ -0,0 +1,88 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX
+
+; Function Attrs: nounwind uwtable
+define dso_local signext i32 @main() local_unnamed_addr {
+; CHECK-LABEL: main:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:li 3, -1
+; CHECK-NEXT:li 4, 0
+; CHECK-NEXT:std 3, -8(1)
+; CHECK-NEXT:addi 3, 1, -8
+; CHECK-NEXT:.p2align 5
+; CHECK-NEXT:  .LBB0_1: # %do.body
+; CHECK-NEXT:#
+; CHECK-NEXT:

[PATCH] D105926: [PowerPC] Extra test case for LDARX

[Kai Luo via Phabricator via cfe-commits]

lkail accepted this revision.
lkail added a comment.
This revision is now accepted and ready to land.

LGTM, thanks!


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[PATCH] D105926: [PowerPC] Extra test case for LDARX

[Albion Fung via Phabricator via cfe-commits]

Conanap updated this revision to Diff 360114.
Conanap added a comment.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Moved to llvm/test/CodeGen/PowerPC


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Files:
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-check-ldarx-opt.ll


Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-check-ldarx-opt.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-check-ldarx-opt.ll
@@ -0,0 +1,88 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX
+
+; Function Attrs: nounwind uwtable
+define dso_local signext i32 @main() local_unnamed_addr {
+; CHECK-LABEL: main:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:li 3, -1
+; CHECK-NEXT:li 4, 0
+; CHECK-NEXT:std 3, -8(1)
+; CHECK-NEXT:addi 3, 1, -8
+; CHECK-NEXT:.p2align 5
+; CHECK-NEXT:  .LBB0_1: # %do.body
+; CHECK-NEXT:#
+; CHECK-NEXT:#APP
+; CHECK-NEXT:ldarx 5, 0, 3
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:stdcx. 4, 0, 3
+; CHECK-NEXT:mfocrf 5, 128
+; CHECK-NEXT:srwi 5, 5, 28
+; CHECK-NEXT:cmplwi 5, 0
+; CHECK-NEXT:beq 0, .LBB0_1
+; CHECK-NEXT:  # %bb.2: # %do.end
+; CHECK-NEXT:ld 3, -8(1)
+; CHECK-NEXT:li 4, 55
+; CHECK-NEXT:cmpldi 3, 0
+; CHECK-NEXT:li 3, 66
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: main:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:li 3, -1
+; CHECK-AIX-NEXT:li 4, 0
+; CHECK-AIX-NEXT:std 3, -8(1)
+; CHECK-AIX-NEXT:addi 3, 1, -8
+; CHECK-AIX-NEXT:.align 5
+; CHECK-AIX-NEXT:  L..BB0_1: # %do.body
+; CHECK-AIX-NEXT:#
+; CHECK-AIX-NEXT:#APP
+; CHECK-AIX-NEXT:ldarx 5, 0, 3
+; CHECK-AIX-NEXT:#NO_APP
+; CHECK-AIX-NEXT:stdcx. 4, 0, 3
+; CHECK-AIX-NEXT:mfocrf 5, 128
+; CHECK-AIX-NEXT:srwi 5, 5, 28
+; CHECK-AIX-NEXT:cmplwi 5, 0
+; CHECK-AIX-NEXT:beq 0, L..BB0_1
+; CHECK-AIX-NEXT:  # %bb.2: # %do.end
+; CHECK-AIX-NEXT:ld 3, -8(1)
+; CHECK-AIX-NEXT:li 4, 55
+; CHECK-AIX-NEXT:cmpldi 3, 0
+; CHECK-AIX-NEXT:li 3, 66
+; CHECK-AIX-NEXT:iseleq 3, 4, 3
+; CHECK-AIX-NEXT:blr
+entry:
+  %x64 = alloca i64, align 8
+  %0 = bitcast i64* %x64 to i8*
+  call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0)
+  store i64 -1, i64* %x64, align 8
+  br label %do.body
+
+do.body:  ; preds = %do.body, %entry
+  %1 = call i64 asm sideeffect "ldarx $0, ${1:y}", "=r,*Z,~{memory}"(i64* 
nonnull %x64)
+  %2 = call i32 @llvm.ppc.stdcx(i8* nonnull %0, i64 0)
+  %tobool.not = icmp eq i32 %2, 0
+  br i1 %tobool.not, label %do.body, label %do.end
+
+do.end:   ; preds = %do.body
+  %3 = load i64, i64* %x64, align 8
+  %cmp = icmp eq i64 %3, 0
+  %. = select i1 %cmp, i32 55, i32 66
+  call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %0)
+  ret i32 %.
+}
+
+; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
+declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
+
+; Function Attrs: nounwind writeonly
+declare i32 @llvm.ppc.stdcx(i8*, i64)
+
+; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
+declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)


Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-check-ldarx-opt.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-check-ldarx-opt.ll
@@ -0,0 +1,88 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX
+
+; Function Attrs: nounwind uwtable
+define dso_local signext i32 @main() local_unnamed_addr {
+; CHECK-LABEL: main:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:li 3, -1
+; CHECK-NEXT:li 4, 0
+; CHECK-NEXT:std 3, -8(1)
+; CHECK-NEXT:addi 3, 1, -8
+; CHECK-NEXT:.p2align 5
+; CHECK-NEXT:  .LBB0_1: # %do.body
+; CHECK-NEXT:#
+; CHECK-NEXT:#APP
+; CHECK-NEXT:ldarx 5, 0, 3
+; 

[PATCH] D105926: [PowerPC] Extra test case for LDARX

[Kai Luo via Phabricator via cfe-commits]

lkail requested changes to this revision.
lkail added a comment.
This revision now requires changes to proceed.

Looks we should put it in `llvm/test/CodeGen/PowerPC`.


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[PATCH] D105926: [PowerPC] Extra test case for LDARX

[Kai Luo via Phabricator via cfe-commits]

lkail added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \

This looks problematic, we should not generate `llc`'s output in clang's test.


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[PATCH] D105926: [PowerPC] Extra test case for LDARX

[Albion Fung via Phabricator via cfe-commits]

Conanap reopened this revision.
Conanap added a comment.
This revision is now accepted and ready to land.

Had to revert this as I'm seeing failures on buildbots not owned by us. The 
error is:

  llc: error: : error: unable to get target for 
'powerpc64le-unknown-linux-gnu', see --version and --triple.

Note that when testing on local machines I did not encounter this error, 
neither did PowerPC buildbots, so I'll need to look into it.


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[PATCH] D105926: [PowerPC] Extra test case for LDARX

[Albion Fung via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG1d3e77e7a842: [PowerPC] Extra test case for LDARX (authored 
by Conanap).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll


Index: clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
@@ -0,0 +1,88 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX
+
+; Function Attrs: nounwind uwtable
+define dso_local signext i32 @main() local_unnamed_addr {
+; CHECK-LABEL: main:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:li 3, -1
+; CHECK-NEXT:li 4, 0
+; CHECK-NEXT:std 3, -8(1)
+; CHECK-NEXT:addi 3, 1, -8
+; CHECK-NEXT:.p2align 5
+; CHECK-NEXT:  .LBB0_1: # %do.body
+; CHECK-NEXT:#
+; CHECK-NEXT:#APP
+; CHECK-NEXT:ldarx 5, 0, 3
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:stdcx. 4, 0, 3
+; CHECK-NEXT:mfocrf 5, 128
+; CHECK-NEXT:srwi 5, 5, 28
+; CHECK-NEXT:cmplwi 5, 0
+; CHECK-NEXT:beq 0, .LBB0_1
+; CHECK-NEXT:  # %bb.2: # %do.end
+; CHECK-NEXT:ld 3, -8(1)
+; CHECK-NEXT:li 4, 55
+; CHECK-NEXT:cmpldi 3, 0
+; CHECK-NEXT:li 3, 66
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: main:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:li 3, -1
+; CHECK-AIX-NEXT:li 4, 0
+; CHECK-AIX-NEXT:std 3, -8(1)
+; CHECK-AIX-NEXT:addi 3, 1, -8
+; CHECK-AIX-NEXT:.align 5
+; CHECK-AIX-NEXT:  L..BB0_1: # %do.body
+; CHECK-AIX-NEXT:#
+; CHECK-AIX-NEXT:#APP
+; CHECK-AIX-NEXT:ldarx 5, 0, 3
+; CHECK-AIX-NEXT:#NO_APP
+; CHECK-AIX-NEXT:stdcx. 4, 0, 3
+; CHECK-AIX-NEXT:mfocrf 5, 128
+; CHECK-AIX-NEXT:srwi 5, 5, 28
+; CHECK-AIX-NEXT:cmplwi 5, 0
+; CHECK-AIX-NEXT:beq 0, L..BB0_1
+; CHECK-AIX-NEXT:  # %bb.2: # %do.end
+; CHECK-AIX-NEXT:ld 3, -8(1)
+; CHECK-AIX-NEXT:li 4, 55
+; CHECK-AIX-NEXT:cmpldi 3, 0
+; CHECK-AIX-NEXT:li 3, 66
+; CHECK-AIX-NEXT:iseleq 3, 4, 3
+; CHECK-AIX-NEXT:blr
+entry:
+  %x64 = alloca i64, align 8
+  %0 = bitcast i64* %x64 to i8*
+  call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0)
+  store i64 -1, i64* %x64, align 8
+  br label %do.body
+
+do.body:  ; preds = %do.body, %entry
+  %1 = call i64 asm sideeffect "ldarx $0, ${1:y}", "=r,*Z,~{memory}"(i64* 
nonnull %x64)
+  %2 = call i32 @llvm.ppc.stdcx(i8* nonnull %0, i64 0)
+  %tobool.not = icmp eq i32 %2, 0
+  br i1 %tobool.not, label %do.body, label %do.end
+
+do.end:   ; preds = %do.body
+  %3 = load i64, i64* %x64, align 8
+  %cmp = icmp eq i64 %3, 0
+  %. = select i1 %cmp, i32 55, i32 66
+  call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %0)
+  ret i32 %.
+}
+
+; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
+declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
+
+; Function Attrs: nounwind writeonly
+declare i32 @llvm.ppc.stdcx(i8*, i64)
+
+; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
+declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)


Index: clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
@@ -0,0 +1,88 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX
+
+; Function Attrs: nounwind uwtable
+define dso_local signext i32 @main() local_unnamed_addr {
+; CHECK-LABEL: main:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:li 3, -1
+; CHECK-NEXT:li 4, 0
+; CHECK-NEXT:std 3, -8(1)
+; CHECK-NEXT:addi 3, 1, -8
+; CHECK-NEXT:.p2align 5
+; CHECK-NEXT:  .LBB0_1: # %do.body
+; CHECK-NEXT:#
+; CHECK-NEXT:#APP
+; CHECK-NEXT:ldarx 5, 0, 3

[PATCH] D105926: [PowerPC] Extra test case for LDARX

[Nemanja Ivanovic via Phabricator via cfe-commits]

nemanjai accepted this revision.
nemanjai added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D105926: [PowerPC] Extra test case for LDARX

[Albion Fung via Phabricator via cfe-commits]

Conanap updated this revision to Diff 359681.
Conanap added a comment.

Removed metadata, -O3 to generate the test case


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Index: clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
@@ -0,0 +1,88 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX
+
+; Function Attrs: nounwind uwtable
+define dso_local signext i32 @main() local_unnamed_addr {
+; CHECK-LABEL: main:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:li 3, -1
+; CHECK-NEXT:li 4, 0
+; CHECK-NEXT:std 3, -8(1)
+; CHECK-NEXT:addi 3, 1, -8
+; CHECK-NEXT:.p2align 5
+; CHECK-NEXT:  .LBB0_1: # %do.body
+; CHECK-NEXT:#
+; CHECK-NEXT:#APP
+; CHECK-NEXT:ldarx 5, 0, 3
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:stdcx. 4, 0, 3
+; CHECK-NEXT:mfocrf 5, 128
+; CHECK-NEXT:srwi 5, 5, 28
+; CHECK-NEXT:cmplwi 5, 0
+; CHECK-NEXT:beq 0, .LBB0_1
+; CHECK-NEXT:  # %bb.2: # %do.end
+; CHECK-NEXT:ld 3, -8(1)
+; CHECK-NEXT:li 4, 55
+; CHECK-NEXT:cmpldi 3, 0
+; CHECK-NEXT:li 3, 66
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: main:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:li 3, -1
+; CHECK-AIX-NEXT:li 4, 0
+; CHECK-AIX-NEXT:std 3, -8(1)
+; CHECK-AIX-NEXT:addi 3, 1, -8
+; CHECK-AIX-NEXT:.align 5
+; CHECK-AIX-NEXT:  L..BB0_1: # %do.body
+; CHECK-AIX-NEXT:#
+; CHECK-AIX-NEXT:#APP
+; CHECK-AIX-NEXT:ldarx 5, 0, 3
+; CHECK-AIX-NEXT:#NO_APP
+; CHECK-AIX-NEXT:stdcx. 4, 0, 3
+; CHECK-AIX-NEXT:mfocrf 5, 128
+; CHECK-AIX-NEXT:srwi 5, 5, 28
+; CHECK-AIX-NEXT:cmplwi 5, 0
+; CHECK-AIX-NEXT:beq 0, L..BB0_1
+; CHECK-AIX-NEXT:  # %bb.2: # %do.end
+; CHECK-AIX-NEXT:ld 3, -8(1)
+; CHECK-AIX-NEXT:li 4, 55
+; CHECK-AIX-NEXT:cmpldi 3, 0
+; CHECK-AIX-NEXT:li 3, 66
+; CHECK-AIX-NEXT:iseleq 3, 4, 3
+; CHECK-AIX-NEXT:blr
+entry:
+  %x64 = alloca i64, align 8
+  %0 = bitcast i64* %x64 to i8*
+  call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0)
+  store i64 -1, i64* %x64, align 8
+  br label %do.body
+
+do.body:  ; preds = %do.body, %entry
+  %1 = call i64 asm sideeffect "ldarx $0, ${1:y}", "=r,*Z,~{memory}"(i64* 
nonnull %x64)
+  %2 = call i32 @llvm.ppc.stdcx(i8* nonnull %0, i64 0)
+  %tobool.not = icmp eq i32 %2, 0
+  br i1 %tobool.not, label %do.body, label %do.end
+
+do.end:   ; preds = %do.body
+  %3 = load i64, i64* %x64, align 8
+  %cmp = icmp eq i64 %3, 0
+  %. = select i1 %cmp, i32 55, i32 66
+  call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %0)
+  ret i32 %.
+}
+
+; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
+declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
+
+; Function Attrs: nounwind writeonly
+declare i32 @llvm.ppc.stdcx(i8*, i64)
+
+; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
+declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)


Index: clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
@@ -0,0 +1,88 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX
+
+; Function Attrs: nounwind uwtable
+define dso_local signext i32 @main() local_unnamed_addr {
+; CHECK-LABEL: main:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:li 3, -1
+; CHECK-NEXT:li 4, 0
+; CHECK-NEXT:std 3, -8(1)
+; CHECK-NEXT:addi 3, 1, -8
+; CHECK-NEXT:.p2align 5
+; CHECK-NEXT:  .LBB0_1: # %do.body
+; CHECK-NEXT:#
+; CHECK-NEXT:#APP
+; CHECK-NEXT:ldarx 5, 0, 3
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:stdcx. 4, 0, 3
+; CHECK-NEXT:mfocrf 5, 128
+; 

[PATCH] D105926: [PowerPC] Extra test case for LDARX

[Albion Fung via Phabricator via cfe-commits]

Conanap added a comment.

In D105926#2885291 , @teemperor wrote:

> Sorry for raising an unrelated topic here, but I can't reach @Conanap 
> directly via the mail from the git commits: @Conanap could you please create 
> the git branches for your patches in your own Github fork instead of the main 
> LLVM repo? LLVM's policy is to have working branches in everyone's private 
> fork (even though I don't think we explicitly tell people that when they get 
> commit access). I'll go ahead and delete your created branches end of next 
> week, but let me know if I should wait a bit longer with that. Thanks!

Ah apologies, I'll do that. Sorry about that! I'll keep the rest of the 
branches on my personal repo; please feel free to delete these by the end of 
next week.


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[PATCH] D105926: [PowerPC] Extra test case for LDARX

[Raphael Isemann via Phabricator via cfe-commits]

teemperor added a comment.

Sorry for raising an unrelated topic here, but I can't reach @Conanap directly 
via the mail from the git commits: @Conanap could you please create the git 
branches for your patches in your own Github fork instead of the main LLVM 
repo? LLVM's policy is to have working branches in everyone's private fork 
(even though I don't think we explicitly tell people that when they get commit 
access). I'll go ahead and delete your created branches end of next week, but 
let me know if I should wait a bit longer with that. Thanks!


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[PATCH] D105926: [PowerPC] Extra test case for LDARX

[Nemanja Ivanovic via Phabricator via cfe-commits]

nemanjai added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll:149
+
+attributes #0 = { noinline nounwind optnone uwtable "frame-pointer"="all" 
"min-legal-vector-width"="0" "no-trapping-math"="true" 
"stack-protector-buffer-size"="8" "target-cpu"="ppc64le" 
"target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+isa-v207-instructions,+power8-vector,+vsx,-isa-v30-instructions,-power9-vector,-privileged,-rop-protect,-spe"
 }
+attributes #1 = { nounwind writeonly }

Get rid of all the metadata please.


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[PATCH] D105926: [PowerPC] Extra test case for LDARX

[Nemanja Ivanovic via Phabricator via cfe-commits]

nemanjai requested changes to this revision.
nemanjai added inline comments.
This revision now requires changes to proceed.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \

Please pre-optimize this test case by running `opt -O3` on it (or produce it 
with `clang -O3 -S -emit-llvm`).


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[PATCH] D105926: [PowerPC] Extra test case for LDARX

[Albion Fung via Phabricator via cfe-commits]

Conanap created this revision.
Herald added subscribers: shchenz, kbarton, nemanjai.
Conanap requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

An extra test case added for the builtin __LDARX.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D105926

Files:
  clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll

Index: clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
@@ -0,0 +1,160 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX
+
+; Function Attrs: noinline nounwind optnone uwtable
+define dso_local signext i32 @main() #0 {
+; CHECK-LABEL: main:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:stw 3, -12(1)
+; CHECK-NEXT:li 3, -1
+; CHECK-NEXT:std 3, -32(1)
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:std 3, -40(1)
+; CHECK-NEXT:  .LBB0_1: # %do.body
+; CHECK-NEXT:#
+; CHECK-NEXT:addi 3, 1, -32
+; CHECK-NEXT:#APP
+; CHECK-NEXT:ldarx 3, 0, 3
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:std 3, -24(1)
+; CHECK-NEXT:addi 3, 1, -32
+; CHECK-NEXT:ld 4, -24(1)
+; CHECK-NEXT:ld 5, -40(1)
+; CHECK-NEXT:and 4, 4, 5
+; CHECK-NEXT:stdcx. 4, 0, 3
+; CHECK-NEXT:mfocrf 3, 128
+; CHECK-NEXT:srwi 3, 3, 28
+; CHECK-NEXT:stw 3, -44(1)
+; CHECK-NEXT:  # %bb.2: # %do.cond
+; CHECK-NEXT:#
+; CHECK-NEXT:lwz 3, -44(1)
+; CHECK-NEXT:cmplwi 3, 0
+; CHECK-NEXT:beq 0, .LBB0_1
+; CHECK-NEXT:b .LBB0_3
+; CHECK-NEXT:  .LBB0_3: # %do.end
+; CHECK-NEXT:ld 3, -32(1)
+; CHECK-NEXT:cmpdi 3, 0
+; CHECK-NEXT:bne 0, .LBB0_5
+; CHECK-NEXT:  # %bb.4: # %if.then
+; CHECK-NEXT:li 3, 55
+; CHECK-NEXT:stw 3, -12(1)
+; CHECK-NEXT:b .LBB0_6
+; CHECK-NEXT:  .LBB0_5: # %if.end
+; CHECK-NEXT:li 3, 66
+; CHECK-NEXT:stw 3, -12(1)
+; CHECK-NEXT:  .LBB0_6: # %return
+; CHECK-NEXT:lwa 3, -12(1)
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: main:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:li 3, 0
+; CHECK-AIX-NEXT:stw 3, -12(1)
+; CHECK-AIX-NEXT:li 4, -1
+; CHECK-AIX-NEXT:std 4, -32(1)
+; CHECK-AIX-NEXT:std 3, -40(1)
+; CHECK-AIX-NEXT:b L..BB0_1
+; CHECK-AIX-NEXT:  L..BB0_1: # %do.body
+; CHECK-AIX-NEXT:#
+; CHECK-AIX-NEXT:addi 3, 1, -32
+; CHECK-AIX-NEXT:#APP
+; CHECK-AIX-NEXT:ldarx 4, 0, 3
+; CHECK-AIX-NEXT:#NO_APP
+; CHECK-AIX-NEXT:std 4, -24(1)
+; CHECK-AIX-NEXT:ld 4, -24(1)
+; CHECK-AIX-NEXT:ld 5, -40(1)
+; CHECK-AIX-NEXT:and 4, 4, 5
+; CHECK-AIX-NEXT:stdcx. 4, 0, 3
+; CHECK-AIX-NEXT:mfocrf 3, 128
+; CHECK-AIX-NEXT:srwi 3, 3, 28
+; CHECK-AIX-NEXT:stw 3, -44(1)
+; CHECK-AIX-NEXT:b L..BB0_2
+; CHECK-AIX-NEXT:  L..BB0_2: # %do.cond
+; CHECK-AIX-NEXT:#
+; CHECK-AIX-NEXT:lwz 3, -44(1)
+; CHECK-AIX-NEXT:cmplwi 3, 0
+; CHECK-AIX-NEXT:beq 0, L..BB0_1
+; CHECK-AIX-NEXT:b L..BB0_3
+; CHECK-AIX-NEXT:  L..BB0_3: # %do.end
+; CHECK-AIX-NEXT:ld 3, -32(1)
+; CHECK-AIX-NEXT:cmpldi 3, 0
+; CHECK-AIX-NEXT:bne 0, L..BB0_5
+; CHECK-AIX-NEXT:b L..BB0_4
+; CHECK-AIX-NEXT:  L..BB0_4: # %if.then
+; CHECK-AIX-NEXT:li 3, 55
+; CHECK-AIX-NEXT:stw 3, -12(1)
+; CHECK-AIX-NEXT:b L..BB0_6
+; CHECK-AIX-NEXT:  L..BB0_5: # %if.end
+; CHECK-AIX-NEXT:li 3, 66
+; CHECK-AIX-NEXT:stw 3, -12(1)
+; CHECK-AIX-NEXT:b L..BB0_6
+; CHECK-AIX-NEXT:  L..BB0_6: # %return
+; CHECK-AIX-NEXT:lwa 3, -12(1)
+; CHECK-AIX-NEXT:blr
+entry:
+  %retval = alloca i32, align 4
+  %x = alloca i64, align 8
+  %x64 = alloca i64, align 8
+  %andval = alloca i64, align 8
+  %k = alloca i32, align 4
+  store i32 0, i32* %retval, align 4
+  store i64 -1, i64* %x64, align 8
+  store i64 0, i64* %andval, align 8
+  br label %do.body
+
+do.body:  ; preds = %do.cond, %entry
+  %0 = call i64 asm sideeffect "ldarx $0, ${1:y}", "=r,*Z,~{memory}"(i64* %x64)
+  store i64 %0, i64* %x, align 8
+  %1 = bitcast i64* %x64 to i8*
+  %2 = load i64, i64* %x, align 8
+  %3 = load i64, i64* %andval, align 8
+  %and = and i64 %2, %3
+  %4 = call i32 @llvm.ppc.stdcx(i8* %1, i64 %and)
+  store i32 %4, i32* %k, align 4
+  br label %do.cond
+
+do.cond:  ; preds = %do.body
+  %5 = load i32, i32* %k, align 4
+  %tobool = icmp ne i32 %5, 0
+  %lnot = xor i1 %tobool, true
+  br i1 %lnot, label %do.body, label