[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG832aae738bec: [asan] Implemented intrinsic for the custom
calling convention similar used by… (authored by kstoimenov).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D107850/new/
https://reviews.llvm.org/D107850
Files:
llvm/include/llvm/IR/Intrinsics.td
llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h
llvm/lib/Target/X86/X86AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.h
llvm/lib/Target/X86/X86InstrCompiler.td
llvm/lib/Target/X86/X86MCInstLower.cpp
llvm/lib/Target/X86/X86RegisterInfo.td
llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
Index: llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
@@ -0,0 +1,253 @@
+; RUN: llc < %s | FileCheck %s
+
+target triple = "x86_64-pc-win"
+
+define void @load1(i8* nocapture readonly %x) {
+; CHECK: callq __asan_check_load1_rn[[RN1:.*]]
+; CHECK: callq __asan_check_store1_rn[[RN1]]
+; CHECK-NEXT: retq
+ call void @llvm.asan.check.memaccess(i8* %x, i32 0)
+ call void @llvm.asan.check.memaccess(i8* %x, i32 32)
+ ret void
+}
+
+define void @load2(i16* nocapture readonly %x) {
+; CHECK: callq __asan_check_load2_rn[[RN2:.*]]
+; CHECK: callq __asan_check_store2_rn[[RN2]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i16* %x to i64
+ %2 = bitcast i16* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 2)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 34)
+ ret void
+}
+
+define void @load4(i32* nocapture readonly %x) {
+; CHECK: callq __asan_check_load4_rn[[RN4:.*]]
+; CHECK: callq __asan_check_store4_rn[[RN4]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i32* %x to i64
+ %2 = bitcast i32* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 4)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 36)
+ ret void
+}
+define void @load8(i64* nocapture readonly %x) {
+; CHECK: callq __asan_check_load8_rn[[RN8:.*]]
+; CHECK: callq __asan_check_store8_rn[[RN8]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i64* %x to i64
+ %2 = bitcast i64* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 6)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 38)
+ ret void
+}
+
+define void @load16(i128* nocapture readonly %x) {
+; CHECK: callq __asan_check_load16_rn[[RN16:.*]]
+; CHECK: callq __asan_check_store16_rn[[RN16]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i128* %x to i64
+ %2 = bitcast i128* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 8)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 40)
+ ret void
+}
+
+; CHECK: .type __asan_check_load1_rn[[RN1]],@function
+; CHECK-NEXT: .weak __asan_check_load1_rn[[RN1]]
+; CHECK-NEXT: .hidden __asan_check_load1_rn[[RN1]]
+; CHECK-NEXT: __asan_check_load1_rn[[RN1]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl [[RET]]
+; CHECK-NEXT: movq[[REG:.*]], %rdi
+; CHECK-NEXT: jmp __asan_report_load1
+
+; CHECK: .type __asan_check_load2_rn[[RN2]],@function
+; CHECK-NEXT: .weak __asan_check_load2_rn[[RN2]]
+; CHECK-NEXT: .hidden __asan_check_load2_rn[[RN2]]
+; CHECK-NEXT: __asan_check_load2_rn[[RN2]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: addl$1, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl [[RET]]
+; CHECK-NEXT: movq[[REG:.*]], %rdi
+; CHECK-NEXT: jmp __asan_report_load2
+
+; CHECK: .type _
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
kstoimenov updated this revision to Diff 368650.
kstoimenov added a comment.
Updated from the revert commit.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D107850/new/
https://reviews.llvm.org/D107850
Files:
llvm/include/llvm/IR/Intrinsics.td
llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h
llvm/lib/Target/X86/X86AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.h
llvm/lib/Target/X86/X86InstrCompiler.td
llvm/lib/Target/X86/X86MCInstLower.cpp
llvm/lib/Target/X86/X86RegisterInfo.td
llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
Index: llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
@@ -0,0 +1,253 @@
+; RUN: llc < %s | FileCheck %s
+
+target triple = "x86_64-pc-win"
+
+define void @load1(i8* nocapture readonly %x) {
+; CHECK: callq __asan_check_load1_rn[[RN1:.*]]
+; CHECK: callq __asan_check_store1_rn[[RN1]]
+; CHECK-NEXT: retq
+ call void @llvm.asan.check.memaccess(i8* %x, i32 0)
+ call void @llvm.asan.check.memaccess(i8* %x, i32 32)
+ ret void
+}
+
+define void @load2(i16* nocapture readonly %x) {
+; CHECK: callq __asan_check_load2_rn[[RN2:.*]]
+; CHECK: callq __asan_check_store2_rn[[RN2]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i16* %x to i64
+ %2 = bitcast i16* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 2)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 34)
+ ret void
+}
+
+define void @load4(i32* nocapture readonly %x) {
+; CHECK: callq __asan_check_load4_rn[[RN4:.*]]
+; CHECK: callq __asan_check_store4_rn[[RN4]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i32* %x to i64
+ %2 = bitcast i32* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 4)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 36)
+ ret void
+}
+define void @load8(i64* nocapture readonly %x) {
+; CHECK: callq __asan_check_load8_rn[[RN8:.*]]
+; CHECK: callq __asan_check_store8_rn[[RN8]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i64* %x to i64
+ %2 = bitcast i64* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 6)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 38)
+ ret void
+}
+
+define void @load16(i128* nocapture readonly %x) {
+; CHECK: callq __asan_check_load16_rn[[RN16:.*]]
+; CHECK: callq __asan_check_store16_rn[[RN16]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i128* %x to i64
+ %2 = bitcast i128* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 8)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 40)
+ ret void
+}
+
+; CHECK: .type __asan_check_load1_rn[[RN1]],@function
+; CHECK-NEXT: .weak __asan_check_load1_rn[[RN1]]
+; CHECK-NEXT: .hidden __asan_check_load1_rn[[RN1]]
+; CHECK-NEXT: __asan_check_load1_rn[[RN1]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl [[RET]]
+; CHECK-NEXT: movq[[REG:.*]], %rdi
+; CHECK-NEXT: jmp __asan_report_load1
+
+; CHECK: .type __asan_check_load2_rn[[RN2]],@function
+; CHECK-NEXT: .weak __asan_check_load2_rn[[RN2]]
+; CHECK-NEXT: .hidden __asan_check_load2_rn[[RN2]]
+; CHECK-NEXT: __asan_check_load2_rn[[RN2]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: addl$1, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl [[RET]]
+; CHECK-NEXT: movq[[REG:.*]], %rdi
+; CHECK-NEXT: jmp __asan_report_load2
+
+; CHECK: .type __asan_check_load4_rn[[RN4]],@function
+; CHECK-NEXT: .weak __asan_check_load4_rn[[RN4]]
+; CHECK-NEXT: .hidden __asan_check_load4_rn[[RN4]]
+
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
kstoimenov added a comment. Thanks! I will submit tomorrow morning. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107850/new/ https://reviews.llvm.org/D107850 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
vitalybuka accepted this revision. vitalybuka added a comment. And if it's straightforward fix for the revert you can "reuse" approvals and land without additional review. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107850/new/ https://reviews.llvm.org/D107850 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
kstoimenov updated this revision to Diff 368510.
kstoimenov added a comment.
Updated with the fix for Bazel build.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D107850/new/
https://reviews.llvm.org/D107850
Files:
llvm/include/llvm/IR/Intrinsics.td
llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h
llvm/lib/Target/X86/X86AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.h
llvm/lib/Target/X86/X86InstrCompiler.td
llvm/lib/Target/X86/X86MCInstLower.cpp
llvm/lib/Target/X86/X86RegisterInfo.td
llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
Index: llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
@@ -0,0 +1,253 @@
+; RUN: llc < %s | FileCheck %s
+
+target triple = "x86_64-pc-win"
+
+define void @load1(i8* nocapture readonly %x) {
+; CHECK: callq __asan_check_load1_rn[[RN1:.*]]
+; CHECK: callq __asan_check_store1_rn[[RN1]]
+; CHECK-NEXT: retq
+ call void @llvm.asan.check.memaccess(i8* %x, i32 0)
+ call void @llvm.asan.check.memaccess(i8* %x, i32 32)
+ ret void
+}
+
+define void @load2(i16* nocapture readonly %x) {
+; CHECK: callq __asan_check_load2_rn[[RN2:.*]]
+; CHECK: callq __asan_check_store2_rn[[RN2]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i16* %x to i64
+ %2 = bitcast i16* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 2)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 34)
+ ret void
+}
+
+define void @load4(i32* nocapture readonly %x) {
+; CHECK: callq __asan_check_load4_rn[[RN4:.*]]
+; CHECK: callq __asan_check_store4_rn[[RN4]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i32* %x to i64
+ %2 = bitcast i32* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 4)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 36)
+ ret void
+}
+define void @load8(i64* nocapture readonly %x) {
+; CHECK: callq __asan_check_load8_rn[[RN8:.*]]
+; CHECK: callq __asan_check_store8_rn[[RN8]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i64* %x to i64
+ %2 = bitcast i64* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 6)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 38)
+ ret void
+}
+
+define void @load16(i128* nocapture readonly %x) {
+; CHECK: callq __asan_check_load16_rn[[RN16:.*]]
+; CHECK: callq __asan_check_store16_rn[[RN16]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i128* %x to i64
+ %2 = bitcast i128* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 8)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 40)
+ ret void
+}
+
+; CHECK: .type __asan_check_load1_rn[[RN1]],@function
+; CHECK-NEXT: .weak __asan_check_load1_rn[[RN1]]
+; CHECK-NEXT: .hidden __asan_check_load1_rn[[RN1]]
+; CHECK-NEXT: __asan_check_load1_rn[[RN1]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl [[RET]]
+; CHECK-NEXT: movq[[REG:.*]], %rdi
+; CHECK-NEXT: jmp __asan_report_load1
+
+; CHECK: .type __asan_check_load2_rn[[RN2]],@function
+; CHECK-NEXT: .weak __asan_check_load2_rn[[RN2]]
+; CHECK-NEXT: .hidden __asan_check_load2_rn[[RN2]]
+; CHECK-NEXT: __asan_check_load2_rn[[RN2]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: addl$1, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl [[RET]]
+; CHECK-NEXT: movq[[REG:.*]], %rdi
+; CHECK-NEXT: jmp __asan_report_load2
+
+; CHECK: .type __asan_check_load4_rn[[RN4]],@function
+; CHECK-NEXT: .weak __asan_check_load4_rn[[RN4]]
+; CHECK-NEXT: .hidden __asan_check_load4_rn[[R
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG9588b685c6b2: [asan] Implemented intrinsic for the custom
calling convention similar used by… (authored by kstoimenov).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D107850/new/
https://reviews.llvm.org/D107850
Files:
llvm/include/llvm/IR/Intrinsics.td
llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h
llvm/lib/Target/X86/X86AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.h
llvm/lib/Target/X86/X86InstrCompiler.td
llvm/lib/Target/X86/X86MCInstLower.cpp
llvm/lib/Target/X86/X86RegisterInfo.td
llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
llvm/tools/llvm-exegesis/CMakeLists.txt
Index: llvm/tools/llvm-exegesis/CMakeLists.txt
===
--- llvm/tools/llvm-exegesis/CMakeLists.txt
+++ llvm/tools/llvm-exegesis/CMakeLists.txt
@@ -1,4 +1,5 @@
set(LLVM_LINK_COMPONENTS
+ Instrumentation
MC
MCParser
Support
Index: llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
@@ -0,0 +1,253 @@
+; RUN: llc < %s | FileCheck %s
+
+target triple = "x86_64-pc-win"
+
+define void @load1(i8* nocapture readonly %x) {
+; CHECK: callq __asan_check_load1_rn[[RN1:.*]]
+; CHECK: callq __asan_check_store1_rn[[RN1]]
+; CHECK-NEXT: retq
+ call void @llvm.asan.check.memaccess(i8* %x, i32 0)
+ call void @llvm.asan.check.memaccess(i8* %x, i32 32)
+ ret void
+}
+
+define void @load2(i16* nocapture readonly %x) {
+; CHECK: callq __asan_check_load2_rn[[RN2:.*]]
+; CHECK: callq __asan_check_store2_rn[[RN2]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i16* %x to i64
+ %2 = bitcast i16* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 2)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 34)
+ ret void
+}
+
+define void @load4(i32* nocapture readonly %x) {
+; CHECK: callq __asan_check_load4_rn[[RN4:.*]]
+; CHECK: callq __asan_check_store4_rn[[RN4]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i32* %x to i64
+ %2 = bitcast i32* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 4)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 36)
+ ret void
+}
+define void @load8(i64* nocapture readonly %x) {
+; CHECK: callq __asan_check_load8_rn[[RN8:.*]]
+; CHECK: callq __asan_check_store8_rn[[RN8]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i64* %x to i64
+ %2 = bitcast i64* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 6)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 38)
+ ret void
+}
+
+define void @load16(i128* nocapture readonly %x) {
+; CHECK: callq __asan_check_load16_rn[[RN16:.*]]
+; CHECK: callq __asan_check_store16_rn[[RN16]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i128* %x to i64
+ %2 = bitcast i128* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 8)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 40)
+ ret void
+}
+
+; CHECK: .type __asan_check_load1_rn[[RN1]],@function
+; CHECK-NEXT: .weak __asan_check_load1_rn[[RN1]]
+; CHECK-NEXT: .hidden __asan_check_load1_rn[[RN1]]
+; CHECK-NEXT: __asan_check_load1_rn[[RN1]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl [[RET]]
+; CHECK-NEXT: movq[[REG:.*]], %rdi
+; CHECK-NEXT: jmp __asan_report_load1
+
+; CHECK: .type __asan_check_load2_rn[[RN2]],@function
+; CHECK-NEXT: .weak __asan_check_load2_rn[[RN2]]
+; CHECK-NEXT: .hidden __asan_check_load2_rn[[RN2]]
+; CHECK-NEXT: __asan_check_load2_rn[[RN2]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq %rcx
+; CHECK-NEXT: movq[[REG]],
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
vitalybuka accepted this revision. vitalybuka added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107850/new/ https://reviews.llvm.org/D107850 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
kstoimenov added inline comments. Comment at: llvm/lib/Target/X86/X86MCInstLower.cpp:1426 + OutStreamer->emitInstruction(MCInstBuilder(X86::AND32ri8) + .addReg(X86::ECX) + .addReg(X86::ECX) vitalybuka wrote: > kstoimenov wrote: > > vitalybuka wrote: > > > what is in ECX register here? > > Should be NoRegister. Done. > Why NoRegister update is not reflected in tests? The instruction template for AND32ri8 expects 2 registers for some reason, which I am not sure why. If I provide only one register I get a clang crash. The emitted instruction is what I want so I didn't dig much deeper into it. Comment at: llvm/test/CodeGen/X86/asan-check-memaccess-or.ll:94 +; CHECK-NEXT: movq[[REG]], %rcx +; CHECK-NEXT: andl$7, %ecx +; CHECK-NEXT: addl$1, %ecx vitalybuka wrote: > What is ECX here? ECX is the lower 3 bits of the address. Is is the second part of the check "((Addr & 7) + AccessSize > k)". Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107850/new/ https://reviews.llvm.org/D107850 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
kstoimenov updated this revision to Diff 368367.
kstoimenov marked an inline comment as done.
kstoimenov added a comment.
Fixed a crash.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D107850/new/
https://reviews.llvm.org/D107850
Files:
llvm/include/llvm/IR/Intrinsics.td
llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h
llvm/lib/Target/X86/X86AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.h
llvm/lib/Target/X86/X86InstrCompiler.td
llvm/lib/Target/X86/X86MCInstLower.cpp
llvm/lib/Target/X86/X86RegisterInfo.td
llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
llvm/tools/llvm-exegesis/CMakeLists.txt
Index: llvm/tools/llvm-exegesis/CMakeLists.txt
===
--- llvm/tools/llvm-exegesis/CMakeLists.txt
+++ llvm/tools/llvm-exegesis/CMakeLists.txt
@@ -1,4 +1,5 @@
set(LLVM_LINK_COMPONENTS
+ Instrumentation
MC
MCParser
Support
Index: llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
@@ -0,0 +1,253 @@
+; RUN: llc < %s | FileCheck %s
+
+target triple = "x86_64-pc-win"
+
+define void @load1(i8* nocapture readonly %x) {
+; CHECK: callq __asan_check_load1_rn[[RN1:.*]]
+; CHECK: callq __asan_check_store1_rn[[RN1]]
+; CHECK-NEXT: retq
+ call void @llvm.asan.check.memaccess(i8* %x, i32 0)
+ call void @llvm.asan.check.memaccess(i8* %x, i32 32)
+ ret void
+}
+
+define void @load2(i16* nocapture readonly %x) {
+; CHECK: callq __asan_check_load2_rn[[RN2:.*]]
+; CHECK: callq __asan_check_store2_rn[[RN2]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i16* %x to i64
+ %2 = bitcast i16* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 2)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 34)
+ ret void
+}
+
+define void @load4(i32* nocapture readonly %x) {
+; CHECK: callq __asan_check_load4_rn[[RN4:.*]]
+; CHECK: callq __asan_check_store4_rn[[RN4]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i32* %x to i64
+ %2 = bitcast i32* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 4)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 36)
+ ret void
+}
+define void @load8(i64* nocapture readonly %x) {
+; CHECK: callq __asan_check_load8_rn[[RN8:.*]]
+; CHECK: callq __asan_check_store8_rn[[RN8]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i64* %x to i64
+ %2 = bitcast i64* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 6)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 38)
+ ret void
+}
+
+define void @load16(i128* nocapture readonly %x) {
+; CHECK: callq __asan_check_load16_rn[[RN16:.*]]
+; CHECK: callq __asan_check_store16_rn[[RN16]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i128* %x to i64
+ %2 = bitcast i128* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 8)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 40)
+ ret void
+}
+
+; CHECK: .type __asan_check_load1_rn[[RN1]],@function
+; CHECK-NEXT: .weak __asan_check_load1_rn[[RN1]]
+; CHECK-NEXT: .hidden __asan_check_load1_rn[[RN1]]
+; CHECK-NEXT: __asan_check_load1_rn[[RN1]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl [[RET]]
+; CHECK-NEXT: movq[[REG:.*]], %rdi
+; CHECK-NEXT: jmp __asan_report_load1
+
+; CHECK: .type __asan_check_load2_rn[[RN2]],@function
+; CHECK-NEXT: .weak __asan_check_load2_rn[[RN2]]
+; CHECK-NEXT: .hidden __asan_check_load2_rn[[RN2]]
+; CHECK-NEXT: __asan_check_load2_rn[[RN2]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: addl$1, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; C
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
kstoimenov updated this revision to Diff 368352.
kstoimenov added a comment.
Second attempt to split AddressSanitizer.cpp.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D107850/new/
https://reviews.llvm.org/D107850
Files:
llvm/include/llvm/IR/Intrinsics.td
llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h
llvm/lib/Target/X86/X86AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.h
llvm/lib/Target/X86/X86InstrCompiler.td
llvm/lib/Target/X86/X86MCInstLower.cpp
llvm/lib/Target/X86/X86RegisterInfo.td
llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
llvm/tools/llvm-exegesis/CMakeLists.txt
Index: llvm/tools/llvm-exegesis/CMakeLists.txt
===
--- llvm/tools/llvm-exegesis/CMakeLists.txt
+++ llvm/tools/llvm-exegesis/CMakeLists.txt
@@ -1,4 +1,5 @@
set(LLVM_LINK_COMPONENTS
+ Instrumentation
MC
MCParser
Support
Index: llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
@@ -0,0 +1,253 @@
+; RUN: llc < %s | FileCheck %s
+
+target triple = "x86_64-pc-win"
+
+define void @load1(i8* nocapture readonly %x) {
+; CHECK: callq __asan_check_load1_rn[[RN1:.*]]
+; CHECK: callq __asan_check_store1_rn[[RN1]]
+; CHECK-NEXT: retq
+ call void @llvm.asan.check.memaccess(i8* %x, i32 0)
+ call void @llvm.asan.check.memaccess(i8* %x, i32 32)
+ ret void
+}
+
+define void @load2(i16* nocapture readonly %x) {
+; CHECK: callq __asan_check_load2_rn[[RN2:.*]]
+; CHECK: callq __asan_check_store2_rn[[RN2]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i16* %x to i64
+ %2 = bitcast i16* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 2)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 34)
+ ret void
+}
+
+define void @load4(i32* nocapture readonly %x) {
+; CHECK: callq __asan_check_load4_rn[[RN4:.*]]
+; CHECK: callq __asan_check_store4_rn[[RN4]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i32* %x to i64
+ %2 = bitcast i32* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 4)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 36)
+ ret void
+}
+define void @load8(i64* nocapture readonly %x) {
+; CHECK: callq __asan_check_load8_rn[[RN8:.*]]
+; CHECK: callq __asan_check_store8_rn[[RN8]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i64* %x to i64
+ %2 = bitcast i64* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 6)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 38)
+ ret void
+}
+
+define void @load16(i128* nocapture readonly %x) {
+; CHECK: callq __asan_check_load16_rn[[RN16:.*]]
+; CHECK: callq __asan_check_store16_rn[[RN16]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i128* %x to i64
+ %2 = bitcast i128* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 8)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 40)
+ ret void
+}
+
+; CHECK: .type __asan_check_load1_rn[[RN1]],@function
+; CHECK-NEXT: .weak __asan_check_load1_rn[[RN1]]
+; CHECK-NEXT: .hidden __asan_check_load1_rn[[RN1]]
+; CHECK-NEXT: __asan_check_load1_rn[[RN1]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl [[RET]]
+; CHECK-NEXT: movq[[REG:.*]], %rdi
+; CHECK-NEXT: jmp __asan_report_load1
+
+; CHECK: .type __asan_check_load2_rn[[RN2]],@function
+; CHECK-NEXT: .weak __asan_check_load2_rn[[RN2]]
+; CHECK-NEXT: .hidden __asan_check_load2_rn[[RN2]]
+; CHECK-NEXT: __asan_check_load2_rn[[RN2]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: addl$1, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT:
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
kstoimenov updated this revision to Diff 368347.
kstoimenov added a comment.
Attempt to split AddressSanitizer.cpp.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D107850/new/
https://reviews.llvm.org/D107850
Files:
llvm/include/llvm/IR/Intrinsics.td
llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h
llvm/lib/Target/X86/X86AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.h
llvm/lib/Target/X86/X86InstrCompiler.td
llvm/lib/Target/X86/X86MCInstLower.cpp
llvm/lib/Target/X86/X86RegisterInfo.td
llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
llvm/tools/llvm-exegesis/CMakeLists.txt
Index: llvm/tools/llvm-exegesis/CMakeLists.txt
===
--- llvm/tools/llvm-exegesis/CMakeLists.txt
+++ llvm/tools/llvm-exegesis/CMakeLists.txt
@@ -1,4 +1,5 @@
set(LLVM_LINK_COMPONENTS
+ Instrumentation
MC
MCParser
Support
Index: llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
@@ -0,0 +1,253 @@
+; RUN: llc < %s | FileCheck %s
+
+target triple = "x86_64-pc-win"
+
+define void @load1(i8* nocapture readonly %x) {
+; CHECK: callq __asan_check_load1_rn[[RN1:.*]]
+; CHECK: callq __asan_check_store1_rn[[RN1]]
+; CHECK-NEXT: retq
+ call void @llvm.asan.check.memaccess(i8* %x, i32 0)
+ call void @llvm.asan.check.memaccess(i8* %x, i32 32)
+ ret void
+}
+
+define void @load2(i16* nocapture readonly %x) {
+; CHECK: callq __asan_check_load2_rn[[RN2:.*]]
+; CHECK: callq __asan_check_store2_rn[[RN2]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i16* %x to i64
+ %2 = bitcast i16* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 2)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 34)
+ ret void
+}
+
+define void @load4(i32* nocapture readonly %x) {
+; CHECK: callq __asan_check_load4_rn[[RN4:.*]]
+; CHECK: callq __asan_check_store4_rn[[RN4]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i32* %x to i64
+ %2 = bitcast i32* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 4)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 36)
+ ret void
+}
+define void @load8(i64* nocapture readonly %x) {
+; CHECK: callq __asan_check_load8_rn[[RN8:.*]]
+; CHECK: callq __asan_check_store8_rn[[RN8]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i64* %x to i64
+ %2 = bitcast i64* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 6)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 38)
+ ret void
+}
+
+define void @load16(i128* nocapture readonly %x) {
+; CHECK: callq __asan_check_load16_rn[[RN16:.*]]
+; CHECK: callq __asan_check_store16_rn[[RN16]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i128* %x to i64
+ %2 = bitcast i128* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 8)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 40)
+ ret void
+}
+
+; CHECK: .type __asan_check_load1_rn[[RN1]],@function
+; CHECK-NEXT: .weak __asan_check_load1_rn[[RN1]]
+; CHECK-NEXT: .hidden __asan_check_load1_rn[[RN1]]
+; CHECK-NEXT: __asan_check_load1_rn[[RN1]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl [[RET]]
+; CHECK-NEXT: movq[[REG:.*]], %rdi
+; CHECK-NEXT: jmp __asan_report_load1
+
+; CHECK: .type __asan_check_load2_rn[[RN2]],@function
+; CHECK-NEXT: .weak __asan_check_load2_rn[[RN2]]
+; CHECK-NEXT: .hidden __asan_check_load2_rn[[RN2]]
+; CHECK-NEXT: __asan_check_load2_rn[[RN2]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: addl$1, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl [[RET]]
+; CHECK-
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
vitalybuka added inline comments. Comment at: llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h:166 + ASanAccessInfo(bool IsWrite, bool CompileKernel, uint8_t AccessSizeIndex); +}; + .cpp file is missing Comment at: llvm/lib/Target/X86/X86MCInstLower.cpp:1426 + OutStreamer->emitInstruction(MCInstBuilder(X86::AND32ri8) + .addReg(X86::ECX) + .addReg(X86::ECX) kstoimenov wrote: > vitalybuka wrote: > > what is in ECX register here? > Should be NoRegister. Done. Why NoRegister update is not reflected in tests? Comment at: llvm/test/CodeGen/X86/asan-check-memaccess-or.ll:94 +; CHECK-NEXT: movq[[REG]], %rcx +; CHECK-NEXT: andl$7, %ecx +; CHECK-NEXT: addl$1, %ecx What is ECX here? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107850/new/ https://reviews.llvm.org/D107850 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
kstoimenov updated this revision to Diff 368236.
kstoimenov added a comment.
Fixed code generation bug.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D107850/new/
https://reviews.llvm.org/D107850
Files:
llvm/include/llvm/IR/Intrinsics.td
llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h
llvm/lib/Target/X86/X86AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.h
llvm/lib/Target/X86/X86InstrCompiler.td
llvm/lib/Target/X86/X86MCInstLower.cpp
llvm/lib/Target/X86/X86RegisterInfo.td
llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
llvm/tools/llvm-exegesis/CMakeLists.txt
Index: llvm/tools/llvm-exegesis/CMakeLists.txt
===
--- llvm/tools/llvm-exegesis/CMakeLists.txt
+++ llvm/tools/llvm-exegesis/CMakeLists.txt
@@ -1,4 +1,5 @@
set(LLVM_LINK_COMPONENTS
+ Instrumentation
MC
MCParser
Support
Index: llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
@@ -0,0 +1,253 @@
+; RUN: llc < %s | FileCheck %s
+
+target triple = "x86_64-pc-win"
+
+define void @load1(i8* nocapture readonly %x) {
+; CHECK: callq __asan_check_load1_rn[[RN1:.*]]
+; CHECK: callq __asan_check_store1_rn[[RN1]]
+; CHECK-NEXT: retq
+ call void @llvm.asan.check.memaccess(i8* %x, i32 0)
+ call void @llvm.asan.check.memaccess(i8* %x, i32 32)
+ ret void
+}
+
+define void @load2(i16* nocapture readonly %x) {
+; CHECK: callq __asan_check_load2_rn[[RN2:.*]]
+; CHECK: callq __asan_check_store2_rn[[RN2]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i16* %x to i64
+ %2 = bitcast i16* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 2)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 34)
+ ret void
+}
+
+define void @load4(i32* nocapture readonly %x) {
+; CHECK: callq __asan_check_load4_rn[[RN4:.*]]
+; CHECK: callq __asan_check_store4_rn[[RN4]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i32* %x to i64
+ %2 = bitcast i32* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 4)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 36)
+ ret void
+}
+define void @load8(i64* nocapture readonly %x) {
+; CHECK: callq __asan_check_load8_rn[[RN8:.*]]
+; CHECK: callq __asan_check_store8_rn[[RN8]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i64* %x to i64
+ %2 = bitcast i64* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 6)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 38)
+ ret void
+}
+
+define void @load16(i128* nocapture readonly %x) {
+; CHECK: callq __asan_check_load16_rn[[RN16:.*]]
+; CHECK: callq __asan_check_store16_rn[[RN16]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i128* %x to i64
+ %2 = bitcast i128* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 8)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 40)
+ ret void
+}
+
+; CHECK: .type __asan_check_load1_rn[[RN1]],@function
+; CHECK-NEXT: .weak __asan_check_load1_rn[[RN1]]
+; CHECK-NEXT: .hidden __asan_check_load1_rn[[RN1]]
+; CHECK-NEXT: __asan_check_load1_rn[[RN1]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl [[RET]]
+; CHECK-NEXT: movq[[REG:.*]], %rdi
+; CHECK-NEXT: jmp __asan_report_load1
+
+; CHECK: .type __asan_check_load2_rn[[RN2]],@function
+; CHECK-NEXT: .weak __asan_check_load2_rn[[RN2]]
+; CHECK-NEXT: .hidden __asan_check_load2_rn[[RN2]]
+; CHECK-NEXT: __asan_check_load2_rn[[RN2]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: addl$1, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl [[RET]]
+; CHECK-NEXT:
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
kstoimenov added inline comments.
Comment at: llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h:150
+namespace AsanAccessInfo {
+
vitalybuka wrote:
> kstoimenov wrote:
> > vitalybuka wrote:
> > > It's not how enums described here
> > > https://llvm.org/docs/CodingStandards.html#id43
> > > Also it's common to use enum class nowerdays.
> > >
> > >
> > > However this one does not need to be enum and just "constexpr size_t"
> > I wanted to be as close as possible to the HWASan style. Please let me know
> > if you want me to change it.
> They are quite unrelated, no need to violate coding style to match them.
>
> Also packing and unpacking implementation unnecessary separated.
> Maybe something like this and keep bit arithmetic in a single cpp file:
> ```
> struct AsanAccessInfo {
> uint8_t AccessSize;
> bool CompileKernel;
> bool IsWrite;
> ...
>
> explicit AsanAccessInfo(int64_t packed);
> int64_t Pack() const;
> }
> ```
>
> Also math a little bit simpler if 4bit field is the last
I like the idea. Keeps things well encapsulated in the implementation file.
Done.
Comment at: llvm/lib/Target/X86/X86MCInstLower.cpp:1426
+ OutStreamer->emitInstruction(MCInstBuilder(X86::AND32ri8)
+ .addReg(X86::ECX)
+ .addReg(X86::ECX)
vitalybuka wrote:
> what is in ECX register here?
Should be NoRegister. Done.
Comment at: llvm/lib/Target/X86/X86MCInstLower.cpp:1561-1564
+bool CompileKernel = (AccessInfo >> ASanAccessInfo::CompileKernelShift) &
1;
+int32_t AccessSizeIndex =
+(AccessInfo >> ASanAccessInfo::AccessSizeShift) & 0xf;
+bool IsWrite = (AccessInfo >> ASanAccessInfo::IsWriteShift) & 1;
vitalybuka wrote:
> as-is shifts are in the header, and masks are here, which is not nice.
Encapsulated in the implementation file as you have recommended.
Comment at: llvm/test/CodeGen/X86/asan-check-memaccess-add.ll:6
+define void @load1(i8* nocapture readonly %x) {
+; CHECK: callq __asan_check_load1_rn[[RN1:.*]]
+; CHECK: callq __asan_check_store1_rn[[RN1]]
vitalybuka wrote:
> should we also check how we load registers before callq?
The issue is that there is no load instruction, because the registers are
implied.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D107850/new/
https://reviews.llvm.org/D107850
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
kstoimenov updated this revision to Diff 368162.
kstoimenov marked 4 inline comments as done.
kstoimenov added a comment.
Addressed the comments.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D107850/new/
https://reviews.llvm.org/D107850
Files:
llvm/include/llvm/IR/Intrinsics.td
llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h
llvm/lib/Target/X86/X86AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.h
llvm/lib/Target/X86/X86InstrCompiler.td
llvm/lib/Target/X86/X86MCInstLower.cpp
llvm/lib/Target/X86/X86RegisterInfo.td
llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
llvm/tools/llvm-exegesis/CMakeLists.txt
Index: llvm/tools/llvm-exegesis/CMakeLists.txt
===
--- llvm/tools/llvm-exegesis/CMakeLists.txt
+++ llvm/tools/llvm-exegesis/CMakeLists.txt
@@ -1,4 +1,5 @@
set(LLVM_LINK_COMPONENTS
+ Instrumentation
MC
MCParser
Support
Index: llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
@@ -0,0 +1,253 @@
+; RUN: llc < %s | FileCheck %s
+
+target triple = "x86_64-pc-win"
+
+define void @load1(i8* nocapture readonly %x) {
+; CHECK: callq __asan_check_load1_rn[[RN1:.*]]
+; CHECK: callq __asan_check_store1_rn[[RN1]]
+; CHECK-NEXT: retq
+ call void @llvm.asan.check.memaccess(i8* %x, i32 0)
+ call void @llvm.asan.check.memaccess(i8* %x, i32 32)
+ ret void
+}
+
+define void @load2(i16* nocapture readonly %x) {
+; CHECK: callq __asan_check_load2_rn[[RN2:.*]]
+; CHECK: callq __asan_check_store2_rn[[RN2]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i16* %x to i64
+ %2 = bitcast i16* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 2)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 34)
+ ret void
+}
+
+define void @load4(i32* nocapture readonly %x) {
+; CHECK: callq __asan_check_load4_rn[[RN4:.*]]
+; CHECK: callq __asan_check_store4_rn[[RN4]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i32* %x to i64
+ %2 = bitcast i32* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 4)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 36)
+ ret void
+}
+define void @load8(i64* nocapture readonly %x) {
+; CHECK: callq __asan_check_load8_rn[[RN8:.*]]
+; CHECK: callq __asan_check_store8_rn[[RN8]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i64* %x to i64
+ %2 = bitcast i64* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 6)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 38)
+ ret void
+}
+
+define void @load16(i128* nocapture readonly %x) {
+; CHECK: callq __asan_check_load16_rn[[RN16:.*]]
+; CHECK: callq __asan_check_store16_rn[[RN16]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i128* %x to i64
+ %2 = bitcast i128* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 8)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 40)
+ ret void
+}
+
+; CHECK: .type __asan_check_load1_rn[[RN1]],@function
+; CHECK-NEXT: .weak __asan_check_load1_rn[[RN1]]
+; CHECK-NEXT: .hidden __asan_check_load1_rn[[RN1]]
+; CHECK-NEXT: __asan_check_load1_rn[[RN1]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl [[RET]]
+; CHECK-NEXT: movq[[REG:.*]], %rdi
+; CHECK-NEXT: jmp __asan_report_load1
+
+; CHECK: .type __asan_check_load2_rn[[RN2]],@function
+; CHECK-NEXT: .weak __asan_check_load2_rn[[RN2]]
+; CHECK-NEXT: .hidden __asan_check_load2_rn[[RN2]]
+; CHECK-NEXT: __asan_check_load2_rn[[RN2]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: addl$1, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT:
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
vitalybuka added inline comments.
Comment at: llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h:150
+namespace AsanAccessInfo {
+
kstoimenov wrote:
> vitalybuka wrote:
> > It's not how enums described here
> > https://llvm.org/docs/CodingStandards.html#id43
> > Also it's common to use enum class nowerdays.
> >
> >
> > However this one does not need to be enum and just "constexpr size_t"
> I wanted to be as close as possible to the HWASan style. Please let me know
> if you want me to change it.
They are quite unrelated, no need to violate coding style to match them.
Also packing and unpacking implementation unnecessary separated.
Maybe something like this and keep bit arithmetic in a single cpp file:
```
struct AsanAccessInfo {
uint8_t AccessSize;
bool CompileKernel;
bool IsWrite;
...
explicit AsanAccessInfo(int64_t packed);
int64_t Pack() const;
}
```
Also math a little bit simpler if 4bit field is the last
Comment at: llvm/lib/Target/X86/X86MCInstLower.cpp:1426
+ OutStreamer->emitInstruction(MCInstBuilder(X86::AND32ri8)
+ .addReg(X86::ECX)
+ .addReg(X86::ECX)
what is in ECX register here?
Comment at: llvm/lib/Target/X86/X86MCInstLower.cpp:1553-1555
+OutStreamer->emitSymbolAttribute(Sym, MCSA_ELF_TypeFunction);
+OutStreamer->emitSymbolAttribute(Sym, MCSA_Weak);
+OutStreamer->emitSymbolAttribute(Sym, MCSA_Hidden);
Tests do not check these attributes.
Comment at: llvm/lib/Target/X86/X86MCInstLower.cpp:1561-1564
+bool CompileKernel = (AccessInfo >> ASanAccessInfo::CompileKernelShift) &
1;
+int32_t AccessSizeIndex =
+(AccessInfo >> ASanAccessInfo::AccessSizeShift) & 0xf;
+bool IsWrite = (AccessInfo >> ASanAccessInfo::IsWriteShift) & 1;
as-is shifts are in the header, and masks are here, which is not nice.
Comment at: llvm/test/CodeGen/X86/asan-check-memaccess-add.ll:6
+define void @load1(i8* nocapture readonly %x) {
+; CHECK: callq __asan_check_load1_rn[[RN1:.*]]
+; CHECK: callq __asan_check_store1_rn[[RN1]]
should we also check how we load registers before callq?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D107850/new/
https://reviews.llvm.org/D107850
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
kstoimenov added a comment.
All tests are passing locally. Should be good to review now.
Comment at: llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h:150
+namespace AsanAccessInfo {
+
vitalybuka wrote:
> It's not how enums described here
> https://llvm.org/docs/CodingStandards.html#id43
> Also it's common to use enum class nowerdays.
>
>
> However this one does not need to be enum and just "constexpr size_t"
I wanted to be as close as possible to the HWASan style. Please let me know if
you want me to change it.
Comment at: llvm/test/CodeGen/X86/asan-check-memaccess-or.ll:47
+ %2 = bitcast i64* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 0,
+ i32 3, i32 3, i32 1)
vitalybuka wrote:
> Is this test out of date? Code has fewer arguments now.
Should be updated now.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D107850/new/
https://reviews.llvm.org/D107850
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
kstoimenov updated this revision to Diff 367882.
kstoimenov added a comment.
Upload after updating AddressSanitizer.cpp.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D107850/new/
https://reviews.llvm.org/D107850
Files:
llvm/include/llvm/IR/Intrinsics.td
llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h
llvm/lib/Target/X86/X86AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.h
llvm/lib/Target/X86/X86InstrCompiler.td
llvm/lib/Target/X86/X86MCInstLower.cpp
llvm/lib/Target/X86/X86RegisterInfo.td
llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
llvm/tools/llvm-exegesis/CMakeLists.txt
Index: llvm/tools/llvm-exegesis/CMakeLists.txt
===
--- llvm/tools/llvm-exegesis/CMakeLists.txt
+++ llvm/tools/llvm-exegesis/CMakeLists.txt
@@ -1,4 +1,5 @@
set(LLVM_LINK_COMPONENTS
+ Instrumentation
MC
MCParser
Support
Index: llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
@@ -0,0 +1,223 @@
+; RUN: llc < %s | FileCheck %s
+
+target triple = "x86_64-pc-win"
+
+define void @load1(i8* nocapture readonly %x) {
+; CHECK: callq __asan_check_load1_rn[[RN1:.*]]
+; CHECK: callq __asan_check_store1_rn[[RN1]]
+; CHECK-NEXT: retq
+ call void @llvm.asan.check.memaccess(i8* %x, i32 0)
+ call void @llvm.asan.check.memaccess(i8* %x, i32 32)
+ ret void
+}
+
+define void @load2(i16* nocapture readonly %x) {
+; CHECK: callq __asan_check_load2_rn[[RN2:.*]]
+; CHECK: callq __asan_check_store2_rn[[RN2]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i16* %x to i64
+ %2 = bitcast i16* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 2)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 34)
+ ret void
+}
+
+define void @load4(i32* nocapture readonly %x) {
+; CHECK: callq __asan_check_load4_rn[[RN4:.*]]
+; CHECK: callq __asan_check_store4_rn[[RN4]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i32* %x to i64
+ %2 = bitcast i32* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 4)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 36)
+ ret void
+}
+define void @load8(i64* nocapture readonly %x) {
+; CHECK: callq __asan_check_load8_rn[[RN8:.*]]
+; CHECK: callq __asan_check_store8_rn[[RN8]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i64* %x to i64
+ %2 = bitcast i64* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 6)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 38)
+ ret void
+}
+
+define void @load16(i128* nocapture readonly %x) {
+; CHECK: callq __asan_check_load16_rn[[RN16:.*]]
+; CHECK: callq __asan_check_store16_rn[[RN16]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i128* %x to i64
+ %2 = bitcast i128* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 8)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 40)
+ ret void
+}
+
+; CHECK: __asan_check_load1_rn[[RN1]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl [[RET]]
+; CHECK-NEXT: movq[[REG:.*]], %rdi
+; CHECK-NEXT: jmp __asan_report_load1
+
+; CHECK: __asan_check_load2_rn[[RN2]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: addl$1, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl [[RET]]
+; CHECK-NEXT: movq[[REG:.*]], %rdi
+; CHECK-NEXT: jmp __asan_report_load2
+
+; CHECK: __asan_check_load4_rn[[RN4]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb %r8b, %r8b
+; CHECK-
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
kstoimenov updated this revision to Diff 367876.
kstoimenov added a comment.
Herald added a subscriber: mgorny.
Moved back to using AccessInfo and fixed the tests.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D107850/new/
https://reviews.llvm.org/D107850
Files:
llvm/include/llvm/IR/Intrinsics.td
llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h
llvm/lib/Target/X86/X86AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.h
llvm/lib/Target/X86/X86InstrCompiler.td
llvm/lib/Target/X86/X86MCInstLower.cpp
llvm/lib/Target/X86/X86RegisterInfo.td
llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
llvm/tools/llvm-exegesis/CMakeLists.txt
Index: llvm/tools/llvm-exegesis/CMakeLists.txt
===
--- llvm/tools/llvm-exegesis/CMakeLists.txt
+++ llvm/tools/llvm-exegesis/CMakeLists.txt
@@ -1,4 +1,5 @@
set(LLVM_LINK_COMPONENTS
+ Instrumentation
MC
MCParser
Support
Index: llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
@@ -0,0 +1,223 @@
+; RUN: llc < %s | FileCheck %s
+
+target triple = "x86_64-pc-win"
+
+define void @load1(i8* nocapture readonly %x) {
+; CHECK: callq __asan_check_load1_rn[[RN1:.*]]
+; CHECK: callq __asan_check_store1_rn[[RN1]]
+; CHECK-NEXT: retq
+ call void @llvm.asan.check.memaccess(i8* %x, i32 0)
+ call void @llvm.asan.check.memaccess(i8* %x, i32 32)
+ ret void
+}
+
+define void @load2(i16* nocapture readonly %x) {
+; CHECK: callq __asan_check_load2_rn[[RN2:.*]]
+; CHECK: callq __asan_check_store2_rn[[RN2]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i16* %x to i64
+ %2 = bitcast i16* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 2)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 34)
+ ret void
+}
+
+define void @load4(i32* nocapture readonly %x) {
+; CHECK: callq __asan_check_load4_rn[[RN4:.*]]
+; CHECK: callq __asan_check_store4_rn[[RN4]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i32* %x to i64
+ %2 = bitcast i32* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 4)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 36)
+ ret void
+}
+define void @load8(i64* nocapture readonly %x) {
+; CHECK: callq __asan_check_load8_rn[[RN8:.*]]
+; CHECK: callq __asan_check_store8_rn[[RN8]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i64* %x to i64
+ %2 = bitcast i64* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 6)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 38)
+ ret void
+}
+
+define void @load16(i128* nocapture readonly %x) {
+; CHECK: callq __asan_check_load16_rn[[RN16:.*]]
+; CHECK: callq __asan_check_store16_rn[[RN16]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i128* %x to i64
+ %2 = bitcast i128* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i32 8)
+ call void @llvm.asan.check.memaccess(i8* %2, i32 40)
+ ret void
+}
+
+; CHECK: __asan_check_load1_rn[[RN1]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl [[RET]]
+; CHECK-NEXT: movq[[REG:.*]], %rdi
+; CHECK-NEXT: jmp __asan_report_load1
+
+; CHECK: __asan_check_load2_rn[[RN2]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $17592186044416, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: addl$1, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl [[RET]]
+; CHECK-NEXT: movq[[REG:.*]], %rdi
+; CHECK-NEXT: jmp __asan_report_load2
+
+; CHECK: __asan_check_load4_rn[[RN4]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $17592186044416, %r
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
vitalybuka added inline comments. Comment at: llvm/test/CodeGen/X86/asan-check-memaccess-or.ll:47 + %2 = bitcast i64* %x to i8* + call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 0, + i32 3, i32 3, i32 1) Is this test out of date? Code has fewer arguments now. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107850/new/ https://reviews.llvm.org/D107850 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
vitalybuka added inline comments.
Comment at: llvm/include/llvm/IR/Intrinsics.td:1640
+def int_asan_check_memaccess :
+ Intrinsic<[],[llvm_ptr_ty, llvm_i8_ty, llvm_i8_ty],
eugenis wrote:
> vitalybuka wrote:
> > pcc wrote:
> > > eugenis wrote:
> > > > vitalybuka wrote:
> > > > > kstoimenov wrote:
> > > > > > vitalybuka wrote:
> > > > > > > vitalybuka wrote:
> > > > > > > > PTAL at lvm.read_register.i32
> > > > > > > >
> > > > > > > > How about:
> > > > > > > >
> > > > > > > > llvm.asan.check.memaccess ->
> > > > > > > > lvm.asan.check_read
> > > > > > > > lvm.asan.check_write
> > > > > > > > lvm.asan.kernel.check_read
> > > > > > > > lvm.asan.kernel.check_write
> > > > > > > >
> > > > > > > > Even better
> > > > > > > > lvm.asan.check_read.{i8, i16, i32, ...}
> > > > > > > > lvm.asan.check_write.{i8, i16, i32, ...}
> > > > > > > > lvm.asan.kernel.check_read.{i8, i16, i32, ...}
> > > > > > > > lvm.asan.kernel.check_write.{i8, i16, i32, ...}
> > > > > > > >
> > > > > > > Looks like underscore is not used in intrinsic names, so
> > > > > > > essentially the same with dots.
> > > > > > Sounds good to me. I do the full expansion so there will be 20
> > > > > > intrinsics altogether. I will update the code and ping you when
> > > > > > done.
> > > > > @pcc @eugenis
> > > > > WDYT, I think later we can do the same for HWASAN?
> > > > I don't see what these multiple intrinsics give us that a single
> > > > memaccess one does not provide?
> > > >
> > > > As long as access type and similar arguments are immediates.
> > > >
> > > Agree with @eugenis - these sorts of intrinsic variants are typically
> > > used for distinguishing different pointer element types and we're in the
> > > process of getting rid of those anyway.
> > @pcc @eugenis Then do you prefer to encode is_write+size+kernel into
> > non-human unreadable AccessInfo, like hwasan, or separate 0/1 arguments.
> > I probably prefer AccessInfo, as they both unreadable, but the hwasan
> > version is shorter.
> don't have a strong opinion, but sometimes I wish that hwasan outlined
> function names were more readable. The magic number in the names takes effort
> to decode.
>
AccessInfo
Comment at: llvm/include/llvm/IR/Intrinsics.td:1640
+def int_asan_check_memaccess :
+ Intrinsic<[],[llvm_ptr_ty, llvm_i8_ty, llvm_i8_ty],
pcc wrote:
> kstoimenov wrote:
> > vitalybuka wrote:
> > > eugenis wrote:
> > > > vitalybuka wrote:
> > > > > pcc wrote:
> > > > > > eugenis wrote:
> > > > > > > vitalybuka wrote:
> > > > > > > > kstoimenov wrote:
> > > > > > > > > vitalybuka wrote:
> > > > > > > > > > vitalybuka wrote:
> > > > > > > > > > > PTAL at lvm.read_register.i32
> > > > > > > > > > >
> > > > > > > > > > > How about:
> > > > > > > > > > >
> > > > > > > > > > > llvm.asan.check.memaccess ->
> > > > > > > > > > > lvm.asan.check_read
> > > > > > > > > > > lvm.asan.check_write
> > > > > > > > > > > lvm.asan.kernel.check_read
> > > > > > > > > > > lvm.asan.kernel.check_write
> > > > > > > > > > >
> > > > > > > > > > > Even better
> > > > > > > > > > > lvm.asan.check_read.{i8, i16, i32, ...}
> > > > > > > > > > > lvm.asan.check_write.{i8, i16, i32, ...}
> > > > > > > > > > > lvm.asan.kernel.check_read.{i8, i16, i32, ...}
> > > > > > > > > > > lvm.asan.kernel.check_write.{i8, i16, i32, ...}
> > > > > > > > > > >
> > > > > > > > > > Looks like underscore is not used in intrinsic names, so
> > > > > > > > > > essentially the same with dots.
> > > > > > > > > Sounds good to me. I do the full expansion so there will be
> > > > > > > > > 20 intrinsics altogether. I will update the code and ping you
> > > > > > > > > when done.
> > > > > > > > @pcc @eugenis
> > > > > > > > WDYT, I think later we can do the same for HWASAN?
> > > > > > > I don't see what these multiple intrinsics give us that a single
> > > > > > > memaccess one does not provide?
> > > > > > >
> > > > > > > As long as access type and similar arguments are immediates.
> > > > > > >
> > > > > > Agree with @eugenis - these sorts of intrinsic variants are
> > > > > > typically used for distinguishing different pointer element types
> > > > > > and we're in the process of getting rid of those anyway.
> > > > > @pcc @eugenis Then do you prefer to encode is_write+size+kernel into
> > > > > non-human unreadable AccessInfo, like hwasan, or separate 0/1
> > > > > arguments.
> > > > > I probably prefer AccessInfo, as they both unreadable, but the hwasan
> > > > > version is shorter.
> > > > don't have a strong opinion, but sometimes I wish that hwasan outlined
> > > > function names were more readable. The magic number in the names takes
> > > > effort to decode.
> > > >
> > > AccessInfo
> > I think I am gonna go with int_asan_check(?_kernel)_(load|store) and pass
> > the size as parameter. What do you think?
> You mean in a register? I think that could mean more register pressure ->
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
pcc added inline comments.
Comment at: llvm/include/llvm/IR/Intrinsics.td:1640
+def int_asan_check_memaccess :
+ Intrinsic<[],[llvm_ptr_ty, llvm_i8_ty, llvm_i8_ty],
kstoimenov wrote:
> eugenis wrote:
> > vitalybuka wrote:
> > > pcc wrote:
> > > > eugenis wrote:
> > > > > vitalybuka wrote:
> > > > > > kstoimenov wrote:
> > > > > > > vitalybuka wrote:
> > > > > > > > vitalybuka wrote:
> > > > > > > > > PTAL at lvm.read_register.i32
> > > > > > > > >
> > > > > > > > > How about:
> > > > > > > > >
> > > > > > > > > llvm.asan.check.memaccess ->
> > > > > > > > > lvm.asan.check_read
> > > > > > > > > lvm.asan.check_write
> > > > > > > > > lvm.asan.kernel.check_read
> > > > > > > > > lvm.asan.kernel.check_write
> > > > > > > > >
> > > > > > > > > Even better
> > > > > > > > > lvm.asan.check_read.{i8, i16, i32, ...}
> > > > > > > > > lvm.asan.check_write.{i8, i16, i32, ...}
> > > > > > > > > lvm.asan.kernel.check_read.{i8, i16, i32, ...}
> > > > > > > > > lvm.asan.kernel.check_write.{i8, i16, i32, ...}
> > > > > > > > >
> > > > > > > > Looks like underscore is not used in intrinsic names, so
> > > > > > > > essentially the same with dots.
> > > > > > > Sounds good to me. I do the full expansion so there will be 20
> > > > > > > intrinsics altogether. I will update the code and ping you when
> > > > > > > done.
> > > > > > @pcc @eugenis
> > > > > > WDYT, I think later we can do the same for HWASAN?
> > > > > I don't see what these multiple intrinsics give us that a single
> > > > > memaccess one does not provide?
> > > > >
> > > > > As long as access type and similar arguments are immediates.
> > > > >
> > > > Agree with @eugenis - these sorts of intrinsic variants are typically
> > > > used for distinguishing different pointer element types and we're in
> > > > the process of getting rid of those anyway.
> > > @pcc @eugenis Then do you prefer to encode is_write+size+kernel into
> > > non-human unreadable AccessInfo, like hwasan, or separate 0/1 arguments.
> > > I probably prefer AccessInfo, as they both unreadable, but the hwasan
> > > version is shorter.
> > don't have a strong opinion, but sometimes I wish that hwasan outlined
> > function names were more readable. The magic number in the names takes
> > effort to decode.
> >
> I think I am gonna go with int_asan_check(?_kernel)_(load|store) and pass the
> size as parameter. What do you think?
You mean in a register? I think that could mean more register pressure ->
higher code size.
The magic numbers are unfortunate but they aren't that hard to decode (maybe we
should be printing them as hex to make it a bit easier). I suppose we could
pretty print the access info into the symbol name but only a few people will be
looking at these so I'm not sure it's worth the effort.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D107850/new/
https://reviews.llvm.org/D107850
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
kstoimenov marked an inline comment as done.
kstoimenov added inline comments.
Comment at: llvm/include/llvm/IR/Intrinsics.td:1640
+def int_asan_check_memaccess :
+ Intrinsic<[],[llvm_ptr_ty, llvm_i8_ty, llvm_i8_ty],
eugenis wrote:
> vitalybuka wrote:
> > pcc wrote:
> > > eugenis wrote:
> > > > vitalybuka wrote:
> > > > > kstoimenov wrote:
> > > > > > vitalybuka wrote:
> > > > > > > vitalybuka wrote:
> > > > > > > > PTAL at lvm.read_register.i32
> > > > > > > >
> > > > > > > > How about:
> > > > > > > >
> > > > > > > > llvm.asan.check.memaccess ->
> > > > > > > > lvm.asan.check_read
> > > > > > > > lvm.asan.check_write
> > > > > > > > lvm.asan.kernel.check_read
> > > > > > > > lvm.asan.kernel.check_write
> > > > > > > >
> > > > > > > > Even better
> > > > > > > > lvm.asan.check_read.{i8, i16, i32, ...}
> > > > > > > > lvm.asan.check_write.{i8, i16, i32, ...}
> > > > > > > > lvm.asan.kernel.check_read.{i8, i16, i32, ...}
> > > > > > > > lvm.asan.kernel.check_write.{i8, i16, i32, ...}
> > > > > > > >
> > > > > > > Looks like underscore is not used in intrinsic names, so
> > > > > > > essentially the same with dots.
> > > > > > Sounds good to me. I do the full expansion so there will be 20
> > > > > > intrinsics altogether. I will update the code and ping you when
> > > > > > done.
> > > > > @pcc @eugenis
> > > > > WDYT, I think later we can do the same for HWASAN?
> > > > I don't see what these multiple intrinsics give us that a single
> > > > memaccess one does not provide?
> > > >
> > > > As long as access type and similar arguments are immediates.
> > > >
> > > Agree with @eugenis - these sorts of intrinsic variants are typically
> > > used for distinguishing different pointer element types and we're in the
> > > process of getting rid of those anyway.
> > @pcc @eugenis Then do you prefer to encode is_write+size+kernel into
> > non-human unreadable AccessInfo, like hwasan, or separate 0/1 arguments.
> > I probably prefer AccessInfo, as they both unreadable, but the hwasan
> > version is shorter.
> don't have a strong opinion, but sometimes I wish that hwasan outlined
> function names were more readable. The magic number in the names takes effort
> to decode.
>
I think I am gonna go with int_asan_check(?_kernel)_(load|store) and pass the
size as parameter. What do you think?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D107850/new/
https://reviews.llvm.org/D107850
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
kstoimenov updated this revision to Diff 367601.
kstoimenov retitled this revision from "[asan] Implemented intrinsic for
the custom calling convention similar used by HWASan for X86." to "[asan]
Implemented intrinsic for the custom calling convention similar used by HWASan
for X86.".
kstoimenov added a comment.
Removed IntrInaccessibleMemOnly.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D107850/new/
https://reviews.llvm.org/D107850
Files:
llvm/include/llvm/IR/Intrinsics.td
llvm/lib/Target/X86/X86AsmPrinter.cpp
llvm/lib/Target/X86/X86AsmPrinter.h
llvm/lib/Target/X86/X86InstrCompiler.td
llvm/lib/Target/X86/X86MCInstLower.cpp
llvm/lib/Target/X86/X86RegisterInfo.td
llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
Index: llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
@@ -0,0 +1,234 @@
+; RUN: llc < %s | FileCheck %s
+
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @load1(i8* nocapture readonly %x) {
+; CHECK: callq __asan_check_load1_rn[[RN1:.*]]
+; CHECK: callq __asan_check_store1_rn[[RN1]]
+; CHECK-NEXT: retq
+ call void @llvm.asan.check.memaccess(i8* %x, i64 2147450880, i32 0,
+ i32 0, i32 3, i32 1)
+ call void @llvm.asan.check.memaccess(i8* %x, i64 2147450880, i32 1,
+ i32 0, i32 3, i32 1)
+ ret void
+}
+
+define void @load2(i16* nocapture readonly %x) {
+; CHECK: callq __asan_check_load2_rn[[RN2:.*]]
+; CHECK: callq __asan_check_store2_rn[[RN2]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i16* %x to i64
+ %2 = bitcast i16* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 0,
+ i32 1, i32 3, i32 1)
+ call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 1,
+ i32 1, i32 3, i32 1)
+ ret void
+}
+
+define void @load4(i32* nocapture readonly %x) {
+; CHECK: callq __asan_check_load4_rn[[RN4:.*]]
+; CHECK: callq __asan_check_store4_rn[[RN4]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i32* %x to i64
+ %2 = bitcast i32* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 0,
+ i32 2, i32 3, i32 1)
+ call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 1,
+ i32 2, i32 3, i32 1)
+ ret void
+}
+define void @load8(i64* nocapture readonly %x) {
+; CHECK: callq __asan_check_load8_rn[[RN8:.*]]
+; CHECK: callq __asan_check_store8_rn[[RN8]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i64* %x to i64
+ %2 = bitcast i64* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 0,
+ i32 3, i32 3, i32 1)
+ call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 1,
+ i32 3, i32 3, i32 1)
+ ret void
+}
+
+define void @load16(i128* nocapture readonly %x) {
+; CHECK: callq __asan_check_load16_rn[[RN16:.*]]
+; CHECK: callq __asan_check_store16_rn[[RN16]]
+; CHECK-NEXT: retq
+ %1 = ptrtoint i128* %x to i64
+ %2 = bitcast i128* %x to i8*
+ call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 0,
+ i32 4, i32 3, i32 1)
+ call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 1,
+ i32 4, i32 3, i32 1)
+ ret void
+}
+
+; CHECK: __asan_check_load1_rn[[RN1]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $2147450880, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl [[RET]]
+; CHECK-NEXT: movq[[REG:.*]], %rdi
+; CHECK-NEXT: jmp __asan_report_load1
+
+; CHECK: __asan_check_load2_rn[[RN2]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $2147450880, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq %rcx
+; CHECK-NEXT: mov
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
eugenis added inline comments.
Comment at: llvm/include/llvm/IR/Intrinsics.td:1640
+def int_asan_check_memaccess :
+ Intrinsic<[],[llvm_ptr_ty, llvm_i8_ty, llvm_i8_ty],
vitalybuka wrote:
> pcc wrote:
> > eugenis wrote:
> > > vitalybuka wrote:
> > > > kstoimenov wrote:
> > > > > vitalybuka wrote:
> > > > > > vitalybuka wrote:
> > > > > > > PTAL at lvm.read_register.i32
> > > > > > >
> > > > > > > How about:
> > > > > > >
> > > > > > > llvm.asan.check.memaccess ->
> > > > > > > lvm.asan.check_read
> > > > > > > lvm.asan.check_write
> > > > > > > lvm.asan.kernel.check_read
> > > > > > > lvm.asan.kernel.check_write
> > > > > > >
> > > > > > > Even better
> > > > > > > lvm.asan.check_read.{i8, i16, i32, ...}
> > > > > > > lvm.asan.check_write.{i8, i16, i32, ...}
> > > > > > > lvm.asan.kernel.check_read.{i8, i16, i32, ...}
> > > > > > > lvm.asan.kernel.check_write.{i8, i16, i32, ...}
> > > > > > >
> > > > > > Looks like underscore is not used in intrinsic names, so
> > > > > > essentially the same with dots.
> > > > > Sounds good to me. I do the full expansion so there will be 20
> > > > > intrinsics altogether. I will update the code and ping you when done.
> > > > @pcc @eugenis
> > > > WDYT, I think later we can do the same for HWASAN?
> > > I don't see what these multiple intrinsics give us that a single
> > > memaccess one does not provide?
> > >
> > > As long as access type and similar arguments are immediates.
> > >
> > Agree with @eugenis - these sorts of intrinsic variants are typically used
> > for distinguishing different pointer element types and we're in the process
> > of getting rid of those anyway.
> @pcc @eugenis Then do you prefer to encode is_write+size+kernel into
> non-human unreadable AccessInfo, like hwasan, or separate 0/1 arguments.
> I probably prefer AccessInfo, as they both unreadable, but the hwasan version
> is shorter.
don't have a strong opinion, but sometimes I wish that hwasan outlined function
names were more readable. The magic number in the names takes effort to decode.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D107850/new/
https://reviews.llvm.org/D107850
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
vitalybuka added inline comments.
Comment at: llvm/include/llvm/IR/Intrinsics.td:1640
+def int_asan_check_memaccess :
+ Intrinsic<[],[llvm_ptr_ty, llvm_i8_ty, llvm_i8_ty],
pcc wrote:
> eugenis wrote:
> > vitalybuka wrote:
> > > kstoimenov wrote:
> > > > vitalybuka wrote:
> > > > > vitalybuka wrote:
> > > > > > PTAL at lvm.read_register.i32
> > > > > >
> > > > > > How about:
> > > > > >
> > > > > > llvm.asan.check.memaccess ->
> > > > > > lvm.asan.check_read
> > > > > > lvm.asan.check_write
> > > > > > lvm.asan.kernel.check_read
> > > > > > lvm.asan.kernel.check_write
> > > > > >
> > > > > > Even better
> > > > > > lvm.asan.check_read.{i8, i16, i32, ...}
> > > > > > lvm.asan.check_write.{i8, i16, i32, ...}
> > > > > > lvm.asan.kernel.check_read.{i8, i16, i32, ...}
> > > > > > lvm.asan.kernel.check_write.{i8, i16, i32, ...}
> > > > > >
> > > > > Looks like underscore is not used in intrinsic names, so essentially
> > > > > the same with dots.
> > > > Sounds good to me. I do the full expansion so there will be 20
> > > > intrinsics altogether. I will update the code and ping you when done.
> > > @pcc @eugenis
> > > WDYT, I think later we can do the same for HWASAN?
> > I don't see what these multiple intrinsics give us that a single memaccess
> > one does not provide?
> >
> > As long as access type and similar arguments are immediates.
> >
> Agree with @eugenis - these sorts of intrinsic variants are typically used
> for distinguishing different pointer element types and we're in the process
> of getting rid of those anyway.
@pcc @eugenis Then do you prefer to encode is_write+size+kernel into non-human
unreadable AccessInfo, like hwasan, or separate 0/1 arguments.
I probably prefer AccessInfo, as they both unreadable, but the hwasan version
is shorter.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D107850/new/
https://reviews.llvm.org/D107850
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D107850: [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86.
pcc added inline comments.
Comment at: llvm/include/llvm/IR/Intrinsics.td:1640
+def int_asan_check_memaccess :
+ Intrinsic<[],[llvm_ptr_ty, llvm_i8_ty, llvm_i8_ty],
eugenis wrote:
> vitalybuka wrote:
> > kstoimenov wrote:
> > > vitalybuka wrote:
> > > > vitalybuka wrote:
> > > > > PTAL at lvm.read_register.i32
> > > > >
> > > > > How about:
> > > > >
> > > > > llvm.asan.check.memaccess ->
> > > > > lvm.asan.check_read
> > > > > lvm.asan.check_write
> > > > > lvm.asan.kernel.check_read
> > > > > lvm.asan.kernel.check_write
> > > > >
> > > > > Even better
> > > > > lvm.asan.check_read.{i8, i16, i32, ...}
> > > > > lvm.asan.check_write.{i8, i16, i32, ...}
> > > > > lvm.asan.kernel.check_read.{i8, i16, i32, ...}
> > > > > lvm.asan.kernel.check_write.{i8, i16, i32, ...}
> > > > >
> > > > Looks like underscore is not used in intrinsic names, so essentially
> > > > the same with dots.
> > > Sounds good to me. I do the full expansion so there will be 20 intrinsics
> > > altogether. I will update the code and ping you when done.
> > @pcc @eugenis
> > WDYT, I think later we can do the same for HWASAN?
> I don't see what these multiple intrinsics give us that a single memaccess
> one does not provide?
>
> As long as access type and similar arguments are immediates.
>
Agree with @eugenis - these sorts of intrinsic variants are typically used for
distinguishing different pointer element types and we're in the process of
getting rid of those anyway.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D107850/new/
https://reviews.llvm.org/D107850
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
