[PATCH] D153370: [RISCV] Add support for custom instructions for Sifive S76.

2023-06-26 Thread Craig Topper via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rG4c37d30e22ae: [RISCV] Add support for custom instructions 
for Sifive S76. (authored by garvitgupta08, committed by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153370/new/

https://reviews.llvm.org/D153370

Files:
  clang/test/Driver/riscv-cpus.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
  llvm/lib/Target/RISCV/RISCVProcessors.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/xsfcie-invalid.s
  llvm/test/MC/RISCV/xsfcie-valid.s

Index: llvm/test/MC/RISCV/xsfcie-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/xsfcie-valid.s
@@ -0,0 +1,42 @@
+# SCIE - SiFive Custom Instructions Extension.
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+xsfcie -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xsfcie -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xsfcie < %s \
+# RUN: | llvm-objdump --mattr=+xsfcie -M no-aliases -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xsfcie < %s \
+# RUN: | llvm-objdump --mattr=+xsfcie -M no-aliases -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mcpu=sifive-s76 -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mcpu=sifive-s76 < %s \
+# RUN: | llvm-objdump --mcpu=sifive-s76 -M no-aliases -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+
+# CHECK-INST: cflush.d.l1 zero
+# CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc]
+# CHECK-INST: cflush.d.l1 zero
+# CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc]
+cflush.d.l1 x0
+cflush.d.l1
+
+# CHECK-INST: cflush.d.l1 t2
+# CHECK-ENC: encoding: [0x73,0x80,0x03,0xfc]
+cflush.d.l1 x7
+
+# CHECK-INST: cdiscard.d.l1   zero
+# CHECK-ENC: encoding: [0x73,0x00,0x20,0xfc]
+# CHECK-INST: cdiscard.d.l1 zero
+# CHECK-ENC: encoding: [0x73,0x00,0x20,0xfc]
+cdiscard.d.l1 x0
+cdiscard.d.l1
+
+# CHECK-INST: cdiscard.d.l1   t2
+# CHECK-ENC: encoding: [0x73,0x80,0x23,0xfc]
+cdiscard.d.l1 x7
+
+# CHECK-INST: cease
+# CHECK-ENC: encoding: [0x73,0x00,0x50,0x30]
+cease
Index: llvm/test/MC/RISCV/xsfcie-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/xsfcie-invalid.s
@@ -0,0 +1,25 @@
+# SCIE - SiFive Custom Instructions Extension.
+# RUN: not llvm-mc -triple riscv32 -mattr=-xsfcie < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=-xsfcie < %s 2>&1 | FileCheck %s
+
+cflush.d.l1 0x10 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+
+cdiscard.d.l1 0x10 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+
+cflush.d.l1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
+
+cdiscard.d.l1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
+
+cflush.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
+
+cflush.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
+
+cdiscard.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
+
+cdiscard.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
+
+cease x1 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
+
+cease 0x10 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
+
+cease # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -278,3 +278,6 @@
 
 .attribute arch, "rv32i_zvfbfwma0p6"
 # CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfwma0p6_zvl32b1p0"
+
+.attribute arch, "rv64i_xsfcie"
+# CHECK: attribute  5, "rv64i2p1_xsfcie1p0"
Index: llvm/lib/Target/RISCV/RISCVProcessors.td
===
--- llvm/lib/Target/RISCV/RISCVProcessors.td
+++ llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -142,7 +142

[PATCH] D153370: [RISCV] Add support for custom instructions for Sifive S76.

2023-06-26 Thread garvit gupta via Phabricator via cfe-commits 
garvitgupta08 added a comment.

In D153370#4447824 , @craig.topper 
wrote:

> In D153370#4447817 , @garvitgupta08 
> wrote:
>
>> Addressed the changes. I do not have commit access, could you please commit 
>> this differential on my behalf? Thanks.
>
> Yes. Can you provide the name and email address for the git log.

Name - Garvit Gupta
Email - quic_garvg...@quicinc.com


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[PATCH] D153370: [RISCV] Add support for custom instructions for Sifive S76.

2023-06-26 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added a comment.

In D153370#4447817 , @garvitgupta08 
wrote:

> Addressed the changes. I do not have commit access, could you please commit 
> this differential on my behalf? Thanks.

Yes. Can you provide the name and email address for the git log.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D153370: [RISCV] Add support for custom instructions for Sifive S76.

2023-06-26 Thread garvit gupta via Phabricator via cfe-commits 
garvitgupta08 updated this revision to Diff 534437.
garvitgupta08 added a comment.

Addressed the changes. I do not have commit access, could you please commit 
this differential on my behalf? Thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153370/new/

https://reviews.llvm.org/D153370

Files:
  clang/test/Driver/riscv-cpus.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
  llvm/lib/Target/RISCV/RISCVProcessors.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/xsfcie-invalid.s
  llvm/test/MC/RISCV/xsfcie-valid.s

Index: llvm/test/MC/RISCV/xsfcie-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/xsfcie-valid.s
@@ -0,0 +1,42 @@
+# SCIE - SiFive Custom Instructions Extension.
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+xsfcie -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xsfcie -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xsfcie < %s \
+# RUN: | llvm-objdump --mattr=+xsfcie -M no-aliases -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xsfcie < %s \
+# RUN: | llvm-objdump --mattr=+xsfcie -M no-aliases -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mcpu=sifive-s76 -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mcpu=sifive-s76 < %s \
+# RUN: | llvm-objdump --mcpu=sifive-s76 -M no-aliases -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+
+# CHECK-INST: cflush.d.l1 zero
+# CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc]
+# CHECK-INST: cflush.d.l1 zero
+# CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc]
+cflush.d.l1 x0
+cflush.d.l1
+
+# CHECK-INST: cflush.d.l1 t2
+# CHECK-ENC: encoding: [0x73,0x80,0x03,0xfc]
+cflush.d.l1 x7
+
+# CHECK-INST: cdiscard.d.l1   zero
+# CHECK-ENC: encoding: [0x73,0x00,0x20,0xfc]
+# CHECK-INST: cdiscard.d.l1 zero
+# CHECK-ENC: encoding: [0x73,0x00,0x20,0xfc]
+cdiscard.d.l1 x0
+cdiscard.d.l1
+
+# CHECK-INST: cdiscard.d.l1   t2
+# CHECK-ENC: encoding: [0x73,0x80,0x23,0xfc]
+cdiscard.d.l1 x7
+
+# CHECK-INST: cease
+# CHECK-ENC: encoding: [0x73,0x00,0x50,0x30]
+cease
Index: llvm/test/MC/RISCV/xsfcie-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/xsfcie-invalid.s
@@ -0,0 +1,25 @@
+# SCIE - SiFive Custom Instructions Extension.
+# RUN: not llvm-mc -triple riscv32 -mattr=-xsfcie < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=-xsfcie < %s 2>&1 | FileCheck %s
+
+cflush.d.l1 0x10 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+
+cdiscard.d.l1 0x10 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+
+cflush.d.l1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
+
+cdiscard.d.l1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
+
+cflush.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
+
+cflush.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
+
+cdiscard.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
+
+cdiscard.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
+
+cease x1 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
+
+cease 0x10 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
+
+cease # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -278,3 +278,6 @@
 
 .attribute arch, "rv32i_zvfbfwma0p6"
 # CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfwma0p6_zvl32b1p0"
+
+.attribute arch, "rv64i_xsfcie"
+# CHECK: attribute  5, "rv64i2p1_xsfcie1p0"
Index: llvm/lib/Target/RISCV/RISCVProcessors.td
===
--- llvm/lib/Target/RISCV/RISCVProcessors.td
+++ llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -142,7 +142,9 @@

[PATCH] D153370: [RISCV] Add support for custom instructions for Sifive S76.

2023-06-23 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper accepted this revision.
craig.topper added inline comments.
This revision is now accepted and ready to land.



Comment at: llvm/docs/ReleaseNotes.rst:209
   disassembler/assembler.
+* Added support for the vendor-defined Xsfcie (SiFive SCIE) extension
+  disassembler/assembler.

SCIE->CIE since the S already stands for SiFive.



Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:562
+TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcie, DecoderTableXSfcie32,
+  "SCIE custom opcode table");
 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,

SCIE -> SiFive CIE


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[PATCH] D153370: [RISCV] Add support for custom instructions for Sifive S76.

2023-06-23 Thread garvit gupta via Phabricator via cfe-commits 
garvitgupta08 updated this revision to Diff 534018.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/test/Driver/riscv-cpus.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
  llvm/lib/Target/RISCV/RISCVProcessors.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/xsfcie-invalid.s
  llvm/test/MC/RISCV/xsfcie-valid.s

Index: llvm/test/MC/RISCV/xsfcie-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/xsfcie-valid.s
@@ -0,0 +1,42 @@
+# SCIE - SiFive Custom Instructions Extension.
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+xsfcie -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xsfcie -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xsfcie < %s \
+# RUN: | llvm-objdump --mattr=+xsfcie -M no-aliases -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xsfcie < %s \
+# RUN: | llvm-objdump --mattr=+xsfcie -M no-aliases -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mcpu=sifive-s76 -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mcpu=sifive-s76 < %s \
+# RUN: | llvm-objdump --mcpu=sifive-s76 -M no-aliases -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+
+# CHECK-INST: cflush.d.l1 zero
+# CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc]
+# CHECK-INST: cflush.d.l1 zero
+# CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc]
+cflush.d.l1 x0
+cflush.d.l1
+
+# CHECK-INST: cflush.d.l1 t2
+# CHECK-ENC: encoding: [0x73,0x80,0x03,0xfc]
+cflush.d.l1 x7
+
+# CHECK-INST: cdiscard.d.l1   zero
+# CHECK-ENC: encoding: [0x73,0x00,0x20,0xfc]
+# CHECK-INST: cdiscard.d.l1 zero
+# CHECK-ENC: encoding: [0x73,0x00,0x20,0xfc]
+cdiscard.d.l1 x0
+cdiscard.d.l1
+
+# CHECK-INST: cdiscard.d.l1   t2
+# CHECK-ENC: encoding: [0x73,0x80,0x23,0xfc]
+cdiscard.d.l1 x7
+
+# CHECK-INST: cease
+# CHECK-ENC: encoding: [0x73,0x00,0x50,0x30]
+cease
Index: llvm/test/MC/RISCV/xsfcie-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/xsfcie-invalid.s
@@ -0,0 +1,25 @@
+# SCIE - SiFive Custom Instructions Extension.
+# RUN: not llvm-mc -triple riscv32 -mattr=-xsfcie < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=-xsfcie < %s 2>&1 | FileCheck %s
+
+cflush.d.l1 0x10 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+
+cdiscard.d.l1 0x10 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+
+cflush.d.l1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
+
+cdiscard.d.l1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
+
+cflush.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
+
+cflush.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
+
+cdiscard.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
+
+cdiscard.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
+
+cease x1 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
+
+cease 0x10 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
+
+cease # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE.)
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -278,3 +278,6 @@
 
 .attribute arch, "rv32i_zvfbfwma0p6"
 # CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfwma0p6_zvl32b1p0"
+
+.attribute arch, "rv64i_xsfcie"
+# CHECK: attribute  5, "rv64i2p1_xsfcie1p0"
Index: llvm/lib/Target/RISCV/RISCVProcessors.td
===
--- llvm/lib/Target/RISCV/RISCVProcessors.td
+++ llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -142,7 +142,9 @@
   FeatureStdExtA,
   FeatureStdExtF,
   FeatureStdExtD,
-

[PATCH] D153370: [RISCV] Add support for custom instructions for Sifive S76.

2023-06-22 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added inline comments.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:123
 {"xsfvcp", RISCVExtensionVersion{1, 0}},
+{"xsfcie", RISCVExtensionVersion{1, 0}},
 {"xtheadba", RISCVExtensionVersion{1, 0}},

Alphabetize.



Comment at: llvm/lib/Target/RISCV/RISCVFeatures.td:757
+: SubtargetFeature<"xsfcie", "HasVendorXSfcie", "true",
+   "'XSfcie' (SiFive Custom Instruction Extension SCIE for 
S76.)">;
+def HasVendorXSfcie : Predicate<"Subtarget->hasVendorXSfcie()">,

Drop "for S76"


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[PATCH] D153370: [RISCV] Add support for custom instructions for Sifive S76.

2023-06-22 Thread garvit gupta via Phabricator via cfe-commits 
garvitgupta08 updated this revision to Diff 533668.
garvitgupta08 added a comment.

Addressed the comments


Repository:
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Files:
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
  llvm/lib/Target/RISCV/RISCVProcessors.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/xsfcie-invalid.s
  llvm/test/MC/RISCV/xsfcie-valid.s

Index: llvm/test/MC/RISCV/xsfcie-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/xsfcie-valid.s
@@ -0,0 +1,42 @@
+# SCIE - SiFive S76 Custom Instructions and CSRs.
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+xsfcie -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xsfcie -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xsfcie < %s \
+# RUN: | llvm-objdump --mattr=+xsfcie -M no-aliases -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xsfcie < %s \
+# RUN: | llvm-objdump --mattr=+xsfcie -M no-aliases -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mcpu=sifive-s76 -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mcpu=sifive-s76 < %s \
+# RUN: | llvm-objdump --mcpu=sifive-s76 -M no-aliases -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+
+# CHECK-INST: cflush.d.l1 zero
+# CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc]
+# CHECK-INST: cflush.d.l1 zero
+# CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc]
+cflush.d.l1 x0
+cflush.d.l1
+
+# CHECK-INST: cflush.d.l1 t2
+# CHECK-ENC: encoding: [0x73,0x80,0x03,0xfc]
+cflush.d.l1 x7
+
+# CHECK-INST: cdiscard.d.l1   zero
+# CHECK-ENC: encoding: [0x73,0x00,0x20,0xfc]
+# CHECK-INST: cdiscard.d.l1 zero
+# CHECK-ENC: encoding: [0x73,0x00,0x20,0xfc]
+cdiscard.d.l1 x0
+cdiscard.d.l1
+
+# CHECK-INST: cdiscard.d.l1   t2
+# CHECK-ENC: encoding: [0x73,0x80,0x23,0xfc]
+cdiscard.d.l1 x7
+
+# CHECK-INST: cease
+# CHECK-ENC: encoding: [0x73,0x00,0x50,0x30]
+cease
Index: llvm/test/MC/RISCV/xsfcie-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/xsfcie-invalid.s
@@ -0,0 +1,25 @@
+# SCIE - SiFive S76 Custom Instructions and CSRs.
+# RUN: not llvm-mc -triple riscv32 -mattr=-xsfcie < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=-xsfcie < %s 2>&1 | FileCheck %s
+
+cflush.d.l1 0x10 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+
+cdiscard.d.l1 0x10 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+
+cflush.d.l1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE for S76.)
+
+cdiscard.d.l1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE for S76.)
+
+cflush.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE for S76.)
+
+cflush.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE for S76.)
+
+cdiscard.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE for S76.)
+
+cdiscard.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE for S76.)
+
+cease x1 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
+
+cease 0x10 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
+
+cease # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SCIE for S76.)
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -278,3 +278,6 @@
 
 .attribute arch, "rv32i_zvfbfwma0p6"
 # CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfwma0p6_zvl32b1p0"
+
+.attribute arch, "rv64i_xsfcie"
+# CHECK: attribute  5, "rv64i2p1_xsfcie1p0"
Index: llvm/lib/Target/RISCV/RISCVProcessors.td
===
--- llvm/lib/Target/RISCV/RISCVProcessors.td
+++ llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -142,7 +142,9 @@
   FeatureStdExtA,

[PATCH] D153370: [RISCV] Add support for custom instructions for Sifive S76.

2023-06-21 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added inline comments.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:135
 {"xventanacondops", RISCVExtensionVersion{1, 0}},
+{"xsfcie", RISCVExtensionVersion{1, 0}},
 };

Put this with xsfvcp



Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:564
   "CORE-V Bit Manipulation custom opcode table");
+TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcie, DecoderTableXSfcie32,
+  "SiFive custom instruction opcode table");

Keep SiFive extensions together.



Comment at: llvm/lib/Target/RISCV/RISCVFeatures.td:763
 
+def FeatureVendorXSfcie
+: SubtargetFeature<"xsfcie", "HasVendorXSfcie", "true",

Keep SiFive extensions together



Comment at: llvm/lib/Target/RISCV/RISCVFeatures.td:765
+: SubtargetFeature<"xsfcie", "HasVendorXSfcie", "true",
+   "'XSfcie' (SiFive Custom Instruction Extension SFCIE 
for S76.)">;
+def HasVendorXSfcie : Predicate<"Subtarget->hasVendorXSfcie()">,

I believe the SiFive documentation uses SCIE not SFCIE?



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td:508
+
+let Predicates = [IsRV64, HasVendorXSfcie] in {
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0, DecoderNamespace = "XSfcie" 
in {

I don't think these are restricted to RV64. They're in the E76 core complex 
manual too.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td:510
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0, DecoderNamespace = "XSfcie" 
in {
+def Sfv_CFLUSH_D_L1 : RVInstI<0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1), 
"cflush.d.l1","$rs1">,  Sched<[]> {
+  let rd = 0;

Don't exceed 80 columns



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td:510
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0, DecoderNamespace = "XSfcie" 
in {
+def Sfv_CFLUSH_D_L1 : RVInstI<0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1), 
"cflush.d.l1","$rs1">,  Sched<[]> {
+  let rd = 0;

craig.topper wrote:
> Don't exceed 80 columns
Use SF_ instead of Sfv_


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153370/new/

https://reviews.llvm.org/D153370

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[PATCH] D153370: [RISCV] Add support for custom instructions for Sifive S76.

2023-06-20 Thread garvit gupta via Phabricator via cfe-commits 
garvitgupta08 created this revision.
garvitgupta08 added reviewers: asb, apazos, jrtc27.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
luismarques, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, 
the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, 
kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya, 
arichardson.
Herald added a project: All.
garvitgupta08 requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, wangpc, eopXD, MaskRay.
Herald added projects: clang, LLVM.

Support for below instruction is added

1. CFLUSH.D.L1 
2. CDISCARD.D.L1 
3. CEASE

Additionally, Zihintpause extension is added to sifive s76 for pause
instruction.

Spec - 
https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153370

Files:
  clang/test/Driver/riscv-cpus.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
  llvm/lib/Target/RISCV/RISCVProcessors.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/xsfcie-invalid.s
  llvm/test/MC/RISCV/xsfcie-valid.s

Index: llvm/test/MC/RISCV/xsfcie-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/xsfcie-valid.s
@@ -0,0 +1,38 @@
+# SFCIE - SiFive S76 Custom Instructions and CSRs.
+# RUN: llvm-mc %s -triple=riscv64 -mcpu=sifive-s76 -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xsfcie -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mcpu=sifive-s76 < %s \
+# RUN: | llvm-objdump --mcpu=sifive-s76 -M no-aliases -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xsfcie < %s \
+# RUN: | llvm-objdump --mattr=+xsfcie -M no-aliases -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+
+# CHECK-INST: cflush.d.l1 zero
+# CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc]
+# CHECK-INST: cflush.d.l1 zero
+# CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc]
+cflush.d.l1 x0
+cflush.d.l1
+
+# CHECK-INST: cflush.d.l1 t2
+# CHECK-ENC: encoding: [0x73,0x80,0x03,0xfc]
+cflush.d.l1 x7
+
+# CHECK-INST: cdiscard.d.l1   zero
+# CHECK-ENC: encoding: [0x73,0x00,0x20,0xfc]
+# CHECK-INST: cdiscard.d.l1 zero
+# CHECK-ENC: encoding: [0x73,0x00,0x20,0xfc]
+cdiscard.d.l1 x0
+cdiscard.d.l1
+
+# CHECK-INST: cdiscard.d.l1   t2
+# CHECK-ENC: encoding: [0x73,0x80,0x23,0xfc]
+cdiscard.d.l1 x7
+
+# CHECK-INST: cease
+# CHECK-ENC: encoding: [0x73,0x00,0x50,0x30]
+cease
+
Index: llvm/test/MC/RISCV/xsfcie-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/xsfcie-invalid.s
@@ -0,0 +1,24 @@
+# SFCIE - SiFive S76 Custom Instructions and CSRs.
+# RUN: not llvm-mc -triple riscv64 -mattr=-xsfcie < %s 2>&1 | FileCheck %s
+
+cflush.d.l1 0x10 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+
+cdiscard.d.l1 0x10 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+
+cflush.d.l1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SFCIE for S76.)
+
+cdiscard.d.l1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SFCIE for S76.)
+
+cflush.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SFCIE for S76.)
+
+cflush.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SFCIE for S76.)
+
+cdiscard.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SFCIE for S76.)
+
+cdiscard.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SFCIE for S76.)
+
+cease x1 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
+
+cease 0x10 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
+
+cease # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcie' (SiFive Custom Instruction Extension SFCIE for S76 MC)
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -278,3 +278,6 @@
 
 .attribute arch, "rv32i_zvfbfwma0p6"
 # CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfwma0p6_zvl3