[PATCH] D54091: [RISCV] Add inline asm constraints I, J & K for RISC-V

[Lewis Revill via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL363055: [RISCV] Add inline asm constraints I, J  K for 
RISC-V (authored by lewis-revill, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D54091?vs=203367=204043#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54091/new/

https://reviews.llvm.org/D54091

Files:
  cfe/trunk/lib/Basic/Targets/RISCV.cpp
  cfe/trunk/lib/Basic/Targets/RISCV.h


Index: cfe/trunk/lib/Basic/Targets/RISCV.cpp
===
--- cfe/trunk/lib/Basic/Targets/RISCV.cpp
+++ cfe/trunk/lib/Basic/Targets/RISCV.cpp
@@ -39,6 +39,26 @@
   return llvm::makeArrayRef(GCCRegAliases);
 }
 
+bool RISCVTargetInfo::validateAsmConstraint(
+const char *, TargetInfo::ConstraintInfo ) const {
+  switch (*Name) {
+  default:
+return false;
+  case 'I':
+// A 12-bit signed immediate.
+Info.setRequiresImmediate(-2048, 2047);
+return true;
+  case 'J':
+// Integer zero.
+Info.setRequiresImmediate(0);
+return true;
+  case 'K':
+// A 5-bit unsigned immediate for CSR access instructions.
+Info.setRequiresImmediate(0, 31);
+return true;
+  }
+}
+
 void RISCVTargetInfo::getTargetDefines(const LangOptions ,
MacroBuilder ) const {
   Builder.defineMacro("__ELF__");
Index: cfe/trunk/lib/Basic/Targets/RISCV.h
===
--- cfe/trunk/lib/Basic/Targets/RISCV.h
+++ cfe/trunk/lib/Basic/Targets/RISCV.h
@@ -61,9 +61,7 @@
   ArrayRef getGCCRegAliases() const override;
 
   bool validateAsmConstraint(const char *,
- TargetInfo::ConstraintInfo ) const override {
-return false;
-  }
+ TargetInfo::ConstraintInfo ) const override;
 
   bool hasFeature(StringRef Feature) const override;
 


Index: cfe/trunk/lib/Basic/Targets/RISCV.cpp
===
--- cfe/trunk/lib/Basic/Targets/RISCV.cpp
+++ cfe/trunk/lib/Basic/Targets/RISCV.cpp
@@ -39,6 +39,26 @@
   return llvm::makeArrayRef(GCCRegAliases);
 }
 
+bool RISCVTargetInfo::validateAsmConstraint(
+const char *, TargetInfo::ConstraintInfo ) const {
+  switch (*Name) {
+  default:
+return false;
+  case 'I':
+// A 12-bit signed immediate.
+Info.setRequiresImmediate(-2048, 2047);
+return true;
+  case 'J':
+// Integer zero.
+Info.setRequiresImmediate(0);
+return true;
+  case 'K':
+// A 5-bit unsigned immediate for CSR access instructions.
+Info.setRequiresImmediate(0, 31);
+return true;
+  }
+}
+
 void RISCVTargetInfo::getTargetDefines(const LangOptions ,
MacroBuilder ) const {
   Builder.defineMacro("__ELF__");
Index: cfe/trunk/lib/Basic/Targets/RISCV.h
===
--- cfe/trunk/lib/Basic/Targets/RISCV.h
+++ cfe/trunk/lib/Basic/Targets/RISCV.h
@@ -61,9 +61,7 @@
   ArrayRef getGCCRegAliases() const override;
 
   bool validateAsmConstraint(const char *,
- TargetInfo::ConstraintInfo ) const override {
-return false;
-  }
+ TargetInfo::ConstraintInfo ) const override;
 
   bool hasFeature(StringRef Feature) const override;
 
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D54091: [RISCV] Add inline asm constraints I, J & K for RISC-V

[Alex Bradbury via Phabricator via cfe-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.
Herald added a subscriber: Jim.

This looks good to me, but is blocked on the dependent patch being updated. I 
added a minor comment on riscv-inline-asm.c




Comment at: test/CodeGen/riscv-inline-asm.c:1
+// RUN: %clang_cc1 -triple riscv32 -target-feature +f -O2 -emit-llvm %s -o - \
+// RUN: | FileCheck %s

No need to enable +f for the test, as written.


Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54091/new/

https://reviews.llvm.org/D54091



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D54091: [RISCV] Add inline asm constraints I, J & K for RISC-V

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 203367.
lewis-revill edited the summary of this revision.
lewis-revill added a comment.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

- Rebased and fixed test run line


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54091/new/

https://reviews.llvm.org/D54091

Files:
  lib/Basic/Targets/RISCV.cpp
  lib/Basic/Targets/RISCV.h
  test/CodeGen/riscv-inline-asm.c
  test/Sema/inline-asm-validate-riscv.c

Index: test/Sema/inline-asm-validate-riscv.c
===
--- /dev/null
+++ test/Sema/inline-asm-validate-riscv.c
@@ -0,0 +1,26 @@
+// RUN: %clang_cc1 -triple riscv32 -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple riscv64 -fsyntax-only -verify %s
+
+void I(int i) {
+  static const int BelowMin = -2049;
+  static const int AboveMax = 2048;
+  asm volatile ("" :: "I"(i)); // expected-error{{constraint 'I' expects an integer constant expression}}
+  asm volatile ("" :: "I"(BelowMin)); // expected-error{{value '-2049' out of range for constraint 'I'}}
+  asm volatile ("" :: "I"(AboveMax)); // expected-error{{value '2048' out of range for constraint 'I'}}
+}
+
+void J(int j) {
+  static const int BelowMin = -1;
+  static const int AboveMax = 1;
+  asm volatile ("" :: "J"(j)); // expected-error{{constraint 'J' expects an integer constant expression}}
+  asm volatile ("" :: "J"(BelowMin)); // expected-error{{value '-1' out of range for constraint 'J'}}
+  asm volatile ("" :: "J"(AboveMax)); // expected-error{{value '1' out of range for constraint 'J'}}
+}
+
+void K(int k) {
+  static const int BelowMin = -1;
+  static const int AboveMax = 32;
+  asm volatile ("" :: "K"(k)); // expected-error{{constraint 'K' expects an integer constant expression}}
+  asm volatile ("" :: "K"(BelowMin)); // expected-error{{value '-1' out of range for constraint 'K'}}
+  asm volatile ("" :: "K"(AboveMax)); // expected-error{{value '32' out of range for constraint 'K'}}
+}
Index: test/CodeGen/riscv-inline-asm.c
===
--- /dev/null
+++ test/CodeGen/riscv-inline-asm.c
@@ -0,0 +1,28 @@
+// RUN: %clang_cc1 -triple riscv32 -O2 -emit-llvm %s -o - \
+// RUN: | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -O2 -emit-llvm %s -o - \
+// RUN: | FileCheck %s
+
+// Test RISC-V specific inline assembly constraints.
+
+void test_I() {
+// CHECK-LABEL: define void @test_I()
+// CHECK: call void asm sideeffect "", "I"(i32 2047)
+  asm volatile ("" :: "I"(2047));
+// CHECK: call void asm sideeffect "", "I"(i32 -2048)
+  asm volatile ("" :: "I"(-2048));
+}
+
+void test_J() {
+// CHECK-LABEL: define void @test_J()
+// CHECK: call void asm sideeffect "", "J"(i32 0)
+  asm volatile ("" :: "J"(0));
+}
+
+void test_K() {
+// CHECK-LABEL: define void @test_K()
+// CHECK: call void asm sideeffect "", "K"(i32 31)
+  asm volatile ("" :: "K"(31));
+// CHECK: call void asm sideeffect "", "K"(i32 0)
+  asm volatile ("" :: "K"(0));
+}
Index: lib/Basic/Targets/RISCV.h
===
--- lib/Basic/Targets/RISCV.h
+++ lib/Basic/Targets/RISCV.h
@@ -61,9 +61,7 @@
   ArrayRef getGCCRegAliases() const override;
 
   bool validateAsmConstraint(const char *,
- TargetInfo::ConstraintInfo ) const override {
-return false;
-  }
+ TargetInfo::ConstraintInfo ) const override;
 
   bool hasFeature(StringRef Feature) const override;
 
Index: lib/Basic/Targets/RISCV.cpp
===
--- lib/Basic/Targets/RISCV.cpp
+++ lib/Basic/Targets/RISCV.cpp
@@ -39,6 +39,26 @@
   return llvm::makeArrayRef(GCCRegAliases);
 }
 
+bool RISCVTargetInfo::validateAsmConstraint(
+const char *, TargetInfo::ConstraintInfo ) const {
+  switch (*Name) {
+  default:
+return false;
+  case 'I':
+// A 12-bit signed immediate.
+Info.setRequiresImmediate(-2048, 2047);
+return true;
+  case 'J':
+// Integer zero.
+Info.setRequiresImmediate(0);
+return true;
+  case 'K':
+// A 5-bit unsigned immediate for CSR access instructions.
+Info.setRequiresImmediate(0, 31);
+return true;
+  }
+}
+
 void RISCVTargetInfo::getTargetDefines(const LangOptions ,
MacroBuilder ) const {
   Builder.defineMacro("__ELF__");
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D54091: [RISCV] Add inline asm constraints I, J & K for RISC-V

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 174360.
lewis-revill edited the summary of this revision.
lewis-revill added a comment.

Updated to reflect desired changes (and fix an incorrect boundary). I didn't 
add r & m to riscv-inline-asm.c as I wasn't clear what exactly was desired.


Repository:
  rC Clang

https://reviews.llvm.org/D54091

Files:
  lib/Basic/Targets/RISCV.cpp
  lib/Basic/Targets/RISCV.h
  test/CodeGen/riscv-inline-asm.c
  test/Sema/inline-asm-validate-riscv.c

Index: test/Sema/inline-asm-validate-riscv.c
===
--- /dev/null
+++ test/Sema/inline-asm-validate-riscv.c
@@ -0,0 +1,26 @@
+// RUN: %clang_cc1 -triple riscv32 -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple riscv64 -fsyntax-only -verify %s
+
+void I(int i) {
+  static const int BelowMin = -2049;
+  static const int AboveMax = 2048;
+  asm volatile ("" :: "I"(i)); // expected-error{{constraint 'I' expects an integer constant expression}}
+  asm volatile ("" :: "I"(BelowMin)); // expected-error{{value '-2049' out of range for constraint 'I'}}
+  asm volatile ("" :: "I"(AboveMax)); // expected-error{{value '2048' out of range for constraint 'I'}}
+}
+
+void J(int j) {
+  static const int BelowMin = -1;
+  static const int AboveMax = 1;
+  asm volatile ("" :: "J"(j)); // expected-error{{constraint 'J' expects an integer constant expression}}
+  asm volatile ("" :: "J"(BelowMin)); // expected-error{{value '-1' out of range for constraint 'J'}}
+  asm volatile ("" :: "J"(AboveMax)); // expected-error{{value '1' out of range for constraint 'J'}}
+}
+
+void K(int k) {
+  static const int BelowMin = -1;
+  static const int AboveMax = 32;
+  asm volatile ("" :: "K"(k)); // expected-error{{constraint 'K' expects an integer constant expression}}
+  asm volatile ("" :: "K"(BelowMin)); // expected-error{{value '-1' out of range for constraint 'K'}}
+  asm volatile ("" :: "K"(AboveMax)); // expected-error{{value '32' out of range for constraint 'K'}}
+}
Index: test/CodeGen/riscv-inline-asm.c
===
--- /dev/null
+++ test/CodeGen/riscv-inline-asm.c
@@ -0,0 +1,28 @@
+// RUN: %clang_cc1 -triple riscv32 -target-feature +f -O2 -emit-llvm %s -o - \
+// RUN: | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -O2 -emit-llvm %s -o - \
+// RUN: | FileCheck %s
+
+// Test RISC-V specific inline assembly constraints.
+
+void test_I() {
+// CHECK-LABEL: define void @test_I()
+// CHECK: call void asm sideeffect "", "I"(i32 2047)
+  asm volatile ("" :: "I"(2047));
+// CHECK: call void asm sideeffect "", "I"(i32 -2048)
+  asm volatile ("" :: "I"(-2048));
+}
+
+void test_J() {
+// CHECK-LABEL: define void @test_J()
+// CHECK: call void asm sideeffect "", "J"(i32 0)
+  asm volatile ("" :: "J"(0));
+}
+
+void test_K() {
+// CHECK-LABEL: define void @test_K()
+// CHECK: call void asm sideeffect "", "K"(i32 31)
+  asm volatile ("" :: "K"(31));
+// CHECK: call void asm sideeffect "", "K"(i32 0)
+  asm volatile ("" :: "K"(0));
+}
Index: lib/Basic/Targets/RISCV.h
===
--- lib/Basic/Targets/RISCV.h
+++ lib/Basic/Targets/RISCV.h
@@ -62,9 +62,7 @@
   ArrayRef getGCCRegAliases() const override;
 
   bool validateAsmConstraint(const char *,
- TargetInfo::ConstraintInfo ) const override {
-return false;
-  }
+ TargetInfo::ConstraintInfo ) const override;
 
   bool hasFeature(StringRef Feature) const override;
 
Index: lib/Basic/Targets/RISCV.cpp
===
--- lib/Basic/Targets/RISCV.cpp
+++ lib/Basic/Targets/RISCV.cpp
@@ -40,6 +40,26 @@
   return llvm::makeArrayRef(GCCRegAliases);
 }
 
+bool RISCVTargetInfo::validateAsmConstraint(
+const char *, TargetInfo::ConstraintInfo ) const {
+  switch (*Name) {
+  default:
+return false;
+  case 'I':
+// A 12-bit signed immediate.
+Info.setRequiresImmediate(-2048, 2047);
+return true;
+  case 'J':
+// Integer zero.
+Info.setRequiresImmediate(0);
+return true;
+  case 'K':
+// A 5-bit unsigned immediate for CSR access instructions.
+Info.setRequiresImmediate(0, 31);
+return true;
+  }
+}
+
 void RISCVTargetInfo::getTargetDefines(const LangOptions ,
MacroBuilder ) const {
   Builder.defineMacro("__ELF__");
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D54091: [RISCV] Add inline asm constraints I, J & K for RISC-V

[Alex Bradbury via Phabricator via cfe-commits]

asb requested changes to this revision.
asb added a comment.
This revision now requires changes to proceed.

Thanks for the patch Lewis. Could I please request the following changes:

- It would be handy to link to 
https://gcc.gnu.org/onlinedocs/gccint/Machine-Constraints.html in the patch 
summary, so people can easily double-check the constraint definitions for 
themselves
- Could you add tests for values outside of the expected range. AArch64 and X86 
do this in test/Sema/inline-asm-validate-{aarch64,x86}.c
- It would be worth expanding riscv-inline-asm.c to provide simple sanity 
checks for "m" and "r"


Repository:
  rC Clang

https://reviews.llvm.org/D54091



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D54091: [RISCV] Add inline asm constraints I, J & K for RISC-V

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill created this revision.
lewis-revill added a reviewer: asb.
Herald added subscribers: cfe-commits, jocewei, PkmX, rkruppe, the_o, 
brucehoult, MartinMosbeck, rogfer01, mgrang, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, 
eraman.

This allows the constraints I, J & K to be used in inline asm for RISC-V, with 
the following semantics (equivalent to GCC):

I: Any 12-bit signed immediate.
J: Immediate integer zero only.
K: Any 5-bit unsigned immediate.

Note that GCC also implements 'f' for floating point register and 'A' for 
address-only operand. These are not implemented here because:

1. It appears trivial to implement the floating point register constraint, 
however since floating point registers are not recognised by the calling 
convention the call to the inline asm node cannot be lowered.
2. I'm not yet certain how to implement an 'address-only' operand and I'd 
rather get the above constraints done first and add it later.


Repository:
  rC Clang

https://reviews.llvm.org/D54091

Files:
  lib/Basic/Targets/RISCV.cpp
  lib/Basic/Targets/RISCV.h
  test/CodeGen/riscv-inline-asm.c


Index: test/CodeGen/riscv-inline-asm.c
===
--- /dev/null
+++ test/CodeGen/riscv-inline-asm.c
@@ -0,0 +1,28 @@
+// RUN: %clang_cc1 -triple riscv32 -target-feature +f -O2 -emit-llvm %s -o - \
+// RUN: | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -O2 -emit-llvm %s -o - \
+// RUN: | FileCheck %s
+
+// Test RISC-V specific inline assembly constraints.
+
+void test_I() {
+// CHECK-LABEL: define void @test_I()
+// CHECK: call void asm sideeffect "", "I"(i32 2047)
+  asm volatile ("" :: "I"(2047));
+// CHECK: call void asm sideeffect "", "I"(i32 -2048)
+  asm volatile ("" :: "I"(-2048));
+}
+
+void test_J() {
+// CHECK-LABEL: define void @test_J()
+// CHECK: call void asm sideeffect "", "J"(i32 0)
+  asm volatile ("" :: "J"(0));
+}
+
+void test_K() {
+// CHECK-LABEL: define void @test_K()
+// CHECK: call void asm sideeffect "", "K"(i32 31)
+  asm volatile ("" :: "K"(31));
+// CHECK: call void asm sideeffect "", "K"(i32 0)
+  asm volatile ("" :: "K"(0));
+}
Index: lib/Basic/Targets/RISCV.h
===
--- lib/Basic/Targets/RISCV.h
+++ lib/Basic/Targets/RISCV.h
@@ -62,9 +62,7 @@
   ArrayRef getGCCRegAliases() const override;
 
   bool validateAsmConstraint(const char *,
- TargetInfo::ConstraintInfo ) const override {
-return false;
-  }
+ TargetInfo::ConstraintInfo ) const override;
 
   bool hasFeature(StringRef Feature) const override;
 
Index: lib/Basic/Targets/RISCV.cpp
===
--- lib/Basic/Targets/RISCV.cpp
+++ lib/Basic/Targets/RISCV.cpp
@@ -40,6 +40,26 @@
   return llvm::makeArrayRef(GCCRegAliases);
 }
 
+bool RISCVTargetInfo::validateAsmConstraint(
+const char *, TargetInfo::ConstraintInfo ) const {
+  switch (*Name) {
+  default:
+return false;
+  case 'I':
+// A 12-bit signed immediate.
+Info.setRequiresImmediate(-2048, 2048);
+return true;
+  case 'J':
+// Integer zero.
+Info.setRequiresImmediate(0);
+return true;
+  case 'K':
+// A 5-bit unsigned immediate for CSR access instructions.
+Info.setRequiresImmediate(0, 31);
+return true;
+  }
+}
+
 void RISCVTargetInfo::getTargetDefines(const LangOptions ,
MacroBuilder ) const {
   Builder.defineMacro("__ELF__");


Index: test/CodeGen/riscv-inline-asm.c
===
--- /dev/null
+++ test/CodeGen/riscv-inline-asm.c
@@ -0,0 +1,28 @@
+// RUN: %clang_cc1 -triple riscv32 -target-feature +f -O2 -emit-llvm %s -o - \
+// RUN: | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -O2 -emit-llvm %s -o - \
+// RUN: | FileCheck %s
+
+// Test RISC-V specific inline assembly constraints.
+
+void test_I() {
+// CHECK-LABEL: define void @test_I()
+// CHECK: call void asm sideeffect "", "I"(i32 2047)
+  asm volatile ("" :: "I"(2047));
+// CHECK: call void asm sideeffect "", "I"(i32 -2048)
+  asm volatile ("" :: "I"(-2048));
+}
+
+void test_J() {
+// CHECK-LABEL: define void @test_J()
+// CHECK: call void asm sideeffect "", "J"(i32 0)
+  asm volatile ("" :: "J"(0));
+}
+
+void test_K() {
+// CHECK-LABEL: define void @test_K()
+// CHECK: call void asm sideeffect "", "K"(i32 31)
+  asm volatile ("" :: "K"(31));
+// CHECK: call void asm sideeffect "", "K"(i32 0)
+  asm volatile ("" :: "K"(0));
+}
Index: lib/Basic/Targets/RISCV.h
===
--- lib/Basic/Targets/RISCV.h
+++ lib/Basic/Targets/RISCV.h
@@ -62,9 +62,7 @@
   ArrayRef getGCCRegAliases() const override;
 
   bool validateAsmConstraint(const char *,
-