subject:"\[PATCH\] D67425\: \[WebAssembly\] Narrowing and widening SIMD ops"

[PATCH] D67425: [WebAssembly] Narrowing and widening SIMD ops

2019-09-13 Thread Thomas Lively via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL371906: [WebAssembly] Narrowing and widening SIMD ops 
(authored by tlively, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D67425?vs=219784=220189#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67425/new/

https://reviews.llvm.org/D67425

Files:
  cfe/trunk/include/clang/Basic/BuiltinsWebAssembly.def
  cfe/trunk/lib/CodeGen/CGBuiltin.cpp
  cfe/trunk/test/CodeGen/builtins-wasm.c
  llvm/trunk/include/llvm/IR/IntrinsicsWebAssembly.td
  llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
  llvm/trunk/test/CodeGen/WebAssembly/simd-intrinsics.ll
  llvm/trunk/test/MC/WebAssembly/simd-encodings.s

Index: llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
===
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -712,6 +712,42 @@
 defm "" : SIMDConvert;
 defm "" : SIMDConvert;
 
+// Widening operations
+multiclass SIMDWiden baseInst> {
+  defm "" : SIMDConvert;
+  defm "" : SIMDConvert;
+  defm "" : SIMDConvert;
+  defm "" : SIMDConvert;
+}
+
+defm "" : SIMDWiden;
+defm "" : SIMDWiden;
+
+// Narrowing operations
+multiclass SIMDNarrow baseInst> {
+  defm NARROW_S_#vec_t :
+SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins),
+   [(set (vec_t V128:$dst), (vec_t (int_wasm_narrow_signed
+ (arg_t V128:$low), (arg_t V128:$high],
+   vec#".narrow_"#arg#"_s\t$dst, $low, $high", vec#".narrow_"#arg#"_s",
+   baseInst>;
+  defm NARROW_U_#vec_t :
+SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins),
+   [(set (vec_t V128:$dst), (vec_t (int_wasm_narrow_unsigned
+ (arg_t V128:$low), (arg_t V128:$high],
+   vec#".narrow_"#arg#"_u\t$dst, $low, $high", vec#".narrow_"#arg#"_u",
+   !add(baseInst, 1)>;
+}
+
+defm "" : SIMDNarrow;
+defm "" : SIMDNarrow;
+
 // Lower llvm.wasm.trunc.saturate.* to saturating instructions
 def : Pat<(v4i32 (int_wasm_trunc_saturate_signed (v4f32 V128:$src))),
   (fp_to_sint_v4i32_v4f32 (v4f32 V128:$src))>;
Index: llvm/trunk/include/llvm/IR/IntrinsicsWebAssembly.td
===
--- llvm/trunk/include/llvm/IR/IntrinsicsWebAssembly.td
+++ llvm/trunk/include/llvm/IR/IntrinsicsWebAssembly.td
@@ -117,6 +117,31 @@
   Intrinsic<[llvm_anyvector_ty],
 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 [IntrNoMem, IntrSpeculatable]>;
+def int_wasm_narrow_signed :
+  Intrinsic<[llvm_anyvector_ty],
+[llvm_anyvector_ty, LLVMMatchType<1>],
+[IntrNoMem, IntrSpeculatable]>;
+def int_wasm_narrow_unsigned :
+  Intrinsic<[llvm_anyvector_ty],
+[llvm_anyvector_ty, LLVMMatchType<1>],
+[IntrNoMem, IntrSpeculatable]>;
+def int_wasm_widen_low_signed :
+  Intrinsic<[llvm_anyvector_ty],
+[llvm_anyvector_ty],
+[IntrNoMem, IntrSpeculatable]>;
+def int_wasm_widen_high_signed :
+  Intrinsic<[llvm_anyvector_ty],
+[llvm_anyvector_ty],
+[IntrNoMem, IntrSpeculatable]>;
+def int_wasm_widen_low_unsigned :
+  Intrinsic<[llvm_anyvector_ty],
+[llvm_anyvector_ty],
+[IntrNoMem, IntrSpeculatable]>;
+def int_wasm_widen_high_unsigned :
+  Intrinsic<[llvm_anyvector_ty],
+[llvm_anyvector_ty],
+[IntrNoMem, IntrSpeculatable]>;
+
 
 //===--===//
 // Bulk memory intrinsics
Index: llvm/trunk/test/CodeGen/WebAssembly/simd-intrinsics.ll
===
--- llvm/trunk/test/CodeGen/WebAssembly/simd-intrinsics.ll
+++ llvm/trunk/test/CodeGen/WebAssembly/simd-intrinsics.ll
@@ -87,6 +87,30 @@
   ret <16 x i8> %a
 }
 
+; CHECK-LABEL: narrow_signed_v16i8:
+; SIMD128-NEXT: .functype narrow_signed_v16i8 (v128, v128) -> (v128){{$}}
+; SIMD128-NEXT: i8x16.narrow_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16(<8 x i16>, <8 x i16>)
+define <16 x i8> @narrow_signed_v16i8(<8 x i16> %low, <8 x i16> %high) {
+  %a = call <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16(
+<8 x i16> %low, <8 x i16> %high
+  )
+  ret <16 x i8> %a
+}
+
+; CHECK-LABEL: narrow_unsigned_v16i8:
+; SIMD128-NEXT: .functype narrow_unsigned_v16i8 (v128, v128) -> (v128){{$}}
+; SIMD128-NEXT: i8x16.narrow_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16(<8 x i16>, <8 x i16>)
+define <16 x i8> @narrow_unsigned_v16i8(<8 x i16> %low, <8 x i16> %high) {
+  %a = call <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16(
+<8 x i16> %low, <8 x i16> %high
+  )
+  ret <16 x i8>

[PATCH] D67425: [WebAssembly] Narrowing and widening SIMD ops

2019-09-12 Thread Thomas Lively via Phabricator via cfe-commits

tlively added a comment.

In D67425#1668831 , @aheejin wrote:

> LGTM.
>
> - Maybe we can lower these 
> 
>  to these new instructions later? (I'm not very sure what the difference 
> between versions with and without `VECTOR`, because the versions without 
> `VECTOR` seem to be able to take vector arguments as well.)
> - Will this simplify the complicated lowering of `SIGN_EXTEND_INREG` 
> ?


Yes, good points. I will make a note to go back and clean these up once we are 
able to emit these instructions without explicit user opt-in.


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[PATCH] D67425: [WebAssembly] Narrowing and widening SIMD ops

2019-09-12 Thread Heejin Ahn via Phabricator via cfe-commits

aheejin accepted this revision.
aheejin added a comment.
This revision is now accepted and ready to land.

LGTM.

- Maybe we can lower these 

 to these new instructions later? (I'm not very sure what the difference 
between versions with and without `VECTOR`, because the versions without 
`VECTOR` seem to be able to take vector arguments as well.)
- Will this simplify the complicated lowering of `SIGN_EXTEND_INREG` 
?


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[PATCH] D67425: [WebAssembly] Narrowing and widening SIMD ops

2019-09-11 Thread Thomas Lively via Phabricator via cfe-commits

tlively updated this revision to Diff 219784.
tlively added a comment.

- Make narrows binary ops


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67425/new/

https://reviews.llvm.org/D67425

Files:
  clang/include/clang/Basic/BuiltinsWebAssembly.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-wasm.c
  llvm/include/llvm/IR/IntrinsicsWebAssembly.td
  llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
  llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
  llvm/test/MC/WebAssembly/simd-encodings.s

Index: llvm/test/MC/WebAssembly/simd-encodings.s
===
--- llvm/test/MC/WebAssembly/simd-encodings.s
+++ llvm/test/MC/WebAssembly/simd-encodings.s
@@ -463,4 +463,40 @@
 # CHECK: f64x2.convert_i64x2_u # encoding: [0xfd,0xb2,0x01]
 f64x2.convert_i64x2_u
 
+# CHECK: i8x16.narrow_i16x8_s # encoding: [0xfd,0xc6,0x01]
+i8x16.narrow_i16x8_s
+
+# CHECK: i8x16.narrow_i16x8_u # encoding: [0xfd,0xc7,0x01]
+i8x16.narrow_i16x8_u
+
+# CHECK: i16x8.narrow_i32x4_s # encoding: [0xfd,0xc8,0x01]
+i16x8.narrow_i32x4_s
+
+# CHECK: i16x8.narrow_i32x4_u # encoding: [0xfd,0xc9,0x01]
+i16x8.narrow_i32x4_u
+
+# CHECK: i16x8.widen_low_i8x16_s # encoding: [0xfd,0xca,0x01]
+i16x8.widen_low_i8x16_s
+
+# CHECK: i16x8.widen_high_i8x16_s # encoding: [0xfd,0xcb,0x01]
+i16x8.widen_high_i8x16_s
+
+# CHECK: i16x8.widen_low_i8x16_u # encoding: [0xfd,0xcc,0x01]
+i16x8.widen_low_i8x16_u
+
+# CHECK: i16x8.widen_high_i8x16_u # encoding: [0xfd,0xcd,0x01]
+i16x8.widen_high_i8x16_u
+
+# CHECK: i32x4.widen_low_i16x8_s # encoding: [0xfd,0xce,0x01]
+i32x4.widen_low_i16x8_s
+
+# CHECK: i32x4.widen_high_i16x8_s # encoding: [0xfd,0xcf,0x01]
+i32x4.widen_high_i16x8_s
+
+# CHECK: i32x4.widen_low_i16x8_u # encoding: [0xfd,0xd0,0x01]
+i32x4.widen_low_i16x8_u
+
+# CHECK: i32x4.widen_high_i16x8_u # encoding: [0xfd,0xd1,0x01]
+i32x4.widen_high_i16x8_u
+
 end_function
Index: llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
===
--- llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
+++ llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
@@ -87,6 +87,30 @@
   ret <16 x i8> %a
 }
 
+; CHECK-LABEL: narrow_signed_v16i8:
+; SIMD128-NEXT: .functype narrow_signed_v16i8 (v128, v128) -> (v128){{$}}
+; SIMD128-NEXT: i8x16.narrow_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16(<8 x i16>, <8 x i16>)
+define <16 x i8> @narrow_signed_v16i8(<8 x i16> %low, <8 x i16> %high) {
+  %a = call <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16(
+<8 x i16> %low, <8 x i16> %high
+  )
+  ret <16 x i8> %a
+}
+
+; CHECK-LABEL: narrow_unsigned_v16i8:
+; SIMD128-NEXT: .functype narrow_unsigned_v16i8 (v128, v128) -> (v128){{$}}
+; SIMD128-NEXT: i8x16.narrow_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16(<8 x i16>, <8 x i16>)
+define <16 x i8> @narrow_unsigned_v16i8(<8 x i16> %low, <8 x i16> %high) {
+  %a = call <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16(
+<8 x i16> %low, <8 x i16> %high
+  )
+  ret <16 x i8> %a
+}
+
 ; ==
 ; 8 x i16
 ; ==
@@ -166,6 +190,70 @@
   ret <8 x i16> %a
 }
 
+; CHECK-LABEL: narrow_signed_v8i16:
+; SIMD128-NEXT: .functype narrow_signed_v8i16 (v128, v128) -> (v128){{$}}
+; SIMD128-NEXT: i16x8.narrow_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32(<4 x i32>, <4 x i32>)
+define <8 x i16> @narrow_signed_v8i16(<4 x i32> %low, <4 x i32> %high) {
+  %a = call <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32(
+<4 x i32> %low, <4 x i32> %high
+  )
+  ret <8 x i16> %a
+}
+
+; CHECK-LABEL: narrow_unsigned_v8i16:
+; SIMD128-NEXT: .functype narrow_unsigned_v8i16 (v128, v128) -> (v128){{$}}
+; SIMD128-NEXT: i16x8.narrow_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32(<4 x i32>, <4 x i32>)
+define <8 x i16> @narrow_unsigned_v8i16(<4 x i32> %low, <4 x i32> %high) {
+  %a = call <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32(
+<4 x i32> %low, <4 x i32> %high
+  )
+  ret <8 x i16> %a
+}
+
+; CHECK-LABEL: widen_low_signed_v8i16:
+; SIMD128-NEXT: .functype widen_low_signed_v8i16 (v128) -> (v128){{$}}
+; SIMD128-NEXT: i16x8.widen_low_i8x16_s $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <8 x i16> @llvm.wasm.widen.low.signed.v8i16.v16i8(<16 x i8>)
+define <8 x i16> @widen_low_signed_v8i16(<16 x i8> %v) {
+  %a = call <8 x i16>

[PATCH] D67425: [WebAssembly] Narrowing and widening SIMD ops

2019-09-10 Thread Thomas Lively via Phabricator via cfe-commits

tlively planned changes to this revision.
tlively added a comment.

I missed the fact that the narrows are supposed to be binary operations. Oops.


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[PATCH] D67425: [WebAssembly] Narrowing and widening SIMD ops

2019-09-10 Thread Heejin Ahn via Phabricator via cfe-commits

aheejin added a comment.

Can you give the link for the spec of these new instructions?


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[PATCH] D67425: [WebAssembly] Narrowing and widening SIMD ops

2019-09-10 Thread Thomas Lively via Phabricator via cfe-commits

tlively created this revision.
tlively added a reviewer: aheejin.
Herald added subscribers: llvm-commits, cfe-commits, sunfish, hiraditya, 
jgravelle-google, sbc100, dschuff.
Herald added projects: clang, LLVM.

Implements target-specific LLVM intrinsics and clang builtins for
these new SIMD operations.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D67425

Files:
  clang/include/clang/Basic/BuiltinsWebAssembly.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-wasm.c
  llvm/include/llvm/IR/IntrinsicsWebAssembly.td
  llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
  llvm/test/MC/WebAssembly/simd-encodings.s

Index: llvm/test/MC/WebAssembly/simd-encodings.s
===
--- llvm/test/MC/WebAssembly/simd-encodings.s
+++ llvm/test/MC/WebAssembly/simd-encodings.s
@@ -463,4 +463,40 @@
 # CHECK: f64x2.convert_i64x2_u # encoding: [0xfd,0xb2,0x01]
 f64x2.convert_i64x2_u
 
+# CHECK: i8x16.narrow_i16x8_s # encoding: [0xfd,0xc6,0x01]
+i8x16.narrow_i16x8_s
+
+# CHECK: i8x16.narrow_i16x8_u # encoding: [0xfd,0xc7,0x01]
+i8x16.narrow_i16x8_u
+
+# CHECK: i16x8.narrow_i32x4_s # encoding: [0xfd,0xc8,0x01]
+i16x8.narrow_i32x4_s
+
+# CHECK: i16x8.narrow_i32x4_u # encoding: [0xfd,0xc9,0x01]
+i16x8.narrow_i32x4_u
+
+# CHECK: i16x8.widen_low_i8x16_s # encoding: [0xfd,0xca,0x01]
+i16x8.widen_low_i8x16_s
+
+# CHECK: i16x8.widen_high_i8x16_s # encoding: [0xfd,0xcb,0x01]
+i16x8.widen_high_i8x16_s
+
+# CHECK: i16x8.widen_low_i8x16_u # encoding: [0xfd,0xcc,0x01]
+i16x8.widen_low_i8x16_u
+
+# CHECK: i16x8.widen_high_i8x16_u # encoding: [0xfd,0xcd,0x01]
+i16x8.widen_high_i8x16_u
+
+# CHECK: i32x4.widen_low_i16x8_s # encoding: [0xfd,0xce,0x01]
+i32x4.widen_low_i16x8_s
+
+# CHECK: i32x4.widen_high_i16x8_s # encoding: [0xfd,0xcf,0x01]
+i32x4.widen_high_i16x8_s
+
+# CHECK: i32x4.widen_low_i16x8_u # encoding: [0xfd,0xd0,0x01]
+i32x4.widen_low_i16x8_u
+
+# CHECK: i32x4.widen_high_i16x8_u # encoding: [0xfd,0xd1,0x01]
+i32x4.widen_high_i16x8_u
+
 end_function
Index: llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
===
--- llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -712,6 +712,33 @@
 defm "" : SIMDConvert;
 defm "" : SIMDConvert;
 
+// Narrowing operations
+multiclass SIMDNarrow baseInst> {
+  defm "" : SIMDConvert;
+  defm "" : SIMDConvert;
+}
+defm "" : SIMDNarrow;
+defm "" : SIMDNarrow;
+
+// Widening operations
+multiclass SIMDWiden baseInst> {
+  defm "" : SIMDConvert;
+  defm "" : SIMDConvert;
+  defm "" : SIMDConvert;
+  defm "" : SIMDConvert;
+}
+
+defm "" : SIMDWiden;
+defm "" : SIMDWiden;
+
 // Lower llvm.wasm.trunc.saturate.* to saturating instructions
 def : Pat<(v4i32 (int_wasm_trunc_saturate_signed (v4f32 V128:$src))),
   (fp_to_sint_v4i32_v4f32 (v4f32 V128:$src))>;
Index: llvm/include/llvm/IR/IntrinsicsWebAssembly.td
===
--- llvm/include/llvm/IR/IntrinsicsWebAssembly.td
+++ llvm/include/llvm/IR/IntrinsicsWebAssembly.td
@@ -117,6 +117,31 @@
   Intrinsic<[llvm_anyvector_ty],
 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 [IntrNoMem, IntrSpeculatable]>;
+def int_wasm_narrow_signed :
+  Intrinsic<[llvm_anyvector_ty],
+[llvm_anyvector_ty],
+[IntrNoMem, IntrSpeculatable]>;
+def int_wasm_narrow_unsigned :
+  Intrinsic<[llvm_anyvector_ty],
+[llvm_anyvector_ty],
+[IntrNoMem, IntrSpeculatable]>;
+def int_wasm_widen_low_signed :
+  Intrinsic<[llvm_anyvector_ty],
+[llvm_anyvector_ty],
+[IntrNoMem, IntrSpeculatable]>;
+def int_wasm_widen_high_signed :
+  Intrinsic<[llvm_anyvector_ty],
+[llvm_anyvector_ty],
+[IntrNoMem, IntrSpeculatable]>;
+def int_wasm_widen_low_unsigned :
+  Intrinsic<[llvm_anyvector_ty],
+[llvm_anyvector_ty],
+[IntrNoMem, IntrSpeculatable]>;
+def int_wasm_widen_high_unsigned :
+  Intrinsic<[llvm_anyvector_ty],
+[llvm_anyvector_ty],
+[IntrNoMem, IntrSpeculatable]>;
+
 
 //===--===//
 // Bulk memory intrinsics
Index: clang/test/CodeGen/builtins-wasm.c
===
--- clang/test/CodeGen/builtins-wasm.c
+++ clang/test/CodeGen/builtins-wasm.c
@@ -463,3 +463,75 @@
   // WEBASSEMBLY: call <2 x i64> @llvm.wasm.trunc.saturate.unsigned.v2i64.v2f64(<2 x double> %f)
   // WEBASSEMBLY-NEXT: ret
 }
+
+i8x16 narrow_s_i8x16_i16x8(i16x8 v) {
+  return __builtin_wasm_narrow_s_i8x16_i16x8(v);
+  // WEBASSEMBLY: call <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16(<8 x i16> %v)
+  // WEBASSEMBLY: ret
+}
+
+i8x16 narrow_u_i8x16_i16x8(i16x8 v) {
+

[PATCH] D67425: [WebAssembly] Narrowing and widening SIMD ops

[PATCH] D67425: [WebAssembly] Narrowing and widening SIMD ops

[PATCH] D67425: [WebAssembly] Narrowing and widening SIMD ops

[PATCH] D67425: [WebAssembly] Narrowing and widening SIMD ops

[PATCH] D67425: [WebAssembly] Narrowing and widening SIMD ops

[PATCH] D67425: [WebAssembly] Narrowing and widening SIMD ops

[PATCH] D67425: [WebAssembly] Narrowing and widening SIMD ops

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