[PATCH] D94583: [RISCV] Update V extension to v1.0-draft 08a0b464.

2021-01-25 Thread Hsiangkai Wang via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGf19849a07b67: [RISCV] Update V extension to v1.0-draft 
08a0b464. (authored by HsiangKai).

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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -40,7 +40,7 @@
 # CHECK: attribute  5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_v0p9"
+# CHECK: attribute  5, "rv32i2p0_v1p0"
 
 .attribute arch, "rv32izba"
 # CHECK: attribute  5, "rv32i2p0_zba0p93"
@@ -79,7 +79,7 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
 .attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
+# CHECK: attribute  5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv_zvamo0p9_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
+.attribute arch, "rv32iv_zvamo1p0_zvlsseg"
+# CHECK: attribute  5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -47,7 +47,7 @@
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
 ; RV32B: .attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
-; RV32V: .attribute 5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
+; RV32V: .attribute 5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba0p93"
 ; RV32ZBB: .attribute 5, "rv32i2p0_zbb0p93"
@@ -60,7 +60,7 @@
 ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
 ; RV32ZBS: .attribute 5, "rv32i2p0_zbs0p93"
 ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
-; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p9_zfh0p1_zbb0p93_zvamo0p9_zvlsseg0p9"
+; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v1p0_zfh0p1_zbb0p93_zvamo1p0_zvlsseg1p0"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
@@ -80,8 +80,8 @@
 ; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
 ; RV64ZBS: .attribute 5, "rv64i2p0_zbs0p93"
 ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
-; RV64V: .attribute 5, "rv64i2p0_v0p9_zvamo0p9_zvlsseg0p9"
-; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p9_zfh0p1_zbb0p93_zvamo0p9_zvlsseg0p9"
+; RV64V: .attribute 5, "rv64i2p0_v1p0_zvamo1p0_zvlsseg1p0"
+; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v1p0_zfh0p1_zbb0p93_zvamo1p0_zvlsseg1p0"
 
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -63,7 +63,7 @@
   if (STI.hasFeature(RISCV::FeatureStdExtB))
 Arch += "_b0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtV))
-Arch += "_v0p9";
+Arch += "_v1p0";
   if (STI.hasFeature(RISCV::FeatureExtZfh))
 Arch += "_zfh0p1";
   if (STI.hasFeature(RISCV::FeatureExtZba))
@@ -89,9 +89,9 @@
   if (STI.hasFeature(RISCV::FeatureExtZbt))
 Arch += "_zbt0p93";
   if (STI.hasFeature(RISCV::FeatureExtZvamo))
-Arch += "_zvamo0p9";
+Arch += "_zvamo1p0";
   if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg))
-Arch += "_zvlsseg0p9";
+Arch += "_zvlsseg1p0";
 
   emitTextAttribute(RISCVAttrs::ARCH, Arch);
 }
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2126,7 +2126,7 @@
   if (getFeatureBits(RISCV::FeatureStdExtB))
 formalArchStr = (Twine(formalArchStr) + "_b0p93").str();
   if (getFeatureBits(RISCV::FeatureStdExtV))
-formalArchStr = (Twine(formalArchStr) + "_v0p9").str();
+formalArchStr = (Twine(formalArchStr) + "_v1p0").str();
   if (getFeatureBits(RISCV::FeatureExtZfh))
 formalArchStr = (Twine(formalArchStr) + "_zfh0p1").str();
   if (getFeatureBits(RISCV::FeatureExtZba))
@@ -2152,9 +2152,9 @@
   if (getFeatureBits(RISCV::FeatureExtZbt))
 formal

[PATCH] D94583: [RISCV] Update V extension to v1.0-draft 08a0b464.

2021-01-25 Thread Evandro Menezes via Phabricator via cfe-commits 
evandro added a comment.

Also, when the V spec becomes official, it'll be labeled v2.0.  Therefore, as 
long as v0.9 or v1.0 is implemented, V is only available as an experimental 
feature.


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[PATCH] D94583: [RISCV] Update V extension to v1.0-draft 08a0b464.

2021-01-25 Thread Hsiangkai Wang via Phabricator via cfe-commits 
HsiangKai updated this revision to Diff 318929.
HsiangKai added a comment.
Herald added subscribers: jdoerfert, hiraditya.
Herald added a project: LLVM.

Rebase.


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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -40,7 +40,7 @@
 # CHECK: attribute  5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_v0p9"
+# CHECK: attribute  5, "rv32i2p0_v1p0"
 
 .attribute arch, "rv32izba"
 # CHECK: attribute  5, "rv32i2p0_zba0p93"
@@ -79,7 +79,7 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh0p1"
 
 .attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
+# CHECK: attribute  5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv_zvamo0p9_zvlsseg"
-# CHECK: attribute  5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
+.attribute arch, "rv32iv_zvamo1p0_zvlsseg"
+# CHECK: attribute  5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -47,7 +47,7 @@
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
 ; RV32B: .attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
-; RV32V: .attribute 5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
+; RV32V: .attribute 5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba0p93"
 ; RV32ZBB: .attribute 5, "rv32i2p0_zbb0p93"
@@ -60,7 +60,7 @@
 ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
 ; RV32ZBS: .attribute 5, "rv32i2p0_zbs0p93"
 ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
-; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p9_zfh0p1_zbb0p93_zvamo0p9_zvlsseg0p9"
+; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v1p0_zfh0p1_zbb0p93_zvamo1p0_zvlsseg1p0"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
@@ -80,8 +80,8 @@
 ; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
 ; RV64ZBS: .attribute 5, "rv64i2p0_zbs0p93"
 ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
-; RV64V: .attribute 5, "rv64i2p0_v0p9_zvamo0p9_zvlsseg0p9"
-; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p9_zfh0p1_zbb0p93_zvamo0p9_zvlsseg0p9"
+; RV64V: .attribute 5, "rv64i2p0_v1p0_zvamo1p0_zvlsseg1p0"
+; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v1p0_zfh0p1_zbb0p93_zvamo1p0_zvlsseg1p0"
 
 
 define i32 @addi(i32 %a) {
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -63,7 +63,7 @@
   if (STI.hasFeature(RISCV::FeatureStdExtB))
 Arch += "_b0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtV))
-Arch += "_v0p9";
+Arch += "_v1p0";
   if (STI.hasFeature(RISCV::FeatureExtZfh))
 Arch += "_zfh0p1";
   if (STI.hasFeature(RISCV::FeatureExtZba))
@@ -89,9 +89,9 @@
   if (STI.hasFeature(RISCV::FeatureExtZbt))
 Arch += "_zbt0p93";
   if (STI.hasFeature(RISCV::FeatureExtZvamo))
-Arch += "_zvamo0p9";
+Arch += "_zvamo1p0";
   if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg))
-Arch += "_zvlsseg0p9";
+Arch += "_zvlsseg1p0";
 
   emitTextAttribute(RISCVAttrs::ARCH, Arch);
 }
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2126,7 +2126,7 @@
   if (getFeatureBits(RISCV::FeatureStdExtB))
 formalArchStr = (Twine(formalArchStr) + "_b0p93").str();
   if (getFeatureBits(RISCV::FeatureStdExtV))
-formalArchStr = (Twine(formalArchStr) + "_v0p9").str();
+formalArchStr = (Twine(formalArchStr) + "_v1p0").str();
   if (getFeatureBits(RISCV::FeatureExtZfh))
 formalArchStr = (Twine(formalArchStr) + "_zfh0p1").str();
   if (getFeatureBits(RISCV::FeatureExtZba))
@@ -2152,9 +2152,9 @@
   if (getFeatureBits(RISCV::FeatureExtZbt))
 formalArchStr = (Twine(formalArchStr) + "_zbt0p93").str();
   if (getFeatureBit

[PATCH] D94583: [RISCV] Update V extension to v1.0-draft 08a0b464.

2021-01-25 Thread Kito Cheng via Phabricator via cfe-commits 
kito-cheng added a comment.

Could you also update macros and attributes which implemented in 
https://reviews.llvm.org/D94403 and https://reviews.llvm.org/D94931


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[PATCH] D94583: [RISCV] Update V extension to v1.0-draft 08a0b464.

2021-01-24 Thread Hsiangkai Wang via Phabricator via cfe-commits 
HsiangKai added a comment.

In D94583#2514434 , @jrtc27 wrote:

> In D94583#2513915 , @HsiangKai wrote:
>
>> In D94583#2513070 , @jrtc27 wrote:
>>
>>> There are a lot of "Resolve for v1.0" issues open against the spec still. 
>>> Are we sure we want to brand this as 1.0? It will end up as such in the ELF 
>>> attributes and thus be deemed compatible with future "real" 1.0 binaries.
>>
>> We could keep the version number as v0.9 or do you think it is better to 
>> keep it as v1.020201218.
>
> You don't want it to be higher than 1.0 either as that would be newer than 
> the future actual 1.0.

Vector extension is under `-enable-experimental-extensions` in LLVM. Could we 
change the version number to v1.0 to align with current V specification? 
"Experimental v1.0" should be more consistent with "v1.0-draft" V 
specification. What do you think?


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[PATCH] D94583: [RISCV] Update V extension to v1.0-draft 08a0b464.

2021-01-21 Thread Kito Cheng via Phabricator via cfe-commits 
kito-cheng added a comment.

@jrtc27 just let you know I have same concern too, that's one major reason why 
we don't upstream those extension on GNU toolchain... we are intend to 
introduce an internal revision number on ELF attribute in near future, e.g. 
v-ext 0.9.1 / v0p9p1 to prevent compatible issue here.


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[PATCH] D94583: [RISCV] Update V extension to v1.0-draft 08a0b464.

2021-01-21 Thread Jessica Clarke via Phabricator via cfe-commits 
jrtc27 added a comment.

(Their problem stems from having 1.0 drafts before they've resolved all the 
outstanding issues and frozen the instruction set; if they didn't jump the gun 
then things would be saner for people implementing it)


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[PATCH] D94583: [RISCV] Update V extension to v1.0-draft 08a0b464.

2021-01-21 Thread Jessica Clarke via Phabricator via cfe-commits 
jrtc27 added a comment.

In D94583#2513915 , @HsiangKai wrote:

> In D94583#2513070 , @jrtc27 wrote:
>
>> There are a lot of "Resolve for v1.0" issues open against the spec still. 
>> Are we sure we want to brand this as 1.0? It will end up as such in the ELF 
>> attributes and thus be deemed compatible with future "real" 1.0 binaries.
>
> We could keep the version number as v0.9 or do you think it is better to keep 
> it as v1.020201218.

You don't want it to be higher than 1.0 either as that would be newer than the 
future actual 1.0.


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[PATCH] D94583: [RISCV] Update V extension to v1.0-draft 08a0b464.

2021-01-21 Thread Hsiangkai Wang via Phabricator via cfe-commits 
HsiangKai added a comment.

In D94583#2513070 , @jrtc27 wrote:

> There are a lot of "Resolve for v1.0" issues open against the spec still. Are 
> we sure we want to brand this as 1.0? It will end up as such in the ELF 
> attributes and thus be deemed compatible with future "real" 1.0 binaries.

We could keep the version number as v0.9 or do you think it is better to keep 
it as v1.020201218.


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[PATCH] D94583: [RISCV] Update V extension to v1.0-draft 08a0b464.

2021-01-21 Thread Jessica Clarke via Phabricator via cfe-commits 
jrtc27 added a comment.

There are a lot of "Resolve for v1.0" issues open against the spec still. Are 
we sure we want to brand this as 1.0? It will end up as such in the ELF 
attributes and thus be deemed compatible with future "real" 1.0 binaries.


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[PATCH] D94583: [RISCV] Update V extension to v1.0-draft 08a0b464.

2021-01-21 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D94583: [RISCV] Update V extension to v1.0-draft 08a0b464.

2021-01-21 Thread Hsiangkai Wang via Phabricator via cfe-commits 
HsiangKai updated this revision to Diff 318221.
HsiangKai added a comment.

Use v1.0 instead of strange version number. It is under 
-enable-experimental-extensions. So, I think it should be ok to do this.


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Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -80,10 +80,10 @@
 // CHECK-DOUBLE-NOT: __riscv_float_abi_single
 
 // RUN: %clang -target riscv32-unknown-linux-gnu 
-menable-experimental-extensions \
-// RUN:   -march=rv32iv0p9 -x c -E -dM %s \
+// RUN:   -march=rv32iv1p0 -x c -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu 
-menable-experimental-extensions \
-// RUN:   -march=rv64iv0p9 -x c -E -dM %s \
+// RUN:   -march=rv64iv1p0 -x c -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
 // CHECK-V-EXT: __riscv_vector 1
 //
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -380,7 +380,7 @@
 // RV32-EXPERIMENTAL-V-BADVERS: error: invalid arch name 'rv32iv0p1'
 // RV32-EXPERIMENTAL-V-BADVERS: unsupported version number 0.1 for 
experimental extension
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p9 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0 
-menable-experimental-extensions -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s
 // RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"
 
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -63,7 +63,7 @@
   Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
 return RISCVExtensionVersion{"0", "92"};
   if (Ext == "v")
-return RISCVExtensionVersion{"0", "9"};
+return RISCVExtensionVersion{"1", "0"};
   if (Ext == "zfh")
 return RISCVExtensionVersion{"0", "1"};
   return None;


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -80,10 +80,10 @@
 // CHECK-DOUBLE-NOT: __riscv_float_abi_single
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
-// RUN:   -march=rv32iv0p9 -x c -E -dM %s \
+// RUN:   -march=rv32iv1p0 -x c -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
-// RUN:   -march=rv64iv0p9 -x c -E -dM %s \
+// RUN:   -march=rv64iv1p0 -x c -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
 // CHECK-V-EXT: __riscv_vector 1
 //
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -380,7 +380,7 @@
 // RV32-EXPERIMENTAL-V-BADVERS: error: invalid arch name 'rv32iv0p1'
 // RV32-EXPERIMENTAL-V-BADVERS: unsupported version number 0.1 for experimental extension
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p9 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0 -menable-experimental-extensions -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s
 // RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"
 
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -63,7 +63,7 @@
   Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
 return RISCVExtensionVersion{"0", "92"};
   if (Ext == "v")
-return RISCVExtensionVersion{"0", "9"};
+return RISCVExtensionVersion{"1", "0"};
   if (Ext == "zfh")
 return RISCVExtensionVersion{"0", "1"};
   return None;
___
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[PATCH] D94583: [RISCV] Update V extension to v1.0-draft 08a0b464.

2021-01-12 Thread Hsiangkai Wang via Phabricator via cfe-commits 
HsiangKai created this revision.
HsiangKai added reviewers: craig.topper, evandro, rogfer01, frasercrmck, asb, 
luismarques, kito-cheng.
Herald added subscribers: NickHung, apazos, sameer.abuasal, pzheng, s.egerton, 
Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, 
edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, 
johnrusso, rbar.
HsiangKai requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

D93611 , D93612 
, D93613 , 
and D93614  have been reviewed and accepted. I 
change the version number of vector extension to v1.020201218, i.e., append the 
date of commit 08a0b464 in riscv-v-spec to v1.0.

Currently, there is no v1.0 tag in riscv-v-spec. That is why I use the date of 
the commit as the draft version number. We hope v1.0 could be merged into LLVM 
12. I am not sure whether it is an acceptable way to do it or not.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D94583

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -80,10 +80,10 @@
 // CHECK-DOUBLE-NOT: __riscv_float_abi_single
 
 // RUN: %clang -target riscv32-unknown-linux-gnu 
-menable-experimental-extensions \
-// RUN:   -march=rv32iv0p9 -x c -E -dM %s \
+// RUN:   -march=rv32iv1p020201218 -x c -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu 
-menable-experimental-extensions \
-// RUN:   -march=rv64iv0p9 -x c -E -dM %s \
+// RUN:   -march=rv64iv1p020201218 -x c -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
 // CHECK-V-EXT: __riscv_vector 1
 //
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -380,7 +380,7 @@
 // RV32-EXPERIMENTAL-V-BADVERS: error: invalid arch name 'rv32iv0p1'
 // RV32-EXPERIMENTAL-V-BADVERS: unsupported version number 0.1 for 
experimental extension
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p9 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p020201218 
-menable-experimental-extensions -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s
 // RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"
 
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -63,7 +63,7 @@
   Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
 return RISCVExtensionVersion{"0", "92"};
   if (Ext == "v")
-return RISCVExtensionVersion{"0", "9"};
+return RISCVExtensionVersion{"1", "020201218"};
   if (Ext == "zfh")
 return RISCVExtensionVersion{"0", "1"};
   return None;


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -80,10 +80,10 @@
 // CHECK-DOUBLE-NOT: __riscv_float_abi_single
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
-// RUN:   -march=rv32iv0p9 -x c -E -dM %s \
+// RUN:   -march=rv32iv1p020201218 -x c -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
-// RUN:   -march=rv64iv0p9 -x c -E -dM %s \
+// RUN:   -march=rv64iv1p020201218 -x c -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
 // CHECK-V-EXT: __riscv_vector 1
 //
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -380,7 +380,7 @@
 // RV32-EXPERIMENTAL-V-BADVERS: error: invalid arch name 'rv32iv0p1'
 // RV32-EXPERIMENTAL-V-BADVERS: unsupported version number 0.1 for experimental extension
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p9 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p020201218 -menable-experimental-extensions -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s
 // RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"
 
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp