[clang] [SVE][InstCombine] Delete redundante sel instructions with ptrue (PR #68463)

2023-10-10 Thread via cfe-commits 


@@ -800,6 +800,13 @@ instCombineConvertFromSVBool(InstCombiner &IC, 
IntrinsicInst &II) {
 
 static std::optional instCombineSVESel(InstCombiner &IC,
   IntrinsicInst &II) {
+  // svsel(ptrue, x, y) => x
+  auto *OpPredicate = II.getOperand(0);

vfdff wrote:

Yes, you are right. Writing more efficient code is another way to optimize.

https://github.com/llvm/llvm-project/pull/68463
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[clang] [SVE][InstCombine] Delete redundante sel instructions with ptrue (PR #68463)

2023-10-10 Thread David Sherwood via cfe-commits 


@@ -63,6 +63,20 @@ svint32_t test_svsel_s32(svbool_t pg, svint32_t op1, 
svint32_t op2)
   return SVE_ACLE_FUNC(svsel,_s32,,)(pg, op1, op2);
 }
 
+// CHECK-LABEL: @test_svsel_s32_ptrue(

david-arm wrote:

I'm not sure if this test really adds any more value, since the other test in 
Transforms/InstCombine/AArch64/sve-intrinsic-sel.ll is also testing the 
InstCombine.

https://github.com/llvm/llvm-project/pull/68463
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[clang] [SVE][InstCombine] Delete redundante sel instructions with ptrue (PR #68463)

2023-10-10 Thread David Sherwood via cfe-commits 


@@ -800,6 +800,13 @@ instCombineConvertFromSVBool(InstCombiner &IC, 
IntrinsicInst &II) {
 
 static std::optional instCombineSVESel(InstCombiner &IC,
   IntrinsicInst &II) {
+  // svsel(ptrue, x, y) => x
+  auto *OpPredicate = II.getOperand(0);

david-arm wrote:

This looks like a valid optimisation, but it also suggests that the ACLE code 
written in C/C++ would benefit from being rewritten in a way that avoids this.

https://github.com/llvm/llvm-project/pull/68463
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[clang] [SVE][InstCombine] Delete redundante sel instructions with ptrue (PR #68463)

2023-10-06 Thread via cfe-commits 

llvmbot wrote:




@llvm/pr-subscribers-clang


Changes

svsel(pture, x, y) => x. depend on D121792

---
Full diff: https://github.com/llvm/llvm-project/pull/68463.diff


3 Files Affected:

- (modified) clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c (+14) 
- (modified) llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp (+7) 
- (modified) llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-sel.ll 
(+10) 


``diff
diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c 
b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c
index ee29fe8a026d27c..7261ad7c147b38a 100644
--- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c
+++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c
@@ -63,6 +63,20 @@ svint32_t test_svsel_s32(svbool_t pg, svint32_t op1, 
svint32_t op2)
   return SVE_ACLE_FUNC(svsel,_s32,,)(pg, op1, op2);
 }
 
+// CHECK-LABEL: @test_svsel_s32_ptrue(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:ret  [[OP1:%.*]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svsel_s32_ptrueu11__SVInt32_tu11__SVInt32_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:ret  [[OP1:%.*]]
+//
+svint32_t test_svsel_s32_ptrue(svint32_t op1, svint32_t op2)
+{
+  svbool_t pg = svptrue_b32();
+  return SVE_ACLE_FUNC(svsel,_s32,,)(pg, op1, op2);
+}
+
 // CHECK-LABEL: @test_svsel_s64(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]])
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp 
b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index cded28054f59259..70bdb29ffcb13c3 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -800,6 +800,13 @@ instCombineConvertFromSVBool(InstCombiner &IC, 
IntrinsicInst &II) {
 
 static std::optional instCombineSVESel(InstCombiner &IC,
   IntrinsicInst &II) {
+  // svsel(ptrue, x, y) => x
+  auto *OpPredicate = II.getOperand(0);
+  if (match(OpPredicate, m_Intrinsic(
+ m_ConstantInt( {
+return IC.replaceInstUsesWith(II, II.getOperand(1));
+  }
+
   auto Select = IC.Builder.CreateSelect(II.getOperand(0), II.getOperand(1),
 II.getOperand(2));
   return IC.replaceInstUsesWith(II, Select);
diff --git a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-sel.ll 
b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-sel.ll
index b0f059c9de605e1..c6f08ce82882664 100644
--- a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-sel.ll
+++ b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-sel.ll
@@ -12,6 +12,16 @@ define  @replace_sel_intrinsic( %p,  %1
 }
 
+define  @sel_ptrue( %a,  
%b) {
+; CHECK-LABEL: @sel_ptrue(
+; CHECK-NEXT:ret  [[A:%.*]]
+;
+  %pred = call  @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
+  %res = call  @llvm.aarch64.sve.sel.nxv4i32( %pred,  %a,  %b)
+  ret  %res
+}
+
+declare  @llvm.aarch64.sve.ptrue.nxv4i1(i32)
 declare  @llvm.aarch64.sve.sel.nxv4i32(, 
, )
 
 attributes #0 = { "target-features"="+sve" }

``




https://github.com/llvm/llvm-project/pull/68463
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[clang] [SVE][InstCombine] Delete redundante sel instructions with ptrue (PR #68463)

2023-10-06 Thread via cfe-commits 

https://github.com/vfdff created https://github.com/llvm/llvm-project/pull/68463

svsel(pture, x, y) => x. depend on D121792

>From d4d0d96afa5c98be6b4a443f017321fbd1c41112 Mon Sep 17 00:00:00 2001
From: zhongyunde 00443407 
Date: Fri, 6 Oct 2023 21:54:36 -0400
Subject: [PATCH 1/2] [SVE][InstCombine] Precommit tests for select + ptrue

---
 .../aarch64-sve-intrinsics/acle_sve_sel.c  | 18 ++
 .../InstCombine/AArch64/sve-intrinsic-sel.ll   | 12 
 2 files changed, 30 insertions(+)

diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c 
b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c
index ee29fe8a026d27c..b2f5d6403c1050c 100644
--- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c
+++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c
@@ -63,6 +63,24 @@ svint32_t test_svsel_s32(svbool_t pg, svint32_t op1, 
svint32_t op2)
   return SVE_ACLE_FUNC(svsel,_s32,,)(pg, op1, op2);
 }
 
+// CHECK-LABEL: @test_svsel_s32_ptrue(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
+// CHECK-NEXT:[[TMP1:%.*]] = select  [[TMP0]],  [[OP1:%.*]],  [[OP2:%.*]]
+// CHECK-NEXT:ret  [[TMP1]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svsel_s32_ptrueu11__SVInt32_tu11__SVInt32_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
+// CPP-CHECK-NEXT:[[TMP1:%.*]] = select  [[TMP0]], 
 [[OP1:%.*]],  [[OP2:%.*]]
+// CPP-CHECK-NEXT:ret  [[TMP1]]
+//
+svint32_t test_svsel_s32_ptrue(svint32_t op1, svint32_t op2)
+{
+  svbool_t pg = svptrue_b32();
+  return SVE_ACLE_FUNC(svsel,_s32,,)(pg, op1, op2);
+}
+
 // CHECK-LABEL: @test_svsel_s64(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]])
diff --git a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-sel.ll 
b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-sel.ll
index b0f059c9de605e1..0d0c3b9892758e1 100644
--- a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-sel.ll
+++ b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-sel.ll
@@ -12,6 +12,18 @@ define  @replace_sel_intrinsic( %p,  %1
 }
 
+define  @sel_ptrue( %a,  
%b) {
+; CHECK-LABEL: @sel_ptrue(
+; CHECK-NEXT:[[PRED:%.*]] = call  
@llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
+; CHECK-NEXT:[[RES:%.*]] = select  [[PRED]],  [[A:%.*]],  [[B:%.*]]
+; CHECK-NEXT:ret  [[RES]]
+;
+  %pred = call  @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
+  %res = call  @llvm.aarch64.sve.sel.nxv4i32( %pred,  %a,  %b)
+  ret  %res
+}
+
+declare  @llvm.aarch64.sve.ptrue.nxv4i1(i32)
 declare  @llvm.aarch64.sve.sel.nxv4i32(, 
, )
 
 attributes #0 = { "target-features"="+sve" }

>From dd8b1da9e376ded84614837d65f50c4f797e60d8 Mon Sep 17 00:00:00 2001
From: zhongyunde 00443407 
Date: Wed, 27 Sep 2023 22:42:43 -0400
Subject: [PATCH 2/2] [SVE][InstCombine] Delete redundante sel instructions
 with ptrue

svsel(pture, x, y) => x. depend on D121792
---
 clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c  | 8 ++--
 llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp| 7 +++
 .../Transforms/InstCombine/AArch64/sve-intrinsic-sel.ll   | 4 +---
 3 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c 
b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c
index b2f5d6403c1050c..7261ad7c147b38a 100644
--- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c
+++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c
@@ -65,15 +65,11 @@ svint32_t test_svsel_s32(svbool_t pg, svint32_t op1, 
svint32_t op2)
 
 // CHECK-LABEL: @test_svsel_s32_ptrue(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
-// CHECK-NEXT:[[TMP1:%.*]] = select  [[TMP0]],  [[OP1:%.*]],  [[OP2:%.*]]
-// CHECK-NEXT:ret  [[TMP1]]
+// CHECK-NEXT:ret  [[OP1:%.*]]
 //
 // CPP-CHECK-LABEL: @_Z20test_svsel_s32_ptrueu11__SVInt32_tu11__SVInt32_t(
 // CPP-CHECK-NEXT:  entry:
-// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
-// CPP-CHECK-NEXT:[[TMP1:%.*]] = select  [[TMP0]], 
 [[OP1:%.*]],  [[OP2:%.*]]
-// CPP-CHECK-NEXT:ret  [[TMP1]]
+// CPP-CHECK-NEXT:ret  [[OP1:%.*]]
 //
 svint32_t test_svsel_s32_ptrue(svint32_t op1, svint32_t op2)
 {
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp 
b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index cded28054f59259..70bdb29ffcb13c3 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -800,6 +800,13 @@ instCombineConvertFromSVBool(InstCombiner &IC, 
IntrinsicInst &II) {
 
 static std::optional instCombineSVESel(InstCombiner &IC,
   IntrinsicInst &II) {
+  // svsel(ptrue, x, y) => x
+  auto *OpPredicat