[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
CarolineConcatto wrote: I believe it is fixed with this patch: commit 177cbd16663a2ca36d0d7145c3b62f2d756f8f7f (HEAD -> main, origin/main, origin/HEAD) Author: Caroline Concatto Date: Wed Jun 26 12:35:21 2024 + [Clang][SME2.1] Add REQUIRES: aarch64-registered-target to test PR#88710 is failing because the test file needs REQUIRES: aarch64-registered-target https://github.com/llvm/llvm-project/pull/88710 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
llvm-ci wrote: LLVM Buildbot has detected a new failure on builder `arc-builder` running on `arc-worker` while building `clang,llvm` at step 6 "test-build-unified-tree-check-all". Full details are available at: https://lab.llvm.org/buildbot/#/builders/3/builds/624 Here is the relevant piece of the build log for the reference: ``` Step 6 (test-build-unified-tree-check-all) failure: test (failure) TEST 'Clang :: CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c' FAILED Exit Code: 1 Command Output (stderr): -- RUN: at line 2: /buildbot/worker/arc-folder/build/bin/clang -cc1 -internal-isystem /buildbot/worker/arc-folder/build/lib/clang/19/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /buildbot/worker/arc-folder/llvm-project/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c | /buildbot/worker/arc-folder/build/bin/opt -S -p mem2reg,instcombine,tailcallelim | /buildbot/worker/arc-folder/build/bin/FileCheck /buildbot/worker/arc-folder/llvm-project/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c + /buildbot/worker/arc-folder/build/bin/opt -S -p mem2reg,instcombine,tailcallelim + /buildbot/worker/arc-folder/build/bin/FileCheck /buildbot/worker/arc-folder/llvm-project/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c + /buildbot/worker/arc-folder/build/bin/clang -cc1 -internal-isystem /buildbot/worker/arc-folder/build/lib/clang/19/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /buildbot/worker/arc-folder/llvm-project/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c /buildbot/worker/arc-folder/llvm-project/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c:6:10: fatal error: 'arm_sme.h' file not found 6 | #include | ^~~ 1 error generated. /buildbot/worker/arc-folder/llvm-project/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c:10:17: error: CHECK-LABEL: expected string not found in input // CHECK-LABEL: define dso_local @test_svreadz_hor_za8_s8_x2( ^ :1:1: note: scanning from here ; ModuleID = '' ^ Input file: Check file: /buildbot/worker/arc-folder/llvm-project/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c -dump-input=help explains the following input dump. Input was: << 1: ; ModuleID = '' label:10 X~~ error: no match found 2: source_filename = "" label:10 >> -- ``` https://github.com/llvm/llvm-project/pull/88710 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
llvm-ci wrote: LLVM Buildbot has detected a new failure on builder `openmp-offload-sles-build-only` running on `rocm-worker-hw-04-sles` while building `clang,llvm` at step 6 "Add check check-clang". Full details are available at: https://lab.llvm.org/buildbot/#/builders/140/builds/815 Here is the relevant piece of the build log for the reference: ``` Step 6 (Add check check-clang) failure: test (failure) TEST 'Clang :: CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c' FAILED Exit Code: 1 Command Output (stderr): -- RUN: at line 2: /home/botworker/bbot/builds/openmp-offload-sles-build/llvm.build/bin/clang -cc1 -internal-isystem /home/botworker/bbot/builds/openmp-offload-sles-build/llvm.build/lib/clang/19/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /home/botworker/bbot/builds/openmp-offload-sles-build/llvm.src/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c | /home/botworker/bbot/builds/openmp-offload-sles-build/llvm.build/bin/opt -S -p mem2reg,instcombine,tailcallelim | /home/botworker/bbot/builds/openmp-offload-sles-build/llvm.build/bin/FileCheck /home/botworker/bbot/builds/openmp-offload-sles-build/llvm.src/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c + /home/botworker/bbot/builds/openmp-offload-sles-build/llvm.build/bin/clang -cc1 -internal-isystem /home/botworker/bbot/builds/openmp-offload-sles-build/llvm.build/lib/clang/19/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /home/botworker/bbot/builds/openmp-offload-sles-build/llvm.src/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c + /home/botworker/bbot/builds/openmp-offload-sles-build/llvm.build/bin/FileCheck /home/botworker/bbot/builds/openmp-offload-sles-build/llvm.src/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c + /home/botworker/bbot/builds/openmp-offload-sles-build/llvm.build/bin/opt -S -p mem2reg,instcombine,tailcallelim /home/botworker/bbot/builds/openmp-offload-sles-build/llvm.src/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c:6:10: fatal error: 'arm_sme.h' file not found 6 | #include | ^~~ 1 error generated. /home/botworker/bbot/builds/openmp-offload-sles-build/llvm.src/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c:10:17: error: CHECK-LABEL: expected string not found in input // CHECK-LABEL: define dso_local @test_svreadz_hor_za8_s8_x2( ^ :1:1: note: scanning from here ; ModuleID = '' ^ Input file: Check file: /home/botworker/bbot/builds/openmp-offload-sles-build/llvm.src/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c -dump-input=help explains the following input dump. Input was: << 1: ; ModuleID = '' label:10 X~~ error: no match found 2: source_filename = "" label:10 >> -- ``` https://github.com/llvm/llvm-project/pull/88710 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
llvm-ci wrote: LLVM Buildbot has detected a new failure on builder `llvm-clang-x86_64-sie-ubuntu-fast` running on `sie-linux-worker` while building `clang,llvm` at step 6 "test-build-unified-tree-check-all". Full details are available at: https://lab.llvm.org/buildbot/#/builders/144/builds/905 Here is the relevant piece of the build log for the reference: ``` Step 6 (test-build-unified-tree-check-all) failure: test (failure) TEST 'Clang :: CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c' FAILED Exit Code: 1 Command Output (stderr): -- RUN: at line 2: /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/build/bin/clang -cc1 -internal-isystem /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/build/lib/clang/19/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/llvm-project/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c | /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/build/bin/opt -S -p mem2reg,instcombine,tailcallelim | /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/build/bin/FileCheck /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/llvm-project/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c + /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/build/bin/clang -cc1 -internal-isystem /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/build/lib/clang/19/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/llvm-project/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c + /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/build/bin/opt -S -p mem2reg,instcombine,tailcallelim + /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/build/bin/FileCheck /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/llvm-project/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/llvm-project/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c:6:10: fatal error: 'arm_sme.h' file not found 6 | #include | ^~~ 1 error generated. [1m/home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/llvm-project/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c:10:17: [0m[0;1;31merror: [0m[1mCHECK-LABEL: expected string not found in input [0m// CHECK-LABEL: define dso_local @test_svreadz_hor_za8_s8_x2( [0;1;32m^ [0m[1m:1:1: [0m[0;1;30mnote: [0m[1mscanning from here [0m; ModuleID = '' [0;1;32m^ [0m Input file: Check file: /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/llvm-project/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c -dump-input=help explains the following input dump. Input was: << [1m[0m[0;1;30m 1: [0m[1m[0;1;46m; ModuleID = '' [0m [0;1;31mlabel:10 X~~ error: no match found [0m[0;1;30m 2: [0m[1m[0;1;46msource_filename = "" [0m [0;1;31mlabel:10 [0m>> -- ``` https://github.com/llvm/llvm-project/pull/88710 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
llvm-ci wrote: LLVM Buildbot has detected a new failure on builder `clang-ve-ninja` running on `hpce-ve-main` while building `clang,llvm` at step 4 "annotate". Full details are available at: https://lab.llvm.org/buildbot/#/builders/12/builds/720 Here is the relevant piece of the build log for the reference: ``` Step 4 (annotate) failure: 'python ../llvm-zorg/zorg/buildbot/builders/annotated/ve-linux.py ...' (failure) ... [300/306] Building CXX object tools/clang/unittests/Interpreter/CMakeFiles/ClangReplInterpreterTests.dir/InterpreterTest.cpp.o [301/306] Linking CXX executable tools/clang/unittests/Frontend/FrontendTests [302/306] Linking CXX executable tools/clang/unittests/Tooling/ToolingTests [303/306] Linking CXX executable tools/clang/unittests/CodeGen/ClangCodeGenTests [304/306] Linking CXX executable tools/clang/unittests/Interpreter/ExceptionTests/ClangReplInterpreterExceptionTests [305/306] Linking CXX executable tools/clang/unittests/Interpreter/ClangReplInterpreterTests [305/306] Running the Clang regression tests -- Testing: 20665 tests, 48 workers -- llvm-lit: /scratch/buildbot/bothome/clang-ve-ninja/llvm-project/llvm/utils/lit/lit/llvm/config.py:508: note: using clang: /scratch/buildbot/bothome/clang-ve-ninja/build/build_llvm/bin/clang Testing: 0.. 10.. 20. FAIL: Clang :: CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c (5659 of 20665) TEST 'Clang :: CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c' FAILED Exit Code: 1 Command Output (stderr): -- RUN: at line 2: /scratch/buildbot/bothome/clang-ve-ninja/build/build_llvm/bin/clang -cc1 -internal-isystem /scratch/buildbot/bothome/clang-ve-ninja/build/build_llvm/lib/clang/19/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /scratch/buildbot/bothome/clang-ve-ninja/llvm-project/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c | /scratch/buildbot/bothome/clang-ve-ninja/build/build_llvm/bin/opt -S -p mem2reg,instcombine,tailcallelim | /scratch/buildbot/bothome/clang-ve-ninja/build/build_llvm/bin/FileCheck /scratch/buildbot/bothome/clang-ve-ninja/llvm-project/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c + /scratch/buildbot/bothome/clang-ve-ninja/build/build_llvm/bin/clang -cc1 -internal-isystem /scratch/buildbot/bothome/clang-ve-ninja/build/build_llvm/lib/clang/19/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /scratch/buildbot/bothome/clang-ve-ninja/llvm-project/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c + /scratch/buildbot/bothome/clang-ve-ninja/build/build_llvm/bin/opt -S -p mem2reg,instcombine,tailcallelim + /scratch/buildbot/bothome/clang-ve-ninja/build/build_llvm/bin/FileCheck /scratch/buildbot/bothome/clang-ve-ninja/llvm-project/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c /scratch/buildbot/bothome/clang-ve-ninja/llvm-project/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c:6:10: fatal error: 'arm_sme.h' file not found 6 | #include | ^~~ 1 error generated. /scratch/buildbot/bothome/clang-ve-ninja/llvm-project/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c:10:17: error: CHECK-LABEL: expected string not found in input // CHECK-LABEL: define dso_local @test_svreadz_hor_za8_s8_x2( ^ :1:1: note: scanning from here ; ModuleID = '' ^ Input file: Check file: /scratch/buildbot/bothome/clang-ve-ninja/llvm-project/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c -dump-input=help explains the following input dump. Input was: << 1: ; ModuleID = '' label:10 X~~ error: no match found 2: source_filename = "" label:10 >> -- Testing: 0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.. Step 8 (check-llvm) failure: check-llvm (failure) ... [300/306] Building CXX object tools/clang/unittests/Interpreter/CMakeFiles/ClangReplInterpreterTests.dir/InterpreterTest.cpp.o [301/306] Linking CXX executable tools/clang/unittests/Frontend/FrontendTests [302/306] Linking CXX executable tools/clang/unittests/Tooling/ToolingTests [303/306] Linking CXX executable tools/clang/unittests/CodeGen/ClangCodeGenTests [304/306] Linking CXX executable tools/clang/unittests/Interpreter/ExceptionTests/ClangReplInterpreterExceptionTests [305/306] Linking CXX executable tools/clang/unittests/Interpreter/ClangReplInterpreterTests [305/306] Running the Clang regression tests -- Testing: 20665 tests, 48 workers -- llvm-lit: /scratch/buildbot/bothome/clang-ve-ninja/llvm-project/llvm/utils/lit/lit/llvm/config.py:508: note: using clang:
[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
https://github.com/CarolineConcatto closed https://github.com/llvm/llvm-project/pull/88710 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
aemerson wrote: Reverse ping https://github.com/llvm/llvm-project/pull/88710 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
https://github.com/momchil-velikov approved this pull request. https://github.com/llvm/llvm-project/pull/88710 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
https://github.com/aemerson approved this pull request. LGTM unless others have comments. https://github.com/llvm/llvm-project/pull/88710 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
@@ -674,3 +674,26 @@ let TargetGuard = "sme2" in {
def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i",
"cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming,
IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
def SVLUTI4_LANE_ZT_X2 : Inst<"svluti4_lane_zt_{d}_x2", "2.di[i",
"cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x2", [IsStreaming,
IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>;
}
+
+multiclass ZAReadz ch> {
+ let TargetGuard = "sme2p1" in {
+def NAME # _H : SInst<"svreadz_hor_" # n_suffix # "_{d}_vg" # vg_num,
vg_num # "im", t,
+ MergeNone, i_prefix # "_horiz_x" # vg_num,
+ [IsStreaming, IsInOutZA], ch>;
aemerson wrote:
Ah indeed.
https://github.com/llvm/llvm-project/pull/88710
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[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
@@ -674,3 +674,26 @@ let TargetGuard = "sme2" in {
def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i",
"cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming,
IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
def SVLUTI4_LANE_ZT_X2 : Inst<"svluti4_lane_zt_{d}_x2", "2.di[i",
"cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x2", [IsStreaming,
IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>;
}
+
+multiclass ZAReadz ch> {
+ let TargetGuard = "sme2p1" in {
+def NAME # _H : SInst<"svreadz_hor_" # n_suffix # "_{d}_vg" # vg_num,
vg_num # "im", t,
+ MergeNone, i_prefix # "_horiz_x" # vg_num,
+ [IsStreaming, IsInOutZA], ch>;
momchil-velikov wrote:
> Should these be `InZA` instead of `InOutZA`? And also `ReadZA` (not sure what
> that's for).
The instructions zero the source tiles after copying
(https://developer.arm.com/documentation/ddi0602/2024-03/SME-Instructions/MOVAZ--tile-to-vector--four-registers---Move-and-zero-four-ZA-tile-slices-to-vector-registers-?lang=en
).
https://github.com/llvm/llvm-project/pull/88710
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[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
@@ -674,3 +674,26 @@ let TargetGuard = "sme2" in {
def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i",
"cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming,
IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
def SVLUTI4_LANE_ZT_X2 : Inst<"svluti4_lane_zt_{d}_x2", "2.di[i",
"cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x2", [IsStreaming,
IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>;
}
+
+multiclass ZAReadz ch> {
+ let TargetGuard = "sme2p1" in {
+def NAME # _H : SInst<"svreadz_hor_" # n_suffix # "_{d}_vg" # vg_num,
vg_num # "im", t,
+ MergeNone, i_prefix # "_horiz_x" # vg_num,
+ [IsStreaming, IsInOutZA], ch>;
CarolineConcatto wrote:
According to the speck
https://github.com/ARM-software/acle/pull/309/files#diff-516526d4a18101dc85300bc2033d0f86dc46c505b7510a7694baabea851aedfaR12190
All movaz instructions are InOutZa:
svint8x2_t svreadz_hor_za8_s8_vg2(uint64_t tile, uint32_t slice)
__arm_streaming __arm_inout("za");
About ReadZA does not look like I need that:
```
if (TypeFlags.isReadZA())
Ops[1] = EmitSVEPredicateCast(Ops[1], VecTy);
else if (TypeFlags.isWriteZA())
Ops[2] = EmitSVEPredicateCast(Ops[2], VecTy);
```
https://github.com/llvm/llvm-project/pull/88710
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[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
@@ -674,3 +674,26 @@ let TargetGuard = "sme2" in {
def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i",
"cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming,
IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
def SVLUTI4_LANE_ZT_X2 : Inst<"svluti4_lane_zt_{d}_x2", "2.di[i",
"cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x2", [IsStreaming,
IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>;
}
+
+multiclass ZAReadz ch> {
+ let TargetGuard = "sme2p1" in {
+def NAME # _H : SInst<"svreadz_hor_" # n_suffix # "_{d}_vg" # vg_num,
vg_num # "im", t,
+ MergeNone, i_prefix # "_horiz_x" # vg_num,
+ [IsStreaming, IsInOutZA], ch>;
aemerson wrote:
Should these be `InZA` instead of `InOutZA`? And also `ReadZA` (not sure what
that's for).
https://github.com/llvm/llvm-project/pull/88710
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[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
@@ -2939,59 +2922,18 @@ MachineBasicBlock
*AArch64TargetLowering::EmitInstrWithCustomInserter(
TII->get(MI.getOpcode()).TSFlags & AArch64::SMEMatrixTypeMask;
switch (SMEMatrixType) {
case (AArch64::SMEMatrixArray):
- return EmitZAInstr(SMEOrigInstr, AArch64::ZA, MI, BB, /*HasTile*/ false,
- /*HasZPROut*/ false);
+ return EmitZAInstr(SMEOrigInstr, AArch64::ZA, MI, BB);
case (AArch64::SMEMatrixTileB):
- switch (MI.getOpcode()) {
- case AArch64::MOVAZ_2ZMI_H_B_PSEUDO:
- case AArch64::MOVAZ_2ZMI_V_B_PSEUDO:
- case AArch64::MOVAZ_4ZMI_H_B_PSEUDO:
- case AArch64::MOVAZ_4ZMI_V_B_PSEUDO:
-return EmitZAInstr(SMEOrigInstr, AArch64::ZAB0, MI, BB,
- /*HasTile*/ true, /*HasZPROut*/ true);
- default:
-return EmitZAInstr(SMEOrigInstr, AArch64::ZAB0, MI, BB,
- /*HasTile*/ true, /*HasZPROut*/ false);
- }
+ return EmitZAInstr(SMEOrigInstr, AArch64::ZAB0, MI, BB);
case (AArch64::SMEMatrixTileH):
- switch (MI.getOpcode()) {
- case AArch64::MOVAZ_2ZMI_H_H_PSEUDO:
- case AArch64::MOVAZ_2ZMI_V_H_PSEUDO:
- case AArch64::MOVAZ_4ZMI_H_H_PSEUDO:
- case AArch64::MOVAZ_4ZMI_V_H_PSEUDO:
-return EmitZAInstr(SMEOrigInstr, AArch64::ZAH0, MI, BB,
- /*HasTile*/ true, /*HasZPROut*/ true);
- default:
-return EmitZAInstr(SMEOrigInstr, AArch64::ZAH0, MI, BB,
- /*HasTile*/ true, /*HasZPROut*/ false);
- }
+ return EmitZAInstr(SMEOrigInstr, AArch64::ZAH0, MI, BB);
+ ///*HasTile*/ true, /*HasZPROut*/ false);
momchil-velikov wrote:
Stray comment.
https://github.com/llvm/llvm-project/pull/88710
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[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
momchil-velikov wrote:
```
if (HasTile) {
MIB.addReg(BaseReg + MI.getOperand(0).getImm(), RegState::Define);
MIB.addReg(BaseReg + MI.getOperand(0).getImm());
StartIdx = 1;
} else
MIB.addReg(BaseReg, RegState::Define).addReg(BaseReg);
}
```
Needs extra braces around the `else` clause,
https://llvm.org/docs/CodingStandards.html#don-t-use-braces-on-simple-single-statement-bodies-of-if-else-loop-statements
cf.
```
// Use braces for the `if` block to keep it uniform with the `else` block.
if (isa(D)) {
handleFunctionDecl(D);
} else {
// In this `else` case, it is necessary that we explain the situation with
// this surprisingly long comment, so it would be unclear without the braces
// whether the following statement is in the scope of the `if`.
handleOtherDecl(D);
}
```
https://github.com/llvm/llvm-project/pull/88710
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[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
@@ -2883,19 +2883,28 @@ MachineBasicBlock
*AArch64TargetLowering::EmitZTInstr(MachineInstr ,
MachineBasicBlock *
AArch64TargetLowering::EmitZAInstr(unsigned Opc, unsigned BaseReg,
- MachineInstr ,
- MachineBasicBlock *BB, bool HasTile) const {
+ MachineInstr , MachineBasicBlock *BB,
+ bool HasTile, bool HasZPROut) const {
const TargetInstrInfo *TII = Subtarget->getInstrInfo();
MachineInstrBuilder MIB = BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Opc));
unsigned StartIdx = 0;
- if (HasTile) {
-MIB.addReg(BaseReg + MI.getOperand(0).getImm(), RegState::Define);
-MIB.addReg(BaseReg + MI.getOperand(0).getImm());
-StartIdx = 1;
- } else
-MIB.addReg(BaseReg, RegState::Define).addReg(BaseReg);
-
+ if (HasZPROut) {
momchil-velikov wrote:
Looks good with the last change. Still can further simplify and make it more
readable like in the snippet above.
https://github.com/llvm/llvm-project/pull/88710
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[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
https://github.com/momchil-velikov edited https://github.com/llvm/llvm-project/pull/88710 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
https://github.com/momchil-velikov edited https://github.com/llvm/llvm-project/pull/88710 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
@@ -2883,19 +2883,28 @@ MachineBasicBlock
*AArch64TargetLowering::EmitZTInstr(MachineInstr ,
MachineBasicBlock *
AArch64TargetLowering::EmitZAInstr(unsigned Opc, unsigned BaseReg,
- MachineInstr ,
- MachineBasicBlock *BB, bool HasTile) const {
+ MachineInstr , MachineBasicBlock *BB,
+ bool HasTile, bool HasZPROut) const {
const TargetInstrInfo *TII = Subtarget->getInstrInfo();
MachineInstrBuilder MIB = BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Opc));
unsigned StartIdx = 0;
- if (HasTile) {
-MIB.addReg(BaseReg + MI.getOperand(0).getImm(), RegState::Define);
-MIB.addReg(BaseReg + MI.getOperand(0).getImm());
-StartIdx = 1;
- } else
-MIB.addReg(BaseReg, RegState::Define).addReg(BaseReg);
-
+ if (HasZPROut) {
momchil-velikov wrote:
I think it can be made a bit more clear and less verbose if we separate the
conditions and use `StartIdx` to track how many of the input operands we have
consumes, something like:
```
unsigned StartIdx = 0;
if (HasGPROut) {
MIB.add(MI.getOperand(0)); // Output ZPR
++StartIdx;
}
if (HasTile) {
MIB.addReg(BaseReg + MI.getOperand(StartIdx).getImm(), RegState::Define); //
Output ZA Tile
MIB.addReg(BaseReg + MI.getOperand(StartIdx).getImm()); // Input Za Tile
++StartIdx;
} else {
MIB.addReg(BaseReg, RegState::Define).addReg(BaseReg);
}
```
https://github.com/llvm/llvm-project/pull/88710
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[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
@@ -2883,19 +2883,28 @@ MachineBasicBlock
*AArch64TargetLowering::EmitZTInstr(MachineInstr ,
MachineBasicBlock *
AArch64TargetLowering::EmitZAInstr(unsigned Opc, unsigned BaseReg,
- MachineInstr ,
- MachineBasicBlock *BB, bool HasTile) const {
+ MachineInstr , MachineBasicBlock *BB,
+ bool HasTile, bool HasZPROut) const {
momchil-velikov wrote:
I'm wondering would it be possible to remove *both* `bool` parameters and
instead infer their value in the function itself.
Maybe like this:
```
bool HasTile = BaseReg != AArch64::ZA;
bool HasZPROut = HasTile && MI.getOperand(0).isReg();
```
https://github.com/llvm/llvm-project/pull/88710
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[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
@@ -2930,17 +2939,59 @@ MachineBasicBlock
*AArch64TargetLowering::EmitInstrWithCustomInserter(
TII->get(MI.getOpcode()).TSFlags & AArch64::SMEMatrixTypeMask;
switch (SMEMatrixType) {
case (AArch64::SMEMatrixArray):
- return EmitZAInstr(SMEOrigInstr, AArch64::ZA, MI, BB, /*HasTile*/ false);
+ return EmitZAInstr(SMEOrigInstr, AArch64::ZA, MI, BB, /*HasTile*/ false,
momchil-velikov wrote:
We the changes from the comment above we can remove all the `bool` arguments
and, most importantly, all those opcodes.
https://github.com/llvm/llvm-project/pull/88710
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[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
@@ -1985,6 +1986,34 @@ void AArch64DAGToDAGISel::SelectMultiVectorMove(SDNode *N, unsigned NumVecs, CurDAG->RemoveDeadNode(N); } +template +void AArch64DAGToDAGISel::SelectMultiVectorMoveZ(SDNode *N, unsigned NumVecs, Lukacma wrote: That's a good point. Somehow I assumed we are using the template version of `SelectSMETileSlice` so I didn't question it https://github.com/llvm/llvm-project/pull/88710 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
@@ -1985,6 +1986,34 @@ void AArch64DAGToDAGISel::SelectMultiVectorMove(SDNode *N, unsigned NumVecs, CurDAG->RemoveDeadNode(N); } +template +void AArch64DAGToDAGISel::SelectMultiVectorMoveZ(SDNode *N, unsigned NumVecs, momchil-velikov wrote: The real question is why is this is a function template or, if you want, why `AArch64DAGToDAGISel::SelectMultiVectorMove` is a function template? Both the template parameters do not affect any type, so we aren't benefiting from any kind of parametric polymorphism, the parameters themselves are only passed as ordinary parameters to `SelectSMETileSlice` and as such can't participate in any constant folding that would warrant multiple instantiations (each of which is essentially a specialisation of the function). IMHO, it's OK to have the `Scale` and `NumVecs` separate since `SelectMultiVectorMove` is a hint we may need it some day. https://github.com/llvm/llvm-project/pull/88710 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
@@ -1985,6 +1986,34 @@ void AArch64DAGToDAGISel::SelectMultiVectorMove(SDNode *N, unsigned NumVecs, CurDAG->RemoveDeadNode(N); } +template +void AArch64DAGToDAGISel::SelectMultiVectorMoveZ(SDNode *N, unsigned NumVecs, Lukacma wrote: `Scale` could be used instead of `NumVecs` parameter https://github.com/llvm/llvm-project/pull/88710 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
https://github.com/Lukacma deleted https://github.com/llvm/llvm-project/pull/88710 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
@@ -0,0 +1,457 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2p1 -verify-machineinstrs <
%s | FileCheck %s
+
+;MOVAZ (tile to vector, Multi)
+
+
+;;
+; X2 - Horiz
+;;
+
+define {, } @test_readz_hor_z8_i8_x2(i32
%tile, i32 %slice) {
+; CHECK-LABEL: test_readz_hor_z8_i8_x2:
+; CHECK: // %bb.0:
+; CHECK-NEXT:mov w12, w1
+; CHECK-NEXT:movaz { z0.b, z1.b }, za0h.b[w12, 0:1]
+; CHECK-NEXT:movaz { z0.b, z1.b }, za0h.b[w12, 14:15]
+; CHECK-NEXT:ret
+ %res = call {, }
@llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %slice)
+ %slice.max = add i32 %slice, 14
+ %res2 = call {, }
@llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %slice.max)
+ ret {, } %res2
+}
+define {, } @test_readz_hor_z16_i16_x2(i32
%slice) {
+; CHECK-LABEL: test_readz_hor_z16_i16_x2:
+; CHECK: // %bb.0:
+; CHECK-NEXT:mov w12, w0
+; CHECK-NEXT:movaz { z0.h, z1.h }, za0h.h[w12, 0:1]
+; CHECK-NEXT:movaz { z0.h, z1.h }, za1h.h[w12, 6:7]
+; CHECK-NEXT:ret
+ %res = call {, }
@llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 0, i32 %slice)
+ %slice.max = add i32 %slice, 6
+ %res2 = call {, }
@llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 1, i32 %slice.max)
+ ret {, } %res2
+}
+
+define {, } @test_readz_hor_z32_i32_x2(i32
%slice) {
+; CHECK-LABEL: test_readz_hor_z32_i32_x2:
+; CHECK: // %bb.0:
+; CHECK-NEXT:mov w12, w0
+; CHECK-NEXT:movaz { z0.s, z1.s }, za0h.s[w12, 0:1]
+; CHECK-NEXT:movaz { z0.s, z1.s }, za3h.s[w12, 2:3]
+; CHECK-NEXT:ret
+ %res = call {, }
@llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 0, i32 %slice)
+ %slice.max = add i32 %slice, 2
+ %res2 = call {, }
@llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 3, i32 %slice.max)
+ ret {, } %res2
+}
+
+define {, } @test_readz_hor_z64_i64_x2(i32
%slice) {
+; CHECK-LABEL: test_readz_hor_z64_i64_x2:
+; CHECK: // %bb.0:
+; CHECK-NEXT:mov w12, w0
+; CHECK-NEXT:movaz { z0.d, z1.d }, za0h.d[w12, 0:1]
+; CHECK-NEXT:movaz { z2.d, z3.d }, za7h.d[w12, 0:1]
+; CHECK-NEXT:ret
+ %res = call {, }
@llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 0, i32 %slice)
+ %res2 = call {, }
@llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 7, i32 %slice)
+ ret {, } %res
+}
+
+define {, }
@test_readz_hor_z16_bf16_x2(i32 %slice) {
+; CHECK-LABEL: test_readz_hor_z16_bf16_x2:
+; CHECK: // %bb.0:
+; CHECK-NEXT:mov w12, w0
+; CHECK-NEXT:movaz { z0.h, z1.h }, za0h.h[w12, 0:1]
+; CHECK-NEXT:movaz { z0.h, z1.h }, za1h.h[w12, 6:7]
+; CHECK-NEXT:ret
+ %res = call {, }
@llvm.aarch64.sme.readz.horiz.x2.nxv8bf16(i32 0, i32 %slice)
+ %slice.max = add i32 %slice, 6
+ %res2 = call {, }
@llvm.aarch64.sme.readz.horiz.x2.nxv8bf16(i32 1, i32 %slice.max)
+ ret {, } %res2
+}
+
+define {, }
@test_readz_hor_z16_f16_x2(i32 %slice) {
+; CHECK-LABEL: test_readz_hor_z16_f16_x2:
+; CHECK: // %bb.0:
+; CHECK-NEXT:mov w12, w0
+; CHECK-NEXT:movaz { z0.h, z1.h }, za0h.h[w12, 0:1]
+; CHECK-NEXT:movaz { z0.h, z1.h }, za1h.h[w12, 6:7]
+; CHECK-NEXT:ret
+ %res = call {, }
@llvm.aarch64.sme.readz.horiz.x2.nxv8f16(i32 0, i32 %slice)
+ %slice.max = add i32 %slice, 6
+ %res2 = call {, }
@llvm.aarch64.sme.readz.horiz.x2.nxv8f16(i32 1, i32 %slice.max)
+ ret {, } %res2
+}
+
+define {, }
@test_readz_hor_z32_f32_x2(i32 %slice) {
+; CHECK-LABEL: test_readz_hor_z32_f32_x2:
+; CHECK: // %bb.0:
+; CHECK-NEXT:mov w12, w0
+; CHECK-NEXT:movaz { z0.s, z1.s }, za0h.s[w12, 0:1]
Lukacma wrote:
I am using this as an example, but the comment is more general to whole
assembly. Looking at latest
[spec](https://aig.euhpc.arm.com/job/mrs-release-nightly-dpisa/lastSuccessfulBuild/artifact/output/ISA/v9Ap5-A/xml/release/package/ISA_A64_xml_dpisa-nightly/movaz_mz_za2.xml)
for the instruction it seems assembly should look like this:
`MOVAZ { .D-.D }, ZA.D[, {, VGx2}]
`
which is not what is produced currently. The `ZA` field has tile identification
info attached and we have .S instead of .D (Thought from reading spec this is
fine and only matters for dissasembly?). Is this an error in assembly
generation or am I missing smth here ?
https://github.com/llvm/llvm-project/pull/88710
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[clang] [llvm] [CLANG][LLVM][AArch64]SME2.1 intrinsics for MOVAZ tile to 2/4 vectors (PR #88710)
llvmbot wrote:
@llvm/pr-subscribers-llvm-ir
@llvm/pr-subscribers-backend-aarch64
Author: None (CarolineConcatto)
Changes
According to the specification in
ARM-software/acle#309 this adds the intrinsics
// Variants are also available for _za8_u8, _za16_s16, _za16_u16, // _za16_f16,
_za16_bf16, _za32_s32, _za32_u32, _za32_f32, // _za64_s64, _za64_u64 and
_za64_f64
svint8x2_t svreadz_hor_za8_s8_vg2(uint64_t tile, uint32_t slice)
__arm_streaming __arm_inout("za");
// Variants are also available for _za8_u8, _za16_s16, _za16_u16, // _za16_f16,
_za16_bf16, _za32_s32, _za32_u32, _za32_f32, // _za64_s64, _za64_u64 and
_za64_f64
svint8x4_t svreadz_hor_za8_s8_vg4(uint64_t tile, uint32_t slice)
__arm_streaming __arm_inout("za");
// Variants are also available for _za8_u8, _za16_s16, _za16_u16, // _za16_f16,
_za16_bf16, _za32_s32, _za32_u32, _za32_f32, // _za64_s64, _za64_u64 and
_za64_f64
svint8x2_t svreadz_ver_za8_s8_vg2(uint64_t tile, uint32_t slice)
__arm_streaming __arm_inout("za");
// Variants are also available for _za8_u8, _za16_s16, _za16_u16, // _za16_f16,
_za16_bf16, _za32_s32, _za32_u32, _za32_f32, // _za64_s64, _za64_u64 and
_za64_f64
svint8x4_t svreadz_ver_za8_s8_vg4(uint64_t tile, uint32_t slice)
__arm_streaming __arm_inout("za");
---
Patch is 175.61 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/88710.diff
9 Files Affected:
- (modified) clang/include/clang/Basic/arm_sme.td (+23)
- (added) clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c
(+1414)
- (modified) llvm/include/llvm/IR/IntrinsicsAArch64.td (+19-1)
- (modified) llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (+98-1)
- (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+49)
- (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.h (+3)
- (modified) llvm/lib/Target/AArch64/SMEInstrFormats.td (+27)
- (added) llvm/test/CodeGen/AArch64/sme2p1-intrinsics-movaz.ll (+457)
- (added) llvm/test/CodeGen/AArch64/sme2p1-intrinsics-movaz.s ()
``diff
diff --git a/clang/include/clang/Basic/arm_sme.td
b/clang/include/clang/Basic/arm_sme.td
index 1ac6d5170ea283..44bb32916d86bb 100644
--- a/clang/include/clang/Basic/arm_sme.td
+++ b/clang/include/clang/Basic/arm_sme.td
@@ -674,3 +674,26 @@ let TargetGuard = "sme2" in {
def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i",
"cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming,
IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
def SVLUTI4_LANE_ZT_X2 : Inst<"svluti4_lane_zt_{d}_x2", "2.di[i",
"cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x2", [IsStreaming,
IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>;
}
+
+multiclass ZAReadz ch> {
+ let TargetGuard = "sme2p1" in {
+def NAME # _H : SInst<"svreadz_hor_" # n_suffix # "_{d}_vg" # vg_num,
vg_num # "im", t,
+ MergeNone, i_prefix # "_horiz_x" # vg_num,
+ [IsStreaming, IsInOutZA], ch>;
+
+def NAME # _V : SInst<"svreadz_ver_" # n_suffix # "_{d}_vg" # vg_num,
vg_num # "im", t,
+ MergeNone, i_prefix # "_vert_x" #vg_num,
+ [IsStreaming, IsInOutZA], ch>;
+ }
+}
+
+defm SVREADZ_ZA8_X2 : ZAReadz<"za8", "2", "cUc", "aarch64_sme_readz",
[ImmCheck<0, ImmCheck0_0>]>;
+defm SVREADZ_ZA16_X2 : ZAReadz<"za16", "2", "sUshb", "aarch64_sme_readz",
[ImmCheck<0, ImmCheck0_1>]>;
+defm SVREADZ_ZA32_X2 : ZAReadz<"za32", "2", "iUif", "aarch64_sme_readz",
[ImmCheck<0, ImmCheck0_3>]>;
+defm SVREADZ_ZA64_X2 : ZAReadz<"za64", "2", "lUld", "aarch64_sme_readz",
[ImmCheck<0, ImmCheck0_7>]>;
+
+defm SVREADZ_ZA8_X4 : ZAReadz<"za8", "4", "cUc", "aarch64_sme_readz",
[ImmCheck<0, ImmCheck0_0>]>;
+defm SVREADZ_ZA16_X4 : ZAReadz<"za16", "4", "sUshb", "aarch64_sme_readz",
[ImmCheck<0, ImmCheck0_1>]>;
+defm SVREADZ_ZA32_X4 : ZAReadz<"za32", "4", "iUif", "aarch64_sme_readz",
[ImmCheck<0, ImmCheck0_3>]>;
+defm SVREADZ_ZA64_X4 : ZAReadz<"za64", "4", "lUld", "aarch64_sme_readz",
[ImmCheck<0, ImmCheck0_7>]>;
+
diff --git a/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c
b/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c
new file mode 100644
index 00..2b80c76e3d
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c
@@ -0,0 +1,1414 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 4
+ //RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2p1
-target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s |
opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2p1
-target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x
c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
-check-prefix=CPP-CHECK
+// RUN: %clang_cc1
