[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/94578
>From 57c914eaefa7e59aa51a2b1e730fe1b7d6d10e57 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Thu, 6 Jun 2024 13:48:34 +0800
Subject: [PATCH 1/4] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
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Created using spr 1.3.6-beta.1
---
clang/include/clang/Basic/BuiltinsRISCV.td| 18 ++
clang/lib/CodeGen/CGBuiltin.cpp | 22 ++
clang/lib/Headers/CMakeLists.txt | 1 +
clang/lib/Headers/riscv_atomics.h | 36 +++
clang/lib/Sema/SemaRISCV.cpp | 10 +-
.../RISCV/atomics-intrinsics/zalrsc-error.c | 13 +
.../CodeGen/RISCV/atomics-intrinsics/zalrsc.c | 222 ++
.../CodeGen/RISCV/atomics-intrinsics/zawrs.c | 42
llvm/include/llvm/IR/IntrinsicsRISCV.td | 32 +++
llvm/lib/Target/RISCV/RISCVInstrInfoA.td | 25 ++
llvm/lib/Target/RISCV/RISCVInstrInfoZa.td | 5 +-
llvm/test/CodeGen/RISCV/zalrsc-rv32.ll| 74 ++
llvm/test/CodeGen/RISCV/zalrsc-rv64.ll| 74 ++
llvm/test/CodeGen/RISCV/zawrs.ll | 33 +++
14 files changed, 605 insertions(+), 2 deletions(-)
create mode 100644 clang/lib/Headers/riscv_atomics.h
create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc-error.c
create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zalrsc.c
create mode 100644 clang/test/CodeGen/RISCV/atomics-intrinsics/zawrs.c
create mode 100644 llvm/test/CodeGen/RISCV/zalrsc-rv32.ll
create mode 100644 llvm/test/CodeGen/RISCV/zalrsc-rv64.ll
create mode 100644 llvm/test/CodeGen/RISCV/zawrs.ll
diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td
b/clang/include/clang/Basic/BuiltinsRISCV.td
index 4cc89a8a9d8af..458c755179417 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCV.td
@@ -146,3 +146,21 @@ let Features = "zihintntl", Attributes =
[CustomTypeChecking] in {
def ntl_load : RISCVBuiltin<"void(...)">;
def ntl_store : RISCVBuiltin<"void(...)">;
} // Features = "zihintntl", Attributes = [CustomTypeChecking]
+
+//===--===//
+// Zawrs extension.
+//===--===//
+let Features = "zawrs" in {
+def wrs_nto : RISCVBuiltin<"void()">;
+def wrs_sto : RISCVBuiltin<"void()">;
+} // Features = "zawrs"
+
+//===--===//
+// Zalrsc extension.
+//===--===//
+let Features = "zalrsc" in {
+def lr_w : RISCVBuiltin<"int(int *, _Constant unsigned int)">;
+def lr_d : RISCVBuiltin<"int64_t(int64_t *, _Constant unsigned int)">;
+def sc_w : RISCVBuiltin<"int(int, int *, _Constant unsigned int)">;
+def sc_d : RISCVBuiltin<"int64_t(int64_t, int64_t *, _Constant unsigned int)">;
+} // Features = "zalrsc"
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 37d0c478e0330..db48c69e10c86 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -21769,6 +21769,28 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned
BuiltinID,
ID = Intrinsic::riscv_sm3p1;
break;
+ // Zawrs
+ case RISCV::BI__builtin_riscv_wrs_nto:
+ID = Intrinsic::riscv_wrs_nto;
+break;
+ case RISCV::BI__builtin_riscv_wrs_sto:
+ID = Intrinsic::riscv_wrs_sto;
+break;
+
+ // Zalrsc
+ case RISCV::BI__builtin_riscv_lr_w:
+ID = Intrinsic::riscv_lr_w;
+break;
+ case RISCV::BI__builtin_riscv_lr_d:
+ID = Intrinsic::riscv_lr_d;
+break;
+ case RISCV::BI__builtin_riscv_sc_w:
+ID = Intrinsic::riscv_sc_w;
+break;
+ case RISCV::BI__builtin_riscv_sc_d:
+ID = Intrinsic::riscv_sc_d;
+break;
+
// Zihintntl
case RISCV::BI__builtin_riscv_ntl_load: {
llvm::Type *ResTy = ConvertType(E->getType());
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index d3090e488306f..cf2fbf1893772 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -118,6 +118,7 @@ set(ppc_htm_files
)
set(riscv_files
+ riscv_atomics.h
riscv_bitmanip.h
riscv_crypto.h
riscv_ntlh.h
diff --git a/clang/lib/Headers/riscv_atomics.h
b/clang/lib/Headers/riscv_atomics.h
new file mode 100644
index 0..35db57fe36131
--- /dev/null
+++ b/clang/lib/Headers/riscv_atomics.h
@@ -0,0 +1,36 @@
+/*=== riscv_atomics.h - RISC-V atomics intrinsics --===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===--
[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)
https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/94578 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)
efriedma-quic wrote: lr/sc builtins are extremely fragile: there's no reasonable way for the compiler to guarantee that the sc is placed in such a way that it will eventually succeed. (The equivalent intrinsics do exist on ARM, but ARM has significantly stronger guarantees here. Even then, it's not completely reliable.) https://github.com/llvm/llvm-project/pull/94578 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)
wangpc-pp wrote: > lr/sc builtins are extremely fragile: there's no reasonable way for the > compiler to guarantee that the sc is placed in such a way that it will > eventually succeed. I think the user should have enough knowledges about lr/sc to make the logic reasonable. If we don't provide these intrinsics, the user who wants to implement custom locks will use inline assemly instead. > (The equivalent intrinsics do exist on ARM, but ARM has significantly > stronger guarantees here. Even then, it's not completely reliable.) I don't know much about there intrinsics on ARM, what are the `stronger guarantees`? https://github.com/llvm/llvm-project/pull/94578 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)
jrtc27 wrote: > > lr/sc builtins are extremely fragile: there's no reasonable way for the > > compiler to guarantee that the sc is placed in such a way that it will > > eventually succeed. > > I think the user should have enough knowledges about lr/sc to make the logic > reasonable. It's not about knowledge, it's that they are basically impossible for the compiler to actually guarantee they'll work at all. > If we don't provide these intrinsics, the user who wants to implement custom > locks will use inline assemly instead. Good, because other than using C11-style atomics (or Itanium-style __sync builtins), that's the right thing to do. https://github.com/llvm/llvm-project/pull/94578 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)
wangpc-pp wrote: If we are talking about the necessariness of adding these intrinsics, please refer to the ARM implementations in DPDK (https://github.com/DPDK/dpdk/blob/76cef1af8bdaeaf67a5c4ca5df3f221df994dc46/lib/eal/arm/include/rte_pause_64.h).We want to use https://github.com/llvm/llvm-project/pull/94578 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)
jrtc27 wrote: > If we are talking about the necessariness of adding these intrinsics, please > refer to the ARM implementations in DPDK > (https://github.com/DPDK/dpdk/blob/76cef1af8bdaeaf67a5c4ca5df3f221df994dc46/lib/eal/arm/include/rte_pause_64.h). > > We want to use Zawrs&Zalrsc instructions to implement these on RISCV. Then write the loops in assembly. Really, it's not hard to do, and it's the only real way to guarantee it'll actually work the way you think it does. Compilers are free to insert whatever stack spills and reloads they want in between your inline assembly blocks or intrinsic calls, which can wreak havoc with load reservations if you're expecting them to be untouched in between. C is just not the right language to be modelling that kind of thing in, assembly is. https://github.com/llvm/llvm-project/pull/94578 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)
topperc wrote: > Compilers are free to insert whatever stack spills and reloads they want in > between your inline assembly blocks or intrinsic calls Especially with -O0. https://github.com/llvm/llvm-project/pull/94578 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)
efriedma-quic wrote: > I don't know much about there intrinsics on ARM, what are the stronger > guarantees? The Arm specifies that there's a memory reservation, and you can write whatever operations you want as long as you don't break that reservation. And the reservation is usually only a few bytes. RISC-V specifically only guarantees behavior for sequences of integer instructions. https://github.com/llvm/llvm-project/pull/94578 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)
asb wrote: My understanding from the sync-up call just now is you're planning to drop lr/sc intrinsics due to the concerns listed in this thread (which I share), but will keep pushing the zawrs intrinsics. https://github.com/llvm/llvm-project/pull/94578 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)
https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/94578 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
