[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
FreddyLeaf wrote: Sorry, I was OOO, thanks for the fix! https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
banach-space wrote: Should be fixed by https://github.com/llvm/llvm-project/pull/93794 https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
RKSimon wrote: @FreddyLeaf This is corrupting git checkouts on windows - please can you revert ? https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
banach-space wrote: Hi, thanks for this contribution. Sadly, it messes up my local checkout on MacOS (which is insensitive when it comes to files names). These files are problematic: * "asm-constraint-jR.ll" and "asm-constraint-jr.ll" Please, could you rename them so that they are not identical on case-insensitive systems? https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
https://github.com/FreddyLeaf closed https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
https://github.com/KanRobert approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 01/13] [X86] Support EGPR for inline assembly.
"jR": explictly enables EGPR
"r": enables/disables EGPR w/wo -mapx-inline-asm-use-gpr32
-mapx-inline-asm-use-gpr32 will also define a new Macro:
__APX_INLINE_ASM_USE_GPR32__
---
clang/include/clang/Driver/Options.td | 2 +
clang/lib/Basic/Targets/X86.cpp | 26 +
clang/lib/Basic/Targets/X86.h | 1 +
clang/lib/Driver/ToolChains/Arch/X86.cpp | 2 +
.../Driver/x86-apx-inline-asm-use-gpr32.cpp | 3 +
clang/test/Preprocessor/x86_target_features.c | 3 +
llvm/lib/Target/X86/X86.td| 3 +
llvm/lib/Target/X86/X86ISelLowering.cpp | 57 +--
.../CodeGen/X86/inline-asm-jR-constraint.ll | 19 +++
.../CodeGen/X86/inline-asm-r-constraint.ll| 16 ++
10 files changed, 127 insertions(+), 5 deletions(-)
create mode 100644 clang/test/Driver/x86-apx-inline-asm-use-gpr32.cpp
create mode 100644 llvm/test/CodeGen/X86/inline-asm-jR-constraint.ll
create mode 100644 llvm/test/CodeGen/X86/inline-asm-r-constraint.ll
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 73a2518480e9b..20a7c482bbf06 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -6281,6 +6281,8 @@ def mno_apx_features_EQ : CommaJoined<["-"],
"mno-apx-features=">, Group, Alias,
AliasArgs<["egpr","push2pop2","ppx", "ndd"]>;
def mno_apxf : Flag<["-"], "mno-apxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd"]>;
+def mapx_inline_asm_use_gpr32 : Flag<["-"], "mapx-inline-asm-use-gpr32">,
Group,
+HelpText<"Enable use of GPR32 in inline
assembly for APX">;
} // let Flags = [TargetSpecific]
// VE feature flags
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 67e2126cf766b..9e61b6e6d6441 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
+ HasInlineAsmUseGPR32 = true;
} else if (Feature == "+push2pop2") {
HasPush2Pop2 = true;
} else if (Feature == "+ppx") {
@@ -974,6 +976,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
// Condition here is aligned with the feature set of mapxf in Options.td
if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD)
Builder.defineMacro("__APX_F__");
+ if (HasInlineAsmUseGPR32)
+Builder.defineMacro("__APX_INLINE_ASM_USE_GPR32__");
// Each case falls through to the previous one here.
switch (SSELevel) {
@@ -1493,6 +1497,15 @@ bool X86TargetInfo::validateAsmConstraint(
case 'C': // SSE floating point constant.
case 'G': // x87 floating point constant.
return true;
+ case 'j':
+Name++;
+switch (*Name) {
+default:
+ return false;
+case 'R':
+ Info.setAllowsRegister();
+ return true;
+}
case '@':
// CC condition changes.
if (auto Len = matchAsmCCConstraint(Name)) {
@@ -1764,6 +1777,19 @@ std::string X86TargetInfo::convertConstraint(const char
*&Constraint) const {
// to the next constraint.
return std::string("^") + std::string(Constraint++, 2);
}
+ case 'j':
+switch (Constraint[1]) {
+default:
+ // Break from inner switch and fall through (copy single char),
+ // continue parsing after copying the current constraint into
+ // the return string.
+ break;
+case 'R':
+ // "^" hints llvm that this is a 2 letter constraint.
+ // "Constraint++" is used to promote the string iterator
+ // to the next constraint.
+ return std::string("^") + std::string(Constraint++, 2);
+}
[[fallthrough]];
default:
return std::string(1, *Constraint);
diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h
index c14e4d5f433d8..69c68ee80f3ba 100644
--- a/clang/lib/Basic/Targets/X86.h
+++ b/clang/lib/Basic/Targets/X86.h
@@ -174,6 +174,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public
TargetInfo {
bool HasNDD = false;
bool HasCCMP = false;
bool HasCF = false;
+ bool HasInlineAsmUseGPR32 = false;
protected:
llvm::X86::CPUKind CPU = llvm::X86::CK_None;
diff --git a/clang/lib/Driver/ToolChains/Arch/X86.cpp
b/clang/lib/Driver/ToolChains/Arch/X86.cpp
index 53e26a9f8e229..085ff4824a9b0 100644
--- a/clang/lib/Driver/ToolChains/Arch/X86.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/X86.cpp
@@ -309,4 +309,6 @@ void x86::getX86TargetFeatures(const Driver &D, const
llvm::Triple &Triple,
Features.push_back("+prefer-no-gat
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -1,21 +1,27 @@ ; Check r16-r31 can not be used with 'q','r','l' constraint for backward compatibility. -; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 | FileCheck %s --check-prefix=ERR FreddyLeaf wrote: [e752556](https://github.com/llvm/llvm-project/pull/92338/commits/e752556c06ac25d905c6e642bdcb5e9244db5da3) https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -57999,13 +58020,25 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
if (Subtarget.is64Bit()) {
if (VT == MVT::i8 || VT == MVT::i1)
- return std::make_pair(0U, &X86::GR8_NOREX2RegClass);
+ return std::make_pair(0U, Subtarget.hasEGPR() &&
+Subtarget.useInlineAsmGPR32()
FreddyLeaf wrote:
[e752556](https://github.com/llvm/llvm-project/pull/92338/commits/e752556c06ac25d905c6e642bdcb5e9244db5da3)
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
FreddyLeaf wrote: [e752556](https://github.com/llvm/llvm-project/pull/92338/commits/e752556c06ac25d905c6e642bdcb5e9244db5da3) https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
FreddyLeaf wrote: [e752556](https://github.com/llvm/llvm-project/pull/92338/commits/e752556c06ac25d905c6e642bdcb5e9244db5da3) https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -0,0 +1,25 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: not llc -mtriple=x86_64 < %s | FileCheck %s +; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s FreddyLeaf wrote: [e752556](https://github.com/llvm/llvm-project/pull/92338/commits/e752556c06ac25d905c6e642bdcb5e9244db5da3) https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 01/13] [X86] Support EGPR for inline assembly.
"jR": explictly enables EGPR
"r": enables/disables EGPR w/wo -mapx-inline-asm-use-gpr32
-mapx-inline-asm-use-gpr32 will also define a new Macro:
__APX_INLINE_ASM_USE_GPR32__
---
clang/include/clang/Driver/Options.td | 2 +
clang/lib/Basic/Targets/X86.cpp | 26 +
clang/lib/Basic/Targets/X86.h | 1 +
clang/lib/Driver/ToolChains/Arch/X86.cpp | 2 +
.../Driver/x86-apx-inline-asm-use-gpr32.cpp | 3 +
clang/test/Preprocessor/x86_target_features.c | 3 +
llvm/lib/Target/X86/X86.td| 3 +
llvm/lib/Target/X86/X86ISelLowering.cpp | 57 +--
.../CodeGen/X86/inline-asm-jR-constraint.ll | 19 +++
.../CodeGen/X86/inline-asm-r-constraint.ll| 16 ++
10 files changed, 127 insertions(+), 5 deletions(-)
create mode 100644 clang/test/Driver/x86-apx-inline-asm-use-gpr32.cpp
create mode 100644 llvm/test/CodeGen/X86/inline-asm-jR-constraint.ll
create mode 100644 llvm/test/CodeGen/X86/inline-asm-r-constraint.ll
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 73a2518480e9b..20a7c482bbf06 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -6281,6 +6281,8 @@ def mno_apx_features_EQ : CommaJoined<["-"],
"mno-apx-features=">, Group, Alias,
AliasArgs<["egpr","push2pop2","ppx", "ndd"]>;
def mno_apxf : Flag<["-"], "mno-apxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd"]>;
+def mapx_inline_asm_use_gpr32 : Flag<["-"], "mapx-inline-asm-use-gpr32">,
Group,
+HelpText<"Enable use of GPR32 in inline
assembly for APX">;
} // let Flags = [TargetSpecific]
// VE feature flags
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 67e2126cf766b..9e61b6e6d6441 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
+ HasInlineAsmUseGPR32 = true;
} else if (Feature == "+push2pop2") {
HasPush2Pop2 = true;
} else if (Feature == "+ppx") {
@@ -974,6 +976,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
// Condition here is aligned with the feature set of mapxf in Options.td
if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD)
Builder.defineMacro("__APX_F__");
+ if (HasInlineAsmUseGPR32)
+Builder.defineMacro("__APX_INLINE_ASM_USE_GPR32__");
// Each case falls through to the previous one here.
switch (SSELevel) {
@@ -1493,6 +1497,15 @@ bool X86TargetInfo::validateAsmConstraint(
case 'C': // SSE floating point constant.
case 'G': // x87 floating point constant.
return true;
+ case 'j':
+Name++;
+switch (*Name) {
+default:
+ return false;
+case 'R':
+ Info.setAllowsRegister();
+ return true;
+}
case '@':
// CC condition changes.
if (auto Len = matchAsmCCConstraint(Name)) {
@@ -1764,6 +1777,19 @@ std::string X86TargetInfo::convertConstraint(const char
*&Constraint) const {
// to the next constraint.
return std::string("^") + std::string(Constraint++, 2);
}
+ case 'j':
+switch (Constraint[1]) {
+default:
+ // Break from inner switch and fall through (copy single char),
+ // continue parsing after copying the current constraint into
+ // the return string.
+ break;
+case 'R':
+ // "^" hints llvm that this is a 2 letter constraint.
+ // "Constraint++" is used to promote the string iterator
+ // to the next constraint.
+ return std::string("^") + std::string(Constraint++, 2);
+}
[[fallthrough]];
default:
return std::string(1, *Constraint);
diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h
index c14e4d5f433d8..69c68ee80f3ba 100644
--- a/clang/lib/Basic/Targets/X86.h
+++ b/clang/lib/Basic/Targets/X86.h
@@ -174,6 +174,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public
TargetInfo {
bool HasNDD = false;
bool HasCCMP = false;
bool HasCF = false;
+ bool HasInlineAsmUseGPR32 = false;
protected:
llvm::X86::CPUKind CPU = llvm::X86::CK_None;
diff --git a/clang/lib/Driver/ToolChains/Arch/X86.cpp
b/clang/lib/Driver/ToolChains/Arch/X86.cpp
index 53e26a9f8e229..085ff4824a9b0 100644
--- a/clang/lib/Driver/ToolChains/Arch/X86.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/X86.cpp
@@ -309,4 +309,6 @@ void x86::getX86TargetFeatures(const Driver &D, const
llvm::Triple &Triple,
Features.push_back("+prefer-no-gat
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -1,21 +1,27 @@ ; Check r16-r31 can not be used with 'q','r','l' constraint for backward compatibility. -; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 | FileCheck %s --check-prefix=ERR FreddyLeaf wrote: oh, I got your point. I messed with line 5 https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -0,0 +1,25 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: not llc -mtriple=x86_64 < %s | FileCheck %s +; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s FreddyLeaf wrote: I'll try. If so, we can refine llvm/test/CodeGen/X86/apx/asm-constraint.ll as well. https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -1,21 +1,27 @@ ; Check r16-r31 can not be used with 'q','r','l' constraint for backward compatibility. -; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 | FileCheck %s --check-prefix=ERR FreddyLeaf wrote: no, it didn't add `2>&1` https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
https://github.com/KanRobert edited https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
https://github.com/KanRobert edited https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -0,0 +1,25 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: not llc -mtriple=x86_64 < %s | FileCheck %s +; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s KanRobert wrote: You can use sth like ``` not llc -mtriple=x86_64 -mattr=+egpr < %s >%t1 2>%t2 FileCheck %s %t1 FileCheck %s %t2 --check-prefix=ERR ``` https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -1,21 +1,27 @@ ; Check r16-r31 can not be used with 'q','r','l' constraint for backward compatibility. -; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 | FileCheck %s --check-prefix=ERR KanRobert wrote: Really? IMO, line 4 is checking stderr too. https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
https://github.com/FreddyLeaf edited https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -1,21 +1,27 @@ ; Check r16-r31 can not be used with 'q','r','l' constraint for backward compatibility. -; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 | FileCheck %s --check-prefix=ERR FreddyLeaf wrote: line 2 is to check stderr, line 4 is to check stdout, I don't have a good way to check them both in on RUN line. Any idea? https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
KanRobert wrote: Nits: Rename this file to llvm/test/CodeGen/X86/apx/asm-constraint-jr.ll to align with existing one https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
KanRobert wrote: Nits: Rename this file to llvm/test/CodeGen/X86/apx/asm-constraint-jR.ll to align with existing one https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -57999,13 +58020,25 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
if (Subtarget.is64Bit()) {
if (VT == MVT::i8 || VT == MVT::i1)
- return std::make_pair(0U, &X86::GR8_NOREX2RegClass);
+ return std::make_pair(0U, Subtarget.hasEGPR() &&
+Subtarget.useInlineAsmGPR32()
KanRobert wrote:
Define a local helper for `Subtarget.hasEGPR() &&
Subtarget.useInlineAsmGPR32()`?
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -1,21 +1,27 @@ ; Check r16-r31 can not be used with 'q','r','l' constraint for backward compatibility. -; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 | FileCheck %s --check-prefix=ERR KanRobert wrote: Is line 2 same as line 4? If so, remove line 2. https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 01/12] [X86] Support EGPR for inline assembly.
"jR": explictly enables EGPR
"r": enables/disables EGPR w/wo -mapx-inline-asm-use-gpr32
-mapx-inline-asm-use-gpr32 will also define a new Macro:
__APX_INLINE_ASM_USE_GPR32__
---
clang/include/clang/Driver/Options.td | 2 +
clang/lib/Basic/Targets/X86.cpp | 26 +
clang/lib/Basic/Targets/X86.h | 1 +
clang/lib/Driver/ToolChains/Arch/X86.cpp | 2 +
.../Driver/x86-apx-inline-asm-use-gpr32.cpp | 3 +
clang/test/Preprocessor/x86_target_features.c | 3 +
llvm/lib/Target/X86/X86.td| 3 +
llvm/lib/Target/X86/X86ISelLowering.cpp | 57 +--
.../CodeGen/X86/inline-asm-jR-constraint.ll | 19 +++
.../CodeGen/X86/inline-asm-r-constraint.ll| 16 ++
10 files changed, 127 insertions(+), 5 deletions(-)
create mode 100644 clang/test/Driver/x86-apx-inline-asm-use-gpr32.cpp
create mode 100644 llvm/test/CodeGen/X86/inline-asm-jR-constraint.ll
create mode 100644 llvm/test/CodeGen/X86/inline-asm-r-constraint.ll
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 73a2518480e9b..20a7c482bbf06 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -6281,6 +6281,8 @@ def mno_apx_features_EQ : CommaJoined<["-"],
"mno-apx-features=">, Group, Alias,
AliasArgs<["egpr","push2pop2","ppx", "ndd"]>;
def mno_apxf : Flag<["-"], "mno-apxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd"]>;
+def mapx_inline_asm_use_gpr32 : Flag<["-"], "mapx-inline-asm-use-gpr32">,
Group,
+HelpText<"Enable use of GPR32 in inline
assembly for APX">;
} // let Flags = [TargetSpecific]
// VE feature flags
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 67e2126cf766b..9e61b6e6d6441 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
+ HasInlineAsmUseGPR32 = true;
} else if (Feature == "+push2pop2") {
HasPush2Pop2 = true;
} else if (Feature == "+ppx") {
@@ -974,6 +976,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
// Condition here is aligned with the feature set of mapxf in Options.td
if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD)
Builder.defineMacro("__APX_F__");
+ if (HasInlineAsmUseGPR32)
+Builder.defineMacro("__APX_INLINE_ASM_USE_GPR32__");
// Each case falls through to the previous one here.
switch (SSELevel) {
@@ -1493,6 +1497,15 @@ bool X86TargetInfo::validateAsmConstraint(
case 'C': // SSE floating point constant.
case 'G': // x87 floating point constant.
return true;
+ case 'j':
+Name++;
+switch (*Name) {
+default:
+ return false;
+case 'R':
+ Info.setAllowsRegister();
+ return true;
+}
case '@':
// CC condition changes.
if (auto Len = matchAsmCCConstraint(Name)) {
@@ -1764,6 +1777,19 @@ std::string X86TargetInfo::convertConstraint(const char
*&Constraint) const {
// to the next constraint.
return std::string("^") + std::string(Constraint++, 2);
}
+ case 'j':
+switch (Constraint[1]) {
+default:
+ // Break from inner switch and fall through (copy single char),
+ // continue parsing after copying the current constraint into
+ // the return string.
+ break;
+case 'R':
+ // "^" hints llvm that this is a 2 letter constraint.
+ // "Constraint++" is used to promote the string iterator
+ // to the next constraint.
+ return std::string("^") + std::string(Constraint++, 2);
+}
[[fallthrough]];
default:
return std::string(1, *Constraint);
diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h
index c14e4d5f433d8..69c68ee80f3ba 100644
--- a/clang/lib/Basic/Targets/X86.h
+++ b/clang/lib/Basic/Targets/X86.h
@@ -174,6 +174,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public
TargetInfo {
bool HasNDD = false;
bool HasCCMP = false;
bool HasCF = false;
+ bool HasInlineAsmUseGPR32 = false;
protected:
llvm::X86::CPUKind CPU = llvm::X86::CK_None;
diff --git a/clang/lib/Driver/ToolChains/Arch/X86.cpp
b/clang/lib/Driver/ToolChains/Arch/X86.cpp
index 53e26a9f8e229..085ff4824a9b0 100644
--- a/clang/lib/Driver/ToolChains/Arch/X86.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/X86.cpp
@@ -309,4 +309,6 @@ void x86::getX86TargetFeatures(const Driver &D, const
llvm::Triple &Triple,
Features.push_back("+prefer-no-gat
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -0,0 +1,16 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR +; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s +; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-asm-use-gpr32 < %s | FileCheck %s FreddyLeaf wrote: 81f58b6 https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
FreddyLeaf wrote: 81f58b6, pls review if I understand correctly. https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
FreddyLeaf wrote: 81f58b6 https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -5394,10 +5394,12 @@ X86: - ``Z``: An immediate 32-bit unsigned integer. - ``q``: An 8, 16, 32, or 64-bit register which can be accessed as an 8-bit ``l`` integer register. On X86-32, this is the ``a``, ``b``, ``c``, and ``d`` - registers, and on X86-64, it is all of the integer registers. + registers, and on X86-64, it is all of the integer registers. When feature + `egpr` and `inline-asm-use-gpr32` are both on, they will be extended to EGPR. - ``Q``: An 8, 16, 32, or 64-bit register which can be accessed as an 8-bit ``h`` integer register. This is the ``a``, ``b``, ``c``, and ``d`` registers. -- ``r`` or ``l``: An 8, 16, 32, or 64-bit integer register. +- ``r`` or ``l``: An 8, 16, 32, or 64-bit integer register. When feature + `egpr` and `inline-asm-use-gpr32` are both on, they will be extended to EGPR. FreddyLeaf wrote: 81f58b6 https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -5394,10 +5394,12 @@ X86: - ``Z``: An immediate 32-bit unsigned integer. - ``q``: An 8, 16, 32, or 64-bit register which can be accessed as an 8-bit ``l`` integer register. On X86-32, this is the ``a``, ``b``, ``c``, and ``d`` - registers, and on X86-64, it is all of the integer registers. + registers, and on X86-64, it is all of the integer registers. When feature + `egpr` and `inline-asm-use-gpr32` are both on, they will be extended to EGPR. FreddyLeaf wrote: 81f58b6 https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 01/11] [X86] Support EGPR for inline assembly.
"jR": explictly enables EGPR
"r": enables/disables EGPR w/wo -mapx-inline-asm-use-gpr32
-mapx-inline-asm-use-gpr32 will also define a new Macro:
__APX_INLINE_ASM_USE_GPR32__
---
clang/include/clang/Driver/Options.td | 2 +
clang/lib/Basic/Targets/X86.cpp | 26 +
clang/lib/Basic/Targets/X86.h | 1 +
clang/lib/Driver/ToolChains/Arch/X86.cpp | 2 +
.../Driver/x86-apx-inline-asm-use-gpr32.cpp | 3 +
clang/test/Preprocessor/x86_target_features.c | 3 +
llvm/lib/Target/X86/X86.td| 3 +
llvm/lib/Target/X86/X86ISelLowering.cpp | 57 +--
.../CodeGen/X86/inline-asm-jR-constraint.ll | 19 +++
.../CodeGen/X86/inline-asm-r-constraint.ll| 16 ++
10 files changed, 127 insertions(+), 5 deletions(-)
create mode 100644 clang/test/Driver/x86-apx-inline-asm-use-gpr32.cpp
create mode 100644 llvm/test/CodeGen/X86/inline-asm-jR-constraint.ll
create mode 100644 llvm/test/CodeGen/X86/inline-asm-r-constraint.ll
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 73a2518480e9b..20a7c482bbf06 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -6281,6 +6281,8 @@ def mno_apx_features_EQ : CommaJoined<["-"],
"mno-apx-features=">, Group, Alias,
AliasArgs<["egpr","push2pop2","ppx", "ndd"]>;
def mno_apxf : Flag<["-"], "mno-apxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd"]>;
+def mapx_inline_asm_use_gpr32 : Flag<["-"], "mapx-inline-asm-use-gpr32">,
Group,
+HelpText<"Enable use of GPR32 in inline
assembly for APX">;
} // let Flags = [TargetSpecific]
// VE feature flags
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 67e2126cf766b..9e61b6e6d6441 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
+ HasInlineAsmUseGPR32 = true;
} else if (Feature == "+push2pop2") {
HasPush2Pop2 = true;
} else if (Feature == "+ppx") {
@@ -974,6 +976,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
// Condition here is aligned with the feature set of mapxf in Options.td
if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD)
Builder.defineMacro("__APX_F__");
+ if (HasInlineAsmUseGPR32)
+Builder.defineMacro("__APX_INLINE_ASM_USE_GPR32__");
// Each case falls through to the previous one here.
switch (SSELevel) {
@@ -1493,6 +1497,15 @@ bool X86TargetInfo::validateAsmConstraint(
case 'C': // SSE floating point constant.
case 'G': // x87 floating point constant.
return true;
+ case 'j':
+Name++;
+switch (*Name) {
+default:
+ return false;
+case 'R':
+ Info.setAllowsRegister();
+ return true;
+}
case '@':
// CC condition changes.
if (auto Len = matchAsmCCConstraint(Name)) {
@@ -1764,6 +1777,19 @@ std::string X86TargetInfo::convertConstraint(const char
*&Constraint) const {
// to the next constraint.
return std::string("^") + std::string(Constraint++, 2);
}
+ case 'j':
+switch (Constraint[1]) {
+default:
+ // Break from inner switch and fall through (copy single char),
+ // continue parsing after copying the current constraint into
+ // the return string.
+ break;
+case 'R':
+ // "^" hints llvm that this is a 2 letter constraint.
+ // "Constraint++" is used to promote the string iterator
+ // to the next constraint.
+ return std::string("^") + std::string(Constraint++, 2);
+}
[[fallthrough]];
default:
return std::string(1, *Constraint);
diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h
index c14e4d5f433d8..69c68ee80f3ba 100644
--- a/clang/lib/Basic/Targets/X86.h
+++ b/clang/lib/Basic/Targets/X86.h
@@ -174,6 +174,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public
TargetInfo {
bool HasNDD = false;
bool HasCCMP = false;
bool HasCF = false;
+ bool HasInlineAsmUseGPR32 = false;
protected:
llvm::X86::CPUKind CPU = llvm::X86::CK_None;
diff --git a/clang/lib/Driver/ToolChains/Arch/X86.cpp
b/clang/lib/Driver/ToolChains/Arch/X86.cpp
index 53e26a9f8e229..085ff4824a9b0 100644
--- a/clang/lib/Driver/ToolChains/Arch/X86.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/X86.cpp
@@ -309,4 +309,6 @@ void x86::getX86TargetFeatures(const Driver &D, const
llvm::Triple &Triple,
Features.push_back("+prefer-no-gat
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -57581,6 +57581,14 @@ X86TargetLowering::getConstraintType(StringRef
Constraint) const {
case '2':
return C_RegisterClass;
}
+case 'j':
+ switch (Constraint[1]) {
+ default:
+break;
+ case 'r':
+ case 'R':
+return C_RegisterClass;
FreddyLeaf wrote:
relate assertion:
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:9938: void
llvm::SelectionDAGBuilder::visitInlineAsm(const llvm::CallBase&, const
llvm::BasicBlock*): Assertion `(OpIn
fo.ConstraintType == TargetLowering::C_RegisterClass || OpInfo.ConstraintType
== TargetLowering::C_Register) && "Unknown constraint type!"' failed.
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -57660,6 +57668,19 @@ X86TargetLowering::getSingleConstraintMatchWeight(
break;
}
break;
+ case 'j':
+if (StringRef(Constraint).size() != 2)
+ break;
+switch (Constraint[1]) {
+default:
+ return CW_Invalid;
+case 'r':
+case 'R':
+ if (CallOperandVal->getType()->isIntegerTy())
+Wt = CW_SpecificReg;
FreddyLeaf wrote:
ditto
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -57581,6 +57581,14 @@ X86TargetLowering::getConstraintType(StringRef
Constraint) const {
case '2':
return C_RegisterClass;
}
+case 'j':
+ switch (Constraint[1]) {
+ default:
+break;
+ case 'r':
+ case 'R':
+return C_RegisterClass;
FreddyLeaf wrote:
`r` is handled at TargetLowering::getConstraintType
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -0,0 +1,16 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR +; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s +; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-asm-use-gpr32 < %s | FileCheck %s KanRobert wrote: Add a new line for +inline-asm-use-gpr32 only https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
KanRobert wrote: Merge this into llvm/test/CodeGen/X86/apx/inline-asm-jr-constraint.ll You can add `not` at each run line. llc does not stop processing when encountering such kind of error. https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
KanRobert wrote: Remove this test and update llvm/test/CodeGen/X86/apx/asm-constraint.ll https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -57660,6 +57668,19 @@ X86TargetLowering::getSingleConstraintMatchWeight(
break;
}
break;
+ case 'j':
+if (StringRef(Constraint).size() != 2)
+ break;
+switch (Constraint[1]) {
+default:
+ return CW_Invalid;
+case 'r':
+case 'R':
+ if (CallOperandVal->getType()->isIntegerTy())
+Wt = CW_SpecificReg;
KanRobert wrote:
Same question here.
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -57581,6 +57581,14 @@ X86TargetLowering::getConstraintType(StringRef
Constraint) const {
case '2':
return C_RegisterClass;
}
+case 'j':
+ switch (Constraint[1]) {
+ default:
+break;
+ case 'r':
+ case 'R':
+return C_RegisterClass;
KanRobert wrote:
What's this used for? I can't find `r` in the switch-cases before this PR.
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -5394,10 +5394,12 @@ X86: - ``Z``: An immediate 32-bit unsigned integer. - ``q``: An 8, 16, 32, or 64-bit register which can be accessed as an 8-bit ``l`` integer register. On X86-32, this is the ``a``, ``b``, ``c``, and ``d`` - registers, and on X86-64, it is all of the integer registers. + registers, and on X86-64, it is all of the integer registers. When feature + `egpr` and `inline-asm-use-gpr32` are both on, they will be extended to EGPR. - ``Q``: An 8, 16, 32, or 64-bit register which can be accessed as an 8-bit ``h`` integer register. This is the ``a``, ``b``, ``c``, and ``d`` registers. -- ``r`` or ``l``: An 8, 16, 32, or 64-bit integer register. +- ``r`` or ``l``: An 8, 16, 32, or 64-bit integer register. When feature + `egpr` and `inline-asm-use-gpr32` are both on, they will be extended to EGPR. KanRobert wrote: ditto https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -5394,10 +5394,12 @@ X86: - ``Z``: An immediate 32-bit unsigned integer. - ``q``: An 8, 16, 32, or 64-bit register which can be accessed as an 8-bit ``l`` integer register. On X86-32, this is the ``a``, ``b``, ``c``, and ``d`` - registers, and on X86-64, it is all of the integer registers. + registers, and on X86-64, it is all of the integer registers. When feature + `egpr` and `inline-asm-use-gpr32` are both on, they will be extended to EGPR. KanRobert wrote: EGPR -> gp32 EGPR refers to r16-r31. https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -5418,6 +5418,8 @@ X86: operand will get allocated only to RAX -- if two 32-bit operands are needed, you're better off splitting it yourself, before passing it to the asm statement. +- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on. FreddyLeaf wrote: [fb6ba87](https://github.com/llvm/llvm-project/pull/92338/commits/fb6ba87b4f678df51d9e9e0807401f883bdbaced) https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 01/10] [X86] Support EGPR for inline assembly.
"jR": explictly enables EGPR
"r": enables/disables EGPR w/wo -mapx-inline-asm-use-gpr32
-mapx-inline-asm-use-gpr32 will also define a new Macro:
__APX_INLINE_ASM_USE_GPR32__
---
clang/include/clang/Driver/Options.td | 2 +
clang/lib/Basic/Targets/X86.cpp | 26 +
clang/lib/Basic/Targets/X86.h | 1 +
clang/lib/Driver/ToolChains/Arch/X86.cpp | 2 +
.../Driver/x86-apx-inline-asm-use-gpr32.cpp | 3 +
clang/test/Preprocessor/x86_target_features.c | 3 +
llvm/lib/Target/X86/X86.td| 3 +
llvm/lib/Target/X86/X86ISelLowering.cpp | 57 +--
.../CodeGen/X86/inline-asm-jR-constraint.ll | 19 +++
.../CodeGen/X86/inline-asm-r-constraint.ll| 16 ++
10 files changed, 127 insertions(+), 5 deletions(-)
create mode 100644 clang/test/Driver/x86-apx-inline-asm-use-gpr32.cpp
create mode 100644 llvm/test/CodeGen/X86/inline-asm-jR-constraint.ll
create mode 100644 llvm/test/CodeGen/X86/inline-asm-r-constraint.ll
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 73a2518480e9b..20a7c482bbf06 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -6281,6 +6281,8 @@ def mno_apx_features_EQ : CommaJoined<["-"],
"mno-apx-features=">, Group, Alias,
AliasArgs<["egpr","push2pop2","ppx", "ndd"]>;
def mno_apxf : Flag<["-"], "mno-apxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd"]>;
+def mapx_inline_asm_use_gpr32 : Flag<["-"], "mapx-inline-asm-use-gpr32">,
Group,
+HelpText<"Enable use of GPR32 in inline
assembly for APX">;
} // let Flags = [TargetSpecific]
// VE feature flags
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 67e2126cf766b..9e61b6e6d6441 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
+ HasInlineAsmUseGPR32 = true;
} else if (Feature == "+push2pop2") {
HasPush2Pop2 = true;
} else if (Feature == "+ppx") {
@@ -974,6 +976,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
// Condition here is aligned with the feature set of mapxf in Options.td
if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD)
Builder.defineMacro("__APX_F__");
+ if (HasInlineAsmUseGPR32)
+Builder.defineMacro("__APX_INLINE_ASM_USE_GPR32__");
// Each case falls through to the previous one here.
switch (SSELevel) {
@@ -1493,6 +1497,15 @@ bool X86TargetInfo::validateAsmConstraint(
case 'C': // SSE floating point constant.
case 'G': // x87 floating point constant.
return true;
+ case 'j':
+Name++;
+switch (*Name) {
+default:
+ return false;
+case 'R':
+ Info.setAllowsRegister();
+ return true;
+}
case '@':
// CC condition changes.
if (auto Len = matchAsmCCConstraint(Name)) {
@@ -1764,6 +1777,19 @@ std::string X86TargetInfo::convertConstraint(const char
*&Constraint) const {
// to the next constraint.
return std::string("^") + std::string(Constraint++, 2);
}
+ case 'j':
+switch (Constraint[1]) {
+default:
+ // Break from inner switch and fall through (copy single char),
+ // continue parsing after copying the current constraint into
+ // the return string.
+ break;
+case 'R':
+ // "^" hints llvm that this is a 2 letter constraint.
+ // "Constraint++" is used to promote the string iterator
+ // to the next constraint.
+ return std::string("^") + std::string(Constraint++, 2);
+}
[[fallthrough]];
default:
return std::string(1, *Constraint);
diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h
index c14e4d5f433d8..69c68ee80f3ba 100644
--- a/clang/lib/Basic/Targets/X86.h
+++ b/clang/lib/Basic/Targets/X86.h
@@ -174,6 +174,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public
TargetInfo {
bool HasNDD = false;
bool HasCCMP = false;
bool HasCF = false;
+ bool HasInlineAsmUseGPR32 = false;
protected:
llvm::X86::CPUKind CPU = llvm::X86::CK_None;
diff --git a/clang/lib/Driver/ToolChains/Arch/X86.cpp
b/clang/lib/Driver/ToolChains/Arch/X86.cpp
index 53e26a9f8e229..085ff4824a9b0 100644
--- a/clang/lib/Driver/ToolChains/Arch/X86.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/X86.cpp
@@ -309,4 +309,6 @@ void x86::getX86TargetFeatures(const Driver &D, const
llvm::Triple &Triple,
Features.push_back("+prefer-no-gat
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -5418,6 +5418,8 @@ X86: operand will get allocated only to RAX -- if two 32-bit operands are needed, you're better off splitting it yourself, before passing it to the asm statement. +- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on. + Otherwise, same as ``R``. FreddyLeaf wrote: [bf3a53c](https://github.com/llvm/llvm-project/pull/92338/commits/bf3a53c0b7fc1828572f771e4772d25062110dc0) extended jr, l, q https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -58024,15 +58043,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, case 'r': // GENERAL_REGS case 'l': // INDEX_REGS if (VT == MVT::i8 || VT == MVT::i1) -return std::make_pair(0U, &X86::GR8_NOREX2RegClass); +return std::make_pair(0U, Subtarget.useInlineAsmGPR32() + ? &X86::GR8_NOREX2RegClass + : &X86::GR8RegClass); if (VT == MVT::i16) -return std::make_pair(0U, &X86::GR16_NOREX2RegClass); +return std::make_pair(0U, Subtarget.useInlineAsmGPR32() + ? &X86::GR16_NOREX2RegClass + : &X86::GR16RegClass); if (VT == MVT::i32 || VT == MVT::f32 || (!VT.isVector() && !Subtarget.is64Bit())) -return std::make_pair(0U, &X86::GR32_NOREX2RegClass); +return std::make_pair(0U, Subtarget.useInlineAsmGPR32() FreddyLeaf wrote: addressed in [bf3a53c](https://github.com/llvm/llvm-project/pull/92338/commits/bf3a53c0b7fc1828572f771e4772d25062110dc0) https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -58255,6 +58281,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
}
break;
}
+ } else if (Constraint.size() == 2 && Constraint[0] == 'j') {
+switch (Constraint[1]) {
+default:
+ break;
+case 'R':
+ if (VT == MVT::i8 || VT == MVT::i1)
+return std::make_pair(0U, &X86::GR8RegClass);
+ if (VT == MVT::i16)
+return std::make_pair(0U, &X86::GR16RegClass);
+ if (VT == MVT::i32 || VT == MVT::f32 ||
+ (!VT.isVector() && !Subtarget.is64Bit()))
+return std::make_pair(0U, &X86::GR32RegClass);
FreddyLeaf wrote:
addressed in
[bf3a53c](https://github.com/llvm/llvm-project/pull/92338/commits/bf3a53c0b7fc1828572f771e4772d25062110dc0)
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-asm-use-gpr32 < %s | FileCheck
%s
+
+; ERR: error: inline assembly requires more registers than available
+
+define void @constraint_jR_test() nounwind "frame-pointer"="all" {
FreddyLeaf wrote:
it turns out relate to `rbp`, addressed in
[bf3a53c](https://github.com/llvm/llvm-project/pull/92338/commits/bf3a53c0b7fc1828572f771e4772d25062110dc0)
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s 2>&1 | FileCheck %s
--check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-asm-use-gpr32 < %s | FileCheck
%s
+
+; ERR: error: inline assembly requires more registers than available
+
+define void @constraint_r_test() nounwind "frame-pointer"="all" {
FreddyLeaf wrote:
addressed in
[bf3a53c](https://github.com/llvm/llvm-project/pull/92338/commits/bf3a53c0b7fc1828572f771e4772d25062110dc0)
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -0,0 +1,16 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: not llc -mtriple=x86_64 < %s 2>&1 | FileCheck %s --check-prefix=ERR +; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s 2>&1 | FileCheck %s --check-prefix=ERR +; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-asm-use-gpr32 < %s | FileCheck %s FreddyLeaf wrote: agree, extended `q` in [bf3a53c](https://github.com/llvm/llvm-project/pull/92338/commits/bf3a53c0b7fc1828572f771e4772d25062110dc0) https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
https://github.com/FreddyLeaf edited https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/9] [X86] Support EGPR for inline assembly.
"jR": explictly enables EGPR
"r": enables/disables EGPR w/wo -mapx-inline-asm-use-gpr32
-mapx-inline-asm-use-gpr32 will also define a new Macro:
__APX_INLINE_ASM_USE_GPR32__
---
clang/include/clang/Driver/Options.td | 2 +
clang/lib/Basic/Targets/X86.cpp | 26 +
clang/lib/Basic/Targets/X86.h | 1 +
clang/lib/Driver/ToolChains/Arch/X86.cpp | 2 +
.../Driver/x86-apx-inline-asm-use-gpr32.cpp | 3 +
clang/test/Preprocessor/x86_target_features.c | 3 +
llvm/lib/Target/X86/X86.td| 3 +
llvm/lib/Target/X86/X86ISelLowering.cpp | 57 +--
.../CodeGen/X86/inline-asm-jR-constraint.ll | 19 +++
.../CodeGen/X86/inline-asm-r-constraint.ll| 16 ++
10 files changed, 127 insertions(+), 5 deletions(-)
create mode 100644 clang/test/Driver/x86-apx-inline-asm-use-gpr32.cpp
create mode 100644 llvm/test/CodeGen/X86/inline-asm-jR-constraint.ll
create mode 100644 llvm/test/CodeGen/X86/inline-asm-r-constraint.ll
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 73a2518480e9b..20a7c482bbf06 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -6281,6 +6281,8 @@ def mno_apx_features_EQ : CommaJoined<["-"],
"mno-apx-features=">, Group, Alias,
AliasArgs<["egpr","push2pop2","ppx", "ndd"]>;
def mno_apxf : Flag<["-"], "mno-apxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd"]>;
+def mapx_inline_asm_use_gpr32 : Flag<["-"], "mapx-inline-asm-use-gpr32">,
Group,
+HelpText<"Enable use of GPR32 in inline
assembly for APX">;
} // let Flags = [TargetSpecific]
// VE feature flags
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 67e2126cf766b..9e61b6e6d6441 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
+ HasInlineAsmUseGPR32 = true;
} else if (Feature == "+push2pop2") {
HasPush2Pop2 = true;
} else if (Feature == "+ppx") {
@@ -974,6 +976,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
// Condition here is aligned with the feature set of mapxf in Options.td
if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD)
Builder.defineMacro("__APX_F__");
+ if (HasInlineAsmUseGPR32)
+Builder.defineMacro("__APX_INLINE_ASM_USE_GPR32__");
// Each case falls through to the previous one here.
switch (SSELevel) {
@@ -1493,6 +1497,15 @@ bool X86TargetInfo::validateAsmConstraint(
case 'C': // SSE floating point constant.
case 'G': // x87 floating point constant.
return true;
+ case 'j':
+Name++;
+switch (*Name) {
+default:
+ return false;
+case 'R':
+ Info.setAllowsRegister();
+ return true;
+}
case '@':
// CC condition changes.
if (auto Len = matchAsmCCConstraint(Name)) {
@@ -1764,6 +1777,19 @@ std::string X86TargetInfo::convertConstraint(const char
*&Constraint) const {
// to the next constraint.
return std::string("^") + std::string(Constraint++, 2);
}
+ case 'j':
+switch (Constraint[1]) {
+default:
+ // Break from inner switch and fall through (copy single char),
+ // continue parsing after copying the current constraint into
+ // the return string.
+ break;
+case 'R':
+ // "^" hints llvm that this is a 2 letter constraint.
+ // "Constraint++" is used to promote the string iterator
+ // to the next constraint.
+ return std::string("^") + std::string(Constraint++, 2);
+}
[[fallthrough]];
default:
return std::string(1, *Constraint);
diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h
index c14e4d5f433d8..69c68ee80f3ba 100644
--- a/clang/lib/Basic/Targets/X86.h
+++ b/clang/lib/Basic/Targets/X86.h
@@ -174,6 +174,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public
TargetInfo {
bool HasNDD = false;
bool HasCCMP = false;
bool HasCF = false;
+ bool HasInlineAsmUseGPR32 = false;
protected:
llvm::X86::CPUKind CPU = llvm::X86::CK_None;
diff --git a/clang/lib/Driver/ToolChains/Arch/X86.cpp
b/clang/lib/Driver/ToolChains/Arch/X86.cpp
index 53e26a9f8e229..085ff4824a9b0 100644
--- a/clang/lib/Driver/ToolChains/Arch/X86.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/X86.cpp
@@ -309,4 +309,6 @@ void x86::getX86TargetFeatures(const Driver &D, const
llvm::Triple &Triple,
Features.push_back("+prefer-no-gathe
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -58024,15 +58043,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, case 'r': // GENERAL_REGS case 'l': // INDEX_REGS if (VT == MVT::i8 || VT == MVT::i1) -return std::make_pair(0U, &X86::GR8_NOREX2RegClass); +return std::make_pair(0U, Subtarget.useInlineAsmGPR32() + ? &X86::GR8_NOREX2RegClass + : &X86::GR8RegClass); if (VT == MVT::i16) -return std::make_pair(0U, &X86::GR16_NOREX2RegClass); +return std::make_pair(0U, Subtarget.useInlineAsmGPR32() + ? &X86::GR16_NOREX2RegClass + : &X86::GR16RegClass); if (VT == MVT::i32 || VT == MVT::f32 || (!VT.isVector() && !Subtarget.is64Bit())) -return std::make_pair(0U, &X86::GR32_NOREX2RegClass); +return std::make_pair(0U, Subtarget.useInlineAsmGPR32() KanRobert wrote: The order should be reversed. Subtarget.useInlineAsmGPR32() ? GR32 : GR32_NOREX2 https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -58024,15 +58043,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, case 'r': // GENERAL_REGS case 'l': // INDEX_REGS if (VT == MVT::i8 || VT == MVT::i1) -return std::make_pair(0U, &X86::GR8_NOREX2RegClass); +return std::make_pair(0U, Subtarget.useInlineAsmGPR32() + ? &X86::GR8_NOREX2RegClass + : &X86::GR8RegClass); if (VT == MVT::i16) -return std::make_pair(0U, &X86::GR16_NOREX2RegClass); +return std::make_pair(0U, Subtarget.useInlineAsmGPR32() + ? &X86::GR16_NOREX2RegClass + : &X86::GR16RegClass); if (VT == MVT::i32 || VT == MVT::f32 || (!VT.isVector() && !Subtarget.is64Bit())) -return std::make_pair(0U, &X86::GR32_NOREX2RegClass); +return std::make_pair(0U, Subtarget.useInlineAsmGPR32() FreddyLeaf wrote: covered by getPreserverdRegister in RA. https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -5418,6 +5418,8 @@ X86: operand will get allocated only to RAX -- if two 32-bit operands are needed, you're better off splitting it yourself, before passing it to the asm statement. +- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on. + Otherwise, same as ``R``. FreddyLeaf wrote: > `r` is same as `R` for X86 IIUC. Sorry, wrong conclusion. I did bad experiment before, making me judge clang didn't clarify for 'R' and 'r' for X86. https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-asm-use-gpr32 < %s | FileCheck
%s
+
+; ERR: error: inline assembly requires more registers than available
+
+define void @constraint_jR_test() nounwind "frame-pointer"="all" {
KanRobert wrote:
How does it help? The error should not be related to frame pointer.
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -5418,6 +5418,8 @@ X86: operand will get allocated only to RAX -- if two 32-bit operands are needed, you're better off splitting it yourself, before passing it to the asm statement. +- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on. + Otherwise, same as ``R``. KanRobert wrote: I think no ``` - ``r`` or ``l``: An 8, 16, 32, or 64-bit integer register. - ``R``: An 8, 16, 32, or 64-bit "legacy" integer register -- one which has existed since i386, and can be accessed without the REX prefix. ``` `jR` seems weird by the existing conventions. We can change the design before we have the real users. https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -0,0 +1,16 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: not llc -mtriple=x86_64 < %s 2>&1 | FileCheck %s --check-prefix=ERR +; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s 2>&1 | FileCheck %s --check-prefix=ERR +; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-asm-use-gpr32 < %s | FileCheck %s KanRobert wrote: I find you also extend the `l` constraint. Should we have a test for it? And how about `q` https://github.com/llvm/llvm-project/pull/73529 ? I think it should be extended too. https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-asm-use-gpr32 < %s | FileCheck
%s
+
+; ERR: error: inline assembly requires more registers than available
+
+define void @constraint_jR_test() nounwind "frame-pointer"="all" {
FreddyLeaf wrote:
"frame-pointer"="all" helps throw the error here.
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -5418,6 +5418,8 @@ X86: operand will get allocated only to RAX -- if two 32-bit operands are needed, you're better off splitting it yourself, before passing it to the asm statement. +- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on. + Otherwise, same as ``R``. FreddyLeaf wrote: `r` is same as `R` for X86 IIUC. jR is to follow gcc https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s 2>&1 | FileCheck %s
--check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-asm-use-gpr32 < %s | FileCheck
%s
+
+; ERR: error: inline assembly requires more registers than available
+
+define void @constraint_r_test() nounwind "frame-pointer"="all" {
KanRobert wrote:
ditto
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-asm-use-gpr32 < %s | FileCheck
%s
+
+; ERR: error: inline assembly requires more registers than available
+
+define void @constraint_jR_test() nounwind "frame-pointer"="all" {
KanRobert wrote:
Remove "frame-pointer"="all"?
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -58255,6 +58281,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
}
break;
}
+ } else if (Constraint.size() == 2 && Constraint[0] == 'j') {
+switch (Constraint[1]) {
+default:
+ break;
+case 'R':
+ if (VT == MVT::i8 || VT == MVT::i1)
+return std::make_pair(0U, &X86::GR8RegClass);
+ if (VT == MVT::i16)
+return std::make_pair(0U, &X86::GR16RegClass);
+ if (VT == MVT::i32 || VT == MVT::f32 ||
+ (!VT.isVector() && !Subtarget.is64Bit()))
+return std::make_pair(0U, &X86::GR32RegClass);
KanRobert wrote:
The predicate is incorrect. EGPR is not supported in 32-bit mode.
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -58024,15 +58043,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, case 'r': // GENERAL_REGS case 'l': // INDEX_REGS if (VT == MVT::i8 || VT == MVT::i1) -return std::make_pair(0U, &X86::GR8_NOREX2RegClass); +return std::make_pair(0U, Subtarget.useInlineAsmGPR32() + ? &X86::GR8_NOREX2RegClass + : &X86::GR8RegClass); if (VT == MVT::i16) -return std::make_pair(0U, &X86::GR16_NOREX2RegClass); +return std::make_pair(0U, Subtarget.useInlineAsmGPR32() + ? &X86::GR16_NOREX2RegClass + : &X86::GR16RegClass); if (VT == MVT::i32 || VT == MVT::f32 || (!VT.isVector() && !Subtarget.is64Bit())) -return std::make_pair(0U, &X86::GR32_NOREX2RegClass); +return std::make_pair(0U, Subtarget.useInlineAsmGPR32() KanRobert wrote: Need to check hasEGPR() too https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
https://github.com/KanRobert deleted https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -346,6 +346,9 @@ def FeatureNF : SubtargetFeature<"nf", "HasNF", "true", "Support status flags update suppression">; def FeatureCF : SubtargetFeature<"cf", "HasCF", "true", "Support conditional faulting">; +def FeatureUseGPR32InInlineAsm +: SubtargetFeature<"inline-asm-use-gpr32", "UseInlineAsmGPR32", "false", + "Enable use of GPR32 in inline assembly for APX">; KanRobert wrote: Add `[FeatureEGPR]` https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -5418,6 +5418,8 @@ X86: operand will get allocated only to RAX -- if two 32-bit operands are needed, you're better off splitting it yourself, before passing it to the asm statement. +- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on. + Otherwise, same as ``R``. KanRobert wrote: I think it's same as `r` instead of `R` if egpr is off. Could I know why we design it as `jR` instead of `jr`? https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -5418,6 +5418,8 @@ X86: operand will get allocated only to RAX -- if two 32-bit operands are needed, you're better off splitting it yourself, before passing it to the asm statement. +- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on. KanRobert wrote: ```suggestion - ``jR``: An 8, 16, 32, or 64-bit gpr32 if EGPR is enabled. ``` The old statement is misleading b/c EGPR refers to R16-R31 only. https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
https://github.com/KanRobert edited https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
FreddyLeaf wrote: ping @KanRobert https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/8] [X86] Support EGPR for inline assembly.
"jR": explictly enables EGPR
"r": enables/disables EGPR w/wo -mapx-inline-asm-use-gpr32
-mapx-inline-asm-use-gpr32 will also define a new Macro:
__APX_INLINE_ASM_USE_GPR32__
---
clang/include/clang/Driver/Options.td | 2 +
clang/lib/Basic/Targets/X86.cpp | 26 +
clang/lib/Basic/Targets/X86.h | 1 +
clang/lib/Driver/ToolChains/Arch/X86.cpp | 2 +
.../Driver/x86-apx-inline-asm-use-gpr32.cpp | 3 +
clang/test/Preprocessor/x86_target_features.c | 3 +
llvm/lib/Target/X86/X86.td| 3 +
llvm/lib/Target/X86/X86ISelLowering.cpp | 57 +--
.../CodeGen/X86/inline-asm-jR-constraint.ll | 19 +++
.../CodeGen/X86/inline-asm-r-constraint.ll| 16 ++
10 files changed, 127 insertions(+), 5 deletions(-)
create mode 100644 clang/test/Driver/x86-apx-inline-asm-use-gpr32.cpp
create mode 100644 llvm/test/CodeGen/X86/inline-asm-jR-constraint.ll
create mode 100644 llvm/test/CodeGen/X86/inline-asm-r-constraint.ll
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 73a2518480e9b..20a7c482bbf06 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -6281,6 +6281,8 @@ def mno_apx_features_EQ : CommaJoined<["-"],
"mno-apx-features=">, Group, Alias,
AliasArgs<["egpr","push2pop2","ppx", "ndd"]>;
def mno_apxf : Flag<["-"], "mno-apxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd"]>;
+def mapx_inline_asm_use_gpr32 : Flag<["-"], "mapx-inline-asm-use-gpr32">,
Group,
+HelpText<"Enable use of GPR32 in inline
assembly for APX">;
} // let Flags = [TargetSpecific]
// VE feature flags
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 67e2126cf766b..9e61b6e6d6441 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
+ HasInlineAsmUseGPR32 = true;
} else if (Feature == "+push2pop2") {
HasPush2Pop2 = true;
} else if (Feature == "+ppx") {
@@ -974,6 +976,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
// Condition here is aligned with the feature set of mapxf in Options.td
if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD)
Builder.defineMacro("__APX_F__");
+ if (HasInlineAsmUseGPR32)
+Builder.defineMacro("__APX_INLINE_ASM_USE_GPR32__");
// Each case falls through to the previous one here.
switch (SSELevel) {
@@ -1493,6 +1497,15 @@ bool X86TargetInfo::validateAsmConstraint(
case 'C': // SSE floating point constant.
case 'G': // x87 floating point constant.
return true;
+ case 'j':
+Name++;
+switch (*Name) {
+default:
+ return false;
+case 'R':
+ Info.setAllowsRegister();
+ return true;
+}
case '@':
// CC condition changes.
if (auto Len = matchAsmCCConstraint(Name)) {
@@ -1764,6 +1777,19 @@ std::string X86TargetInfo::convertConstraint(const char
*&Constraint) const {
// to the next constraint.
return std::string("^") + std::string(Constraint++, 2);
}
+ case 'j':
+switch (Constraint[1]) {
+default:
+ // Break from inner switch and fall through (copy single char),
+ // continue parsing after copying the current constraint into
+ // the return string.
+ break;
+case 'R':
+ // "^" hints llvm that this is a 2 letter constraint.
+ // "Constraint++" is used to promote the string iterator
+ // to the next constraint.
+ return std::string("^") + std::string(Constraint++, 2);
+}
[[fallthrough]];
default:
return std::string(1, *Constraint);
diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h
index c14e4d5f433d8..69c68ee80f3ba 100644
--- a/clang/lib/Basic/Targets/X86.h
+++ b/clang/lib/Basic/Targets/X86.h
@@ -174,6 +174,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public
TargetInfo {
bool HasNDD = false;
bool HasCCMP = false;
bool HasCF = false;
+ bool HasInlineAsmUseGPR32 = false;
protected:
llvm::X86::CPUKind CPU = llvm::X86::CK_None;
diff --git a/clang/lib/Driver/ToolChains/Arch/X86.cpp
b/clang/lib/Driver/ToolChains/Arch/X86.cpp
index 53e26a9f8e229..085ff4824a9b0 100644
--- a/clang/lib/Driver/ToolChains/Arch/X86.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/X86.cpp
@@ -309,4 +309,6 @@ void x86::getX86TargetFeatures(const Driver &D, const
llvm::Triple &Triple,
Features.push_back("+prefer-no-gathe
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
https://github.com/nickdesaulniers approved this pull request. someone with more knowledge about EGPR should approve this as well, but I'm happy with the code style for the additions. https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -58016,15 +58035,27 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
break;
case 'r': // GENERAL_REGS
case 'l': // INDEX_REGS
+ if (Subtarget.useInlineAsmGPR32()) {
+if (VT == MVT::i8 || VT == MVT::i1)
+ return std::make_pair(0U, &X86::GR8_NOREX2RegClass);
+if (VT == MVT::i16)
+ return std::make_pair(0U, &X86::GR16_NOREX2RegClass);
+if (VT == MVT::i32 || VT == MVT::f32 ||
+(!VT.isVector() && !Subtarget.is64Bit()))
+ return std::make_pair(0U, &X86::GR32_NOREX2RegClass);
+if (VT != MVT::f80 && !VT.isVector())
+ return std::make_pair(0U, &X86::GR64_NOREX2RegClass);
+break;
+ }
if (VT == MVT::i8 || VT == MVT::i1)
-return std::make_pair(0U, &X86::GR8_NOREX2RegClass);
+return std::make_pair(0U, &X86::GR8RegClass);
if (VT == MVT::i16)
-return std::make_pair(0U, &X86::GR16_NOREX2RegClass);
+return std::make_pair(0U, &X86::GR16RegClass);
if (VT == MVT::i32 || VT == MVT::f32 ||
(!VT.isVector() && !Subtarget.is64Bit()))
-return std::make_pair(0U, &X86::GR32_NOREX2RegClass);
+return std::make_pair(0U, &X86::GR32RegClass);
if (VT != MVT::f80 && !VT.isVector())
-return std::make_pair(0U, &X86::GR64_NOREX2RegClass);
+return std::make_pair(0U, &X86::GR64RegClass);
FreddyLeaf wrote:
you're right. 4a9bf69673a2da02293aa3cf9cab54fbc98a89a2
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/8] [X86] Support EGPR for inline assembly.
"jR": explictly enables EGPR
"r": enables/disables EGPR w/wo -mapx-inline-asm-use-gpr32
-mapx-inline-asm-use-gpr32 will also define a new Macro:
__APX_INLINE_ASM_USE_GPR32__
---
clang/include/clang/Driver/Options.td | 2 +
clang/lib/Basic/Targets/X86.cpp | 26 +
clang/lib/Basic/Targets/X86.h | 1 +
clang/lib/Driver/ToolChains/Arch/X86.cpp | 2 +
.../Driver/x86-apx-inline-asm-use-gpr32.cpp | 3 +
clang/test/Preprocessor/x86_target_features.c | 3 +
llvm/lib/Target/X86/X86.td| 3 +
llvm/lib/Target/X86/X86ISelLowering.cpp | 57 +--
.../CodeGen/X86/inline-asm-jR-constraint.ll | 19 +++
.../CodeGen/X86/inline-asm-r-constraint.ll| 16 ++
10 files changed, 127 insertions(+), 5 deletions(-)
create mode 100644 clang/test/Driver/x86-apx-inline-asm-use-gpr32.cpp
create mode 100644 llvm/test/CodeGen/X86/inline-asm-jR-constraint.ll
create mode 100644 llvm/test/CodeGen/X86/inline-asm-r-constraint.ll
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 73a2518480e9b..20a7c482bbf06 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -6281,6 +6281,8 @@ def mno_apx_features_EQ : CommaJoined<["-"],
"mno-apx-features=">, Group, Alias,
AliasArgs<["egpr","push2pop2","ppx", "ndd"]>;
def mno_apxf : Flag<["-"], "mno-apxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd"]>;
+def mapx_inline_asm_use_gpr32 : Flag<["-"], "mapx-inline-asm-use-gpr32">,
Group,
+HelpText<"Enable use of GPR32 in inline
assembly for APX">;
} // let Flags = [TargetSpecific]
// VE feature flags
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 67e2126cf766b..9e61b6e6d6441 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
+ HasInlineAsmUseGPR32 = true;
} else if (Feature == "+push2pop2") {
HasPush2Pop2 = true;
} else if (Feature == "+ppx") {
@@ -974,6 +976,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
// Condition here is aligned with the feature set of mapxf in Options.td
if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD)
Builder.defineMacro("__APX_F__");
+ if (HasInlineAsmUseGPR32)
+Builder.defineMacro("__APX_INLINE_ASM_USE_GPR32__");
// Each case falls through to the previous one here.
switch (SSELevel) {
@@ -1493,6 +1497,15 @@ bool X86TargetInfo::validateAsmConstraint(
case 'C': // SSE floating point constant.
case 'G': // x87 floating point constant.
return true;
+ case 'j':
+Name++;
+switch (*Name) {
+default:
+ return false;
+case 'R':
+ Info.setAllowsRegister();
+ return true;
+}
case '@':
// CC condition changes.
if (auto Len = matchAsmCCConstraint(Name)) {
@@ -1764,6 +1777,19 @@ std::string X86TargetInfo::convertConstraint(const char
*&Constraint) const {
// to the next constraint.
return std::string("^") + std::string(Constraint++, 2);
}
+ case 'j':
+switch (Constraint[1]) {
+default:
+ // Break from inner switch and fall through (copy single char),
+ // continue parsing after copying the current constraint into
+ // the return string.
+ break;
+case 'R':
+ // "^" hints llvm that this is a 2 letter constraint.
+ // "Constraint++" is used to promote the string iterator
+ // to the next constraint.
+ return std::string("^") + std::string(Constraint++, 2);
+}
[[fallthrough]];
default:
return std::string(1, *Constraint);
diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h
index c14e4d5f433d8..69c68ee80f3ba 100644
--- a/clang/lib/Basic/Targets/X86.h
+++ b/clang/lib/Basic/Targets/X86.h
@@ -174,6 +174,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public
TargetInfo {
bool HasNDD = false;
bool HasCCMP = false;
bool HasCF = false;
+ bool HasInlineAsmUseGPR32 = false;
protected:
llvm::X86::CPUKind CPU = llvm::X86::CK_None;
diff --git a/clang/lib/Driver/ToolChains/Arch/X86.cpp
b/clang/lib/Driver/ToolChains/Arch/X86.cpp
index 53e26a9f8e229..085ff4824a9b0 100644
--- a/clang/lib/Driver/ToolChains/Arch/X86.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/X86.cpp
@@ -309,4 +309,6 @@ void x86::getX86TargetFeatures(const Driver &D, const
llvm::Triple &Triple,
Features.push_back("+prefer-no-gathe
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -58016,15 +58035,27 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
break;
case 'r': // GENERAL_REGS
case 'l': // INDEX_REGS
+ if (Subtarget.useInlineAsmGPR32()) {
+if (VT == MVT::i8 || VT == MVT::i1)
+ return std::make_pair(0U, &X86::GR8_NOREX2RegClass);
+if (VT == MVT::i16)
+ return std::make_pair(0U, &X86::GR16_NOREX2RegClass);
+if (VT == MVT::i32 || VT == MVT::f32 ||
+(!VT.isVector() && !Subtarget.is64Bit()))
+ return std::make_pair(0U, &X86::GR32_NOREX2RegClass);
+if (VT != MVT::f80 && !VT.isVector())
+ return std::make_pair(0U, &X86::GR64_NOREX2RegClass);
+break;
+ }
if (VT == MVT::i8 || VT == MVT::i1)
-return std::make_pair(0U, &X86::GR8_NOREX2RegClass);
+return std::make_pair(0U, &X86::GR8RegClass);
if (VT == MVT::i16)
-return std::make_pair(0U, &X86::GR16_NOREX2RegClass);
+return std::make_pair(0U, &X86::GR16RegClass);
if (VT == MVT::i32 || VT == MVT::f32 ||
(!VT.isVector() && !Subtarget.is64Bit()))
-return std::make_pair(0U, &X86::GR32_NOREX2RegClass);
+return std::make_pair(0U, &X86::GR32RegClass);
if (VT != MVT::f80 && !VT.isVector())
-return std::make_pair(0U, &X86::GR64_NOREX2RegClass);
+return std::make_pair(0U, &X86::GR64RegClass);
nickdesaulniers wrote:
Is it more concise to use ternary expressions here rather than duplicate so
much logic?
```c++
if (VT == MVT::i8 || VT == MVT::i1)
return std::make_pair(0U, Subtarget.useInlineAsmGPR32() ?
&X86::GR8_NOREX2RegClass : &X86::GR8RegClass);
if (VT == MVT::i16)
return std::make_pair(0U, Subtarget.useInlineAsmGPR32() ?
&X86::GR16_NOREX2RegClass : &X86::GR16RegClass);
if (VT == MVT::i32 || VT == MVT::f32 ||
(!VT.isVector() && !Subtarget.is64Bit()))
return std::make_pair(0U, Subtarget.useInlineAsmGPR32() ?
&X86::GR32_NOREX2RegClass : &X86::GR32RegClass);
if (VT != MVT::f80 && !VT.isVector())
return std::make_pair(0U, Subtarget.useInlineAsmGPR32() ?
&X86::GR64_NOREX2RegClass : &X86::GR64RegClass);
```
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
--check-prefix=EGPR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-asm-use-gpr32 < %s |
FileCheck %s --check-prefix=EGPRUSEGPR32
+
+; ERR: error: inline assembly requires more registers than available
+
+define void @constraint_jR_test() nounwind "frame-pointer"="all" {
+; EGPR-LABEL: constraint_jR_test:
+; EGPR:addq %r16, %rax
+;
+; EGPRUSEGPR32-LABEL: constraint_jR_test:
+; EGPRUSEGPR32:addq %r16, %rax
FreddyLeaf wrote:
0bb6794
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s 2>&1 | FileCheck %s
--check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-asm-use-gpr32 < %s | FileCheck
%s --check-prefix=USEGPR32
+
+; ERR: error: inline assembly requires more registers than available
+
+define void @constraint_r_test() nounwind "frame-pointer"="all" {
+; USEGPR32-LABEL: constraint_r_test:
+; USEGPR32:addq %r16, %rax
+entry:
+ %reg = alloca i64, align 8
+ %0 = load i64, ptr %reg, align 8
+ call void asm sideeffect "add $0, %rax",
"r,~{rax},~{rbx},~{rcx},~{rdx},~{rdi},~{rsi},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{dirflag},~{fpsr},~{flags}"(i64
%0)
+ ret void
+}
+
+define void @constraint_jR_test() nounwind "frame-pointer"="all" {
+; EGPR-LABEL: constraint_jR_test:
+; EGPR:addq %r16, %rax
+;
+; EGPRUSEGPR32-LABEL: constraint_jR_test:
+; EGPRUSEGPR32:addq %r16, %rax
FreddyLeaf wrote:
0bb6794
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/7] [X86] Support EGPR for inline assembly.
"jR": explictly enables EGPR
"r": enables/disables EGPR w/wo -mapx-inline-asm-use-gpr32
-mapx-inline-asm-use-gpr32 will also define a new Macro:
__APX_INLINE_ASM_USE_GPR32__
---
clang/include/clang/Driver/Options.td | 2 +
clang/lib/Basic/Targets/X86.cpp | 26 +
clang/lib/Basic/Targets/X86.h | 1 +
clang/lib/Driver/ToolChains/Arch/X86.cpp | 2 +
.../Driver/x86-apx-inline-asm-use-gpr32.cpp | 3 +
clang/test/Preprocessor/x86_target_features.c | 3 +
llvm/lib/Target/X86/X86.td| 3 +
llvm/lib/Target/X86/X86ISelLowering.cpp | 57 +--
.../CodeGen/X86/inline-asm-jR-constraint.ll | 19 +++
.../CodeGen/X86/inline-asm-r-constraint.ll| 16 ++
10 files changed, 127 insertions(+), 5 deletions(-)
create mode 100644 clang/test/Driver/x86-apx-inline-asm-use-gpr32.cpp
create mode 100644 llvm/test/CodeGen/X86/inline-asm-jR-constraint.ll
create mode 100644 llvm/test/CodeGen/X86/inline-asm-r-constraint.ll
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 73a2518480e9b..20a7c482bbf06 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -6281,6 +6281,8 @@ def mno_apx_features_EQ : CommaJoined<["-"],
"mno-apx-features=">, Group, Alias,
AliasArgs<["egpr","push2pop2","ppx", "ndd"]>;
def mno_apxf : Flag<["-"], "mno-apxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd"]>;
+def mapx_inline_asm_use_gpr32 : Flag<["-"], "mapx-inline-asm-use-gpr32">,
Group,
+HelpText<"Enable use of GPR32 in inline
assembly for APX">;
} // let Flags = [TargetSpecific]
// VE feature flags
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 67e2126cf766b..9e61b6e6d6441 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
+ HasInlineAsmUseGPR32 = true;
} else if (Feature == "+push2pop2") {
HasPush2Pop2 = true;
} else if (Feature == "+ppx") {
@@ -974,6 +976,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
// Condition here is aligned with the feature set of mapxf in Options.td
if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD)
Builder.defineMacro("__APX_F__");
+ if (HasInlineAsmUseGPR32)
+Builder.defineMacro("__APX_INLINE_ASM_USE_GPR32__");
// Each case falls through to the previous one here.
switch (SSELevel) {
@@ -1493,6 +1497,15 @@ bool X86TargetInfo::validateAsmConstraint(
case 'C': // SSE floating point constant.
case 'G': // x87 floating point constant.
return true;
+ case 'j':
+Name++;
+switch (*Name) {
+default:
+ return false;
+case 'R':
+ Info.setAllowsRegister();
+ return true;
+}
case '@':
// CC condition changes.
if (auto Len = matchAsmCCConstraint(Name)) {
@@ -1764,6 +1777,19 @@ std::string X86TargetInfo::convertConstraint(const char
*&Constraint) const {
// to the next constraint.
return std::string("^") + std::string(Constraint++, 2);
}
+ case 'j':
+switch (Constraint[1]) {
+default:
+ // Break from inner switch and fall through (copy single char),
+ // continue parsing after copying the current constraint into
+ // the return string.
+ break;
+case 'R':
+ // "^" hints llvm that this is a 2 letter constraint.
+ // "Constraint++" is used to promote the string iterator
+ // to the next constraint.
+ return std::string("^") + std::string(Constraint++, 2);
+}
[[fallthrough]];
default:
return std::string(1, *Constraint);
diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h
index c14e4d5f433d8..69c68ee80f3ba 100644
--- a/clang/lib/Basic/Targets/X86.h
+++ b/clang/lib/Basic/Targets/X86.h
@@ -174,6 +174,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public
TargetInfo {
bool HasNDD = false;
bool HasCCMP = false;
bool HasCF = false;
+ bool HasInlineAsmUseGPR32 = false;
protected:
llvm::X86::CPUKind CPU = llvm::X86::CK_None;
diff --git a/clang/lib/Driver/ToolChains/Arch/X86.cpp
b/clang/lib/Driver/ToolChains/Arch/X86.cpp
index 53e26a9f8e229..085ff4824a9b0 100644
--- a/clang/lib/Driver/ToolChains/Arch/X86.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/X86.cpp
@@ -309,4 +309,6 @@ void x86::getX86TargetFeatures(const Driver &D, const
llvm::Triple &Triple,
Features.push_back("+prefer-no-gathe
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s 2>&1 | FileCheck %s
--check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-asm-use-gpr32 < %s | FileCheck
%s --check-prefix=USEGPR32
+
+; ERR: error: inline assembly requires more registers than available
+
+define void @constraint_r_test() nounwind "frame-pointer"="all" {
+; USEGPR32-LABEL: constraint_r_test:
+; USEGPR32:addq %r16, %rax
+entry:
+ %reg = alloca i64, align 8
+ %0 = load i64, ptr %reg, align 8
+ call void asm sideeffect "add $0, %rax",
"r,~{rax},~{rbx},~{rcx},~{rdx},~{rdi},~{rsi},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{dirflag},~{fpsr},~{flags}"(i64
%0)
+ ret void
+}
+
+define void @constraint_jR_test() nounwind "frame-pointer"="all" {
+; EGPR-LABEL: constraint_jR_test:
+; EGPR:addq %r16, %rax
+;
+; EGPRUSEGPR32-LABEL: constraint_jR_test:
+; EGPRUSEGPR32:addq %r16, %rax
nickdesaulniers wrote:
Are these dead check lines? No `RUN` lines above use this check prefix.
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
--check-prefix=EGPR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-asm-use-gpr32 < %s |
FileCheck %s --check-prefix=EGPRUSEGPR32
+
+; ERR: error: inline assembly requires more registers than available
+
+define void @constraint_jR_test() nounwind "frame-pointer"="all" {
+; EGPR-LABEL: constraint_jR_test:
+; EGPR:addq %r16, %rax
+;
+; EGPRUSEGPR32-LABEL: constraint_jR_test:
+; EGPRUSEGPR32:addq %r16, %rax
nickdesaulniers wrote:
These 2 are the same; consider using the same check prefix. You can omit
`--check-prefix` and just use `CHECK:` here.
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
FreddyLeaf wrote: > ` > [4087704](/llvm/llvm-project/pull/92338/commits/40877041618aa8f472f0da7cda06c21f4007a1ec)` Thanks reminding. Added in 4087704, pls help review. https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/6] [X86] Support EGPR for inline assembly.
"jR": explictly enables EGPR
"r": enables/disables EGPR w/wo -mapx-inline-asm-use-gpr32
-mapx-inline-asm-use-gpr32 will also define a new Macro:
__APX_INLINE_ASM_USE_GPR32__
---
clang/include/clang/Driver/Options.td | 2 +
clang/lib/Basic/Targets/X86.cpp | 26 +
clang/lib/Basic/Targets/X86.h | 1 +
clang/lib/Driver/ToolChains/Arch/X86.cpp | 2 +
.../Driver/x86-apx-inline-asm-use-gpr32.cpp | 3 +
clang/test/Preprocessor/x86_target_features.c | 3 +
llvm/lib/Target/X86/X86.td| 3 +
llvm/lib/Target/X86/X86ISelLowering.cpp | 57 +--
.../CodeGen/X86/inline-asm-jR-constraint.ll | 19 +++
.../CodeGen/X86/inline-asm-r-constraint.ll| 16 ++
10 files changed, 127 insertions(+), 5 deletions(-)
create mode 100644 clang/test/Driver/x86-apx-inline-asm-use-gpr32.cpp
create mode 100644 llvm/test/CodeGen/X86/inline-asm-jR-constraint.ll
create mode 100644 llvm/test/CodeGen/X86/inline-asm-r-constraint.ll
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 73a2518480e9b..20a7c482bbf06 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -6281,6 +6281,8 @@ def mno_apx_features_EQ : CommaJoined<["-"],
"mno-apx-features=">, Group, Alias,
AliasArgs<["egpr","push2pop2","ppx", "ndd"]>;
def mno_apxf : Flag<["-"], "mno-apxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd"]>;
+def mapx_inline_asm_use_gpr32 : Flag<["-"], "mapx-inline-asm-use-gpr32">,
Group,
+HelpText<"Enable use of GPR32 in inline
assembly for APX">;
} // let Flags = [TargetSpecific]
// VE feature flags
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 67e2126cf766b..9e61b6e6d6441 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
+ HasInlineAsmUseGPR32 = true;
} else if (Feature == "+push2pop2") {
HasPush2Pop2 = true;
} else if (Feature == "+ppx") {
@@ -974,6 +976,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
// Condition here is aligned with the feature set of mapxf in Options.td
if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD)
Builder.defineMacro("__APX_F__");
+ if (HasInlineAsmUseGPR32)
+Builder.defineMacro("__APX_INLINE_ASM_USE_GPR32__");
// Each case falls through to the previous one here.
switch (SSELevel) {
@@ -1493,6 +1497,15 @@ bool X86TargetInfo::validateAsmConstraint(
case 'C': // SSE floating point constant.
case 'G': // x87 floating point constant.
return true;
+ case 'j':
+Name++;
+switch (*Name) {
+default:
+ return false;
+case 'R':
+ Info.setAllowsRegister();
+ return true;
+}
case '@':
// CC condition changes.
if (auto Len = matchAsmCCConstraint(Name)) {
@@ -1764,6 +1777,19 @@ std::string X86TargetInfo::convertConstraint(const char
*&Constraint) const {
// to the next constraint.
return std::string("^") + std::string(Constraint++, 2);
}
+ case 'j':
+switch (Constraint[1]) {
+default:
+ // Break from inner switch and fall through (copy single char),
+ // continue parsing after copying the current constraint into
+ // the return string.
+ break;
+case 'R':
+ // "^" hints llvm that this is a 2 letter constraint.
+ // "Constraint++" is used to promote the string iterator
+ // to the next constraint.
+ return std::string("^") + std::string(Constraint++, 2);
+}
[[fallthrough]];
default:
return std::string(1, *Constraint);
diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h
index c14e4d5f433d8..69c68ee80f3ba 100644
--- a/clang/lib/Basic/Targets/X86.h
+++ b/clang/lib/Basic/Targets/X86.h
@@ -174,6 +174,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public
TargetInfo {
bool HasNDD = false;
bool HasCCMP = false;
bool HasCF = false;
+ bool HasInlineAsmUseGPR32 = false;
protected:
llvm::X86::CPUKind CPU = llvm::X86::CK_None;
diff --git a/clang/lib/Driver/ToolChains/Arch/X86.cpp
b/clang/lib/Driver/ToolChains/Arch/X86.cpp
index 53e26a9f8e229..085ff4824a9b0 100644
--- a/clang/lib/Driver/ToolChains/Arch/X86.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/X86.cpp
@@ -309,4 +309,6 @@ void x86::getX86TargetFeatures(const Driver &D, const
llvm::Triple &Triple,
Features.push_back("+prefer-no-gathe
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
jyknight wrote: Please update the constraint code list https://llvm.org/docs/LangRef.html#supported-constraint-code-list with any new codes. https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
FreddyLeaf wrote: [4d1ad30](https://github.com/llvm/llvm-project/pull/92338/commits/4d1ad3090416cda320c88f1ddc0937b5749e64b4) moved but not merged. These two constraints will behavior different under -mattr=+egpr. https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/5] [X86] Support EGPR for inline assembly.
"jR": explictly enables EGPR
"r": enables/disables EGPR w/wo -mapx-inline-asm-use-gpr32
-mapx-inline-asm-use-gpr32 will also define a new Macro:
__APX_INLINE_ASM_USE_GPR32__
---
clang/include/clang/Driver/Options.td | 2 +
clang/lib/Basic/Targets/X86.cpp | 26 +
clang/lib/Basic/Targets/X86.h | 1 +
clang/lib/Driver/ToolChains/Arch/X86.cpp | 2 +
.../Driver/x86-apx-inline-asm-use-gpr32.cpp | 3 +
clang/test/Preprocessor/x86_target_features.c | 3 +
llvm/lib/Target/X86/X86.td| 3 +
llvm/lib/Target/X86/X86ISelLowering.cpp | 57 +--
.../CodeGen/X86/inline-asm-jR-constraint.ll | 19 +++
.../CodeGen/X86/inline-asm-r-constraint.ll| 16 ++
10 files changed, 127 insertions(+), 5 deletions(-)
create mode 100644 clang/test/Driver/x86-apx-inline-asm-use-gpr32.cpp
create mode 100644 llvm/test/CodeGen/X86/inline-asm-jR-constraint.ll
create mode 100644 llvm/test/CodeGen/X86/inline-asm-r-constraint.ll
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 73a2518480e9b..20a7c482bbf06 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -6281,6 +6281,8 @@ def mno_apx_features_EQ : CommaJoined<["-"],
"mno-apx-features=">, Group, Alias,
AliasArgs<["egpr","push2pop2","ppx", "ndd"]>;
def mno_apxf : Flag<["-"], "mno-apxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd"]>;
+def mapx_inline_asm_use_gpr32 : Flag<["-"], "mapx-inline-asm-use-gpr32">,
Group,
+HelpText<"Enable use of GPR32 in inline
assembly for APX">;
} // let Flags = [TargetSpecific]
// VE feature flags
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 67e2126cf766b..9e61b6e6d6441 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
+ HasInlineAsmUseGPR32 = true;
} else if (Feature == "+push2pop2") {
HasPush2Pop2 = true;
} else if (Feature == "+ppx") {
@@ -974,6 +976,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
// Condition here is aligned with the feature set of mapxf in Options.td
if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD)
Builder.defineMacro("__APX_F__");
+ if (HasInlineAsmUseGPR32)
+Builder.defineMacro("__APX_INLINE_ASM_USE_GPR32__");
// Each case falls through to the previous one here.
switch (SSELevel) {
@@ -1493,6 +1497,15 @@ bool X86TargetInfo::validateAsmConstraint(
case 'C': // SSE floating point constant.
case 'G': // x87 floating point constant.
return true;
+ case 'j':
+Name++;
+switch (*Name) {
+default:
+ return false;
+case 'R':
+ Info.setAllowsRegister();
+ return true;
+}
case '@':
// CC condition changes.
if (auto Len = matchAsmCCConstraint(Name)) {
@@ -1764,6 +1777,19 @@ std::string X86TargetInfo::convertConstraint(const char
*&Constraint) const {
// to the next constraint.
return std::string("^") + std::string(Constraint++, 2);
}
+ case 'j':
+switch (Constraint[1]) {
+default:
+ // Break from inner switch and fall through (copy single char),
+ // continue parsing after copying the current constraint into
+ // the return string.
+ break;
+case 'R':
+ // "^" hints llvm that this is a 2 letter constraint.
+ // "Constraint++" is used to promote the string iterator
+ // to the next constraint.
+ return std::string("^") + std::string(Constraint++, 2);
+}
[[fallthrough]];
default:
return std::string(1, *Constraint);
diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h
index c14e4d5f433d8..69c68ee80f3ba 100644
--- a/clang/lib/Basic/Targets/X86.h
+++ b/clang/lib/Basic/Targets/X86.h
@@ -174,6 +174,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public
TargetInfo {
bool HasNDD = false;
bool HasCCMP = false;
bool HasCF = false;
+ bool HasInlineAsmUseGPR32 = false;
protected:
llvm::X86::CPUKind CPU = llvm::X86::CK_None;
diff --git a/clang/lib/Driver/ToolChains/Arch/X86.cpp
b/clang/lib/Driver/ToolChains/Arch/X86.cpp
index 53e26a9f8e229..085ff4824a9b0 100644
--- a/clang/lib/Driver/ToolChains/Arch/X86.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/X86.cpp
@@ -309,4 +309,6 @@ void x86::getX86TargetFeatures(const Driver &D, const
llvm::Triple &Triple,
Features.push_back("+prefer-no-gathe
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
KanRobert wrote: Merge the two tests into one and put it under apx directory. https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
FreddyLeaf wrote: ping for review https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/4] [X86] Support EGPR for inline assembly.
"jR": explictly enables EGPR
"r": enables/disables EGPR w/wo -mapx-inline-asm-use-gpr32
-mapx-inline-asm-use-gpr32 will also define a new Macro:
__APX_INLINE_ASM_USE_GPR32__
---
clang/include/clang/Driver/Options.td | 2 +
clang/lib/Basic/Targets/X86.cpp | 26 +
clang/lib/Basic/Targets/X86.h | 1 +
clang/lib/Driver/ToolChains/Arch/X86.cpp | 2 +
.../Driver/x86-apx-inline-asm-use-gpr32.cpp | 3 +
clang/test/Preprocessor/x86_target_features.c | 3 +
llvm/lib/Target/X86/X86.td| 3 +
llvm/lib/Target/X86/X86ISelLowering.cpp | 57 +--
.../CodeGen/X86/inline-asm-jR-constraint.ll | 19 +++
.../CodeGen/X86/inline-asm-r-constraint.ll| 16 ++
10 files changed, 127 insertions(+), 5 deletions(-)
create mode 100644 clang/test/Driver/x86-apx-inline-asm-use-gpr32.cpp
create mode 100644 llvm/test/CodeGen/X86/inline-asm-jR-constraint.ll
create mode 100644 llvm/test/CodeGen/X86/inline-asm-r-constraint.ll
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 73a2518480e9b..20a7c482bbf06 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -6281,6 +6281,8 @@ def mno_apx_features_EQ : CommaJoined<["-"],
"mno-apx-features=">, Group, Alias,
AliasArgs<["egpr","push2pop2","ppx", "ndd"]>;
def mno_apxf : Flag<["-"], "mno-apxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd"]>;
+def mapx_inline_asm_use_gpr32 : Flag<["-"], "mapx-inline-asm-use-gpr32">,
Group,
+HelpText<"Enable use of GPR32 in inline
assembly for APX">;
} // let Flags = [TargetSpecific]
// VE feature flags
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 67e2126cf766b..9e61b6e6d6441 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
+ HasInlineAsmUseGPR32 = true;
} else if (Feature == "+push2pop2") {
HasPush2Pop2 = true;
} else if (Feature == "+ppx") {
@@ -974,6 +976,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
// Condition here is aligned with the feature set of mapxf in Options.td
if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD)
Builder.defineMacro("__APX_F__");
+ if (HasInlineAsmUseGPR32)
+Builder.defineMacro("__APX_INLINE_ASM_USE_GPR32__");
// Each case falls through to the previous one here.
switch (SSELevel) {
@@ -1493,6 +1497,15 @@ bool X86TargetInfo::validateAsmConstraint(
case 'C': // SSE floating point constant.
case 'G': // x87 floating point constant.
return true;
+ case 'j':
+Name++;
+switch (*Name) {
+default:
+ return false;
+case 'R':
+ Info.setAllowsRegister();
+ return true;
+}
case '@':
// CC condition changes.
if (auto Len = matchAsmCCConstraint(Name)) {
@@ -1764,6 +1777,19 @@ std::string X86TargetInfo::convertConstraint(const char
*&Constraint) const {
// to the next constraint.
return std::string("^") + std::string(Constraint++, 2);
}
+ case 'j':
+switch (Constraint[1]) {
+default:
+ // Break from inner switch and fall through (copy single char),
+ // continue parsing after copying the current constraint into
+ // the return string.
+ break;
+case 'R':
+ // "^" hints llvm that this is a 2 letter constraint.
+ // "Constraint++" is used to promote the string iterator
+ // to the next constraint.
+ return std::string("^") + std::string(Constraint++, 2);
+}
[[fallthrough]];
default:
return std::string(1, *Constraint);
diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h
index c14e4d5f433d8..69c68ee80f3ba 100644
--- a/clang/lib/Basic/Targets/X86.h
+++ b/clang/lib/Basic/Targets/X86.h
@@ -174,6 +174,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public
TargetInfo {
bool HasNDD = false;
bool HasCCMP = false;
bool HasCF = false;
+ bool HasInlineAsmUseGPR32 = false;
protected:
llvm::X86::CPUKind CPU = llvm::X86::CK_None;
diff --git a/clang/lib/Driver/ToolChains/Arch/X86.cpp
b/clang/lib/Driver/ToolChains/Arch/X86.cpp
index 53e26a9f8e229..085ff4824a9b0 100644
--- a/clang/lib/Driver/ToolChains/Arch/X86.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/X86.cpp
@@ -309,4 +309,6 @@ void x86::getX86TargetFeatures(const Driver &D, const
llvm::Triple &Triple,
Features.push_back("+prefer-no-gathe
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
https://github.com/KanRobert edited https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
KanRobert wrote:
> SSELevel relies on feature string in IR attribute as well.
Which one do you mean?
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
FreddyLeaf wrote:
> > > Will the feature be emitted in IR?
> >
> >
> > yes, I was referring `prefer-no-gather`
>
> Then it's not expected. `prefer-no-gather` is a real tuning feature.
actually, no cpus enabled this tuning feature.
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
FreddyLeaf wrote:
SSELevel relies on feature string in IR attribute as well. it's same situation
here.
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
KanRobert wrote:
> > Will the feature be emitted in IR?
>
> yes, I was referring `prefer-no-gather`
Then it's not expected. `prefer-no-gather` is a real tuning feature.
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
FreddyLeaf wrote:
> Will the feature be emitted in IR?
yes, I was referring `prefer-no-gather`
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
KanRobert wrote:
> `mcmodel` maybe not a good reference here since it's target independent.
```
if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
switch (SSELevel) {
case AVX512F:
case AVX2:
case AVX:
case SSE42:
case SSE41:
case SSSE3:
case SSE3:
case SSE2:
Builder.defineMacro("_M_IX86_FP", Twine(2));
break;
case SSE1:
Builder.defineMacro("_M_IX86_FP", Twine(1));
break;
default:
Builder.defineMacro("_M_IX86_FP", Twine(0));
break;
}
}
```
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
https://github.com/KanRobert edited https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
KanRobert wrote:
Will the feature be emitted in IR?
https://github.com/llvm/llvm-project/pull/92338
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/92338
>From 41fbc18c7a4a26b11bc4b772bbe2e384ad9d9dbc Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 10 May 2024 16:29:55 +0800
Subject: [PATCH 1/3] [X86] Support EGPR for inline assembly.
"jR": explictly enables EGPR
"r": enables/disables EGPR w/wo -mapx-inline-asm-use-gpr32
-mapx-inline-asm-use-gpr32 will also define a new Macro:
__APX_INLINE_ASM_USE_GPR32__
---
clang/include/clang/Driver/Options.td | 2 +
clang/lib/Basic/Targets/X86.cpp | 26 +
clang/lib/Basic/Targets/X86.h | 1 +
clang/lib/Driver/ToolChains/Arch/X86.cpp | 2 +
.../Driver/x86-apx-inline-asm-use-gpr32.cpp | 3 +
clang/test/Preprocessor/x86_target_features.c | 3 +
llvm/lib/Target/X86/X86.td| 3 +
llvm/lib/Target/X86/X86ISelLowering.cpp | 57 +--
.../CodeGen/X86/inline-asm-jR-constraint.ll | 19 +++
.../CodeGen/X86/inline-asm-r-constraint.ll| 16 ++
10 files changed, 127 insertions(+), 5 deletions(-)
create mode 100644 clang/test/Driver/x86-apx-inline-asm-use-gpr32.cpp
create mode 100644 llvm/test/CodeGen/X86/inline-asm-jR-constraint.ll
create mode 100644 llvm/test/CodeGen/X86/inline-asm-r-constraint.ll
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 73a2518480e9b..20a7c482bbf06 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -6281,6 +6281,8 @@ def mno_apx_features_EQ : CommaJoined<["-"],
"mno-apx-features=">, Group, Alias,
AliasArgs<["egpr","push2pop2","ppx", "ndd"]>;
def mno_apxf : Flag<["-"], "mno-apxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd"]>;
+def mapx_inline_asm_use_gpr32 : Flag<["-"], "mapx-inline-asm-use-gpr32">,
Group,
+HelpText<"Enable use of GPR32 in inline
assembly for APX">;
} // let Flags = [TargetSpecific]
// VE feature flags
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 67e2126cf766b..9e61b6e6d6441 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
+ HasInlineAsmUseGPR32 = true;
} else if (Feature == "+push2pop2") {
HasPush2Pop2 = true;
} else if (Feature == "+ppx") {
@@ -974,6 +976,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
// Condition here is aligned with the feature set of mapxf in Options.td
if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD)
Builder.defineMacro("__APX_F__");
+ if (HasInlineAsmUseGPR32)
+Builder.defineMacro("__APX_INLINE_ASM_USE_GPR32__");
// Each case falls through to the previous one here.
switch (SSELevel) {
@@ -1493,6 +1497,15 @@ bool X86TargetInfo::validateAsmConstraint(
case 'C': // SSE floating point constant.
case 'G': // x87 floating point constant.
return true;
+ case 'j':
+Name++;
+switch (*Name) {
+default:
+ return false;
+case 'R':
+ Info.setAllowsRegister();
+ return true;
+}
case '@':
// CC condition changes.
if (auto Len = matchAsmCCConstraint(Name)) {
@@ -1764,6 +1777,19 @@ std::string X86TargetInfo::convertConstraint(const char
*&Constraint) const {
// to the next constraint.
return std::string("^") + std::string(Constraint++, 2);
}
+ case 'j':
+switch (Constraint[1]) {
+default:
+ // Break from inner switch and fall through (copy single char),
+ // continue parsing after copying the current constraint into
+ // the return string.
+ break;
+case 'R':
+ // "^" hints llvm that this is a 2 letter constraint.
+ // "Constraint++" is used to promote the string iterator
+ // to the next constraint.
+ return std::string("^") + std::string(Constraint++, 2);
+}
[[fallthrough]];
default:
return std::string(1, *Constraint);
diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h
index c14e4d5f433d8..69c68ee80f3ba 100644
--- a/clang/lib/Basic/Targets/X86.h
+++ b/clang/lib/Basic/Targets/X86.h
@@ -174,6 +174,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public
TargetInfo {
bool HasNDD = false;
bool HasCCMP = false;
bool HasCF = false;
+ bool HasInlineAsmUseGPR32 = false;
protected:
llvm::X86::CPUKind CPU = llvm::X86::CK_None;
diff --git a/clang/lib/Driver/ToolChains/Arch/X86.cpp
b/clang/lib/Driver/ToolChains/Arch/X86.cpp
index 53e26a9f8e229..085ff4824a9b0 100644
--- a/clang/lib/Driver/ToolChains/Arch/X86.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/X86.cpp
@@ -309,4 +309,6 @@ void x86::getX86TargetFeatures(const Driver &D, const
llvm::Triple &Triple,
Features.push_back("+prefer-no-gathe
[clang] [llvm] [X86] Support EGPR for inline assembly. (PR #92338)
FreddyLeaf wrote: > Please put the corresponding GCC links for your description done. https://github.com/llvm/llvm-project/pull/92338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
