Author: 4vtomat Date: 2023-08-13T22:33:52-07:00 New Revision: a23d65ac89ce1263b58690fa051e81d7cd0b139d
URL: https://github.com/llvm/llvm-project/commit/a23d65ac89ce1263b58690fa051e81d7cd0b139d DIFF: https://github.com/llvm/llvm-project/commit/a23d65ac89ce1263b58690fa051e81d7cd0b139d.diff LOG: [RISCV] Add missing Xsfvcp extension check in clang sema Differential Revision: https://reviews.llvm.org/D157474 Added: clang/test/Sema/rvv-required-features-invalid.c clang/test/Sema/rvv-required-features.c Modified: clang/lib/Sema/SemaRISCVVectorLookup.cpp Removed: ################################################################################ diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp b/clang/lib/Sema/SemaRISCVVectorLookup.cpp index eec2bc11e35d9e..486f901a6cf1e6 100644 --- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp +++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp @@ -202,10 +202,20 @@ class RISCVIntrinsicManagerImpl : public sema::RISCVIntrinsicManager { void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics( ArrayRef<RVVIntrinsicRecord> Recs, IntrinsicKind K) { const TargetInfo &TI = Context.getTargetInfo(); - bool HasRV64 = TI.hasFeature("64bit"); + static const std::pair<const char *, uint8_t> FeatureCheckList[] = { + {"64bit", RVV_REQ_RV64}, + {"xsfvcp", RVV_REQ_Xsfvcp}}; + // Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics // in RISCVVEmitter.cpp. for (auto &Record : Recs) { + // Check requirements. + if (llvm::any_of(FeatureCheckList, [&](const auto &Item) { + return (Record.RequiredExtensions & Item.second) == Item.second && + !TI.hasFeature(Item.first); + })) + continue; + // Create Intrinsics for each type and LMUL. BasicType BaseType = BasicType::Unknown; ArrayRef<PrototypeDescriptor> BasicProtoSeq = @@ -251,11 +261,6 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics( if ((BaseTypeI & Record.TypeRangeMask) != BaseTypeI) continue; - // Check requirement. - if (((Record.RequiredExtensions & RVV_REQ_RV64) == RVV_REQ_RV64) && - !HasRV64) - continue; - // Expanded with diff erent LMUL. for (int Log2LMUL = -3; Log2LMUL <= 3; Log2LMUL++) { if (!(Record.Log2LMULMask & (1 << (Log2LMUL + 3)))) diff --git a/clang/test/Sema/rvv-required-features-invalid.c b/clang/test/Sema/rvv-required-features-invalid.c new file mode 100644 index 00000000000000..0d0d00764a31e3 --- /dev/null +++ b/clang/test/Sema/rvv-required-features-invalid.c @@ -0,0 +1,17 @@ +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv32 -target-feature +v %s -fsyntax-only -verify + +#include <riscv_vector.h> +#include <sifive_vector.h> + +vint8m1_t test_vloxei64_v_i8m1(const int8_t *base, vuint64m8_t bindex, size_t vl) { + return __riscv_vloxei64(base, bindex, vl); // expected-error {{call to undeclared function '__riscv_vloxei64'}} expected-error {{returning 'int' from a function with incompatible result type 'vint8m1_t'}} +} + +void test_vsoxei64_v_i8m1(int8_t *base, vuint64m8_t bindex, vint8m1_t value, size_t vl) { + __riscv_vsoxei64(base, bindex, value, vl); // expected-error {{call to undeclared function '__riscv_vsoxei64'}} +} + +void test_xsfvcp_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) { + __riscv_sf_vc_x_se_u64m1(1, 1, 1, rs1, vl); // expected-error {{call to undeclared function '__riscv_sf_vc_x_se_u64m1'}} +} diff --git a/clang/test/Sema/rvv-required-features.c b/clang/test/Sema/rvv-required-features.c new file mode 100644 index 00000000000000..c3b7965599e68f --- /dev/null +++ b/clang/test/Sema/rvv-required-features.c @@ -0,0 +1,19 @@ +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp %s -fsyntax-only -verify + +// expected-no-diagnostics + +#include <riscv_vector.h> +#include <sifive_vector.h> + +vint8m1_t test_vloxei64_v_i8m1(const int8_t *base, vuint64m8_t bindex, size_t vl) { + return __riscv_vloxei64(base, bindex, vl); +} + +void test_vsoxei64_v_i8m1(int8_t *base, vuint64m8_t bindex, vint8m1_t value, size_t vl) { + __riscv_vsoxei64(base, bindex, value, vl); +} + +void test_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) { + __riscv_sf_vc_x_se_u64m1(1, 1, 1, rs1, vl); +} _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
