[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
https://github.com/asb approved this pull request. LGTM. Thanks for your persistence on this! https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
@@ -985,9 +1003,10 @@ void RISCVFrameLowering::determineCalleeSaves(MachineFunction , }; for (auto Reg : CSRegs) - SavedRegs.set(Reg); + if (Reg < RISCV::X16 || !Subtarget.isRVE()) wangpc-pp wrote: Though it's nearly impossible to have such configuration in real application, I saved x15-x16 in https://github.com/llvm/llvm-project/pull/76777/commits/20ffba38548c823d6ef286bcad63385087438d57. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
@@ -985,9 +1003,10 @@ void RISCVFrameLowering::determineCalleeSaves(MachineFunction , }; for (auto Reg : CSRegs) - SavedRegs.set(Reg); + if (Reg < RISCV::X16 || !Subtarget.isRVE()) wangpc-pp wrote: The psABI says: > If used with an ISA that has any of the registers x16-x31 and f0-f31, then > these registers are considered temporaries. So I think we should. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
@@ -50,11 +50,14 @@ void RISCVTargetStreamer::setTargetABI(RISCVABI::ABI ABI) {
void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo ,
bool EmitStackAlign) {
- if (STI.hasFeature(RISCV::FeatureRVE))
-report_fatal_error("Codegen not yet implemented for RVE");
-
- if (EmitStackAlign)
-emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
+ if (EmitStackAlign) {
+if (STI.hasFeature(RISCV::FeatureRVE))
nemanjai wrote:
This seems to not match what the usage doc above says. Namely, the doc says
that the alignment is dependent on the ABI but this uses the ISA feature rather
than the ABI.
Furthermore, `getABIStackAlignment()` also obviously uses the ABI rather than
the ISA feature.
https://github.com/llvm/llvm-project/pull/76777
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[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
@@ -985,9 +1003,10 @@ void RISCVFrameLowering::determineCalleeSaves(MachineFunction , }; for (auto Reg : CSRegs) - SavedRegs.set(Reg); + if (Reg < RISCV::X16 || !Subtarget.isRVE()) nemanjai wrote: What happens if we are using `ilp32e/lp64e` ABI on a subtarget that isn't RVE? Should these registers be saved? https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
@@ -38,3 +40,14 @@ def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add CSR_Interrupt, // Same as CSR_Interrupt, but including all 64-bit FP registers. def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add CSR_Interrupt, (sequence "F%u_D", 0, 31))>; + +// Same as CSR_Interrupt, but excluding X16-X31. +def CSR_Interrupt_RVE : CalleeSavedRegs<(add X1, (sequence "X%u", 5, 15))>; nemanjai wrote: Minor nit: I think it would be nice if the code reads as clearly as this comment does. Namely `(sub CSR_Interrupt, (sequence "X%u, 16, 31))` Similarly below. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
https://github.com/nemanjai edited https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
nemanjai wrote: > @nemanjai I'm curious if you have an interest / need to support RVE or not? I most certainly do. Thank you for alerting me to this PR. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
koute wrote: > Can you fire a PR for these changes? I think we should support it in > compiler-rt once we have merged this PR. Once this PR is merged, sure, I can make a PR. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
wangpc-pp wrote: > > As for your diffs, it seems that you only handle the > > `__riscv_save/restore_[2|1|0]`, which is incomplete. And the code is not > > different with non-rve cases? > > Yes, I mostly copy-pasted the existing code and removed all of the code > dealing with registers not available on RV32E, so having only > `__riscv_save/restore_[2|1|0]` is intended I suppose because there are only > this many saved registers on RV32E. (There's probably a better way of doing > it, and it looks like I screwed up the RV64E part of the patch.) > > If I remember correctly I think I did this because otherwise compiling > `compiler-rt` was not possible for RV32E and the compilation was spewing out > errors about the unavailable registers? But I need to check this again once I > finish porting this newest version of the patch to the most recent version of > Rust. Oh, I see. My previous comment was wrong. I just checked GCC implementation, we do need to handle RVE cases (but GCC still lacks of RV64E handling). LLVM hasn't handled this mainly because we haven't support RVE now, I think. Can you fire a PR for these changes? I think we should support it in compiler-rt once we have merge this PR. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
koute wrote: > But I think this patch can work just fine [...] Apart from vendors' need, the > request is mainly from Rust language community I think. To put our 3 cents here, [we](https://github.com/paritytech) also need it. We are (well, it's mostly me right now since it's still a prototype) currently building [a virtual machine that is based on RV32E](https://github.com/koute/polkavm) (and in the future also RV64E), and, long story short, thanks to the magic of RV32E it achieves execution performance roughly the same as [wasmtime](https://github.com/bytecodealliance/wasmtime) (which is a state-of-art WASM VM) while compiling into native code over ~200 times faster and being orders of magnitude simpler (because you can mostly naively translate RV32E machine code 1-to-1 into native AMD64 code as the reduced number of registers makes this barely possible, and the code is still very fast). As far as testing this patch, as a fairly decent test case I've used one of the previous versions to compile DOOM into RV32E and ran it under our VM (in fact, [you can play it here it you want](https://github.com/koute/polkavm/tree/master/examples/doom)), so the patch definitely works. Anyway, people are underestimating RV32E thinking it's only for bottom tier microcontrollers, but this couldn't be further from the truth. It's not perfect, but it's also a really great VM bytecode; dare I say, I think it's a better WASM than WASM for non-Web uses. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
@@ -179,6 +180,11 @@ Assembly Support Supported Fully supported by the compiler. This includes everything in Assembly Support, along with - if relevant - C language intrinsics for the instructions and pattern matching by the compiler to recognize idiomatic patterns which can be lowered to the associated instructions. +.. _riscv-rve-note: + +``E`` + Support of RV32E/RV64E and ilp32e/lp64e ABIs are experimental. asb wrote: Maybe this would be a good place to add "To be compatible with the implementation of ilp32e in GCC, we don't use aligned registers to pass variadic arguments and set stack alignment to 4-bytes for types with length of 2*XLEN." Given this gap in the ABI, it would be good if we could document it somewhere outside of the commit message. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
asb wrote: @nemanjai I'm curious if you have an interest / need to support RVE or not? https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
wangpc-pp wrote: > @wangpc-pp did you have interested on helping psABI side? it would be great > if you can help since I suspect I don't have enough bandwidth to deal with > that soon. Yes, I'm glad to. I think what we need to do is to fix some Zdinx issues? :-) And, I think I have to explain the background here: I started to maintain this patch about two years ago when I was in T-head, since they have some old RV32E cores (AFAIK, SiFive has RV32E cores too?) and some customers needed the support of RV32E/ilp32e. Now, both T-head and SiFive didn't release RV32E cores any more, and the RVI doesn't put its focuses on RVE too I think. But I don't think there is no vendor that developed or developing their own RV32E implementations. Now I am no longer working at T-head and my current work is not about RV32E, so I don't have environment to test it. But I think this patch can work just fine since it has been used in T-head's downstream for a long time (since LLVM 13, IIRC) and @zixuan-wu has reported several issues (already solved) before. Apart from vendors' need, the request is mainly from Rust language community I think. IIUC, this is for the Rust implementation of SBI (https://github.com/rustsbi/rustsbi). They are using T-head E902 (rv32em?) and RV32E core from SiFive. So, yeah, I will try my best to fix the ABI issue, but I think we still need the help of the RISC-V community. I will contact with T-head guys to see if they are interested in this. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
kito-cheng wrote: @wangpc-pp did you have interested on helping psABI side? it would be great if you can help since I suspect I don't have enough bandwidth to deal with that soon. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
kito-cheng wrote: Hmmm, RISC-V ISA is growth after https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/257 again, I mean...we have zfinx and zdinx, which is also valid combination with rv32e/rv64e, so we may need to revise ilp32e ABI again on the psABI side, but my intention is not to block this PR. Anyway, I think we could track that on psABI repo, and we...already has an old issue to track that: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/269 https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
asb wrote: The conclusion from the previous review was this was OK to merge. I think I held it up by not responding to a ping (apologies). I've had another scan through and don't see a problem with merging this and considering it experimental once Craig's review comments are addressed. For the psABI, there's a gap here I think as GCC and LLVM need to deviate from what is currently written. I think https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/257 tried to partially address this. I wonder if we need a tracking issue in that repo to try to get this properly documented via that PR or otherwise (what do you think @jrtc27 @kito-cheng?). https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
@@ -68,6 +68,11 @@ ABI computeTargetABI(const Triple , const FeatureBitset
,
TargetABI = ABI_Unknown;
}
+ if ((TargetABI == RISCVABI::ABI::ABI_ILP32E ||
+ (TargetABI == ABI_Unknown && IsRVE && !IsRV64)) &&
+ FeatureBits[RISCV::FeatureStdExtD])
+report_fatal_error("ILP32E must not be used with the D ISA extension");
topperc wrote:
"must not" -> "cannot"
https://github.com/llvm/llvm-project/pull/76777
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[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
@@ -17134,30 +17133,64 @@ static const MCPhysReg ArgVRM4s[] = {RISCV::V8M4,
RISCV::V12M4, RISCV::V16M4,
RISCV::V20M4};
static const MCPhysReg ArgVRM8s[] = {RISCV::V8M8, RISCV::V16M8};
-ArrayRef RISCV::getArgGPRs() {
- static const MCPhysReg ArgGPRs[] = {RISCV::X10, RISCV::X11, RISCV::X12,
- RISCV::X13, RISCV::X14, RISCV::X15,
- RISCV::X16, RISCV::X17};
+ArrayRef RISCV::getArgGPRs(const RISCVABI::ABI ABI) {
+ // The GPRs used for passing arguments in the ILP32* and LP64* ABIs, except
+ // the ILP32E ABI.
+ static const MCPhysReg ArgIGPRs[] = {RISCV::X10, RISCV::X11, RISCV::X12,
+ RISCV::X13, RISCV::X14, RISCV::X15,
+ RISCV::X16, RISCV::X17};
+ // The GPRs used for passing arguments in the ILP32E/ILP64E ABI.
+ static const MCPhysReg ArgEGPRs[] = {RISCV::X10, RISCV::X11, RISCV::X12,
+ RISCV::X13, RISCV::X14, RISCV::X15};
+
+ if (ABI == RISCVABI::ABI_ILP32E || ABI == RISCVABI::ABI_LP64E)
+return ArrayRef(ArgEGPRs);
+
+ return ArrayRef(ArgIGPRs);
+}
+
+static ArrayRef getFastCCArgGPRs(const RISCVABI::ABI ABI) {
+ // The GPRs used for passing arguments in the FastCC, X5 and X6 might be used
+ // for save-restore libcall, so we don't use them.
+ static const MCPhysReg FastCCIGPRs[] = {
+ RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14,
+ RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X7, RISCV::X28,
+ RISCV::X29, RISCV::X30, RISCV::X31};
+
+ // The GPRs used for passing arguments in the FastCC when using
ILP32E/ILP64E.
+ static const MCPhysReg FastCCEGPRs[] = {RISCV::X10, RISCV::X11, RISCV::X12,
+ RISCV::X13, RISCV::X14, RISCV::X15,
+ RISCV::X7};
- return ArrayRef(ArgGPRs);
+ if (ABI == RISCVABI::ABI_ILP32E || ABI == RISCVABI::ABI_LP64E)
+return ArrayRef(FastCCEGPRs);
+
+ return ArrayRef(FastCCIGPRs);
}
// Pass a 2*XLEN argument that has been split into two XLEN values through
// registers or the stack as necessary.
static bool CC_RISCVAssign2XLen(unsigned XLen, CCState , CCValAssign VA1,
ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2,
MVT ValVT2, MVT LocVT2,
-ISD::ArgFlagsTy ArgFlags2) {
+ISD::ArgFlagsTy ArgFlags2, bool EABI) {
unsigned XLenInBytes = XLen / 8;
- ArrayRef ArgGPRs = RISCV::getArgGPRs();
+ const RISCVSubtarget =
+ State.getMachineFunction().getSubtarget();
+ ArrayRef ArgGPRs = RISCV::getArgGPRs(STI.getTargetABI());
+
if (Register Reg = State.AllocateReg(ArgGPRs)) {
// At least one half can be passed via register.
State.addLoc(CCValAssign::getReg(VA1.getValNo(), VA1.getValVT(), Reg,
VA1.getLocVT(), CCValAssign::Full));
} else {
// Both halves must be passed on the stack, with proper alignment.
+// TODO: To be compatible with GCC's behaviors, we force them to have
4-byte
+// alignment. This behavior may be changed when RV32E/ILP32E is ratified.
Align StackAlign =
-std::max(Align(XLenInBytes), ArgFlags1.getNonZeroOrigAlign());
+EABI && XLen == 32
topperc wrote:
```
Align StackAlign(XLenInBytes);
if (!EABI || XLen != 32)
StackAlign = std::max(StackAlign, ArgFlags1.getNonZeroOrigAlign());
```
https://github.com/llvm/llvm-project/pull/76777
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[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
@@ -499,7 +514,8 @@ void RISCVFrameLowering::emitPrologue(MachineFunction ,
if (int LibCallRegs = getLibCallID(MF, MFI.getCalleeSavedInfo()) + 1) {
// Calculate the size of the frame managed by the libcall. The libcalls are
// implemented such that the stack will always be 16 byte aligned.
topperc wrote:
Does this comment about 16 byte aligned need to be updated?
https://github.com/llvm/llvm-project/pull/76777
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[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
@@ -0,0 +1,221 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv64 -target-abi lp64e -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=RV64I-LP64E-FPELIM %s +; RUN: llc -mtriple=riscv64 -target-abi lp64e -verify-machineinstrs -frame-pointer=all < %s \ +; RUN: | FileCheck -check-prefix=RV64I-LP64E-WITHFP %s + +; As well as calling convention details, we check that ra and fp are +; consistently stored to fp-8 and fp-16. + +; Any tests that would have identical output for some combination of the lp64* topperc wrote: This comment isn't accurate for this test. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
topperc wrote: What was the last bit of discussion on the phabricator review? I can no longer access it. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
llvmbot wrote: @llvm/pr-subscribers-clang Author: Wang Pengcheng (wangpc-pp) Changes This commit includes the necessary changes to clang and LLVM to support codegen of `RVE` and the `ilp32e`/`lp64e` ABIs. The differences between `RVE` and `RVI` are: * `RVE` reduces the integer register count to 16(x0-x16). * The ABI should be `ilp32e` for 32 bits and `lp64e` for 64 bits. `RVE` can be combined with all current standard extensions. The central changes in ilp32e/lp64e ABI, compared to ilp32/lp64 are: * Only 6 integer argument registers (rather than 8). * Only 2 callee-saved registers (rather than 12). * A Stack Alignment of 32bits (rather than 128bits). * ilp32e isn't compatible with D ISA extension. If `ilp32e` or `lp64` is used with an ISA that has any of the registers x16-x31 and f0-f31, then these registers are considered temporaries. To be compatible with the implementation of ilp32e in GCC, we don't use aligned registers to pass variadic arguments and set stack alignment\ to 4-bytes for types with length of 2*XLEN. FastCC is also supported on RVE, while GHC isn't since there is only one avaiable register. Differential Revision: https://reviews.llvm.org/D70401 --- Patch is 422.14 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/76777.diff 45 Files Affected: - (modified) clang/docs/ReleaseNotes.rst (+2) - (modified) clang/lib/Basic/Targets/RISCV.cpp (+13-1) - (modified) clang/lib/Basic/Targets/RISCV.h (+12) - (modified) clang/lib/CodeGen/CodeGenModule.cpp (+2-1) - (modified) clang/lib/CodeGen/TargetInfo.h (+2-1) - (modified) clang/lib/CodeGen/Targets/RISCV.cpp (+25-10) - (modified) clang/lib/Driver/ToolChains/Arch/RISCV.cpp (+4) - (modified) clang/test/CodeGen/RISCV/riscv32-abi.c (+3) - (added) clang/test/CodeGen/RISCV/riscv32-ilp32e-error.c (+4) - (modified) clang/test/CodeGen/RISCV/riscv32-vararg.c (+421-141) - (modified) clang/test/CodeGen/RISCV/riscv64-abi.c (+4) - (modified) clang/test/CodeGen/RISCV/riscv64-vararg.c (+2) - (modified) clang/test/Preprocessor/riscv-target-features.c (+22) - (modified) llvm/docs/RISCVUsage.rst (+6) - (modified) llvm/docs/ReleaseNotes.rst (+2) - (modified) llvm/include/llvm/Support/RISCVAttributes.h (+1-1) - (modified) llvm/lib/Support/RISCVISAInfo.cpp (+4-4) - (modified) llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp (+1-1) - (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp (+5) - (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp (+8-5) - (modified) llvm/lib/Target/RISCV/RISCVCallingConv.td (+14-1) - (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+7) - (modified) llvm/lib/Target/RISCV/RISCVFrameLowering.cpp (+21-3) - (modified) llvm/lib/Target/RISCV/RISCVFrameLowering.h (+1-6) - (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+65-28) - (modified) llvm/lib/Target/RISCV/RISCVISelLowering.h (+1-1) - (modified) llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp (+17-3) - (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+13-3) - (modified) llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll (+432-2) - (modified) llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll (+216-1) - (modified) llvm/test/CodeGen/RISCV/callee-saved-gprs.ll (+530) - (added) llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll (+2556) - (added) llvm/test/CodeGen/RISCV/calling-conv-lp64e.ll (+221) - (added) llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32e.ll (+83) - (modified) llvm/test/CodeGen/RISCV/interrupt-attr.ll (+745) - (added) llvm/test/CodeGen/RISCV/rv32e.ll (+25) - (added) llvm/test/CodeGen/RISCV/rv64e.ll (+25) - (removed) llvm/test/CodeGen/RISCV/rve.ll (-8) - (modified) llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll (+60) - (modified) llvm/test/CodeGen/RISCV/stack-realignment.ll (+652) - (modified) llvm/test/CodeGen/RISCV/target-abi-valid.ll (+4-5) - (added) llvm/test/CodeGen/RISCV/vararg-ilp32e.ll (+148) - (modified) llvm/test/CodeGen/RISCV/vararg.ll (+1261) - (modified) llvm/test/MC/RISCV/option-invalid.s (-3) - (modified) llvm/test/MC/RISCV/target-abi-invalid.s (+6-3) ``diff diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 0c8fec691bf3c9..aa8d27f5c17551 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -971,6 +971,8 @@ RISC-V Support ^^ - Unaligned memory accesses can be toggled by ``-m[no-]unaligned-access`` or the aliases ``-m[no-]strict-align``. +- CodeGen of RV32E/RV64E are supported experimentally. +- CodeGen of ilp32e/lp64e are supported experimentally. - Default ABI with F but without D was changed to ilp32f for RV32 and to lp64f for RV64. diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp index 6bc57a83a2d5ae..8db989df04c87b 100644 --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -154,7 +154,7 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions ,
