Re: [coreboot] [RFC] CMOS options
On Sat, Dec 12, 2009 at 02:30:01PM +0100, Stefan Reinauer wrote: On 12/11/09 8:39 PM, ron minnich wrote: On Wed, Dec 9, 2009 at 2:57 AM, Andrew Goodbody andrew.goodb...@tadpole.com wrote: Luc Verhaegen wrote: We have 892 bytes to our disposal in cmos. We can reserve 128 for board/cmos versioning, and reserve even 256 for the bootloader, and still have 512bytes left for coreboot options, which is tons when bits are used properly and when strings are not used. Most boards I have used have a maximum space of 256 bytes that includes the RTC. Where does the extra come from? On much of my hardware, the most I can assume is 128 bytes - subtracting many bytes that are weirdly hardware controlled (such as date). Some of our hardware has 256 bytes. The io ports only support an 8-bit address I thought? The ports 0x70/0x71 even only support 7 bits... The 8th bit is used for NMI control. Higher CMOS bytes can be accessed by 0x72/0x73, 0x74/0x75 However, if you try to access the upper 128 bytes by setting the topmost bit in 0x70 it will just look like the upper 128 byte are a mirror of the lower 128 bytes. Stefan Ah, my bad, i guess 1024 bits is why my synapses brought up that figure. Still, it should still be possible to segment this up nicely, and then we suddenly do have a lot of space for bools, sets and integers. And maybe a string or two to denote the board. Luc Verhaegen -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Problems compiling H8DMR_FAM10 because of section overlaps.
Hello, I'm now trying to get coreboot working on a Supermicro H8QME-2+ board. This board is really similar to the H8DMR/H8DMR_FAM10 boards already supported by coreboot. Since my board is populated with 4 Opteron family 10 processors I thought of trying to compile the H8DMR_FAM10 to get a rom and flash it to board to see what happens. But compiling I got the section overlaps error since its recommended to increase the ROM_IMAGE_SIZE I added the following lines to Kconfig: config ROM_IMAGE_SIZE hex default 0x15800 depends on BOARD_SUPERMICRO_H8DMR_FAM10 than a made a make distclean, make config, make and got following message: /usr/lib64/gcc/x86_64-suse-linux/4.3/../../../../x86_64-suse-linux/bin/ld: section .reset [fff0 - ] overlaps section .rom [5800 - 0001929f] /usr/lib64/gcc/x86_64-suse-linux/4.3/../../../../x86_64-suse-linux/bin/ld: /home/knut/Documents/Supertrunk4978/build/coreboot: section .reset vma 0xfff0 overlaps previous sections Taking a good look at the ranges I increased ROM_SIZE to 0x1 and it worked but not at all because: /usr/lib64/gcc/x86_64-suse-linux/4.3/../../../../x86_64-suse-linux/bin/ld: section .id [0001fffeff58 - 0001fffeff7f] overlaps section .rom [0001fffe - 00013a9f] /usr/lib64/gcc/x86_64-suse-linux/4.3/../../../../x86_64-suse-linux/bin/ld: /home/knut/Documents/Supertrunk4978/build/coreboot: section .id vma 0x1fffeff58 overlaps previous sections /usr/lib64/gcc/x86_64-suse-linux/4.3/../../../../x86_64-suse-linux/bin/ld: /home/knut/Documents/Supertrunk4978/build/coreboot: section .romstrap vma 0x1fffeffa0 overlaps previous sections now it's .id that overlaps section .rom and not .reset :( Now I followed the instructions on the coreboot side about section overlaps and I did this: 00013a9f-0001fffeff58= 3b47 = 3b48 config ROM_IMAGE_SIZE hex default 0x13b48 depends on BOARD_SUPERMICRO_H8DMR_FAM10 make distclean, make config, make and got /usr/lib64/gcc/x86_64-suse-linux/4.3/../../../../x86_64-suse-linux/bin/ld: section .id [00013aa0 - 00013ac7] overlaps section .rom [0001fffe3b48 - 000175ef] /usr/lib64/gcc/x86_64-suse-linux/4.3/../../../../x86_64-suse-linux/bin/ld: /home/knut/Documents/Supertrunk4978/build/coreboot: section .id vma 0x13aa0 overlaps previous sections /usr/lib64/gcc/x86_64-suse-linux/4.3/../../../../x86_64-suse-linux/bin/ld: /home/knut/Documents/Supertrunk4978/build/coreboot: section .romstrap vma 0x13ae8 overlaps previous sections I can see that no only the .rom range changed but also the .id range should it do that?? So what can I do to make it work? A little frustrated I successfully compiled the H8DMR rom and flashed it into the bios chip thinking that at least some debug messages should appear since on both boards the way to the winbond chip is the same but I only got some ·$·)?· rubbish. I of course tested the serial before and it worked fine. thanks, Knut Kujat. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Problems compiling H8DMR_FAM10 because of section overlaps.
Am 16.12.2009 15:30, schrieb Knut Kujat: Hello, I'm now trying to get coreboot working on a Supermicro H8QME-2+ board. This board is really similar to the H8DMR/H8DMR_FAM10 boards already supported by coreboot. Since my board is populated with 4 Opteron family 10 processors I thought of trying to compile the H8DMR_FAM10 to get a rom and flash it to board to see what happens. But compiling I got the section overlaps error since its recommended to increase the ROM_IMAGE_SIZE I added the following lines to Kconfig: Fam10 is not supported with kconfig yet. Regards, Patrick Georgi -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Problems compiling H8DMR_FAM10 because of section overlaps.
Patrick Georgi escribió: Am 16.12.2009 15:30, schrieb Knut Kujat: Hello, I'm now trying to get coreboot working on a Supermicro H8QME-2+ board. This board is really similar to the H8DMR/H8DMR_FAM10 boards already supported by coreboot. Since my board is populated with 4 Opteron family 10 processors I thought of trying to compile the H8DMR_FAM10 to get a rom and flash it to board to see what happens. But compiling I got the section overlaps error since its recommended to increase the ROM_IMAGE_SIZE I added the following lines to Kconfig: Fam10 is not supported with kconfig yet. Regards, Patrick Georgi Aham, thx for the hint. Now it worked building it with ./builtarget but I'm only getting rubbish from the serial using standard settings 115200 8n1. Some suggestions? thx, Knut Kujat. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Problems compiling H8DMR_FAM10 because of section overlaps.
Knut Kujat wrote: I'm only getting rubbish from the serial using standard settings 115200 8n1. Some suggestions? Try all other speeds. It's not uncommon for a clock multiplier to be off, causing double or half the expected speed. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Problems compiling H8DMR_FAM10 because of section overlaps.
On Wed, Dec 16, 2009 at 10:04 AM, Peter Stuge pe...@stuge.se wrote: Knut Kujat wrote: I'm only getting rubbish from the serial using standard settings 115200 8n1. Some suggestions? Try all other speeds. It's not uncommon for a clock multiplier to be off, causing double or half the expected speed. As Peter said, it is probably the SIO clock setting. Check the setup in cach_as_ram_auto.c. Marc -- http://marcjonesconsulting.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r4979 - trunk/targets/supermicro/h8dmr_fam10
Author: ward Date: 2009-12-16 20:48:45 +0100 (Wed, 16 Dec 2009) New Revision: 4979 Modified: trunk/targets/supermicro/h8dmr_fam10/VERSION Log: Make sure that the h8dmr_fam10 has the proper version string. This is a trivial patch. Signed-off-by: Ward Vandewege w...@gnu.org Acked-by: Ward Vandewege w...@gnu.org Modified: trunk/targets/supermicro/h8dmr_fam10/VERSION === --- trunk/targets/supermicro/h8dmr_fam10/VERSION2009-12-14 21:52:56 UTC (rev 4978) +++ trunk/targets/supermicro/h8dmr_fam10/VERSION2009-12-16 19:48:45 UTC (rev 4979) @@ -1 +1 @@ -_h8dmr +_h8dmr_fam10 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Serial Console option (was Coreboot fails to initialize on ASUS A8V-E SE)
On 12/15/2009 01:47 PM, ron minnich wrote: On Tue, Dec 15, 2009 at 10:29 AM, Myles Watsonmyle...@gmail.com wrote: I guess I was looking at it more like this: All the boards that we support have serial ports. If we have a serial port it makes sense to enable it. The option to disable the serial port should disappear because it can be subsumed in the I have a serial port (CONFIG_SUPERIO_*) option. I can see your point, though. So, to fix the problem of Kconfig having options that break the build, you'd like to use #ifdefs, right? I have no idea to tell you the truth. I trust you more than I trust me :-) Hmm, I have been doing a little research lately on a Wyse terminal with a Geode that doesn't have a superio or per say an official serial port. I know the southbridge supports UART ports but will this throw a wrench into things? Especially what you are talking about above? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Serial Console option (was Coreboot fails to initialize on ASUS A8V-E SE)
Hmm, I have been doing a little research lately on a Wyse terminal with a Geode that doesn't have a superio or per say an official serial port. I know the southbridge supports UART ports but will this throw a wrench into things? Especially what you are talking about above? I don't think it will be a problem. I'm not going to change anything for now. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Asrock 939A785GMH/128M - socket 939 + AMD 785G
Hello all, Just FYI. I bought this motherboard. It has the socket 939, newest AMD 785G! It has 1MB socketed SPI flash. The superio is W83627DHG. SB is 710. Looking forward for the AMD code :) The serial is on header. Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] The function int15 running on the Technexion's tim5690.
Hello,
I modified int15_handler on mainboard.
The VGA BIOS is through int15 getting LCD panel's ID. Then the VBIOS
call int15.
The panel's ID is selection by switch.
This functions is reference AMD RS690 ASIC Family BIOS Developer’s
Guide.
Thanks.
Signed-off-by: Libra Li libra...@technexion.com
2009/12/16 ron minnich rminn...@gmail.com
On Tue, Dec 15, 2009 at 9:30 AM, Stefan Reinauer ste...@coresystems.de
wrote:
I think it should go to southbridge/amd/rs690, or even to the mainboard
directory, if it's about detecting a specific LCD version.
oops. You're right. Mainboard directory.
Should we use the weak symbols thing for attaching handlers like this?
So the default in yabel is a weak symbol and can be over-ridden by a
compiled in handler?
ron
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Index: src/mainboard/technexion/tim5690/Makefile.inc
===
--- src/mainboard/technexion/tim5690/Makefile.inc (revision 4977)
+++ src/mainboard/technexion/tim5690/Makefile.inc (working copy)
@@ -33,6 +33,7 @@
obj-y += tn_post_code.o
obj-y += speaker.o
+obj-y += vgabios.o
# This is part of the conversion to init-obj and away from included code.
Index: src/mainboard/technexion/tim5690/cache_as_ram_auto.c
===
--- src/mainboard/technexion/tim5690/cache_as_ram_auto.c (revision 4977)
+++ src/mainboard/technexion/tim5690/cache_as_ram_auto.c (working copy)
@@ -145,20 +145,6 @@
}
#endif/* CONFIG_USE_FALLBACK_IMAGE == 1 */
-/* Early mainboard specific GPIO setup. */
-static void mb_gpio_init(void)
-{
- /* Init Super I/O GPIOs. Done early. */
- it8712f_enter_conf();
- outb(IT8712F_CONFIG_REG_LDN, SIO_INDEX);
- outb(IT8712F_GPIO, SIO_DATA);
- outb(0x62, SIO_INDEX); // set Simple I/O Base Address 0x200
- outb(0x02, SIO_DATA);
- outb(0x63, SIO_INDEX);
- outb(0x00, SIO_DATA);
- it8712f_exit_conf();
-}
-
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -191,7 +177,6 @@
/* it8712f_enable_serial does not use its 1st parameter. */
it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
- mb_gpio_init();
it8712f_kill_watchdog();
uart_init();
console_init();
Index: src/mainboard/technexion/tim5690/mainboard.c
===
--- src/mainboard/technexion/tim5690/mainboard.c (revision 4977)
+++ src/mainboard/technexion/tim5690/mainboard.c (working copy)
@@ -26,13 +26,56 @@
#include cpu/amd/mtrr.h
#include device/pci_def.h
#include ../southbridge/amd/sb600/sb600.h
+#include ../superio/ite/it8712f/it8712f.h
#include chip.h
#include tn_post_code.h
+#include vgabios.h
#define ADT7461_ADDRESS 0x4C
#define ARA_ADDRESS 0x0C /* Alert Response Address */
#define SMBUS_IO_BASE 0x1000
+
+/* Video BIOS Function Extensions Specification
+ */
+//Callback Sub-Function 00h - Get LCD Panel ID
+#define LCD_PANEL_ID_NO 0x00 /* No LCD */
+#define LCD_PANEL_ID_01 0x01 /* 1024x768, 24 bits, 1 channel */
+#define LCD_PANEL_ID_02 0x02 /* 1280x1024, 24 bits, 2 channels */
+#define LCD_PANEL_ID_03 0x03 /* 1440x900, 24 bits, 2 channels */
+#define LCD_PANEL_ID_04 0x04 /* 1680x1050, 24 bits, 2 channels */
+#define LCD_PANEL_ID_05 0x05 /* 1920x1200, 24 bits, 2 channels */
+#define LCD_PANEL_ID_06 0x06 /* 1920x1080, 24 bits, 2 channels */
+//Callback Sub-Function 05h – Select Boot-up TV Standard
+#define TV_MODE_00 0x00 /* NTSC */
+#define TV_MODE_01 0x01 /* PAL */
+#define TV_MODE_02 0x02 /* PALM */
+#define TV_MODE_03 0x03 /* PAL60 */
+#define TV_MODE_04 0x04 /* NTSCJ */
+#define TV_MODE_05 0x05 /* PALCN */
+#define TV_MODE_06 0x06 /* PALN */
+#define TV_MODE_09 0x09 /* SCART-RGB */
+#define TV_MODE_NO 0xff /* No TV Support */
+
+
+/* The base address is 0x2e or 0x4e, depending on config bytes. */
+#define SIO_BASE 0x2e
+#define SIO_INDEXSIO_BASE
+#define SIO_DATA SIO_BASE+1
+
+/* Global configuration registers. */
+#define IT8712F_CONFIG_REG_CC0x02 /* Configure Control (write-only). */
+#define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
+#define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
+#define IT8712F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
+#define IT8712F_CONFIG_REG_SWSUSP0x24 /* Software Suspend, Flash I/F. */
+#define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */
+#define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */
+
+#define IT8712F_CONFIGURATION_PORT 0x2e /* Write-only. */
+#define IT8712F_SIMPLE_IO_BASE 0x200 /* Simple I/O base address */
+
+
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
