Re: [coreboot] Help for motherboard
On 02/19/2011 01:39 PM, sh4...@gmail.com wrote: But I did not found here new Intel and AMD cpu for motherboards in Desktop/Workstation section (except Laptop) mentioned for e.g. Intel Core 7i Intel Core 3i Won't happen because Intel won't tell us how to initialize that hardware. So just stay away. and similar AMD's latest. Support for AMD Fam 14h just got added a few days ago. There are only two AMD boards that are currently supported. It's a very new product, so we don't have the boards (yet?). So finally I like to know do these newer CPU's any motherboard going to be supported in near future, So I will purchase that motherboard. Your board will be supported if you do the port yourself, or are lucky enough to have the same board as someone who has already ported (is doing the port). I'm working on the VIA VX900, so you could expect that to be supported in a couple of months (or earlier, depending on how difficult the chipset is). I want to find it out as it will be difficult to change hardware than software later. Please suggest which CPU/motherboard combination is good with coreboot. What do you want to do with your computer? For HTPC, VIA Nano is pretty good. For regular desktop, we have a few good AM3 boards supported. For workstation/server, you can get your hands dirty, get a single/dual-socket G34 board, and start porting. We have most infrastructure code for that, so it shouldn't be too hard. :) And someone wiser may give you a more complete answer. Alex -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r6373 - in trunk/src/superio: fintek/f71805f fintek/f71859 fintek/f71863fg fintek/f71872 fintek/f71889 intel/i3100 ite/it8712f ite/it8716f smsc/lpc47b272 smsc/lpc47b397 smsc/lpc47m
Author: ruik
Date: Sat Feb 19 15:51:31 2011
New Revision: 6373
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6373
Log:
It turns out that the code which enables specific LDN is somewhat buggy.
Instead of enable the device the device gets disabled. However after some time
the serial line gets back, most likely some enable resources might fix it.
I'm attaching patch which somewhat fixes the problem and changes the function
to look same in all superio code. Some boards even did not convert the
dev-enabled to 0,1 values.
Signed-off-by: Rudolf Marek r.ma...@assembler.cz
Acked-by: Peter Stuge pe...@stuge.se
Modified:
trunk/src/superio/fintek/f71805f/superio.c
trunk/src/superio/fintek/f71859/superio.c
trunk/src/superio/fintek/f71863fg/superio.c
trunk/src/superio/fintek/f71872/superio.c
trunk/src/superio/fintek/f71889/superio.c
trunk/src/superio/intel/i3100/superio.c
trunk/src/superio/ite/it8712f/superio.c
trunk/src/superio/ite/it8716f/superio.c
trunk/src/superio/smsc/lpc47b272/superio.c
trunk/src/superio/smsc/lpc47b397/superio.c
trunk/src/superio/smsc/lpc47m10x/superio.c
trunk/src/superio/smsc/lpc47m15x/superio.c
trunk/src/superio/smsc/lpc47n217/superio.c
trunk/src/superio/smsc/lpc47n227/superio.c
trunk/src/superio/smsc/smscsuperio/superio.c
trunk/src/superio/via/vt1211/vt1211.c
trunk/src/superio/winbond/w83627dhg/superio.c
trunk/src/superio/winbond/w83627ehg/superio.c
trunk/src/superio/winbond/w83627hf/superio.c
trunk/src/superio/winbond/w83697hf/superio.c
Modified: trunk/src/superio/fintek/f71805f/superio.c
==
--- trunk/src/superio/fintek/f71805f/superio.c Thu Feb 17 21:48:45 2011
(r6372)
+++ trunk/src/superio/fintek/f71805f/superio.c Sat Feb 19 15:51:31 2011
(r6373)
@@ -77,7 +77,7 @@
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
- (dev-enabled) ? pnp_set_enable(dev, 1) : pnp_set_enable(dev, 0);
+ pnp_set_enable(dev, !!dev-enabled);
pnp_exit_conf_state(dev);
}
Modified: trunk/src/superio/fintek/f71859/superio.c
==
--- trunk/src/superio/fintek/f71859/superio.c Thu Feb 17 21:48:45 2011
(r6372)
+++ trunk/src/superio/fintek/f71859/superio.c Sat Feb 19 15:51:31 2011
(r6373)
@@ -74,7 +74,7 @@
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
- (dev-enabled) ? pnp_set_enable(dev, 1) : pnp_set_enable(dev, 0);
+ pnp_set_enable(dev, !!dev-enabled);
pnp_exit_conf_state(dev);
}
Modified: trunk/src/superio/fintek/f71863fg/superio.c
==
--- trunk/src/superio/fintek/f71863fg/superio.c Thu Feb 17 21:48:45 2011
(r6372)
+++ trunk/src/superio/fintek/f71863fg/superio.c Sat Feb 19 15:51:31 2011
(r6373)
@@ -81,7 +81,7 @@
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
- (dev-enabled) ? pnp_set_enable(dev, 1) : pnp_set_enable(dev, 0);
+ pnp_set_enable(dev, !!dev-enabled);
pnp_exit_conf_state(dev);
}
Modified: trunk/src/superio/fintek/f71872/superio.c
==
--- trunk/src/superio/fintek/f71872/superio.c Thu Feb 17 21:48:45 2011
(r6372)
+++ trunk/src/superio/fintek/f71872/superio.c Sat Feb 19 15:51:31 2011
(r6373)
@@ -79,7 +79,7 @@
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
- (dev-enabled) ? pnp_set_enable(dev, 1) : pnp_set_enable(dev, 0);
+ pnp_set_enable(dev, !!dev-enabled);
pnp_exit_conf_state(dev);
}
Modified: trunk/src/superio/fintek/f71889/superio.c
==
--- trunk/src/superio/fintek/f71889/superio.c Thu Feb 17 21:48:45 2011
(r6372)
+++ trunk/src/superio/fintek/f71889/superio.c Sat Feb 19 15:51:31 2011
(r6373)
@@ -80,7 +80,7 @@
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
- (dev-enabled) ? pnp_set_enable(dev, 1) : pnp_set_enable(dev, 0);
+ pnp_set_enable(dev, !!dev-enabled);
pnp_exit_conf_state(dev);
}
Modified: trunk/src/superio/intel/i3100/superio.c
==
--- trunk/src/superio/intel/i3100/superio.c Thu Feb 17 21:48:45 2011
(r6372)
+++ trunk/src/superio/intel/i3100/superio.c Sat Feb 19 15:51:31 2011
(r6373)
@@ -78,7 +78,7 @@
{
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
- pnp_set_enable(dev, dev-enabled);
+ pnp_set_enable(dev, !!dev-enabled);
pnp_exit_ext_func_mode(dev);
}
Modified: trunk/src/superio/ite/it8712f/superio.c
Re: [coreboot] Help for motherboard
-Original Message- From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On Behalf Of Alex G. Sent: Saturday, February 19, 2011 08:17 AM To: coreboot@coreboot.org Subject: Re: [coreboot] Help for motherboard ]On 02/19/2011 01:39 PM, sh4...@gmail.com wrote: ] But I did not found here new Intel and AMD cpu for motherboards in ] Desktop/Workstation section (except Laptop) ] mentioned for e.g. ] Intel Core 7i ] Intel Core 3i ] ]Won't happen because Intel won't tell us how to initialize that ]hardware. So just stay away. ] ] and similar AMD's latest. ] ]Support for AMD Fam 14h just got added a few days ago. There are only ]two AMD boards that are currently supported. It's a very new product, so ]we don't have the boards (yet?). I found two AMD family 14h boards on sale at newegg.com: 1) ASRock E350M1 - US$ 109.99 2) GIGABYTE GA-E350N-USB3 - US$ 149.99 I ordered #1 because it has a serial port header. I will try to get coreboot working on it in my spare time. Board #2 looks interesting. It apparently has no serial port. But underneath is the pad for a jtag debugging header. I think soldering a header would allow the Sage SmartProbe (http://se-eng.com/) to work. Thanks, Scott ] So finally I like to know do these newer CPU's any motherboard going ] to be supported in near future, So I will purchase that motherboard. ] ]Your board will be supported if you do the port yourself, or are lucky ]enough to have the same board as someone who has already ported (is ]doing the port). ] ]I'm working on the VIA VX900, so you could expect that to be supported ]in a couple of months (or earlier, depending on how difficult the ]chipset is). ] ] I want to find it out as it will be difficult to change hardware than ] software later. Please suggest which CPU/motherboard combination is ] good with coreboot. ] ]What do you want to do with your computer? ]For HTPC, VIA Nano is pretty good. ]For regular desktop, we have a few good AM3 boards supported. ]For workstation/server, you can get your hands dirty, get a ]single/dual-socket G34 board, and start porting. We have most ]infrastructure code for that, so it shouldn't be too hard. :) ] ]And someone wiser may give you a more complete answer. ] ]Alex -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Help for motherboard
On Sat, Feb 19 2011, Alex G. wrote: On 02/19/2011 01:39 PM, sh4...@gmail.com wrote: But I did not found here new Intel and AMD cpu for motherboards in Desktop/Workstation section (except Laptop) mentioned for e.g. Intel Core 7i Intel Core 3i Won't happen because Intel won't tell us how to initialize that hardware. So just stay away. I was not aware. and similar AMD's latest. Support for AMD Fam 14h just got added a few days ago. There are only two AMD boards that are currently supported. It's a very new product, so we don't have the boards (yet?). So finally I like to know do these newer CPU's any motherboard going to be supported in near future, So I will purchase that motherboard. Your board will be supported if you do the port yourself, or are lucky enough to have the same board as someone who has already ported (is doing the port). I'm working on the VIA VX900, so you could expect that to be supported in a couple of months (or earlier, depending on how difficult the chipset is). I want to find it out as it will be difficult to change hardware than software later. Please suggest which CPU/motherboard combination is good with coreboot. What do you want to do with your computer? For HTPC, VIA Nano is pretty good. For regular desktop, we have a few good AM3 boards supported. For workstation/server, you can get your hands dirty, get a single/dual-socket G34 board, and start porting. We have most infrastructure code for that, so it shouldn't be too hard. :) I wanted general purpose regular desktop for programming, internet, GNU/Linux with common servers dovecote, tomcat, apache etc And someone wiser may give you a more complete answer. -- Regards, -sharad -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Help for motherboard
On 02/19/2011 06:58 PM, sh4...@gmail.com wrote: I wanted general purpose regular desktop for programming, internet, GNU/Linux with common servers dovecote, tomcat, apache etc Probably a socket AM2+ board will be best for you if you want to run coreboot. The Gigabyte GA-MA785GMT-UD2H is the only AM3 board supported. Someone recently had a problem getting it to run, but at worst, it needs a bit of tweaking. It has a COM port header, so we can use that to debug if something may not be working. It doesn't include the adapter for the com port, but that should be cheap to get. http://www.coreboot.org/GIGABYTE_GA-MA785GMT-UD2H The board has 4 hardware versions, so you may encounter issues depending on which version you get. I'd definitely suggest AM3 versus the older AM2/AM2+. You can also pick your favorite board and port it (which we'd all love :p ). Alex -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] disabling microcode update
On Fri, Feb 18, 2011 at 10:19:31AM -0500, Ward Vandewege wrote:
Hi Xavi,
On Wed, Feb 16, 2011 at 02:45:02PM +0100, Xavi Drudis Ferran wrote:
Should I send a patch making a Kconfig option to not upgrade microcode for
fam10? Is there any interest in that ?
Yes, please. I would test and ack that.
Thanks,
Ward.
Here it is. It's limited to fam10. I don't know about other families nor can
test.
Sorry about having missed the request from Ivaylo, for a moment I
thought I was the only one interested.
It works in my board (but my board still does not boot, so tests in
functional boards are welcome).
Thanks. Allow the user to disable cpu microcode updating
(only for AMD model_10xxx cpus) in make menuconfig.
If disabled the microcode is not included in
update_microcode.c and therefore the generate image
does not include it.
Signed-off-by: Xavi Drudis Ferran xdru...@tinet.cat
---
I've abuild tested it with default y and default n,
not sure if abuild build with all default options and
so both cases are tested or I should do something else.
--- src/cpu/amd/model_10xxx/Kconfig 2011-02-19 21:56:44.0 +0100
+++ src/cpu/amd/model_10xxx/Kconfig 2011-02-19 19:48:20.0 +0100
@@ -50,3 +50,22 @@
endif
endif
+
+config UPDATE_CPU_MICROCODE
+ bool Update cpu microcode
+ default y
+ depends on CPU_AMD_MODEL_10XXX
+help
+ Select this to apply (propietary?) patches to the cpu
+ microcode provided by AMD to correct issues in the CPU after
+ production, and distributed with coreboot (not necessarily
+ the latest microcode version produced by AMD, but only
+ applied if newer than the version in your CPU).
+
+ Unselect to let FAM10 CPUs run with factory microcode. If
+ you unselect this, no binary microcode patches will be
+ included in the image, so it will help you get an image
+ which you have the entire source code for and may simplify
+ license compliance (IANAL).
+
+
--- src/cpu/amd/model_10xxx/update_microcode.c 2011-02-19 21:56:44.0 +0100
+++ src/cpu/amd/model_10xxx/update_microcode.c 2011-02-19 22:09:17.0 +0100
@@ -29,6 +29,7 @@
#include cpu/amd/microcode.h
#endif
+#if CONFIG_UPDATE_CPU_MICROCODE
static const u8 microcode_updates[] __attribute__ ((aligned(16))) = {
#ifdef __PRE_RAM__
@@ -93,9 +94,11 @@
return new_id;
}
+#endif
void update_microcode(u32 cpu_deviceid)
{
+#if CONFIG_UPDATE_CPU_MICROCODE
u32 equivalent_processor_rev_id;
/* Update the microcode */
@@ -105,5 +108,6 @@
} else {
printk(BIOS_DEBUG, microcode: rev id not found. Skipping microcode patch!\n);
}
+#endif
}
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] P2B-LS help: Onboard SCSI BIOS failed to boot
Raised debug level in SeaBIOS. Here is what's new from Running option rom at c800:0003 in the old log: pmm call arg1=0 pmm00: length=1000 handle=29400131 flags=1 pmm_malloc zone=0x000f5770 handle=29400131 size=65536 align=10 ret=0x0008 () pmm call arg1=0 pmm00: length=400 handle=29400132 flags=1 pmm_malloc zone=0x000f5770 handle=29400132 size=16384 align=10 ret=0x0007c000 () pnp call arg1=60 pnp call arg1=61 invalid handle_1ab103:78: a=b103 b= c=0001 d=03bc ds=8000 es=7c00 ss= si=0001 di=5387 bp=6ab2 sp=6ab0 cs=8000 ip=9f11 f=0002 This is the Ralf Brown Interrupt List entry for the call being made: X-1AB103- INT 1A - PCI BIOS v2.0c+ - FIND PCI CLASS CODE AX = B103h ECX = class code (see also #F0085,#00878) bits 31-24 unused bits 23-16 class bits 15-8 subclass bits 7-0 programming interface SI = device index (0-n) Return: CF clear if successful CF set on error AH = status (00h,86h) (see #00729) 00h successful BH = bus number BL = device/function number (bits 7-3 device, bits 2-0 func) 86h device not found EAX, EBX, ECX, and EDX may be modified all other flags (except IF) may be modified Notes: this function may require up to 1024 byte of stack; it will not enable interrupts if they were disabled before making the call the meanings of BL and BH on return were exchanged between the initial drafts of the specification and final implementation all devices sharing the same Class Code may be enumerated by incrementing SI from 0 until error 86h is returned SeeAlso: AX=B183h --- It's looking for the second mass storage device in the system, which seems perfectly reasonable. So some PCI bios support seems to be amiss. Something to take to SeaBIOS mailing list? Also I'm finding without the option rom added, Linux now was able to load aic7xxx module and assign an irq to it. I'm not having fun on the SerialICE front. The Fedora qemu is 0.13.0; 0.14.0 has just been released. I have to download 0.11.0 per instructions. I'm using lua 5.1.4 as provided by Fedora, because I'm not sure if my 64bit laptop needs any patch. Website says patch needed on 32bit platforms; the patch is about 64bit. Then once I have the SerialICE chip flashed, qemu patched and compiled, lua stuff in place, then it complains it cannot index 'regs' because it's nil. So I have no access to any registers and no idea where things are going because I can't see CS:EIP. I'm using the P2B support on P2B-LS. Again I'm trying to figure out how to switch on/off termination for the onboard SCSI. I think I am stuck and need more help. Thanks Keith On Sat, Feb 19, 2011 at 8:31 AM, Idwer Vollering vid...@gmail.com wrote: 2011/2/19 Keith Hui buu...@gmail.com: I am trying (again) to get the Adaptec SCSI on my P2B-LS to initialize properly with coreboot. But it won't boot. Attached is a serial log of what happened. After compiling coreboot I checked out SeaBIOS through git and added the SCSI option rom extracted from my factory bios. A port and a few other resources is assigned, but no IRQ. The SCSI option rom would initialize, I can press the hotkey to enter the utility, but that's it. That option rom hangs before getting any responses from the SCSI hardware. You want to see what happens during execution. Can you create a separate git tree ( git clone git://git.seabios.org/seabios.git dirname_of_choice ) where you run make menuconfig in, then set CONFIG_DEBUG_LEVEL to 8 (make menuconfig debugging debug level) ? Have a look at the other options too, maybe. Add the resulting file (out/bios.bin.elf) as the payload. I am trying to set up SerialICE to see what is going on. Just looking for some insights before I reach that point. I have to jumper off the SCSI to get it to boot. I don't know if this has anything to do but the Ultra2 port on my other P2B-LS is fubared and nothing plugged there would register. Afraid the same may befall this board too. I have an unused dawicontrol dc-974 (scsi2 ?) that I should try booting off. Thanks Keith -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
