[coreboot] Patch set updated: 367bfb7 cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.
Keith Hui (buu...@gmail.com) just uploaded a new patch set to gerrit, which you
can find at http://review.coreboot.org/122
-gerrit
commit 367bfb756f320019b0ea316a98dd260754cade4f
Author: Keith Hui buu...@gmail.com
Date: Wed Jul 27 23:06:16 2011 -0400
cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.
Bring from coreboot v1 support for initializing L2 cache on Slot 1
Pentium II/III CPUs, code names Klamath, Deschutes and Katmai.
Build tested on ASUS P2B-LS and P3B-F. Boot tested on P2B-LS with
Pentium III 600MHz, Katmai core.
Also add missing include of model_68x in slot_1, to address a
similar problem seen before r5945.
Change-Id: I502e8481d1a20f0a2504685e7be16b57f59c8257
Signed-off-by: Keith Hui buu...@gmail.com
---
src/cpu/intel/model_65x/model_65x_init.c |3 +
src/cpu/intel/model_67x/model_67x_init.c |4 +
src/cpu/intel/slot_1/Makefile.inc|2 +
src/cpu/intel/slot_1/l2_cache.c | 810 ++
src/include/cpu/intel/l2_cache.h | 102
5 files changed, 921 insertions(+), 0 deletions(-)
diff --git a/src/cpu/intel/model_65x/model_65x_init.c
b/src/cpu/intel/model_65x/model_65x_init.c
index 8f9fc66..dc889d8 100644
--- a/src/cpu/intel/model_65x/model_65x_init.c
+++ b/src/cpu/intel/model_65x/model_65x_init.c
@@ -27,6 +27,7 @@
#include cpu/x86/lapic.h
#include cpu/intel/microcode.h
#include cpu/x86/cache.h
+#include cpu/intel/l2_cache.h
static u32 microcode_updates[] = {
#include microcode-410-MU16522d.h
@@ -64,6 +65,8 @@ static void model_65x_init(device_t dev)
/* Update the microcode */
intel_update_microcode(microcode_updates);
+ p6_configure_l2_cache();
+
/* Enable the local cpu apics */
setup_lapic();
};
diff --git a/src/cpu/intel/model_67x/model_67x_init.c
b/src/cpu/intel/model_67x/model_67x_init.c
index 76a840e..12cb3a1 100644
--- a/src/cpu/intel/model_67x/model_67x_init.c
+++ b/src/cpu/intel/model_67x/model_67x_init.c
@@ -26,6 +26,7 @@
#include cpu/intel/microcode.h
#include cpu/x86/cache.h
#include cpu/x86/msr.h
+#include cpu/intel/l2_cache.h
static const uint32_t microcode_updates[] = {
/* Include microcode updates here. */
@@ -46,6 +47,9 @@ static void model_67x_init(device_t cpu)
/* Update the microcode */
intel_update_microcode(microcode_updates);
+ /* Initialize L2 cache */
+ p6_configure_l2_cache();
+
/* Turn on caching if we haven't already */
x86_enable_cache();
diff --git a/src/cpu/intel/slot_1/Makefile.inc
b/src/cpu/intel/slot_1/Makefile.inc
index 297ef18..a4de6e0 100644
--- a/src/cpu/intel/slot_1/Makefile.inc
+++ b/src/cpu/intel/slot_1/Makefile.inc
@@ -19,9 +19,11 @@
##
ramstage-y += slot_1.c
+ramstage-y += l2_cache.c
subdirs-y += ../model_6xx
subdirs-y += ../model_65x
subdirs-y += ../model_67x
+subdirs-y += ../model_68x
subdirs-y += ../model_6bx
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c
new file mode 100644
index 000..9185722
--- /dev/null
+++ b/src/cpu/intel/slot_1/l2_cache.c
@@ -0,0 +1,810 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000 Denis Dowling d...@alphalink.com.au
+ * Copyright (C) 2010 Keith Hui buu...@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * Intel Pentium L2 Cache initialization.
+ * This code was developed by reverse engineering
+ * the BIOS. Where the code accesses documented
+ * registers I have added comments as best I can.
+ * Some undocumented registers on the Pentium II are
+ * used so some of the documentation is incomplete.
+ *
+ * References:
+ * Intel Architecture Software Developer's Manual
+ * Volume 3B: System Programming Guide, Part 2 (#253669)
+ * Appendix B.9
+ */
+
+/* This code is ported from coreboot v1.
+ * The L2 cache initalization sequence here only apply to SECC/SECC2 P6 family
+ * CPUs with Klamath (63x), Deschutes (65x) and Katmai (67x) cores.
+ * It is not required for Coppermine (68x) and Tualatin (6bx) cores.
+ * It is currently not known if Celerons with Mendocino (66x) core require the
+ * special initialization.
+ * Covington-core Celerons do not have L2
[coreboot] git help: I can't get my whitespace cleanup in!
I'm trying to get this back in after we switched to git: http://review.coreboot.org/122 All seems good except some whitespace fixes. Making the fix is easy, submitting it through git is where I need help. Problem is I can't seem to get correct the sequence of commands. Right now I would... git clone... make gitconfig Do the cleanup git add the files git commit git rebase -i master git push origin and now I don't know if I have done it right. At one time gerrit rejected my submit, on next try the second submitted is identical to the first. Another problem is a few other commits gets merged into master in the meantime and it wants me to merge them in my local before accepting my push, which is making me feel lost. At this point should i expect an incremental commit with the original, submitted commit being the parent? How do I make sure gerrit know this is for the same Change-Id? I'll admit before this I have never used git, and yes, I have read the few sites about this. Thanks for your help. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review: fa78e5d Do not compile nuvoton wpcm450 early init
Alexandru Gagniuc (mr.nuke...@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/123 -gerrit commit fa78e5d1efc9b155537562ed385ad76ddc216a3c Author: Alexandru Gagniuc mr.nuke...@gmail.com Date: Mon Aug 1 03:54:58 2011 -0500 Do not compile nuvoton wpcm450 early init wpcm450 early_init.c was compiled whether or not this superio is selected. Change-Id: Iabc1970847b8383a01eb94012dcbec83dd774233 Signed-off-by: Alexandru Gagniuc mr.nuke...@gmail.com --- src/superio/nuvoton/wpcm450/Makefile.inc |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/superio/nuvoton/wpcm450/Makefile.inc b/src/superio/nuvoton/wpcm450/Makefile.inc index c70b2fb..db88097 100644 --- a/src/superio/nuvoton/wpcm450/Makefile.inc +++ b/src/superio/nuvoton/wpcm450/Makefile.inc @@ -18,6 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-y += early_init.c +romstage-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += early_init.c ramstage-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += superio.c -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review: 3d487da Add PCI IDs vor VIA VX900 chipset
Alexandru Gagniuc (mr.nuke...@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/124 -gerrit commit 3d487dab9ae1a16bb98d3077caa3ac5bc70f8a29 Author: Alexandru Gagniuc mr.nuke...@gmail.com Date: Mon Aug 1 05:16:20 2011 -0500 Add PCI IDs vor VIA VX900 chipset Change-Id: I59dc8caa22b66980560d5afb76eae801efaa29ad Signed-off-by: Alexandru Gagniuc mr.nuke...@gmail.com --- src/include/device/pci_ids.h | 22 ++ 1 files changed, 22 insertions(+), 0 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 9886199..0c06d74 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -1325,6 +1325,28 @@ #define PCI_DEVICE_ID_VIA_VX855_VGA0x5122 #define PCI_DEVICE_ID_VIA_VX855_VLINK 0x7409 #define PCI_DEVICE_ID_VIA_VX855_MEMCTRL0x3409 +/* VIA VX900 PCI IDs */ +#define PCI_DEVICE_ID_VIA_VX900_HOST_BR0x0410 +#define PCI_DEVICE_ID_VIA_VX900_ERROR_REPORT 0x1410 +#define PCI_DEVICE_ID_VIA_VX900_CPU_CTR0x2410 +#define PCI_DEVICE_ID_VIA_VX900_DRAM_CTR 0x3410 +#define PCI_DEVICE_ID_VIA_VX900_PWR_MGMT 0x4410 +#define PCI_DEVICE_ID_VIA_VX900_TRAF_CTR 0x5410 +#define PCI_DEVICE_ID_VIA_VX900_SCRATCH_REG0x6410 +#define PCI_DEVICE_ID_VIA_VX900_NORTH_NB_SB_CTR0x7410 +#define PCI_DEVICE_ID_VIA_VX900_LPC0x8410 +#define PCI_DEVICE_ID_VIA_VX900_PEX1 0xa410 +#define PCI_DEVICE_ID_VIA_VX900_PEX2 0xb410 +#define PCI_DEVICE_ID_VIA_VX900_PEX3 0xc410 +#define PCI_DEVICE_ID_VIA_VX900_PEX4 0xd410 +#define PCI_DEVICE_ID_VIA_VX900_PEX_CTR0xe410 +#define PCI_DEVICE_ID_VIA_VX900_SOUTH_NB_SB_CTR0xa535 +#define PCI_DEVICE_ID_VIA_VX900_PCI_BR 0xb535 +#define PCI_DEVICE_ID_VIA_VX900_VGA0x7122 +#define PCI_DEVICE_ID_VIA_VX900_VGA_UNKNOWN0x9170 +#define PCI_DEVICE_ID_VIA_VX900_HDAC 0x3288 +#define PCI_DEVICE_ID_VIA_VX900_ETHERNER 0x3119 +/* VIA CN700 */ #define PCI_DEVICE_ID_VIA_CN700_AGP0x0314 #define PCI_DEVICE_ID_VIA_CN700_ERR0x1314 #define PCI_DEVICE_ID_VIA_CN700_HOST 0x2314 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Trac reminder: list of new ticket(s)
Ticket Owner Status Description #180 ste...@coresystems.de new ASRock E350M1 Gigabit Ethernet Problem #179 ste...@coresystems.de new Coreboot on GigaByte GA-8IEXP ver. 1.2 #178 ste...@coresystems.de new linux kernel hang while boot from SATA SSD on EPIA CN #177 ste...@coresystems.de new Not compiling coreBoot #176 ste...@coresystems.de new inteltool: added PCI_DEVICE_ID_INTEL_X44 0x29e0 #174 ste...@coresystems.de new Unable to boot from qemu-kvm -- seems to be a cbfs problem #170 ste...@coresystems.de new Need coreboot for ASUS P4PE_X/SE #169 ste...@coresystems.de new ASUS P4PE-X/SE. #168 ste...@coresystems.de new USBDEBUG might slow down coreboot #162 oxygene new Move SYSTEM_TYPE to Kconfig #160 oxygene new Build system: There's no convincing CFLAGS management for util/* #158 w...@gnu.org new buildrom svn error #156 hailfinger new Add Layout File capability to v3 and LAR tool #154 hailfinger new Flashing BIOSes from Fujitsu/Siemens is not supported #150 somebody new AMD DB800 dev board PLL strapping leaves CPU and GLIU in non-optimal clock #147 somebody new Linux kernel halts when scanning the PCI bus below 0:14.4 on RS690 #145 somebody new Fix CMOS handling #143 oxygene new unify intel car for model_6[ef]x #135 ward new Flashrom deletes MAC addresses on Tyan Tomcat n3400B (S2925-E) #129 stepan new etherboot payload does not work with HIGH_TABLES #128 somebody new Improve email user interface for trac #125 somebody new BCM5785 / HT1000 reset functions #111 somebody new Add i18n support for translating strings e.g. for bayou / coreinfo #110 somebody new Allow for per-device subsystem IDs #77 somebody new hang on the "Jumping to coreboot" step on via epia-m with 4-chip 128Mbyte DDR module #76 rminnich new coreboot messages should be accessible in dmesg #18 oxygene new autoprobe apic cluster and application processors on K8 systems #17 stepan new clean up coreboot table handling #16 ollie new I2C driver and mainboard Config.lb #11 yhlu new pirq table automation #5 uwe new Add license header to all source files #2 somebody new Complete tables of supported motherboards -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] git help: I can't get my whitespace cleanup in!
Hi Keith, On Mon, Aug 1, 2011 at 12:41 AM, Keith Hui buu...@gmail.com wrote: I'm trying to get this back in after we switched to git: http://review.coreboot.org/122 All seems good except some whitespace fixes. Making the fix is easy, submitting it through git is where I need help. Problem is I can't seem to get correct the sequence of commands. Right now I would... git clone... make gitconfig Do the cleanup git add the files git commit git rebase -i master git push origin and now I don't know if I have done it right. At one time gerrit rejected my submit, on next try the second submitted is identical to the first. Another problem is a few other commits gets merged into master in the meantime and it wants me to merge them in my local before accepting my push, which is making me feel lost. At this point should i expect an incremental commit with the original, submitted commit being the parent? How do I make sure gerrit know this is for the same Change-Id? I'll admit before this I have never used git, and yes, I have read the few sites about this. Thanks for your help. An incremental commit on the same change ID needs to have the entire commit you want to make. You can't have two commits with one change-id. What you want to do is edit your commit, rebase -i, and edit the commit. You best option for getting more help is in #coreboot. Marc -- http://se-eng.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review: 523ae5d Use preferred style of fixed-width integer types
Jonathan A. Kollasch (jakll...@kollasch.net) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/125
-gerrit
commit 523ae5d776879621fabe6f338c1b8c808636a57d
Author: Jonathan A. Kollasch jakll...@kollasch.net
Date: Mon Aug 1 14:15:28 2011 -0500
Use preferred style of fixed-width integer types
Change-Id: I1abaaa2af4de940584039f9b8c348bb57fb611e0
Signed-off-by: Jonathan A. Kollasch jakll...@kollasch.net
---
src/mainboard/msi/ms7135/mptable.c |2 +-
src/mainboard/msi/ms7135/romstage.c |6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/msi/ms7135/mptable.c
b/src/mainboard/msi/ms7135/mptable.c
index fc1caa5..3412145 100644
--- a/src/mainboard/msi/ms7135/mptable.c
+++ b/src/mainboard/msi/ms7135/mptable.c
@@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v)
{
device_t dev;
struct resource *res;
- uint32_t dword;
+ u32 dword;
dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0));
if (dev) {
diff --git a/src/mainboard/msi/ms7135/romstage.c
b/src/mainboard/msi/ms7135/romstage.c
index 8609142..5feef79 100644
--- a/src/mainboard/msi/ms7135/romstage.c
+++ b/src/mainboard/msi/ms7135/romstage.c
@@ -68,8 +68,8 @@ static inline int spd_read_byte(unsigned device, unsigned
address)
static void sio_setup(void)
{
- uint32_t dword;
- uint8_t byte;
+ u32 dword;
+ u8 byte;
/* Subject decoding */
byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b);
@@ -85,7 +85,7 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- static const uint16_t spd_addr[] = {
+ static const u16 spd_addr[] = {
DIMM0, DIMM1, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review: aad6f2a Add voltage control of southbridge and RAM on ms7135
Jonathan A. Kollasch (jakll...@kollasch.net) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/126
-gerrit
commit aad6f2ab566dffc055e7a1403348c3b38c120751
Author: Jonathan A. Kollasch jakll...@kollasch.net
Date: Mon Aug 1 14:24:02 2011 -0500
Add voltage control of southbridge and RAM on ms7135
Change-Id: I5d79b4838f69cad56d58363608b801f8b1d3ab43
Signed-off-by: Jonathan A. Kollasch jakll...@kollasch.net
---
src/mainboard/msi/ms7135/cmos.layout | 16 +--
src/mainboard/msi/ms7135/romstage.c | 49 ++---
2 files changed, 51 insertions(+), 14 deletions(-)
diff --git a/src/mainboard/msi/ms7135/cmos.layout
b/src/mainboard/msi/ms7135/cmos.layout
index 53fdef5..694554d 100644
--- a/src/mainboard/msi/ms7135/cmos.layout
+++ b/src/mainboard/msi/ms7135/cmos.layout
@@ -43,6 +43,8 @@ entries
440 4 e 9slow_cpu
444 1 e 1nmi
445 1 e 1iommu
+448 4 e 10ram_voltage
+452 4 e 11nf4_voltage
728256 h 0user_data
984 16 h 0check_sum
# Reserve the extended AMD configuration registers
@@ -74,10 +76,10 @@ enumerations
7 0 Network
7 1 HDD
7 2 Floppy
+#7 3 ROM
7 8 Fallback_Network
7 9 Fallback_HDD
7 10Fallback_Floppy
-#7 3 ROM
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
@@ -91,8 +93,16 @@ enumerations
9 6 25.0%
9 7 12.5%
-checksums
+100 2.55
+101 2.50
+102 2.60
+103 2.65
+104 2.70
-checksum 392 983 984
+110 1.50
+111 1.55
+112 1.60
+checksums
+checksum 392 983 984
diff --git a/src/mainboard/msi/ms7135/romstage.c
b/src/mainboard/msi/ms7135/romstage.c
index 8609142..dc01b6a 100644
--- a/src/mainboard/msi/ms7135/romstage.c
+++ b/src/mainboard/msi/ms7135/romstage.c
@@ -48,6 +48,10 @@
#include cpu/amd/dualcore/dualcore.c
#include spd.h
+#if CONFIG_HAVE_OPTION_TABLE
+#include option_table.h
+#endif
+
#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
static void memreset(int controllers, const struct mem_controller *ctrl) { }
@@ -66,6 +70,31 @@ static inline int spd_read_byte(unsigned device, unsigned
address)
#include cpu/amd/model_fxx/init_cpus.c
#include northbridge/amd/amdk8/early_ht.c
+static void ms7135_set_ram_voltage(void)
+{
+ u8 b;
+ b = read_option(ram_voltage, 0);
+ if (b 4) /* default if above 2.70v */
+ b = 0;
+ print_debug(setting RAM voltage );
+ print_debug_hex8(b);
+ print_debug(\n);
+ ck804_smbus_write_byte(1, 0x2f, 0x00, b);
+}
+
+static void ms7135_set_nf4_voltage(void)
+{
+ u8 b;
+ b = read_option(nf4_voltage, 0);
+ if (b 2) /* default if above 1.60v */
+ b = 0;
+ b |= 0x10;
+ print_debug(setting NF4 voltage );
+ print_debug_hex8(b);
+ print_debug(\n);
+ ck804_smbus_write_byte(1, 0x2f, 0x02, b);
+}
+
static void sio_setup(void)
{
uint32_t dword;
@@ -107,14 +136,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long
cpu_init_detectedx)
bsp_apicid = init_cpus(cpu_init_detectedx);
w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+#if CONFIG_USBDEBUG
+ ck804_enable_usbdebug(USBDEBUG_DEFAULT_PORT);
+ early_usbdebug_init();
+#endif
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
-#if 0
- dump_pci_device(PCI_DEV(0, 0x18, 0));
-#endif
+ enable_smbus();
+
+ ms7135_set_nf4_voltage();
+ ms7135_set_ram_voltage();
needs_reset = setup_coherent_ht_domain();
@@ -138,19 +172,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long
cpu_init_detectedx)
//It's the time to set ctrl now;
fill_mem_ctrl(nodes, ctrl, spd_addr);
- enable_smbus();
-
-#if 0
+#if CONFIG_DEBUG_SMBUS
dump_spd_registers(ctrl[0]);
dump_smbus_registers();
#endif
sdram_initialize(nodes, ctrl);
-#if 0
- print_pci_devices();
- dump_pci_devices();
-#endif
-
post_cache_as_ram();
}
--
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http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] libpci accesses in CAR, I need a suggestion
Hi, thank you both for the answers. I have studied libpci from libpayload and removed that device list generation with mallocs. Done a bunch of trial-error cleanup and now chipset enable and probing for flash works in ramstage's top of hardwaremain function with this line included: x86_setup_mtrrs(36); //from cpu init routine see attached log: ramstage_with_mtrr.txt. Also attaching nonworking logs in romstage and ramstage. Now the question is how these mtrrs should be set in cache_as_ram.inc or maybe I'm totally wrong? :) Thanks, Tadas coreboot-4.0-r6637 Mon Aug 1 21:55:46 EEST 2011 starting... Loading image. Check CBFS header at fc9e magic is 4f524243 Found CBFS header at fc9e Check fallback/romstage CBFS: follow chain: fffc + 38 + 6840 + align - fffc6880 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x10 (180224 bytes), entry @ 0x10 Stage: done loading. Jumping to image. coreboot-4.0-r6637 Mon Aug 1 21:55:46 EEST 2011 booting... Setting fixed MTRRs(0-88) Type: UC DONE fixed MTRRs call enable_fixed_mtrr() Zero-sized MTRR range @0KB Zero-sized MTRR range @0KB DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs flashrom is free software, get the source code at http://www.flashrom.org Initializing internal programmer chipset enable :)Found chipset Intel PIIX4/4E/4M, enabling flash write... chipset PCI ID is 8086:7110, enablef0 enablef1 enablef2 OK. Probing for Winbond W29C020(C)/W29C022, 256 kB: clocks_per_usec: 402 probe_jedec_common: id1 0xda, id2 0x45 Found chip Winbond W29C020(C)/W29C022 (256 kB, bustype :) . coreboot-4.0-r6637 Mon Aug 1 21:47:20 EEST 2011 starting... Loading image. Check CBFS header at fc9e magic is 4f524243 Found CBFS header at fc9e Check fallback/romstage CBFS: follow chain: fffc + 38 + 6840 + align - fffc6880 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x10 (180224 bytes), entry @ 0x10 Stage: done loading. Jumping to image. coreboot-4.0-r6637 Mon Aug 1 21:47:20 EEST 2011 booting... flashrom is free software, get the source code at http://www.flashrom.org Initializing internal programmer chipset enable :)Found chipset Intel PIIX4/4E/4M, enabling flash write... chipset PCI ID is 8086:7110, enablef0 enablef1 enablef2 OK. Probing for Winbond W29C020(C)/W29C022, 256 kB: clocks_per_usec: 402 probe_jedec_common: id1 0x4c, id2 0x41, id1 is normal flash content, id2 is normal flash content No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. coreboot-4.0-r6637 Mon Aug 1 21:40:30 EEST 2011 starting... flashrom is free software, get the source code at http://www.flashrom.org Initializing internal programmer chipset enable :)Found chipset Intel PIIX4/4E/4M, enabling flash write... chipset PCI ID is 8086:7110, enablef0 enablef1 enablef2 OK. Probing for Winbond W29C020(C)/W29C022, 256 kB: probe_jedec_common: id1 0x4c, id2 0x41, id1 is normal flash content, id2 is normal flash content No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. Loading image. Check CBFS header at fc9e magic is 4f524243 Found CBFS header at fc9e Check fallback/romstage CBFS: follow chain: fffc + 38 + 6840 + align - fffc6880 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x10 (180224 bytes), entry @ 0x10 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch set updated: 0f196d4 cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.
Keith Hui (buu...@gmail.com) just uploaded a new patch set to gerrit, which you
can find at http://review.coreboot.org/122
-gerrit
commit 0f196d4cf39e680389a2098e10739d8545397203
Author: Keith Hui buu...@gmail.com
Date: Wed Jul 27 23:06:16 2011 -0400
cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.
Bring from coreboot v1 support for initializing L2 cache on Slot 1
Pentium II/III CPUs, code names Klamath, Deschutes and Katmai.
Build tested on ASUS P2B-LS and P3B-F. Boot tested on P2B-LS with
Pentium III 600MHz, Katmai core.
Also add missing include of model_68x in slot_1, to address a
similar problem fixed for model_6bx by r5945.
Also change Deschutes CPU init sequence to match Katmai.
Change-Id: I502e8481d1a20f0a2504685e7be16b57f59c8257
Signed-off-by: Keith Hui buu...@gmail.com
---
src/cpu/intel/model_65x/model_65x_init.c | 10 +-
src/cpu/intel/model_67x/model_67x_init.c |4 +
src/cpu/intel/slot_1/Makefile.inc|2 +
src/cpu/intel/slot_1/l2_cache.c | 810 ++
src/include/cpu/intel/l2_cache.h | 101
5 files changed, 924 insertions(+), 3 deletions(-)
diff --git a/src/cpu/intel/model_65x/model_65x_init.c
b/src/cpu/intel/model_65x/model_65x_init.c
index 8f9fc66..ef97597 100644
--- a/src/cpu/intel/model_65x/model_65x_init.c
+++ b/src/cpu/intel/model_65x/model_65x_init.c
@@ -27,6 +27,7 @@
#include cpu/x86/lapic.h
#include cpu/intel/microcode.h
#include cpu/x86/cache.h
+#include cpu/intel/l2_cache.h
static u32 microcode_updates[] = {
#include microcode-410-MU16522d.h
@@ -56,14 +57,17 @@ static u32 microcode_updates[] = {
static void model_65x_init(device_t dev)
{
+ /* Update the microcode */
+ intel_update_microcode(microcode_updates);
+
+ /* Initialize L2 cache */
+ p6_configure_l2_cache();
+
/* Turn on caching if we haven't already */
x86_enable_cache();
x86_setup_mtrrs(36);
x86_mtrr_check();
- /* Update the microcode */
- intel_update_microcode(microcode_updates);
-
/* Enable the local cpu apics */
setup_lapic();
};
diff --git a/src/cpu/intel/model_67x/model_67x_init.c
b/src/cpu/intel/model_67x/model_67x_init.c
index 76a840e..0c9b3d2 100644
--- a/src/cpu/intel/model_67x/model_67x_init.c
+++ b/src/cpu/intel/model_67x/model_67x_init.c
@@ -26,6 +26,7 @@
#include cpu/intel/microcode.h
#include cpu/x86/cache.h
#include cpu/x86/msr.h
+#include cpu/intel/l2_cache.h
static const uint32_t microcode_updates[] = {
/* Include microcode updates here. */
@@ -46,6 +47,9 @@ static void model_67x_init(device_t cpu)
/* Update the microcode */
intel_update_microcode(microcode_updates);
+ /* Initialize L2 cache */
+ p6_configure_l2_cache();
+
/* Turn on caching if we haven't already */
x86_enable_cache();
diff --git a/src/cpu/intel/slot_1/Makefile.inc
b/src/cpu/intel/slot_1/Makefile.inc
index 297ef18..a4de6e0 100644
--- a/src/cpu/intel/slot_1/Makefile.inc
+++ b/src/cpu/intel/slot_1/Makefile.inc
@@ -19,9 +19,11 @@
##
ramstage-y += slot_1.c
+ramstage-y += l2_cache.c
subdirs-y += ../model_6xx
subdirs-y += ../model_65x
subdirs-y += ../model_67x
+subdirs-y += ../model_68x
subdirs-y += ../model_6bx
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c
new file mode 100644
index 000..9a694e0
--- /dev/null
+++ b/src/cpu/intel/slot_1/l2_cache.c
@@ -0,0 +1,810 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000 Denis Dowling d...@alphalink.com.au
+ * Copyright (C) 2010 Keith Hui buu...@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * Intel Pentium L2 Cache initialization.
+ * This code was developed by reverse engineering
+ * the BIOS. Where the code accesses documented
+ * registers I have added comments as best I can.
+ * Some undocumented registers on the Pentium II are
+ * used so some of the documentation is incomplete.
+ *
+ * References:
+ * Intel Architecture Software Developer's Manual
+ * Volume 3B: System Programming Guide, Part 2 (#253669)
+ * Appendix B.9
+ */
+
+/* This code is ported from coreboot v1.
+ *
[coreboot] New patch to review: df8d54c Initialize ACPI to prevent spurious events at OS boot
Jonathan A. Kollasch (jakll...@kollasch.net) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/127
-gerrit
commit df8d54c4372f1e851c413c5903db20284eb57c06
Author: Jonathan A. Kollasch jakll...@kollasch.net
Date: Mon Aug 1 15:17:08 2011 -0500
Initialize ACPI to prevent spurious events at OS boot
Change-Id: I7e1138360f18ba857cf533baa8ec1db555aebcde
Signed-off-by: Jonathan A. Kollasch jakll...@kollasch.net
---
src/southbridge/nvidia/ck804/lpc.c | 20
1 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/src/southbridge/nvidia/ck804/lpc.c
b/src/southbridge/nvidia/ck804/lpc.c
index d371882..b66a569 100644
--- a/src/southbridge/nvidia/ck804/lpc.c
+++ b/src/southbridge/nvidia/ck804/lpc.c
@@ -28,6 +28,7 @@
#include device/pci_ops.h
#include pc80/mc146818rtc.h
#include pc80/isa-dma.h
+#include delay.h
#include bitops.h
#include arch/io.h
#include arch/ioapic.h
@@ -104,6 +105,23 @@ static void rom_dummy_write(device_t dev)
pci_write_config8(dev, 0x6d, new);
}
+static void lpc_acpi_init(u16 base)
+{
+ u16 word;
+
+ printk(BIOS_SPEW, %s: base = %x \n, __func__, base);
+
+ /* clear sleep, set SCI_EN */
+ word = inw(base + 4);
+ word = ~(7 10);
+ word |= 1;
+ outw(word, base + 4);
+ udelay(100); /* seems to be needed */
+
+ /* clear ACPI PM1 event status */
+ outw(0x, base + 0);
+}
+
unsigned pm_base = 0;
static void lpc_init(device_t dev)
@@ -169,6 +187,8 @@ static void lpc_init(device_t dev)
/* Initialize ISA DMA. */
isa_dma_init();
+ lpc_acpi_init(pm_base);
+
rom_dummy_write(dev);
}
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] libpci accesses in CAR, I need a suggestion
Tadas, On Mon, Aug 1, 2011 at 1:08 PM, Tadas Slotkus devta...@gmail.com wrote: Hi, thank you both for the answers. I have studied libpci from libpayload and removed that device list generation with mallocs. Done a bunch of trial-error cleanup and now chipset enable and probing for flash works in ramstage's top of hardwaremain function with this line included: x86_setup_mtrrs(36); //from cpu init routine see attached log: ramstage_with_mtrr.txt. Also attaching nonworking logs in romstage and ramstage. Now the question is how these mtrrs should be set in cache_as_ram.inc or maybe I'm totally wrong? :) You will need the MTRR setup from CAR. You will want your code to execute in the XIP area, so that it may be cashed. You may still have stack/mem issues. That may be the first place you look for problems. You may need to find a way to optimize for resources. Marc -- http://se-eng.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] libpci accesses in CAR, I need a suggestion
On 8/1/11 1:28 PM, Marc Jones wrote: Tadas, On Mon, Aug 1, 2011 at 1:08 PM, Tadas Slotkusdevta...@gmail.com wrote: Hi, thank you both for the answers. I have studied libpci from libpayload and removed that device list generation with mallocs. Done a bunch of trial-error cleanup and now chipset enable and probing for flash works in ramstage's top of hardwaremain function with this line included: x86_setup_mtrrs(36); //from cpu init routine see attached log: ramstage_with_mtrr.txt. Also attaching nonworking logs in romstage and ramstage. Now the question is how these mtrrs should be set in cache_as_ram.inc or maybe I'm totally wrong? :) You will need the MTRR setup from CAR. You will want your code to execute in the XIP area, so that it may be cashed. You may still have stack/mem issues. That may be the first place you look for problems. You may need to find a way to optimize for resources. There will be a problem leaving the XIP area cached while trying to write to the flash. At the least this means it's not possible to write the whole flash. Is this intended? What's the plan here? Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
