[coreboot] State of xHCI driver, specifically for Baytrail
Does anyone have a view on the state of xHCI on baytrail_fsp platforms? I've enabled xHCI ( and disabled eHCI ) in devicetree.cb, but the resulting build with SeaBIOS as a payload will not go further than displaying the SeaBIOS header string. With both xHCI and eHCI enabled in devicetree.cb - which the comments in that file say I should not do - SeaBIOS loads, and can recognize a DVD drive attached to a USB3 USB hub. I'm not sure whether this is a safe combination, or whether there are other settings I should change. Cheers, Mike -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] setting smbios values from the OS
Rafael, i don't think that you can update them once the OS loads. The OS would have already made decisions based on the settings. Marc On Tue, Jun 10, 2014 at 7:41 PM, Rafael Vanoni rafael.van...@pluribusnetworks.com wrote: Hi folks, first time posting here. I was wondering if it would be possible to modify smbios values once a system is up and running. Has anyone ever looked into that? If not, any pointers on how to implement this would be greatly appreciated. I'm fairly new to coreboot but would like to look into this. This is with coreboot + seabios, btw. Thanks, Rafael -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- http://se-eng.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] x60s tablet question : optimized kernel, coreboot with the video fix and serial ports support
On 11.06.2014 09:46, derpeter wrote: I tried this last month. I cherrypickt everything execpt the video fix and got a working coreboot. Sadly i could not bring the wacom to work but i'm not sure if its a problem of coreboot or linux. Submit logs then: Xorg log, dmesg and coreboot log. signature.asc Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] State of xHCI driver, specifically for Baytrail
Hi Mike, the FSP is configuring the XHCI controller. Coreboot is not touching it - this is at Intel's request. Enabling both the XHCI and EHCI controllers in devicetree sets XHCI off and EHCI on. You'll see the state of all of the devices that gets passed into the FSP very early in the boot sequence if you have the console set to debug or spew. I saw the same hang in SeaBIOS when I used the default SeaBIOS built by coreboot. When I built it separately, It still didn't boot from the XHCI device, but it did identify it, and didn't hang. I'm including the SeaBIOS .config that I used. Martin On 06/13/2014 04:21 AM, Mike Hibbett wrote: Does anyone have a view on the state of xHCI on baytrail_fsp platforms? I've enabled xHCI ( and disabled eHCI ) in devicetree.cb, but the resulting build with SeaBIOS as a payload will not go further than displaying the SeaBIOS header string. With both xHCI and eHCI enabled in devicetree.cb - which the comments in that file say I should not do - SeaBIOS loads, and can recognize a DVD drive attached to a USB3 USB hub. I'm not sure whether this is a safe combination, or whether there are other settings I should change. Cheers, Mike # # Automatically generated file; DO NOT EDIT. # SeaBIOS Configuration # # # General Features # CONFIG_COREBOOT=y # CONFIG_QEMU is not set # CONFIG_CSM is not set # CONFIG_QEMU_HARDWARE is not set CONFIG_THREADS=y CONFIG_RELOCATE_INIT=y CONFIG_BOOTMENU=y # CONFIG_BOOTSPLASH is not set CONFIG_BOOTORDER=y CONFIG_COREBOOT_FLASH=y CONFIG_LZMA=y CONFIG_CBFS_LOCATION=0 CONFIG_FLASH_FLOPPY=y CONFIG_ENTRY_EXTRASTACK=y # CONFIG_MALLOC_UPPERMEMORY is not set CONFIG_ROM_SIZE=0 # # Hardware support # # CONFIG_ATA is not set CONFIG_AHCI=y # CONFIG_MEGASAS is not set # CONFIG_FLOPPY is not set CONFIG_PS2PORT=y CONFIG_USB=y CONFIG_USB_UHCI=y CONFIG_USB_OHCI=y CONFIG_USB_EHCI=y CONFIG_USB_XHCI=y CONFIG_USB_MSC=y # CONFIG_USB_UAS is not set CONFIG_USB_HUB=y CONFIG_USB_KEYBOARD=y CONFIG_USB_MOUSE=y CONFIG_SERIAL=y CONFIG_LPT=y CONFIG_PMTIMER=y # # BIOS interfaces # CONFIG_DRIVES=y CONFIG_CDROM_BOOT=y CONFIG_CDROM_EMU=y CONFIG_PCIBIOS=y CONFIG_APMBIOS=y CONFIG_PNPBIOS=y CONFIG_OPTIONROMS=y CONFIG_PMM=y CONFIG_BOOT=y CONFIG_KEYBOARD=y CONFIG_KBD_CALL_INT15_4F=y CONFIG_MOUSE=y CONFIG_S3_RESUME=y CONFIG_VGAHOOKS=y CONFIG_DISABLE_A20=y # # VGA ROM # CONFIG_NO_VGABIOS=y # CONFIG_VGA_GEODEGX2 is not set # CONFIG_VGA_GEODELX is not set # CONFIG_VGA_COREBOOT is not set # CONFIG_BUILD_VGABIOS is not set CONFIG_VGA_EXTRA_STACK_SIZE=512 # # Debugging # CONFIG_DEBUG_LEVEL=2 CONFIG_DEBUG_SERIAL=y CONFIG_DEBUG_SERIAL_PORT=0x3f8 CONFIG_DEBUG_COREBOOT=y -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] MMCONF (again) issues on Fam 10H
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi, The fact that my M4A785T-M got unusable with master pushed me to retest that patch: 23:58 PaulePanter GNUtoo-irssi: git fetch http://review.coreboot.org/coreboot refs/changes/41/4541/1 git checkout FETCH_HEAD So instead of doing a checkout, I did a cherry-pick of the patch on top of master, and I've attached the log. I don't remember what happened but we probably deadlocked each other. What probably happened is that you wrote a mail to the mailing list, which I didn't respond to because I responded trough IRC. I probably didn't even see the thread because with my mali setup, the coreboot mails are now automatically in a coreboot folder, and since I don't work on it right now, I probably didn't look it up. M4A785T-M status: - - Here is the difference of status since I touched it last time(probably about one year ago). The new status of the M4A785T-M is on top of a patched old master. * The mmconf issues are still there on master * Ram init got very unstable lately, lately I have freeze once booted, and before I had difficult boot (sometimes it reseted during the boot). * 4G of RAM doesn't work, most probably because of the unstable RAM init, because it has the same reboot symptom, but way more frequently. * The sound card now works! Denis. -BEGIN PGP SIGNATURE- Version: GnuPG v2 iQIcBAEBAgAGBQJTm33EAAoJENWQk6o21VqZ0w4P/0usTXDzu0nnmx6th1BakwHX w3WdudpmYgbIRV5hC9mbax+X0tV3aKcMrbBYVLdgUxCmrLNUr55nxuX+Kku5loIA 5YvCTMtmX4oKLS5FWiP9cMMCNY5mkUAeQT/bNWgqScxizBc1fD2KvLUyB35rP56t 6G7A+4GmmEYYTwk83dJDK4nn8zRvRKkqSuFd4Dt7Ha4OWSI1h/N5PodYILhtNR7C U62mTYJ7J1n6iD09GDMBuBvo8pBnZ2T8r1QbCc4tw5M+JPRtJQ7CYrBm/tRoDVdT DgZOpRygnnUVT3VDfoWsKvdU0JtSIxvI0WENYujw439+7nfACeMOV6X9EACPu7Zu +gF0pN0jsnGxcd7A6wvq+gZ8ojljheKvFRVCYz1M9irezN4iPfuBRI0voMTBTjVP do0n2hacbqXKznkWXS8OSF032LLF/mONOfG8GFZjXt0a6Esgkfye30UHq1eX4jLp 8cek7XvdC5TnX940zcNPhY4fLySDtYCU4awEnphU27w9JfJsAQWr1snTavFILE+z J2B7UJ9oRq0i1Sq1Gz6MurqgeGuhXzoPYPRaTbgQTqxKG1IXSQvW8P/yknCX6YJe eQGjIkRMZoQ9OwvVfNYZ5l2TZvL2XstImXzDzwT/QbVwsibRRErjAHXepj7v/jd3 WPeI3uOQ5r3/JHk/5/e0 =sEXG -END PGP SIGNATURE- gnutoo@X60 ~ % picocom -b 115200 /dev/ttyUSB0 picocom v1.7 port is: /dev/ttyUSB0 flowcontrol: none baudrate is: 115200 parity is : none databits are : 8 escape is : C-a local echo is : no noinit is : no noreset is : no nolock is : no send_cmd is: sz -vv receive_cmd is : rz -vv imap is: omap is: emap is: crcrlf,delbs, Terminal ready coreboot-4.0-6222-g4312dde Sat Jun 14 00:17:54 CEST 2014 starting... BSP Family_Model: 00100f62 *sysinfo range: [000c4000,000c7360] bsp_apicid = 00 cpu_init_detectedx = microcode: equivalent rev id = 0x1062, current patch id = 0x microcode: patch id to apply = 0x019f microcode: updated to patch id = 0x019f success cpuSetAMDMSR done Enter amd_ht_init() Exit amd_ht_init() cpuSetAMDPCI 00 done Prep FID/VID Node:00 F3x80: e600e681 F3x84: 80e641e6 F3xD4: c8810f24 F3xD8: 03001016 F3xDC: 532a core0 started: start_other_cores() init node: 00 cores: 01 Start other core - nodeid: 00 cores: 01 started ap apicid: * AP 01started rs780_early_setup() fam10_optimization() rs780_por_init sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A14 sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-18-0 sb700_pmio_por_init() Begin FIDVID MSR 0xc0010071 0x30bc0073 0x44035440 FIDVID on BSP, APIC_id: 00 BSP fid = 10600 Wait for AP stage 1: ap_apicid = 1 readback = 1010601 common_fid(packed) = 10600 common_fid = 10600 FID Change Node:00, F3xD4: c8810f26 End FIDVIDMSR 0xc0010071 0x30bc0073 0x3c005440 rs780_htinit cpu_ht_freq=b. rs780_htinit: HT3 mode ...WARM RESET... coreboot-4.0-6222-g4312dde Sat Jun 14 00:17:54 CEST 2014 starting... BSP Family_Model: 00100f62 *sysinfo range: [000c4000,000c7360] bsp_apicid = 00 cpu_init_detectedx = microcode: equivalent rev id = 0x1062, current patch id = 0x microcode: patch id to apply = 0x019f microcode: updated to patch id = 0x019f success cpuSetAMDMSR done Enter amd_ht_init() Exit amd_ht_init() cpuSetAMDPCI 00 done Prep FID/VID Node:00 F3x80: e600e681 F3x84: 80e641e6 F3xD4: c8810f26 F3xD8: 03001016 F3xDC: 532a core0 started: start_other_cores() init node: 00 cores: 01 Start other core - nodeid: 00 cores: 01 started ap apicid: * AP 01started rs780_early_setup() fam10_optimization() rs780_por_init sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A14 sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3
