[coreboot] Re: Installing coreboot with SeaBIOS
Hello Nico,Thanks for replying "tl;dr Go!" ...Though, I didn't understand that but I interpret it as a request to go on "AFAICT" ...I also didn't get that.Should I use this tutorial, that applies to the ThinkPad X200 where I got a ThinkPad X220, for opening the housing and figuring out what screws to open in order to get access to the chip or is there one for the ThinkPad X220, too (https://libreboot.org/docs/install/x200_external.html)?Bernd Originalnachricht Betreff: [coreboot] Re: Installing coreboot with SeaBIOSVon: Nico Huber An: bernd...@web.deCc: coreboot@coreboot.orgHi Bernd,On 18.01.22 14:41, bernd...@web.de wrote:> So, after having made clear the corresponding points do you think that the> following hardware will be sufficient to flash the coreboot/SeaBIOS ROM to the> chip of my ThinkPad X220 (notebook version, not tablet version):>> Raspberry Pi with keyboard and screen> Pomona or SOIC8 programming clip> 8 jumper wires/dupont wires that fit the clip 10 to 20 cm each> PSUs to power everythingtl;dr Go!If you want to be 100% sure, you should open your ThinkPad and checkthat your BIOS flash is indeed in a SOIC-8 package, and that there isonly a single flash chip. In theory it can be different, but so farpeople have only encountered a single SOIC-8 chip, AFAICT.Minor corrections: Pomona is the name of the manufacturer (of thebetter clips). You only need 6 wires; /HOLD and /WP pins of the flashare already properly connected by the mainboard.Nico___coreboot mailing list -- coreboot@coreboot.orgTo unsubscribe send an email to coreboot-le...@coreboot.org___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Memory Down approach Error on intel Denverton board
Hi, Did you adjusted mMemoryDownConfig structure in mainboard`s romstage.c file to much your memory down configuration? Refer to commented out example just above structure definition. Also double check if .SpdDataPtr structure member for memory down slot has correct pointer to spd.bin content. Mariusz -- Intel Research and Development Ireland Limited Registered in Ireland Registered Office: Collinstown Industrial Park, Leixlip, County Kildare Registered Number: 308263 This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Memory Down approach Error on intel Denverton board
Hi , Greetings . We are working on intel c508 intel denverton board . It has a soldered 4GB DDR4 connected to Channel 0 , Dimm 0 . Below are the changes made : 1. We are using harcuvar board as a reference . I have selected * Enable Memory down option in menu config 2. Added spd values file in src/mainboard/intel/harcuvar/spd/spd_filename.hex 3. spd.bn getting generated in CBFS FMAP REGION: COREBOOT Name Offset Type Size Comp cbfs master header 0x0cbfs header32 none fallback/romstage 0x80 stage 42084 none cpu_microcode_blob.bin 0xa580 microcode 11264 none fallback/ramstage 0xd200 stage 70701 none config 0x1e680raw 1227 none revision 0x1ebc0raw 691 none spd.bin0x1eec0spd 512 none fallback/dsdt.aml 0x1f100raw 7791 none fallback/postcar 0x20fc0stage 21832 none fallback/payload 0x26540simple elf 656810 none (empty)0xc6b40null 6656600 none fspt.bin 0x71fdc0 fsp 4096 none (empty)0x720e00 null 3992 none fspm.bin 0x721dc0 fsp589824 none (empty)0x7b1e00 null 3992 none fsps.bin 0x7b2dc0 fsp102400 none (empty)0x7cbe00 null 114584 none bootblock 0x7e7dc0 bootblock 32768 none 4. Tried giving 256 and 512 values CONFIG_DIMM_SPD_SIZE=256 We are using Fitc tool to generate full fw image,getting below error and got stuck after loading the build UMA: ME UMA size set to 0. Isoc is Disabled. SMBus Legacy: SPD Write Disable bit is locked now! SMBus Host: SPD Write Disable bit is locked now! MRC VERSION: 0x950441 MRCDATA Size: 115F1 MRC_SAVE_RESTORE Size: 6F2C SocStepping: 16 Warning: MspData data structure hasn't been locked yet Dunit Fuse Configuration SCRAMBLER_SUPPORTED: 1 DDR_MAX_FREQ_LIMIT: 1 DDR_CURRENT_FREQ: 1 SINGLE_CHANNEL: 0 IPROCTRIM: 2 TIMING_1N_SUPPORTED: 1 X4_SUPPORTED: 1 X8_SUPPORTED: 1 DDR4_SUPPORTED: 1 DDR3_SUPPORTED: 1 DOUBLE_RANK_SUPPORTED: 1 POPULATE_2DPC_SUPPORTED: 1 ECC_SUPPORTED: 1 MAX_DEN_SUPPORTED: 3 MAX_MEM_SUPPORTED: 7 Warning: MspData data structure hasn't been locked yet Dunit Fuse Configuration SCRAMBLER_SUPPORTED: 1 DDR_MAX_FREQ_LIMIT: 1 DDR_CURRENT_FREQ: 1 SINGLE_CHANNEL: 0 IPROCTRIM: 2 TIMING_1N_SUPPORTED: 1 X4_SUPPORTED: 1 X8_SUPPORTED: 1 DDR4_SUPPORTED: 1 DDR3_SUPPORTED: 1 DOUBLE_RANK_SUPPORTED: 1 POPULATE_2DPC_SUPPORTED: 1 ECC_SUPPORTED: 1 MAX_DEN_SUPPORTED: 3 MAX_MEM_SUPPORTED: 7 GetSpdData(ch:0) Dimm:0 MemDn=1 Error! Unsuported DDR type: 255 Status = 0x0001 Any help on this is highly appreciated . Thanks, Ganesh kumar C ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Git reports an interesting error message
Hi Jay, from your description I'm not clear what you added to your root certificate store. Let's Encrypt provides their root certs in various formats at https://letsencrypt.org/certificates/ Things should work after you add those (right now, review.coreboot.org is certified through the X1 root) If that doesn't help, the issue might be incompatible cipher suite requirements (your clients only supporting cryptographic algorithms that the server doesn't support) but I don't think we changed anything in that regard on the servers in the last few years. Patrick Am Di., 18. Jan. 2022 um 02:26 Uhr schrieb Jay Talbott < jaytalb...@sysproconsulting.com>: > Ok, I'm running into the same issue on an Ubuntu 16.04 system. > > $ git clone https://review.coreboot.org/coreboot.git > Cloning into 'coreboot'... > fatal: unable to access 'https://review.coreboot.org/coreboot.git/': > server certificate verification failed. CAfile: > /etc/ssl/certs/ca-certificates.crt CRLfile: none > > In the past I've had no problems with cloning coreboot on this system, but > now it's broken with the same error message as Gregg encountered. > > I've updated the ca-certificates, but it said I already had the latest > certs and that didn't fix it. > > I found an article online about pulling the cert from coreboot into a .pem > file, and then appending that into the ca-certificdates.crt file, but that > didn’t work either. > > I imagine there are others that have run into this... what's the solution? > > Thanks, > > - Jay > > > -Original Message- > > From: Gregg Levine > > Sent: Thursday, September 30, 2021 6:16 PM > > To: Patrick Georgi > > Cc: coreboot > > Subject: [coreboot] Re: Git reports an interesting error message > > > > Hello! > > Okay update. This is WSL remember, I grabbed an Ubuntu image that I'd > > previously claimed and allowed the automation to install it. I should > > mention that I also followed normal Debian based Linux methods to > > upgrade it. > > And I then pulled over a tar compressed with Bzip2 tree of my entire > > work, and extracted it. Inside it I went into the original coreboot > > directory from a while ago. Inside it I ran the git command steps to > > update it. I did not see the error message. > > > > I did note that it found problems with updating an earlier source > > tree, but had no problems pulling down a new one. The problems were > > related to the contents. I renamed the tree to call it a backup. It is > > still working to retrieve things. So I believe the problems were > > related to the SuSe image I was using, it was not put together in a > > form that could be properly updated. Yes I agree with you regarding > > the pending certificates but will the problem such as it is impact us? > > And when? > > - > > Gregg C Levine gregg.drw...@gmail.com > > "This signature fought the Time Wars, time and again." > > > > On Thu, Sep 30, 2021 at 6:19 PM Gregg Levine > > wrote: > > > > > > Hello! > > > Okay, I tried setting that variable, and it did not show me anything. > > > I also looked at the page you suggested. Interesting, I suspect I'd > > > need to do that should I go ahead and want to contribute. > > > > > > As for updating certificates, the big problem is that is a WSL > > > prebuilt image, and someone else built it, and deliberately broke the > > > methods SuSe uses to update things. > > > - > > > Gregg C Levine gregg.drw...@gmail.com > > > "This signature fought the Time Wars, time and again." > > > > > > On Thu, Sep 30, 2021 at 3:37 PM Patrick Georgi > > wrote: > > > > > > > > Hi Gregg, > > > > > > > > Am Do., 30. Sept. 2021 um 21:16 Uhr schrieb Gregg Levine > > : > > > >> > > > >> fatal: unable to access 'https://review.coreboot.org/coreboot.git/ > ': > > > >> SSL certificate problem: certificate has expired > > > > > > > > > > > > Given the timing, I wonder if > https://techcrunch.com/2021/09/21/lets- > > encrypt-root-expiry/ might be the cause: We serve a pretty complete > > certificate chain but if your client doesn't support the root > certificate that we > > now rely on exclusively (because the other path using the more popular > root > > has expired), your client won't like any of our certs. > > > > > > > > You could try changing the environment to carry > > GIT_CURL_VERBOSE=true to see what's going on, or maybe just look at > > updating the ca-certificate store of your system. > > > > > > > > Alternatively you could set up the SSH based access method to access > the > > server, as outlined in > https://doc.coreboot.org/tutorial/part2.html#step-2a- > > set-up-rsa-private-public-key but you might run into more issues with > certs > > going forward on other servers if the cert store is old. > > > > > > > > > > > > All the best, > > > > Patrick > > > > -- > > > > Google Germany GmbH, ABC-Str. 19, 20354 Hamburg > > > > Registergericht und -nummer: Hamburg, HRB 86891, Sitz der > Gesellschaft: > > Hamburg > > > > Geschäftsführer: Paul Manicle, Halimah DeLaine Prado > >
