[coreboot] Re: Add memory support for mb/apple: MacBook Air 5,2 (A1466)
Hi! Thank you. Just in case, can you please also attach the full output of inteltool -g. On 04.12.2021 13:30, Mariusz Grabarczyk wrote: Hi I would like to have memory support added for mb/apple: MacBook Air 5,2 (A1466) Per https://review.coreboot.org/c/coreboot/+/32604/36/Documentation/mainboard/apple/macbookair5_2.md#51 Originally https://review.coreboot.org/c/coreboot/+/32604 If your RAM configuration is not supported, you can help supporting it. Run `sudo inteltool -m`, save output to a text file and send a message to coreboot inteltool -g | get_macbook_ramcfg -m mba52 unsupported memory configuration 1 inteltool -m >> macbook52_memory Attached is dump file ___ coreboot mailing list --coreboot@coreboot.org To unsubscribe send an email tocoreboot-le...@coreboot.org___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Extended IvyBridge CPU configuration
So, it's been three weeks, no hangs, no crashes, everything's fine on my W530 (which is my primary working machine) with 5.4.28-gentoo kernel and HT disabled by coreboot patch. CPU is i7-3940XM. On 20.06.2020 14:46, Evgeny Zinoviev via coreboot wrote: Could be... Thanks for testing! I've also put it on some of my daily work machines: a quad-code Ivy and a dual-code Sandy in order to see how it works in a real world... Works so far. So if it doesn't end up crashing in a week or two I'd say it's stable. We'll see. On 6/20/20 1:42 PM, Lars Hochstetter wrote: Update II: All tests passed with and without HT enabled! I discovered something curious though - if I disable HT memtest86+ finishes a pass in 45ish minutes. If I enable HT it takes 4+ hours. I don't know if it's due to coreboot or memtest86+ as memtest86+ v5.01 also took around 4+ hours for all tests with HT enabled. Maybe it is a bug with memtest86+ ? On 19.06.20 00:58, Lars Hochstetter wrote: Update: I managed to get memtest86+ v5.31b running. I downloaded the .iso.zip and used geteltorito v0.6 to turn the .iso file into a 1.44meg floppy image. I then added the floppy image like the memtest86+ v5.01 floppy image to my coreboot image (4.12 + patchset 15). Preliminary tests with memtest86+ v5.31b went without an issue (Note: I didn't run all the tests, but test #7 was passed with and without HT). I'll try to run all tests with and without HT on 4.12 + patchset 15 around the weekend. ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Extended IvyBridge CPU configuration
Hi again. There's another patch that fits to the topic that you will probably want to try out: https://review.coreboot.org/c/coreboot/+/42547/ On 12/15/19 3:57 PM, Lars Hochstetter wrote: Hi everyone, I'm looking for an option to configure my Intel IvyBridge CPU (enable / disable Hyperthreading, TurboBoost, set configurable TDP level etc.) using coreboot / nvramcui. My board is a Lenovo Thinkpad T430. So far, "only virtualization" is configurable and can not be enabled / disabled "in flight" but requires a rebuild of coreboot. Is anyone currently working on something similar? Is anything planned in that regard? Kind regards lhochstetter ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Extended IvyBridge CPU configuration
s/code/core/, lol. On 6/20/20 2:46 PM, Evgeny Zinoviev via coreboot wrote: Could be... Thanks for testing! I've also put it on some of my daily work machines: a quad-code Ivy and a dual-code Sandy in order to see how it works in a real world... Works so far. So if it doesn't end up crashing in a week or two I'd say it's stable. We'll see. On 6/20/20 1:42 PM, Lars Hochstetter wrote: Update II: All tests passed with and without HT enabled! I discovered something curious though - if I disable HT memtest86+ finishes a pass in 45ish minutes. If I enable HT it takes 4+ hours. I don't know if it's due to coreboot or memtest86+ as memtest86+ v5.01 also took around 4+ hours for all tests with HT enabled. Maybe it is a bug with memtest86+ ? On 19.06.20 00:58, Lars Hochstetter wrote: Update: I managed to get memtest86+ v5.31b running. I downloaded the .iso.zip and used geteltorito v0.6 to turn the .iso file into a 1.44meg floppy image. I then added the floppy image like the memtest86+ v5.01 floppy image to my coreboot image (4.12 + patchset 15). Preliminary tests with memtest86+ v5.31b went without an issue (Note: I didn't run all the tests, but test #7 was passed with and without HT). I'll try to run all tests with and without HT on 4.12 + patchset 15 around the weekend. ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Extended IvyBridge CPU configuration
Could be... Thanks for testing! I've also put it on some of my daily work machines: a quad-code Ivy and a dual-code Sandy in order to see how it works in a real world... Works so far. So if it doesn't end up crashing in a week or two I'd say it's stable. We'll see. On 6/20/20 1:42 PM, Lars Hochstetter wrote: Update II: All tests passed with and without HT enabled! I discovered something curious though - if I disable HT memtest86+ finishes a pass in 45ish minutes. If I enable HT it takes 4+ hours. I don't know if it's due to coreboot or memtest86+ as memtest86+ v5.01 also took around 4+ hours for all tests with HT enabled. Maybe it is a bug with memtest86+ ? On 19.06.20 00:58, Lars Hochstetter wrote: Update: I managed to get memtest86+ v5.31b running. I downloaded the .iso.zip and used geteltorito v0.6 to turn the .iso file into a 1.44meg floppy image. I then added the floppy image like the memtest86+ v5.01 floppy image to my coreboot image (4.12 + patchset 15). Preliminary tests with memtest86+ v5.31b went without an issue (Note: I didn't run all the tests, but test #7 was passed with and without HT). I'll try to run all tests with and without HT on 4.12 + patchset 15 around the weekend. ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Extended IvyBridge CPU configuration
Hi! Thank you for the report. If you're still on it, can you try the latest update? There was seemingly incorrect reset sequence after setting the HT disable bit. I'm not sure if it was the reason of problems, but would be good to test again. On 6/16/20 12:31 PM, Lars Hochstetter wrote: Sorry for the long silence - I finally found some time to test the HT patch. I used coreboot v4.11 as a basis since at this point in time the patch produced merge conflicts with newer commits. I used memtest86+ v5.01 (forced SMP, RAM: 16GB @ 1600MHz, CPU: Intel i7-3840QM) as mentioned in my last mail. When HT is enabled memtest86+ runs just fine. When I disable HT it gets reproducibly stuck at test #7 (block move), at 4096M-6144M, with cores 0-2 working, core 3 just switched to "W". I'll test some other workloads which were problematic in the past (compiling coreboot, watching videos using Firefox). Shall I provide my .config or any other information? Regards lhochstetter On 11/02/2020 15:23, Lars Hochstetter wrote: I managed to find some time to run memtest86+ v5.01 as a SeaBIOS payload [1]. As it turns out the RAM went bad - I made sure to check with another pair of sticks. I'll replace the RAM and retry the HT patch when my free time allows for it. Sorry for creating so much noise over something so simple. Regards lhochstetter [1] https://mail.coreboot.org/pipermail/coreboot/2018-November/087713.html On 2/8/20 4:23 PM, Lars Hochstetter wrote: Unfortunately I'll be rather busy until mid April this year - here is my plan for the time being: I'll reinstall Linux Mint Cinnamon, integrate memtest86+ into coreboot and run it. I'll report back if it's just bad RAM or something else. Since my T430 was modified a couple times I'd also suggest we try to find someone with a more stock T430 to see if your HT patch works. The X230 somewhere in this thread worked and I'd argue that it does work properly on unmodified Thinkpads. Sorry for a long reply too. About mrc.bin: no, it's actually possible to use mrc blob on Sandy/Ivy, but as I see it's not supported across all boards. X220 has support, other boards needs patching (or maybe patches are already on gerrit, I'm not sure). It shouldn't be hard to get it working, though. Can you elaborate on this one? Why does the X220 has support and other Sandy/IvyBridge based laptops are not supported? Wasn't one of the ideas for coreboot to have a more common code base or am I missing something obvious? Regards lhochstetter ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Query regarding CoreBoot
coreboot doesn't boot the OS, it performs hardware initialization and passes control to a payload (SeaBIOS, GRUB, Tianocore, etc. - these are payloads). So you would have to use something like clover anyway. On 6/8/20 6:22 PM, lol wrote: Hi, I wanted to ask if coreboot is capable of booting macOS. There are bootloaders like clover and opencore that does the job but does coreboot do this thing with more efficiency? ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Status of Optimus work? Target laptops?
Is [1] the current, most recent work on supporting nvidia Optimus? Yes! Needs rebasing, though. ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Installing Core Boot on a Lenovo X230 with a script.
On 2/21/20 9:16 PM, Matt DeVillier wrote: if you want to disable the ME [...], hardware flashing is mandatory). You can also disable ME without external flashing with this patch: https://review.coreboot.org/c/coreboot/+/37115 It will not unlock FD and you can't use more space for coreboot, though. ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Installing Coreboot on a Libreboot Lenovo X200
Hi. You can just use flashrom and flash internally, unless you specifically modified libreboot to set flash protections. It's recommended to flash only bios region (use --ifd -i bios -N), as it's generally safer. On 2/16/20 12:31 PM, Human Human wrote: Hello, I am wondering what steps do I need to take to install Coreboot on a laptop that has Libreboot already installed on it. Do I need to hardware flash Coreboot or can I use flashrom since Libreboot is already installed. Thank you for your time and help. ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Extended IvyBridge CPU configuration
Sorry for a long reply too. About mrc.bin: no, it's actually possible to use mrc blob on Sandy/Ivy, but as I see it's not supported across all boards. X220 has support, other boards needs patching (or maybe patches are already on gerrit, I'm not sure). It shouldn't be hard to get it working, though. Can you elaborate on this one? Why does the X220 has support and other Sandy/IvyBridge based laptops are not supported? Wasn't one of the ideas for coreboot to have a more common code base or am I missing something obvious? Basically, it's just not enabled in other boards' configs. I don't know why exactly it is enabled only in X220, but I can guess it's because the native raminit is preferable, works quite well and nobody needed mrc raminit on other models. You can try this patch https://review.coreboot.org/c/coreboot/+/37153 on your T430. ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: thinkpad x250 support
No, they have Intel Boot Guard, which prevents running custom firmware. On 2/11/20 12:47 PM, Eero Volotinen wrote: Hi, is the thinkpad x250 .. x260 supported in coreboot? ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Extended IvyBridge CPU configuration
I personally don't think that libgfxinit instead of vgabios or vice versa will make any difference in this case. I'd recommend to test native raminit vs mrc.bin instead. Correct me if I'm wrong but isn't the mrc.bin Haswell specific [1]? From what I recall I never saw an option in "make menuconfig" to choose native raminit or mrc.bin on IvyBridge. If there is such an option (now) I'll definitely try it! Sorry for a long reply too. About mrc.bin: no, it's actually possible to use mrc blob on Sandy/Ivy, but as I see it's not supported across all boards. X220 has support, other boards needs patching (or maybe patches are already on gerrit, I'm not sure). It shouldn't be hard to get it working, though. ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Extended IvyBridge CPU configuration
From what I recall, the last coreboot master I tried resulted in crashes without your patch. If it's so, then the HT patch is not to blame... But we'll see after your tests. I intend to run following tests with the latest coreboot master (I'll note the commit hash and use the same commit for all of my tests) and SeaBIOS as payload (blobs will be extracted from the Lenovo OEM BIOS v2.81): 1. fully blob'ed (vgabios, ifd, me, gbe) 2. libgfxinit instead of vgabios 3. fully blob'ed with the me shrinked 4. libgfxinit instead of vgabios with the me shrinked I personally don't think that libgfxinit instead of vgabios or vice versa will make any difference in this case. I'd recommend to test native raminit vs mrc.bin instead. I'm unsure on how to provide the µCode patches, i.e. integrate them in coreboot or have them patched by Linux. If you mean microcode updates, then there's an option in coreboot's config (and you also need to enable use of binary-only repository in the General section). ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Extended IvyBridge CPU configuration
Hi, Lars. Update: I flashed the original Lenovo BIOS v2.81 (with keyboard EC mod) and the issues seem to be gone. Do you have any freezes/crashes while running latest coreboot (from master) without the HT patch? ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Extended IvyBridge CPU configuration
I however also noticed severe freezes / crashes (OS Debian 10.2) but I'm unsure if they are related to the patch or something different. Have you got any logs? Do these crashes/freezes look like https://ticket.coreboot.org/issues/121? ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Extended IvyBridge CPU configuration
OK, I've just updated the patch. Use "hyper_threading" CMOS option to switch it on and off. (Don't forget to enable CMOS support.) On 12/19/19 10:25 AM, Jose Trujillo via coreboot wrote: Hello: I am also interested and will help test and I think it will be the best to leave it as CMOS option. Thank you Jose. Sent with ProtonMail Secure Email. ‐‐‐ Original Message ‐‐‐ On Tuesday, December 17, 2019 5:12 PM, Evgeny Zinoviev via coreboot wrote: Hi. As for HT, there's this patch: https://review.coreboot.org/c/coreboot/+/29669 but it needs polishing and testing. Last time I touched it, it worked good (or so it seemed to me) on X220. If you have an interest and wish help to test, we could finish it. (We also need to decide, whether to leave it as a CMOS option or turn into a Kconfig option.) On 15.12.2019 15:57, Lars Hochstetter wrote: Hi everyone, I'm looking for an option to configure my Intel IvyBridge CPU (enable / disable Hyperthreading, TurboBoost, set configurable TDP level etc.) using coreboot / nvramcui. My board is a Lenovo Thinkpad T430. So far, "only virtualization" is configurable and can not be enabled / disabled "in flight" but requires a rebuild of coreboot. Is anyone currently working on something similar? Is anything planned in that regard? Kind regards lhochstetter coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Extended IvyBridge CPU configuration
Hi. As for HT, there's this patch: https://review.coreboot.org/c/coreboot/+/29669 but it needs polishing and testing. Last time I touched it, it worked good (or so it seemed to me) on X220. If you have an interest and wish help to test, we could finish it. (We also need to decide, whether to leave it as a CMOS option or turn into a Kconfig option.) On 15.12.2019 15:57, Lars Hochstetter wrote: Hi everyone, I'm looking for an option to configure my Intel IvyBridge CPU (enable / disable Hyperthreading, TurboBoost, set configurable TDP level etc.) using coreboot / nvramcui. My board is a Lenovo Thinkpad T430. So far, "only virtualization" is configurable and can not be enabled / disabled "in flight" but requires a rebuild of coreboot. Is anyone currently working on something similar? Is anything planned in that regard? Kind regards lhochstetter ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: DIY debug Dongle
On 13.10.2019 10:27, Mike Banon wrote: With a couple of FT232H from china/aliexpress and two USB extension cables for them Actually, even just one FT232H plus one USB-UART (pl2303, for example) will work. ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Does Coreboot support the following options to enable/disable?
There is unfinished hyperthreading patch for Sandy/Ivy: https://review.coreboot.org/c/coreboot/+/29669 On 7/2/19 9:33 AM, ashmita.chakrabo...@ltts.com wrote: > Does the coreboot support the following options to enable/disable: > > > HyperThreading- Disabled > Execute Disable Bit - Enabled > Intel Virtualization Tech- Enabled > Intel (R) TXT- Disabled > Enhanced Error Containment Mode -Disabled > MLC Streamer -Enabled > MLC Spatial Prefetcher -Enabled > DUC Data Prefetcher -Enabled > DUC Instruction Prefetcher-Enabled > LLC Prefetch - Enabled > Intel Configurable TDB -Enabled > TDP Level -level 2 > > > Please let me know. > > Thanks in advance. > > Regards, > Ashmita Chakraborty > ___ > coreboot mailing list -- coreboot@coreboot.org > To unsubscribe send an email to coreboot-le...@coreboot.org ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Starting the coreboot 4.10 release process
Your plan worked, I've just uploaded board status for 4 more boards. On 6/2/19 9:26 PM, Mike Banon wrote: > I've just added a "Recently tested mainboards:" section to the end of > https://piratenpad.de/p/coreboot4.10-release-checklist . I think its' > existence could encourage the people to submit a board status report > for their board, to increase its' visibility and attract more > potential users/developers who'll read these release notes at some > opensource-dedicated websites and may become interested at coreboot > project. This section includes 6 laptops and 2 desktops for which the > board status reports have been submitted during May and the beginning > of June. Luckily 4.10 release is not there yet, so the people still > have some time to submit a fresh board status for their board and then > it could be included to this list. > > Also, regarding the significant changes: " ### Tianocore UEFI > integrated as payload " . I hope it doesn't mean that Tianocore will > become the default payload, since there are ideological/technical > reasons against this ( I think there's a significant overlap between > the groups of people who love / interested in coreboot and hate UEFI ) > > Recently tested mainboards: > --- > * Lenovo Ideapad G505S > * Lenovo Thinkpad T400 > * Lenovo Thinkpad T430 > * Lenovo Thinkpad T430s baseboard > * Lenovo Thinkpad X131e Chromebook > * Lenovo Thinkpad X230 > * Gigabyte GA-B75M-D3H > * Asrock E350M1 > > On Fri, May 10, 2019 at 11:17 PM Patrick Georgi via coreboot > wrote: >> Hi everybody, >> >> with this mail I'm officially starting the 4.10 release process. >> As per the first step of our checklist >> (Documentation/releases/checklist.md), I hereby announce the intent to >> release coreboot 4.10 in about 2 weeks. I'm aiming for May 28th to avoid >> releasing into the weekend or on Memorial Day in the US, but I'll likely >> lock down the commit we'll designate 4.10 during those days to give some >> room for testing. >> >> I created a copy of the checklist on >> https://piratenpad.de/p/coreboot4.10-release-checklist, also including the >> current state of the 4.10 release notes. >> >> Please test the boards you have around and provide fixes, please be careful >> with intrusive changes (and maybe postpone them until after the release) and >> please update the release notes >> (Documentation/releases/coreboot-4.10-relnotes.md or near the bottom of the >> etherpad doc, I'll carry them over into our git repo then). >> >> As promised with the 4.9 release there won't be deprecations after 4.10. >> However we need to finalize our set of deprecations we want to announce with >> 4.10 that will happen after the 4.11 release (those also belong in the >> release notes). >> >> >> Regards, >> Patrick >> -- >> Google Germany GmbH, ABC-Str. 19, 20354 Hamburg >> Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: >> Hamburg >> Geschäftsführer: Paul Manicle, Halimah DeLaine Prado >> ___ >> coreboot mailing list -- coreboot@coreboot.org >> To unsubscribe send an email to coreboot-le...@coreboot.org > ___ > coreboot mailing list -- coreboot@coreboot.org > To unsubscribe send an email to coreboot-le...@coreboot.org ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
