Re: [coreboot] Custom Layer or Overlay

[Naveed Ghori]

Thanks David.
Not sure if it exactly what I recall as being mentioned. .. but could be
wrong.

Basically I wanted to place my proprietary board files in a location that
would not pollute the main Coreboot repo with boards that no one else has
access to.
I will look further into thridparty but according to the text file you
pointed to it is probably not exactly what I am after.

On Sat, Feb 10, 2018 at 4:56 AM, David Hendricks 
wrote:

> Hi Naveed,
> 3rdparty/ is probably what you want. That directory is managed using git
> submodules: https://review.coreboot.org/cgit/coreboot.git/tree/Documenta
> tion/submodules.txt
>
>
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[coreboot] Custom Layer or Overlay

[Naveed Ghori]

Hi,
At the Detroit conference someone mentioned that there can is a place to
put proprietary code that is not for checking in to the public coreboot
repo.

I could not find this information on the coreboot website. Maybe I was
looking in the wrong places or using the wrong keyword.

Can some please enlighten me as to where to put such code. I believe it was
a speicif name folder in the root of the repo.

Thanks in advance.

Best Regards,
Naveed
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Re: [coreboot] [RFH] Draft release notes for coreboot 4.7

[Naveed Ghori]

Hi all,

Going forward would it be worth doing release notes progressively as bug fixes 
and features are added to the code. This may make the actual release process 
easier.
As I have not contributed to bug fixes/features this far I may be missing 
something (e.g. this is already happening)

My 2c.
Regards,
Naveed

-Original Message-
From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Paul Menzel
Sent: Thursday, 21 December 2017 4:24 PM
To: coreboot@coreboot.org
Subject: [coreboot] [RFH] Draft release notes for coreboot 4.7

Dear coreboot folks,


Martin said, that the missing/unwritten release notes are the reason holding up 
the coreboot 4.7 release.

Could the maintainers, developers, and users please jump in and help write 
them. Please use the pad [1]. Some coreboot folks already contributed. Big 
thank you to them.

Also, thanks to the now mostly great and elaborate commit messages, the release 
notes should really just give a broad overview. The detail can then be looked 
up.

Additionally, can you think of the something that has to be adapted by someone 
switching from coreboot 4.6 to coreboot 4.7?


Thanks,

Paul


[1] 
https://linkprotect.cudasvc.com/url?a=https://pads.ccc.de/s7c2eXetAu&c=E,1,jYNN-Jv9ujvYDutxAcDWBlDkhPkoO2Jq8oAI8X4PYtQ7zeuZLh9bn1D2uHLy7YMVUAtUNdCMb3FBPzxNXpO98kzhHUXj62jbpqeLIwjRmHPma5xOv-HkZAk,&typo=1
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Re: [coreboot] Can't disable CONFIG_ENABLE_FSP_FAST_BOOT flag on Intel Baytrail platform

[Naveed Ghori]

Nico,
I faced this same thing earlier I believe.
The reason I disabled it was to stop coreboot from writing to the flash chip. I 
was advised to turn off CONFIG_ENABLE_FSP_FAST_BOOT and this worked for the 
flash but had this side affect.

Garrett, Are you disabling it for the same reason?

Regards,
Naveed

-Original Message-
From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Nico Huber
Sent: Wednesday, 13 December 2017 2:12 AM
To: GARRETT DOORENBOS; coreboot@coreboot.org
Subject: Re: [coreboot] Can't disable CONFIG_ENABLE_FSP_FAST_BOOT flag on Intel 
Baytrail platform

Hello Garrett,

On 11.12.2017 18:16, GARRETT DOORENBOS wrote:
> I'm running coreboot on an Intel Atom Bay Trail based platform. When I 
> turn off the CONFIG_ENABLE_FSP_FAST_BOOT flag, I get stuck in the 
> Intel FSP (it never returns) after a warm boot. The only way around it 
> is a power cycle. Has anyone seen this before?

AFAICS, the Bay Trail FSP doesn't have such an option. So it might be the case 
that the binary always expects a non-volative cache. But that is disabled in 
coreboot if you disable ENABLE_FSP_FAST_BOOT (by chance).
Intel is known to present options where only one value works.

The correct solution seems to be to always `select ENABLE_MRC_CACHE` for 
fsp_baytrail and remove the related guards in its code. And hide 
ENABLE_FSP_FAST_BOOT for fsp_baytrail because it just doesn't apply.

May I ask why you want to disable fast boot?

Hope that helps,
Nico

> Hello,
> 
> 
> Thanks,
> Garrett Doorenbos
> Software Engineer - Almost Hardware
> 
> Office: 256.963.6369
> Email: 
> garrett.dooren...@adtran.com
> Web: 
> https://linkprotect.cudasvc.com/url?a=https://www.adtran.com&c=E,1,zia
> _2uPTk6eMKH9gxkBHCoibI9nwJEX2LFUylJISwIdygIKxKW7m9UY_xFRaUZNXqWJbsPdXa
> zGCnP8yadglsZ-8otIfNn5reQKUZwil-62tbqBxWi6O&typo=1 .cudasvc.com/url?a=http://s.bl-1.com/h/CoY1mz9%3furl%3dhttp://www.adtr
> an.com&c=E,1,beG-szik-KkZHDBsYBUzzoYyR9r5_94FiWhrk0r_Jz7lqTwQtZS9QP3Bp
> NWye1btciSTvOOYIxQVfV-GDtWIzNVSVkhXlNoT7wIQGQEtnw,,&typo=1>
> 
> ADTRAN
> 901 Explorer Boulevard
> Huntsville, AL 35806 - USA
> 
> [ADTRAN] 1mz9%3furl%3dhttp://www.adtran.com&c=E,1,ihpsTD49cQZcEW4B_7z9R-e0pweJL
> hZ2Jc7tv8TAZgScBYpApgkTONb1FlsLlksahwDapvtGPkUDoCG6M4ntljQ71glwSRSrrHL
> xu6IHzg,,&typo=1>
> 

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Re: [coreboot] Can't disable CONFIG_ENABLE_FSP_FAST_BOOT flag on Intel Baytrail platform

[Naveed Ghori]

Garrett,
I have seen this before. Details are probably in the coreboot list logs 
somewhere.
It basically would freeze on reboot and then after about 20s reset it self.
I have bypassed the issue without actually fixing it but forcing a CPU reset on 
reboot.

PS: I had disabled it to ensure that bios chip was not written to, so we can 
now do a verify on the whole chip.
Hope this helps.
Naveed

From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of GARRETT 
DOORENBOS
Sent: Tuesday, 12 December 2017 1:17 AM
To: coreboot@coreboot.org
Subject: [coreboot] Can't disable CONFIG_ENABLE_FSP_FAST_BOOT flag on Intel 
Baytrail platform

Hello,

I'm running coreboot on an Intel Atom Bay Trail based platform. When I turn off 
the CONFIG_ENABLE_FSP_FAST_BOOT flag, I get stuck in the Intel FSP (it never 
returns) after a warm boot. The only way around it is a power cycle. Has anyone 
seen this before?

Thanks,
Garrett Doorenbos
Software Engineer - Almost Hardware

Office: 256.963.6369
Email: garrett.dooren...@adtran.com
Web: 
www.adtran.com

ADTRAN
901 Explorer Boulevard
Huntsville, AL 35806 - USA

[ADTRAN]

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Re: [coreboot] 2017 North American coreboot Conference

[Naveed Ghori]

Hi,
Any update on registration payment and number of people attending.
I guess I just want verification that it is still on there has been no 
communications recently.

Cheer,
Naveed

From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Martin Roth
Sent: Friday, 3 February 2017 1:32 AM
To: coreboot
Subject: [coreboot] 2017 North American coreboot Conference

We are happy to announce that the 2017 North American coreboot Conference will 
be held in Denver, Colorado on June 5th & 6th, with an optional hacking day on 
June 7th.


Register here:  https://goo.gl/o2j4gX


The cost will be $250 for corporate attendees, $100 for individuals, and $25 
for students.
All fees go up by $50 for registrations received after May 5.
Payment is NOT required at the time of registration.  We will contact you later 
with payment information.


Hotel, travel, and other additional information is available on the coreboot 
wiki: 
https://www.coreboot.org/Denver2017


If you have any questions, please email us at 
convent...@coreboot.org


Martin
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Re: [coreboot] INTEL VBT (Video BIOS Table)

[Naveed Ghori]

Please check. Link not working for me.

From: coreboot [coreboot-boun...@coreboot.org] on behalf of Zoran Stojsavljevic 
[zoran.stojsavlje...@gmail.com]
Sent: Saturday, 8 April 2017 9:48 PM
To: coreboot
Subject: [coreboot] INTEL VBT (Video BIOS Table)

Here it is: https://en.wikipedia.org/wiki/Coreboot/VBT

Feel absolutely free to review it, to add/modify/discuss/hit me with the 
baseball bat, yell/scream/sob at me... :-)

Best Regards,
Zoran

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Re: [coreboot] Coreboot 4.5: No early serial output

[Naveed Ghori]

Fixed.
Best I can tell it was due to a clean build as all the other parameters are the 
same.
I had gone back to v4.4 to rebuild and check too, but the problem has 
persisted. Potentially to do with using .config from a different version of 
coreboot.

But it works so no more investigation ☺.
Naveed

From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com]
Sent: Thursday, 30 March 2017 12:49 AM
To: Naveed Ghori
Cc: coreboot@coreboot.org
Subject: Re: [coreboot] Coreboot 4.5: No early serial output

Hello Naveed,

> In Coreboot 4.4 (Intel baytrail FSP) early serial output use to work (first 
> line being coreboot version followed by RTC Init)
> In Coreboot 4.5 it seems that serial output only works once the FSP 
> initializes the serial port (first line being romstage_main_continue).

What entity initializes serial port in Coreboot 4.4 (BYT FSP or Coreboot 
itself)? In which stage?

Once you get answer to this question, you should know what to do for/in 
Coreboot 4.5 . ;-)

Zoran

On Wed, Mar 29, 2017 at 10:55 AM, Naveed Ghori 
mailto:naveed.gh...@dti.com.au>> wrote:
Hi all,

In Coreboot 4.4 (Intel baytrail FSP) early serial output use to work (first 
line being coreboot version followed by RTC Init)
In Coreboot 4.5 it seems that serial output only works once the FSP initializes 
the serial port (first line being romstage_main_continue).

Notes: Setup for spew output, using the debug serial port lines.
I am looking at what might have caused this but though I’d ask if this was a 
known issue, possibly already fixed with a patch or if it was an error on my 
part.

Note sure exactly where to search as I have already reviewed the changes in 
src/drivers/uart/uart8250io.c

Regards,
Naveed
Naveed Ghori | Lead Firmware & Driver Engineer


DTI Group Ltd | Transit Security & Surveillance


31 Affleck Road, Perth Airport, Western Australia 6105, Australia

P +61 8 9373 2905,151 | F +61 8 9479 
1190 | 
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[coreboot] Coreboot 4.5: No early serial output

[Naveed Ghori]

Hi all,

In Coreboot 4.4 (Intel baytrail FSP) early serial output use to work (first 
line being coreboot version followed by RTC Init)
In Coreboot 4.5 it seems that serial output only works once the FSP initializes 
the serial port (first line being romstage_main_continue).

Notes: Setup for spew output, using the debug serial port lines.
I am looking at what might have caused this but though I'd ask if this was a 
known issue, possibly already fixed with a patch or if it was an error on my 
part.

Note sure exactly where to search as I have already reviewed the changes in 
src/drivers/uart/uart8250io.c

Regards,
Naveed
Naveed Ghori | Lead Firmware & Driver Engineer
DTI Group Ltd | Transit Security & Surveillance
31 Affleck Road, Perth Airport, Western Australia 6105, Australia
P +61 8 9373 2905,151 | F +61 8 9479 1190 | 
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Re: [coreboot] SPI Flash Writeprotect

[Naveed Ghori]

It was the MRC cache. :)
One issue however with disabling the cache is that we get a long 20-30s beep 
(annoyingly loud :)) on shutdown. Any idea why as it doesn't seem to do this 
with the MRC cache turned off.

I might start a new thread for this depending on response.
Cheers,
And again Thanks for the help in this regard.

-Original Message-
From: Naveed Ghori 
Sent: Tuesday, 28 February 2017 9:59 AM
To: coreboot@coreboot.org
Subject: RE: [coreboot] SPI Flash Writeprotect


Thanks all for your suggestions. I do have fast boot enabled (and probably MRC 
cache too). I will try to disable that.

Main issue was that we have had a unit not boot up at all and a unit not boot 
up properly (as in Windows logo would fade in and out but stay in that state 
without progressing).

Both issues were fixed by writing the same bios (using a programmer or if the 
system would boot) or flashrom. This write should however remove anything 
written by the system on first boot. This makes me think that the cache or 
whatever else is writing to the flash chip is causing the system to fail.

I will test and update once I know if it was the MRC writing to the flash.
Regards,
Naveed
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Re: [coreboot] SPI Flash Writeprotect

[Naveed Ghori]

Thanks all for your suggestions. I do have fast boot enabled (and probably MRC 
cache too). I will try to disable that.

Main issue was that we have had a unit not boot up at all and a unit not boot 
up properly (as in Windows logo would fade in and out but stay in that state 
without progressing).

Both issues were fixed by writing the same bios (using a programmer or if the 
system would boot) or flashrom. This write should however remove anything 
written by the system on first boot. This makes me think that the cache or 
whatever else is writing to the flash chip is causing the system to fail.

I will test and update once I know if it was the MRC writing to the flash.
Regards,
Naveed
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[coreboot] SPI Flash Writeprotect

[Naveed Ghori]

Hi all,
Does Coreboot write to the flash chip it resides on? Can this be disabled?
Verify of the SPI bios chip fails once the unit has booted up at least once.

Best Regards,
Naveed
Naveed Ghori | Lead Firmware & Driver Engineer
DTI Group Ltd | Transit Security & Surveillance
31 Affleck Road, Perth Airport, Western Australia 6105, Australia
P +61 8 9373 2905,151 | F +61 8 9479 1190 | 
naveed.gh...@dti.com.au<mailto:naveed.gh...@dti.com.au>

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Re: [coreboot] chat.coreboot.org is on

[Naveed Ghori]

All

I find forums easier to navigate (depending on the forum provider) and follow a 
discussion. Email archives currently) are per month rather than per topic. A 
discussion it seems can be split if it happens across months.

Moderation should be just as much as emails as any request to remove stuff from 
archive whould be just as tedious so we do not lose anything there as far as I 
know. In fact might be easier depending on the forum software used.

Data loss again is probably just as likely in email archive as forum.

My 2c.

Naveed


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Re: [coreboot] chat.coreboot.org is on

[Naveed Ghori]

+1 to the web forum approach.

-Original Message-
From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Philipp 
Stanner
Sent: Saturday, 7 January 2017 4:20 PM
To: Patrick Georgi
Cc: coreboot@coreboot.org
Subject: Re: [coreboot] chat.coreboot.org is on

That's a wise decision.

If you'd ask me I would also think about creating a coreboot-forum. It would 
make certain diskussions more clear than the mailing list, especially if they 
last longer than a few days.

Am 07.01.2017 um 08:42 schrieb Patrick Georgi:
> Hi all,
>
> we've set up a mattermost instance on 
> https://linkprotect.cudasvc.com/url?a=https://chat.coreboot.org/&c=E,1,e9Yrcx6WE9pXqu38xm5Z4EWfyYNQElN_jUb4iNzmswa5RHE0-Ed8y0ybRUyQsv4aB9OvGL2IMlhhv8vxRy3_d2D7AqbGC6lsjiDg_kT_Tn10vUyVxNQ,&typo=1
>  in the hope to lower the barriers to entry into our community.
>
> It comes with a bridge to IRC, history (but not web-indexable, which 
> was a major concern with IRC logs so far) and the ability to start 
> topic channels that are discoverable yet separate from the main 
> discussion.
>
>
> See you there,
> Patrick
>


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Re: [coreboot] USB3.0 enumeration in Baytrail E3845 with coreboot

[Naveed Ghori]

Mayuri

If you have eHCI enabled then it may use that instaed of xHCI. With eHCI you 
will not have any USB 3.0 support.
There is switching mode for enabling xHCI in the OS and use eHCI during boot 
but it does not appear to be supported as is in the FSP.
I had attempted to get this going but found the easier way is to enabled xHCI 
only. However you then have to mod Windows 7 install image (boot,img) file to 
support the xHCI intel drivers or you will not have any USB devices working in 
the installer (including the installation USB).

Naveed


From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Mayuri 
Tendulkar
Sent: Thursday, 4 August 2016 1:15 PM
To: Zoran Stojsavljevic
Cc: coreboot
Subject: Re: [coreboot] USB3.0 enumeration in Baytrail E3845 with coreboot

Hi Zoran

Thanks for your inputs.

I am checking on Ubuntu.

As per minnowmax, devicetree.cb file, below like says default will be EHCI.

How we should change it at runtime, what is the setting?

device pci 14.0 on end # 8086 0F35 - USB XHCI - Onboard & HSEC  - Enabling 
both EHCI and XHCI will default to EHCI if not changed at runtime
device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling both EHCI and XHCI 
will default to EHCI if not changed at runtime

regards
Mayuri

From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com]
Sent: 04 August 2016 01:06
To: Mayuri Tendulkar 
mailto:mayuri.tendul...@aricent.com>>
Cc: coreboot mailto:coreboot@coreboot.org>>
Subject: Re: [coreboot] USB3.0 enumeration in Baytrail E3845 with coreboot

Hello Mayuri,

Some of us (at least me) know that INTEL USB 3.0 implementations have here and 
there mortal problems for years, as well as in CORE, also in ATOM families. 
There are lists of problems, but most of them are closed Intellectual 
Properties, INTEL Inside.

I had yesterday terrible problem to set CANON PIXMA MG3650 home printer edition 
I bought in Saturn to pair over USB with my mobile i5-4300 INTEL Inside HSW 
laptop (CPUID 0x40561), so I needed 4 hours to investigate and find the interim 
solution for INTEL buggy embedded USB 3.0 root port (it is consumers' QA issue 
with INTEL design, so INTEL should take care of this, my best guess)... :-((

In this lieu I will advise you the two way approach.

One is to contact/to engage with your INTEL FAE/representative, and ask him 
about the problems which are well described in internal INTEL documents (BYT 
wise).

The other approach is to work out these problems yourself. So, there are 
several facts about the USB 3.0.

There are (my best guess) some BYT USB fixes done by other people in Coreboot. 
I'll let these people to speak for themselves. If? You can also try to bring 
some Linux distros (Fedora for example) and try to see what is going on while 
you bring up the system (dmesg log). Also you can do the following commands:
   lsusb -v
   lsusb -t

At least, you can do lsusb --h to see options which can help you to start 
debugging this issue.

Zoran

On Wed, Aug 3, 2016 at 11:23 AM, Mayuri Tendulkar 
mailto:mayuri.tendul...@aricent.com>> wrote:
Hi

I am facing issue in enumerating USB3.0 device on baytrail processor with 
coreboot with seabios.

Is there any setting in coreboot where we need to enable this separately.

Regards
Mayuri
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[coreboot] Support for USB auto switching in Intel FSP

[Naveed Ghori]

Hi all,

I wanted to know if anyone had gotten the Intel FSP to work with auto mode. It 
does not work for me in Seabios. I have not tried EDKII yet.
However I believe the FSP is not setup for it anyway out of the box.

Any help appreciated.
Naveed Ghori

Naveed Ghori | Lead Firmware & Driver Engineer

DTI Group Ltd | Transit Security & Surveillance

31 Affleck Road, Perth Airport, Western Australia 6105, AU

P +61 8 9373 2905,151 | F +61 8 9479 1190 | naveed.gh...@dti.com.au



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Re: [coreboot] Help on setting clock speed in coreboot

[Naveed Ghori]

Great to hear! Serial does give out some useful information too so it will be 
useful.
Maybe try a different board if you have multiples.

From: Mayuri Tendulkar [mailto:mayuri.tendul...@aricent.com]
Sent: Wednesday, 13 July 2016 8:21 AM
To: Naveed Ghori; coreboot
Subject: Re: Help on setting clock speed in coreboot

Hi

We got some brkthru today. Though serial still shows garbage, we got bios up 
and then OS also. USB, display came up, but serial still no luck.

We will continue debugging. Thanks for all support.

We are using serial to USB, we tried putty as well as minicom.

Regards
Mayuri

From: Naveed Ghori [mailto:naveed.gh...@dti.com.au]
Sent: 12 July 2016 17:12
To: Mayuri Tendulkar 
mailto:mayuri.tendul...@aricent.com>>; coreboot 
mailto:coreboot@coreboot.org>>
Subject: Re: Help on setting clock speed in coreboot

The only thing I can think of is to use an oscilloscope to see if the signal is 
clear.
No changes were made to the USB as it just comes up to as a COM Port and I 
connect using putty at the required baud rate.
Are you using a Serial to USB or a real RS232 serial port? On Windows there are 
setting for each serial port (where you can set its baud rate etc, but I think 
these are for default connection and do not affect most terminal software that 
connect using a particular baud rate.

From: Mayuri Tendulkar [mailto:mayuri.tendul...@aricent.com]
Sent: Wednesday, 13 July 2016 2:18 AM
To: Naveed Ghori; coreboot
Subject: Re: Help on setting clock speed in coreboot

Hi

Minnowboard also uses the same pin BD14 (GPIO_S0_SC[57]) as TX and 61 as RX and 
baud rate 115200.

We have not enabled post codes, but only enabled serial port console o/p.

It works fine on Minnowboard, but not on this.

So not getting any clue.

Regards
Mayuri

From: Naveed Ghori [mailto:naveed.gh...@dti.com.au]
Sent: 11 July 2016 20:03
To: Mayuri Tendulkar 
mailto:mayuri.tendul...@aricent.com>>; coreboot 
mailto:coreboot@coreboot.org>>
Subject: Re: Help on setting clock speed in coreboot

First thing is to get serial output as there will probably be other hurdles 
before the display works.
I used coreboot bayleybay as the basis and it had the port mentioned (pin BD14 
(GPIO_S0_SC[57]))) setup for debug output and the baud rate of 115200.
Minnowboard may be different.
Also,  I had to setup the full 8MB of flash using the FITC tool but this is 
probably not your issue since you probably have serial output already.
All I can think of is baud rate setting under console in "make menuconfig".

Also the output may be setup to output POST codes only in which case to a text 
terminal it will like only junk is coming out. Make sure console debug level is 
set to DEBUG or SPEW to get a lot more debug initially.
Also Enable "Serial Port Console output"


From: Mayuri Tendulkar [mailto:mayuri.tendul...@aricent.com]
Sent: Tuesday, 12 July 2016 10:53 AM
To: Naveed Ghori
Subject: Re: Help on setting clock speed in coreboot

We didn't change anything. Our base is valley island. As it was not having 
serial, we took tht part same as Minnowboard (PCU UART)

Tried different rates but doesn't work.

We checked TTL levels, so we were seeing freq as 38.4, so tried tht also.

Somehow its stuck somewhere as we don't see USB and display also not coming, 
but nt able to get exact data due to serial prints.

From: Naveed Ghori [mailto:naveed.gh...@dti.com.au]
Sent: 11 July 2016 19:48
To: Mayuri Tendulkar 
mailto:mayuri.tendul...@aricent.com>>
Subject: Re: Help on setting clock speed in coreboot

Did you change anything? Is your base Bayley Bay? The default setting for it 
are 115200 with the output pin as per below.
Check the console settings in the menuconfig. If you are getting junk then I 
assume it is already enabled but maybe just the baud is modified by mistake.

From: Mayuri Tendulkar [mailto:mayuri.tendul...@aricent.com]
Sent: Tuesday, 12 July 2016 10:45 AM
To: Naveed Ghori
Subject: Re: Help on setting clock speed in coreboot

But what settings to be added in coreboot config?

From: Naveed Ghori [mailto:naveed.gh...@dti.com.au]
Sent: 11 July 2016 18:42
To: Mayuri Tendulkar 
mailto:mayuri.tendul...@aricent.com>>; coreboot 
mailto:coreboot@coreboot.org>>
Subject: Re: Help on setting clock speed in coreboot

We take the pins direct off the E3845 (only really need the tx (pin BD14 
(GPIO_S0_SC[57]))). The pins direct are TTL so we had to use a TTL-USB serial 
port converter.

From: Mayuri Tendulkar [mailto:mayuri.tendul...@aricent.com]
Sent: Tuesday, 12 July 2016 9:37 AM
To: Naveed Ghori; coreboot
Subject: Re: Help on setting clock speed in coreboot

Thanks. We tried 115200, but it didn't work. We checked TTL levels and tried to 
match, but no luck.

Are you using PCU UART (same as minnowboard) or anything different?

From: Naveed Ghori [mailto:naveed.gh...@dti.com.au]
Sent: 11 July 2016 18:17
To: Mayuri Tendulkar 
mailto:mayuri.tendul...@aricent.com>>; coreb

Re: [coreboot] Help on setting clock speed in coreboot

[Naveed Ghori]

The only thing I can think of is to use an oscilloscope to see if the signal is 
clear.
No changes were made to the USB as it just comes up to as a COM Port and I 
connect using putty at the required baud rate.
Are you using a Serial to USB or a real RS232 serial port? On Windows there are 
setting for each serial port (where you can set its baud rate etc, but I think 
these are for default connection and do not affect most terminal software that 
connect using a particular baud rate.

From: Mayuri Tendulkar [mailto:mayuri.tendul...@aricent.com]
Sent: Wednesday, 13 July 2016 2:18 AM
To: Naveed Ghori; coreboot
Subject: Re: Help on setting clock speed in coreboot

Hi

Minnowboard also uses the same pin BD14 (GPIO_S0_SC[57]) as TX and 61 as RX and 
baud rate 115200.

We have not enabled post codes, but only enabled serial port console o/p.

It works fine on Minnowboard, but not on this.

So not getting any clue.

Regards
Mayuri

From: Naveed Ghori [mailto:naveed.gh...@dti.com.au]
Sent: 11 July 2016 20:03
To: Mayuri Tendulkar 
mailto:mayuri.tendul...@aricent.com>>; coreboot 
mailto:coreboot@coreboot.org>>
Subject: Re: Help on setting clock speed in coreboot

First thing is to get serial output as there will probably be other hurdles 
before the display works.
I used coreboot bayleybay as the basis and it had the port mentioned (pin BD14 
(GPIO_S0_SC[57]))) setup for debug output and the baud rate of 115200.
Minnowboard may be different.
Also,  I had to setup the full 8MB of flash using the FITC tool but this is 
probably not your issue since you probably have serial output already.
All I can think of is baud rate setting under console in "make menuconfig".

Also the output may be setup to output POST codes only in which case to a text 
terminal it will like only junk is coming out. Make sure console debug level is 
set to DEBUG or SPEW to get a lot more debug initially.
Also Enable "Serial Port Console output"


From: Mayuri Tendulkar [mailto:mayuri.tendul...@aricent.com]
Sent: Tuesday, 12 July 2016 10:53 AM
To: Naveed Ghori
Subject: Re: Help on setting clock speed in coreboot

We didn't change anything. Our base is valley island. As it was not having 
serial, we took tht part same as Minnowboard (PCU UART)

Tried different rates but doesn't work.

We checked TTL levels, so we were seeing freq as 38.4, so tried tht also.

Somehow its stuck somewhere as we don't see USB and display also not coming, 
but nt able to get exact data due to serial prints.

From: Naveed Ghori [mailto:naveed.gh...@dti.com.au]
Sent: 11 July 2016 19:48
To: Mayuri Tendulkar 
mailto:mayuri.tendul...@aricent.com>>
Subject: Re: Help on setting clock speed in coreboot

Did you change anything? Is your base Bayley Bay? The default setting for it 
are 115200 with the output pin as per below.
Check the console settings in the menuconfig. If you are getting junk then I 
assume it is already enabled but maybe just the baud is modified by mistake.

From: Mayuri Tendulkar [mailto:mayuri.tendul...@aricent.com]
Sent: Tuesday, 12 July 2016 10:45 AM
To: Naveed Ghori
Subject: Re: Help on setting clock speed in coreboot

But what settings to be added in coreboot config?

From: Naveed Ghori [mailto:naveed.gh...@dti.com.au]
Sent: 11 July 2016 18:42
To: Mayuri Tendulkar 
mailto:mayuri.tendul...@aricent.com>>; coreboot 
mailto:coreboot@coreboot.org>>
Subject: Re: Help on setting clock speed in coreboot

We take the pins direct off the E3845 (only really need the tx (pin BD14 
(GPIO_S0_SC[57]))). The pins direct are TTL so we had to use a TTL-USB serial 
port converter.

From: Mayuri Tendulkar [mailto:mayuri.tendul...@aricent.com]
Sent: Tuesday, 12 July 2016 9:37 AM
To: Naveed Ghori; coreboot
Subject: Re: Help on setting clock speed in coreboot

Thanks. We tried 115200, but it didn't work. We checked TTL levels and tried to 
match, but no luck.

Are you using PCU UART (same as minnowboard) or anything different?

From: Naveed Ghori [mailto:naveed.gh...@dti.com.au]
Sent: 11 July 2016 18:17
To: Mayuri Tendulkar 
mailto:mayuri.tendul...@aricent.com>>; coreboot 
mailto:coreboot@coreboot.org>>
Subject: Re: Help on setting clock speed in coreboot

Hi,
Garbage usually means baud rate. Did you try 115200baud?
If you are still getting garbage I would recommend seeing it on the scope and 
making sure voltage levels are fine. The output by default would be TTL level 
and may need to be converted.
I have used some TTL (1.8V if I remember correctly (TTL-232RG) to convert the 
signal so I could read the output.

Cheers,
Naveed

From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Mayuri 
Tendulkar
Sent: Tuesday, 12 July 2016 8:27 AM
To: coreboot
Subject: [coreboot] Help on setting clock speed in coreboot

Hi Team

I have a customized board based on Intel valley island design. Reference design 
uses Intel Baytrail processor E3825, while my design is using E3845.

I am customiz

Re: [coreboot] Help on setting clock speed in coreboot

[Naveed Ghori]

First thing is to get serial output as there will probably be other hurdles 
before the display works.
I used coreboot bayleybay as the basis and it had the port mentioned (pin BD14 
(GPIO_S0_SC[57]))) setup for debug output and the baud rate of 115200.
Minnowboard may be different.
Also,  I had to setup the full 8MB of flash using the FITC tool but this is 
probably not your issue since you probably have serial output already.
All I can think of is baud rate setting under console in "make menuconfig".

Also the output may be setup to output POST codes only in which case to a text 
terminal it will like only junk is coming out. Make sure console debug level is 
set to DEBUG or SPEW to get a lot more debug initially.
Also Enable "Serial Port Console output"


From: Mayuri Tendulkar [mailto:mayuri.tendul...@aricent.com]
Sent: Tuesday, 12 July 2016 10:53 AM
To: Naveed Ghori
Subject: Re: Help on setting clock speed in coreboot

We didn't change anything. Our base is valley island. As it was not having 
serial, we took tht part same as Minnowboard (PCU UART)

Tried different rates but doesn't work.

We checked TTL levels, so we were seeing freq as 38.4, so tried tht also.

Somehow its stuck somewhere as we don't see USB and display also not coming, 
but nt able to get exact data due to serial prints.

From: Naveed Ghori [mailto:naveed.gh...@dti.com.au]
Sent: 11 July 2016 19:48
To: Mayuri Tendulkar 
mailto:mayuri.tendul...@aricent.com>>
Subject: Re: Help on setting clock speed in coreboot

Did you change anything? Is your base Bayley Bay? The default setting for it 
are 115200 with the output pin as per below.
Check the console settings in the menuconfig. If you are getting junk then I 
assume it is already enabled but maybe just the baud is modified by mistake.

From: Mayuri Tendulkar [mailto:mayuri.tendul...@aricent.com]
Sent: Tuesday, 12 July 2016 10:45 AM
To: Naveed Ghori
Subject: Re: Help on setting clock speed in coreboot

But what settings to be added in coreboot config?

From: Naveed Ghori [mailto:naveed.gh...@dti.com.au]
Sent: 11 July 2016 18:42
To: Mayuri Tendulkar 
mailto:mayuri.tendul...@aricent.com>>; coreboot 
mailto:coreboot@coreboot.org>>
Subject: Re: Help on setting clock speed in coreboot

We take the pins direct off the E3845 (only really need the tx (pin BD14 
(GPIO_S0_SC[57]))). The pins direct are TTL so we had to use a TTL-USB serial 
port converter.

From: Mayuri Tendulkar [mailto:mayuri.tendul...@aricent.com]
Sent: Tuesday, 12 July 2016 9:37 AM
To: Naveed Ghori; coreboot
Subject: Re: Help on setting clock speed in coreboot

Thanks. We tried 115200, but it didn't work. We checked TTL levels and tried to 
match, but no luck.

Are you using PCU UART (same as minnowboard) or anything different?

From: Naveed Ghori [mailto:naveed.gh...@dti.com.au]
Sent: 11 July 2016 18:17
To: Mayuri Tendulkar 
mailto:mayuri.tendul...@aricent.com>>; coreboot 
mailto:coreboot@coreboot.org>>
Subject: Re: Help on setting clock speed in coreboot

Hi,
Garbage usually means baud rate. Did you try 115200baud?
If you are still getting garbage I would recommend seeing it on the scope and 
making sure voltage levels are fine. The output by default would be TTL level 
and may need to be converted.
I have used some TTL (1.8V if I remember correctly (TTL-232RG) to convert the 
signal so I could read the output.

Cheers,
Naveed

From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Mayuri 
Tendulkar
Sent: Tuesday, 12 July 2016 8:27 AM
To: coreboot
Subject: [coreboot] Help on setting clock speed in coreboot

Hi Team

I have a customized board based on Intel valley island design. Reference design 
uses Intel Baytrail processor E3825, while my design is using E3845.

I am customizing coreboot for this E3845, but getting just garbage on coreboot, 
so not able to debug where it is stuck.

When I add memory test as secondary payload, I cd see some operations happening 
on console but not able to decode it.

Tried with all possible baud rates, but no success. USB and display also not 
enumerating.

Can you please give some clue? Is it due to different core speed for 
E3835(1.33GHZ) vs E3845(1.91GHz).

Where is the option to change this in coreboot?

Appreciate your support.

Regards
Mayuri
"DISCLAIMER: This message is proprietary to Aricent and is intended solely for 
the use of the individual to whom it is addressed. It may contain privileged or 
confidential information and should not be circulated or used for any purpose 
other than for what it is intended. If you have received this message in error, 
please notify the originator immediately. If you are not the intended 
recipient, you are notified that you are strictly prohibited from using, 
copying, altering, or disclosing the contents of this message. Aricent accepts 
no responsibility for loss or damage arising from the use of the information 
transmitted by this email including dam

Re: [coreboot] Help on setting clock speed in coreboot

[Naveed Ghori]

We take the pins direct off the E3845 (only really need the tx (pin BD14 
(GPIO_S0_SC[57]))). The pins direct are TTL so we had to use a TTL-USB serial 
port converter.

From: Mayuri Tendulkar [mailto:mayuri.tendul...@aricent.com]
Sent: Tuesday, 12 July 2016 9:37 AM
To: Naveed Ghori; coreboot
Subject: Re: Help on setting clock speed in coreboot

Thanks. We tried 115200, but it didn't work. We checked TTL levels and tried to 
match, but no luck.

Are you using PCU UART (same as minnowboard) or anything different?

From: Naveed Ghori [mailto:naveed.gh...@dti.com.au]
Sent: 11 July 2016 18:17
To: Mayuri Tendulkar 
mailto:mayuri.tendul...@aricent.com>>; coreboot 
mailto:coreboot@coreboot.org>>
Subject: Re: Help on setting clock speed in coreboot

Hi,
Garbage usually means baud rate. Did you try 115200baud?
If you are still getting garbage I would recommend seeing it on the scope and 
making sure voltage levels are fine. The output by default would be TTL level 
and may need to be converted.
I have used some TTL (1.8V if I remember correctly (TTL-232RG) to convert the 
signal so I could read the output.

Cheers,
Naveed

From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Mayuri 
Tendulkar
Sent: Tuesday, 12 July 2016 8:27 AM
To: coreboot
Subject: [coreboot] Help on setting clock speed in coreboot

Hi Team

I have a customized board based on Intel valley island design. Reference design 
uses Intel Baytrail processor E3825, while my design is using E3845.

I am customizing coreboot for this E3845, but getting just garbage on coreboot, 
so not able to debug where it is stuck.

When I add memory test as secondary payload, I cd see some operations happening 
on console but not able to decode it.

Tried with all possible baud rates, but no success. USB and display also not 
enumerating.

Can you please give some clue? Is it due to different core speed for 
E3835(1.33GHZ) vs E3845(1.91GHz).

Where is the option to change this in coreboot?

Appreciate your support.

Regards
Mayuri
"DISCLAIMER: This message is proprietary to Aricent and is intended solely for 
the use of the individual to whom it is addressed. It may contain privileged or 
confidential information and should not be circulated or used for any purpose 
other than for what it is intended. If you have received this message in error, 
please notify the originator immediately. If you are not the intended 
recipient, you are notified that you are strictly prohibited from using, 
copying, altering, or disclosing the contents of this message. Aricent accepts 
no responsibility for loss or damage arising from the use of the information 
transmitted by this email including damage from virus."
"DISCLAIMER: This message is proprietary to Aricent and is intended solely for 
the use of the individual to whom it is addressed. It may contain privileged or 
confidential information and should not be circulated or used for any purpose 
other than for what it is intended. If you have received this message in error, 
please notify the originator immediately. If you are not the intended 
recipient, you are notified that you are strictly prohibited from using, 
copying, altering, or disclosing the contents of this message. Aricent accepts 
no responsibility for loss or damage arising from the use of the information 
transmitted by this email including damage from virus."
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Help on setting clock speed in coreboot

[Naveed Ghori]

Hi,
Garbage usually means baud rate. Did you try 115200baud?
If you are still getting garbage I would recommend seeing it on the scope and 
making sure voltage levels are fine. The output by default would be TTL level 
and may need to be converted.
I have used some TTL (1.8V if I remember correctly (TTL-232RG) to convert the 
signal so I could read the output.

Cheers,
Naveed

From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Mayuri 
Tendulkar
Sent: Tuesday, 12 July 2016 8:27 AM
To: coreboot
Subject: [coreboot] Help on setting clock speed in coreboot

Hi Team

I have a customized board based on Intel valley island design. Reference design 
uses Intel Baytrail processor E3825, while my design is using E3845.

I am customizing coreboot for this E3845, but getting just garbage on coreboot, 
so not able to debug where it is stuck.

When I add memory test as secondary payload, I cd see some operations happening 
on console but not able to decode it.

Tried with all possible baud rates, but no success. USB and display also not 
enumerating.

Can you please give some clue? Is it due to different core speed for 
E3835(1.33GHZ) vs E3845(1.91GHz).

Where is the option to change this in coreboot?

Appreciate your support.

Regards
Mayuri
"DISCLAIMER: This message is proprietary to Aricent and is intended solely for 
the use of the individual to whom it is addressed. It may contain privileged or 
confidential information and should not be circulated or used for any purpose 
other than for what it is intended. If you have received this message in error, 
please notify the originator immediately. If you are not the intended 
recipient, you are notified that you are strictly prohibited from using, 
copying, altering, or disclosing the contents of this message. Aricent accepts 
no responsibility for loss or damage arising from the use of the information 
transmitted by this email including damage from virus."
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Windows only seeing 2GB of 4G (Seabios

[Naveed Ghori]

To close out this topic.

Windows 7 (32bit) can address maximum of 4GB so the default setting of 2GB for 
MIMO will reduce the 4GB to 2GB.
If I setup MIMO memory to be 1GB then I can see almost 3GB (2.92MB). The rest 
probably used by graphics etc.

Regards,
Naveed.


-Original Message-
From: Naveed Ghori 
Sent: Wednesday, 8 June 2016 10:27 AM
To: 'Nico Huber'; Zoran Stojsavljevic
Cc: coreboot
Subject: RE: [coreboot] Windows only seeing 2GB of 4G (Seabios

Thanks Nico,
What options should I be looking to tune? 3Gig should be fine as that is what I 
have seen in another product. 

However in that product (non coreboot) It says for "Installed Memory (RAM)" as 
"4.00GB (2.89GB available)": So windows actually shows both what is installed 
and what is available.

Regards,
Naveed
-Original Message-
From: Nico Huber [mailto:nico.hu...@secunet.com] 
Sent: Tuesday, 7 June 2016 5:37 PM
To: Naveed Ghori; Zoran Stojsavljevic
Cc: coreboot
Subject: Re: [coreboot] Windows only seeing 2GB of 4G (Seabios

Hello Naveed,

On 07.06.2016 07:21, Naveed Ghori wrote:
> But I should still see 4GB without any patch. Right?
no, I'm afraid not.

> Windows only see 1.92GB as “Installed Memory (RAM)” in Control Panel->System.
This is correct as the 4GiB address space is not only used for RAM but shared 
with other resources on modern systems.

> I am happy for the system to see up to 4GB only.
It might be possible to tune the configuration a little. But you'd never get 
the full 4GiB. About 3GiB is a common limit today if you really want to run a 
32bit OS without PAE support.

Nico
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Windows only seeing 2GB of 4G (Seabios

[Naveed Ghori]

Thanks Nico,
What options should I be looking to tune? 3Gig should be fine as that is what I 
have seen in another product. 

However in that product (non coreboot) It says for "Installed Memory (RAM)" as 
"4.00GB (2.89GB available)": So windows actually shows both what is installed 
and what is available.

Regards,
Naveed
-Original Message-
From: Nico Huber [mailto:nico.hu...@secunet.com] 
Sent: Tuesday, 7 June 2016 5:37 PM
To: Naveed Ghori; Zoran Stojsavljevic
Cc: coreboot
Subject: Re: [coreboot] Windows only seeing 2GB of 4G (Seabios

Hello Naveed,

On 07.06.2016 07:21, Naveed Ghori wrote:
> But I should still see 4GB without any patch. Right?
no, I'm afraid not.

> Windows only see 1.92GB as “Installed Memory (RAM)” in Control Panel->System.
This is correct as the 4GiB address space is not only used for RAM but shared 
with other resources on modern systems.

> I am happy for the system to see up to 4GB only.
It might be possible to tune the configuration a little. But you'd never get 
the full 4GiB. About 3GiB is a common limit today if you really want to run a 
32bit OS without PAE support.

Nico
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Windows only seeing 2GB of 4G (Seabios

[Naveed Ghori]

But I should still see 4GB without any patch. Right?
Windows only see 1.92GB as “Installed Memory (RAM)” in Control Panel->System.
I am happy for the system to see up to 4GB only.

From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com]
Sent: Tuesday, 7 June 2016 1:13 PM
To: Naveed Ghori
Cc: coreboot
Subject: Re: [coreboot] Windows only seeing 2GB of 4G (Seabios

Hello Naveed,

For you to read: https://en.wikipedia.org/wiki/Physical_Address_Extension

Important: With PAE, IA-32<https://en.wikipedia.org/wiki/IA-32> architecture is 
augmented with additional address lines used to select the additional memory, 
so physical address size increases from 32 bits to 36 bits.

Then, after reading, this can/will help you: 
https://wj32.org/wp/2011/02/23/pae-patch-updated-for-windows-7-sp1/<https://linkprotect.cudasvc.com/url?a=https://wj32.org/wp/2011/02/23/pae-patch-updated-for-windows-7-sp1/&c=E,1,4TzuPPEqEt09bfSHLiacrY50KGLRosTpaWTwnQSnoSKs3XZAVCm1oYCwQgdB0tNnt34H5_afYQx62tS0zDeEB4hnXiXrwGbJe3QaP4bkeTL8zwo,&typo=1>

Zoran


On Tue, Jun 7, 2016 at 6:23 AM, Naveed Ghori 
mailto:naveed.gh...@dti.com.au>> wrote:
Hi all,

I am booting a 32 bit Win 7 image (via Seabios).

Windows is detecting only 1.92GB (even though there is 8GB of memory available.
Being a 32 bit OS I would have expected it to see at least 4GB.

Coreboot logs shows:
Available memory below 4GB: 0x7ae0 (1966M)
Available memory above 4GB: 6144M

What can cause the full 4GB to not be seen. Should I install only 4GB of memory 
instead of 4GB? I have ordered some to try in any case.

Best Regards,
Naveed

Naveed Ghori | Lead Firmware & Driver Engineer

DTI Group Ltd | Transit Security & Surveillance

31 Affleck Road, Perth Airport, Western Australia 6105, AU

P +61 8 9373 2905,151 | F +61 8 9479 
1190 | 
naveed.gh...@dti.com.au<mailto:naveed.gh...@dti.com.au>



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Re: [coreboot] BSOD Win7 x86 for Baytrail E3845 Dsplay Driver

[Naveed Ghori]

Sorry I meant v36_15_0_1091 (x86) which is the latest on the Intel website that 
I can find.
I cannot find v36.15.0.1127.
I am quite sure the driver is OK but that there is something else fundamental 
causing the BSOD. I have used it on another system (non coreboot) with an E3845 
processor.

Regards,
Naveed

From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com]
Sent: Tuesday, 7 June 2016 12:52 PM
To: Naveed Ghori
Cc: coreboot
Subject: Re: [coreboot] BSOD Win7 x86 for Baytrail E3845 Dsplay Driver

Hello Naveed,

Little bit of google searching:
http://wikifixes.com/en/errors/0x/0xC005/?gclid=CJDYx4WIlc0CFY9uGwodBrIHbQ<https://linkprotect.cudasvc.com/url?a=http://wikifixes.com/en/errors/0x/0xC005/%3fgclid%3dCJDYx4WIlc0CFY9uGwodBrIHbQ&c=E,1,maDDPcoFMc0NXq9eFXI27icMuYi0yqHk0ge6jqblQB7xbkdxkSpkP_7kZ6dQdjZ_F3DYoYWn4XS2yUXPct8tjugDIjmi01gD6DBr7JdZ&typo=1>

As I understood, you are using 36.15.0.1 (x86 aka 32b). This is very old one.

The latest to use is: 36.15.0.1127 for x86 and 37.15.0.1127 for x86_64. Please, 
contact INTEL for these EMGD based WIN7/WIN 8.1 GFX drivers.

Zoran

On Tue, Jun 7, 2016 at 5:16 AM, Naveed Ghori 
mailto:naveed.gh...@dti.com.au>> wrote:
Hi all,

I have Windows Embedded Standard 7 x86 working in with SeaBIOS. If I install 
the graphics driver for it however I get a BSOD while Windows is booting up 
(screen flashes before the BSOD)

As a Coreboot newbie it would be good to get an idea as to what may cause this. 
I am thinking video memory allocation.

The error is below:
*** STOP: 0x007E (0xC005, 0x8D58B437, 0x92717C04, 0x927177E0)
*** igdkmd32.sys – Address 8D58B437 base at 8D423000, DateStamp, 53ac9002

The driver version is the Intel EMGD v 36.15.0.1.

Thanks in advance.
Naveed.

Naveed Ghori | Lead Firmware & Driver Engineer

DTI Group Ltd | Transit Security & Surveillance

31 Affleck Road, Perth Airport, Western Australia 6105, AU

P +61 8 9373 2905,151 | F +61 8 9479 
1190 | 
naveed.gh...@dti.com.au<mailto:naveed.gh...@dti.com.au>



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[coreboot] Windows only seeing 2GB of 4G (Seabios

[Naveed Ghori]

Hi all,

I am booting a 32 bit Win 7 image (via Seabios).

Windows is detecting only 1.92GB (even though there is 8GB of memory available.
Being a 32 bit OS I would have expected it to see at least 4GB.

Coreboot logs shows:
Available memory below 4GB: 0x7ae0 (1966M)
Available memory above 4GB: 6144M

What can cause the full 4GB to not be seen. Should I install only 4GB of memory 
instead of 4GB? I have ordered some to try in any case.

Best Regards,
Naveed

Naveed Ghori | Lead Firmware & Driver Engineer

DTI Group Ltd | Transit Security & Surveillance

31 Affleck Road, Perth Airport, Western Australia 6105, AU

P +61 8 9373 2905,151 | F +61 8 9479 1190 | naveed.gh...@dti.com.au



Visit our website www.dti.com.au<http://www.dti.com.au>

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email in error, please inform DTI Group Ltd via the above contact details. If 
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[coreboot] BSOD Win7 x86 for Baytrail E3845 Dsplay Driver

[Naveed Ghori]

Hi all,

I have Windows Embedded Standard 7 x86 working in with SeaBIOS. If I install 
the graphics driver for it however I get a BSOD while Windows is booting up 
(screen flashes before the BSOD)

As a Coreboot newbie it would be good to get an idea as to what may cause this. 
I am thinking video memory allocation.

The error is below:
*** STOP: 0x007E (0xC005, 0x8D58B437, 0x92717C04, 0x927177E0)
*** igdkmd32.sys - Address 8D58B437 base at 8D423000, DateStamp, 53ac9002

The driver version is the Intel EMGD v 36.15.0.1.

Thanks in advance.
Naveed.

Naveed Ghori | Lead Firmware & Driver Engineer

DTI Group Ltd | Transit Security & Surveillance

31 Affleck Road, Perth Airport, Western Australia 6105, AU

P +61 8 9373 2905,151 | F +61 8 9479 1190 | naveed.gh...@dti.com.au



Visit our website www.dti.com.au<http://www.dti.com.au>

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Re: [coreboot] Add bootorder file for Seabios

[Naveed Ghori]

Thanks Martin,
I will definitely check it out.

-Original Message-
From: Martin Roth [mailto:gauml...@gmail.com] 
Sent: Monday, 6 June 2016 12:34 AM
To: Naveed Ghori
Cc: coreboot
Subject: Re: [coreboot] Add bootorder file for Seabios

Hi Naveed,
  Currently, the bootorder file would need to be manually added after the build.
https://linkprotect.cudasvc.com/url?a=https://www.coreboot.org/SeaBIOS%23Configuring_boot_order&c=E,1,iIHTvoLOc1PE_bv9FUhasHzYWn2Our4MRmStwbp6oJAaS9ki3-yRr9XdJjOTP8t6I1Ok7FIAwwfIXsIeCXXkOLVkspQopZzNXxXnbKeQdAlLWbIpCwKQIqo,&typo=1

I just pushed a patch to allow the bootorder to be added during the build 
process.
https://linkprotect.cudasvc.com/url?a=https://review.coreboot.org/15076&c=E,1,Tes-T0GbAGYj9jS89pmfSmIUzgJQ20U0tcGnGhg2Iz6KLhfa5x72wtDQSw8HrOAq9A5AU9F4i3lGNZXkk9qW7VcHbZh0a6alXmfujF8bfW3CGLN5xQ,,&typo=1

Martin

On Tue, May 31, 2016 at 2:28 AM, Naveed Ghori  wrote:
> What is the easiest way to do this.
>
> Is there already a way to do it cleanly and have the bootorder file in 
> the mainboard area or will I have to add a patch to add it on to CBFS.
>
>
>
> Regards,
>
> Naveed Ghori | Lead Firmware & Driver Engineer
>
> DTI Group Ltd | Transit Security & Surveillance
>
> 31 Affleck Road, Perth Airport, Western Australia 6105, AU
>
> P +61 8 9373 2905,151 | F +61 8 9479 1190 | naveed.gh...@dti.com.au
>
>
>
> Visit our website 
> https://linkprotect.cudasvc.com/url?a=https://www.dti.com.au&c=E,1,QPs
> TCBN9uj1QWAuCHJciZF_ToY-hw31WKGXpEEphJo7CcAKcm6E8r14rtIoCjibvTocxd5HKR
> tvGOowohSHfAXvj2Wj3cz0zF1haH9rBk7Z1EQoPDaiwyD4ikg,,&typo=1
>
> The information contained in this email is confidential. If you 
> receive this email in error, please inform DTI Group Ltd via the above 
> contact details.
> If you are not the intended recipient, you may not use or disclose the 
> information contained in this email or attachments.
>
>
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[coreboot] Add bootorder file for Seabios

[Naveed Ghori]

What is the easiest way to do this.
Is there already a way to do it cleanly and have the bootorder file in the 
mainboard area or will I have to add a patch to add it on to CBFS.

Regards,

Naveed Ghori | Lead Firmware & Driver Engineer

DTI Group Ltd | Transit Security & Surveillance

31 Affleck Road, Perth Airport, Western Australia 6105, AU

P +61 8 9373 2905,151 | F +61 8 9479 1190 | naveed.gh...@dti.com.au



Visit our website www.dti.com.au<http://www.dti.com.au>

The information contained in this email is confidential. If you receive this 
email in error, please inform DTI Group Ltd via the above contact details. If 
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Re: [coreboot] Debug builds and memory testing

[Naveed Ghori]

To clarify. DDR3L is the correct one to use (I was wrongly using DDR3)

From: Naveed Ghori
Sent: Tuesday, 31 May 2016 12:45 PM
To: 'Mayuri Tendulkar'; coreboot
Subject: Re: Debug builds and memory testing

I was using DDR3 instead of the low voltage DDR3L

From: Mayuri Tendulkar [mailto:mayuri.tendul...@aricent.com]
Sent: Tuesday, 31 May 2016 12:40 PM
To: Naveed Ghori; coreboot
Subject: Re: Debug builds and memory testing

How u resolved memory issue?

From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Naveed Ghori
Sent: 31 May 2016 06:52
To: coreboot mailto:coreboot@coreboot.org>>
Subject: Re: [coreboot] Debug builds and memory testing

To update this: There are option in the menuconfig to enable various debugging 
options and logs.

From: Naveed Ghori
Sent: Tuesday, 24 May 2016 2:04 PM
To: coreboot
Subject: Debug builds and memory testing

Hi all,

Is there a debug build of coreboot or a way to test memory very early on.
My custom board goes through the romstage just fine but stops booting while 
trying to enumerate the buses.

I am suspecting RAM might be an issue so would like to eliminate that by doing 
a memory test on it.
--
POST: 0x72
Enumerating buses...
Show all devs... Before device enumeration.
Root Dev
--

Thanks in advance,
Naveed
"DISCLAIMER: This message is proprietary to Aricent and is intended solely for 
the use of the individual to whom it is addressed. It may contain privileged or 
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other than for what it is intended. If you have received this message in error, 
please notify the originator immediately. If you are not the intended 
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Re: [coreboot] Debug builds and memory testing

[Naveed Ghori]

I was using DDR3 instead of the low voltage DDR3L

From: Mayuri Tendulkar [mailto:mayuri.tendul...@aricent.com]
Sent: Tuesday, 31 May 2016 12:40 PM
To: Naveed Ghori; coreboot
Subject: Re: Debug builds and memory testing

How u resolved memory issue?

From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Naveed Ghori
Sent: 31 May 2016 06:52
To: coreboot mailto:coreboot@coreboot.org>>
Subject: Re: [coreboot] Debug builds and memory testing

To update this: There are option in the menuconfig to enable various debugging 
options and logs.

From: Naveed Ghori
Sent: Tuesday, 24 May 2016 2:04 PM
To: coreboot
Subject: Debug builds and memory testing

Hi all,

Is there a debug build of coreboot or a way to test memory very early on.
My custom board goes through the romstage just fine but stops booting while 
trying to enumerate the buses.

I am suspecting RAM might be an issue so would like to eliminate that by doing 
a memory test on it.
--
POST: 0x72
Enumerating buses...
Show all devs... Before device enumeration.
Root Dev
--

Thanks in advance,
Naveed
"DISCLAIMER: This message is proprietary to Aricent and is intended solely for 
the use of the individual to whom it is addressed. It may contain privileged or 
confidential information and should not be circulated or used for any purpose 
other than for what it is intended. If you have received this message in error, 
please notify the originator immediately. If you are not the intended 
recipient, you are notified that you are strictly prohibited from using, 
copying, altering, or disclosing the contents of this message. Aricent accepts 
no responsibility for loss or damage arising from the use of the information 
transmitted by this email including damage from virus."
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Re: [coreboot] Debug builds and memory testing

[Naveed Ghori]

To update this: There are option in the menuconfig to enable various debugging 
options and logs.

From: Naveed Ghori
Sent: Tuesday, 24 May 2016 2:04 PM
To: coreboot
Subject: Debug builds and memory testing

Hi all,

Is there a debug build of coreboot or a way to test memory very early on.
My custom board goes through the romstage just fine but stops booting while 
trying to enumerate the buses.

I am suspecting RAM might be an issue so would like to eliminate that by doing 
a memory test on it.
--
POST: 0x72
Enumerating buses...
Show all devs... Before device enumeration.
Root Dev
--

Thanks in advance,
Naveed
-- 
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Re: [coreboot] Query regarding coreboot for new intel customized board

[Naveed Ghori]

That looks a lot like the Valley Island design.

I was able to get serial output by overwriting coreboot (last 2MB of the 8MB 
bios chip) on the bios that comes with it.
However as you will see in the history of emails still get stuck during the 
boot process.

Hope the above helps you get further.

From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Mayuri 
Tendulkar
Sent: Thursday, 26 May 2016 12:33 PM
To: Wim Vervoorn; coreboot
Subject: Re: [coreboot] Query regarding coreboot for new intel customized board

Thanks Vim.

Currently I am not able to get any serial prints out on my reference board.

My board is based on Intel ISX board based on Baytrail-I soc E3825 given below.

https://www-ssl.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e3800-dev-kit-isx-ref-design-product-brief.html

I have built coreboot for this, but unable to get serial prints.

How I should debug this further.

Regards
Mayuri

From: Wim Vervoorn [mailto:wvervo...@eltan.com]
Sent: 24 May 2016 13:26
To: Mayuri Tendulkar 
mailto:mayuri.tendul...@aricent.com>>
Subject: Re: Query regarding coreboot for new intel customized board

Hello Mayuri,

If your rom image is the same it could be due to the lack of support for the 
flash device you are using. The MRC cache is preserved in flash so you need to 
be able to write it.

For the others the numbers etc you mention are informational for the OS. They 
are not strictly required but the OS builds a registry of the items it 
retrieves from the SMBIOS. If you don't require this you could also disable the 
functionality.


Best Regards,
Wim Vervoorn

Eltan B.V.
Ambachtstraat 23
5481 SM Schijndel
The Netherlands

T : +31-(0)73-594 46 64
E : wvervo...@eltan.com
W : http://www.eltan.com
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From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Mayuri 
Tendulkar
Sent: Tuesday, May 24, 2016 7:26 AM
To: coreboot mailto:coreboot@coreboot.org>>
Subject: [coreboot] Query regarding coreboot for new intel customized board

Hi team

I am working on building coreboot for one of our customized board. This is 
based on Intel ISX board reference design, reference can be taken as 
Minnowboard or BayleyBay CRB.

As per documentation given under coreboot, I created folder with my board name 
under src/intel/mainboard/xxx and did changes required.

If I tried the coreboot with these changes on minnowboard, it got stuck at FSP 
MRC Cache not found.

But if the same code changes I copied under  src/intel/mainboard/minnowmax and 
built, it booted fine.

I would like to know what is the importance of these board names, SMBIOS table 
name, serial no which are defined for Minnowmax.

Is there some master registry where all these are stored, and if any new entry 
comes, how we should add it.

Regards
Mayuri


"DISCLAIMER: This message is proprietary to Aricent and is intended solely for 
the use of the individual to whom it is addressed. It may contain privileged or 
confidential information and should not be circulated or used for any purpose 
other than for what it is intended. If you have received this message in error, 
please notify the originator immediately. If you are not the intended 
recipient, you are notified that you are strictly prohibited from using, 
copying, altering, or disclosing the contents of this message. Aricent accepts 
no responsibility for loss or damage arising from the use of the information 
transmitted by this email including damage from virus."
"DISCLAIMER: This message is proprietary to Aricent and is intended solely for 
the use of the individual to whom it is addressed. It may contain privileged or 
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other than for what it is intended. If you have received this message in error, 
please notify the originator immediately. If you are not the intended 
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[coreboot] Debug builds and memory testing

[Naveed Ghori]

Hi all,

Is there a debug build of coreboot or a way to test memory very early on.
My custom board goes through the romstage just fine but stops booting while 
trying to enumerate the buses.

I am suspecting RAM might be an issue so would like to eliminate that by doing 
a memory test on it.
--
POST: 0x72
Enumerating buses...
Show all devs... Before device enumeration.
Root Dev
--

Thanks in advance,
Naveed

Naveed Ghori | Lead Firmware & Driver Engineer

DTI Group Ltd | Transit Security & Surveillance

31 Affleck Road, Perth Airport, Western Australia 6105, AU

P +61 8 9373 2905,151 | F +61 8 9479 1190 | naveed.gh...@dti.com.au



Visit our website www.dti.com.au<http://www.dti.com.au>

The information contained in this email is confidential. If you receive this 
email in error, please inform DTI Group Ltd via the above contact details. If 
you are not the intended recipient, you may not use or disclose the information 
contained in this email or attachments.
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[coreboot] New custom board (Intel Baytrail FSP based on Valley Island reference design)

[Naveed Ghori]

Hi,
I am bringing up a new board using coreboot as the bios.

Hardware:

-   Based on Intel Valley Island design (which has TPE)

-  No TPM

Coreboot:

-  Source coreboot 4.4 release

-  Using code based on Bayley bay (Intel FSP)

-  FSP: Gold3

-  Using a bios based on Valley Island for the non-coreboot sections

The board boots, goes through romstage and then freezes early in the ramstage 
(before enabling any devices): see output below
To me it seems there may be a hardware issue (new board, I am suspecting 
memory) but I thought I would ask as someone may have seen something similar.


1)  Could the non coreboot part of the bios chip cause this.

2)  Is there a way to check memory at the rom stage.

3)  Is there any information on the memory map of the bios chip.

4)  Is there a way to check other devices at the romstage or early ram 
stage.

I have tried skipping the "Enumeratin busses" section but it just crashes at 
the next stage (I guess I cannot really expect ti to get very far without its 
busses).

Note: I am new to coreboot and bios development in general.
Any help, suggestion appreciated.

Output Log:
--
coreboot-099d78c-dirty Thu May 12 05:41:22 UTC 2016 romstage starting...
RTC Init
POST: 0x44
POST: 0x47
POST: 0x48
Starting the Intel FSP (early_init)
PM1_STS = 0x100 PM1_CNT = 0x0 GEN_PMCON1 = 0x45008
prev_sleep_state = S5
Configure Default UPD Data
PcdMrcInitSPDAddr1: 0xa0 (default)
PcdMrcInitSPDAddr2: 0xa2 (default)
PcdSataMode:0x01 (set)
PcdLpssSioEnablePciMode:0x01 (default)
PcdMrcInitMmioSize: 0x800 (default)
PcdIgdDvmt50PreAlloc:   0x02 (default)
PcdApertureSize:0x02 (default)
PcdGttSize: 0x02 (default)
SerialDebugPortAddress: 0x3f8 (default)
SerialDebugPortType:0x01 (default)
PcdMrcDebugMsg: 0x00 (default)
PcdSccEnablePciMode:0x01 (default)
IgdRenderStandby:   0x00 (default)
TxeUmaEnable:   0x00 (default)
PcdOsSelection: 0x04 (default)
PcdEMMC45DDR50Enabled:  0x01 (default)
PcdEMMC45HS200Enabled:  0x00 (default)
PcdEMMC45RetuneTimerValue:  0x08 (default)
PcdEnableIgd:   0x00 (default)
AutoSelfRefreshEnable:  0x00 (default)
APTaskTimeoutCnt:   0x00 (default)
GTT Size:   2 MB
Tseg Size:  8 MB
Aperture Size:  256 MB
IGD Memory Size:64 MB
MMIO Size:  2048 MB
MIPI/ISP:   Disabled
Sdio:   Enabled
Sdcard: Enabled
SATA:   Enabled
SIO Dma 0:  Enabled
SIO I2C0:   Enabled
SIO I2C1:   Enabled
SIO I2C2:   Enabled
SIO I2C3:   Enabled
SIO I2C4:   Enabled
SIO I2C5:   Enabled
SIO I2C6:   Enabled
Azalia: Enabled
SIO Dma1:   Enabled
Pwm0:   Enabled
Pwm1:   Enabled
Hsuart0:Enabled
Hsuart1:Enabled
Spi:Enabled
Lpe:Disabled
eMMC Mode:  eMMC 4.5
SATA Mode:  AHCI
Xhci:   Enabled
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'mrc.cache'
CBFS: Found @ offset fec0 size 1
find_current_mrc_cache_local: No valid fast boot cache found.
FSP MRC cache not present.
POST: 0x92
POST: 0x4a
romstage_main_continue status: 0  hob_list_ptr: 7ae2
FSP Status: 0x0
PM1_STS = 0x101 PM1_CNT = 0x0 GEN_PMCON1 = 0x1001808
romstage_main_continue: prev_sleep_state = S0
Baytrail Chip Variant: Bay Trail-I (ISG/embedded)
MRC v0.100
2 channels of DDR3 @ 1333MHz
POST: 0x4b
POST: 0x4c
POST: 0x4d
CBMEM:
IMD: root @ 7adff000 254 entries.
IMD: root @ 7adfec00 62 entries.
POST: 0x4e
POST: 0x4f
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'fallback/ramstage'
CBFS: Found @ offset 46380 size d5be


coreboot-099d78c-dirty Thu May 12 05:41:22 UTC 2016 ramstage starting...
POST: 0x39
Moving GDT to 7adfe9c0...ok
POST: 0x80
POST: 0x70
BS: BS_PRE_DEVICE times (us): entry 0 run 1168 exit 0
POST: 0x71
CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 1ff00 size 26400
microcode: sig=0x30679 pf=0x1 revision=0x901
CPUID: 00030679
Cores: 4
Revision ID: 11
Stepping: D0
msr(17) = 90041743
msr(ce) = 06001700
BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 30606 exit 0
POST: 0x72
Enumerating buses...
Show all devs... Before device enumeration.
Root Dev


Naveed Ghori | Lead Firmware & Driver Engineer

DTI Group Ltd | Transit Security & Surveillance

31 Affleck Road, Perth Airport, Western Australia 6105, AU

P +61 8 93