[coreboot] amd/pademelon has push to https://github.com/BTDC/coreboot
Hi, all AMD has a low cost Carrizo board pademelon. We brought it up. The serial port works. But we don't test every feature. I push code to https://github.com/BTDC/coreboot , branch pademelon. src/mainboard/amd/ipc_fp4_lc is the mainboard code. I named it ipc_fp4_lc. I hope this is useful. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] We provide stable Bettong code in github
Hi, all coreboot is changing all the time and the patches are reabsed when pushed to community, so it is a little difficult to provide stable Bettong code. >From now on, AMD provides source code which is validated by QA team. The code is pushed to github https://github.com/BTDC/coreboot The version is identified by a tag. All the changes will be pushed to coreboot community. = Version: TCMEF1F0Release Date: 09/29/2015 Changes from last version: 1. Fix external graphics issue. 2. Add board ID support. 3. Support DDR4. 4. Support SD 2.0. 5. Fix Windows 7 S4 issue. 6. Add GPIO, I2C and UART support. 7. Fix the interrupt routine. 8. Restruct PCI interrupt table (C00/C01). 9. Fix DSDT issue. 10. Fix the PCIe lane map. 11. Lower the TOM to give more MMIO space. 12. Add USB device. 13. Set the USB3 port as unremoveable. 14. Update AGESA to CarrizoPI 1.1.0.1. Yours sincerely, WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] ACPI resource problem
Memory32Fixed(ReadWrite, 0xFEDC2000, 0x1000) reserves memory in asl. I
tried to add DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
but not work.
On Tue, Jul 7, 2015 at 7:22 PM WANG FEI wangfei.ji...@gmail.com wrote:
Siyuan, did you reserved 0xFEDC2000 - 0xFEDC2FFF in ASL file? what you've
done in your code is to reserve this MMIO area in E820 table, OS will not
take this area, but it's not enough for ACPI.
Here is a sample to reserve MMIO area in asl file.
// TPM Area (0xfed4-0xfed44fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x, 0xfed4, 0xfed44fff, 0x,
0x5000,,, TPMR)
On Mon, Jul 6, 2015 at 12:31 PM, WANG Siyuan wangsiyuanb...@gmail.com
wrote:
Hi,
I have a question about acpi resource.
My device need the resource:
Name(_CRS, ResourceTemplate() {
IRQ(Edge, ActiveHigh, Exclusive) {3}
Memory32Fixed(ReadWrite, 0xFEDC2000, 0x1000)
})
In Win8's device manager, I got error This device cannot find enough
free resources that it can use.
I reserve resource (0xFEDC2000 - 0xFEDC2FFF) using flag resource-flags =
IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED
| IORESOURCE_ASSIGNED; I still got this error.
I have 2 questions:
1) Do I need to reserve MMIO for (0xFEDC2000 - 0xFEDC2FFF)?
2) Do I need to do some thing for IRQ(Edge, ActiveHigh, Exclusive) {3}?
Any replay is appreciated!
Yours sincerely,
WANG Siyuan
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[coreboot] ACPI resource problem
Hi,
I have a question about acpi resource.
My device need the resource:
Name(_CRS, ResourceTemplate() {
IRQ(Edge, ActiveHigh, Exclusive) {3}
Memory32Fixed(ReadWrite, 0xFEDC2000, 0x1000)
})
In Win8's device manager, I got error This device cannot find enough free
resources that it can use.
I reserve resource (0xFEDC2000 - 0xFEDC2FFF) using flag resource-flags =
IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED
| IORESOURCE_ASSIGNED; I still got this error.
I have 2 questions:
1) Do I need to reserve MMIO for (0xFEDC2000 - 0xFEDC2FFF)?
2) Do I need to do some thing for IRQ(Edge, ActiveHigh, Exclusive) {3}?
Any replay is appreciated!
Yours sincerely,
WANG Siyuan
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[coreboot] push error (not Signed-off-by author/committer/uploader in commit message footer)
Hi, I push code as normal, but I got this error: $ git push Counting objects: 27, done. Delta compression using up to 4 threads. Compressing objects: 100% (15/15), done. Writing objects: 100% (15/15), 3.56 KiB, done. Total 15 (delta 13), reused 0 (delta 0) remote: Resolving deltas: 100% (13/13) remote: Processing changes: refs: 1, done To ssh://siy...@review.coreboot.org:29418/coreboot ! [remote rejected] HEAD - refs/for/master (not Signed-off-by author/committer/uploader in commit message footer) error: failed to push some refs to 'ssh://siy...@review.coreboot.org:29418/coreboot' My commit message is: commit 9df9e354dee0f07569adfd69976d27e30fd99710 Author: WANG Siyuan wangsiyuanb...@gmail.com Date: Fri Jun 5 13:22:44 2015 +0800 update submodule when 'make' rather than 'make menuconfig' 'git submodule update --init' runs before 'make menuconfig'. This is very inconvenience when developing. CONFIG_USE_BLOBS is used to control updating submodule, but the original command is wrong. With this patch, people can choose 'Allow use of binary-only repository' if they want to update submodule. Change-Id: I4b49f9b0d258ba22a006b6e669bf7fa016ecd76c Signed-off-by: WANG Siyuan siyuan.w...@amd.com Signed-off-by: WANG Siyuan wangsiyuanb...@gmail.com What is the problem? Thanks a lot. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] build error: fmd_scanner.l:47: error: declaration of ‘input’ shadows a global declaration
Hi, My host gcc is gcc version 4.6.1 (Debian 4.6.1-4). Remove -Wshadow can walk around this problem. diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index 1aa9d76..a55475b 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -42,7 +42,7 @@ rmodobj += elfheaders.o rmodobj += xdr.o TOOLCFLAGS ?= -std=c99 -Werror -Wall -Wextra -TOOLCFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow +TOOLCFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls TOOLCFLAGS += -Wstrict-prototypes -Wwrite-strings TOOLCPPFLAGS ?= -D_DEFAULT_SOURCE # memccpy() from string.h TOOLCPPFLAGS += -D_POSIX_C_SOURCE=200809L # strdup() from string.h On 5/13/2015 5:03 PM, WANG Siyuan wrote: Hi, When I build olivehillplus, I got this error: fmd_scanner.l: In function ‘parse_integer’: fmd_scanner.l:47: error: declaration of ‘input’ shadows a global declaration stdout:1192: error: shadowed declaration is here fmd_scanner.l: In function ‘copy_string’: fmd_scanner.l:74: error: declaration of ‘input’ shadows a global declaration stdout:1192: error: shadowed declaration is here make: *** [build/util/cbfstool/fmd_scanner.o] Error 1 Where is the problem? Thank you very much. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] build error: fmd_scanner.l:47: error: declaration of ‘input’ shadows a global declaration
Hi, When I build olivehillplus, I got this error: fmd_scanner.l: In function ‘parse_integer’: fmd_scanner.l:47: error: declaration of ‘input’ shadows a global declaration stdout:1192: error: shadowed declaration is here fmd_scanner.l: In function ‘copy_string’: fmd_scanner.l:74: error: declaration of ‘input’ shadows a global declaration stdout:1192: error: shadowed declaration is here make: *** [build/util/cbfstool/fmd_scanner.o] Error 1 Where is the problem? Thank you very much. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Booting Windows 8 failed
GnbGetScsDataCZ, 183:PspDir=ff86 Yours sincerely, WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] AMD Olivehill plus Wiki is finished
Hi, This is AMD Olivehill plus Wiki: http://www.coreboot.org/Board:amd/olivehillplus Yours sincerely, WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] How to edit coreboot wiki page
Peter and Stefan, Thank you very much! I can login now. Yours sincerely, WANG Siyuan On Wed, Sep 24, 2014 at 12:08 PM, Peter Stuge pe...@stuge.se wrote: WANG Siyuan wrote: It seems that I can't register a user name... Your username is meant to already be registered by Stefan. Check if there was mention of a username in Stefan's email yesterday. Kind regards //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] 回复: How to edit coreboot wiki page
Hi, Boatd_status. sh got wrong CPU and socket name of olivehill_plus. Maybe I have to change the page manually? 来自我的华为手机 Marc Jones marcj...@gmail.com编写： Hi Siyuan, Please also run the board_status.sh. It reports LOTs of important informationand you don't need to edit the wiki directly. http://www.coreboot.org/Supported_Motherboards#coreboot_status_by_mainboard http://review.coreboot.org/gitweb?p=coreboot.git;a=tree;f=util/board_status;hb=HEAD Regards, Marc On Mon, Sep 22, 2014 at 9:40 PM, WANG Siyuan wangsiyuanb...@gmail.com wrote: Hi, all I want to edit this page: http://www.coreboot.org/Board:amd/olivehillplus But I don’t have permission. It seems that I even can’t register a user name. So how can I get the permission to edit this page? Yours sincerely, WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- http://se-eng.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] How to edit coreboot wiki page
Hi, Stefan It seems that I can't register a user name... Yours sincerely, WANG Siyuan On Wed, Sep 24, 2014 at 4:23 AM, Stefan Tauner stefan.tau...@alumni.tuwien.ac.at wrote: On Tue, 23 Sep 2014 11:40:46 +0800 WANG Siyuan wangsiyuanb...@gmail.com wrote: Hi, all I want to edit this page: http://www.coreboot.org/Board:amd/olivehillplus But I don't have permission. It seems that I even can't register a user name. So how can I get the permission to edit this page? By sending a message to the mailing list asking how you get the permission to edit that page ;) You should have got your login data by email now. If you have any questions regarding the wiki please post them here (or on IRC), thanks. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] How to edit coreboot wiki page
Hi, all I want to edit this page: http://www.coreboot.org/Board:amd/olivehillplus But I don't have permission. It seems that I even can't register a user name. So how can I get the permission to edit this page? Yours sincerely, WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] S3 Resume on AMD Trinity APU
Hi, We have 2 boards with Trinity CPU, Thatcher and Parmer. S3 works on both of them. The default config is OK. VGA, DP and HDMI are good with S3 resume. Yours sincerely, WANG Siyuan On Thu, Apr 17, 2014 at 8:43 AM, mrnuke mr.nuke...@gmail.com wrote: For those of you with Trinity CPUs, coreboot, and working S3 resume, is it necessary to run the VGA option ROM on S3 resume to get video back? Which output are you using (VGA, DP, etc) ? Alex -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] IMB-A180E H coreboot won't boot
Hi,Mark Mason Have you resolved this issue? Maybe you can uncomment #define IDSOPT_TRACING_ENABLED TRUE in src/mainboard/asrock/imb-a180/OptionsIds.h. Then you can get more debug message in Agesa. Try to debug into AmdInitMid() in src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitMid.c to see where the problem is. Yours sincerely, WANG Siyuan On Sat, Feb 8, 2014 at 2:23 AM, Mark C. Mason m...@edt.com wrote: I'm new to coreboot, and I'm working to use it with an ASROCK IMB-A180, the H version with the LVDS port. I've read previous posts regarding the IMB-A180 won't boot on this group, and tried the .config that was posted, but the result is the same. The debugging output shows things progressing until agesawwrapper_amdinitmid is called, then the boot restarts, then stops cold at the same point: PCI: 00:18.4 PCI: 00:18.5 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 1095130 exit 0 POST: 0x74 Enabling resources... Fam16 - domain_enable_resources: AmdInitMid. agesawrapper_amdinitmid ^@^@^@^@佚沈h褕9589蝸捄4.0-5169-g9d1d740 Tue Feb 4 16:46:38 PST 2014 starting... Any help with this would be greatly appreciated. Full serial debug output then .config are attached below. Best regards, Mark Mason Engineering Design Team -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Fans and BIOS
Hi Vitor, Amd Parmer and Olivehill support FAN control. EC is used in these boards to control fan speed. Yours sincerely, WANG Siyuan On Sat, Apr 12, 2014 at 9:04 AM, Vitor Augusto vitora...@gmail.com wrote: Hello. I'm searching for any information about where (memory, IO port, etc.) the status (on or off) of the fans of a laptop are stored. Anything is very welcome! This is to improve the compatibility of i8kutils package at Linux. The site of the development is https://launchpad.net/i8kutils;. Thanks in advance. Vitor Augusto -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] PCI BAR resource problem
Hi, I have a question about assigning PCI BAR resource. In OliveHill, internal graphics(bus 0, dev 1, func 0)'s BAR0 (base address register) is 0xe00c. This is Graphic Memory Base Address. I want to change this value to 0xc00c. I have to do 2 things: 1) alloc resource at 0xc000 whose length is 512M 2) write the address value to internal graphics(bus 0, dev 1, func 0)'s BAR0 for 1), maybe I can alloc resource when reading resource. but I don't know how to deal with 2). It seems that, BAR's resources are assigned by device's ops-set_resources() function. But I can't find this function. My question is 1) when internal graphics(bus 0, dev 1, func 0)'s BAR0 is set to 0xe000? How can I change it? 2) How does coreboot alloc resources on 0xe000? I also can't find it. This is a general question: how does coreboot assign PCI device's BAR resource? Yours sincerely, WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] ASSERTION FAILED: file 'src/mainboard/amd/parmer/agesawrapper.c', line 431
Hi, Prop Would you provide the board version? On Thu, Nov 7, 2013 at 8:42 AM, Prop 395 prop...@gmail.com wrote: I am getting this AGESA error when booting Parmer with SeaBIOS. Contents of log: http://pastebin.com/xjANhWts Any help appreciated. -- Yours sincerely, WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] New Kabini Hardware
Hi, Andrew coreboot + seabios work well with AMD Catalyst graphics driver on OliveHill. If you think it was an acpi issue, maybe you can check src/mainboard/amd/olivehill/acpi/routing.asl On Tue, Oct 1, 2013 at 6:16 AM, Andrew DeAngelis and...@cogcomp.com wrote: Hello all, I am a computer engineer from Cogent Computer Systems. I'm bringing up Coreboot on our new CSB1890t10/CSB1801t10 system which is based largely on the AMD Olivehill platform. Is there anyone out there who has experience with Coreboot on Kabini and may be able to answer questions about unexpected resets when using the AMD Catalyst graphics driver? We're booting Ubuntu and Windows 7 right now with a barely modified mainboard code brought over from Olivehill, but I'm sure there must be some things we are doing wrong, esp. ACPI. Also, are there any candidates who may be interested in trading our potentially buggy hardware system for some expert help with the board port? Please let me know! Andrew DeAngelis Design Engineer Cogent Computer Systems 17 Industrial Drive Smithfield, RI 02917 tel: 401-349-3999 fax: 401-349-3998 E-mail: and...@cogcomp.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- Yours sincerely, WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] why /root_complex is deprecated
Hi, When I compile AMD Parmer, I got this warning: WARNING: Use of deprecated chip component northbridge/amd/agesa/family15tn/root_complex I found this warning is printed by util/sconfig/main.c line 172 Why 'northbridge/amd/agesa/family15tn/root_complex' is deprecated? -- Yours sincerely, WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] How to push 3rdparty?
Hi, I added two files in 3rdparty and commit the change. But how to push to gerrit? -- Yours sincerely, WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] S3 fails to suspend after wake up from USB keyboard
Hi, I am trying to debug an issue on Parmer. 1) use pm-suspend to suspend. 2) use USB keyboard to wake up. 3) use pm-suspend to suspend. FAIL To SUSPEND. After wake up by USB keyboard, I got some errors in dmesg: [ 55.585935] Disabling IRQ #9 I don't know why this is happened. It seems that ACPI method (_PTS, _WAK) have nothing to do with suspend and wake up. Does anybody can help me? 1) What is the workflow of USB keyboard wake up from S3? 2) What are differences between power button wake up and USB keyboard wake up? dmesg: [ 55.585874] irq 9: nobody cared (try booting with the irqpoll option) [ 55.585880] Pid: 691, comm: X Tainted: P O 3.6.11-1-ARCH #1 [ 55.585882] Call Trace: [ 55.585884] IRQ [810daffd] __report_bad_irq+0x3d/0xe0 [ 55.585895] [810db2f3] note_interrupt+0x1a3/0x1f0 [ 55.585899] [810e1bdf] ? rcu_process_callbacks+0xaf/0x5b0 [ 55.585903] [810d8bcf] handle_irq_event_percpu+0xbf/0x260 [ 55.585907] [8105e952] ? __do_softirq+0x122/0x240 [ 55.585910] [810d8db8] handle_irq_event+0x48/0x70 [ 55.585913] [810dbe0a] handle_fasteoi_irq+0x5a/0x100 [ 55.585917] [81017502] handle_irq+0x22/0x40 [ 55.585921] [8149c04a] do_IRQ+0x5a/0xe0 [ 55.585925] [8149356a] common_interrupt+0x6a/0x6a [ 55.585926] EOI [8149a4ed] ? system_call_fastpath+0x1a/0x1f [ 55.585931] handlers: [ 55.585933] [812b758f] acpi_irq [ 55.585935] Disabling IRQ #9 -- Yours sincerely, WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [SeaBIOS] [SimNow] PORT_IRQ_STAT register is 0 in ahci_port_setup
On 03/08/13 21:27, Kevin O'Connor wrote: On Fri, Mar 08, 2013 at 11:48:57AM +0800, WANG Siyuan wrote: According to this piece of code in src/ahci.c, seabios fails to set DMA or PIO on ahci. PORT_IRQ_STAT is 0. Thanks. Can you send a patch with the proposed fix? -Kevin I am sorry, but I don't know how to fix this issue until now.. Do you have any suggestion? Thanks. -- WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [SeaBIOS] [SimNow] PORT_IRQ_STAT register is 0 in ahci_port_setup
Hi, I am trying to boot a hard disk image using coreboot and seabios on SimNow Simulator. The system stops at seabios stage. PORT_CMD_START fails in function ahci_port_setup (seabios/src/ahci.c), Then I traced into function ahci_command (seabios/src/ahci.c), I found the value of register ORT_IRQ_STAT is always 0: intbits = ahci_port_readl(ctrl, pnr, PORT_IRQ_STAT); intbits returns 0 all the time, so system stops here until time out. Any comments would be appreciated. -- Yours sincerely, WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [SeaBIOS] [SimNow] PORT_IRQ_STAT register is 0 in ahci_port_setup
Thank you, 1) It is time out, the log is: AHCI/0: probing AHCI/0: link up AHCI/0: send cmd ... WARNING - Timeout at ahci_command:158! AHCI/0: send cmd ... WARNING - Timeout at ahci_command:158! in line 158(src/ahci.c) is warn_timeout(); 2) If ahci is disabled, the simulator can not find hard disk image. The hard disk image is added as a sata device. 3) The attachment is the log of seabios stage. Thank you again! On Fri, Mar 8, 2013 at 7:34 AM, Kevin O'Connor ke...@koconnor.net wrote: On Thu, Mar 07, 2013 at 04:59:43PM +0800, WANG Siyuan wrote: Hi, I am trying to boot a hard disk image using coreboot and seabios on SimNow Simulator. The system stops at seabios stage. PORT_CMD_START fails in function ahci_port_setup (seabios/src/ahci.c), Then I traced into function ahci_command (seabios/src/ahci.c), I found the value of register ORT_IRQ_STAT is always 0: intbits = ahci_port_readl(ctrl, pnr, PORT_IRQ_STAT); intbits returns 0 all the time, so system stops here until time out. Any comments would be appreciated. There is a 32 second timeout in that code (which may be a longer wall time if run under a simulator) - are you sure it didn't eventually time out. As to why it is taking so long - could be an error in the simulator or in the seabios driver. You could try disabling the ahci code in seabios via kconfig. -Kevin -- Yours sincerely, WANG Siyuan seabios.log Description: Binary data -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [SeaBIOS] [SimNow] PORT_IRQ_STAT register is 0 in ahci_port_setup
According to this piece of code in src/ahci.c, seabios fails to set
DMA or PIO on ahci. PORT_IRQ_STAT is 0.
end = calc_future_tsc(AHCI_REQUEST_TIMEOUT);
do {
for (;;) {
intbits = ahci_port_readl(ctrl, pnr, PORT_IRQ_STAT);
//dprintf(1, intbits == 0x%x\n, intbits);
if (intbits) {
ahci_port_writel(ctrl, pnr, PORT_IRQ_STAT, intbits);
if (intbits 0x02) {
status = GET_LOWFLAT(fis-psfis[2]);
error = GET_LOWFLAT(fis-psfis[3]);
break;
}
if (intbits 0x01) {
status = GET_LOWFLAT(fis-rfis[2]);
error = GET_LOWFLAT(fis-rfis[3]);
break;
}
}
if (check_tsc(end)) {
warn_timeout();
return -1;
}
yield();
}
dprintf(8, AHCI/%d: ... intbits 0x%x, status 0x%x ...\n,
pnr, intbits, status);
} while (status ATA_CB_STAT_BSY);
On Fri, Mar 8, 2013 at 7:34 AM, Kevin O'Connor ke...@koconnor.net wrote:
On Thu, Mar 07, 2013 at 04:59:43PM +0800, WANG Siyuan wrote:
Hi,
I am trying to boot a hard disk image using coreboot and seabios on
SimNow Simulator.
The system stops at seabios stage.
PORT_CMD_START fails in function ahci_port_setup (seabios/src/ahci.c),
Then I traced into function ahci_command (seabios/src/ahci.c), I found
the value of register ORT_IRQ_STAT is always 0:
intbits = ahci_port_readl(ctrl, pnr, PORT_IRQ_STAT);
intbits returns 0 all the time, so system stops here until time out.
Any comments would be appreciated.
There is a 32 second timeout in that code (which may be a longer wall
time if run under a simulator) - are you sure it didn't eventually
time out. As to why it is taking so long - could be an error in the
simulator or in the seabios driver. You could try disabling the ahci
code in seabios via kconfig.
-Kevin
--
Yours sincerely,
WANG Siyuan
--
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[coreboot] cross gcc 4.7.2 bit filed issue
Hi,
I found an issue of cross gcc built by util/crossgcc/buildgcc
take this piece of code as an example
struct st{
unsigned int a:12;
};
then I declare a variable:
struct st m;
This is my test result:
1) If I compile it by host gcc, sizeof(m) is 4.
2) If I put these codes in a coreboot mainboard, build it by cross
gcc. use printk to print the length.
sizeof(m) is 2.
3) If I use cross gcc, compile the code use -c flag (put these code
in size.c, not put it in a mainboard's source)
use nm --format sysv size.o to check, the length is 4
Name Value ClassType Size Line Section
m |0004| C |OBJECT|0004| |*COM*
My question is:
Although 12 bits only take 2 Bytes, in the struct I declare it as
unsigned int. So sizeof(m) should be 4. Why it is 2 when building it
in coreboot?
About test 3:
coreboot's cross gcc doesn't have C Library, so I declare a global
variable and use nm to check the size.
--
Yours sincerely,
WANG Siyuan
--
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[coreboot] Coreboot Seabios's Makefile.inc build issue.
Hi, I build coreboot and seabios separately , and then add a payload in coreboot , no err occurs. By the way, I think seabios should have a method to use cross compile tool chain like coreboot. I have to modify makefile now. On Wednesday, January 30, 2013, Denis 'GNUtoo' Carikli wrote: Hi, When building SeaBIOS from 1.7.1 coreboot builds correctly. But when I try master it fails this way: make[2]: *** No rule to make target `out/misc.o', needed by `/home/gnutoo/x86/coreboot/build/seabios/out/ccode32flat.o'. Stop. I've tried a lot of combinaisons in the Makefile.inc that is in payloads/external/SeaBIOS but I didn't succeed at fixing it. I also lack the time to fix it right now, and that issue has been there for a long time... However running the following command in coreboot's topdir make it succeed: make -C build/seabios Then a normal make finishes to compiles coreboot. Denis. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- Yours sincerely, WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot Seabios's Makefile.inc build issue.
Hi, I build coreboot and seabios separately , and then add a payload in coreboot , no err occurs. By the way, I think seabios should have a method to use cross compile tool chain like coreboot. I have to modify makefile. On Wednesday, January 30, 2013, Denis 'GNUtoo' Carikli wrote: Hi, When building SeaBIOS from 1.7.1 coreboot builds correctly. But when I try master it fails this way: make[2]: *** No rule to make target `out/misc.o', needed by `/home/gnutoo/x86/coreboot/build/seabios/out/ccode32flat.o'. Stop. I've tried a lot of combinaisons in the Makefile.inc that is in payloads/external/SeaBIOS but I didn't succeed at fixing it. I also lack the time to fix it right now, and that issue has been there for a long time... However running the following command in coreboot's topdir make it succeed: make -C build/seabios Then a normal make finishes to compiles coreboot. Denis. -- coreboot mailing list: coreboot@coreboot.org javascript:; http://www.coreboot.org/mailman/listinfo/coreboot -- Yours sincerely, WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Gerrit problem: Not able to sign in
Me too. On Thu, Jan 31, 2013 at 4:52 PM, Paul Menzel paulepan...@users.sourceforge.net wrote: Dear coreboot admins, currently I am not able to sign into Gerrit using my Google Mail account. Not found The page you requested was not found, or you do not have permission to view this page. Do you have similar problems? Thanks, Paul -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- Yours sincerely, WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] anyone built emulation/qemu for x86 lately?
Hi, Ron I have ever built coreboot for qemu. Please note: 1) build seabios and coreboot separately rather than build seabios in coreboot. Chose ' Build Target (Build for coreboot) ' in seabios. 2) after build seabios successfuly, copy out/bios.bin.elf to coreboot dirctory and add it as a payload of coreboot. 3) build coreboot and seabios with 32-bit compile toolchain. 4) start qemu with qemu -bios /path/to/coreboot.rom On Thu, Jan 24, 2013 at 8:13 PM, ron minnich rminn...@gmail.com wrote: here I thought it was built as part of checkin. If I do a clean pull, and try to build the qemu target, I hit a lot of bad issues with ACPI RESUME being misconfigured. Anyone else seeing this? ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- Yours sincerely, WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] RAM speed problem on Supermicro H8QGI (Family 15h)
Hi, Константин Did you try to change BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT and BLDCFG_MEMORY_CLOCK_SELECT in src/mainboard/supermicro/h8qgi/buildOpts.c ? BLDCFG_USE_HT_ASSIST can't be set as TRUE on h8qgi now. I am sorry but I don't know how to debug this issue. On Thu, Jan 24, 2013 at 3:42 PM, Константин Аладышев aladys...@nicevt.ru wrote: I have server Supermicro H8QGI board with 4 AMD Opteron f15 processors and 128 GB RAM (16x8Gb, 4 dimms per socket, 1 dimm per channel). I've tested my board in STREAM and noticed that coreboot gives RAM speed 5 times slower than original BIOS (16 MB/s against 80 MB/s). What can lead to this problem? Is it family 15h or motherboard issue? Does another families have such problem? I've dumped registers from coreboot and original BIOS. After that i enabled/disabled some functions in buildOps.c to make dumps look more similar. Now dumps allmost identical (but RAM speed problem still exist). Also i should mention that original BIOS have HT-ASSIST feature enabled, but i can't enable it in coreboot (http://www.coreboot.org/pipermail/coreboot/2012-December/073001.html) But according to this link http://www.amd.com/us/products/server/processors/six-core-opteron/Pages/six-core-faq-ht-assist.aspx HT-ASSIST can increase performance by up to 60% (not 500%!). So i think it isn't the main problem. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- Yours sincerely, WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Can WinDbg debug Windows graphic driver?
Hi, everyone My coreboot can boot Windows 7 with VGA driver but cannot boot Windows 7 with AMD driver. The monitor is black but system is still alive. I can connect it by Remote Desktop. There is no dump files generated. I try to use WinDbg to debug. Now, I know how to debug a process and setup a server-client environment, But how to debug Graphic Driver without source code? Thank you! -- Yours sincerely, WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot can boot Linux but cannot boot Windows7
Hi, Ron Win7 boot at the windows logo, and then system reset. But Linux works well. On Tue, Jan 22, 2013 at 12:54 PM, ron minnich rminn...@gmail.com wrote: On Mon, Jan 21, 2013 at 6:14 PM, WANG Siyuan wangsiyuanb...@gmail.com wrote: Hi, I am debugging a board. coreboot could boot Linux and load graphic driver, but it could not boot Windows 7. Has anyone encountered similar problem? sure, and we had to fix it, but there is not enough information in your note to tell us what might be wrong. ron -- Yours sincerely, WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot can boot Linux but cannot boot Windows7
Hi, Patrick My windows 7 stopped at windows logo, It cannot enter win7 desktop. Can this situation debug by windbg? On Tue, Jan 22, 2013 at 3:42 PM, Patrick Georgi patr...@georgi-clan.de wrote: Am 2013-01-22 03:14, schrieb WANG Siyuan: I am debugging a board. coreboot could boot Linux and load graphic driver, but it could not boot Windows 7. Has anyone encountered similar problem? Linux is much more tolerant about many things, in particular about ACPI and a couple more tables. I collected a bunch of issues at http://www.coreboot.org/ACPI#Windows_Errors - if you find issues that aren't listed there, you can look for an explanation (of STOP codes and similar behaviour) on msdn.com. If that still doesn't help you, you will have to debug your windows install (with windbg) and figure out what the problem is. If you can get hold of checked Windows builds, I recommend these - they're much more helpful (especially when it comes to ACPI). Unfortunately their install CD is unchecked, so if you fail to find informations on the installer, you'll have to install on another machine and swap disks (or use legacy BIOS), and probe the installed windows. In any case, please document your results on the wiki page I mentioned. Patrick -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- Yours sincerely, WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] coreboot can boot Linux but cannot boot Windows7
Hi, I am debugging a board. coreboot could boot Linux and load graphic driver, but it could not boot Windows 7. Has anyone encountered similar problem? Thank you! -- Yours sincerely, WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] could OVMF be a payload of coreboot?
Hi, OVMF is a project of tianocore: http://sourceforge.net/apps/mediawiki/tianocore/index.php?title=OVMF OVMF could be UEFI bios of qemu (-bios OVMF.fd), it could boot a UEFI image and enter UEFI shell. I have build and test. it works well in qemu. So I think it could be a payload of coreboot. coreboot init hardware and pass control to OVMF. Does anyone do that? Is it possible? -- Yours sincerely, WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] how to use TianoCore as a coreboot payload
On Wed, Dec 5, 2012 at 6:12 AM, David Hendricks dhend...@google.com wrote: Hello Siyuan, You might find this webpage useful: http://www.phisch.org/website/efiboot/ No code are provided. Have you built Coreboot for your target mainboard or emulator? Coreboot can load any ELF payload (Payload - Add a payload - An ELF executable payload and provide the path to your payload). which ELF payload you used? It is open source software or commercial software? Thank you! -- Yours sincerely, WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] how to use TianoCore as a coreboot payload
In this page http://www.coreboot.org/TianoCore , It is said that TianoCore could be a payload of coreboot to implement opensource UEFI environment. Now, I have built UDK(UEFI development Kit) successfully. Then what to do next? how to use these as payload of coreboot? -- Yours sincerely, WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Fwd: do_IRQ: 1.55 No irq handler for vector (irq -1)
:02:00.1: irq 90 for MSI/MSI-X [5.330751] igb :02:00.1: Intel(R) Gigabit Ethernet Network Connection [5.330754] igb :02:00.1: eth2: (PCIe:2.5Gb/s:Width x4) 00:e0:81:c9:94:11 [5.330832] igb :02:00.1: eth2: PBA No: FF-0FF [5.330834] igb :02:00.1: Using MSI-X interrupts. 8 rx queue(s), 8 tx queue(s) [5.525692] EXT4-fs (sda2): re-mounted. Opts: (null) [5.598476] Adding 2097148k swap on /dev/sda1. Priority:-1 extents:1 across:2097148k [8.306906] e1000e :01:00.0: irq 72 for MSI/MSI-X [8.360103] e1000e :01:00.0: irq 72 for MSI/MSI-X [8.361252] ADDRCONF(NETDEV_UP): eth0: link is not ready [8.519362] ADDRCONF(NETDEV_UP): eth1: link is not ready [8.635696] ADDRCONF(NETDEV_UP): eth2: link is not ready -- WANG Siyuan -- WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] qemu boot error: Unexpected Exception: 6 @ 10:00109910 - Halting
hi, I want to boot qemu with coreboot. the disk image use grub to load linux. but I got errors in write_coreboot_table() how to deal with it? the following msg is the wrong log. the attachment is the whole log. thank you! SMBIOS tables: 370 bytes. Adding CBMEM entry as no. 4 Writing high table forward entry at 0x0500 Wrote coreboot table at: 0500, 0x10 bytes, checksum 63e0 New low_table_end: 0x0528 Now going to write high coreboot table at 0x7ffe1c00 rom_table_end = 0x7ffe1c00 Adjust low_table_end from 0x0528 to 0x1000 Adjust rom_table_end from 0x7ffe1c00 to 0x7fff Unexpected Exception: 6 @ 10:00109910 - Halting Code: 0 eflags: 00010006 eax: 7ffe1c18 ebx: 0001 ecx: 0014 edx: edi: 7ffe1c00 esi: 0011ff10 ebp: 0005 esp: 0011feb4 001098d0: ec 7c 89 44 24 14 8b 40 001098d8: 04 8d 74 24 5c c7 44 24 001098e0: 18 00 00 00 00 89 74 24 001098e8: 3c 89 44 24 10 83 e8 08 001098f0: f7 f1 89 44 24 34 89 44 001098f8: 24 38 8b 44 24 14 89 44 00109900: 24 30 e9 a5 00 00 00 6b 00109908: 44 24 18 14 03 44 24 14 00109910: 66 0f 6e 40 0c 66 0f d6 00109918: 44 24 20 8b 54 24 20 8d 00109920: 58 08 8b 40 08 89 5c 24 00109928: 28 8b 5c 24 18 89 d1 31 00109930: d2 89 4c 24 24 8b 4c 24 00109938: 30 89 54 24 20 31 d2 01 00109940: 44 24 20 11 54 24 24 83 00109948: c1 08 89 4c 24 2c 6b cb -- WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] how to assign irq to a device
hi, i am debugging a mainboard with an external pci network adapter. the adapter share irq with usb. it seems not correct, so i want to assign an irq for this adapter. how to do that? thank you. /proc/interrupt eth1 is an external pci network adapter. i want to assign irq 21 for it. CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7 0: 59 0 0 0 0 0 0 0 IO-APIC-edge timer 1: 0 0 1 0 1 1 0 0 IO-APIC-edge i8042 7: 1 0 0 0 0 0 0 0 IO-APIC-edge 8: 0 0 0 0 0 0 0 0 IO-APIC-edge rtc0 9: 0 0 0 0 0 0 0 0 IO-APIC-fasteoi acpi 12: 0 0 0 1 1 0 1 1 IO-APIC-edge i8042 14: 0 0 0 0 0 0 0 0 IO-APIC-edge pata_atiixp 15: 0 0 0 0 0 0 0 0 IO-APIC-edge pata_atiixp 16: 93 95 80 91 96 94 98 97 IO-APIC-fasteoi ohci_hcd:usb3, ohci_hcd:usb4 17: 1 0 1 0 0 0 0 0 IO-APIC-fasteoi ehci_hcd:usb1 18: 4 4 4 4 4 4 2 4 IO-APIC-fasteoi ohci_hcd:usb5, ohci_hcd:usb6, ohci_hcd:usb7 19: 1 1 0 0 0 0 0 0 IO-APIC-fasteoi ehci_hcd:usb2, eth1 22:672685691692693683 687681 IO-APIC-fasteoi ahci 296:119 99127 87125 96 121105 PCI-MSI-edge eth0-rx-0 297: 0 0 0 0 0 0 0 0 PCI-MSI-edge eth0-tx-0 298: 1 0 0 0 0 0 0 0 PCI-MSI-edge eth0 299:123125105138 93135 106132 PCI-MSI-edge eth2-rx-0 300: 2 4 4 0 1 2 1 3 PCI-MSI-edge eth2-tx-0 301: 0 0 1 0 0 0 0 2 PCI-MSI-edge eth2 NMI: 0 0 0 0 0 0 0 0 Non-maskable interrupts LOC: 4050 1673 3943 2348 2519 2963 3093 1644 Local timer interrupts SPU: 0 0 0 0 0 0 0 0 Spurious interrupts PMI: 0 0 0 0 0 0 0 0 Performance monitoring interrupts IWI: 0 0 0 0 0 0 0 0 IRQ work interrupts RTR: 0 0 0 0 0 0 0 0 APIC ICR read retries RES: 5454 4177 5477 3690 5121 3822 5342 3630 Rescheduling interrupts CAL: 44 58 52 57 46 56 50 59 Function call interrupts TLB:291391291336274344 237395 TLB shootdowns TRM: 0 0 0 0 0 0 0 0 Thermal event interrupts THR: 0 0 0 0 0 0 0 0 Threshold APIC interrupts MCE: 0 0 0 0 0 0 0 0 Machine check exceptions MCP: 6 6 6 6 6 6 6 6 Machine check polls ERR: 1 MIS: 0 -- WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] how to assign irq to a device
hi, ali thank you. this is an Ethernet controller plugged in PCI slot. maybe it is also called LAN card. this card is not plugged in USB slot, it is plugged in PCI slot. so I think the irq is not right. On Wed, Oct 10, 2012 at 7:34 PM, ali hagigat hagigat...@gmail.com wrote: External PCI network adaptor? If it is plugged in PCI slot so it is internal. Is it a LAN card plugged into USB slot? On Wed, Oct 10, 2012 at 2:41 PM, WANG Siyuan wangsiyuanb...@gmail.com wrote: hi, i am debugging a mainboard with an external pci network adapter. the adapter share irq with usb. it seems not correct, so i want to assign an irq for this adapter. how to do that? thank you. /proc/interrupt eth1 is an external pci network adapter. i want to assign irq 21 for it. CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7 0: 59 0 0 0 0 0 0 0 IO-APIC-edge timer 1: 0 0 1 0 1 1 0 0 IO-APIC-edge i8042 7: 1 0 0 0 0 0 0 0 IO-APIC-edge 8: 0 0 0 0 0 0 0 0 IO-APIC-edge rtc0 9: 0 0 0 0 0 0 0 0 IO-APIC-fasteoi acpi 12: 0 0 0 1 1 0 1 1 IO-APIC-edge i8042 14: 0 0 0 0 0 0 0 0 IO-APIC-edge pata_atiixp 15: 0 0 0 0 0 0 0 0 IO-APIC-edge pata_atiixp 16: 93 95 80 91 96 94 98 97 IO-APIC-fasteoi ohci_hcd:usb3, ohci_hcd:usb4 17: 1 0 1 0 0 0 0 0 IO-APIC-fasteoi ehci_hcd:usb1 18: 4 4 4 4 4 4 2 4 IO-APIC-fasteoi ohci_hcd:usb5, ohci_hcd:usb6, ohci_hcd:usb7 19: 1 1 0 0 0 0 0 0 IO-APIC-fasteoi ehci_hcd:usb2, eth1 22:672685691692693683 687681 IO-APIC-fasteoi ahci 296:119 99127 87125 96 121105 PCI-MSI-edge eth0-rx-0 297: 0 0 0 0 0 0 0 0 PCI-MSI-edge eth0-tx-0 298: 1 0 0 0 0 0 0 0 PCI-MSI-edge eth0 299:123125105138 93135 106132 PCI-MSI-edge eth2-rx-0 300: 2 4 4 0 1 2 1 3 PCI-MSI-edge eth2-tx-0 301: 0 0 1 0 0 0 0 2 PCI-MSI-edge eth2 NMI: 0 0 0 0 0 0 0 0 Non-maskable interrupts LOC: 4050 1673 3943 2348 2519 2963 3093 1644 Local timer interrupts SPU: 0 0 0 0 0 0 0 0 Spurious interrupts PMI: 0 0 0 0 0 0 0 0 Performance monitoring interrupts IWI: 0 0 0 0 0 0 0 0 IRQ work interrupts RTR: 0 0 0 0 0 0 0 0 APIC ICR read retries RES: 5454 4177 5477 3690 5121 3822 5342 3630 Rescheduling interrupts CAL: 44 58 52 57 46 56 50 59 Function call interrupts TLB:291391291336274344 237395 TLB shootdowns TRM: 0 0 0 0 0 0 0 0 Thermal event interrupts THR: 0 0 0 0 0 0 0 0 Threshold APIC interrupts MCE: 0 0 0 0 0 0 0 0 Machine check exceptions MCP: 6 6 6 6 6 6 6 6 Machine check polls ERR: 1 MIS: 0 -- WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- WANG Siyuan
[coreboot] git commit problem
Hi, there is problem when I use git commit to commit changes. the message says: test failed: 'build/.../static.c build/.../static.c build/.../static.ramstage.o build/.../static.romstage.o' should be 'build/.../static.c build/.../static.c build/.../static.ramstage.o build/.../static.romstage.o' then I discard all my changes, but the problem is still there. would somebody can help me? thank you! -- WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
