[coreboot] BayleyBay FSP booting

[Tuan Vu]

I'm trying to investigate Coreboot and FSP booting performance on the Intel's 
Bayley Bay board and having trouble getting it to boot SeaBIOS.  I had to 
modify some files to get it to the point of attempting to load the payload but 
it gets stuck here:

Could not find a bounce buffer...
Could not load payload

Additional printfk reveals that none of the memory ranges described in bootmem 
has the tag LB_MEM_RAM; they all have the LB_MEM_RESERVED, LB_MEM_TABLE and 
LB_MEM_UNUSABLE.  Any ideas what went wrong here? Typically, what creates the 
memory ranges?

Thanks,

Tuan Vu

Software Engineer
Insyde Software, Inc.

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Re: [coreboot] BayleyBay FSP booting

[Aaron Durbin]

On Tue, Jul 1, 2014 at 10:55 AM, Tuan Vu  wrote:
> I’m trying to investigate Coreboot and FSP booting performance on the
> Intel’s Bayley Bay board and having trouble getting it to boot SeaBIOS.  I
> had to modify some files to get it to the point of attempting to load the
> payload but it gets stuck here:
>
>
>
> Could not find a bounce buffer...
>
> Could not load payload
>
>
>
> Additional printfk reveals that none of the memory ranges described in
> bootmem has the tag LB_MEM_RAM; they all have the LB_MEM_RESERVED,
> LB_MEM_TABLE and LB_MEM_UNUSABLE.  Any ideas what went wrong here?
> Typically, what creates the memory ranges?
>

Could you provide all the logs?

In src/soc/intel/fsp_baytrail/northcluster.c there is a function
nc_read_resources() which should add the appropriate resources. See if
that is being called. If not, maybe another PCI device id needs to be
added to that file to match on the appropriate driver.
>
>
> Thanks,
>
>
>
> Tuan Vu
>
>
>
> Software Engineer
>
> Insyde Software, Inc.
>
>
>
>
> --
> coreboot mailing list: coreboot@coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] BayleyBay FSP booting

[ron minnich]

we had this recently in another context. A log would be useful. It will try
to find a bounce buffer if your payload will end up replacing parts of
coreboot. What is your base/size for coreboot and for the payload?

ron
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Re: [coreboot] BayleyBay FSP booting

[Tuan Vu]

Hi guys, thanks for responding.  I actually got it to boot DOS now, it was a 
mismatch device id for the northbridge.  Once I change it to match the device, 
it got through fine.  The GFX device id was also wrong so once I change that, 
video started working too.

Curiously, Intel's document states that the northbridge device id is 0x0F00 and 
the GFX is 0x0F31, but on my board it's 0x and 0x0031.  Wonder if it's a 
microcode mistake, any ideas?  I have 2 boards to test with and apparently they 
both have this issue.

Thanks,

Tuan

From: adur...@google.com [adur...@google.com] on behalf of Aaron Durbin 
[adur...@chromium.org]
Sent: Thursday, July 10, 2014 4:15 PM
To: Tuan Vu
Cc: coreboot@coreboot.org
Subject: Re: [coreboot] BayleyBay FSP booting

On Tue, Jul 1, 2014 at 10:55 AM, Tuan Vu  wrote:
> I’m trying to investigate Coreboot and FSP booting performance on the
> Intel’s Bayley Bay board and having trouble getting it to boot SeaBIOS.  I
> had to modify some files to get it to the point of attempting to load the
> payload but it gets stuck here:
>
>
>
> Could not find a bounce buffer...
>
> Could not load payload
>
>
>
> Additional printfk reveals that none of the memory ranges described in
> bootmem has the tag LB_MEM_RAM; they all have the LB_MEM_RESERVED,
> LB_MEM_TABLE and LB_MEM_UNUSABLE.  Any ideas what went wrong here?
> Typically, what creates the memory ranges?
>

Could you provide all the logs?

In src/soc/intel/fsp_baytrail/northcluster.c there is a function
nc_read_resources() which should add the appropriate resources. See if
that is being called. If not, maybe another PCI device id needs to be
added to that file to match on the appropriate driver.
>
>
> Thanks,
>
>
>
> Tuan Vu
>
>
>
> Software Engineer
>
> Insyde Software, Inc.
>
>
>
>
> --
> coreboot mailing list: coreboot@coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] BayleyBay FSP booting

[Sean McNeil]

This is because you do not have a correct Intel Firmware Descriptor 
(IFD). You may run into additional problems at a later time and you most 
assuredly do not have any protection against changing flash content by 
the CPU.


On 07/11/2014 08:25 AM, Tuan Vu wrote:

Hi guys, thanks for responding.  I actually got it to boot DOS now, it was a 
mismatch device id for the northbridge.  Once I change it to match the device, 
it got through fine.  The GFX device id was also wrong so once I change that, 
video started working too.

Curiously, Intel's document states that the northbridge device id is 0x0F00 and 
the GFX is 0x0F31, but on my board it's 0x and 0x0031.  Wonder if it's a 
microcode mistake, any ideas?  I have 2 boards to test with and apparently they 
both have this issue.

Thanks,

Tuan

From: adur...@google.com [adur...@google.com] on behalf of Aaron Durbin 
[adur...@chromium.org]
Sent: Thursday, July 10, 2014 4:15 PM
To: Tuan Vu
Cc: coreboot@coreboot.org
Subject: Re: [coreboot] BayleyBay FSP booting

On Tue, Jul 1, 2014 at 10:55 AM, Tuan Vu  wrote:

I’m trying to investigate Coreboot and FSP booting performance on the
Intel’s Bayley Bay board and having trouble getting it to boot SeaBIOS.  I
had to modify some files to get it to the point of attempting to load the
payload but it gets stuck here:



Could not find a bounce buffer...

Could not load payload



Additional printfk reveals that none of the memory ranges described in
bootmem has the tag LB_MEM_RAM; they all have the LB_MEM_RESERVED,
LB_MEM_TABLE and LB_MEM_UNUSABLE.  Any ideas what went wrong here?
Typically, what creates the memory ranges?


Could you provide all the logs?

In src/soc/intel/fsp_baytrail/northcluster.c there is a function
nc_read_resources() which should add the appropriate resources. See if
that is being called. If not, maybe another PCI device id needs to be
added to that file to match on the appropriate driver.


Thanks,



Tuan Vu



Software Engineer

Insyde Software, Inc.




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Re: [coreboot] BayleyBay FSP booting

[Patrick Georgi]

Am 01.07.2014 17:55, schrieb Tuan Vu:
> Typically, what creates the memory ranges?
To a large degree the memory init code, which is closed source in the
FSP model and thus unavailable to us.

When it comes to memory issues with FSP, it might be better to ask Intel
directly.


Regards,
Patrick



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Re: [coreboot] BayleyBay FSP booting

[WANG FEI]

Tuan,

Your platform's northbirdge and GFX device ID is 0x0 and 0x0031? It's
definitely wrong, I would suggest you to download the Bayley Bay platform's
official UEFI BIOS from Intel IBL and flash it to you Bayley Bay platform,
then see what's the correct ID.


On Fri, Jul 11, 2014 at 4:36 AM, Patrick Georgi 
wrote:

> Am 01.07.2014 17:55, schrieb Tuan Vu:
> > Typically, what creates the memory ranges?
> To a large degree the memory init code, which is closed source in the
> FSP model and thus unavailable to us.
>
> When it comes to memory issues with FSP, it might be better to ask Intel
> directly.
>
>
> Regards,
> Patrick
>
>
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> coreboot mailing list: coreboot@coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
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Re: [coreboot] BayleyBay FSP booting

[Martin Roth]

Tuan, Sorry - I've been on vacation and missed this thread until now.

What Wang Fei suggested is exactly right - you need to start with a 
different BIOS flashed on the board..  The problem is the Descriptor/TXE 
that is being used.  Intel has said that they would update the build 
instructions included with the FSP to highlight this issue, but I don't 
know if this has been done.


I'm thinking I'll put in a check for this condition and print out a 
message stating what needs to be done.  I'll try to get that added shortly.


Martin

On 07/17/2014 03:55 PM, WANG FEI wrote:

Tuan,

Your platform's northbirdge and GFX device ID is 0x0 and 0x0031? It's 
definitely wrong, I would suggest you to download the Bayley Bay 
platform's official UEFI BIOS from Intel IBL and flash it to you 
Bayley Bay platform, then see what's the correct ID.



On Fri, Jul 11, 2014 at 4:36 AM, Patrick Georgi 
mailto:patr...@georgi-clan.de>> wrote:


Am 01.07.2014 17:55, schrieb Tuan Vu:
> Typically, what creates the memory ranges?
To a large degree the memory init code, which is closed source in the
FSP model and thus unavailable to us.

When it comes to memory issues with FSP, it might be better to ask
Intel
directly.


Regards,
Patrick


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