[coreboot] Patch set updated: 9d4027a Implemented functions for writing most of the ACPI tables
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/76
-gerrit
commit 9d4027a77dda60a64dd0f8af792f4f1c72f0187f
Author: Cristian Măgherușan-Stanciu
Date: Sat Jul 2 01:07:35 2011 +0300
Implemented functions for writing most of the ACPI tables
Fixed compilation failures in the SILC code, but Intel xe7501devkit
still fails to compile due to incomplete southbrige code that does not
implement FADT generation as of yet.
Change-Id: Ib84c845d3f004708a90fd3122485f00b7d20fdbc
Signed-off-by: Cristian Măgherușan-Stanciu
Signed-off-by: Sven Schnelle
---
src/arch/x86/boot/acpi.c | 267 --
src/arch/x86/boot/tables.c |6 +-
src/arch/x86/include/arch/acpi.h | 28 -
3 files changed, 283 insertions(+), 18 deletions(-)
diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c
index 8be7437..d991ce1 100644
--- a/src/arch/x86/boot/acpi.c
+++ b/src/arch/x86/boot/acpi.c
@@ -16,13 +16,15 @@
*/
/*
- * Each system port implementing ACPI has to provide two functions:
- *
- * write_acpi_tables()
- * acpi_dump_apics()
- *
- * See Kontron 986LCD-M port for a good example of an ACPI implementation
- * in coreboot.
+ * Currently each system port implementing ACPI has to provide the following
functions:
+ * - acpi_fill_mcfg()
+ * - acpi_fill_madt()
+ * - acpi_fill_slit()
+ * - acpi_fill_srat()
+ * Optional
+ * - acpi_fill_ssdt_generator()
+ * - acpi_patch_dsdt()
+ * - acpi_dmi_workaround()
*/
#include
@@ -249,6 +251,18 @@ unsigned long __attribute__((weak))
acpi_fill_ssdt_generator(
return current;
}
+/* stub functions that might be implemented in the mainboard code, if needed */
+void __attribute__((weak)) acpi_patch_dsdt(
+ acpi_header_t *dsdt, unsigned long *current)
+{
+}
+
+void __attribute__((weak)) acpi_dmi_workaround(unsigned long *current)
+{
+}
+
+
+
void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id)
{
unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t);
@@ -409,8 +423,9 @@ void acpi_create_facs(acpi_facs_t *facs)
facs->version = 1; /* ACPI 1.0: 0, ACPI 2.0/3.0: 1, ACPI 4.0: 2 */
}
-void acpi_write_rsdt(acpi_rsdt_t *rsdt)
+acpi_rsdt_t *acpi_write_rsdt(unsigned long *current)
{
+ acpi_rsdt_t *rsdt = (acpi_rsdt_t *)*current;
acpi_header_t *header = &(rsdt->header);
/* Fill out header fields. */
@@ -426,10 +441,14 @@ void acpi_write_rsdt(acpi_rsdt_t *rsdt)
/* Fix checksum. */
header->checksum = acpi_checksum((void *)rsdt, sizeof(acpi_rsdt_t));
+ *current += sizeof(acpi_rsdt_t);
+ *current = ALIGN(*current, 64);
+ return rsdt;
}
-void acpi_write_xsdt(acpi_xsdt_t *xsdt)
+acpi_xsdt_t *acpi_write_xsdt(unsigned long *current)
{
+ acpi_xsdt_t *xsdt = (acpi_xsdt_t *)*current;
acpi_header_t *header = &(xsdt->header);
/* Fill out header fields. */
@@ -445,10 +464,15 @@ void acpi_write_xsdt(acpi_xsdt_t *xsdt)
/* Fix checksum. */
header->checksum = acpi_checksum((void *)xsdt, sizeof(acpi_xsdt_t));
+ *current += sizeof(acpi_xsdt_t);
+ *current = ALIGN(*current, 64);
+ return xsdt;
}
-void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, acpi_xsdt_t *xsdt)
+
+acpi_rsdp_t *acpi_write_rsdp(acpi_rsdt_t *rsdt, acpi_xsdt_t *xsdt, unsigned
long *current)
{
+ acpi_rsdp_t *rsdp = (acpi_rsdp_t *)*current;
memset(rsdp, 0, sizeof(acpi_rsdp_t));
memcpy(rsdp->signature, RSDP_SIG, 8);
@@ -474,6 +498,229 @@ void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t
*rsdt, acpi_xsdt_t *xsdt)
/* Calculate checksums. */
rsdp->checksum = acpi_checksum((void *)rsdp, 20);
rsdp->ext_checksum = acpi_checksum((void *)rsdp, sizeof(acpi_rsdp_t));
+ *current += sizeof(acpi_rsdp_t);
+ *current = ALIGN(*current, 64);
+ return rsdp;
+}
+
+
+
+acpi_header_t *acpi_write_dsdt(const unsigned char *AmlCode, unsigned long
*current)
+{
+ acpi_header_t *dsdt = (acpi_header_t *)*current;
+ int len;
+
+ len = ((acpi_header_t *)AmlCode)->length;
+
+ printk(BIOS_DEBUG, "ACPI:* DSDT @ %p, len %d\n", dsdt, len);
+ memcpy(dsdt, AmlCode, len);
+ *current += len;
+ *current = ALIGN(*current, 64);
+ acpi_patch_dsdt(dsdt, current);
+ return dsdt;
+}
+
+acpi_facs_t *acpi_write_facs(unsigned long *current)
+{
+ acpi_facs_t *facs = (acpi_facs_t *)*current;
+ printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", *current);
+ *current += sizeof(acpi_facs_t);
+ *current = ALIGN(*current, 64);
+ acpi_create_facs(facs);
+ return facs;
+}
+
+
+acpi_fadt_t *acpi_write_fadt(acpi_facs_t *facs, acpi_header_t *dsdt,
acpi_rsdp_t *rsdp, unsigned long *current)
[coreboot] Patch set updated: 12782b2 usage example of the simplified ACPI code
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/77
-gerrit
commit 12782b234da51bddd571a19c33cf7a3fd8197599
Author: Cristian Măgherușan-Stanciu
Date: Sat Jul 2 01:11:11 2011 +0300
usage example of the simplified ACPI code
Change-Id: I7dcbf14a327fb347973b4cd9b7b3a4d6cdb31d7f
Signed-off-by: Cristian Măgherușan-Stanciu
---
src/mainboard/asus/m2v-mx_se/acpi_tables.c | 100 +--
src/mainboard/lenovo/t60/acpi_tables.c | 194 +++-
2 files changed, 20 insertions(+), 274 deletions(-)
diff --git a/src/mainboard/asus/m2v-mx_se/acpi_tables.c
b/src/mainboard/asus/m2v-mx_se/acpi_tables.c
index 73e3768..1471ad9 100644
--- a/src/mainboard/asus/m2v-mx_se/acpi_tables.c
+++ b/src/mainboard/asus/m2v-mx_se/acpi_tables.c
@@ -94,103 +94,5 @@ unsigned long acpi_fill_ssdt_generator(unsigned long
current, const char *oem_ta
unsigned long write_acpi_tables(unsigned long start)
{
- unsigned long current;
- acpi_rsdp_t *rsdp;
- acpi_srat_t *srat;
- acpi_rsdt_t *rsdt;
- acpi_mcfg_t *mcfg;
- acpi_hpet_t *hpet;
- acpi_madt_t *madt;
- acpi_fadt_t *fadt;
- acpi_facs_t *facs;
- acpi_slit_t *slit;
- acpi_header_t *ssdt;
- acpi_header_t *dsdt;
-
- /* Align ACPI tables to 16 byte. */
- start = (start + 0x0f) & -0x10;
- current = start;
-
- printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
-
- /* We need at least an RSDP and an RSDT table. */
- rsdp = (acpi_rsdp_t *) current;
- current += sizeof(acpi_rsdp_t);
- rsdt = (acpi_rsdt_t *) current;
- current += sizeof(acpi_rsdt_t);
-
- /* Clear all table memory. */
- memset((void *) start, 0, current - start);
-
- acpi_write_rsdp(rsdp, rsdt, NULL);
- acpi_write_rsdt(rsdt);
-
- /* We explicitly add these tables later on: */
- printk(BIOS_DEBUG, "ACPI: * FACS\n");
-
- /* we should align FACS to 64B as per ACPI specs */
-
- current = ALIGN(current, 64);
- facs = (acpi_facs_t *) current;
- current += sizeof(acpi_facs_t);
- acpi_create_facs(facs);
-
- dsdt = (acpi_header_t *) current;
- memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
- current += dsdt->length;
- memcpy(dsdt, &AmlCode, dsdt->length);
- dsdt->checksum = 0; /* Don't trust iasl to get this right. */
- dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length);
- printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
-dsdt->length);
- printk(BIOS_DEBUG, "ACPI: * FADT\n");
-
- fadt = (acpi_fadt_t *) current;
- current += sizeof(acpi_fadt_t);
-
- acpi_create_fadt(fadt, facs, dsdt);
- acpi_add_table(rsdp, fadt);
-
- printk(BIOS_DEBUG, "ACPI:* HPET\n");
- hpet = (acpi_hpet_t *) current;
- current += sizeof(acpi_hpet_t);
- acpi_create_hpet(hpet);
- acpi_add_table(rsdp, hpet);
-
- /* If we want to use HPET timers Linux wants an MADT. */
- printk(BIOS_DEBUG, "ACPI:* MADT\n");
- madt = (acpi_madt_t *) current;
- acpi_create_madt(madt);
- current += madt->header.length;
- acpi_add_table(rsdp, madt);
-
- printk(BIOS_DEBUG, "ACPI:* MCFG\n");
- mcfg = (acpi_mcfg_t *) current;
- acpi_create_mcfg(mcfg);
- current += mcfg->header.length;
- acpi_add_table(rsdp, mcfg);
-
- printk(BIOS_DEBUG, "ACPI:* SRAT\n");
- srat = (acpi_srat_t *) current;
- acpi_create_srat(srat);
- current += srat->header.length;
- acpi_add_table(rsdp, srat);
-
- /* SLIT */
-printk(BIOS_DEBUG, "ACPI:* SLIT\n");
-slit = (acpi_slit_t *) current;
-acpi_create_slit(slit);
-current+=slit->header.length;
-acpi_add_table(rsdp,slit);
-
- /* SSDT */
- printk(BIOS_DEBUG, "ACPI:* SSDT\n");
- ssdt = (acpi_header_t *)current;
-
- acpi_create_ssdt_generator(ssdt, "DYNADATA");
- current += ssdt->length;
- acpi_add_table(rsdp, ssdt);
-
- printk(BIOS_INFO, "ACPI: done.\n");
- return current;
+ return acpi_write_tables(start, AmlCode);
}
diff --git a/src/mainboard/lenovo/t60/acpi_tables.c
b/src/mainboard/lenovo/t60/acpi_tables.c
index 3742c20..4056e75 100644
--- a/src/mainboard/lenovo/t60/acpi_tables.c
+++ b/src/mainboard/lenovo/t60/acpi_tables.c
@@ -32,9 +32,6 @@
#include "dmi.h"
extern const unsigned char AmlCode[];
-#if CONFIG_HAVE_ACPI_SLIC
-unsigned long acpi_create_slic(unsigned long current);
-#endif
#include "southbridge/intel/i82801gx/nvs.h"
static void acpi_create_gnvs(global_nvs_t *g
[coreboot] Patch set updated: 55aacb4 added support for multiple vendors in the HPET code
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/75 -gerrit commit 55aacb4b76b37451df7215ddbe3d41f4ddd82a4f Author: Cristian Măgherușan-Stanciu Date: Sat Jul 2 01:03:50 2011 +0300 added support for multiple vendors in the HPET code Change-Id: Id13709329c8cc2b3acb55b7ec78fc53c805543eb Signed-off-by: Cristian Măgherușan-Stanciu --- src/arch/x86/boot/acpi.c | 15 +-- 1 files changed, 13 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index caf860e..8be7437 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -376,9 +376,20 @@ void acpi_create_hpet(acpi_hpet_t *hpet) addr->addrl = HPET_ADDR & 0x; addr->addrh = HPET_ADDR >> 32; - hpet->id = 0x102282a0; /* AMD! FIXME */ + /* XXX: Add other vendors */ +#if CONFIG_VENDOR_INTEL + hpet->id = 0x8086a201; + hpet->min_tick = 0x80; +#endif +#if CONFIG_VENDOR_AMD + hpet->id = 0x102282a0; + hpet->min_tick = 0x1000; +#endif +#if CONFIG_VENDOR_VIA + hpet->id = 0x11068201; + hpet->min_tick = 0x90; +#endif hpet->number = 0; - hpet->min_tick = 4096; header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); } -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review: 6a6c528 X60: use new acpi code
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/149
-gerrit
commit 6a6c52824359ec2a0b94492911e89f48d2c75060
Author: Sven Schnelle
Date: Wed Aug 10 22:47:20 2011 +0200
X60: use new acpi code
Change-Id: Id2d7e8fe9e8218eccaef6ad426f40209506a345a
Signed-off-by: Sven Schnelle
---
src/mainboard/lenovo/x60/acpi_tables.c | 194 +++
1 files changed, 19 insertions(+), 175 deletions(-)
diff --git a/src/mainboard/lenovo/x60/acpi_tables.c
b/src/mainboard/lenovo/x60/acpi_tables.c
index 3742c20..4056e75 100644
--- a/src/mainboard/lenovo/x60/acpi_tables.c
+++ b/src/mainboard/lenovo/x60/acpi_tables.c
@@ -32,9 +32,6 @@
#include "dmi.h"
extern const unsigned char AmlCode[];
-#if CONFIG_HAVE_ACPI_SLIC
-unsigned long acpi_create_slic(unsigned long current);
-#endif
#include "southbridge/intel/i82801gx/nvs.h"
static void acpi_create_gnvs(global_nvs_t *gnvs)
@@ -56,38 +53,6 @@ static void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->did[4] = 0x0005;
}
-static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
-{
-#define HPET_ADDR 0xfed0ULL
- acpi_header_t *header = &(hpet->header);
- acpi_addr_t *addr = &(hpet->addr);
-
- memset((void *) hpet, 0, sizeof(acpi_hpet_t));
-
- /* fill out header fields */
- memcpy(header->signature, "HPET", 4);
- memcpy(header->oem_id, OEM_ID, 6);
- memcpy(header->oem_table_id, "COREBOOT", 8);
- memcpy(header->asl_compiler_id, ASLC, 4);
-
- header->length = sizeof(acpi_hpet_t);
- header->revision = 1;
-
- /* fill out HPET address */
- addr->space_id = 0; /* Memory */
- addr->bit_width = 64;
- addr->bit_offset = 0;
- addr->addrl = HPET_ADDR & 0x;
- addr->addrh = HPET_ADDR >> 32;
-
- hpet->id = 0x8086a201; /* Intel */
- hpet->number = 0x00;
- hpet->min_tick = 0x0080;
-
- header->checksum =
- acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
-}
-
unsigned long acpi_fill_madt(unsigned long current)
{
/* Local APICs */
@@ -136,129 +101,31 @@ unsigned long acpi_fill_srat(unsigned long current)
void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
-#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
-unsigned long write_acpi_tables(unsigned long start)
+
+void acpi_patch_dsdt(acpi_header_t *dsdt, unsigned long *current)
{
- unsigned long current;
int i;
- acpi_rsdp_t *rsdp;
- acpi_rsdt_t *rsdt;
- acpi_xsdt_t *xsdt;
- acpi_hpet_t *hpet;
- acpi_madt_t *madt;
- acpi_mcfg_t *mcfg;
- acpi_fadt_t *fadt;
- acpi_facs_t *facs;
-#if CONFIG_HAVE_ACPI_SLIC
- acpi_header_t *slic;
-#endif
- acpi_header_t *ssdt;
- acpi_header_t *dsdt;
void *gnvs;
- current = start;
-
- /* Align ACPI tables to 16byte */
- ALIGN_CURRENT;
-
- printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
-
- /* We need at least an RSDP and an RSDT Table */
- rsdp = (acpi_rsdp_t *) current;
- current += sizeof(acpi_rsdp_t);
- ALIGN_CURRENT;
- rsdt = (acpi_rsdt_t *) current;
- current += sizeof(acpi_rsdt_t);
- ALIGN_CURRENT;
- xsdt = (acpi_xsdt_t *) current;
- current += sizeof(acpi_xsdt_t);
- ALIGN_CURRENT;
-
- /* clear all table memory */
- memset((void *) start, 0, current - start);
-
- acpi_write_rsdp(rsdp, rsdt, xsdt);
- acpi_write_rsdt(rsdt);
- acpi_write_xsdt(xsdt);
-
- /*
-* We explicitly add these tables later on:
-*/
- printk(BIOS_DEBUG, "ACPI:* HPET\n");
-
- hpet = (acpi_hpet_t *) current;
- current += sizeof(acpi_hpet_t);
- ALIGN_CURRENT;
- acpi_create_intel_hpet(hpet);
- acpi_add_table(rsdp, hpet);
-
- /* If we want to use HPET Timers Linux wants an MADT */
- printk(BIOS_DEBUG, "ACPI:* MADT\n");
-
- madt = (acpi_madt_t *) current;
- acpi_create_madt(madt);
- current += madt->header.length;
- ALIGN_CURRENT;
- acpi_add_table(rsdp, madt);
-
- printk(BIOS_DEBUG, "ACPI:* MCFG\n");
- mcfg = (acpi_mcfg_t *) current;
- acpi_create_mcfg(mcfg);
- current += mcfg->header.length;
- ALIGN_CURRENT;
- acpi_add_table(rsdp, mcfg);
-
- printk(BIOS_DEBUG, "ACPI: * FACS\n");
- facs = (acpi_facs_t *) current;
- current += sizeof(acpi_facs_t);
- ALIGN_CURRENT;
- acpi_create_facs(facs);
-
- dsdt = (acpi_header_t *) current;
- memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
- current += dsdt->length;
- memcpy(dsdt, &AmlCode, dsdt->lengt
[coreboot] Patch set updated: d3a81c2 Implemented functions for writing most of the ACPI tables
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/76
-gerrit
commit d3a81c2da0cbfdc4d185388c8b69d131716ddf52
Author: Cristian Măgherușan-Stanciu
Date: Sat Jul 2 01:07:35 2011 +0300
Implemented functions for writing most of the ACPI tables
Fixed compilation failures in the SILC code, but Intel xe7501devkit
still fails to compile due to incomplete southbrige code that does not
implement FADT generation as of yet.
Change-Id: Ib84c845d3f004708a90fd3122485f00b7d20fdbc
Signed-off-by: Cristian Măgherușan-Stanciu
Signed-off-by: Sven Schnelle
---
src/arch/x86/boot/acpi.c | 244 ++
src/arch/x86/boot/tables.c | 10 +-
src/arch/x86/include/arch/acpi.h | 28 -
3 files changed, 248 insertions(+), 34 deletions(-)
diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c
index 8be7437..97110ea 100644
--- a/src/arch/x86/boot/acpi.c
+++ b/src/arch/x86/boot/acpi.c
@@ -16,13 +16,15 @@
*/
/*
- * Each system port implementing ACPI has to provide two functions:
- *
- * write_acpi_tables()
- * acpi_dump_apics()
- *
- * See Kontron 986LCD-M port for a good example of an ACPI implementation
- * in coreboot.
+ * Currently each system port implementing ACPI has to provide the following
functions:
+ * - acpi_fill_mcfg()
+ * - acpi_fill_madt()
+ * - acpi_fill_slit()
+ * - acpi_fill_srat()
+ * Optional
+ * - acpi_fill_ssdt_generator()
+ * - acpi_patch_dsdt()
+ * - acpi_dmi_workaround()
*/
#include
@@ -32,6 +34,8 @@
#include
#include
+extern const unsigned char AmlCode[];
+
u8 acpi_checksum(u8 *table, u32 length)
{
u8 ret = 0;
@@ -42,16 +46,43 @@ u8 acpi_checksum(u8 *table, u32 length)
return -ret;
}
+#if CONFIG_DEBUG_ACPI == 1
+static void dump_mem(void *start, unsigned int cnt)
+{
+ int i;
+
+ for (i = 0; i < cnt; i++) {
+ if (!(i & 0x0f))
+ printk(BIOS_DEBUG, "\n%08x:", (unsigned int)start + i);
+ if (!(i & 0x03)) {
+ printk(BIOS_DEBUG, " ");
+ if (!(i & 0x07))
+ printk(BIOS_DEBUG, " ");
+ }
+ printk(BIOS_DEBUG, " %02x", ((u8 *)start)[i]);
+ }
+ printk(BIOS_DEBUG,"\n");
+}
+#endif
+
/**
* Add an ACPI table to the RSDT (and XSDT) structure, recalculate length
* and checksum.
*/
void acpi_add_table(acpi_rsdp_t *rsdp, void *table)
{
+ acpi_header_t *hdr = (acpi_header_t *)table;
int i, entries_num;
acpi_rsdt_t *rsdt;
acpi_xsdt_t *xsdt = NULL;
+ printk(BIOS_DEBUG, "Adding %4.4s @ %p len %d\n", hdr->signature, table,
hdr->length);
+
+ hdr->checksum = 0;
+ hdr->checksum = acpi_checksum(table, hdr->length);
+#if CONFIG_DEBUG_ACPI == 1
+ dump_mem(table, hdr->length);
+#endif
/* The RSDT is mandatory... */
rsdt = (acpi_rsdt_t *)rsdp->rsdt_address;
@@ -211,8 +242,6 @@ void acpi_create_madt(acpi_madt_t *madt)
/* (Re)calculate length and checksum. */
header->length = current - (unsigned long)madt;
-
- header->checksum = acpi_checksum((void *)madt, header->length);
}
/* MCFG is defined in the PCI Firmware Specification 3.0. */
@@ -236,7 +265,6 @@ void acpi_create_mcfg(acpi_mcfg_t *mcfg)
/* (Re)calculate length and checksum. */
header->length = current - (unsigned long)mcfg;
- header->checksum = acpi_checksum((void *)mcfg, header->length);
}
/*
@@ -249,6 +277,18 @@ unsigned long __attribute__((weak))
acpi_fill_ssdt_generator(
return current;
}
+/* stub functions that might be implemented in the mainboard code, if needed */
+void __attribute__((weak)) acpi_patch_dsdt(
+ acpi_header_t *dsdt, unsigned long *current)
+{
+}
+
+void __attribute__((weak)) acpi_dmi_workaround(unsigned long *current)
+{
+}
+
+
+
void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id)
{
unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t);
@@ -269,7 +309,6 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const
char *oem_table_id)
/* (Re)calculate length and checksum. */
ssdt->length = current - (unsigned long)ssdt;
- ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length);
}
int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic)
@@ -324,7 +363,6 @@ void acpi_create_srat(acpi_srat_t *srat)
/* (Re)calculate length and checksum. */
header->length = current - (unsigned long)srat;
- header->checksum = acpi_checksum((void *)srat, header->length);
}
/* http://h21007.www2.hp.com/portal/download/files/unprot/Itanium/slit.pdf */
@@ -348,7 +3
[coreboot] Patch set updated: aa6b35d usage example of the simplified ACPI code
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/77
-gerrit
commit aa6b35d011e3a66d9a97dfe5032f50360abf0513
Author: Cristian Măgherușan-Stanciu
Date: Sat Jul 2 01:11:11 2011 +0300
usage example of the simplified ACPI code
Change-Id: I7dcbf14a327fb347973b4cd9b7b3a4d6cdb31d7f
Signed-off-by: Cristian Măgherușan-Stanciu
---
src/mainboard/asus/m2v-mx_se/acpi_tables.c | 100 +--
src/mainboard/lenovo/t60/acpi_tables.c | 194 +++-
2 files changed, 20 insertions(+), 274 deletions(-)
diff --git a/src/mainboard/asus/m2v-mx_se/acpi_tables.c
b/src/mainboard/asus/m2v-mx_se/acpi_tables.c
index 73e3768..1471ad9 100644
--- a/src/mainboard/asus/m2v-mx_se/acpi_tables.c
+++ b/src/mainboard/asus/m2v-mx_se/acpi_tables.c
@@ -94,103 +94,5 @@ unsigned long acpi_fill_ssdt_generator(unsigned long
current, const char *oem_ta
unsigned long write_acpi_tables(unsigned long start)
{
- unsigned long current;
- acpi_rsdp_t *rsdp;
- acpi_srat_t *srat;
- acpi_rsdt_t *rsdt;
- acpi_mcfg_t *mcfg;
- acpi_hpet_t *hpet;
- acpi_madt_t *madt;
- acpi_fadt_t *fadt;
- acpi_facs_t *facs;
- acpi_slit_t *slit;
- acpi_header_t *ssdt;
- acpi_header_t *dsdt;
-
- /* Align ACPI tables to 16 byte. */
- start = (start + 0x0f) & -0x10;
- current = start;
-
- printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
-
- /* We need at least an RSDP and an RSDT table. */
- rsdp = (acpi_rsdp_t *) current;
- current += sizeof(acpi_rsdp_t);
- rsdt = (acpi_rsdt_t *) current;
- current += sizeof(acpi_rsdt_t);
-
- /* Clear all table memory. */
- memset((void *) start, 0, current - start);
-
- acpi_write_rsdp(rsdp, rsdt, NULL);
- acpi_write_rsdt(rsdt);
-
- /* We explicitly add these tables later on: */
- printk(BIOS_DEBUG, "ACPI: * FACS\n");
-
- /* we should align FACS to 64B as per ACPI specs */
-
- current = ALIGN(current, 64);
- facs = (acpi_facs_t *) current;
- current += sizeof(acpi_facs_t);
- acpi_create_facs(facs);
-
- dsdt = (acpi_header_t *) current;
- memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
- current += dsdt->length;
- memcpy(dsdt, &AmlCode, dsdt->length);
- dsdt->checksum = 0; /* Don't trust iasl to get this right. */
- dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length);
- printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
-dsdt->length);
- printk(BIOS_DEBUG, "ACPI: * FADT\n");
-
- fadt = (acpi_fadt_t *) current;
- current += sizeof(acpi_fadt_t);
-
- acpi_create_fadt(fadt, facs, dsdt);
- acpi_add_table(rsdp, fadt);
-
- printk(BIOS_DEBUG, "ACPI:* HPET\n");
- hpet = (acpi_hpet_t *) current;
- current += sizeof(acpi_hpet_t);
- acpi_create_hpet(hpet);
- acpi_add_table(rsdp, hpet);
-
- /* If we want to use HPET timers Linux wants an MADT. */
- printk(BIOS_DEBUG, "ACPI:* MADT\n");
- madt = (acpi_madt_t *) current;
- acpi_create_madt(madt);
- current += madt->header.length;
- acpi_add_table(rsdp, madt);
-
- printk(BIOS_DEBUG, "ACPI:* MCFG\n");
- mcfg = (acpi_mcfg_t *) current;
- acpi_create_mcfg(mcfg);
- current += mcfg->header.length;
- acpi_add_table(rsdp, mcfg);
-
- printk(BIOS_DEBUG, "ACPI:* SRAT\n");
- srat = (acpi_srat_t *) current;
- acpi_create_srat(srat);
- current += srat->header.length;
- acpi_add_table(rsdp, srat);
-
- /* SLIT */
-printk(BIOS_DEBUG, "ACPI:* SLIT\n");
-slit = (acpi_slit_t *) current;
-acpi_create_slit(slit);
-current+=slit->header.length;
-acpi_add_table(rsdp,slit);
-
- /* SSDT */
- printk(BIOS_DEBUG, "ACPI:* SSDT\n");
- ssdt = (acpi_header_t *)current;
-
- acpi_create_ssdt_generator(ssdt, "DYNADATA");
- current += ssdt->length;
- acpi_add_table(rsdp, ssdt);
-
- printk(BIOS_INFO, "ACPI: done.\n");
- return current;
+ return acpi_write_tables(start, AmlCode);
}
diff --git a/src/mainboard/lenovo/t60/acpi_tables.c
b/src/mainboard/lenovo/t60/acpi_tables.c
index 3742c20..4056e75 100644
--- a/src/mainboard/lenovo/t60/acpi_tables.c
+++ b/src/mainboard/lenovo/t60/acpi_tables.c
@@ -32,9 +32,6 @@
#include "dmi.h"
extern const unsigned char AmlCode[];
-#if CONFIG_HAVE_ACPI_SLIC
-unsigned long acpi_create_slic(unsigned long current);
-#endif
#include "southbridge/intel/i82801gx/nvs.h"
static void acpi_create_gnvs(global_nvs_t *g
[coreboot] Patch set updated: 071f750 X60: use new acpi code
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/149
-gerrit
commit 071f7502bf104035e6c42d1b3f0281d5607bbeea
Author: Sven Schnelle
Date: Wed Aug 10 22:47:20 2011 +0200
X60: use new acpi code
Change-Id: Id2d7e8fe9e8218eccaef6ad426f40209506a345a
Signed-off-by: Sven Schnelle
---
src/mainboard/lenovo/x60/acpi_tables.c | 193 +++-
src/mainboard/lenovo/x60/mainboard.c |4 +
2 files changed, 19 insertions(+), 178 deletions(-)
diff --git a/src/mainboard/lenovo/x60/acpi_tables.c
b/src/mainboard/lenovo/x60/acpi_tables.c
index 3742c20..af214fb 100644
--- a/src/mainboard/lenovo/x60/acpi_tables.c
+++ b/src/mainboard/lenovo/x60/acpi_tables.c
@@ -32,9 +32,6 @@
#include "dmi.h"
extern const unsigned char AmlCode[];
-#if CONFIG_HAVE_ACPI_SLIC
-unsigned long acpi_create_slic(unsigned long current);
-#endif
#include "southbridge/intel/i82801gx/nvs.h"
static void acpi_create_gnvs(global_nvs_t *gnvs)
@@ -56,38 +53,6 @@ static void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->did[4] = 0x0005;
}
-static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
-{
-#define HPET_ADDR 0xfed0ULL
- acpi_header_t *header = &(hpet->header);
- acpi_addr_t *addr = &(hpet->addr);
-
- memset((void *) hpet, 0, sizeof(acpi_hpet_t));
-
- /* fill out header fields */
- memcpy(header->signature, "HPET", 4);
- memcpy(header->oem_id, OEM_ID, 6);
- memcpy(header->oem_table_id, "COREBOOT", 8);
- memcpy(header->asl_compiler_id, ASLC, 4);
-
- header->length = sizeof(acpi_hpet_t);
- header->revision = 1;
-
- /* fill out HPET address */
- addr->space_id = 0; /* Memory */
- addr->bit_width = 64;
- addr->bit_offset = 0;
- addr->addrl = HPET_ADDR & 0x;
- addr->addrh = HPET_ADDR >> 32;
-
- hpet->id = 0x8086a201; /* Intel */
- hpet->number = 0x00;
- hpet->min_tick = 0x0080;
-
- header->checksum =
- acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
-}
-
unsigned long acpi_fill_madt(unsigned long current)
{
/* Local APICs */
@@ -136,129 +101,31 @@ unsigned long acpi_fill_srat(unsigned long current)
void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
-#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
-unsigned long write_acpi_tables(unsigned long start)
+
+void acpi_patch_dsdt(acpi_header_t *dsdt, unsigned long *current)
{
- unsigned long current;
int i;
- acpi_rsdp_t *rsdp;
- acpi_rsdt_t *rsdt;
- acpi_xsdt_t *xsdt;
- acpi_hpet_t *hpet;
- acpi_madt_t *madt;
- acpi_mcfg_t *mcfg;
- acpi_fadt_t *fadt;
- acpi_facs_t *facs;
-#if CONFIG_HAVE_ACPI_SLIC
- acpi_header_t *slic;
-#endif
- acpi_header_t *ssdt;
- acpi_header_t *dsdt;
void *gnvs;
- current = start;
-
- /* Align ACPI tables to 16byte */
- ALIGN_CURRENT;
-
- printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
-
- /* We need at least an RSDP and an RSDT Table */
- rsdp = (acpi_rsdp_t *) current;
- current += sizeof(acpi_rsdp_t);
- ALIGN_CURRENT;
- rsdt = (acpi_rsdt_t *) current;
- current += sizeof(acpi_rsdt_t);
- ALIGN_CURRENT;
- xsdt = (acpi_xsdt_t *) current;
- current += sizeof(acpi_xsdt_t);
- ALIGN_CURRENT;
-
- /* clear all table memory */
- memset((void *) start, 0, current - start);
-
- acpi_write_rsdp(rsdp, rsdt, xsdt);
- acpi_write_rsdt(rsdt);
- acpi_write_xsdt(xsdt);
-
- /*
-* We explicitly add these tables later on:
-*/
- printk(BIOS_DEBUG, "ACPI:* HPET\n");
-
- hpet = (acpi_hpet_t *) current;
- current += sizeof(acpi_hpet_t);
- ALIGN_CURRENT;
- acpi_create_intel_hpet(hpet);
- acpi_add_table(rsdp, hpet);
-
- /* If we want to use HPET Timers Linux wants an MADT */
- printk(BIOS_DEBUG, "ACPI:* MADT\n");
-
- madt = (acpi_madt_t *) current;
- acpi_create_madt(madt);
- current += madt->header.length;
- ALIGN_CURRENT;
- acpi_add_table(rsdp, madt);
-
- printk(BIOS_DEBUG, "ACPI:* MCFG\n");
- mcfg = (acpi_mcfg_t *) current;
- acpi_create_mcfg(mcfg);
- current += mcfg->header.length;
- ALIGN_CURRENT;
- acpi_add_table(rsdp, mcfg);
-
- printk(BIOS_DEBUG, "ACPI: * FACS\n");
- facs = (acpi_facs_t *) current;
- current += sizeof(acpi_facs_t);
- ALIGN_CURRENT;
- acpi_create_facs(facs);
-
- dsdt = (acpi_header_t *) current;
- memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
- current += dsdt->length;
[coreboot] New patch to review: 21b1ac9 Add automatic SMBIOS table generation
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/152 -gerrit commit 21b1ac93f1fce25d7a8b9a76695d50ef9601e629 Author: Sven Schnelle Date: Sun Aug 14 20:56:34 2011 +0200 Add automatic SMBIOS table generation Change-Id: I0ae16dda8969638a8f70fe1d2e29e992aef3a834 Signed-off-by: Sven Schnelle --- Makefile.inc |1 + src/Kconfig | 14 ++- src/arch/x86/boot/Makefile.inc|1 + src/arch/x86/boot/smbios.c| 239 + src/arch/x86/boot/tables.c| 23 +++- src/include/cbmem.h |1 + src/include/smbios.h | 168 + src/lib/cbmem.c |1 + src/mainboard/getac/p470/acpi_tables.c| 10 - src/mainboard/getac/p470/dmi.h| 31 src/mainboard/ibase/mb899/acpi_tables.c | 10 - src/mainboard/ibase/mb899/dmi.h | 29 --- src/mainboard/intel/d945gclf/acpi_tables.c| 10 - src/mainboard/intel/d945gclf/dmi.h| 29 --- src/mainboard/iwave/iWRainbowG6/acpi_tables.c | 10 - src/mainboard/iwave/iWRainbowG6/dmi.h | 34 src/mainboard/kontron/986lcd-m/acpi_tables.c | 10 - src/mainboard/kontron/986lcd-m/dmi.h | 29 --- src/mainboard/lenovo/t60/acpi_tables.c| 10 - src/mainboard/lenovo/x60/acpi_tables.c| 10 - src/mainboard/roda/rk886ex/acpi_tables.c | 10 - src/mainboard/roda/rk886ex/dmi.h | 29 --- src/mainboard/via/vt8454c/acpi_tables.c |5 - src/mainboard/via/vt8454c/dmi.h | 29 --- 24 files changed, 446 insertions(+), 297 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 89467db..2cc547a 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -128,6 +128,7 @@ $(obj)/build.h: .xcompile printf "#define COREBOOT_VERSION \"$(KERNELVERSION)\"\n" >> $(obj)/build.ht printf "#define COREBOOT_EXTRA_VERSION \"$(COREBOOT_EXTRA_VERSION)\"\n" >> $(obj)/build.ht printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_DMI_DATE \"`LANG= date +"%m/%d/%Y"`\"\n" >> $(obj)/build.ht printf "\n" >> $(obj)/build.ht printf "#define COREBOOT_COMPILER \"$(shell LANG= $(CC) --version | head -n1)\"\n" >> $(obj)/build.ht printf "#define COREBOOT_ASSEMBLER \"$(shell LANG= $(AS) --version | head -n1)\"\n" >> $(obj)/build.ht diff --git a/src/Kconfig b/src/Kconfig index 7b4f487..270b499 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -87,7 +87,7 @@ config SCONFIG_GENPARSER help Enable this option if you are working on the sconfig device tree parser and made changes to sconfig.l and - sconfig.y. + sconfig.y. Otherwise, say N. config USE_OPTION_TABLE @@ -304,6 +304,10 @@ config GENERATE_PIRQ_TABLE bool default HAVE_PIRQ_TABLE +config GENERATE_SMBIOS_TABLES + bool + default y + menu "System tables" config WRITE_HIGH_TABLES @@ -342,6 +346,14 @@ config GENERATE_PIRQ_TABLE If unsure, say Y. +config GENERATE_SMBIOS_TABLES + bool "Generate SMBIOS tables" + default y + help + Generate SMBIOS tables for this board. + + If unsure, say Y. + endmenu menu "Payload" diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index d4a377f..0b448ad 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -6,6 +6,7 @@ ramstage-y += tables.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpigen.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c new file mode 100644 index 000..08560bb --- /dev/null +++ b/src/arch/x86/boot/smbios.c @@ -0,0 +1,239 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more
[coreboot] Patch set updated: 8d4bc2c Add automatic SMBIOS table generation
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/152 -gerrit commit 8d4bc2c422f6b650a918cef5b6766f1c2552c22b Author: Sven Schnelle Date: Sun Aug 14 20:56:34 2011 +0200 Add automatic SMBIOS table generation Change-Id: I0ae16dda8969638a8f70fe1d2e29e992aef3a834 Signed-off-by: Sven Schnelle --- Makefile.inc |1 + src/Kconfig| 15 ++- src/arch/x86/boot/Makefile.inc |2 + src/arch/x86/boot/smbios.c | 290 src/arch/x86/boot/tables.c | 23 ++- src/include/cbmem.h|1 + src/include/device/device.h|2 + src/include/smbios.h | 197 src/lib/cbmem.c|1 + src/mainboard/emulation/qemu-x86/northbridge.c | 69 ++- src/mainboard/getac/p470/acpi_tables.c | 10 - src/mainboard/getac/p470/dmi.h | 31 --- src/mainboard/ibase/mb899/acpi_tables.c| 10 - src/mainboard/ibase/mb899/dmi.h| 29 --- src/mainboard/intel/d945gclf/acpi_tables.c | 10 - src/mainboard/intel/d945gclf/dmi.h | 29 --- src/mainboard/iwave/iWRainbowG6/acpi_tables.c | 10 - src/mainboard/iwave/iWRainbowG6/dmi.h | 34 --- src/mainboard/kontron/986lcd-m/acpi_tables.c | 10 - src/mainboard/kontron/986lcd-m/dmi.h | 29 --- src/mainboard/lenovo/t60/acpi_tables.c | 10 - src/mainboard/lenovo/x60/acpi_tables.c | 10 - src/mainboard/roda/rk886ex/acpi_tables.c | 10 - src/mainboard/roda/rk886ex/dmi.h | 29 --- src/mainboard/via/vt8454c/acpi_tables.c|5 - src/mainboard/via/vt8454c/dmi.h| 29 --- 26 files changed, 594 insertions(+), 302 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 89467db..2cc547a 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -128,6 +128,7 @@ $(obj)/build.h: .xcompile printf "#define COREBOOT_VERSION \"$(KERNELVERSION)\"\n" >> $(obj)/build.ht printf "#define COREBOOT_EXTRA_VERSION \"$(COREBOOT_EXTRA_VERSION)\"\n" >> $(obj)/build.ht printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_DMI_DATE \"`LANG= date +"%m/%d/%Y"`\"\n" >> $(obj)/build.ht printf "\n" >> $(obj)/build.ht printf "#define COREBOOT_COMPILER \"$(shell LANG= $(CC) --version | head -n1)\"\n" >> $(obj)/build.ht printf "#define COREBOOT_ASSEMBLER \"$(shell LANG= $(AS) --version | head -n1)\"\n" >> $(obj)/build.ht diff --git a/src/Kconfig b/src/Kconfig index 7b4f487..f96c903 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -87,7 +87,7 @@ config SCONFIG_GENPARSER help Enable this option if you are working on the sconfig device tree parser and made changes to sconfig.l and - sconfig.y. + sconfig.y. Otherwise, say N. config USE_OPTION_TABLE @@ -304,6 +304,10 @@ config GENERATE_PIRQ_TABLE bool default HAVE_PIRQ_TABLE +config GENERATE_SMBIOS_TABLES + bool + default y + menu "System tables" config WRITE_HIGH_TABLES @@ -342,6 +346,15 @@ config GENERATE_PIRQ_TABLE If unsure, say Y. +config GENERATE_SMBIOS_TABLES + depends on ARCH_X86 + bool "Generate SMBIOS tables" + default y + help + Generate SMBIOS tables for this board. + + If unsure, say Y. + endmenu menu "Payload" diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index d4a377f..3f11c01 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -6,8 +6,10 @@ ramstage-y += tables.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpigen.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S $(obj)/arch/x86/boot/coreboot_table.ramstage.o : $(OPTION_TABLE_H) +$(obj)/arch/x86/boot/smbios.ramstage.o: $(obj)/build.h diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c new file mode 100644 index 000..87eea64 --- /dev/null +++ b/src/arch/x86/boot/smbios.c @@ -0,0 +1,290 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free
[coreboot] New patch to review: 4cc7400 export get_cbfs_header()
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/157
-gerrit
commit 4cc740025729dc0f97d704119d2031c1f47e46bc
Author: Sven Schnelle
Date: Wed Aug 17 18:10:11 2011 +0200
export get_cbfs_header()
Change-Id: I4b6afcee3d0d169e03165a7fb48cfaef2e8253e2
Signed-off-by: Sven Schnelle
---
src/include/cbfs_core.h |1 +
src/lib/cbfs_core.c |2 +-
2 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/src/include/cbfs_core.h b/src/include/cbfs_core.h
index fbe0081..70368f8 100644
--- a/src/include/cbfs_core.h
+++ b/src/include/cbfs_core.h
@@ -176,5 +176,6 @@ void *cbfs_find_file(const char *name, int type);
/* returns 0 on success, -1 on failure */
int cbfs_decompress(int algo, void *src, void *dst, int len);
+struct cbfs_header *get_cbfs_header(void);
#endif
diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c
index 52ba58d..596fa3f 100644
--- a/src/lib/cbfs_core.c
+++ b/src/lib/cbfs_core.c
@@ -55,7 +55,7 @@
/* returns pointer to master header or 0x if not found */
-static struct cbfs_header *get_cbfs_header(void)
+struct cbfs_header *get_cbfs_header(void)
{
struct cbfs_header *header;
--
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[coreboot] Patch set updated: d728674 Add automatic SMBIOS table generation
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/152 -gerrit commit d72867419468c612f18158045817e8e38094d99b Author: Sven Schnelle Date: Sun Aug 14 20:56:34 2011 +0200 Add automatic SMBIOS table generation Change-Id: I0ae16dda8969638a8f70fe1d2e29e992aef3a834 Signed-off-by: Sven Schnelle --- Makefile.inc |1 + src/Kconfig| 15 ++- src/arch/x86/boot/Makefile.inc |2 + src/arch/x86/boot/smbios.c | 293 src/arch/x86/boot/tables.c | 23 ++- src/include/cbmem.h|1 + src/include/device/device.h|6 + src/include/smbios.h | 197 src/lib/cbmem.c|1 + src/mainboard/emulation/qemu-x86/northbridge.c | 72 ++- src/mainboard/getac/p470/acpi_tables.c | 10 - src/mainboard/getac/p470/dmi.h | 31 --- src/mainboard/ibase/mb899/acpi_tables.c| 10 - src/mainboard/ibase/mb899/dmi.h| 29 --- src/mainboard/intel/d945gclf/acpi_tables.c | 10 - src/mainboard/intel/d945gclf/dmi.h | 29 --- src/mainboard/iwave/iWRainbowG6/acpi_tables.c | 10 - src/mainboard/iwave/iWRainbowG6/dmi.h | 34 --- src/mainboard/kontron/986lcd-m/acpi_tables.c | 10 - src/mainboard/kontron/986lcd-m/dmi.h | 29 --- src/mainboard/lenovo/t60/acpi_tables.c | 10 - src/mainboard/lenovo/x60/acpi_tables.c | 10 - src/mainboard/roda/rk886ex/acpi_tables.c | 10 - src/mainboard/roda/rk886ex/dmi.h | 29 --- src/mainboard/via/vt8454c/acpi_tables.c|5 - src/mainboard/via/vt8454c/dmi.h| 29 --- 26 files changed, 604 insertions(+), 302 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 89467db..2cc547a 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -128,6 +128,7 @@ $(obj)/build.h: .xcompile printf "#define COREBOOT_VERSION \"$(KERNELVERSION)\"\n" >> $(obj)/build.ht printf "#define COREBOOT_EXTRA_VERSION \"$(COREBOOT_EXTRA_VERSION)\"\n" >> $(obj)/build.ht printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_DMI_DATE \"`LANG= date +"%m/%d/%Y"`\"\n" >> $(obj)/build.ht printf "\n" >> $(obj)/build.ht printf "#define COREBOOT_COMPILER \"$(shell LANG= $(CC) --version | head -n1)\"\n" >> $(obj)/build.ht printf "#define COREBOOT_ASSEMBLER \"$(shell LANG= $(AS) --version | head -n1)\"\n" >> $(obj)/build.ht diff --git a/src/Kconfig b/src/Kconfig index 7b4f487..f96c903 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -87,7 +87,7 @@ config SCONFIG_GENPARSER help Enable this option if you are working on the sconfig device tree parser and made changes to sconfig.l and - sconfig.y. + sconfig.y. Otherwise, say N. config USE_OPTION_TABLE @@ -304,6 +304,10 @@ config GENERATE_PIRQ_TABLE bool default HAVE_PIRQ_TABLE +config GENERATE_SMBIOS_TABLES + bool + default y + menu "System tables" config WRITE_HIGH_TABLES @@ -342,6 +346,15 @@ config GENERATE_PIRQ_TABLE If unsure, say Y. +config GENERATE_SMBIOS_TABLES + depends on ARCH_X86 + bool "Generate SMBIOS tables" + default y + help + Generate SMBIOS tables for this board. + + If unsure, say Y. + endmenu menu "Payload" diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index d4a377f..3f11c01 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -6,8 +6,10 @@ ramstage-y += tables.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpigen.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S $(obj)/arch/x86/boot/coreboot_table.ramstage.o : $(OPTION_TABLE_H) +$(obj)/arch/x86/boot/smbios.ramstage.o: $(obj)/build.h diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c new file mode 100644 index 000..e5156d9 --- /dev/null +++ b/src/arch/x86/boot/smbios.c @@ -0,0 +1,293 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free
[coreboot] New patch to review: 7793ddb X60: use EC events 0x50/0x58 instead of GPIO GPE for Docking/Undocking
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/161
-gerrit
commit 7793ddb6ddb3040ecf4b49731e2cbb1779d55f1f
Author: Sven Schnelle
Date: Mon Jul 11 18:36:16 2011 +0200
X60: use EC events 0x50/0x58 instead of GPIO GPE for Docking/Undocking
Change-Id: I674e5166f5fb7ba299e6f1231f30434a5bf731c5
Signed-off-by: Sven Schnelle
---
src/mainboard/lenovo/x60/acpi/dock.asl | 14 --
src/mainboard/lenovo/x60/acpi/gpe.asl| 12
src/mainboard/lenovo/x60/devicetree.cb | 11 ++-
src/mainboard/lenovo/x60/dock.c | 10 +-
src/mainboard/lenovo/x60/mainboard.c |6 ++
src/mainboard/lenovo/x60/mainboard_smi.c | 23 ---
6 files changed, 57 insertions(+), 19 deletions(-)
diff --git a/src/mainboard/lenovo/x60/acpi/dock.asl
b/src/mainboard/lenovo/x60/acpi/dock.asl
index d393f44..136f888 100644
--- a/src/mainboard/lenovo/x60/acpi/dock.asl
+++ b/src/mainboard/lenovo/x60/acpi/dock.asl
@@ -39,7 +39,6 @@ Scope (\_SB)
Method(_DCK, 1, NotSerialized)
{
if (Arg0) {
- Sleep(250)
/* connect dock */
TRAP(SMI_DOCK_CONNECT)
} else {
@@ -53,7 +52,7 @@ Scope (\_SB)
Method(_STA, 0, NotSerialized)
{
- Return (DSTA)
+ Return (DSTA)
}
}
}
@@ -64,4 +63,15 @@ Scope(\_SB.PCI0.LPCB.EC)
{
Notify(\_SB.DOCK, 3)
}
+
+ Method(_Q50, 0, NotSerialized)
+ {
+ Notify(\_SB.DOCK, 3)
+ }
+
+ Method(_Q58, 0, NotSerialized)
+ {
+ Notify(\_SB.DOCK, 0)
+ }
+
}
diff --git a/src/mainboard/lenovo/x60/acpi/gpe.asl
b/src/mainboard/lenovo/x60/acpi/gpe.asl
index 11e5dc0..b160b50 100644
--- a/src/mainboard/lenovo/x60/acpi/gpe.asl
+++ b/src/mainboard/lenovo/x60/acpi/gpe.asl
@@ -27,16 +27,4 @@ Scope (\_GPE)
/* Read EC register to clear wake status */
Store(\_SB.PCI0.LPCB.EC.WAKE, Local0)
}
-
- /* SLICE_ON_3M GPE (Dock status) */
- Method(_L1D, 0, NotSerialized)
- {
- if (GP13) {
- Or(GIV1, 0x20, GIV1)
- Notify(\_SB.DOCK, 3)
- } else {
- And(GIV1, 0xdf, GIV1)
- Notify(\_SB.DOCK, 0)
- }
- }
}
diff --git a/src/mainboard/lenovo/x60/devicetree.cb
b/src/mainboard/lenovo/x60/devicetree.cb
index 42a45d1..55e0b2d 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -86,6 +86,7 @@ chip northbridge/intel/i945
device pnp ff.1 on # dummy
end
register "backlight_enable" = "0x01"
+ register "dock_event_enable" = "0x01"
end
chip ec/lenovo/h8
device pnp ff.2 on # dummy
@@ -98,7 +99,7 @@ chip northbridge/intel/i945
register "config0" = "0xa6"
register "config1" = "0x05"
register "config2" = "0xa0"
- register "config3" = "0x05"
+ register "config3" = "0x01"
register "beepmask0" = "0xfe"
register "beepmask1" = "0x96"
@@ -107,7 +108,15 @@ chip northbridge/intel/i945
register "event3_enable" = "0xff"
register "event4_enable" = "0xf4"
register "event5_enable" = "0x3c"
+ register "event6_enable" = "0x80"
+ register "event7_enable" = "0x01"
register "eventc_enable" = "0x3c"
+ register "event8_enable" = "0x01"
+ register "event9_enable" = "0xff"
+ register "eventa_enable" = "0xff"
+ register "eventb_enable" = "0xff"
+
[coreboot] New patch to review: 82e82f6 Lenovo H8: clear audio mute
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/162
-gerrit
commit 82e82f6a480131e3e02096f5aba0b29e293b75e2
Author: Sven Schnelle
Date: Fri Aug 19 13:43:04 2011 +0200
Lenovo H8: clear audio mute
Change-Id: I18bebe532bf21cfb61b3d294a396bf15012f9f1a
Signed-off-by: Sven Schnelle
---
src/ec/lenovo/h8/h8.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c
index 2c25d29..560c39c 100644
--- a/src/ec/lenovo/h8/h8.c
+++ b/src/ec/lenovo/h8/h8.c
@@ -141,6 +141,8 @@ static void h8_enable(device_t dev)
if (!get_option(&val, "volume"))
ec_write(H8_VOLUME_CONTROL, val);
+
+ h8_set_audio_mute(0);
}
struct chip_operations ec_lenovo_h8_ops = {
--
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[coreboot] Patch set updated: 7f87aff Lenovo H8: clear audio mute
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/162
-gerrit
commit 7f87aff40278d16c5df36413f625d6680f63fcb3
Author: Sven Schnelle
Date: Fri Aug 19 13:43:04 2011 +0200
Lenovo H8: clear audio mute
The bit is set by ACPI before poweroff/going to suspend.
So clear it after resume, to have working volume control
even if the ACPI doesn't clear it on resume.
OSPM should control Audio mute with ec bit 0x30:6, so it is
safe to clear this bit even if the user has audio muted.
Change-Id: I18bebe532bf21cfb61b3d294a396bf15012f9f1a
Signed-off-by: Sven Schnelle
---
src/ec/lenovo/h8/h8.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c
index 2c25d29..560c39c 100644
--- a/src/ec/lenovo/h8/h8.c
+++ b/src/ec/lenovo/h8/h8.c
@@ -141,6 +141,8 @@ static void h8_enable(device_t dev)
if (!get_option(&val, "volume"))
ec_write(H8_VOLUME_CONTROL, val);
+
+ h8_set_audio_mute(0);
}
struct chip_operations ec_lenovo_h8_ops = {
--
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[coreboot] Patch set updated: 24cad0c Lenovo H8: Always clear audio mute
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/162
-gerrit
commit 24cad0c7eba676728bae3c8930febbccf07ea3df
Author: Sven Schnelle
Date: Fri Aug 19 13:43:04 2011 +0200
Lenovo H8: Always clear audio mute
The mute bit is set by ACPI before poweroff/going to suspend.
So clear it after resume, to have working volume control
even if the ACPI doesn't clear it on resume.
OSPM should control Audio mute with ec bit 0x30:6, so it is
safe to clear this bit even if the user has audio muted.
Change-Id: I18bebe532bf21cfb61b3d294a396bf15012f9f1a
Signed-off-by: Sven Schnelle
---
src/ec/lenovo/h8/h8.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c
index 2c25d29..560c39c 100644
--- a/src/ec/lenovo/h8/h8.c
+++ b/src/ec/lenovo/h8/h8.c
@@ -141,6 +141,8 @@ static void h8_enable(device_t dev)
if (!get_option(&val, "volume"))
ec_write(H8_VOLUME_CONTROL, val);
+
+ h8_set_audio_mute(0);
}
struct chip_operations ec_lenovo_h8_ops = {
--
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[coreboot] New patch to review: 782eae6 BUILD: add .config dependency to $(obj)/config.h
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/169 -gerrit commit 782eae6fc75f75046bd89c0b4bb72b269ce13992 Author: Sven Schnelle Date: Mon Aug 22 10:38:11 2011 +0200 BUILD: add .config dependency to $(obj)/config.h Without it, replacing .config by a different config leads to all kinds of annoying build errors like the following: $ cp config-t60p .config $ make Makefile:235: warning: overriding commands for target `build/cpu/x86/name/name.ramstage.o' Makefile:235: warning: ignoring old commands for target `build/cpu/x86/name/name.ramstage.o' ROMCC mainboard/lenovo/t60/bootblock.inc GENbootblock/bootblock.S CC mainboard/lenovo/t60/bootblock.s CC mainboard/lenovo/t60/bootblock.o LINK bootblock.elf OBJCOPYcoreboot.bootblock CC lib/ramtest.romstage.o cc1: warnings being treated as errors src/lib/ramtest.c: In function 'ram_fill': src/lib/ramtest.c:60:2: error: format '%08x' expects type 'unsigned int', but argument 3 has type 'long unsigned int' src/lib/ramtest.c:60:2: error: format '%08x' expects type 'unsigned int', but argument 3 has type 'long unsigned int' src/lib/ramtest.c:62:2: error: format '%08x' expects type 'unsigned int', but argument 3 has type 'long unsigned int' src/lib/ramtest.c:62:2: error: format '%08x' expects type 'unsigned int', but argument 3 has type 'long unsigned int' src/lib/ramtest.c:71:4: error: format '%08x' expects type 'unsigned int', but argument 3 has type 'long unsigned int' [..] Change-Id: I0d0509980009f062f621d2afec200f2c5ab0cafa Signed-off-by: Sven Schnelle --- Makefile |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/Makefile b/Makefile index 44a1d63..1fd084f 100644 --- a/Makefile +++ b/Makefile @@ -158,7 +158,7 @@ endif # must come rather early .SECONDEXPANSION: -$(obj)/config.h: +$(obj)/config.h: .config $(MAKE) oldconfig # Add a new class of source/object files to the build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch set updated: 2e78e31 Add automatic SMBIOS table generation
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/152 -gerrit commit 2e78e31959baaf56c4b7e469b55e5d180d5a46b4 Author: Sven Schnelle Date: Sun Aug 14 20:56:34 2011 +0200 Add automatic SMBIOS table generation Change-Id: I0ae16dda8969638a8f70fe1d2e29e992aef3a834 Signed-off-by: Sven Schnelle --- Makefile.inc |1 + src/Kconfig| 15 ++- src/arch/x86/boot/Makefile.inc |2 + src/arch/x86/boot/smbios.c | 293 src/arch/x86/boot/tables.c | 24 ++- src/include/cbmem.h|1 + src/include/device/device.h|6 + src/include/smbios.h | 197 src/lib/cbmem.c|1 + src/mainboard/emulation/qemu-x86/northbridge.c | 72 ++- src/mainboard/getac/p470/acpi_tables.c | 10 - src/mainboard/getac/p470/dmi.h | 31 --- src/mainboard/ibase/mb899/acpi_tables.c| 10 - src/mainboard/ibase/mb899/dmi.h| 29 --- src/mainboard/intel/d945gclf/acpi_tables.c | 10 - src/mainboard/intel/d945gclf/dmi.h | 29 --- src/mainboard/iwave/iWRainbowG6/acpi_tables.c | 10 - src/mainboard/iwave/iWRainbowG6/dmi.h | 34 --- src/mainboard/kontron/986lcd-m/acpi_tables.c | 10 - src/mainboard/kontron/986lcd-m/dmi.h | 29 --- src/mainboard/lenovo/t60/acpi_tables.c | 10 - src/mainboard/lenovo/x60/acpi_tables.c | 10 - src/mainboard/roda/rk886ex/acpi_tables.c | 10 - src/mainboard/roda/rk886ex/dmi.h | 29 --- src/mainboard/via/vt8454c/acpi_tables.c|5 - src/mainboard/via/vt8454c/dmi.h| 29 --- 26 files changed, 605 insertions(+), 302 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 89467db..2cc547a 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -128,6 +128,7 @@ $(obj)/build.h: .xcompile printf "#define COREBOOT_VERSION \"$(KERNELVERSION)\"\n" >> $(obj)/build.ht printf "#define COREBOOT_EXTRA_VERSION \"$(COREBOOT_EXTRA_VERSION)\"\n" >> $(obj)/build.ht printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_DMI_DATE \"`LANG= date +"%m/%d/%Y"`\"\n" >> $(obj)/build.ht printf "\n" >> $(obj)/build.ht printf "#define COREBOOT_COMPILER \"$(shell LANG= $(CC) --version | head -n1)\"\n" >> $(obj)/build.ht printf "#define COREBOOT_ASSEMBLER \"$(shell LANG= $(AS) --version | head -n1)\"\n" >> $(obj)/build.ht diff --git a/src/Kconfig b/src/Kconfig index 7b4f487..f96c903 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -87,7 +87,7 @@ config SCONFIG_GENPARSER help Enable this option if you are working on the sconfig device tree parser and made changes to sconfig.l and - sconfig.y. + sconfig.y. Otherwise, say N. config USE_OPTION_TABLE @@ -304,6 +304,10 @@ config GENERATE_PIRQ_TABLE bool default HAVE_PIRQ_TABLE +config GENERATE_SMBIOS_TABLES + bool + default y + menu "System tables" config WRITE_HIGH_TABLES @@ -342,6 +346,15 @@ config GENERATE_PIRQ_TABLE If unsure, say Y. +config GENERATE_SMBIOS_TABLES + depends on ARCH_X86 + bool "Generate SMBIOS tables" + default y + help + Generate SMBIOS tables for this board. + + If unsure, say Y. + endmenu menu "Payload" diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index d4a377f..3f11c01 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -6,8 +6,10 @@ ramstage-y += tables.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpigen.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S $(obj)/arch/x86/boot/coreboot_table.ramstage.o : $(OPTION_TABLE_H) +$(obj)/arch/x86/boot/smbios.ramstage.o: $(obj)/build.h diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c new file mode 100644 index 000..e5156d9 --- /dev/null +++ b/src/arch/x86/boot/smbios.c @@ -0,0 +1,293 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free
[coreboot] Patch set updated: 92d0649 Add automatic SMBIOS table generation
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/152 -gerrit commit 92d0649385391dace77950191e3146fb1d38e513 Author: Sven Schnelle Date: Sun Aug 14 20:56:34 2011 +0200 Add automatic SMBIOS table generation Change-Id: I0ae16dda8969638a8f70fe1d2e29e992aef3a834 Signed-off-by: Sven Schnelle --- Makefile.inc |1 + src/Kconfig| 15 ++- src/arch/x86/boot/Makefile.inc |2 + src/arch/x86/boot/smbios.c | 293 src/arch/x86/boot/tables.c | 24 ++- src/include/cbmem.h|1 + src/include/device/device.h|6 + src/include/smbios.h | 197 src/lib/cbmem.c|1 + src/mainboard/emulation/qemu-x86/northbridge.c | 72 ++- src/mainboard/getac/p470/acpi_tables.c | 10 - src/mainboard/getac/p470/dmi.h | 31 --- src/mainboard/ibase/mb899/acpi_tables.c| 10 - src/mainboard/ibase/mb899/dmi.h| 29 --- src/mainboard/intel/d945gclf/acpi_tables.c | 10 - src/mainboard/intel/d945gclf/dmi.h | 29 --- src/mainboard/iwave/iWRainbowG6/acpi_tables.c | 10 - src/mainboard/iwave/iWRainbowG6/dmi.h | 34 --- src/mainboard/kontron/986lcd-m/acpi_tables.c | 10 - src/mainboard/kontron/986lcd-m/dmi.h | 29 --- src/mainboard/lenovo/t60/acpi_tables.c | 10 - src/mainboard/lenovo/x60/acpi_tables.c | 10 - src/mainboard/roda/rk886ex/acpi_tables.c | 10 - src/mainboard/roda/rk886ex/dmi.h | 29 --- src/mainboard/via/vt8454c/acpi_tables.c|5 - src/mainboard/via/vt8454c/dmi.h| 29 --- 26 files changed, 605 insertions(+), 302 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 6c51a84..d6f58ed 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -127,6 +127,7 @@ $(obj)/build.h: .xcompile printf "#define COREBOOT_VERSION \"$(KERNELVERSION)\"\n" >> $(obj)/build.ht printf "#define COREBOOT_EXTRA_VERSION \"$(COREBOOT_EXTRA_VERSION)\"\n" >> $(obj)/build.ht printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_DMI_DATE \"`LANG= date +"%m/%d/%Y"`\"\n" >> $(obj)/build.ht printf "\n" >> $(obj)/build.ht printf "#define COREBOOT_COMPILER \"$(shell LANG= $(CC) --version | head -n1)\"\n" >> $(obj)/build.ht printf "#define COREBOOT_ASSEMBLER \"$(shell LANG= $(AS) --version | head -n1)\"\n" >> $(obj)/build.ht diff --git a/src/Kconfig b/src/Kconfig index 7b4f487..f96c903 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -87,7 +87,7 @@ config SCONFIG_GENPARSER help Enable this option if you are working on the sconfig device tree parser and made changes to sconfig.l and - sconfig.y. + sconfig.y. Otherwise, say N. config USE_OPTION_TABLE @@ -304,6 +304,10 @@ config GENERATE_PIRQ_TABLE bool default HAVE_PIRQ_TABLE +config GENERATE_SMBIOS_TABLES + bool + default y + menu "System tables" config WRITE_HIGH_TABLES @@ -342,6 +346,15 @@ config GENERATE_PIRQ_TABLE If unsure, say Y. +config GENERATE_SMBIOS_TABLES + depends on ARCH_X86 + bool "Generate SMBIOS tables" + default y + help + Generate SMBIOS tables for this board. + + If unsure, say Y. + endmenu menu "Payload" diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index d4a377f..3f11c01 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -6,8 +6,10 @@ ramstage-y += tables.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpigen.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S $(obj)/arch/x86/boot/coreboot_table.ramstage.o : $(OPTION_TABLE_H) +$(obj)/arch/x86/boot/smbios.ramstage.o: $(obj)/build.h diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c new file mode 100644 index 000..e5156d9 --- /dev/null +++ b/src/arch/x86/boot/smbios.c @@ -0,0 +1,293 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free
[coreboot] New patch to review: abea90d Add a few more patterns to .gitignore
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/172 -gerrit commit abea90d19c4b6a1120566fc8470fcfd6e8835eab Author: Sven Schnelle Date: Fri Aug 26 21:48:32 2011 +0200 Add a few more patterns to .gitignore Change-Id: If7c1c6d9a96dd788bacee72b6e18a435069cad6e Signed-off-by: Sven Schnelle --- .gitignore |7 +++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/.gitignore b/.gitignore index 78f083c..6ea623e 100644 --- a/.gitignore +++ b/.gitignore @@ -7,3 +7,10 @@ payloads/external/FILO/filo/ payloads/external/SeaBIOS/seabios/ util/crossgcc/tarballs/ util/crossgcc/xgcc/ +*.o +*.elf +*.debug +*.out +*.\# +*.swp +*.bin -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review: a04bb6f Add dirty flag to git describe
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/173 -gerrit commit a04bb6f22eec2673f61fc98c03c224a5f5985b13 Author: Sven Schnelle Date: Fri Aug 26 21:57:53 2011 +0200 Add dirty flag to git describe git describe knows --dirty, which adds -dirty to the verion number if the tree contains uncommited changes. We should add this flag to make it obvious that the COREBOOT_VERSION might be misleading. This is especially important as this version number is now used in the SMBIOS data structures. Change-Id: If4c608c7455e1bbf0cc530c6299fa00eb0fe4d58 Signed-off-by: Sven Schnelle --- Makefile.inc |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index d6f58ed..37e4fb6 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -19,7 +19,7 @@ ### # misleadingly named, this is the coreboot version -export KERNELVERSION := $(shell if [ -d "$(top)/.git" -a -f "`which git`" ]; then git describe; else echo unknown; fi) +export KERNELVERSION := $(shell if [ -d "$(top)/.git" -a -f "`which git`" ]; then git describe --dirty; else echo unknown; fi) ### # Basic component discovery -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review: 81713d0 X60/T60: remove obsolete dmi.h
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/174
-gerrit
commit 81713d0ca03e3b0c0bd9713bd88440776810b0cb
Author: Sven Schnelle
Date: Fri Aug 26 22:18:46 2011 +0200
X60/T60: remove obsolete dmi.h
Change-Id: Id0e8bcc1b93a629f0620b84a060d7ff99a82de78
Signed-off-by: Sven Schnelle
---
src/mainboard/lenovo/t60/dmi.h | 29 -
src/mainboard/lenovo/x60/dmi.h | 29 -
2 files changed, 0 insertions(+), 58 deletions(-)
diff --git a/src/mainboard/lenovo/t60/dmi.h b/src/mainboard/lenovo/t60/dmi.h
deleted file mode 100644
index 96b5873..000
--- a/src/mainboard/lenovo/t60/dmi.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#define DMI_TABLE_SIZE 0x55
-
-static u8 dmi_table[DMI_TABLE_SIZE] = {
- 0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
- 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00,
0x01, 0x00, 0x23, 0x00,
- 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde,
0xcb, 0x7f, 0x00, 0x00,
- 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74,
0x65, 0x6d, 0x73, 0x20,
- 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f,
0x31, 0x33, 0x2f, 0x32,
- 0x30, 0x30, 0x38, 0x00, 0x00
-};
diff --git a/src/mainboard/lenovo/x60/dmi.h b/src/mainboard/lenovo/x60/dmi.h
deleted file mode 100644
index 96b5873..000
--- a/src/mainboard/lenovo/x60/dmi.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#define DMI_TABLE_SIZE 0x55
-
-static u8 dmi_table[DMI_TABLE_SIZE] = {
- 0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
- 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00,
0x01, 0x00, 0x23, 0x00,
- 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde,
0xcb, 0x7f, 0x00, 0x00,
- 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74,
0x65, 0x6d, 0x73, 0x20,
- 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f,
0x31, 0x33, 0x2f, 0x32,
- 0x30, 0x30, 0x38, 0x00, 0x00
-};
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review for coreboot: 6cf3c92 T60: Add support for Ultrabay Legacy I/O devices (40Y8122)
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/282
-gerrit
commit 6cf3c92e3b8d09814af569a4f1a5d64e3c572241
Author: Sven Schnelle
Date: Sat Oct 15 17:31:01 2011 +0200
T60: Add support for Ultrabay Legacy I/O devices (40Y8122)
Those modules have basically the same Super I/O capabilities as
the Docking station. Unfortunately, the Super I/O in the module
shares the same I/O address as the Docking station, so we're not
allowed to connect the LPC Docking Bus if such a module is present.
To be able to detect this device and use it as early console for
coreboot, we have to initialize the GPIO Controller before, as
this device is detected via GPIO06.
Change-Id: If7c38bb6797f76cf28f09f3614ab9a33878571fb
Signed-off-by: Sven Schnelle
---
src/mainboard/lenovo/t60/dock.c | 30 +-
src/mainboard/lenovo/t60/dock.h |3 +++
src/mainboard/lenovo/t60/mainboard.c |7 ++-
src/mainboard/lenovo/t60/mainboard_smi.c |7 ++-
src/mainboard/lenovo/t60/romstage.c | 20 +---
5 files changed, 57 insertions(+), 10 deletions(-)
diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c
index 6642bb3..f0b5a3d 100644
--- a/src/mainboard/lenovo/t60/dock.c
+++ b/src/mainboard/lenovo/t60/dock.c
@@ -28,6 +28,7 @@
#include "dock.h"
#include "superio/nsc/pc87384/pc87384.h"
#include "ec/acpi/ec.h"
+#include "ec/lenovo/pmh7/pmh7.h"
#include "southbridge/intel/i82801gx/i82801gx.h"
static void dlpc_write_register(int reg, int value)
@@ -108,6 +109,9 @@ int dlpc_init(void)
/* Activate DLPC */
dlpc_write_register(0x30, 0x01);
+ /* Reset docking state */
+ outb(0x00, 0x164c);
+
dlpc_gpio_init();
return 0;
}
@@ -127,7 +131,7 @@ static int dock_superio_init(void)
/* set GPIO pins to Serial/Parallel Port
* functions
*/
- dock_write_register(0x22, 0xeb);
+ dock_write_register(0x22, 0xa9);
dock_write_register(0x07, PC87384_GPIO);
dock_write_register(0x60, 0x16);
@@ -217,3 +221,27 @@ int dock_present(void)
return inb(0x15ee) & 1;
}
+static void pmh7_write(int reg, u8 val)
+{
+ outb(reg, EC_LENOVO_PMH7_ADDR);
+ outb(val, EC_LENOVO_PMH7_DATA);
+}
+
+static u8 pmh7_read(int reg)
+{
+ outb(reg, EC_LENOVO_PMH7_ADDR);
+ return inb(EC_LENOVO_PMH7_DATA);
+}
+
+int legacy_io_present(void)
+{
+ return !(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40);
+}
+
+void legacy_io_init(void)
+{
+ /* Enable Power for Ultrabay slot */
+ pmh7_write(0x62, pmh7_read(0x62) & ~0x01);
+ udelay(10);
+ dock_superio_init();
+}
diff --git a/src/mainboard/lenovo/t60/dock.h b/src/mainboard/lenovo/t60/dock.h
index 9d35d9f..631f007 100644
--- a/src/mainboard/lenovo/t60/dock.h
+++ b/src/mainboard/lenovo/t60/dock.h
@@ -24,4 +24,7 @@ extern int dock_connect(void);
extern void dock_disconnect(void);
extern int dock_present(void);
extern int dlpc_init(void);
+
+extern int legacy_io_present(void);
+extern void legacy_io_init(void);
#endif
diff --git a/src/mainboard/lenovo/t60/mainboard.c
b/src/mainboard/lenovo/t60/mainboard.c
index 2b8c5fe..5da6318 100644
--- a/src/mainboard/lenovo/t60/mainboard.c
+++ b/src/mainboard/lenovo/t60/mainboard.c
@@ -50,7 +50,12 @@ static void mainboard_enable(device_t dev)
ec_write(0x0c, 0xc7);
idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1));
- if (idedev && idedev->chip_info && h8_ultrabay_device_present()) {
+
+ if (!(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40)) {
+ /* legacy I/O connected */
+ pmh7_ultrabay_power_enable(1);
+ ec_write(0x0c, 0x84);
+ } else if (idedev && idedev->chip_info && h8_ultrabay_device_present())
{
struct southbridge_intel_i82801gx_config *config =
idedev->chip_info;
config->ide_enable_primary = 1;
pmh7_ultrabay_power_enable(1);
diff --git a/src/mainboard/lenovo/t60/mainboard_smi.c
b/src/mainboard/lenovo/t60/mainboard_smi.c
index 4a0b506..2ab1d4d 100644
--- a/src/mainboard/lenovo/t60/mainboard_smi.c
+++ b/src/mainboard/lenovo/t60/mainboard_smi.c
@@ -75,7 +75,12 @@ int mainboard_io_trap_handler(int smif)
switch (smif) {
case SMI_DOCK_CONNECT:
- dlpc_init();
+ /* If there's an legacy I/O module present, we're not
+ allowed to connect the Docking LPC Bus, as both Super I/O
+ chips are using 0x2e as base address. */
+ if (legacy_io_present())
+ break;
+
if (!dock_connect()) {
/* set dock LED to indicate status */
[coreboot] Patch set updated for coreboot: f8d44a0 T60: Add support for Ultrabay Legacy I/O devices (40Y8122)
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/282
-gerrit
commit f8d44a08ac615fdc2ea680c187bb556e330663cc
Author: Sven Schnelle
Date: Sat Oct 15 17:31:01 2011 +0200
T60: Add support for Ultrabay Legacy I/O devices (40Y8122)
Those modules have basically the same Super I/O capabilities as
the Docking station. Unfortunately, the Super I/O in the module
shares the same I/O address as the Docking station, so we're not
allowed to connect the LPC Docking Bus if such a module is present.
To be able to detect this device and use it as early console for
coreboot, we have to initialize the GPIO Controller before, as
this device is detected via GPIO06.
Change-Id: If7c38bb6797f76cf28f09f3614ab9a33878571fb
Signed-off-by: Sven Schnelle
---
src/mainboard/lenovo/t60/dock.c | 49 +++--
src/mainboard/lenovo/t60/dock.h |3 ++
src/mainboard/lenovo/t60/mainboard.c | 11 +-
src/mainboard/lenovo/t60/mainboard_smi.c |8 -
src/mainboard/lenovo/t60/romstage.c | 21
5 files changed, 72 insertions(+), 20 deletions(-)
diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c
index 6642bb3..b37c2bf 100644
--- a/src/mainboard/lenovo/t60/dock.c
+++ b/src/mainboard/lenovo/t60/dock.c
@@ -28,8 +28,11 @@
#include "dock.h"
#include "superio/nsc/pc87384/pc87384.h"
#include "ec/acpi/ec.h"
+#include "ec/lenovo/pmh7/pmh7.h"
#include "southbridge/intel/i82801gx/i82801gx.h"
+#define DLPC_CONTROL 0x164c
+
static void dlpc_write_register(int reg, int value)
{
outb(reg, 0x164e);
@@ -102,12 +105,15 @@ int dlpc_init(void)
/* Select DLPC module */
dlpc_write_register(0x07, 0x19);
- /* DLPC Base Address 0x164c */
- dlpc_write_register(0x60, 0x16);
- dlpc_write_register(0x61, 0x4c);
+ /* DLPC Base Address */
+ dlpc_write_register(0x60, (DLPC_CONTROL >> 8) & 0xff);
+ dlpc_write_register(0x61, DLPC_CONTROL & 0xff);
/* Activate DLPC */
dlpc_write_register(0x30, 0x01);
+ /* Reset docking state */
+ outb(0x00, DLPC_CONTROL);
+
dlpc_gpio_init();
return 0;
}
@@ -127,7 +133,7 @@ static int dock_superio_init(void)
/* set GPIO pins to Serial/Parallel Port
* functions
*/
- dock_write_register(0x22, 0xeb);
+ dock_write_register(0x22, 0xa9);
dock_write_register(0x07, PC87384_GPIO);
dock_write_register(0x60, 0x16);
@@ -179,16 +185,16 @@ int dock_connect(void)
{
int timeout = 1000;
- outb(0x07, 0x164c);
+ outb(0x07, DLPC_CONTROL);
timeout = 1000;
- while(!(inb(0x164c) & 8) && timeout--)
+ while(!(inb(DLPC_CONTROL) & 8) && timeout--)
udelay(1000);
if (!timeout) {
/* docking failed, disable DLPC switch */
- outb(0x00, 0x164c);
+ outb(0x00, DLPC_CONTROL);
dlpc_write_register(0x30, 0x00);
return 1;
}
@@ -206,14 +212,37 @@ int dock_connect(void)
void dock_disconnect(void)
{
/* disconnect LPC bus */
- outb(0x00, 0x164c);
+ outb(0x00, DLPC_CONTROL);
/* Assert PLTRST and DLPCPD */
outb(0xfc, 0x1680);
}
+static void pmh7_write(int reg, u8 val)
+{
+ outb(reg, EC_LENOVO_PMH7_ADDR);
+ outb(val, EC_LENOVO_PMH7_DATA);
+}
+
+static u8 pmh7_read(int reg)
+{
+ outb(reg, EC_LENOVO_PMH7_ADDR);
+ return inb(EC_LENOVO_PMH7_DATA);
+}
+
int dock_present(void)
{
- outb(0x61, 0x15ec);
- return inb(0x15ee) & 1;
+ return pmh7_read(0x61) & 1;
}
+int legacy_io_present(void)
+{
+ return !(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40);
+}
+
+void legacy_io_init(void)
+{
+ /* Enable Power for Ultrabay slot */
+ pmh7_write(0x62, pmh7_read(0x62) & ~0x01);
+ udelay(10);
+ dock_superio_init();
+}
diff --git a/src/mainboard/lenovo/t60/dock.h b/src/mainboard/lenovo/t60/dock.h
index 9d35d9f..631f007 100644
--- a/src/mainboard/lenovo/t60/dock.h
+++ b/src/mainboard/lenovo/t60/dock.h
@@ -24,4 +24,7 @@ extern int dock_connect(void);
extern void dock_disconnect(void);
extern int dock_present(void);
extern int dlpc_init(void);
+
+extern int legacy_io_present(void);
+extern void legacy_io_init(void);
#endif
diff --git a/src/mainboard/lenovo/t60/mainboard.c
b/src/mainboard/lenovo/t60/mainboard.c
index 2b8c5fe..8456992 100644
--- a/src/mainboard/lenovo/t60/mainboard.c
+++ b/src/mainboard/lenovo/t60/mainboard.c
@@ -38,6 +38,7 @@
static void mainboard_enable(device_t dev)
{
+ struct southbridge_intel_i82801gx_config *config;
device_t dev0, idedev;
u8 defaults_loaded = 0;
@@ -50,8 +51,14 @@ static
[coreboot] Patch set updated for coreboot: 96a5f64 T60: Add support for Ultrabay Legacy I/O devices (40Y8122)
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/282
-gerrit
commit 96a5f648daea651fe427e66c62b31373a3688b38
Author: Sven Schnelle
Date: Sat Oct 15 17:31:01 2011 +0200
T60: Add support for Ultrabay Legacy I/O devices (40Y8122)
Those modules have basically the same Super I/O capabilities as
the Docking station. Unfortunately, the Super I/O in the module
shares the same I/O address as the Docking station, so we're not
allowed to connect the LPC Docking Bus if such a module is present.
To be able to detect this device and use it as early console for
coreboot, we have to initialize the GPIO Controller before, as
this device is detected via GPIO06.
Change-Id: If7c38bb6797f76cf28f09f3614ab9a33878571fb
Signed-off-by: Sven Schnelle
---
src/ec/lenovo/pmh7/pmh7.c|4 +++
src/mainboard/lenovo/t60/Makefile.inc|4 +-
src/mainboard/lenovo/t60/dock.c | 37 +
src/mainboard/lenovo/t60/dock.h |3 ++
src/mainboard/lenovo/t60/mainboard.c | 11 +++-
src/mainboard/lenovo/t60/mainboard_smi.c |8 +-
src/mainboard/lenovo/t60/romstage.c | 21 +++-
7 files changed, 66 insertions(+), 22 deletions(-)
diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c
index 30460c9..844e233 100644
--- a/src/ec/lenovo/pmh7/pmh7.c
+++ b/src/ec/lenovo/pmh7/pmh7.c
@@ -91,6 +91,8 @@ void pmh7_register_write(int reg, int val)
outb(val, EC_LENOVO_PMH7_DATA);
}
+#ifndef __PRE_RAM__
+#ifndef __SMM__
static void enable_dev(device_t dev)
{
struct ec_lenovo_pmh7_config *conf = dev->chip_info;
@@ -115,3 +117,5 @@ struct chip_operations ec_lenovo_pmh7_ops = {
CHIP_NAME("Lenovo Power Management Hardware Hub 7")
.enable_dev = enable_dev,
};
+#endif
+#endif
diff --git a/src/mainboard/lenovo/t60/Makefile.inc
b/src/mainboard/lenovo/t60/Makefile.inc
index 7515258..f86afd1 100644
--- a/src/mainboard/lenovo/t60/Makefile.inc
+++ b/src/mainboard/lenovo/t60/Makefile.inc
@@ -17,5 +17,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c dock.c
-romstage-y += dock.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c dock.c
../../../ec/lenovo/pmh7/pmh7.c
+romstage-y += dock.c ../../../ec/lenovo/pmh7/pmh7.c
diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c
index 6642bb3..5cd8997 100644
--- a/src/mainboard/lenovo/t60/dock.c
+++ b/src/mainboard/lenovo/t60/dock.c
@@ -28,8 +28,11 @@
#include "dock.h"
#include "superio/nsc/pc87384/pc87384.h"
#include "ec/acpi/ec.h"
+#include "ec/lenovo/pmh7/pmh7.h"
#include "southbridge/intel/i82801gx/i82801gx.h"
+#define DLPC_CONTROL 0x164c
+
static void dlpc_write_register(int reg, int value)
{
outb(reg, 0x164e);
@@ -102,12 +105,15 @@ int dlpc_init(void)
/* Select DLPC module */
dlpc_write_register(0x07, 0x19);
- /* DLPC Base Address 0x164c */
- dlpc_write_register(0x60, 0x16);
- dlpc_write_register(0x61, 0x4c);
+ /* DLPC Base Address */
+ dlpc_write_register(0x60, (DLPC_CONTROL >> 8) & 0xff);
+ dlpc_write_register(0x61, DLPC_CONTROL & 0xff);
/* Activate DLPC */
dlpc_write_register(0x30, 0x01);
+ /* Reset docking state */
+ outb(0x00, DLPC_CONTROL);
+
dlpc_gpio_init();
return 0;
}
@@ -127,7 +133,7 @@ static int dock_superio_init(void)
/* set GPIO pins to Serial/Parallel Port
* functions
*/
- dock_write_register(0x22, 0xeb);
+ dock_write_register(0x22, 0xa9);
dock_write_register(0x07, PC87384_GPIO);
dock_write_register(0x60, 0x16);
@@ -179,16 +185,16 @@ int dock_connect(void)
{
int timeout = 1000;
- outb(0x07, 0x164c);
+ outb(0x07, DLPC_CONTROL);
timeout = 1000;
- while(!(inb(0x164c) & 8) && timeout--)
+ while(!(inb(DLPC_CONTROL) & 8) && timeout--)
udelay(1000);
if (!timeout) {
/* docking failed, disable DLPC switch */
- outb(0x00, 0x164c);
+ outb(0x00, DLPC_CONTROL);
dlpc_write_register(0x30, 0x00);
return 1;
}
@@ -206,14 +212,25 @@ int dock_connect(void)
void dock_disconnect(void)
{
/* disconnect LPC bus */
- outb(0x00, 0x164c);
+ outb(0x00, DLPC_CONTROL);
/* Assert PLTRST and DLPCPD */
outb(0xfc, 0x1680);
}
int dock_present(void)
{
- outb(0x61, 0x15ec);
- return inb(0x15ee) & 1;
+ return pmh7_register_read(0x61) & 1;
+}
+
+int legacy_io_present(void)
+{
+ return !(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40);
}
+void lega
[coreboot] New patch to review for coreboot: 210dced I945: replace #ifdef defined by #if
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/293 -gerrit commit 210dcedf6e7afd2d46976a21adcfce92747789fe Author: Sven Schnelle Date: Tue Oct 18 07:58:10 2011 +0200 I945: replace #ifdef defined by #if config.h defines also unset config options (as "0") so #ifdef matches both settings, which isn't what we want. Change-Id: I694e1b8a8ec4c20225d7af1a13a2a336f900e643 Signed-off-by: Sven Schnelle --- src/northbridge/intel/i945/early_init.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 197c58f..14c66c4 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -91,7 +91,7 @@ static void i945m_detect_chipset(void) printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ } printk(BIOS_DEBUG, "\n"); -#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) +#if CONFIG_NORTHBRIDGE_INTEL_I945GC printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); #endif } @@ -140,7 +140,7 @@ static void i945_detect_chipset(void) printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ } printk(BIOS_DEBUG, "\n"); -#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) +#if CONFIG_NORTHBRIDGE_INTEL_I945GM printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); #endif } -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch set updated for coreboot: d088d0d I945: replace #if defined() by #if
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/293 -gerrit commit d088d0d4acbd8e3b0c6c410aed9ed5bde2018cd5 Author: Sven Schnelle Date: Tue Oct 18 07:58:10 2011 +0200 I945: replace #if defined() by #if config.h defines also unset config options (as "0") so #ifdef matches both settings, which isn't what we want. Change-Id: I694e1b8a8ec4c20225d7af1a13a2a336f900e643 Signed-off-by: Sven Schnelle --- src/northbridge/intel/i945/early_init.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 197c58f..14c66c4 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -91,7 +91,7 @@ static void i945m_detect_chipset(void) printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ } printk(BIOS_DEBUG, "\n"); -#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) +#if CONFIG_NORTHBRIDGE_INTEL_I945GC printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); #endif } @@ -140,7 +140,7 @@ static void i945_detect_chipset(void) printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ } printk(BIOS_DEBUG, "\n"); -#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) +#if CONFIG_NORTHBRIDGE_INTEL_I945GM printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); #endif } -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch set updated for coreboot: ec8dd51 T60: Add support for Ultrabay Legacy I/O devices (40Y8122)
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/282
-gerrit
commit ec8dd51ce7df16ddca1d834b97f67be830683ce4
Author: Sven Schnelle
Date: Sat Oct 15 17:31:01 2011 +0200
T60: Add support for Ultrabay Legacy I/O devices (40Y8122)
Those modules have basically the same Super I/O capabilities as
the Docking station. Unfortunately, the Super I/O in the module
shares the same I/O address as the Docking station, so we're not
allowed to connect the LPC Docking Bus if such a module is present.
To be able to detect this device and use it as early console for
coreboot, we have to initialize the GPIO Controller before, as
this device is detected via GPIO06.
Change-Id: If7c38bb6797f76cf28f09f3614ab9a33878571fb
Signed-off-by: Sven Schnelle
---
src/ec/lenovo/pmh7/Makefile.inc |2 +
src/ec/lenovo/pmh7/pmh7.c|4 +++
src/mainboard/lenovo/t60/dock.c | 37 +
src/mainboard/lenovo/t60/dock.h |3 ++
src/mainboard/lenovo/t60/mainboard.c | 11 +++-
src/mainboard/lenovo/t60/mainboard_smi.c |8 +-
src/mainboard/lenovo/t60/romstage.c | 21 +++-
7 files changed, 66 insertions(+), 20 deletions(-)
diff --git a/src/ec/lenovo/pmh7/Makefile.inc b/src/ec/lenovo/pmh7/Makefile.inc
index 4c891b2..e441980 100644
--- a/src/ec/lenovo/pmh7/Makefile.inc
+++ b/src/ec/lenovo/pmh7/Makefile.inc
@@ -1 +1,3 @@
driver-y += pmh7.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += pmh7.c
+romstage-y += pmh7.c
diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c
index 30460c9..844e233 100644
--- a/src/ec/lenovo/pmh7/pmh7.c
+++ b/src/ec/lenovo/pmh7/pmh7.c
@@ -91,6 +91,8 @@ void pmh7_register_write(int reg, int val)
outb(val, EC_LENOVO_PMH7_DATA);
}
+#ifndef __PRE_RAM__
+#ifndef __SMM__
static void enable_dev(device_t dev)
{
struct ec_lenovo_pmh7_config *conf = dev->chip_info;
@@ -115,3 +117,5 @@ struct chip_operations ec_lenovo_pmh7_ops = {
CHIP_NAME("Lenovo Power Management Hardware Hub 7")
.enable_dev = enable_dev,
};
+#endif
+#endif
diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c
index 6642bb3..5cd8997 100644
--- a/src/mainboard/lenovo/t60/dock.c
+++ b/src/mainboard/lenovo/t60/dock.c
@@ -28,8 +28,11 @@
#include "dock.h"
#include "superio/nsc/pc87384/pc87384.h"
#include "ec/acpi/ec.h"
+#include "ec/lenovo/pmh7/pmh7.h"
#include "southbridge/intel/i82801gx/i82801gx.h"
+#define DLPC_CONTROL 0x164c
+
static void dlpc_write_register(int reg, int value)
{
outb(reg, 0x164e);
@@ -102,12 +105,15 @@ int dlpc_init(void)
/* Select DLPC module */
dlpc_write_register(0x07, 0x19);
- /* DLPC Base Address 0x164c */
- dlpc_write_register(0x60, 0x16);
- dlpc_write_register(0x61, 0x4c);
+ /* DLPC Base Address */
+ dlpc_write_register(0x60, (DLPC_CONTROL >> 8) & 0xff);
+ dlpc_write_register(0x61, DLPC_CONTROL & 0xff);
/* Activate DLPC */
dlpc_write_register(0x30, 0x01);
+ /* Reset docking state */
+ outb(0x00, DLPC_CONTROL);
+
dlpc_gpio_init();
return 0;
}
@@ -127,7 +133,7 @@ static int dock_superio_init(void)
/* set GPIO pins to Serial/Parallel Port
* functions
*/
- dock_write_register(0x22, 0xeb);
+ dock_write_register(0x22, 0xa9);
dock_write_register(0x07, PC87384_GPIO);
dock_write_register(0x60, 0x16);
@@ -179,16 +185,16 @@ int dock_connect(void)
{
int timeout = 1000;
- outb(0x07, 0x164c);
+ outb(0x07, DLPC_CONTROL);
timeout = 1000;
- while(!(inb(0x164c) & 8) && timeout--)
+ while(!(inb(DLPC_CONTROL) & 8) && timeout--)
udelay(1000);
if (!timeout) {
/* docking failed, disable DLPC switch */
- outb(0x00, 0x164c);
+ outb(0x00, DLPC_CONTROL);
dlpc_write_register(0x30, 0x00);
return 1;
}
@@ -206,14 +212,25 @@ int dock_connect(void)
void dock_disconnect(void)
{
/* disconnect LPC bus */
- outb(0x00, 0x164c);
+ outb(0x00, DLPC_CONTROL);
/* Assert PLTRST and DLPCPD */
outb(0xfc, 0x1680);
}
int dock_present(void)
{
- outb(0x61, 0x15ec);
- return inb(0x15ee) & 1;
+ return pmh7_register_read(0x61) & 1;
+}
+
+int legacy_io_present(void)
+{
+ return !(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40);
}
+void legacy_io_init(void)
+{
+ /* Enable Power for Ultrabay slot */
+ pmh7_ultrabay_power_enable(1);
+ udelay(10);
+ dock_superio_init();
+}
diff --git a/src/mainboard/lenovo/t60/dock.h b/src/mainboard/lenovo/t60/dock.h
index 9d35d9f..6
[coreboot] New patch to review for coreboot: eb4ee22 ACPI: Add function for writing _CST tables
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/312
-gerrit
commit eb4ee22546fdf69fcfc4fc4d4f4ed883fda09c5c
Author: Sven Schnelle
Date: Fri Oct 21 21:46:47 2011 +0200
ACPI: Add function for writing _CST tables
Change-Id: I4e16a0d37717c56a3529f9f9fdb05efec1d93f99
Signed-off-by: Sven Schnelle
---
src/arch/x86/boot/acpigen.c | 59 +++
src/arch/x86/include/arch/acpigen.h | 14
2 files changed, 73 insertions(+), 0 deletions(-)
diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c
index e8cd724..672548a 100644
--- a/src/arch/x86/boot/acpigen.c
+++ b/src/arch/x86/boot/acpigen.c
@@ -374,6 +374,42 @@ int acpigen_write_PSD_package(u32 domain, u32 numprocs,
PSD_coord coordtype)
return len + lenh;
}
+static int acpigen_write_CST_package_entry(struct cst_entry *entry)
+{
+ int len, len0;
+ char *start, *end;
+
+ len0 = acpigen_write_package(4);
+ len = acpigen_write_resourcetemplate_header();
+ start = acpigen_get_current();
+ acpigen_write_register(entry->type, entry->width, entry->offset,
+ entry->addrsize, entry->address);
+ end = acpigen_get_current();
+ len += end-start;
+ len += acpigen_write_resourcetemplate_footer(len);
+ len += len0;
+ len += acpigen_write_dword(entry->ctype);
+ len += acpigen_write_dword(entry->latency);
+ len += acpigen_write_dword(entry->power);
+ acpigen_patch_len(len - 1);
+ return len;
+}
+
+int acpigen_write_CST_package(struct cst_entry *entry, int nentries)
+{
+ int len, lenh, lenp, i;
+ lenh = acpigen_write_name("_CST");
+ lenp = acpigen_write_package(nentries+1);
+ len = acpigen_write_dword(nentries);
+
+ for (i = 0; i < nentries; i++)
+ len += acpigen_write_CST_package_entry(entry + i);
+
+ len += lenp;
+ acpigen_patch_len(len - 1);
+ return len + lenh;
+}
+
int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size)
{
/*
@@ -399,6 +435,29 @@ int acpigen_write_mem32fixed(int readwrite, u32 base, u32
size)
return 12;
}
+int acpigen_write_register(int type, int width, int offset,
+ int addrsize, u64 address)
+{
+ acpigen_emit_byte(0x82);
+ /* Byte 1+2: length (0x000c) */
+ acpigen_emit_byte(0x0c);
+ acpigen_emit_byte(0x00);
+ /* bit1-7 are ignored */
+ acpigen_emit_byte(type); /* FFixedHW */
+ acpigen_emit_byte(width); /* register width */
+ acpigen_emit_byte(offset); /* register offset */
+ acpigen_emit_byte(addrsize); /* register address size */
+ acpigen_emit_byte(address & 0xff); /* register address 0-7 */
+ acpigen_emit_byte((address >> 8) & 0xff); /* register address 8-15 */
+ acpigen_emit_byte((address >> 16) & 0xff); /* register address 16-23 */
+ acpigen_emit_byte((address >> 24) & 0xff); /* register address 24-31 */
+ acpigen_emit_byte((address >> 32) & 0xff); /* register address 32-39 */
+ acpigen_emit_byte((address >> 40) & 0xff); /* register address 40-47 */
+ acpigen_emit_byte((address >> 48) & 0xff); /* register address 48-55 */
+ acpigen_emit_byte((address >> 56) & 0xff); /* register address 56-63 */
+ return 15;
+}
+
int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16)
{
/*
diff --git a/src/arch/x86/include/arch/acpigen.h
b/src/arch/x86/include/arch/acpigen.h
index 6f13a7a..7ba16bc 100644
--- a/src/arch/x86/include/arch/acpigen.h
+++ b/src/arch/x86/include/arch/acpigen.h
@@ -24,6 +24,17 @@
#include
#include
+struct cst_entry {
+ int type;
+ int width;
+ int offset;
+ int addrsize;
+ u64 address;
+ int ctype;
+ int latency;
+ int power;
+};
+
void acpigen_patch_len(int len);
void acpigen_set_current(char *curr);
char *acpigen_get_current(void);
@@ -45,9 +56,12 @@ int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32
transLat, u32 busmLat
u32 control, u32 status);
typedef enum { SW_ALL=0xfc, SW_ANY=0xfd, HW_ALL=0xfe } PSD_coord;
int acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype);
+int acpigen_write_CST_package(struct cst_entry *entry, int nentries);
int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len);
int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size);
int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16);
+int acpigen_write_register(int type, int width, int offset,
+ int addrsize, u64 address);
int acpigen_write_resourcetemplate_header(void);
int acpigen_write_resourcetemplate_footer(int len);
int acpigen_write_mainb
[coreboot] New patch to review for coreboot: 19f00e2 SPEEDSTEP: write _CST tables
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/321
-gerrit
commit 19f00e23b849da4df905052e0c56aabd3b99836d
Author: Sven Schnelle
Date: Sat Oct 22 13:41:16 2011 +0200
SPEEDSTEP: write _CST tables
Change-Id: Idb4b57044808918de343d31519768d0986840f01
Signed-off-by: Sven Schnelle
---
src/arch/x86/include/arch/acpigen.h |2 ++
src/cpu/intel/speedstep/acpi.c | 10 ++
2 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/src/arch/x86/include/arch/acpigen.h
b/src/arch/x86/include/arch/acpigen.h
index 7feaa8e..0833371 100644
--- a/src/arch/x86/include/arch/acpigen.h
+++ b/src/arch/x86/include/arch/acpigen.h
@@ -66,4 +66,6 @@ int acpigen_write_resourcetemplate_footer(int len);
int acpigen_write_mainboard_resource_template(void);
int acpigen_write_mainboard_resources(const char *scope, const char *name);
+int get_cst_entries(struct cst_entry **) __attribute__((weak));
+
#endif
diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index 48e1a3c..8f32e4f 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -62,6 +62,11 @@ static int get_fsb(void)
return 200;
}
+int get_cst_entries(struct cst_entry **entries __attribute__((unused)))
+{
+ return 0;
+}
+
void generate_cpu_entries(void)
{
int len_pr, len_ps;
@@ -70,6 +75,9 @@ void generate_cpu_entries(void)
int totalcores = determine_total_number_of_cores();
int cores_per_package = (cpuid_ebx(1)>>16) & 0xff;
int numcpus = totalcores/cores_per_package; // this assumes that all
CPUs share the same layout
+ int count;
+ struct cst_entry *cst_entries;
+
printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus,
cores_per_package);
for (cpuID=1; cpuID <=numcpus; cpuID++) {
@@ -81,6 +89,8 @@ void generate_cpu_entries(void)
len_pr =
acpigen_write_processor((cpuID-1)*cores_per_package+coreID-1, pcontrol_blk,
plen);
len_pr += acpigen_write_empty_PCT();
len_pr +=
acpigen_write_PSD_package(cpuID-1,cores_per_package,SW_ANY);
+ if ((count = get_cst_entries(&cst_entries)) > 0)
+ len_pr +=
acpigen_write_CST_package(cst_entries, count);
len_pr += acpigen_write_name("_PSS");
int max_states=8;
--
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[coreboot] New patch to review for coreboot: 9578124 T60: add _CST table
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/322
-gerrit
commit 9578124b3da94c73c388da0a7ef9da93a44a8374
Author: Sven Schnelle
Date: Sat Oct 22 13:41:28 2011 +0200
T60: add _CST table
Only enable C1/C2 for now. (C3 currently freezes the system)
Change-Id: I02c6b10762245bc48f21a341286236e203421de0
Signed-off-by: Sven Schnelle
---
src/mainboard/lenovo/t60/mainboard.c | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/lenovo/t60/mainboard.c
b/src/mainboard/lenovo/t60/mainboard.c
index 8456992..8f5404b 100644
--- a/src/mainboard/lenovo/t60/mainboard.c
+++ b/src/mainboard/lenovo/t60/mainboard.c
@@ -35,6 +35,18 @@
#include
#include
#include
+#include
+
+static struct cst_entry cst_entries[] = {
+ { 0x7f, 1, 2, 0, 1, 1, 1, 1000 },
+ { 0x01, 8, 0, 0, 0x514, 2, 1, 500 },
+};
+
+int get_cst_entries(struct cst_entry **entries)
+{
+ *entries = cst_entries;
+ return ARRAY_SIZE(cst_entries);
+}
static void mainboard_enable(device_t dev)
{
--
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[coreboot] Patch set updated for coreboot: 2abcc17 ACPI: Add function for writing _CST tables
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/312
-gerrit
commit 2abcc17587a4faac6950ee04b68c532d0fefa8c9
Author: Sven Schnelle
Date: Fri Oct 21 21:46:47 2011 +0200
ACPI: Add function for writing _CST tables
Change-Id: I4e16a0d37717c56a3529f9f9fdb05efec1d93f99
Signed-off-by: Sven Schnelle
---
src/arch/x86/boot/acpigen.c | 57 +++
src/arch/x86/include/arch/acpigen.h | 13
2 files changed, 70 insertions(+), 0 deletions(-)
diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c
index e8cd724..7dc7fed 100644
--- a/src/arch/x86/boot/acpigen.c
+++ b/src/arch/x86/boot/acpigen.c
@@ -374,6 +374,41 @@ int acpigen_write_PSD_package(u32 domain, u32 numprocs,
PSD_coord coordtype)
return len + lenh;
}
+static int acpigen_write_CST_package_entry(struct cst_entry *entry)
+{
+ int len, len0;
+ char *start, *end;
+
+ len0 = acpigen_write_package(4);
+ len = acpigen_write_resourcetemplate_header();
+ start = acpigen_get_current();
+ acpigen_write_register(entry->type, entry->width, entry->offset,
entry->addrsize, entry->address);
+ end = acpigen_get_current();
+ len += end-start;
+ len += acpigen_write_resourcetemplate_footer(len);
+ len += len0;
+ len += acpigen_write_dword(entry->ctype);
+ len += acpigen_write_dword(entry->latency);
+ len += acpigen_write_dword(entry->power);
+ acpigen_patch_len(len - 1);
+ return len;
+}
+
+int acpigen_write_CST_package(struct cst_entry *entry, int nentries)
+{
+ int len, lenh, lenp, i;
+ lenh = acpigen_write_name("_CST");
+ lenp = acpigen_write_package(nentries+1);
+ len = acpigen_write_dword(nentries);
+
+ for (i = 0; i < nentries; i++)
+ len += acpigen_write_CST_package_entry(entry + i);
+
+ len += lenp;
+ acpigen_patch_len(len - 1);
+ return len + lenh;
+}
+
int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size)
{
/*
@@ -399,6 +434,28 @@ int acpigen_write_mem32fixed(int readwrite, u32 base, u32
size)
return 12;
}
+int acpigen_write_register(int type, int width, int offset, int addrsize, u64
address)
+{
+ acpigen_emit_byte(0x82);
+ /* Byte 1+2: length (0x000c) */
+ acpigen_emit_byte(0x0c);
+ acpigen_emit_byte(0x00);
+ /* bit1-7 are ignored */
+ acpigen_emit_byte(type); /* FFixedHW */
+ acpigen_emit_byte(width); /* register width */
+ acpigen_emit_byte(offset); /* register offset */
+ acpigen_emit_byte(addrsize); /* register address size */
+ acpigen_emit_byte(address & 0xff); /* register address 0-7 */
+ acpigen_emit_byte((address >> 8) & 0xff); /* register address 8-15 */
+ acpigen_emit_byte((address >> 16) & 0xff); /* register address 16-23 */
+ acpigen_emit_byte((address >> 24) & 0xff); /* register address 24-31 */
+ acpigen_emit_byte((address >> 32) & 0xff); /* register address 32-39 */
+ acpigen_emit_byte((address >> 40) & 0xff); /* register address 40-47 */
+ acpigen_emit_byte((address >> 48) & 0xff); /* register address 48-55 */
+ acpigen_emit_byte((address >> 56) & 0xff); /* register address 56-63 */
+ return 15;
+}
+
int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16)
{
/*
diff --git a/src/arch/x86/include/arch/acpigen.h
b/src/arch/x86/include/arch/acpigen.h
index 6f13a7a..7feaa8e 100644
--- a/src/arch/x86/include/arch/acpigen.h
+++ b/src/arch/x86/include/arch/acpigen.h
@@ -24,6 +24,17 @@
#include
#include
+struct cst_entry {
+ int type;
+ int width;
+ int offset;
+ int addrsize;
+ u64 address;
+ int ctype;
+ int latency;
+ int power;
+};
+
void acpigen_patch_len(int len);
void acpigen_set_current(char *curr);
char *acpigen_get_current(void);
@@ -45,9 +56,11 @@ int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32
transLat, u32 busmLat
u32 control, u32 status);
typedef enum { SW_ALL=0xfc, SW_ANY=0xfd, HW_ALL=0xfe } PSD_coord;
int acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype);
+int acpigen_write_CST_package(struct cst_entry *entry, int nentries);
int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len);
int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size);
int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16);
+int acpigen_write_register(int type, int width, int offset, int addrsize, u64
address);
int acpigen_write_resourcetemplate_header(void);
int acpigen_write_resourcetemplate_footer(int len);
int acpigen_write_mainboard_resource_template(void);
--
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[coreboot] Patch set updated for coreboot: ccc50c9 T60: add _CST table
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/322
-gerrit
commit ccc50c99ded88cb0be633836e19eade3c8686fde
Author: Sven Schnelle
Date: Sat Oct 22 13:41:28 2011 +0200
T60: add _CST table
Only enable C1/C2 for now. (C3 currently freezes the system)
Change-Id: I02c6b10762245bc48f21a341286236e203421de0
Signed-off-by: Sven Schnelle
---
src/mainboard/lenovo/t60/mainboard.c | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/lenovo/t60/mainboard.c
b/src/mainboard/lenovo/t60/mainboard.c
index 8456992..0ee9749 100644
--- a/src/mainboard/lenovo/t60/mainboard.c
+++ b/src/mainboard/lenovo/t60/mainboard.c
@@ -35,6 +35,18 @@
#include
#include
#include
+#include
+
+static struct cst_entry cst_entries[] = {
+ { 0x7f, 1, 2, 0, 1, 1, 1, 1000 },
+ { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 2, 1, 500 },
+};
+
+int get_cst_entries(struct cst_entry **entries)
+{
+ *entries = cst_entries;
+ return ARRAY_SIZE(cst_entries);
+}
static void mainboard_enable(device_t dev)
{
--
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[coreboot] New patch to review for coreboot: 5d681e0 i82801gx: Don't set I/O base address to static value
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/325
-gerrit
commit 5d681e0c15ea595292bd9c40d47691cd153aea34
Author: Sven Schnelle
Date: Sun Oct 23 15:30:29 2011 +0200
i82801gx: Don't set I/O base address to static value
Doing it this way will break all subsequent smbus calls, because
the smbus code still uses res->base, which points to the old base
address.
Change-Id: I0f3d8fba5f8e2db7fe4ca991ef2c345aff436ea4
Signed-off-by: Sven Schnelle
---
src/southbridge/intel/i82801gx/smbus.c | 14 --
1 files changed, 0 insertions(+), 14 deletions(-)
diff --git a/src/southbridge/intel/i82801gx/smbus.c
b/src/southbridge/intel/i82801gx/smbus.c
index 834f310..184120f 100644
--- a/src/southbridge/intel/i82801gx/smbus.c
+++ b/src/southbridge/intel/i82801gx/smbus.c
@@ -29,19 +29,6 @@
#include "i82801gx.h"
#include "smbus.h"
-#define SMB_BASE 0x20
-static void smbus_init(struct device *dev)
-{
- u32 smb_base;
-
- smb_base = pci_read_config32(dev, SMB_BASE);
- printk(BIOS_DEBUG, "Initializing SMBus device:\n");
- printk(BIOS_DEBUG, " Old SMBUS Base Address: 0x%04x\n", smb_base);
- pci_write_config32(dev, SMB_BASE, 0x0401);
- smb_base = pci_read_config32(dev, SMB_BASE);
- printk(BIOS_DEBUG, " New SMBUS Base Address: 0x%04x\n", smb_base);
-}
-
static int lsmbus_read_byte(device_t dev, u8 address)
{
u16 device;
@@ -78,7 +65,6 @@ static struct device_operations smbus_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .init = smbus_init,
.scan_bus = scan_static_bus,
.enable = i82801gx_enable,
.ops_smbus_bus = &lops_smbus_bus,
--
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[coreboot] New patch to review for coreboot: a794ed2 i82801gx: Add write and read/write block functions
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/326
-gerrit
commit a794ed2cd94cfbc2b519d913591801e0633fa48a
Author: Sven Schnelle
Date: Sun Oct 23 15:36:15 2011 +0200
i82801gx: Add write and read/write block functions
Change-Id: Icbfc47a8d7bfe1600e4212b26e99b2a604de9ef7
Signed-off-by: Sven Schnelle
---
src/southbridge/intel/i82801gx/smbus.c | 182
1 files changed, 182 insertions(+), 0 deletions(-)
diff --git a/src/southbridge/intel/i82801gx/smbus.c
b/src/southbridge/intel/i82801gx/smbus.c
index 184120f..1764d97 100644
--- a/src/southbridge/intel/i82801gx/smbus.c
+++ b/src/southbridge/intel/i82801gx/smbus.c
@@ -42,8 +42,190 @@ static int lsmbus_read_byte(device_t dev, u8 address)
return do_smbus_read_byte(res->base, device, address);
}
+static int do_smbus_write_byte(unsigned smbus_base, unsigned device, unsigned
address, unsigned data)
+{
+ unsigned char global_status_register;
+
+ if (smbus_wait_until_ready(smbus_base) < 0)
+ return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+
+ /* Setup transaction */
+ /* Disable interrupts */
+ outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
+ /* Set the device I'm talking too */
+ outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
+ /* Set the command/address... */
+ outb(address & 0xff, smbus_base + SMBHSTCMD);
+ /* Set up for a byte data read */
+ outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
+(smbus_base + SMBHSTCTL));
+ /* Clear any lingering errors, so the transaction will run */
+ outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
+
+ /* Clear the data byte... */
+ outb(data, smbus_base + SMBHSTDAT0);
+
+ /* Start the command */
+ outb((inb(smbus_base + SMBHSTCTL) | 0x40),
+smbus_base + SMBHSTCTL);
+
+ /* Poll for transaction completion */
+ if (smbus_wait_until_done(smbus_base) < 0)
+ return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+
+ global_status_register = inb(smbus_base + SMBHSTSTAT);
+
+ /* Ignore the "In Use" status... */
+ global_status_register &= ~(3 << 5);
+
+ /* Read results of transaction */
+ if (global_status_register != (1 << 1))
+ return SMBUS_ERROR;
+ return 0;
+}
+
+static int lsmbus_write_byte(device_t dev, u8 address, u8 data)
+{
+ u16 device;
+ struct resource *res;
+ struct bus *pbus;
+
+ device = dev->path.i2c.device;
+ pbus = get_pbus_smbus(dev);
+ res = find_resource(pbus->dev, 0x20);
+ return do_smbus_write_byte(res->base, device, address, data);
+}
+
+static int do_smbus_block_write(unsigned smbus_base, unsigned device,
+ unsigned cmd, unsigned bytes, const u8 *buf)
+{
+ u8 status;
+
+ if (smbus_wait_until_ready(smbus_base) < 0)
+ return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+
+ /* Setup transaction */
+ /* Disable interrupts */
+ outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
+ /* Set the device I'm talking too */
+ outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
+ /* Set the command/address... */
+ outb(cmd & 0xff, smbus_base + SMBHSTCMD);
+ /* Set up for a block data write */
+ outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x5 << 2),
+(smbus_base + SMBHSTCTL));
+ /* Clear any lingering errors, so the transaction will run */
+ outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
+
+ /* set number of bytes to transfer */
+ outb(bytes, smbus_base + SMBHSTDAT0);
+
+ outb(*buf++, smbus_base + SMBBLKDAT);
+ bytes--;
+
+ /* Start the command */
+ outb((inb(smbus_base + SMBHSTCTL) | 0x40),
+smbus_base + SMBHSTCTL);
+
+ while(!(inb(smbus_base + SMBHSTSTAT) & 1));
+ /* Poll for transaction completion */
+ do {
+ status = inb(smbus_base + SMBHSTSTAT);
+ if (status & ((1 << 4) | /* FAILED */
+ (1 << 3) | /* BUS ERR */
+ (1 << 2))) /* DEV ERR */
+ return SMBUS_ERROR;
+
+ if (status & 0x80) { /* Byte done */
+ outb(*buf++, smbus_base + SMBBLKDAT);
+ outb(status, smbus_base + SMBHSTSTAT);
+ }
+ } while(status & 0x01);
+
+ return 0;
+}
+
+
+
+static int lsmbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buf)
+{
+ u16 device;
+ struct resource *res;
+ struct bus *pbus;
+
+ device = dev->path.i2c.de
[coreboot] New patch to review for coreboot: b4631f9 Add driver for ICS954309 clock generator
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/327
-gerrit
commit b4631f9483fc7ddcad53ed66901fc970a6b45f2d
Author: Sven Schnelle
Date: Sun Oct 23 15:53:47 2011 +0200
Add driver for ICS954309 clock generator
Change-Id: Iac7e91cdd995dad1954eaa2d4dd52bffa293fc95
Signed-off-by: Sven Schnelle
---
src/drivers/Kconfig |2 +-
src/drivers/Makefile.inc|2 +-
src/drivers/ics/954309/Kconfig |2 +
src/drivers/ics/954309/Makefile.inc |1 +
src/drivers/ics/954309/chip.h | 16 ++
src/drivers/ics/954309/ics954309.c | 56 +++
src/drivers/ics/Kconfig |1 +
src/drivers/ics/Makefile.inc|1 +
8 files changed, 79 insertions(+), 2 deletions(-)
diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig
index 98f2079..259bc29 100644
--- a/src/drivers/Kconfig
+++ b/src/drivers/Kconfig
@@ -25,4 +25,4 @@ source src/drivers/i2c/Kconfig
source src/drivers/oxford/Kconfig
source src/drivers/sil/Kconfig
source src/drivers/trident/Kconfig
-
+source src/drivers/ics/Kconfig
diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc
index ae7a098..21a698a 100644
--- a/src/drivers/Makefile.inc
+++ b/src/drivers/Makefile.inc
@@ -25,4 +25,4 @@ subdirs-y += i2c
subdirs-y += oxford
subdirs-y += sil
subdirs-y += trident
-
+subdirs-y += ics
diff --git a/src/drivers/ics/954309/Kconfig b/src/drivers/ics/954309/Kconfig
new file mode 100644
index 000..43840a3
--- /dev/null
+++ b/src/drivers/ics/954309/Kconfig
@@ -0,0 +1,2 @@
+config DRIVERS_ICS_954309
+ bool
diff --git a/src/drivers/ics/954309/Makefile.inc
b/src/drivers/ics/954309/Makefile.inc
new file mode 100644
index 000..ede9639
--- /dev/null
+++ b/src/drivers/ics/954309/Makefile.inc
@@ -0,0 +1 @@
+driver-$(CONFIG_DRIVERS_ICS_954309) += ics954309.c
diff --git a/src/drivers/ics/954309/chip.h b/src/drivers/ics/954309/chip.h
new file mode 100644
index 000..efd205f
--- /dev/null
+++ b/src/drivers/ics/954309/chip.h
@@ -0,0 +1,16 @@
+extern struct chip_operations drivers_ics_954309_ops;
+
+struct drivers_ics_954309_config {
+ u8 reg0;
+ u8 reg1;
+ u8 reg2;
+ u8 reg3;
+ u8 reg4;
+ u8 reg5;
+ u8 reg6;
+ u8 reg7;
+ u8 reg8;
+ u8 reg9;
+ u8 reg10;
+ u8 reg11;
+};
diff --git a/src/drivers/ics/954309/ics954309.c
b/src/drivers/ics/954309/ics954309.c
new file mode 100644
index 000..a7a350e
--- /dev/null
+++ b/src/drivers/ics/954309/ics954309.c
@@ -0,0 +1,56 @@
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "chip.h"
+#include
+
+static void ics954309_init(device_t dev)
+{
+ struct drivers_ics_954309_config *config;
+ u8 initdata[12];
+
+ if (!dev->enabled || dev->path.type != DEVICE_PATH_I2C)
+ return;
+
+ config = dev->chip_info;
+
+ initdata[0] = config->reg0;
+ initdata[1] = config->reg1;
+ initdata[2] = config->reg2;
+ initdata[3] = config->reg3;
+ initdata[4] = config->reg4;
+ initdata[5] = config->reg5;
+ initdata[6] = config->reg6;
+ initdata[7] = config->reg7;
+ initdata[8] = config->reg8;
+ initdata[9] = config->reg9;
+ initdata[10] = config->reg10;
+ initdata[11] = config->reg11;
+
+ smbus_block_write(dev, 0, 12, initdata);
+}
+
+static void ics954309_noop(device_t dummy)
+{
+}
+
+static struct device_operations ics954309_operations = {
+.read_resources = ics954309_noop,
+.set_resources= ics954309_noop,
+.enable_resources = ics954309_noop,
+.init = ics954309_init,
+};
+
+static void enable_dev(struct device *dev)
+{
+ dev->ops = &ics954309_operations;
+}
+
+struct chip_operations drivers_ics_954309_ops = {
+ CHIP_NAME("ICS 954309 Clock generator")
+ .enable_dev = enable_dev,
+};
diff --git a/src/drivers/ics/Kconfig b/src/drivers/ics/Kconfig
new file mode 100644
index 000..0a0ba66
--- /dev/null
+++ b/src/drivers/ics/Kconfig
@@ -0,0 +1 @@
+source src/drivers/ics/954309/Kconfig
diff --git a/src/drivers/ics/Makefile.inc b/src/drivers/ics/Makefile.inc
new file mode 100644
index 000..39cc90b
--- /dev/null
+++ b/src/drivers/ics/Makefile.inc
@@ -0,0 +1 @@
+subdirs-$(CONFIG_DRIVERS_ICS_954309) += 954309
--
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[coreboot] New patch to review for coreboot: a121fd5 T60: use ICS954309 clock driver
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/328 -gerrit commit a121fd554832055fd069929f4c752bef7ca447f7 Author: Sven Schnelle Date: Sun Oct 23 15:54:31 2011 +0200 T60: use ICS954309 clock driver Change-Id: I3f30fe601215784e1688c5ec51108dc0cf03e320 Signed-off-by: Sven Schnelle --- src/mainboard/lenovo/t60/Kconfig |1 + src/mainboard/lenovo/t60/devicetree.cb | 15 +++ 2 files changed, 16 insertions(+), 0 deletions(-) diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 294384b..9deb5a3 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_TI_PCI1X2X select EC_LENOVO_PMH7 select EC_LENOVO_H8 + select DRIVERS_ICS_954309 select BOARD_HAS_FADT select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 27ce46c..4d0476f 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -197,6 +197,21 @@ chip northbridge/intel/i945 end device pci 1f.3 on # SMBUS subsystemid 0x17aa 0x200f + chip drivers/ics/954309 + register "reg0" = "0x2e" + register "reg1" = "0xf7" + register "reg2" = "0x3c" + register "reg3" = "0x20" + register "reg4" = "0x01" + register "reg5" = "0x00" + register "reg6" = "0x1b" + register "reg7" = "0x01" + register "reg8" = "0x54" + register "reg9" = "0xff" + register "reg10" = "0xff" + register "reg11" = "0x07" + device i2c 69 on end + end end end end -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review for coreboot: 63d7721 i82801gx: Add setting for C4onC3 mode
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/329
-gerrit
commit 63d77216c457f639553a626a081c9013f4c9fef4
Author: Sven Schnelle
Date: Sun Oct 23 16:35:01 2011 +0200
i82801gx: Add setting for C4onC3 mode
If this bit is set, ich7 will enter C4 mode if possible instead of
C3. See ich7 specification (LPC controller, Power management control
registers) for more details.
Change-Id: I352cccdbc51ff6269f153a4542c7ee1df0c01d22
Signed-off-by: Sven Schnelle
---
src/southbridge/intel/i82801gx/chip.h |2 ++
src/southbridge/intel/i82801gx/lpc.c |4
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/src/southbridge/intel/i82801gx/chip.h
b/src/southbridge/intel/i82801gx/chip.h
index 4aea26e..b775d39 100644
--- a/src/southbridge/intel/i82801gx/chip.h
+++ b/src/southbridge/intel/i82801gx/chip.h
@@ -68,6 +68,8 @@ struct southbridge_intel_i82801gx_config {
uint32_t ide_enable_primary;
uint32_t ide_enable_secondary;
uint32_t sata_ahci;
+
+ int c4onc3_enable:1;
};
extern struct chip_operations southbridge_intel_i82801gx_ops;
diff --git a/src/southbridge/intel/i82801gx/lpc.c
b/src/southbridge/intel/i82801gx/lpc.c
index ab3c915..c6b76d3 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -243,6 +243,10 @@ static void i82801gx_power_options(device_t dev)
reg16 |= (1 << 2); // CLKRUN_EN - Mobile/Ultra only
reg16 |= (1 << 3); // Speedstep Enable - Mobile/Ultra only
reg16 |= (1 << 5); // CPUSLP_EN Desktop only
+
+ if (config->c4onc3_enable)
+ reg16 |= (1 << 7);
+
// another laptop wants this?
// reg16 &= ~(1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
--
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[coreboot] Patch set updated for coreboot: db823ad SPEEDSTEP: write _CST tables
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/321
-gerrit
commit db823adef073b9b781828fab9a3b0cc0bf460257
Author: Sven Schnelle
Date: Sat Oct 22 13:41:16 2011 +0200
SPEEDSTEP: write _CST tables
Change-Id: Idb4b57044808918de343d31519768d0986840f01
Signed-off-by: Sven Schnelle
---
src/arch/x86/include/arch/acpigen.h |2 ++
src/cpu/intel/speedstep/acpi.c | 10 ++
2 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/src/arch/x86/include/arch/acpigen.h
b/src/arch/x86/include/arch/acpigen.h
index 7feaa8e..0833371 100644
--- a/src/arch/x86/include/arch/acpigen.h
+++ b/src/arch/x86/include/arch/acpigen.h
@@ -66,4 +66,6 @@ int acpigen_write_resourcetemplate_footer(int len);
int acpigen_write_mainboard_resource_template(void);
int acpigen_write_mainboard_resources(const char *scope, const char *name);
+int get_cst_entries(struct cst_entry **) __attribute__((weak));
+
#endif
diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index 48e1a3c..8f32e4f 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -62,6 +62,11 @@ static int get_fsb(void)
return 200;
}
+int get_cst_entries(struct cst_entry **entries __attribute__((unused)))
+{
+ return 0;
+}
+
void generate_cpu_entries(void)
{
int len_pr, len_ps;
@@ -70,6 +75,9 @@ void generate_cpu_entries(void)
int totalcores = determine_total_number_of_cores();
int cores_per_package = (cpuid_ebx(1)>>16) & 0xff;
int numcpus = totalcores/cores_per_package; // this assumes that all
CPUs share the same layout
+ int count;
+ struct cst_entry *cst_entries;
+
printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus,
cores_per_package);
for (cpuID=1; cpuID <=numcpus; cpuID++) {
@@ -81,6 +89,8 @@ void generate_cpu_entries(void)
len_pr =
acpigen_write_processor((cpuID-1)*cores_per_package+coreID-1, pcontrol_blk,
plen);
len_pr += acpigen_write_empty_PCT();
len_pr +=
acpigen_write_PSD_package(cpuID-1,cores_per_package,SW_ANY);
+ if ((count = get_cst_entries(&cst_entries)) > 0)
+ len_pr +=
acpigen_write_CST_package(cst_entries, count);
len_pr += acpigen_write_name("_PSS");
int max_states=8;
--
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[coreboot] Patch set updated for coreboot: b117811 ACPI: Add function for writing _CST tables
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/312
-gerrit
commit b11781137de0ed6c2b694d710f23abf64e577db7
Author: Sven Schnelle
Date: Fri Oct 21 21:46:47 2011 +0200
ACPI: Add function for writing _CST tables
Change-Id: I4e16a0d37717c56a3529f9f9fdb05efec1d93f99
Signed-off-by: Sven Schnelle
---
src/arch/x86/boot/acpigen.c | 57 +++
src/arch/x86/include/arch/acpigen.h | 13
2 files changed, 70 insertions(+), 0 deletions(-)
diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c
index e8cd724..7dc7fed 100644
--- a/src/arch/x86/boot/acpigen.c
+++ b/src/arch/x86/boot/acpigen.c
@@ -374,6 +374,41 @@ int acpigen_write_PSD_package(u32 domain, u32 numprocs,
PSD_coord coordtype)
return len + lenh;
}
+static int acpigen_write_CST_package_entry(struct cst_entry *entry)
+{
+ int len, len0;
+ char *start, *end;
+
+ len0 = acpigen_write_package(4);
+ len = acpigen_write_resourcetemplate_header();
+ start = acpigen_get_current();
+ acpigen_write_register(entry->type, entry->width, entry->offset,
entry->addrsize, entry->address);
+ end = acpigen_get_current();
+ len += end-start;
+ len += acpigen_write_resourcetemplate_footer(len);
+ len += len0;
+ len += acpigen_write_dword(entry->ctype);
+ len += acpigen_write_dword(entry->latency);
+ len += acpigen_write_dword(entry->power);
+ acpigen_patch_len(len - 1);
+ return len;
+}
+
+int acpigen_write_CST_package(struct cst_entry *entry, int nentries)
+{
+ int len, lenh, lenp, i;
+ lenh = acpigen_write_name("_CST");
+ lenp = acpigen_write_package(nentries+1);
+ len = acpigen_write_dword(nentries);
+
+ for (i = 0; i < nentries; i++)
+ len += acpigen_write_CST_package_entry(entry + i);
+
+ len += lenp;
+ acpigen_patch_len(len - 1);
+ return len + lenh;
+}
+
int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size)
{
/*
@@ -399,6 +434,28 @@ int acpigen_write_mem32fixed(int readwrite, u32 base, u32
size)
return 12;
}
+int acpigen_write_register(int type, int width, int offset, int addrsize, u64
address)
+{
+ acpigen_emit_byte(0x82);
+ /* Byte 1+2: length (0x000c) */
+ acpigen_emit_byte(0x0c);
+ acpigen_emit_byte(0x00);
+ /* bit1-7 are ignored */
+ acpigen_emit_byte(type); /* FFixedHW */
+ acpigen_emit_byte(width); /* register width */
+ acpigen_emit_byte(offset); /* register offset */
+ acpigen_emit_byte(addrsize); /* register address size */
+ acpigen_emit_byte(address & 0xff); /* register address 0-7 */
+ acpigen_emit_byte((address >> 8) & 0xff); /* register address 8-15 */
+ acpigen_emit_byte((address >> 16) & 0xff); /* register address 16-23 */
+ acpigen_emit_byte((address >> 24) & 0xff); /* register address 24-31 */
+ acpigen_emit_byte((address >> 32) & 0xff); /* register address 32-39 */
+ acpigen_emit_byte((address >> 40) & 0xff); /* register address 40-47 */
+ acpigen_emit_byte((address >> 48) & 0xff); /* register address 48-55 */
+ acpigen_emit_byte((address >> 56) & 0xff); /* register address 56-63 */
+ return 15;
+}
+
int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16)
{
/*
diff --git a/src/arch/x86/include/arch/acpigen.h
b/src/arch/x86/include/arch/acpigen.h
index 6f13a7a..7feaa8e 100644
--- a/src/arch/x86/include/arch/acpigen.h
+++ b/src/arch/x86/include/arch/acpigen.h
@@ -24,6 +24,17 @@
#include
#include
+struct cst_entry {
+ int type;
+ int width;
+ int offset;
+ int addrsize;
+ u64 address;
+ int ctype;
+ int latency;
+ int power;
+};
+
void acpigen_patch_len(int len);
void acpigen_set_current(char *curr);
char *acpigen_get_current(void);
@@ -45,9 +56,11 @@ int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32
transLat, u32 busmLat
u32 control, u32 status);
typedef enum { SW_ALL=0xfc, SW_ANY=0xfd, HW_ALL=0xfe } PSD_coord;
int acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype);
+int acpigen_write_CST_package(struct cst_entry *entry, int nentries);
int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len);
int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size);
int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16);
+int acpigen_write_register(int type, int width, int offset, int addrsize, u64
address);
int acpigen_write_resourcetemplate_header(void);
int acpigen_write_resourcetemplate_footer(int len);
int acpigen_write_mainboard_resource_template(void);
--
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[coreboot] New patch to review for coreboot: 81d8670 X60: enable Cx power saving modes
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/331
-gerrit
commit 81d8670d8c50d1851a73be816c934742502ea673
Author: Sven Schnelle
Date: Sun Oct 23 16:57:50 2011 +0200
X60: enable Cx power saving modes
Change-Id: Ib03d9aa77050edde2538b80b32158cb3f0610be6
Signed-off-by: Sven Schnelle
---
src/mainboard/lenovo/x60/Kconfig |1 +
src/mainboard/lenovo/x60/devicetree.cb | 18 ++
src/mainboard/lenovo/x60/mainboard.c | 13 +
3 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig
index c4b2f63..1784505 100644
--- a/src/mainboard/lenovo/x60/Kconfig
+++ b/src/mainboard/lenovo/x60/Kconfig
@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SUPERIO_NSC_PC87392
select EC_LENOVO_PMH7
select EC_LENOVO_H8
+ select DRIVERS_ICS_954309
select BOARD_HAS_FADT
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
diff --git a/src/mainboard/lenovo/x60/devicetree.cb
b/src/mainboard/lenovo/x60/devicetree.cb
index 55e0b2d..000f9c7 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -60,6 +60,8 @@ chip northbridge/intel/i945
register "gpe0_en" = "0x1106"
register "alt_gp_smi_en" = "0x1000"
+
+ register "c4onc3_enable" = "1"
device pci 1b.0 on # Audio Cnotroller
subsystemid 0x17aa 0x2010
end
@@ -174,6 +176,22 @@ chip northbridge/intel/i945
end
device pci 1f.3 on # SMBUS
subsystemid 0x17aa 0x200f
+ chip drivers/ics/954309
+ register "reg0" = "0x2e"
+ register "reg1" = "0xf7"
+ register "reg2" = "0x3c"
+ register "reg3" = "0x20"
+ register "reg4" = "0x01"
+ register "reg5" = "0x00"
+ register "reg6" = "0x1b"
+ register "reg7" = "0x01"
+ register "reg8" = "0x54"
+ register "reg9" = "0xff"
+ register "reg10" = "0xff"
+ register "reg11" = "0x07"
+ device i2c 69 on end
+ end
+
end
end
chip southbridge/ricoh/rl5c476
diff --git a/src/mainboard/lenovo/x60/mainboard.c
b/src/mainboard/lenovo/x60/mainboard.c
index bf3d8d3..ef7d21f 100644
--- a/src/mainboard/lenovo/x60/mainboard.c
+++ b/src/mainboard/lenovo/x60/mainboard.c
@@ -36,6 +36,19 @@
#include
#include
#include "dock.h"
+#include
+
+static struct cst_entry cst_entries[] = {
+ { 0x7f, 1, 2, 0, 1, 1, 1, 1000 },
+ { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 2, 1, 500 },
+ { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 2, 17, 250 },
+};
+
+int get_cst_entries(struct cst_entry **entries)
+{
+ *entries = cst_entries;
+ return ARRAY_SIZE(cst_entries);
+}
static void mainboard_enable(device_t dev)
{
--
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[coreboot] New patch to review for coreboot: d4af8c7 T60: enable C4onC3 mode
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/330 -gerrit commit d4af8c74697b12572a92d502bce2fc97800d36b2 Author: Sven Schnelle Date: Sun Oct 23 16:36:22 2011 +0200 T60: enable C4onC3 mode It is safe to enable this setting on these Boards. Change-Id: Iaa7377117743d18a95c496c25abf9fb4a1b20ad9 Signed-off-by: Sven Schnelle --- src/mainboard/lenovo/t60/devicetree.cb |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 4d0476f..dba3fdd 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -68,6 +68,8 @@ chip northbridge/intel/i945 register "gpe0_en" = "0x1106" register "alt_gp_smi_en" = "0x1000" + register "c4onc3_enable" = "1" + device pci 1b.0 on # Audio Cnotroller subsystemid 0x17aa 0x2010 end -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch set updated for coreboot: 6656f70 T60: add _CST table
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/322
-gerrit
commit 6656f70efbbb71f4fb6e0bb5336525c27d047a96
Author: Sven Schnelle
Date: Sat Oct 22 13:41:28 2011 +0200
T60: add _CST table
Used by power management code to enable Cx powersaving modes.
Change-Id: I02c6b10762245bc48f21a341286236e203421de0
Signed-off-by: Sven Schnelle
---
src/mainboard/lenovo/t60/mainboard.c | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/lenovo/t60/mainboard.c
b/src/mainboard/lenovo/t60/mainboard.c
index 8456992..8c9ef0f 100644
--- a/src/mainboard/lenovo/t60/mainboard.c
+++ b/src/mainboard/lenovo/t60/mainboard.c
@@ -35,6 +35,19 @@
#include
#include
#include
+#include
+
+static struct cst_entry cst_entries[] = {
+ { 0x7f, 1, 2, 0, 1, 1, 1, 1000 },
+ { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 2, 1, 500 },
+ { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 2, 17, 250 },
+};
+
+int get_cst_entries(struct cst_entry **entries)
+{
+ *entries = cst_entries;
+ return ARRAY_SIZE(cst_entries);
+}
static void mainboard_enable(device_t dev)
{
--
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[coreboot] Patch set updated for coreboot: 34fbe31 i82801gx: Add write and read/write block functions
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/326
-gerrit
commit 34fbe315ac9301a0a312b09b386db74f4c3279c4
Author: Sven Schnelle
Date: Sun Oct 23 15:36:15 2011 +0200
i82801gx: Add write and read/write block functions
Change-Id: Icbfc47a8d7bfe1600e4212b26e99b2a604de9ef7
Signed-off-by: Sven Schnelle
---
src/southbridge/intel/i82801gx/smbus.c | 182
1 files changed, 182 insertions(+), 0 deletions(-)
diff --git a/src/southbridge/intel/i82801gx/smbus.c
b/src/southbridge/intel/i82801gx/smbus.c
index f296b46..63be26f 100644
--- a/src/southbridge/intel/i82801gx/smbus.c
+++ b/src/southbridge/intel/i82801gx/smbus.c
@@ -42,8 +42,190 @@ static int lsmbus_read_byte(device_t dev, u8 address)
return do_smbus_read_byte(res->base, device, address);
}
+static int do_smbus_write_byte(unsigned smbus_base, unsigned device, unsigned
address, unsigned data)
+{
+ unsigned char global_status_register;
+
+ if (smbus_wait_until_ready(smbus_base) < 0)
+ return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+
+ /* Setup transaction */
+ /* Disable interrupts */
+ outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
+ /* Set the device I'm talking too */
+ outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
+ /* Set the command/address... */
+ outb(address & 0xff, smbus_base + SMBHSTCMD);
+ /* Set up for a byte data read */
+ outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
+(smbus_base + SMBHSTCTL));
+ /* Clear any lingering errors, so the transaction will run */
+ outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
+
+ /* Clear the data byte... */
+ outb(data, smbus_base + SMBHSTDAT0);
+
+ /* Start the command */
+ outb((inb(smbus_base + SMBHSTCTL) | 0x40),
+smbus_base + SMBHSTCTL);
+
+ /* Poll for transaction completion */
+ if (smbus_wait_until_done(smbus_base) < 0)
+ return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+
+ global_status_register = inb(smbus_base + SMBHSTSTAT);
+
+ /* Ignore the "In Use" status... */
+ global_status_register &= ~(3 << 5);
+
+ /* Read results of transaction */
+ if (global_status_register != (1 << 1))
+ return SMBUS_ERROR;
+ return 0;
+}
+
+static int lsmbus_write_byte(device_t dev, u8 address, u8 data)
+{
+ u16 device;
+ struct resource *res;
+ struct bus *pbus;
+
+ device = dev->path.i2c.device;
+ pbus = get_pbus_smbus(dev);
+ res = find_resource(pbus->dev, 0x20);
+ return do_smbus_write_byte(res->base, device, address, data);
+}
+
+static int do_smbus_block_write(unsigned smbus_base, unsigned device,
+ unsigned cmd, unsigned bytes, const u8 *buf)
+{
+ u8 status;
+
+ if (smbus_wait_until_ready(smbus_base) < 0)
+ return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+
+ /* Setup transaction */
+ /* Disable interrupts */
+ outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
+ /* Set the device I'm talking too */
+ outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
+ /* Set the command/address... */
+ outb(cmd & 0xff, smbus_base + SMBHSTCMD);
+ /* Set up for a block data write */
+ outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x5 << 2),
+(smbus_base + SMBHSTCTL));
+ /* Clear any lingering errors, so the transaction will run */
+ outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
+
+ /* set number of bytes to transfer */
+ outb(bytes, smbus_base + SMBHSTDAT0);
+
+ outb(*buf++, smbus_base + SMBBLKDAT);
+ bytes--;
+
+ /* Start the command */
+ outb((inb(smbus_base + SMBHSTCTL) | 0x40),
+smbus_base + SMBHSTCTL);
+
+ while(!(inb(smbus_base + SMBHSTSTAT) & 1));
+ /* Poll for transaction completion */
+ do {
+ status = inb(smbus_base + SMBHSTSTAT);
+ if (status & ((1 << 4) | /* FAILED */
+ (1 << 3) | /* BUS ERR */
+ (1 << 2))) /* DEV ERR */
+ return SMBUS_ERROR;
+
+ if (status & 0x80) { /* Byte done */
+ outb(*buf++, smbus_base + SMBBLKDAT);
+ outb(status, smbus_base + SMBHSTSTAT);
+ }
+ } while(status & 0x01);
+
+ return 0;
+}
+
+
+
+static int lsmbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buf)
+{
+ u16 device;
+ struct resource *res;
+ struct bus *pbus;
+
+ device = dev->path.i2c.de
[coreboot] Patch set updated for coreboot: 82d5c8f Add driver for ICS954309 clock generator
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/327
-gerrit
commit 82d5c8f249022fe7cc11db7f48b95e57918aca89
Author: Sven Schnelle
Date: Sun Oct 23 15:53:47 2011 +0200
Add driver for ICS954309 clock generator
Change-Id: Iac7e91cdd995dad1954eaa2d4dd52bffa293fc95
Signed-off-by: Sven Schnelle
---
src/drivers/Kconfig |2 +-
src/drivers/Makefile.inc|2 +-
src/drivers/ics/954309/Kconfig |2 +
src/drivers/ics/954309/Makefile.inc |1 +
src/drivers/ics/954309/chip.h | 16 ++
src/drivers/ics/954309/ics954309.c | 56 +++
src/drivers/ics/Kconfig |1 +
src/drivers/ics/Makefile.inc|1 +
8 files changed, 79 insertions(+), 2 deletions(-)
diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig
index 98f2079..259bc29 100644
--- a/src/drivers/Kconfig
+++ b/src/drivers/Kconfig
@@ -25,4 +25,4 @@ source src/drivers/i2c/Kconfig
source src/drivers/oxford/Kconfig
source src/drivers/sil/Kconfig
source src/drivers/trident/Kconfig
-
+source src/drivers/ics/Kconfig
diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc
index ae7a098..21a698a 100644
--- a/src/drivers/Makefile.inc
+++ b/src/drivers/Makefile.inc
@@ -25,4 +25,4 @@ subdirs-y += i2c
subdirs-y += oxford
subdirs-y += sil
subdirs-y += trident
-
+subdirs-y += ics
diff --git a/src/drivers/ics/954309/Kconfig b/src/drivers/ics/954309/Kconfig
new file mode 100644
index 000..43840a3
--- /dev/null
+++ b/src/drivers/ics/954309/Kconfig
@@ -0,0 +1,2 @@
+config DRIVERS_ICS_954309
+ bool
diff --git a/src/drivers/ics/954309/Makefile.inc
b/src/drivers/ics/954309/Makefile.inc
new file mode 100644
index 000..ede9639
--- /dev/null
+++ b/src/drivers/ics/954309/Makefile.inc
@@ -0,0 +1 @@
+driver-$(CONFIG_DRIVERS_ICS_954309) += ics954309.c
diff --git a/src/drivers/ics/954309/chip.h b/src/drivers/ics/954309/chip.h
new file mode 100644
index 000..efd205f
--- /dev/null
+++ b/src/drivers/ics/954309/chip.h
@@ -0,0 +1,16 @@
+extern struct chip_operations drivers_ics_954309_ops;
+
+struct drivers_ics_954309_config {
+ u8 reg0;
+ u8 reg1;
+ u8 reg2;
+ u8 reg3;
+ u8 reg4;
+ u8 reg5;
+ u8 reg6;
+ u8 reg7;
+ u8 reg8;
+ u8 reg9;
+ u8 reg10;
+ u8 reg11;
+};
diff --git a/src/drivers/ics/954309/ics954309.c
b/src/drivers/ics/954309/ics954309.c
new file mode 100644
index 000..a7a350e
--- /dev/null
+++ b/src/drivers/ics/954309/ics954309.c
@@ -0,0 +1,56 @@
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "chip.h"
+#include
+
+static void ics954309_init(device_t dev)
+{
+ struct drivers_ics_954309_config *config;
+ u8 initdata[12];
+
+ if (!dev->enabled || dev->path.type != DEVICE_PATH_I2C)
+ return;
+
+ config = dev->chip_info;
+
+ initdata[0] = config->reg0;
+ initdata[1] = config->reg1;
+ initdata[2] = config->reg2;
+ initdata[3] = config->reg3;
+ initdata[4] = config->reg4;
+ initdata[5] = config->reg5;
+ initdata[6] = config->reg6;
+ initdata[7] = config->reg7;
+ initdata[8] = config->reg8;
+ initdata[9] = config->reg9;
+ initdata[10] = config->reg10;
+ initdata[11] = config->reg11;
+
+ smbus_block_write(dev, 0, 12, initdata);
+}
+
+static void ics954309_noop(device_t dummy)
+{
+}
+
+static struct device_operations ics954309_operations = {
+.read_resources = ics954309_noop,
+.set_resources= ics954309_noop,
+.enable_resources = ics954309_noop,
+.init = ics954309_init,
+};
+
+static void enable_dev(struct device *dev)
+{
+ dev->ops = &ics954309_operations;
+}
+
+struct chip_operations drivers_ics_954309_ops = {
+ CHIP_NAME("ICS 954309 Clock generator")
+ .enable_dev = enable_dev,
+};
diff --git a/src/drivers/ics/Kconfig b/src/drivers/ics/Kconfig
new file mode 100644
index 000..0a0ba66
--- /dev/null
+++ b/src/drivers/ics/Kconfig
@@ -0,0 +1 @@
+source src/drivers/ics/954309/Kconfig
diff --git a/src/drivers/ics/Makefile.inc b/src/drivers/ics/Makefile.inc
new file mode 100644
index 000..39cc90b
--- /dev/null
+++ b/src/drivers/ics/Makefile.inc
@@ -0,0 +1 @@
+subdirs-$(CONFIG_DRIVERS_ICS_954309) += 954309
--
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[coreboot] Patch set updated for coreboot: 384f8a9 i82801gx: Don't set I/O base address to static value
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/325
-gerrit
commit 384f8a938f219c4a1d69eccda24baa79b642d6d0
Author: Sven Schnelle
Date: Sun Oct 23 15:30:29 2011 +0200
i82801gx: Don't set I/O base address to static value
Doing it this way will break all subsequent smbus calls, because
the smbus code still uses res->base, which points to the old base
address. Fix this by allocating a proper resource.
Change-Id: I0f3d8fba5f8e2db7fe4ca991ef2c345aff436ea4
Signed-off-by: Sven Schnelle
---
src/southbridge/intel/i82801gx/smbus.c | 26 +++---
1 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/src/southbridge/intel/i82801gx/smbus.c
b/src/southbridge/intel/i82801gx/smbus.c
index 834f310..f296b46 100644
--- a/src/southbridge/intel/i82801gx/smbus.c
+++ b/src/southbridge/intel/i82801gx/smbus.c
@@ -29,19 +29,6 @@
#include "i82801gx.h"
#include "smbus.h"
-#define SMB_BASE 0x20
-static void smbus_init(struct device *dev)
-{
- u32 smb_base;
-
- smb_base = pci_read_config32(dev, SMB_BASE);
- printk(BIOS_DEBUG, "Initializing SMBus device:\n");
- printk(BIOS_DEBUG, " Old SMBUS Base Address: 0x%04x\n", smb_base);
- pci_write_config32(dev, SMB_BASE, 0x0401);
- smb_base = pci_read_config32(dev, SMB_BASE);
- printk(BIOS_DEBUG, " New SMBUS Base Address: 0x%04x\n", smb_base);
-}
-
static int lsmbus_read_byte(device_t dev, u8 address)
{
u16 device;
@@ -74,11 +61,20 @@ static struct pci_operations smbus_pci_ops = {
.set_subsystem= smbus_set_subsystem,
};
+static void smbus_read_resources(device_t dev)
+{
+ struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
+ res->base = SMBUS_IO_BASE;
+ res->size = 32;
+ res->limit = res->base + res->size - 1;
+ res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
+IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+}
+
static struct device_operations smbus_ops = {
- .read_resources = pci_dev_read_resources,
+ .read_resources = smbus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .init = smbus_init,
.scan_bus = scan_static_bus,
.enable = i82801gx_enable,
.ops_smbus_bus = &lops_smbus_bus,
--
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[coreboot] Patch set updated for coreboot: 88c9838 T60: add _CST table
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/322
-gerrit
commit 88c9838d4f9a1c0285df955225bdd03175b884ba
Author: Sven Schnelle
Date: Sat Oct 22 13:41:28 2011 +0200
T60: add _CST table
Used by power management code to enable Cx powersaving modes.
Change-Id: I02c6b10762245bc48f21a341286236e203421de0
Signed-off-by: Sven Schnelle
---
src/mainboard/lenovo/t60/mainboard.c | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/lenovo/t60/mainboard.c
b/src/mainboard/lenovo/t60/mainboard.c
index 8456992..8c9ef0f 100644
--- a/src/mainboard/lenovo/t60/mainboard.c
+++ b/src/mainboard/lenovo/t60/mainboard.c
@@ -35,6 +35,19 @@
#include
#include
#include
+#include
+
+static struct cst_entry cst_entries[] = {
+ { 0x7f, 1, 2, 0, 1, 1, 1, 1000 },
+ { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 2, 1, 500 },
+ { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 2, 17, 250 },
+};
+
+int get_cst_entries(struct cst_entry **entries)
+{
+ *entries = cst_entries;
+ return ARRAY_SIZE(cst_entries);
+}
static void mainboard_enable(device_t dev)
{
--
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[coreboot] Patch set updated for coreboot: 724a8e3 SPEEDSTEP: write _CST tables
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/321
-gerrit
commit 724a8e37a6175b9c13e8300109aa3f03b75828c8
Author: Sven Schnelle
Date: Sat Oct 22 13:41:16 2011 +0200
SPEEDSTEP: write _CST tables
Change-Id: Idb4b57044808918de343d31519768d0986840f01
Signed-off-by: Sven Schnelle
---
src/arch/x86/include/arch/acpigen.h |2 ++
src/cpu/intel/speedstep/acpi.c | 10 ++
2 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/src/arch/x86/include/arch/acpigen.h
b/src/arch/x86/include/arch/acpigen.h
index 7feaa8e..0833371 100644
--- a/src/arch/x86/include/arch/acpigen.h
+++ b/src/arch/x86/include/arch/acpigen.h
@@ -66,4 +66,6 @@ int acpigen_write_resourcetemplate_footer(int len);
int acpigen_write_mainboard_resource_template(void);
int acpigen_write_mainboard_resources(const char *scope, const char *name);
+int get_cst_entries(struct cst_entry **) __attribute__((weak));
+
#endif
diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index 48e1a3c..8f32e4f 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -62,6 +62,11 @@ static int get_fsb(void)
return 200;
}
+int get_cst_entries(struct cst_entry **entries __attribute__((unused)))
+{
+ return 0;
+}
+
void generate_cpu_entries(void)
{
int len_pr, len_ps;
@@ -70,6 +75,9 @@ void generate_cpu_entries(void)
int totalcores = determine_total_number_of_cores();
int cores_per_package = (cpuid_ebx(1)>>16) & 0xff;
int numcpus = totalcores/cores_per_package; // this assumes that all
CPUs share the same layout
+ int count;
+ struct cst_entry *cst_entries;
+
printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus,
cores_per_package);
for (cpuID=1; cpuID <=numcpus; cpuID++) {
@@ -81,6 +89,8 @@ void generate_cpu_entries(void)
len_pr =
acpigen_write_processor((cpuID-1)*cores_per_package+coreID-1, pcontrol_blk,
plen);
len_pr += acpigen_write_empty_PCT();
len_pr +=
acpigen_write_PSD_package(cpuID-1,cores_per_package,SW_ANY);
+ if ((count = get_cst_entries(&cst_entries)) > 0)
+ len_pr +=
acpigen_write_CST_package(cst_entries, count);
len_pr += acpigen_write_name("_PSS");
int max_states=8;
--
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[coreboot] Patch set updated for coreboot: f9753ed ACPI: Add function for writing _CST tables
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/312
-gerrit
commit f9753ed4de627c84d989673966d8f6cc1230ce39
Author: Sven Schnelle
Date: Fri Oct 21 21:46:47 2011 +0200
ACPI: Add function for writing _CST tables
Change-Id: I4e16a0d37717c56a3529f9f9fdb05efec1d93f99
Signed-off-by: Sven Schnelle
---
src/arch/x86/boot/acpigen.c | 57 +++
src/arch/x86/include/arch/acpigen.h | 13
2 files changed, 70 insertions(+), 0 deletions(-)
diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c
index e8cd724..7dc7fed 100644
--- a/src/arch/x86/boot/acpigen.c
+++ b/src/arch/x86/boot/acpigen.c
@@ -374,6 +374,41 @@ int acpigen_write_PSD_package(u32 domain, u32 numprocs,
PSD_coord coordtype)
return len + lenh;
}
+static int acpigen_write_CST_package_entry(struct cst_entry *entry)
+{
+ int len, len0;
+ char *start, *end;
+
+ len0 = acpigen_write_package(4);
+ len = acpigen_write_resourcetemplate_header();
+ start = acpigen_get_current();
+ acpigen_write_register(entry->type, entry->width, entry->offset,
entry->addrsize, entry->address);
+ end = acpigen_get_current();
+ len += end-start;
+ len += acpigen_write_resourcetemplate_footer(len);
+ len += len0;
+ len += acpigen_write_dword(entry->ctype);
+ len += acpigen_write_dword(entry->latency);
+ len += acpigen_write_dword(entry->power);
+ acpigen_patch_len(len - 1);
+ return len;
+}
+
+int acpigen_write_CST_package(struct cst_entry *entry, int nentries)
+{
+ int len, lenh, lenp, i;
+ lenh = acpigen_write_name("_CST");
+ lenp = acpigen_write_package(nentries+1);
+ len = acpigen_write_dword(nentries);
+
+ for (i = 0; i < nentries; i++)
+ len += acpigen_write_CST_package_entry(entry + i);
+
+ len += lenp;
+ acpigen_patch_len(len - 1);
+ return len + lenh;
+}
+
int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size)
{
/*
@@ -399,6 +434,28 @@ int acpigen_write_mem32fixed(int readwrite, u32 base, u32
size)
return 12;
}
+int acpigen_write_register(int type, int width, int offset, int addrsize, u64
address)
+{
+ acpigen_emit_byte(0x82);
+ /* Byte 1+2: length (0x000c) */
+ acpigen_emit_byte(0x0c);
+ acpigen_emit_byte(0x00);
+ /* bit1-7 are ignored */
+ acpigen_emit_byte(type); /* FFixedHW */
+ acpigen_emit_byte(width); /* register width */
+ acpigen_emit_byte(offset); /* register offset */
+ acpigen_emit_byte(addrsize); /* register address size */
+ acpigen_emit_byte(address & 0xff); /* register address 0-7 */
+ acpigen_emit_byte((address >> 8) & 0xff); /* register address 8-15 */
+ acpigen_emit_byte((address >> 16) & 0xff); /* register address 16-23 */
+ acpigen_emit_byte((address >> 24) & 0xff); /* register address 24-31 */
+ acpigen_emit_byte((address >> 32) & 0xff); /* register address 32-39 */
+ acpigen_emit_byte((address >> 40) & 0xff); /* register address 40-47 */
+ acpigen_emit_byte((address >> 48) & 0xff); /* register address 48-55 */
+ acpigen_emit_byte((address >> 56) & 0xff); /* register address 56-63 */
+ return 15;
+}
+
int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16)
{
/*
diff --git a/src/arch/x86/include/arch/acpigen.h
b/src/arch/x86/include/arch/acpigen.h
index 6f13a7a..7feaa8e 100644
--- a/src/arch/x86/include/arch/acpigen.h
+++ b/src/arch/x86/include/arch/acpigen.h
@@ -24,6 +24,17 @@
#include
#include
+struct cst_entry {
+ int type;
+ int width;
+ int offset;
+ int addrsize;
+ u64 address;
+ int ctype;
+ int latency;
+ int power;
+};
+
void acpigen_patch_len(int len);
void acpigen_set_current(char *curr);
char *acpigen_get_current(void);
@@ -45,9 +56,11 @@ int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32
transLat, u32 busmLat
u32 control, u32 status);
typedef enum { SW_ALL=0xfc, SW_ANY=0xfd, HW_ALL=0xfe } PSD_coord;
int acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype);
+int acpigen_write_CST_package(struct cst_entry *entry, int nentries);
int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len);
int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size);
int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16);
+int acpigen_write_register(int type, int width, int offset, int addrsize, u64
address);
int acpigen_write_resourcetemplate_header(void);
int acpigen_write_resourcetemplate_footer(int len);
int acpigen_write_mainboard_resource_template(void);
--
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[coreboot] Patch set updated for coreboot: 00ed3ec T60: enable C4onC3 mode
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/330 -gerrit commit 00ed3ecace4dfd46b5674580f943230b691e64e2 Author: Sven Schnelle Date: Sun Oct 23 16:36:22 2011 +0200 T60: enable C4onC3 mode It is safe to enable this setting on these Boards. Change-Id: Iaa7377117743d18a95c496c25abf9fb4a1b20ad9 Signed-off-by: Sven Schnelle --- src/mainboard/lenovo/t60/devicetree.cb |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 4d0476f..dba3fdd 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -68,6 +68,8 @@ chip northbridge/intel/i945 register "gpe0_en" = "0x1106" register "alt_gp_smi_en" = "0x1000" + register "c4onc3_enable" = "1" + device pci 1b.0 on # Audio Cnotroller subsystemid 0x17aa 0x2010 end -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch set updated for coreboot: eb04888 X60: enable Cx power saving modes
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/331
-gerrit
commit eb04888eaf8417fe9cdb59718fd2d06cd5e98308
Author: Sven Schnelle
Date: Sun Oct 23 16:57:50 2011 +0200
X60: enable Cx power saving modes
Change-Id: Ib03d9aa77050edde2538b80b32158cb3f0610be6
Signed-off-by: Sven Schnelle
---
src/mainboard/lenovo/x60/Kconfig |1 +
src/mainboard/lenovo/x60/devicetree.cb | 18 ++
src/mainboard/lenovo/x60/mainboard.c | 13 +
3 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig
index c4b2f63..1784505 100644
--- a/src/mainboard/lenovo/x60/Kconfig
+++ b/src/mainboard/lenovo/x60/Kconfig
@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SUPERIO_NSC_PC87392
select EC_LENOVO_PMH7
select EC_LENOVO_H8
+ select DRIVERS_ICS_954309
select BOARD_HAS_FADT
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
diff --git a/src/mainboard/lenovo/x60/devicetree.cb
b/src/mainboard/lenovo/x60/devicetree.cb
index 55e0b2d..000f9c7 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -60,6 +60,8 @@ chip northbridge/intel/i945
register "gpe0_en" = "0x1106"
register "alt_gp_smi_en" = "0x1000"
+
+ register "c4onc3_enable" = "1"
device pci 1b.0 on # Audio Cnotroller
subsystemid 0x17aa 0x2010
end
@@ -174,6 +176,22 @@ chip northbridge/intel/i945
end
device pci 1f.3 on # SMBUS
subsystemid 0x17aa 0x200f
+ chip drivers/ics/954309
+ register "reg0" = "0x2e"
+ register "reg1" = "0xf7"
+ register "reg2" = "0x3c"
+ register "reg3" = "0x20"
+ register "reg4" = "0x01"
+ register "reg5" = "0x00"
+ register "reg6" = "0x1b"
+ register "reg7" = "0x01"
+ register "reg8" = "0x54"
+ register "reg9" = "0xff"
+ register "reg10" = "0xff"
+ register "reg11" = "0x07"
+ device i2c 69 on end
+ end
+
end
end
chip southbridge/ricoh/rl5c476
diff --git a/src/mainboard/lenovo/x60/mainboard.c
b/src/mainboard/lenovo/x60/mainboard.c
index bf3d8d3..ef7d21f 100644
--- a/src/mainboard/lenovo/x60/mainboard.c
+++ b/src/mainboard/lenovo/x60/mainboard.c
@@ -36,6 +36,19 @@
#include
#include
#include "dock.h"
+#include
+
+static struct cst_entry cst_entries[] = {
+ { 0x7f, 1, 2, 0, 1, 1, 1, 1000 },
+ { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 2, 1, 500 },
+ { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 2, 17, 250 },
+};
+
+int get_cst_entries(struct cst_entry **entries)
+{
+ *entries = cst_entries;
+ return ARRAY_SIZE(cst_entries);
+}
static void mainboard_enable(device_t dev)
{
--
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[coreboot] Patch set updated for coreboot: 182921f T60: use ICS954309 clock driver
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/328 -gerrit commit 182921f4d6dbf77328757be109319631a88c810b Author: Sven Schnelle Date: Sun Oct 23 15:54:31 2011 +0200 T60: use ICS954309 clock driver Change-Id: I3f30fe601215784e1688c5ec51108dc0cf03e320 Signed-off-by: Sven Schnelle --- src/mainboard/lenovo/t60/Kconfig |1 + src/mainboard/lenovo/t60/devicetree.cb | 15 +++ 2 files changed, 16 insertions(+), 0 deletions(-) diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 294384b..9deb5a3 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_TI_PCI1X2X select EC_LENOVO_PMH7 select EC_LENOVO_H8 + select DRIVERS_ICS_954309 select BOARD_HAS_FADT select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 27ce46c..4d0476f 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -197,6 +197,21 @@ chip northbridge/intel/i945 end device pci 1f.3 on # SMBUS subsystemid 0x17aa 0x200f + chip drivers/ics/954309 + register "reg0" = "0x2e" + register "reg1" = "0xf7" + register "reg2" = "0x3c" + register "reg3" = "0x20" + register "reg4" = "0x01" + register "reg5" = "0x00" + register "reg6" = "0x1b" + register "reg7" = "0x01" + register "reg8" = "0x54" + register "reg9" = "0xff" + register "reg10" = "0xff" + register "reg11" = "0x07" + device i2c 69 on end + end end end end -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch set updated for coreboot: 96d3f10 i82801gx: Add setting for C4onC3 mode
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/329
-gerrit
commit 96d3f107bdc76252cbe3e22c7aef59c89f3ab988
Author: Sven Schnelle
Date: Sun Oct 23 16:35:01 2011 +0200
i82801gx: Add setting for C4onC3 mode
If this bit is set, ich7 will enter C4 mode if possible instead of
C3. See ich7 specification (LPC controller, Power management control
registers) for more details.
Change-Id: I352cccdbc51ff6269f153a4542c7ee1df0c01d22
Signed-off-by: Sven Schnelle
---
src/southbridge/intel/i82801gx/chip.h |2 ++
src/southbridge/intel/i82801gx/lpc.c |4
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/src/southbridge/intel/i82801gx/chip.h
b/src/southbridge/intel/i82801gx/chip.h
index 4aea26e..b775d39 100644
--- a/src/southbridge/intel/i82801gx/chip.h
+++ b/src/southbridge/intel/i82801gx/chip.h
@@ -68,6 +68,8 @@ struct southbridge_intel_i82801gx_config {
uint32_t ide_enable_primary;
uint32_t ide_enable_secondary;
uint32_t sata_ahci;
+
+ int c4onc3_enable:1;
};
extern struct chip_operations southbridge_intel_i82801gx_ops;
diff --git a/src/southbridge/intel/i82801gx/lpc.c
b/src/southbridge/intel/i82801gx/lpc.c
index ab3c915..c6b76d3 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -243,6 +243,10 @@ static void i82801gx_power_options(device_t dev)
reg16 |= (1 << 2); // CLKRUN_EN - Mobile/Ultra only
reg16 |= (1 << 3); // Speedstep Enable - Mobile/Ultra only
reg16 |= (1 << 5); // CPUSLP_EN Desktop only
+
+ if (config->c4onc3_enable)
+ reg16 |= (1 << 7);
+
// another laptop wants this?
// reg16 &= ~(1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
--
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[coreboot] Patch set updated for coreboot: 51a30f0 i82801gx: Add write and read/write block functions
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/326
-gerrit
commit 51a30f09e47bc743cf9530e86fbfd79c4dc9e2a6
Author: Sven Schnelle
Date: Sun Oct 23 15:36:15 2011 +0200
i82801gx: Add write and read/write block functions
Change-Id: Icbfc47a8d7bfe1600e4212b26e99b2a604de9ef7
Signed-off-by: Sven Schnelle
---
src/southbridge/intel/i82801gx/smbus.c | 183
1 files changed, 183 insertions(+), 0 deletions(-)
diff --git a/src/southbridge/intel/i82801gx/smbus.c
b/src/southbridge/intel/i82801gx/smbus.c
index f296b46..c2e57b1 100644
--- a/src/southbridge/intel/i82801gx/smbus.c
+++ b/src/southbridge/intel/i82801gx/smbus.c
@@ -42,8 +42,191 @@ static int lsmbus_read_byte(device_t dev, u8 address)
return do_smbus_read_byte(res->base, device, address);
}
+static int do_smbus_write_byte(unsigned smbus_base, unsigned device, unsigned
address, unsigned data)
+{
+ unsigned char global_status_register;
+
+ if (smbus_wait_until_ready(smbus_base) < 0)
+ return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+
+ /* Setup transaction */
+ /* Disable interrupts */
+ outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
+ /* Set the device I'm talking too */
+ outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
+ /* Set the command/address... */
+ outb(address & 0xff, smbus_base + SMBHSTCMD);
+ /* Set up for a byte data read */
+ outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
+(smbus_base + SMBHSTCTL));
+ /* Clear any lingering errors, so the transaction will run */
+ outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
+
+ /* Clear the data byte... */
+ outb(data, smbus_base + SMBHSTDAT0);
+
+ /* Start the command */
+ outb((inb(smbus_base + SMBHSTCTL) | 0x40),
+smbus_base + SMBHSTCTL);
+
+ /* Poll for transaction completion */
+ if (smbus_wait_until_done(smbus_base) < 0)
+ return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+
+ global_status_register = inb(smbus_base + SMBHSTSTAT);
+
+ /* Ignore the "In Use" status... */
+ global_status_register &= ~(3 << 5);
+
+ /* Read results of transaction */
+ if (global_status_register != (1 << 1))
+ return SMBUS_ERROR;
+ return 0;
+}
+
+static int lsmbus_write_byte(device_t dev, u8 address, u8 data)
+{
+ u16 device;
+ struct resource *res;
+ struct bus *pbus;
+
+ device = dev->path.i2c.device;
+ pbus = get_pbus_smbus(dev);
+ res = find_resource(pbus->dev, 0x20);
+ return do_smbus_write_byte(res->base, device, address, data);
+}
+
+static int do_smbus_block_write(unsigned smbus_base, unsigned device,
+ unsigned cmd, unsigned bytes, const u8 *buf)
+{
+ u8 status;
+
+ if (smbus_wait_until_ready(smbus_base) < 0)
+ return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+
+ /* Setup transaction */
+ /* Disable interrupts */
+ outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
+ /* Set the device I'm talking too */
+ outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
+ /* Set the command/address... */
+ outb(cmd & 0xff, smbus_base + SMBHSTCMD);
+ /* Set up for a block data write */
+ outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x5 << 2),
+(smbus_base + SMBHSTCTL));
+ /* Clear any lingering errors, so the transaction will run */
+ outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
+
+ /* set number of bytes to transfer */
+ outb(bytes, smbus_base + SMBHSTDAT0);
+
+ outb(*buf++, smbus_base + SMBBLKDAT);
+ bytes--;
+
+ /* Start the command */
+ outb((inb(smbus_base + SMBHSTCTL) | 0x40),
+smbus_base + SMBHSTCTL);
+
+ while(!(inb(smbus_base + SMBHSTSTAT) & 1));
+ /* Poll for transaction completion */
+ do {
+ status = inb(smbus_base + SMBHSTSTAT);
+ if (status & ((1 << 4) | /* FAILED */
+ (1 << 3) | /* BUS ERR */
+ (1 << 2))) /* DEV ERR */
+ return SMBUS_ERROR;
+
+ if (status & 0x80) { /* Byte done */
+ outb(*buf++, smbus_base + SMBBLKDAT);
+ outb(status, smbus_base + SMBHSTSTAT);
+ }
+ } while(status & 0x01);
+
+ return 0;
+}
+
+
+
+static int lsmbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buf)
+{
+ u16 device;
+ struct resource *res;
+ struct bus *pbus;
+
+ device = dev->path.i2c.de
[coreboot] New patch to review for coreboot: 0139e6e Lenovo H8: Fix h8_set_audio_mute()
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/334
-gerrit
commit 0139e6e1c0527c0be622e92f596a3b159ecde2e2
Author: Sven Schnelle
Date: Tue Oct 25 15:29:47 2011 +0200
Lenovo H8: Fix h8_set_audio_mute()
Logic is inverted (if argument is true, one would expect that
mute is enabled) and the wrong bit was used (1 instead 0)
Change-Id: I71133ba639f1fb0d3c3582f16211dd266a11cc64
Signed-off-by: Sven Schnelle
---
src/ec/lenovo/h8/h8.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c
index 560c39c..f81a39c 100644
--- a/src/ec/lenovo/h8/h8.c
+++ b/src/ec/lenovo/h8/h8.c
@@ -63,12 +63,12 @@ static void h8_log_ec_version(void)
fwvh >> 4, fwvh & 0x0f, fwvl >> 4, 0x41 + (fwvl & 0xf));
}
-void h8_set_audio_mute(int on)
+void h8_set_audio_mute(int mute)
{
- if (on)
- ec_clr_bit(0x3a, 0);
+ if (mute)
+ ec_set_bit(0x3a, 0);
else
- ec_set_bit(0x3a, 1);
+ ec_clr_bit(0x3a, 0);
}
void h8_enable_event(int event)
--
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[coreboot] New patch to review for coreboot: d5e94e6 X60/T60: remove superflous h8_set_audio_mute()
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/335
-gerrit
commit d5e94e6830f868d7437f0749be65f0d25869d61f
Author: Sven Schnelle
Date: Tue Oct 25 15:31:26 2011 +0200
X60/T60: remove superflous h8_set_audio_mute()
muting is handled by h8 code, no need to do it here.
Change-Id: I3f152e99f30701cd032b03105cbe3ae778865305
Signed-off-by: Sven Schnelle
---
src/mainboard/lenovo/t60/mainboard.c |3 ---
src/mainboard/lenovo/x60/mainboard.c |3 ---
2 files changed, 0 insertions(+), 6 deletions(-)
diff --git a/src/mainboard/lenovo/t60/mainboard.c
b/src/mainboard/lenovo/t60/mainboard.c
index 8456992..d4f260d 100644
--- a/src/mainboard/lenovo/t60/mainboard.c
+++ b/src/mainboard/lenovo/t60/mainboard.c
@@ -42,9 +42,6 @@ static void mainboard_enable(device_t dev)
device_t dev0, idedev;
u8 defaults_loaded = 0;
- /* enable Audio */
- h8_set_audio_mute(0);
-
/* If we're resuming from suspend, blink suspend LED */
dev0 = dev_find_slot(0, PCI_DEVFN(0,0));
if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC)
diff --git a/src/mainboard/lenovo/x60/mainboard.c
b/src/mainboard/lenovo/x60/mainboard.c
index bf3d8d3..e59b2e4 100644
--- a/src/mainboard/lenovo/x60/mainboard.c
+++ b/src/mainboard/lenovo/x60/mainboard.c
@@ -42,9 +42,6 @@ static void mainboard_enable(device_t dev)
device_t dev0, idedev;
u8 defaults_loaded = 0;
- /* enable Audio */
- h8_set_audio_mute(0);
-
ec_clr_bit(0x03, 2);
if (inb(0x164c) & 0x08) {
--
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[coreboot] Patch set updated for coreboot: f4fd169 Add driver for ICS954309 clock generator
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/327
-gerrit
commit f4fd169c67169c74b5e581f86dea8259a46d627c
Author: Sven Schnelle
Date: Sun Oct 23 15:53:47 2011 +0200
Add driver for ICS954309 clock generator
Change-Id: Iac7e91cdd995dad1954eaa2d4dd52bffa293fc95
Signed-off-by: Sven Schnelle
---
src/drivers/Kconfig |2 +-
src/drivers/Makefile.inc|2 +-
src/drivers/ics/954309/Kconfig |2 +
src/drivers/ics/954309/Makefile.inc |1 +
src/drivers/ics/954309/chip.h | 37 +
src/drivers/ics/954309/ics954309.c | 77 +++
src/drivers/ics/Kconfig |1 +
src/drivers/ics/Makefile.inc|1 +
8 files changed, 121 insertions(+), 2 deletions(-)
diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig
index 98f2079..259bc29 100644
--- a/src/drivers/Kconfig
+++ b/src/drivers/Kconfig
@@ -25,4 +25,4 @@ source src/drivers/i2c/Kconfig
source src/drivers/oxford/Kconfig
source src/drivers/sil/Kconfig
source src/drivers/trident/Kconfig
-
+source src/drivers/ics/Kconfig
diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc
index ae7a098..21a698a 100644
--- a/src/drivers/Makefile.inc
+++ b/src/drivers/Makefile.inc
@@ -25,4 +25,4 @@ subdirs-y += i2c
subdirs-y += oxford
subdirs-y += sil
subdirs-y += trident
-
+subdirs-y += ics
diff --git a/src/drivers/ics/954309/Kconfig b/src/drivers/ics/954309/Kconfig
new file mode 100644
index 000..43840a3
--- /dev/null
+++ b/src/drivers/ics/954309/Kconfig
@@ -0,0 +1,2 @@
+config DRIVERS_ICS_954309
+ bool
diff --git a/src/drivers/ics/954309/Makefile.inc
b/src/drivers/ics/954309/Makefile.inc
new file mode 100644
index 000..ede9639
--- /dev/null
+++ b/src/drivers/ics/954309/Makefile.inc
@@ -0,0 +1 @@
+driver-$(CONFIG_DRIVERS_ICS_954309) += ics954309.c
diff --git a/src/drivers/ics/954309/chip.h b/src/drivers/ics/954309/chip.h
new file mode 100644
index 000..8dfc3e0
--- /dev/null
+++ b/src/drivers/ics/954309/chip.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+extern struct chip_operations drivers_ics_954309_ops;
+
+struct drivers_ics_954309_config {
+ u8 reg0;
+ u8 reg1;
+ u8 reg2;
+ u8 reg3;
+ u8 reg4;
+ u8 reg5;
+ u8 reg6;
+ u8 reg7;
+ u8 reg8;
+ u8 reg9;
+ u8 reg10;
+ u8 reg11;
+};
diff --git a/src/drivers/ics/954309/ics954309.c
b/src/drivers/ics/954309/ics954309.c
new file mode 100644
index 000..ef62879
--- /dev/null
+++ b/src/drivers/ics/954309/ics954309.c
@@ -0,0 +1,77 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "chip.h"
+#include
+
+static void ics954309_init(device_t dev)
+{
+ struct drivers_ics_954309_config *config;
+ u8 initdata[12];
+
+ if (!dev->enabled || dev->path.type != DEVICE_PATH_I2C)
+ return;
+
+ config = dev->chip_info;
+
+ initdata[0] = config->reg0;
+ initdata[1] = config->reg1;
+ initdata[2] = config->reg2;
+ initdata[3] = config->reg3;
+ initdata[4] = config->reg4;
+ initdata[5] = config->reg5;
+ initdata[6] = config->reg6;
+ initdata[7] = config->reg7;
+ initdata[8] = config->reg8;
+ initdata[9] = config->reg9;
+ initdata[1
[coreboot] Patch set updated for coreboot: 517a0ce T60: use ICS954309 clock driver
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/328 -gerrit commit 517a0ce1c3d07e01cfaf340aae889f0a2e0e1cab Author: Sven Schnelle Date: Sun Oct 23 15:54:31 2011 +0200 T60: use ICS954309 clock driver Change-Id: I3f30fe601215784e1688c5ec51108dc0cf03e320 Signed-off-by: Sven Schnelle --- src/mainboard/lenovo/t60/Kconfig |1 + src/mainboard/lenovo/t60/devicetree.cb | 15 +++ 2 files changed, 16 insertions(+), 0 deletions(-) diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index c17d843..9141fc9 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_TI_PCI1X2X select EC_LENOVO_PMH7 select EC_LENOVO_H8 + select DRIVERS_ICS_954309 select BOARD_HAS_FADT select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 27ce46c..4d0476f 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -197,6 +197,21 @@ chip northbridge/intel/i945 end device pci 1f.3 on # SMBUS subsystemid 0x17aa 0x200f + chip drivers/ics/954309 + register "reg0" = "0x2e" + register "reg1" = "0xf7" + register "reg2" = "0x3c" + register "reg3" = "0x20" + register "reg4" = "0x01" + register "reg5" = "0x00" + register "reg6" = "0x1b" + register "reg7" = "0x01" + register "reg8" = "0x54" + register "reg9" = "0xff" + register "reg10" = "0xff" + register "reg11" = "0x07" + device i2c 69 on end + end end end end -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch set updated for coreboot: d53e56b T60: use ICS954309 clock driver
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/328 -gerrit commit d53e56b8e5a8e02c88a02dc4ec74472e8e97dfd7 Author: Sven Schnelle Date: Sun Oct 23 15:54:31 2011 +0200 T60: use ICS954309 clock driver Change-Id: I3f30fe601215784e1688c5ec51108dc0cf03e320 Signed-off-by: Sven Schnelle --- src/mainboard/lenovo/t60/Kconfig |1 + src/mainboard/lenovo/t60/devicetree.cb | 15 +++ 2 files changed, 16 insertions(+), 0 deletions(-) diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index c17d843..9141fc9 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_TI_PCI1X2X select EC_LENOVO_PMH7 select EC_LENOVO_H8 + select DRIVERS_ICS_954309 select BOARD_HAS_FADT select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 27ce46c..4d0476f 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -197,6 +197,21 @@ chip northbridge/intel/i945 end device pci 1f.3 on # SMBUS subsystemid 0x17aa 0x200f + chip drivers/ics/954309 + register "reg0" = "0x2e" + register "reg1" = "0xf7" + register "reg2" = "0x3c" + register "reg3" = "0x20" + register "reg4" = "0x01" + register "reg5" = "0x00" + register "reg6" = "0x1b" + register "reg7" = "0x01" + register "reg8" = "0x54" + register "reg9" = "0xff" + register "reg10" = "0xff" + register "reg11" = "0x07" + device i2c 69 on end + end end end end -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch set updated for coreboot: 8ae1d47 T60: add _CST table
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/322
-gerrit
commit 8ae1d4744e20ee90d4118f20ba5ee2a93bf0b6d1
Author: Sven Schnelle
Date: Sat Oct 22 13:41:28 2011 +0200
T60: add _CST table
Used by power management code to enable Cx powersaving modes.
Change-Id: I02c6b10762245bc48f21a341286236e203421de0
Signed-off-by: Sven Schnelle
---
src/mainboard/lenovo/t60/mainboard.c | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/lenovo/t60/mainboard.c
b/src/mainboard/lenovo/t60/mainboard.c
index d4f260d..19ac221 100644
--- a/src/mainboard/lenovo/t60/mainboard.c
+++ b/src/mainboard/lenovo/t60/mainboard.c
@@ -35,6 +35,19 @@
#include
#include
#include
+#include
+
+static struct cst_entry cst_entries[] = {
+ { 0x7f, 1, 2, 0, 1, 1, 1, 1000 },
+ { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 2, 1, 500 },
+ { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 2, 17, 250 },
+};
+
+int get_cst_entries(struct cst_entry **entries)
+{
+ *entries = cst_entries;
+ return ARRAY_SIZE(cst_entries);
+}
static void mainboard_enable(device_t dev)
{
--
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[coreboot] Patch set updated for coreboot: a8894c6 X60: enable Cx power saving modes
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/331
-gerrit
commit a8894c6ff29a9b7be5b6e90065bd7b404c211e18
Author: Sven Schnelle
Date: Sun Oct 23 16:57:50 2011 +0200
X60: enable Cx power saving modes
Change-Id: Ib03d9aa77050edde2538b80b32158cb3f0610be6
Signed-off-by: Sven Schnelle
---
src/mainboard/lenovo/x60/Kconfig |1 +
src/mainboard/lenovo/x60/devicetree.cb | 18 ++
src/mainboard/lenovo/x60/mainboard.c | 13 +
3 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig
index 3b39ed8..69f83a8 100644
--- a/src/mainboard/lenovo/x60/Kconfig
+++ b/src/mainboard/lenovo/x60/Kconfig
@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SUPERIO_NSC_PC87392
select EC_LENOVO_PMH7
select EC_LENOVO_H8
+ select DRIVERS_ICS_954309
select BOARD_HAS_FADT
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
diff --git a/src/mainboard/lenovo/x60/devicetree.cb
b/src/mainboard/lenovo/x60/devicetree.cb
index 55e0b2d..000f9c7 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -60,6 +60,8 @@ chip northbridge/intel/i945
register "gpe0_en" = "0x1106"
register "alt_gp_smi_en" = "0x1000"
+
+ register "c4onc3_enable" = "1"
device pci 1b.0 on # Audio Cnotroller
subsystemid 0x17aa 0x2010
end
@@ -174,6 +176,22 @@ chip northbridge/intel/i945
end
device pci 1f.3 on # SMBUS
subsystemid 0x17aa 0x200f
+ chip drivers/ics/954309
+ register "reg0" = "0x2e"
+ register "reg1" = "0xf7"
+ register "reg2" = "0x3c"
+ register "reg3" = "0x20"
+ register "reg4" = "0x01"
+ register "reg5" = "0x00"
+ register "reg6" = "0x1b"
+ register "reg7" = "0x01"
+ register "reg8" = "0x54"
+ register "reg9" = "0xff"
+ register "reg10" = "0xff"
+ register "reg11" = "0x07"
+ device i2c 69 on end
+ end
+
end
end
chip southbridge/ricoh/rl5c476
diff --git a/src/mainboard/lenovo/x60/mainboard.c
b/src/mainboard/lenovo/x60/mainboard.c
index e59b2e4..5bc1dca 100644
--- a/src/mainboard/lenovo/x60/mainboard.c
+++ b/src/mainboard/lenovo/x60/mainboard.c
@@ -36,6 +36,19 @@
#include
#include
#include "dock.h"
+#include
+
+static struct cst_entry cst_entries[] = {
+ { 0x7f, 1, 2, 0, 1, 1, 1, 1000 },
+ { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 2, 1, 500 },
+ { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 2, 17, 250 },
+};
+
+int get_cst_entries(struct cst_entry **entries)
+{
+ *entries = cst_entries;
+ return ARRAY_SIZE(cst_entries);
+}
static void mainboard_enable(device_t dev)
{
--
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[coreboot] New patch to review for coreboot: 1cdccab i82801gx: Fix port status in AHCI mode
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/340
-gerrit
commit 1cdccab188602150e7deec78bea8339f733ae68d
Author: Sven Schnelle
Date: Thu Oct 27 13:05:40 2011 +0200
i82801gx: Fix port status in AHCI mode
The code used PCI register 0x92 to enable sata ports,
which is wrong. The ICH7 documentation states:
"This register is only used in systems that do not
support AHCI. In AHCI enabled systems, bits[3:0] must
always be set (ICH7R only) / bits[2,0] must always be set
(Mobile only), and the status of the port is controlled
through AHCI memory space."
Writing 0x0f to ICH7-M doesn't seem to hurt, so lets write
0x0f for both variants. This patch makes sata_ahci work on
my Thinkpad T60 and X60s.
Change-Id: If3b3daec2e5fbaa446de00272ebde01cd8d52475
Signed-off-by: Sven Schnelle
---
src/southbridge/intel/i82801gx/chip.h |1 +
src/southbridge/intel/i82801gx/sata.c |9 -
2 files changed, 9 insertions(+), 1 deletions(-)
diff --git a/src/southbridge/intel/i82801gx/chip.h
b/src/southbridge/intel/i82801gx/chip.h
index b775d39..cc17539 100644
--- a/src/southbridge/intel/i82801gx/chip.h
+++ b/src/southbridge/intel/i82801gx/chip.h
@@ -68,6 +68,7 @@ struct southbridge_intel_i82801gx_config {
uint32_t ide_enable_primary;
uint32_t ide_enable_secondary;
uint32_t sata_ahci;
+ uint32_t sata_ports_implemented;
int c4onc3_enable:1;
};
diff --git a/src/southbridge/intel/i82801gx/sata.c
b/src/southbridge/intel/i82801gx/sata.c
index c390848..0e7a1a7 100644
--- a/src/southbridge/intel/i82801gx/sata.c
+++ b/src/southbridge/intel/i82801gx/sata.c
@@ -30,6 +30,8 @@ static void sata_init(struct device *dev)
{
u32 reg32;
u16 reg16;
+ u32 *ahci_bar;
+
/* Get the chip configuration */
config_t *config = dev->chip_info;
@@ -106,9 +108,14 @@ static void sata_init(struct device *dev)
/* Set Sata Controller Mode. */
pci_write_config8(dev, 0x90, 0x40); // 40=AHCI
- /* Port 0 & 1 enable */
+ /* In ACHI mode, bit[3:0] must always be set
+* (Port status is controlled through AHCI BAR)
+*/
pci_write_config8(dev, 0x92, 0x0f);
+ ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff);
+ ahci_bar[3] = config->sata_ports_implemented;
+
/* SATA Initialization register */
pci_write_config32(dev, 0x94, 0x1a000180);
} else {
--
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[coreboot] New patch to review for coreboot: 64ee1fc X60/T60: enable AHCI mode
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/341 -gerrit commit 64ee1fcb2f421819882b5cc2cd5d1f19ef284c33 Author: Sven Schnelle Date: Thu Oct 27 13:10:14 2011 +0200 X60/T60: enable AHCI mode Signed-off-by: Sven Schnelle Change-Id: I2166ae9ee9e7e0e431583249f015d130d15fac61 --- src/mainboard/lenovo/t60/devicetree.cb |3 ++- src/mainboard/lenovo/x60/devicetree.cb |3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index dba3fdd..f8ba137 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -63,7 +63,8 @@ chip northbridge/intel/i945 register "gpi12_routing" = "2" register "gpi8_routing" = "2" - register "sata_ahci" = "0x0" + register "sata_ahci" = "0x1" + register "sata_ports_implemented" = "0x01" register "gpe0_en" = "0x1106" register "alt_gp_smi_en" = "0x1000" diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 000f9c7..2f0a179 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -56,7 +56,8 @@ chip northbridge/intel/i945 register "gpi12_routing" = "1" register "gpi8_routing" = "2" - register "sata_ahci" = "0x0" + register "sata_ahci" = "0x1" + register "sata_ports_implemented" = "0x01" register "gpe0_en" = "0x1106" register "alt_gp_smi_en" = "0x1000" -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review for coreboot: 9c6f959 Fix compilation with CONFIG_USBDEBUG enabled
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/349
-gerrit
commit 9c6f9594620284770f91cd7a7d31bd1c25988ff9
Author: Sven Schnelle
Date: Fri Oct 28 21:20:36 2011 +0200
Fix compilation with CONFIG_USBDEBUG enabled
Compilation fails with:
src/console/console.c: In function ‘console_init’:
src/console/console.c:104:2: error: implicit declaration of function
‘enable_usbdebug’ [-Werror=implicit-function-declaration]
src/console/console.c:105:2: error: implicit declaration of function
‘early_usbdebug_init’ [-Werror=implicit-function-declaration]
and
build/cpu/x86/smm/smm.o: In function `console_tx_byte':
/home/svens/coreboot/coreboot/src/cpu/x86/smm/smiutil.c:62: undefined
reference to `usbdebug_tx_byte'
move the declarations from the southbridge code to usbdebug.h,
as the prototypes are now unified. Also fix compilation for SMM
code.
Change-Id: Ic444a4ba22710f05af758497935edc277c95c752
Signed-off-by: Sven Schnelle
---
src/console/console.c |3 +++
src/include/usbdebug.h|1 +
src/lib/Makefile.inc |1 +
src/lib/usbdebug.c|2 +-
src/southbridge/amd/sb600/sb600.h |1 -
src/southbridge/amd/sb700/sb700.h |2 --
src/southbridge/amd/sb800/sb800.h |1 -
src/southbridge/intel/i82801gx/i82801gx.h |1 -
src/southbridge/nvidia/ck804/ck804.h |1 -
src/southbridge/nvidia/mcp55/mcp55.h |1 -
src/southbridge/sis/sis966/sis966.h |4
11 files changed, 6 insertions(+), 12 deletions(-)
diff --git a/src/console/console.c b/src/console/console.c
index a73616e..b76c146 100644
--- a/src/console/console.c
+++ b/src/console/console.c
@@ -29,6 +29,9 @@
#if CONFIG_CONSOLE_NE2K
#include
#endif
+#ifdef CONFIG_USBDEBUG
+#include
+#endif
#ifndef __PRE_RAM__
#include
diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h
index 281ccde..ab46c3b 100644
--- a/src/include/usbdebug.h
+++ b/src/include/usbdebug.h
@@ -40,5 +40,6 @@ unsigned get_ehci_debug(void);
void set_debug_port(unsigned port);
int early_usbdebug_init(void);
void usbdebug_tx_byte(unsigned char data);
+void enable_usbdebug(unsigned int port);
#endif
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index b207ffe..8f7ca43 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -32,6 +32,7 @@ ramstage-y += cbmem.c
ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
ramstage-$(CONFIG_USBDEBUG) += usbdebug.c
+smm-$(CONFIG_USBDEBUG) += usbdebug.c
ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
ramstage-$(CONFIG_TRACE) += trace.c
diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c
index d022d2f..8a1a74d 100644
--- a/src/lib/usbdebug.c
+++ b/src/lib/usbdebug.c
@@ -575,6 +575,7 @@ int early_usbdebug_init(void)
return usbdebug_init(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET,
dbg_info);
}
+#endif
void usbdebug_tx_byte(unsigned char data)
{
@@ -588,4 +589,3 @@ void usbdebug_tx_byte(unsigned char data)
dbgp_bulk_write_x(dbg_info, (char*)&data, 1);
}
}
-#endif
diff --git a/src/southbridge/amd/sb600/sb600.h
b/src/southbridge/amd/sb600/sb600.h
index 97a7ad2..629f389 100644
--- a/src/southbridge/amd/sb600/sb600.h
+++ b/src/southbridge/amd/sb600/sb600.h
@@ -40,5 +40,4 @@ void sb600_enable(device_t dev);
void sb600_lpc_port80(void);
void sb600_pci_port80(void);
-void enable_usbdebug(unsigned int port);
#endif /* SB600_H */
diff --git a/src/southbridge/amd/sb700/sb700.h
b/src/southbridge/amd/sb700/sb700.h
index 794dd96..165c72d 100755
--- a/src/southbridge/amd/sb700/sb700.h
+++ b/src/southbridge/amd/sb700/sb700.h
@@ -82,8 +82,6 @@ int acpi_is_wakeup_early(void);
int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
-void enable_usbdebug(unsigned int port);
-
u32 __attribute__ ((weak)) get_sbdn(u32 bus);
void __attribute__((weak)) enable_fid_change_on_sb(u32 sbbusn, u32 sbdn);
#endif /* SB700_H */
diff --git a/src/southbridge/amd/sb800/sb800.h
b/src/southbridge/amd/sb800/sb800.h
index d7a4a38..ffe7aeb 100644
--- a/src/southbridge/amd/sb800/sb800.h
+++ b/src/southbridge/amd/sb800/sb800.h
@@ -58,7 +58,6 @@ void sb800_clk_output_48Mhz(void);
int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
-void enable_usbdebug(unsigned int port);
#else
void sb800_enable(device_t dev);
void __attribute__((weak)) sb800_setup_sata_phys(struct device *dev);
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h
b/src/southbridge/intel/i82801gx/i82801gx.h
index 2ceb215..8fb5b92 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i8280
[coreboot] New patch to review for coreboot: 9aaaa2f T60: remove redundant usbdebug_init call()
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/350 -gerrit commit 92f0eb979ae254a9fa8c5774af419f53989b Author: Sven Schnelle Date: Fri Oct 28 21:26:16 2011 +0200 T60: remove redundant usbdebug_init call() called from console code, no need to call it here. Change-Id: I4c34f89c82cc2478db8de4e98584e69d7ab0ca82 Signed-off-by: Sven Schnelle --- src/mainboard/lenovo/t60/romstage.c |5 - 1 files changed, 0 insertions(+), 5 deletions(-) diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 7ed7768..13faee2 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -240,11 +240,6 @@ void main(unsigned long bist) early_superio_config(); } -#if CONFIG_USBDEBUG - i82801gx_enable_usbdebug(1); - early_usbdebug_init(); -#endif - /* Setup the console */ console_init(); -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review for coreboot: ce854aa remove usbdebug.h include from mainboard/romstage code
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/354 -gerrit commit ce854aa3d858bda151f11ee289fd71f810760d85 Author: Sven Schnelle Date: Sun Oct 30 08:49:43 2011 +0100 remove usbdebug.h include from mainboard/romstage code No romstage is supposed to use usbdebug functions/defines directly, so remove all those includes. The usb code is now called and setup from console code. Change-Id: I9b1120d96f5993303d6b302accc86e14a91f7a9f Signed-off-by: Sven Schnelle --- src/mainboard/amd/bimini_fam10/romstage.c |1 - src/mainboard/amd/dbm690t/romstage.c|1 - src/mainboard/amd/mahogany/romstage.c |1 - src/mainboard/amd/mahogany_fam10/romstage.c |1 - src/mainboard/amd/pistachio/romstage.c |1 - src/mainboard/amd/tilapia_fam10/romstage.c |1 - src/mainboard/asrock/939a785gmh/romstage.c |1 - src/mainboard/asus/m2n-e/romstage.c |1 - src/mainboard/asus/m4a78-em/romstage.c |1 - src/mainboard/asus/m4a785-m/romstage.c |1 - src/mainboard/getac/p470/romstage.c |1 - src/mainboard/gigabyte/ga_2761gxdk/romstage.c |1 - src/mainboard/gigabyte/m57sli/romstage.c|1 - src/mainboard/gigabyte/ma785gmt/romstage.c |1 - src/mainboard/gigabyte/ma78gm/romstage.c|1 - src/mainboard/ibase/mb899/romstage.c|1 - src/mainboard/iei/kino-780am2-fam10/romstage.c |1 - src/mainboard/intel/d945gclf/romstage.c |1 - src/mainboard/jetway/pa78vm5/romstage.c |1 - src/mainboard/kontron/986lcd-m/romstage.c |1 - src/mainboard/kontron/kt690/romstage.c |1 - src/mainboard/lenovo/t60/romstage.c |1 - src/mainboard/lenovo/x60/romstage.c |1 - src/mainboard/msi/ms7260/romstage.c |1 - src/mainboard/msi/ms9652_fam10/romstage.c |1 - src/mainboard/nvidia/l1_2pvv/romstage.c |1 - src/mainboard/roda/rk886ex/romstage.c |1 - src/mainboard/supermicro/h8scm_fam10/romstage.c |1 - src/mainboard/technexion/tim5690/romstage.c |1 - src/mainboard/technexion/tim8690/romstage.c |1 - src/mainboard/tyan/s2912/romstage.c |1 - src/mainboard/tyan/s2912_fam10/romstage.c |1 - 32 files changed, 0 insertions(+), 32 deletions(-) diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 175325e..732e033 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -42,7 +42,6 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include #include "cpu/x86/bist.h" -#include #include "cpu/x86/mtrr/earlymtrr.c" #include #include "northbridge/amd/amdfam10/setup_resource_map.c" diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index f119ec9..66637a8 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -39,7 +39,6 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/early_serial.c" #include -#include #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 5c9d538..104652a 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -39,7 +39,6 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8718f/early_serial.c" -#include #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 4d26ca3..04a9e45 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -43,7 +43,6 @@ #include #include "cpu/x86/bist.h" #include "superio/ite/it8718f/early_serial.c" -#include #include "cpu/x86/mtrr/earlymtrr.c" #include #include "northbridge/amd/amdfam10/setup_resource_map.c" diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index ee00c13..5d6e7a8 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -33,7 +33,6 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/early_serial.c" -#include #include #include "cpu/x86/mtrr/earlymtrr.c"
[coreboot] New patch to review for coreboot: b148312 Fix usb debug dongle support
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/355
-gerrit
commit b1483129aa5aa6b2f22a6565f75bcdb56772d092
Author: Sven Schnelle
Date: Sun Oct 30 09:57:35 2011 +0100
Fix usb debug dongle support
- move enable_usbdebug() declaration to usbdebug.h
- reinitialize debug driver in ramstage, as the copying of the data
structure from romstage doesn't work right now. This way of copying
data from romstage to ramstage is really board/cpu specific, and is
likely to break often. So don't do it.
Change-Id: I394678ded6679c1803e29eb691b926182bdcab68
Signed-off-by: Sven Schnelle
---
src/console/console.c |4
src/console/usbdebug_console.c | 10 +-
src/include/ehci.h |3 ++-
src/include/usbdebug.h |5 -
src/lib/Makefile.inc|1 +
src/lib/usbdebug.c |6 +-
src/southbridge/amd/sb600/Makefile.inc |4 +++-
src/southbridge/amd/sb600/sb600.h |1 -
src/southbridge/amd/sb700/Makefile.inc |4 +++-
src/southbridge/amd/sb700/sb700.h |2 --
src/southbridge/amd/sb800/Makefile.inc |4 +++-
src/southbridge/amd/sb800/sb800.h |1 -
src/southbridge/intel/i82801gx/Makefile.inc |2 ++
src/southbridge/intel/i82801gx/i82801gx.h |1 -
src/southbridge/nvidia/ck804/Makefile.inc |4 +++-
src/southbridge/nvidia/ck804/ck804.h|1 -
src/southbridge/nvidia/mcp55/Makefile.inc |4 +++-
src/southbridge/nvidia/mcp55/mcp55.h|1 -
src/southbridge/sis/sis966/Makefile.inc |5 -
src/southbridge/sis/sis966/sis966.h |4
20 files changed, 34 insertions(+), 33 deletions(-)
diff --git a/src/console/console.c b/src/console/console.c
index a73616e..325170d 100644
--- a/src/console/console.c
+++ b/src/console/console.c
@@ -30,6 +30,10 @@
#include
#endif
+#if CONFIG_USBDEBUG
+#include
+#endif
+
#ifndef __PRE_RAM__
#include
#include
diff --git a/src/console/usbdebug_console.c b/src/console/usbdebug_console.c
index 2270ceb..a624b9d 100644
--- a/src/console/usbdebug_console.c
+++ b/src/console/usbdebug_console.c
@@ -50,15 +50,7 @@ unsigned get_ehci_debug(void)
static void dbgp_init(void)
{
- struct ehci_debug_info *dbg_infox;
-
- /* At this point, all we have to do is copy the fixed address
-* debug_info data structure to our version defined above. */
-
- dbg_infox = (struct ehci_debug_info *)
- ((CONFIG_RAMTOP) - sizeof(struct ehci_debug_info));
-
- memcpy(&dbg_info, dbg_infox, sizeof(struct ehci_debug_info));
+ usbdebug_init(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, &dbg_info);
}
static void dbgp_tx_byte(unsigned char data)
diff --git a/src/include/ehci.h b/src/include/ehci.h
index 4b8c94c..29347f9 100644
--- a/src/include/ehci.h
+++ b/src/include/ehci.h
@@ -25,6 +25,7 @@
#define EHCI_BAR_INDEX 0x10
+#ifndef __ROMCC__
/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
/* Section 2.2 Host Controller Capability Registers */
@@ -199,5 +200,5 @@ struct ehci_dbg_port {
u32 address;
#define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep))
} __attribute__ ((packed));
-
+#endif
#endif
diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h
index 281ccde..a7ab21f 100644
--- a/src/include/usbdebug.h
+++ b/src/include/usbdebug.h
@@ -32,6 +32,8 @@ struct ehci_debug_info {
u32 endpoint_in;
};
+#ifndef __ROMCC__
+void enable_usbdebug(unsigned int port);
int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int
size);
int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size);
void set_ehci_base(unsigned ehci_base);
@@ -40,5 +42,6 @@ unsigned get_ehci_debug(void);
void set_debug_port(unsigned port);
int early_usbdebug_init(void);
void usbdebug_tx_byte(unsigned char data);
-
+int usbdebug_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info
*info);
+#endif
#endif
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index b207ffe..432e24e 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -40,5 +40,6 @@ driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c
smm-y += memcpy.c cbfs.c memset.c memcmp.c
smm-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
+smm-$(CONFIG_USBDEBUG) += usbdebug.c
$(obj)/lib/version.ramstage.o : $(obj)/build.h
diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c
index d022d2f..6b75acf 100644
--- a/src/lib/usbdebug.c
+++ b/src/lib/usbdebug.c
@@ -238,7 +238,6 @@ int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void
*data, int size)
dbg_info->endpoint_in, data, size);
}
-#ifdef __PRE_RAM__
static void dbgp_md
[coreboot] Patch set updated for coreboot: 1621d3c Fix usb debug dongle support
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/355
-gerrit
commit 1621d3cd8d1e01a39dbed72d3627aaca4eb5e999
Author: Sven Schnelle
Date: Sun Oct 30 09:57:35 2011 +0100
Fix usb debug dongle support
- move enable_usbdebug() declaration to usbdebug.h
- reinitialize debug driver in ramstage, as copying the data
structure from romstage doesn't work right now. This way of copying
data from romstage to ramstage is really board/cpu specific, and is
likely to break often. So don't do it.
Change-Id: I394678ded6679c1803e29eb691b926182bdcab68
Signed-off-by: Sven Schnelle
---
src/console/console.c |4
src/console/usbdebug_console.c | 10 +-
src/include/ehci.h |3 ++-
src/include/usbdebug.h |5 -
src/lib/Makefile.inc|1 +
src/lib/usbdebug.c |6 +-
src/southbridge/amd/sb600/Makefile.inc |4 +++-
src/southbridge/amd/sb600/sb600.h |1 -
src/southbridge/amd/sb700/Makefile.inc |4 +++-
src/southbridge/amd/sb700/sb700.h |2 --
src/southbridge/amd/sb800/Makefile.inc |4 +++-
src/southbridge/amd/sb800/sb800.h |1 -
src/southbridge/intel/i82801gx/Makefile.inc |2 ++
src/southbridge/intel/i82801gx/i82801gx.h |1 -
src/southbridge/nvidia/ck804/Makefile.inc |4 +++-
src/southbridge/nvidia/ck804/ck804.h|1 -
src/southbridge/nvidia/mcp55/Makefile.inc |4 +++-
src/southbridge/nvidia/mcp55/mcp55.h|1 -
src/southbridge/sis/sis966/Makefile.inc |5 -
src/southbridge/sis/sis966/sis966.h |4
20 files changed, 34 insertions(+), 33 deletions(-)
diff --git a/src/console/console.c b/src/console/console.c
index a73616e..325170d 100644
--- a/src/console/console.c
+++ b/src/console/console.c
@@ -30,6 +30,10 @@
#include
#endif
+#if CONFIG_USBDEBUG
+#include
+#endif
+
#ifndef __PRE_RAM__
#include
#include
diff --git a/src/console/usbdebug_console.c b/src/console/usbdebug_console.c
index 2270ceb..a624b9d 100644
--- a/src/console/usbdebug_console.c
+++ b/src/console/usbdebug_console.c
@@ -50,15 +50,7 @@ unsigned get_ehci_debug(void)
static void dbgp_init(void)
{
- struct ehci_debug_info *dbg_infox;
-
- /* At this point, all we have to do is copy the fixed address
-* debug_info data structure to our version defined above. */
-
- dbg_infox = (struct ehci_debug_info *)
- ((CONFIG_RAMTOP) - sizeof(struct ehci_debug_info));
-
- memcpy(&dbg_info, dbg_infox, sizeof(struct ehci_debug_info));
+ usbdebug_init(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, &dbg_info);
}
static void dbgp_tx_byte(unsigned char data)
diff --git a/src/include/ehci.h b/src/include/ehci.h
index 4b8c94c..29347f9 100644
--- a/src/include/ehci.h
+++ b/src/include/ehci.h
@@ -25,6 +25,7 @@
#define EHCI_BAR_INDEX 0x10
+#ifndef __ROMCC__
/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
/* Section 2.2 Host Controller Capability Registers */
@@ -199,5 +200,5 @@ struct ehci_dbg_port {
u32 address;
#define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep))
} __attribute__ ((packed));
-
+#endif
#endif
diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h
index 281ccde..a7ab21f 100644
--- a/src/include/usbdebug.h
+++ b/src/include/usbdebug.h
@@ -32,6 +32,8 @@ struct ehci_debug_info {
u32 endpoint_in;
};
+#ifndef __ROMCC__
+void enable_usbdebug(unsigned int port);
int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int
size);
int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size);
void set_ehci_base(unsigned ehci_base);
@@ -40,5 +42,6 @@ unsigned get_ehci_debug(void);
void set_debug_port(unsigned port);
int early_usbdebug_init(void);
void usbdebug_tx_byte(unsigned char data);
-
+int usbdebug_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info
*info);
+#endif
#endif
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index b207ffe..432e24e 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -40,5 +40,6 @@ driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c
smm-y += memcpy.c cbfs.c memset.c memcmp.c
smm-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
+smm-$(CONFIG_USBDEBUG) += usbdebug.c
$(obj)/lib/version.ramstage.o : $(obj)/build.h
diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c
index d022d2f..6b75acf 100644
--- a/src/lib/usbdebug.c
+++ b/src/lib/usbdebug.c
@@ -238,7 +238,6 @@ int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void
*data, int size)
dbg_info->endpoint_in, data, size);
}
-#ifdef __PRE_RAM__
static void dbgp_mdel
[coreboot] Patch set updated for coreboot: d39d04c Fix usb debug dongle support
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/355
-gerrit
commit d39d04c45dd0a66b7d7349fd38012abe4a5b76bf
Author: Sven Schnelle
Date: Sun Oct 30 09:57:35 2011 +0100
Fix usb debug dongle support
- move enable_usbdebug() declaration to usbdebug.h
- reinitialize debug driver in ramstage, as copying the data
structure from romstage doesn't work right now. This way of copying
data from romstage to ramstage is really board/cpu specific, and is
likely to break often. So don't do it.
Change-Id: I394678ded6679c1803e29eb691b926182bdcab68
Signed-off-by: Sven Schnelle
---
src/console/console.c |4
src/console/usbdebug_console.c | 10 +-
src/include/ehci.h |3 ++-
src/include/usbdebug.h |5 -
src/lib/Makefile.inc|1 +
src/lib/usbdebug.c |6 +-
src/southbridge/amd/sb600/Makefile.inc |4 +++-
src/southbridge/amd/sb600/sb600.h |1 -
src/southbridge/amd/sb700/Makefile.inc |4 +++-
src/southbridge/amd/sb700/sb700.h |2 --
src/southbridge/amd/sb800/Makefile.inc |4 +++-
src/southbridge/amd/sb800/sb800.h |1 -
src/southbridge/intel/i82801gx/Makefile.inc |2 ++
src/southbridge/intel/i82801gx/i82801gx.h |1 -
src/southbridge/nvidia/ck804/Makefile.inc |4 +++-
src/southbridge/nvidia/ck804/ck804.h|1 -
src/southbridge/nvidia/mcp55/Makefile.inc |4 +++-
src/southbridge/nvidia/mcp55/mcp55.h|1 -
src/southbridge/sis/sis966/Makefile.inc |5 -
src/southbridge/sis/sis966/sis966.h |4
20 files changed, 34 insertions(+), 33 deletions(-)
diff --git a/src/console/console.c b/src/console/console.c
index a73616e..325170d 100644
--- a/src/console/console.c
+++ b/src/console/console.c
@@ -30,6 +30,10 @@
#include
#endif
+#if CONFIG_USBDEBUG
+#include
+#endif
+
#ifndef __PRE_RAM__
#include
#include
diff --git a/src/console/usbdebug_console.c b/src/console/usbdebug_console.c
index 2270ceb..a624b9d 100644
--- a/src/console/usbdebug_console.c
+++ b/src/console/usbdebug_console.c
@@ -50,15 +50,7 @@ unsigned get_ehci_debug(void)
static void dbgp_init(void)
{
- struct ehci_debug_info *dbg_infox;
-
- /* At this point, all we have to do is copy the fixed address
-* debug_info data structure to our version defined above. */
-
- dbg_infox = (struct ehci_debug_info *)
- ((CONFIG_RAMTOP) - sizeof(struct ehci_debug_info));
-
- memcpy(&dbg_info, dbg_infox, sizeof(struct ehci_debug_info));
+ usbdebug_init(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, &dbg_info);
}
static void dbgp_tx_byte(unsigned char data)
diff --git a/src/include/ehci.h b/src/include/ehci.h
index 4b8c94c..29347f9 100644
--- a/src/include/ehci.h
+++ b/src/include/ehci.h
@@ -25,6 +25,7 @@
#define EHCI_BAR_INDEX 0x10
+#ifndef __ROMCC__
/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
/* Section 2.2 Host Controller Capability Registers */
@@ -199,5 +200,5 @@ struct ehci_dbg_port {
u32 address;
#define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep))
} __attribute__ ((packed));
-
+#endif
#endif
diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h
index 281ccde..a7ab21f 100644
--- a/src/include/usbdebug.h
+++ b/src/include/usbdebug.h
@@ -32,6 +32,8 @@ struct ehci_debug_info {
u32 endpoint_in;
};
+#ifndef __ROMCC__
+void enable_usbdebug(unsigned int port);
int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int
size);
int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size);
void set_ehci_base(unsigned ehci_base);
@@ -40,5 +42,6 @@ unsigned get_ehci_debug(void);
void set_debug_port(unsigned port);
int early_usbdebug_init(void);
void usbdebug_tx_byte(unsigned char data);
-
+int usbdebug_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info
*info);
+#endif
#endif
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index b207ffe..432e24e 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -40,5 +40,6 @@ driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c
smm-y += memcpy.c cbfs.c memset.c memcmp.c
smm-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
+smm-$(CONFIG_USBDEBUG) += usbdebug.c
$(obj)/lib/version.ramstage.o : $(obj)/build.h
diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c
index d022d2f..6b75acf 100644
--- a/src/lib/usbdebug.c
+++ b/src/lib/usbdebug.c
@@ -238,7 +238,6 @@ int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void
*data, int size)
dbg_info->endpoint_in, data, size);
}
-#ifdef __PRE_RAM__
static void dbgp_mdel
[coreboot] Patch set updated for coreboot: f6e9e81 remove usbdebug.h include from mainboard/romstage code
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/354 -gerrit commit f6e9e81303cac8567ed2fa9e391020dc501fc4d3 Author: Sven Schnelle Date: Sun Oct 30 08:49:43 2011 +0100 remove usbdebug.h include from mainboard/romstage code No romstage is supposed to use usbdebug functions/defines directly, so remove all those includes. The usb code is now called and setup from console code. Change-Id: I9b1120d96f5993303d6b302accc86e14a91f7a9f Signed-off-by: Sven Schnelle --- src/mainboard/amd/bimini_fam10/romstage.c |1 - src/mainboard/amd/dbm690t/romstage.c|1 - src/mainboard/amd/mahogany/romstage.c |1 - src/mainboard/amd/mahogany_fam10/romstage.c |1 - src/mainboard/amd/pistachio/romstage.c |1 - src/mainboard/amd/tilapia_fam10/romstage.c |1 - src/mainboard/asrock/939a785gmh/romstage.c |1 - src/mainboard/asus/m2n-e/romstage.c |1 - src/mainboard/asus/m4a78-em/romstage.c |1 - src/mainboard/asus/m4a785-m/romstage.c |1 - src/mainboard/getac/p470/romstage.c |1 - src/mainboard/gigabyte/ga_2761gxdk/romstage.c |1 - src/mainboard/gigabyte/m57sli/romstage.c|1 - src/mainboard/gigabyte/ma785gmt/romstage.c |1 - src/mainboard/gigabyte/ma78gm/romstage.c|1 - src/mainboard/ibase/mb899/romstage.c|1 - src/mainboard/iei/kino-780am2-fam10/romstage.c |1 - src/mainboard/intel/d945gclf/romstage.c |1 - src/mainboard/jetway/pa78vm5/romstage.c |1 - src/mainboard/kontron/986lcd-m/romstage.c |1 - src/mainboard/kontron/kt690/romstage.c |1 - src/mainboard/lenovo/t60/romstage.c |1 - src/mainboard/lenovo/x60/romstage.c |1 - src/mainboard/msi/ms7260/romstage.c |1 - src/mainboard/msi/ms9652_fam10/romstage.c |1 - src/mainboard/nvidia/l1_2pvv/romstage.c |1 - src/mainboard/roda/rk886ex/romstage.c |1 - src/mainboard/supermicro/h8scm_fam10/romstage.c |1 - src/mainboard/technexion/tim5690/romstage.c |1 - src/mainboard/technexion/tim8690/romstage.c |1 - src/mainboard/tyan/s2912/romstage.c |1 - src/mainboard/tyan/s2912_fam10/romstage.c |1 - 32 files changed, 0 insertions(+), 32 deletions(-) diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 175325e..732e033 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -42,7 +42,6 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include #include "cpu/x86/bist.h" -#include #include "cpu/x86/mtrr/earlymtrr.c" #include #include "northbridge/amd/amdfam10/setup_resource_map.c" diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index f119ec9..66637a8 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -39,7 +39,6 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/early_serial.c" #include -#include #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 5c9d538..104652a 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -39,7 +39,6 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8718f/early_serial.c" -#include #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 4d26ca3..04a9e45 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -43,7 +43,6 @@ #include #include "cpu/x86/bist.h" #include "superio/ite/it8718f/early_serial.c" -#include #include "cpu/x86/mtrr/earlymtrr.c" #include #include "northbridge/amd/amdfam10/setup_resource_map.c" diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index ee00c13..5d6e7a8 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -33,7 +33,6 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/early_serial.c" -#include #include #include "cpu/x86/mtrr/earlymtrr.c"
[coreboot] New patch to review for coreboot: b7ff170 inteltool: Add Intel i63xx I/O Controller Hub
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/356
-gerrit
commit b7ff170a978d5a7d03c5a8c1ef344921b54dad7a
Author: Sven Schnelle
Date: Sun Oct 30 13:30:36 2011 +0100
inteltool: Add Intel i63xx I/O Controller Hub
Change-Id: Iaea7e4d1b206d43661ecb61d2ae517723fb8d008
Signed-off-by: Sven Schnelle
---
util/inteltool/gpio.c | 25 +
util/inteltool/inteltool.c |1 +
util/inteltool/inteltool.h |2 +-
util/inteltool/powermgt.c | 52
util/inteltool/rootcmplx.c |1 +
5 files changed, 80 insertions(+), 1 deletions(-)
diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c
index 6b56ec4..1d48a68 100644
--- a/util/inteltool/gpio.c
+++ b/util/inteltool/gpio.c
@@ -203,6 +203,24 @@ static const io_register_t ich10_gpio_registers[] = {
{ 0x7c, 4, "RESERVED" },
};
+static const io_register_t i631x_gpio_registers[] = {
+ { 0x00, 4, "GPIO_USE_SEL" },
+ { 0x04, 4, "GP_IO_SEL" },
+ { 0x08, 4, "RESERVED" },
+ { 0x0c, 4, "GP_LVL" },
+ { 0x10, 4, "RESERVED" },
+ { 0x14, 4, "RESERVED" },
+ { 0x18, 4, "GPO_BLINK" },
+ { 0x1c, 4, "RESERVED" },
+ { 0x20, 4, "RESERVED" },
+ { 0x24, 4, "RESERVED" },
+ { 0x28, 4, "RESERVED" },
+ { 0x2c, 4, "GPI_INV" },
+ { 0x30, 4, "GPIO_USE_SEL2" },
+ { 0x34, 4, "GP_IO_SEL2" },
+ { 0x38, 4, "GP_LVL2" },
+};
+
int print_gpios(struct pci_dev *sb)
{
int i, size;
@@ -269,6 +287,13 @@ int print_gpios(struct pci_dev *sb)
gpio_registers = ich0_gpio_registers;
size = ARRAY_SIZE(ich0_gpio_registers);
break;
+
+ case PCI_DEVICE_ID_INTEL_I63XX:
+ gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
+ gpio_registers = i631x_gpio_registers;
+ size = ARRAY_SIZE(i631x_gpio_registers);
+ break;
+
case PCI_DEVICE_ID_INTEL_82371XX:
printf("This southbridge has GPIOs in the PM unit.\n");
return 1;
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index 6fab118..488d9f5 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -82,6 +82,7 @@ static const struct {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "82371AB/EB/MB" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X44, "82X38/X48" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I63XX, "Intel 63xx I/O
Controller Hub" },
};
#ifndef __DARWIN__
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index bddd17c..1bfb3d1 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -84,7 +84,7 @@
#define PCI_DEVICE_ID_INTEL_X580x3405
#define PCI_DEVICE_ID_INTEL_SCH_POULSBO0x8100
#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000
-
+#define PCI_DEVICE_ID_INTEL_I63XX 0x2670
/* untested, but almost identical to D-series */
#define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010
diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c
index a2ac32e..4974738 100644
--- a/util/inteltool/powermgt.c
+++ b/util/inteltool/powermgt.c
@@ -550,6 +550,51 @@ static const io_register_t i82371xx_pm_registers[] = {
{ 0x37, 1, "GPOREG 3" },
};
+static const io_register_t i63xx_pm_registers[] = {
+ { 0x00, 2, "PM1_STS" },
+ { 0x02, 2, "PM1_EN" },
+ { 0x04, 4, "PM1_CNT" },
+ { 0x08, 4, "PM1_TMR" },
+ { 0x0c, 4, "RESERVED" },
+ { 0x10, 4, "PROC_CNT" },
+#if DANGEROUS_REGISTERS
+ /* This register returns 0 on read, but reading it may cause
+* the system to enter C2 state, which might hang the system.
+*/
+ { 0x14, 1, "LV2" },
+ { 0x15, 1, "RESERVED" },
+ { 0x16, 2, "RESERVED" },
+#endif
+ { 0x18, 4, "RESERVED" },
+ { 0x1c, 4, "RESERVED" },
+ { 0x20, 4, "RESERVED" },
+ { 0x24, 4, "RESERVED" },
+ { 0x28, 4, "GPE0_STS" },
+ { 0x2C, 4, "GPE0_EN" },
+ { 0x30, 4, "SMI_EN" },
+ { 0x34, 4, "SMI_STS" },
+ { 0x38, 2, "ALT_GP_SMI_EN" },
+ { 0x3a, 2, "ALT_GP_SMI_STS" },
+ { 0x3c, 4, "RESERVED" },
+ { 0x40, 4, "RESERVED" },
+ { 0x44, 2, "DEVACT_STS" },
+ { 0x46, 2, "RESERVED" },
+ { 0x48, 4, "RESERVED&qu
[coreboot] New patch to review for coreboot: aadf4c5 X60/T60: reset baudrate loglevel to sane values
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/459
-gerrit
commit aadf4c5effd7f31579d6105d82a7006d08eeab3e
Author: Sven Schnelle
Date: Mon Nov 28 21:12:11 2011 +0100
X60/T60: reset baudrate loglevel to sane values
Change-Id: Iaf5861e9db0a41a184da6d2e515e3b9afe0655d6
Signed-off-by: Sven Schnelle
---
src/mainboard/lenovo/t60/mainboard.c |4
src/mainboard/lenovo/x60/mainboard.c |4
2 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/lenovo/t60/mainboard.c
b/src/mainboard/lenovo/t60/mainboard.c
index 19ac221..a1de756 100644
--- a/src/mainboard/lenovo/t60/mainboard.c
+++ b/src/mainboard/lenovo/t60/mainboard.c
@@ -90,6 +90,10 @@ static void mainboard_enable(device_t dev)
printk(BIOS_INFO, "Restoring CMOS defaults\n");
set_option("tft_brightness", &(u8[]){ 0xff });
set_option("volume", &(u8[]){ 0x03 });
+ /* set baudrate to 115200 baud */
+ set_option("baud_rate", &(u8[]){ 0x05 });
+ /* set default debug_level (DEFAULT_CONSOLE_LOGLEVEL starts at
1) */
+ set_option("debug_level", &(u8[]) {
CONFIG_DEFAULT_CONSOLE_LOGLEVEL+1 });
set_option("cmos_defaults_loaded", &(u8[]){ 0x01 });
}
}
diff --git a/src/mainboard/lenovo/x60/mainboard.c
b/src/mainboard/lenovo/x60/mainboard.c
index 5bc1dca..ee6ac14 100644
--- a/src/mainboard/lenovo/x60/mainboard.c
+++ b/src/mainboard/lenovo/x60/mainboard.c
@@ -88,6 +88,10 @@ static void mainboard_enable(device_t dev)
printk(BIOS_INFO, "Restoring CMOS defaults\n");
set_option("tft_brightness", &(u8[]){ 0xff });
set_option("volume", &(u8[]){ 0x03 });
+ /* set baudrate to 115200 baud */
+ set_option("baud_rate", &(u8[]){ 0x05 });
+ /* set default debug_level (DEFAULT_CONSOLE_LOGLEVEL starts at
1) */
+ set_option("debug_level", &(u8[]) {
CONFIG_DEFAULT_CONSOLE_LOGLEVEL+1 });
set_option("cmos_defaults_loaded", &(u8[]){ 0x01 });
}
}
--
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[coreboot] New patch to review for coreboot: ed0ebd2 i3100: Add HAVE_HARD_RESET
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/469 -gerrit commit ed0ebd28ba3fcda086dad49b21cf34e97caba310 Author: Sven Schnelle Date: Fri Dec 2 16:33:30 2011 +0100 i3100: Add HAVE_HARD_RESET and remove it from mainboard/intel/mtarvon, as this function is implemented in the southbridge code. Change-Id: Id3669aaf99b96b4a7a965f4957e5de7c365acaa6 Signed-off-by: Sven Schnelle --- src/mainboard/intel/mtarvon/Kconfig |1 - src/southbridge/intel/i3100/Kconfig |1 + 2 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/intel/mtarvon/Kconfig b/src/mainboard/intel/mtarvon/Kconfig index 76477b0..af40cad 100644 --- a/src/mainboard/intel/mtarvon/Kconfig +++ b/src/mainboard/intel/mtarvon/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_I3100 select SOUTHBRIDGE_INTEL_I3100 select SUPERIO_INTEL_I3100 - select HAVE_HARD_RESET select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select UDELAY_TSC diff --git a/src/southbridge/intel/i3100/Kconfig b/src/southbridge/intel/i3100/Kconfig index bcb282d..f2b7923 100644 --- a/src/southbridge/intel/i3100/Kconfig +++ b/src/southbridge/intel/i3100/Kconfig @@ -1,3 +1,4 @@ config SOUTHBRIDGE_INTEL_I3100 bool select IOAPIC + select HAVE_HARD_RESET -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review for coreboot: c18ecfd Lenovo X60/T60: add first_battery setting
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/475
-gerrit
commit c18ecfd8b74b1a38bee90270e36630f9fad74b98
Author: Sven Schnelle
Date: Wed Dec 7 14:30:58 2011 -0800
Lenovo X60/T60: add first_battery setting
The EC allows to select the order in which batteries are (dis)charged.
Make this setting available to the user.
Change-Id: Id2a98192565419dbb53f3a7cf0b2c46b672a3ed8
Signed-off-by: Sven Schnelle
---
src/ec/lenovo/h8/h8.c|9 -
src/mainboard/lenovo/t60/cmos.layout |4 +++-
src/mainboard/lenovo/x60/cmos.layout |3 +++
3 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c
index f81a39c..f20cd38 100644
--- a/src/ec/lenovo/h8/h8.c
+++ b/src/ec/lenovo/h8/h8.c
@@ -104,7 +104,7 @@ int h8_ultrabay_device_present(void)
static void h8_enable(device_t dev)
{
struct ec_lenovo_h8_config *conf = dev->chip_info;
- u8 val;
+ u8 val, tmp;
h8_log_ec_version();
@@ -142,6 +142,13 @@ static void h8_enable(device_t dev)
if (!get_option(&val, "volume"))
ec_write(H8_VOLUME_CONTROL, val);
+
+ if (!get_option(&val, "first_battery")) {
+ tmp = ec_read(H8_CONFIG3);
+ tmp &= ~(1 << 4);
+ tmp |= (val & 1)<< 4;
+ ec_write(H8_CONFIG3, tmp);
+ }
h8_set_audio_mute(0);
}
diff --git a/src/mainboard/lenovo/t60/cmos.layout
b/src/mainboard/lenovo/t60/cmos.layout
index a946b4b..8d9dce4 100644
--- a/src/mainboard/lenovo/t60/cmos.layout
+++ b/src/mainboard/lenovo/t60/cmos.layout
@@ -109,6 +109,7 @@ entries
1060 1 e 1touchpad
1064 8 h 0volume
+1072 1 e 9first_battery
# -
enumerations
@@ -142,7 +143,8 @@ enumerations
7 2 Keep
8 0 No
8 1 Yes
-
+9 0Secondary
+9 1Primary
# -
checksums
diff --git a/src/mainboard/lenovo/x60/cmos.layout
b/src/mainboard/lenovo/x60/cmos.layout
index a157513..cae70cb 100644
--- a/src/mainboard/lenovo/x60/cmos.layout
+++ b/src/mainboard/lenovo/x60/cmos.layout
@@ -109,6 +109,7 @@ entries
1064 8 h 0volume
1072 8 h 0tft_brightness
+1080 1 e 9first_battery
# -
enumerations
@@ -142,6 +143,8 @@ enumerations
7 2 Keep
8 0 No
8 1 Yes
+9 0Secondary
+9 1Primary
# -
checksums
--
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[coreboot] New patch to review for coreboot: 3220062 Add Intel Socket LGA771
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/492
-gerrit
commit 3220062a8c6312889c98688c6cee0ced13e31dbf
Author: Sven Schnelle
Date: Fri Dec 2 16:21:35 2011 +0100
Add Intel Socket LGA771
Change-Id: Iee7d3ff2884d8c43ff1af498160589e551bc9cc8
Signed-off-by: Sven Schnelle
---
src/cpu/intel/Kconfig |1 +
src/cpu/intel/Makefile.inc |1 +
src/cpu/intel/socket_LGA771/Kconfig |7 +++
src/cpu/intel/socket_LGA771/Makefile.inc| 11 +++
src/cpu/intel/socket_LGA771/chip.h |4
src/cpu/intel/socket_LGA771/socket_LGA771.c |7 +++
6 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
index 8cf30c9..31c701c 100644
--- a/src/cpu/intel/Kconfig
+++ b/src/cpu/intel/Kconfig
@@ -28,3 +28,4 @@ source src/cpu/intel/socket_mPGA603/Kconfig
source src/cpu/intel/socket_mPGA604/Kconfig
source src/cpu/intel/socket_PGA370/Kconfig
source src/cpu/intel/socket_441/Kconfig
+source src/cpu/intel/socket_LGA771/Kconfig
diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc
index 93ab7de..274c101 100644
--- a/src/cpu/intel/Makefile.inc
+++ b/src/cpu/intel/Makefile.inc
@@ -16,6 +16,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604
subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370
subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2
subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1
+subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA771) += socket_LGA771
#socket_mPGA604_533Mhz
#socket_mPGA604_800Mhz
diff --git a/src/cpu/intel/socket_LGA771/Kconfig
b/src/cpu/intel/socket_LGA771/Kconfig
new file mode 100644
index 000..0821c3e
--- /dev/null
+++ b/src/cpu/intel/socket_LGA771/Kconfig
@@ -0,0 +1,7 @@
+config CPU_INTEL_SOCKET_LGA771
+ bool
+select CPU_INTEL_MODEL_6FX
+select CPU_INTEL_CORE2
+ select SSE2
+ select MMX
+ select AP_IN_SIPI_WAIT
diff --git a/src/cpu/intel/socket_LGA771/Makefile.inc
b/src/cpu/intel/socket_LGA771/Makefile.inc
new file mode 100644
index 000..319430f
--- /dev/null
+++ b/src/cpu/intel/socket_LGA771/Makefile.inc
@@ -0,0 +1,11 @@
+ramstage-y += socket_LGA771.c
+subdirs-y += ../model_6ex
+subdirs-y += ../model_6fx
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../microcode
+subdirs-y += ../hyperthreading
+
diff --git a/src/cpu/intel/socket_LGA771/chip.h
b/src/cpu/intel/socket_LGA771/chip.h
new file mode 100644
index 000..d3f312e
--- /dev/null
+++ b/src/cpu/intel/socket_LGA771/chip.h
@@ -0,0 +1,4 @@
+extern struct chip_operations cpu_intel_socket_LGA771_ops;
+
+struct cpu_intel_socket_LGA771_config {
+};
diff --git a/src/cpu/intel/socket_LGA771/socket_LGA771.c
b/src/cpu/intel/socket_LGA771/socket_LGA771.c
new file mode 100644
index 000..21a7dc9
--- /dev/null
+++ b/src/cpu/intel/socket_LGA771/socket_LGA771.c
@@ -0,0 +1,7 @@
+#include
+#include "chip.h"
+
+
+struct chip_operations cpu_intel_socket_LGA771_ops = {
+ CHIP_NAME("Socket LGA771 CPU")
+};
--
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[coreboot] New patch to review for coreboot: b21b8b8 Add Supermicro X7DB8 motherboard
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/493
-gerrit
commit b21b8b87eb66058448e8803453bc2ccd51f1f6c2
Author: Sven Schnelle
Date: Fri Dec 2 16:22:44 2011 +0100
Add Supermicro X7DB8 motherboard
Change-Id: I5eaac32a8bafa69a05929cf08d869127b9464661
Signed-off-by: Sven Schnelle
---
src/mainboard/supermicro/Kconfig |4 +
src/mainboard/supermicro/x7db8/Kconfig | 46 +++
src/mainboard/supermicro/x7db8/chip.h| 21 +
src/mainboard/supermicro/x7db8/devicetree.cb | 111 ++
src/mainboard/supermicro/x7db8/mainboard.c | 41 ++
src/mainboard/supermicro/x7db8/romstage.c| 98 +++
6 files changed, 321 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/supermicro/Kconfig b/src/mainboard/supermicro/Kconfig
index 80ffd6a..794aead 100755
--- a/src/mainboard/supermicro/Kconfig
+++ b/src/mainboard/supermicro/Kconfig
@@ -25,6 +25,9 @@ config BOARD_SUPERMICRO_X6DHR_IG2
bool "X6DHR-iG2"
config BOARD_SUPERMICRO_X6DHR_IG
bool "X6DHR-iG"
+config BOARD_SUPERMICRO_X7DB8
+ bool "X7DB8"
+
endchoice
@@ -39,6 +42,7 @@ source "src/mainboard/supermicro/x6dhe_g2/Kconfig"
source "src/mainboard/supermicro/x6dhe_g/Kconfig"
source "src/mainboard/supermicro/x6dhr_ig2/Kconfig"
source "src/mainboard/supermicro/x6dhr_ig/Kconfig"
+source "src/mainboard/supermicro/x7db8/Kconfig"
config MAINBOARD_VENDOR
string
diff --git a/src/mainboard/supermicro/x7db8/Kconfig
b/src/mainboard/supermicro/x7db8/Kconfig
new file mode 100644
index 000..56c616a
--- /dev/null
+++ b/src/mainboard/supermicro/x7db8/Kconfig
@@ -0,0 +1,46 @@
+if BOARD_SUPERMICRO_X7DB8
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_LGA771
+ select SOUTHBRIDGE_INTEL_I3100
+ select NORTHBRIDGE_INTEL_I5000
+ select SUPERIO_WINBOND_W83627HF
+ select MMCONF_SUPPORT
+ select HAVE_OPTION_TABLE
+ select BOARD_ROMSIZE_KB_512
+
+config MAINBOARD_DIR
+ string
+ default supermicro/x7db8
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xffdf8000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x8000
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Supermicro X7DB8"
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xe000
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAX_CPUS
+ int
+ default 8
+
+config MAX_PHYSICAL_CPUS
+ int
+ default 2
+
+endif
diff --git a/src/mainboard/supermicro/x7db8/chip.h
b/src/mainboard/supermicro/x7db8/chip.h
new file mode 100644
index 000..70f9bb4
--- /dev/null
+++ b/src/mainboard/supermicro/x7db8/chip.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+struct mainboard_config {};
diff --git a/src/mainboard/supermicro/x7db8/devicetree.cb
b/src/mainboard/supermicro/x7db8/devicetree.cb
new file mode 100644
index 000..36e4aed
--- /dev/null
+++ b/src/mainboard/supermicro/x7db8/devicetree.cb
@@ -0,0 +1,111 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+## Copyright (C) 2011 Sven Schnelle
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+chip northbridge/intel/i5000
+
+ device lapic_cluster 0 on
+ chip cpu/intel/socket_LGA771
+
[coreboot] New patch to review for coreboot: 3ff84d3 ACPI: remove empty get_cst_entries()
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/496
-gerrit
commit 3ff84d326ee881a4ec2f3995744363d75710cf14
Author: Sven Schnelle
Date: Fri Dec 23 10:29:09 2011 +0100
ACPI: remove empty get_cst_entries()
This function prevents the linker from choosing the right
get_cst_entries(), preventing writing the _CST tables.
Change-Id: I4bc0168aee110171faeaa081f217dfd1536bb821
Signed-off-by: Sven Schnelle
---
src/cpu/intel/speedstep/acpi.c |7 +--
1 files changed, 1 insertions(+), 6 deletions(-)
diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index 8f32e4f..c7ad4f6 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -62,11 +62,6 @@ static int get_fsb(void)
return 200;
}
-int get_cst_entries(struct cst_entry **entries __attribute__((unused)))
-{
- return 0;
-}
-
void generate_cpu_entries(void)
{
int len_pr, len_ps;
@@ -89,7 +84,7 @@ void generate_cpu_entries(void)
len_pr =
acpigen_write_processor((cpuID-1)*cores_per_package+coreID-1, pcontrol_blk,
plen);
len_pr += acpigen_write_empty_PCT();
len_pr +=
acpigen_write_PSD_package(cpuID-1,cores_per_package,SW_ANY);
- if ((count = get_cst_entries(&cst_entries)) > 0)
+ if (get_cst_entries && (count =
get_cst_entries(&cst_entries)) > 0)
len_pr +=
acpigen_write_CST_package(cst_entries, count);
len_pr += acpigen_write_name("_PSS");
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review for coreboot: 2ae66cb inteltool: Add support for dumping AMB registers
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/525
-gerrit
commit 2ae66cb092deb642a0d22ed80f73d3411a51c696
Author: Sven Schnelle
Date: Sun Jan 8 15:27:18 2012 +0100
inteltool: Add support for dumping AMB registers
Change-Id: I98615725afdb315caa67b2226224e3eb2a0e4393
Signed-off-by: Sven Schnelle
---
util/inteltool/Makefile|2 +-
util/inteltool/amb.c | 469
util/inteltool/inteltool.c | 16 ++-
util/inteltool/inteltool.h |6 +
4 files changed, 490 insertions(+), 3 deletions(-)
diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile
index db7fca0..6a01173 100644
--- a/util/inteltool/Makefile
+++ b/util/inteltool/Makefile
@@ -27,7 +27,7 @@ PREFIX = /usr/local
CFLAGS = -O2 -g -Wall -W
LDFLAGS = -lpci -lz
-OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o
+OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o amb.o
OS_ARCH= $(shell uname)
ifeq ($(OS_ARCH), Darwin)
diff --git a/util/inteltool/amb.c b/util/inteltool/amb.c
new file mode 100644
index 000..a3ee01d
--- /dev/null
+++ b/util/inteltool/amb.c
@@ -0,0 +1,469 @@
+/*
+ * inteltool - dump all registers on an Intel CPU + chipset based system.
+ *
+ * Copyright (C) 2012 Sven Schnelle
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+
+#include
+#include
+#include "inteltool.h"
+
+#define AMB_CONFIG_SPACE_SIZE 0x2
+
+#define AMB_ADDR(base, fn, reg) (base | ((fn & 7) << 8) | ((reg & 0xff)))
+
+static uint32_t amb_read_config32(volatile void *base, int fn, int reg)
+{
+ return *(uint32_t *)(AMB_ADDR((uint64_t)base, fn, reg));
+}
+
+static void amb_printreg32(volatile void *base, int fn, int reg,
+ const char *name, int printzero)
+{
+ uint32_t val = amb_read_config32(base, fn, reg);
+ if (!val && !printzero)
+ return;
+ printf("%d:%2.2x %-16.16s: 0x%08x\n", fn, reg, name, val);
+}
+
+static uint16_t amb_read_config16(volatile void *base, int fn, int reg)
+{
+ return *(uint16_t *)(AMB_ADDR((uint64_t)base, fn, reg));
+}
+
+static void amb_printreg16(volatile void *base, int fn, int reg,
+ const char *name, int printzero)
+{
+ uint16_t val = amb_read_config16(base, fn, reg);
+ if (!val && !printzero)
+ return;
+ printf("%d:%2.2x %-16.16s: 0x%04x\n", fn, reg, name, val);
+
+}
+
+static uint8_t amb_read_config8(volatile void *base, int fn, int reg)
+{
+ return *(uint8_t *)(AMB_ADDR((uint64_t)base, fn, reg));
+}
+
+static void amb_printreg8(volatile void *base, int fn, int reg,
+ const char *name, int printzero)
+{
+ uint8_t val = amb_read_config8(base, fn, reg);
+ if (!val && !printzero)
+ return;
+ printf("%d:%2.2x %-16.16s: 0x%02x\n", fn, reg, name, val);
+
+}
+
+static void amb_printreg24(volatile void *base, int fn, int reg,
+ const char *name, int printzero)
+{
+ uint32_t val;
+
+ if (reg & 1) {
+ val = amb_read_config8(base, fn, reg) |
+ (amb_read_config16(base, fn, reg + 1) << 8);
+ } else {
+ val = amb_read_config16(base, fn, reg) |
+ (amb_read_config8(base, fn, reg + 2) << 16);
+ }
+
+ if (!val && !printzero)
+ return;
+
+ printf("%d:%2.2x %-16.16s: 0x%06x\n", fn, reg, name, val);
+}
+
+
+struct amb_register {
+ int fn;
+ int offset;
+ const char *name;
+ void (*printfunc)(volatile void *, int, int, const char *, int);
+ int width;
+} amb_registers[] = {
+ { 0, 0x00, "VID", NULL, 2 },
+ { 0, 0x02, "DID", NULL, 2 },
+ { 0, 0x08, "RID", NULL, 1 },
+ { 0, 0x09, "CCR", NULL, 3 },
+ { 0, 0x0e, "HDR", NULL, 1 },
+ { 1, 0x40, "FBDS0", NULL, 1 },
+ { 1, 0x41, "FBDS1", NULL, 1 },
+ { 1, 0x42, "FBDS2", NULL, 1 },
+ { 1, 0x43, "FBDS3", NULL, 1 },
+ { 1, 0x50, "FBDSBCFGCUR", NULL, 1 },
+
[coreboot] Patch set updated for coreboot: 0b00a17 ACPI: mark empty get_cst_entries() weak
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/496
-gerrit
commit 0b00a17cc8276a4ebfbe645d5e66888460b75327
Author: Sven Schnelle
Date: Fri Dec 23 10:29:09 2011 +0100
ACPI: mark empty get_cst_entries() weak
This function prevents the linker from choosing the right
get_cst_entries(), preventing writing the _CST tables.
Change-Id: I4bc0168aee110171faeaa081f217dfd1536bb821
Signed-off-by: Sven Schnelle
Signed-off-by: Patrick Georgi
---
src/arch/x86/include/arch/acpigen.h |2 +-
src/cpu/intel/speedstep/acpi.c |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/arch/x86/include/arch/acpigen.h
b/src/arch/x86/include/arch/acpigen.h
index 0833371..9dc9675 100644
--- a/src/arch/x86/include/arch/acpigen.h
+++ b/src/arch/x86/include/arch/acpigen.h
@@ -66,6 +66,6 @@ int acpigen_write_resourcetemplate_footer(int len);
int acpigen_write_mainboard_resource_template(void);
int acpigen_write_mainboard_resources(const char *scope, const char *name);
-int get_cst_entries(struct cst_entry **) __attribute__((weak));
+int get_cst_entries(struct cst_entry **);
#endif
diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index 8f32e4f..00c4ae9 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -62,7 +62,7 @@ static int get_fsb(void)
return 200;
}
-int get_cst_entries(struct cst_entry **entries __attribute__((unused)))
+int __attribute__((weak)) get_cst_entries(struct cst_entry **entries
__attribute__((unused)))
{
return 0;
}
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review for coreboot: 1ab750f MTRR: get physical address size from CPUID
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/529
-gerrit
commit 1ab750f693375752956642bfc7615954e2942d11
Author: Sven Schnelle
Date: Tue Jan 10 12:01:43 2012 +0100
MTRR: get physical address size from CPUID
The current code uses static values for the physical address size
supported by a CPU. This isn't always the right value: I.e. on
model_6[ef]x Core (2) Duo CPUs physical address size is 36, while
Xeons from the same family have 38 bits, which results in invalid
MTRR setup. Fix this by getting the right number from CPUID.
Change-Id: If019c3d9147c3b86357f0ef0d9fda94d49d811ca
Signed-off-by: Sven Schnelle
---
src/cpu/intel/ep80579/ep80579_init.c |2 +-
src/cpu/intel/model_1067x/model_1067x_init.c |2 +-
src/cpu/intel/model_106cx/model_106cx_init.c |2 +-
src/cpu/intel/model_65x/model_65x_init.c |2 +-
src/cpu/intel/model_67x/model_67x_init.c |2 +-
src/cpu/intel/model_68x/model_68x_init.c |2 +-
src/cpu/intel/model_69x/model_69x_init.c |2 +-
src/cpu/intel/model_6bx/model_6bx_init.c |2 +-
src/cpu/intel/model_6dx/model_6dx_init.c |2 +-
src/cpu/intel/model_6ex/model_6ex_init.c |2 +-
src/cpu/intel/model_6fx/model_6fx_init.c |2 +-
src/cpu/intel/model_6xx/model_6xx_init.c |2 +-
src/cpu/intel/model_f0x/model_f0x_init.c |2 +-
src/cpu/intel/model_f1x/model_f1x_init.c |2 +-
src/cpu/intel/model_f2x/model_f2x_init.c |2 +-
src/cpu/intel/model_f3x/model_f3x_init.c |2 +-
src/cpu/intel/model_f4x/model_f4x_init.c |2 +-
src/cpu/via/model_c3/model_c3_init.c |2 +-
src/cpu/via/model_c7/model_c7_init.c |2 +-
src/cpu/x86/mtrr/mtrr.c |8 ++--
src/include/cpu/x86/mtrr.h |2 +-
21 files changed, 26 insertions(+), 22 deletions(-)
diff --git a/src/cpu/intel/ep80579/ep80579_init.c
b/src/cpu/intel/ep80579/ep80579_init.c
index 2f47158..8b7dba0 100644
--- a/src/cpu/intel/ep80579/ep80579_init.c
+++ b/src/cpu/intel/ep80579/ep80579_init.c
@@ -41,7 +41,7 @@ static void ep80579_init(device_t dev)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
- x86_setup_mtrrs(36);
+ x86_setup_mtrrs();
x86_mtrr_check();
/* Update the microcode */
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c
b/src/cpu/intel/model_1067x/model_1067x_init.c
index ca2b960..c6d716d 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -197,7 +197,7 @@ static void model_1067x_init(device_t cpu)
#endif
/* Setup MTRRs */
- x86_setup_mtrrs(36);
+ x86_setup_mtrrs();
x86_mtrr_check();
#if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c
b/src/cpu/intel/model_106cx/model_106cx_init.c
index 1199315..4bf2924 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -158,7 +158,7 @@ static void model_106cx_init(device_t cpu)
#endif
/* Setup MTRRs */
- x86_setup_mtrrs(32);
+ x86_setup_mtrrs();
x86_mtrr_check();
#if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_65x/model_65x_init.c
b/src/cpu/intel/model_65x/model_65x_init.c
index ef97597..285bacd 100644
--- a/src/cpu/intel/model_65x/model_65x_init.c
+++ b/src/cpu/intel/model_65x/model_65x_init.c
@@ -65,7 +65,7 @@ static void model_65x_init(device_t dev)
/* Turn on caching if we haven't already */
x86_enable_cache();
- x86_setup_mtrrs(36);
+ x86_setup_mtrrs();
x86_mtrr_check();
/* Enable the local cpu apics */
diff --git a/src/cpu/intel/model_67x/model_67x_init.c
b/src/cpu/intel/model_67x/model_67x_init.c
index 0c9b3d2..d34e4da 100644
--- a/src/cpu/intel/model_67x/model_67x_init.c
+++ b/src/cpu/intel/model_67x/model_67x_init.c
@@ -54,7 +54,7 @@ static void model_67x_init(device_t cpu)
x86_enable_cache();
/* Setup MTRRs */
- x86_setup_mtrrs(36);
+ x86_setup_mtrrs();
x86_mtrr_check();
/* Enable the local cpu apics */
diff --git a/src/cpu/intel/model_68x/model_68x_init.c
b/src/cpu/intel/model_68x/model_68x_init.c
index 7244693..fa35e55 100644
--- a/src/cpu/intel/model_68x/model_68x_init.c
+++ b/src/cpu/intel/model_68x/model_68x_init.c
@@ -85,7 +85,7 @@ static void model_68x_init(device_t cpu)
#endif
/* Setup MTRRs */
- x86_setup_mtrrs(36);
+ x86_setup_mtrrs();
x86_mtrr_check();
#if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_69x/model_69x_init.c
b/src/cpu/intel/model_69x/model_69x_init.c
index db8e661..cb805ae 100644
--- a/src/cpu/intel/model_69x/model_69x_init.c
+++ b/src/cpu/intel/model_69x/model_69x_init.c
@@ -25,7 +25,7 @@ static void model_69x_in
[coreboot] Patch set updated for coreboot: 8d9a8bc MTRR: get physical address size from CPUID
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/529
-gerrit
commit 8d9a8bc05374b79360ec627df203306e21ae5c1e
Author: Sven Schnelle
Date: Tue Jan 10 12:01:43 2012 +0100
MTRR: get physical address size from CPUID
The current code uses static values for the physical address size
supported by a CPU. This isn't always the right value: I.e. on
model_6[ef]x Core (2) Duo CPUs physical address size is 36, while
Xeons from the same family have 38 bits, which results in invalid
MTRR setup. Fix this by getting the right number from CPUID.
Change-Id: If019c3d9147c3b86357f0ef0d9fda94d49d811ca
Signed-off-by: Sven Schnelle
---
src/arch/x86/include/arch/cpu.h |2 ++
src/arch/x86/lib/cpu.c | 20
src/cpu/intel/ep80579/ep80579_init.c |2 +-
src/cpu/intel/model_1067x/model_1067x_init.c |2 +-
src/cpu/intel/model_106cx/model_106cx_init.c |2 +-
src/cpu/intel/model_65x/model_65x_init.c |2 +-
src/cpu/intel/model_67x/model_67x_init.c |2 +-
src/cpu/intel/model_68x/model_68x_init.c |2 +-
src/cpu/intel/model_69x/model_69x_init.c |2 +-
src/cpu/intel/model_6bx/model_6bx_init.c |2 +-
src/cpu/intel/model_6dx/model_6dx_init.c |2 +-
src/cpu/intel/model_6ex/model_6ex_init.c |2 +-
src/cpu/intel/model_6fx/model_6fx_init.c |2 +-
src/cpu/intel/model_6xx/model_6xx_init.c |2 +-
src/cpu/intel/model_f0x/model_f0x_init.c |2 +-
src/cpu/intel/model_f1x/model_f1x_init.c |2 +-
src/cpu/intel/model_f2x/model_f2x_init.c |2 +-
src/cpu/intel/model_f3x/model_f3x_init.c |2 +-
src/cpu/intel/model_f4x/model_f4x_init.c |2 +-
src/cpu/via/model_c3/model_c3_init.c |2 +-
src/cpu/via/model_c7/model_c7_init.c |2 +-
src/cpu/x86/mtrr/mtrr.c |8 ++--
src/include/cpu/x86/mtrr.h |2 +-
23 files changed, 48 insertions(+), 22 deletions(-)
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 4d7be86..8089dd5 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -22,6 +22,8 @@
#define X86_EFLAGS_VIP 0x0010 /* Virtual Interrupt Pending */
#define X86_EFLAGS_ID 0x0020 /* CPUID detection flag */
+int cpu_phys_address_size(void);
+
struct cpuid_result {
uint32_t eax;
uint32_t ebx;
diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c
index 3732ae2..aaa0a16 100644
--- a/src/arch/x86/lib/cpu.c
+++ b/src/arch/x86/lib/cpu.c
@@ -131,6 +131,26 @@ static const char *cpu_vendor_name(int vendor)
return name;
}
+static int cpu_cpuid_extended_level(void)
+{
+ return cpuid_eax(0x8000);
+}
+
+#define CPUID_FEATURE_PAE (1 << 6)
+#define CPUID_FEATURE_PSE36 (1 << 17)
+
+int cpu_phys_address_size(void)
+{
+ if (!(have_cpuid_p()))
+ return 32;
+
+ if (cpu_cpuid_extended_level() > 0x8008)
+ return cpuid_eax(0x8008) & 0xff;
+
+ if (cpuid_eax(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36))
+ return 36;
+ return 32;
+}
static void identify_cpu(struct device *cpu)
{
char vendor_name[16];
diff --git a/src/cpu/intel/ep80579/ep80579_init.c
b/src/cpu/intel/ep80579/ep80579_init.c
index 2f47158..8b7dba0 100644
--- a/src/cpu/intel/ep80579/ep80579_init.c
+++ b/src/cpu/intel/ep80579/ep80579_init.c
@@ -41,7 +41,7 @@ static void ep80579_init(device_t dev)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
- x86_setup_mtrrs(36);
+ x86_setup_mtrrs();
x86_mtrr_check();
/* Update the microcode */
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c
b/src/cpu/intel/model_1067x/model_1067x_init.c
index ca2b960..c6d716d 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -197,7 +197,7 @@ static void model_1067x_init(device_t cpu)
#endif
/* Setup MTRRs */
- x86_setup_mtrrs(36);
+ x86_setup_mtrrs();
x86_mtrr_check();
#if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c
b/src/cpu/intel/model_106cx/model_106cx_init.c
index 1199315..4bf2924 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -158,7 +158,7 @@ static void model_106cx_init(device_t cpu)
#endif
/* Setup MTRRs */
- x86_setup_mtrrs(32);
+ x86_setup_mtrrs();
x86_mtrr_check();
#if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_65x/model_65x_init.c
b/src/cpu/intel/model_65x/model_65x_init.c
index ef97597..285bacd 100644
--- a/src/cpu/intel/model_65x/model_65x_init.c
+++ b/src/cpu/intel/model_65x/model_65x_init.c
@@ -65,7 +65,7 @@ static
[coreboot] New patch to review for coreboot: 6b3747f i945: fix tsc udelay()
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/530
-gerrit
commit 6b3747fcc1a57223a25b60e391dc9c1db9ddbbdd
Author: Sven Schnelle
Date: Tue Jan 10 12:16:38 2012 +0100
i945: fix tsc udelay()
The comparision is the wrong way round: as long as tsc
is below tsc1, the timeout is not reached
Change-Id: I75de74ef750b5a45be0156efaf10d7239a0b1136
Signed-off-by: Sven Schnelle
---
src/northbridge/intel/i945/udelay.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/northbridge/intel/i945/udelay.c
b/src/northbridge/intel/i945/udelay.c
index 6b3882b..9170335 100644
--- a/src/northbridge/intel/i945/udelay.c
+++ b/src/northbridge/intel/i945/udelay.c
@@ -78,7 +78,7 @@ void udelay(u32 us)
do {
tsc = rdtsc();
- } while ((tsc.hi > tsc1.hi)
-|| ((tsc.hi == tsc1.hi) && (tsc.lo > tsc1.lo)));
+ } while ((tsc.hi < tsc1.hi)
+|| ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
}
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch set updated for coreboot: a311aff MTRR: get physical address size from CPUID
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/529
-gerrit
commit a311aff916acb0ee221b599f2cc3a707c9b6761f
Author: Sven Schnelle
Date: Tue Jan 10 12:01:43 2012 +0100
MTRR: get physical address size from CPUID
The current code uses static values for the physical address size
supported by a CPU. This isn't always the right value: I.e. on
model_6[ef]x Core (2) Duo CPUs physical address size is 36, while
Xeons from the same family have 38 bits, which results in invalid
MTRR setup. Fix this by getting the right number from CPUID.
Change-Id: If019c3d9147c3b86357f0ef0d9fda94d49d811ca
Signed-off-by: Sven Schnelle
---
src/arch/x86/include/arch/cpu.h |3 +++
src/arch/x86/lib/cpu.c | 20
src/cpu/intel/ep80579/ep80579_init.c |2 +-
src/cpu/intel/model_1067x/model_1067x_init.c |2 +-
src/cpu/intel/model_106cx/model_106cx_init.c |2 +-
src/cpu/intel/model_65x/model_65x_init.c |2 +-
src/cpu/intel/model_67x/model_67x_init.c |2 +-
src/cpu/intel/model_68x/model_68x_init.c |2 +-
src/cpu/intel/model_69x/model_69x_init.c |2 +-
src/cpu/intel/model_6bx/model_6bx_init.c |2 +-
src/cpu/intel/model_6dx/model_6dx_init.c |2 +-
src/cpu/intel/model_6ex/model_6ex_init.c |2 +-
src/cpu/intel/model_6fx/model_6fx_init.c |2 +-
src/cpu/intel/model_6xx/model_6xx_init.c |2 +-
src/cpu/intel/model_f0x/model_f0x_init.c |2 +-
src/cpu/intel/model_f1x/model_f1x_init.c |2 +-
src/cpu/intel/model_f2x/model_f2x_init.c |2 +-
src/cpu/intel/model_f3x/model_f3x_init.c |2 +-
src/cpu/intel/model_f4x/model_f4x_init.c |2 +-
src/cpu/via/model_c3/model_c3_init.c |2 +-
src/cpu/via/model_c7/model_c7_init.c |2 +-
src/cpu/x86/mtrr/mtrr.c |8 ++--
src/include/cpu/x86/mtrr.h |2 +-
23 files changed, 49 insertions(+), 22 deletions(-)
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 4d7be86..79f9113 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -22,6 +22,7 @@
#define X86_EFLAGS_VIP 0x0010 /* Virtual Interrupt Pending */
#define X86_EFLAGS_ID 0x0020 /* CPUID detection flag */
+
struct cpuid_result {
uint32_t eax;
uint32_t ebx;
@@ -108,6 +109,8 @@ static inline unsigned int cpuid_edx(unsigned int op)
#if !defined(__PRE_RAM__)
#include
+int cpu_phys_address_size(void);
+
struct cpu_device_id {
unsigned vendor;
unsigned device;
diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c
index 3732ae2..aaa0a16 100644
--- a/src/arch/x86/lib/cpu.c
+++ b/src/arch/x86/lib/cpu.c
@@ -131,6 +131,26 @@ static const char *cpu_vendor_name(int vendor)
return name;
}
+static int cpu_cpuid_extended_level(void)
+{
+ return cpuid_eax(0x8000);
+}
+
+#define CPUID_FEATURE_PAE (1 << 6)
+#define CPUID_FEATURE_PSE36 (1 << 17)
+
+int cpu_phys_address_size(void)
+{
+ if (!(have_cpuid_p()))
+ return 32;
+
+ if (cpu_cpuid_extended_level() > 0x8008)
+ return cpuid_eax(0x8008) & 0xff;
+
+ if (cpuid_eax(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36))
+ return 36;
+ return 32;
+}
static void identify_cpu(struct device *cpu)
{
char vendor_name[16];
diff --git a/src/cpu/intel/ep80579/ep80579_init.c
b/src/cpu/intel/ep80579/ep80579_init.c
index 2f47158..8b7dba0 100644
--- a/src/cpu/intel/ep80579/ep80579_init.c
+++ b/src/cpu/intel/ep80579/ep80579_init.c
@@ -41,7 +41,7 @@ static void ep80579_init(device_t dev)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
- x86_setup_mtrrs(36);
+ x86_setup_mtrrs();
x86_mtrr_check();
/* Update the microcode */
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c
b/src/cpu/intel/model_1067x/model_1067x_init.c
index ca2b960..c6d716d 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -197,7 +197,7 @@ static void model_1067x_init(device_t cpu)
#endif
/* Setup MTRRs */
- x86_setup_mtrrs(36);
+ x86_setup_mtrrs();
x86_mtrr_check();
#if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c
b/src/cpu/intel/model_106cx/model_106cx_init.c
index 1199315..4bf2924 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -158,7 +158,7 @@ static void model_106cx_init(device_t cpu)
#endif
/* Setup MTRRs */
- x86_setup_mtrrs(32);
+ x86_setup_mtrrs();
x86_mtrr_check();
#if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_65x/model_65x_init.c
b/src/cpu
[coreboot] Patch set updated for coreboot: 734bdc3 MTRR: get physical address size from CPUID
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/529
-gerrit
commit 734bdc32fadc41f4e023868495fbc5b2bef562b3
Author: Sven Schnelle
Date: Tue Jan 10 12:01:43 2012 +0100
MTRR: get physical address size from CPUID
The current code uses static values for the physical address size
supported by a CPU. This isn't always the right value: I.e. on
model_6[ef]x Core (2) Duo CPUs physical address size is 36, while
Xeons from the same family have 38 bits, which results in invalid
MTRR setup. Fix this by getting the right number from CPUID.
Change-Id: If019c3d9147c3b86357f0ef0d9fda94d49d811ca
Signed-off-by: Sven Schnelle
---
src/arch/x86/include/arch/cpu.h |2 ++
src/arch/x86/lib/cpu.c | 20
src/cpu/intel/ep80579/ep80579_init.c |2 +-
src/cpu/intel/model_1067x/model_1067x_init.c |2 +-
src/cpu/intel/model_106cx/model_106cx_init.c |2 +-
src/cpu/intel/model_65x/model_65x_init.c |2 +-
src/cpu/intel/model_67x/model_67x_init.c |2 +-
src/cpu/intel/model_68x/model_68x_init.c |2 +-
src/cpu/intel/model_69x/model_69x_init.c |2 +-
src/cpu/intel/model_6bx/model_6bx_init.c |2 +-
src/cpu/intel/model_6dx/model_6dx_init.c |2 +-
src/cpu/intel/model_6ex/model_6ex_init.c |2 +-
src/cpu/intel/model_6fx/model_6fx_init.c |2 +-
src/cpu/intel/model_6xx/model_6xx_init.c |2 +-
src/cpu/intel/model_f0x/model_f0x_init.c |2 +-
src/cpu/intel/model_f1x/model_f1x_init.c |2 +-
src/cpu/intel/model_f2x/model_f2x_init.c |2 +-
src/cpu/intel/model_f3x/model_f3x_init.c |2 +-
src/cpu/intel/model_f4x/model_f4x_init.c |2 +-
src/cpu/via/model_c3/model_c3_init.c |2 +-
src/cpu/via/model_c7/model_c7_init.c |2 +-
src/cpu/x86/mtrr/mtrr.c |8 ++--
src/include/cpu/x86/mtrr.h |2 +-
23 files changed, 48 insertions(+), 22 deletions(-)
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 4d7be86..85357d7 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -108,6 +108,8 @@ static inline unsigned int cpuid_edx(unsigned int op)
#if !defined(__PRE_RAM__)
#include
+int cpu_phys_address_size(void);
+
struct cpu_device_id {
unsigned vendor;
unsigned device;
diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c
index 3732ae2..aaa0a16 100644
--- a/src/arch/x86/lib/cpu.c
+++ b/src/arch/x86/lib/cpu.c
@@ -131,6 +131,26 @@ static const char *cpu_vendor_name(int vendor)
return name;
}
+static int cpu_cpuid_extended_level(void)
+{
+ return cpuid_eax(0x8000);
+}
+
+#define CPUID_FEATURE_PAE (1 << 6)
+#define CPUID_FEATURE_PSE36 (1 << 17)
+
+int cpu_phys_address_size(void)
+{
+ if (!(have_cpuid_p()))
+ return 32;
+
+ if (cpu_cpuid_extended_level() > 0x8008)
+ return cpuid_eax(0x8008) & 0xff;
+
+ if (cpuid_eax(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36))
+ return 36;
+ return 32;
+}
static void identify_cpu(struct device *cpu)
{
char vendor_name[16];
diff --git a/src/cpu/intel/ep80579/ep80579_init.c
b/src/cpu/intel/ep80579/ep80579_init.c
index 2f47158..8b7dba0 100644
--- a/src/cpu/intel/ep80579/ep80579_init.c
+++ b/src/cpu/intel/ep80579/ep80579_init.c
@@ -41,7 +41,7 @@ static void ep80579_init(device_t dev)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
- x86_setup_mtrrs(36);
+ x86_setup_mtrrs();
x86_mtrr_check();
/* Update the microcode */
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c
b/src/cpu/intel/model_1067x/model_1067x_init.c
index ca2b960..c6d716d 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -197,7 +197,7 @@ static void model_1067x_init(device_t cpu)
#endif
/* Setup MTRRs */
- x86_setup_mtrrs(36);
+ x86_setup_mtrrs();
x86_mtrr_check();
#if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c
b/src/cpu/intel/model_106cx/model_106cx_init.c
index 1199315..4bf2924 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -158,7 +158,7 @@ static void model_106cx_init(device_t cpu)
#endif
/* Setup MTRRs */
- x86_setup_mtrrs(32);
+ x86_setup_mtrrs();
x86_mtrr_check();
#if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_65x/model_65x_init.c
b/src/cpu/intel/model_65x/model_65x_init.c
index ef97597..285bacd 100644
--- a/src/cpu/intel/model_65x/model_65x_init.c
+++ b/src/cpu/intel/model_65x/model_65x_init.c
@@ -65,7 +65,7 @@ static void model_65x_init(device_t dev)
[coreboot] New patch to review for coreboot: d5dad6a Add missing HAVE_HARD_RESET
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/531 -gerrit commit d5dad6a629c2cbe3a5a3d36bb9596ad4e86bc3ed Author: Sven Schnelle Date: Fri Dec 2 16:26:02 2011 +0100 Add missing HAVE_HARD_RESET Change-Id: I6b612dbd3eb6e8cc45f1c7abca85732fb64de98c Signed-off-by: Sven Schnelle --- src/southbridge/intel/esb6300/Kconfig |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/southbridge/intel/esb6300/Kconfig b/src/southbridge/intel/esb6300/Kconfig index 0ef9db5..01f719e 100644 --- a/src/southbridge/intel/esb6300/Kconfig +++ b/src/southbridge/intel/esb6300/Kconfig @@ -1,3 +1,4 @@ config SOUTHBRIDGE_INTEL_ESB6300 bool select IOAPIC + select HAVE_HARD_RESET -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review for coreboot: 616b146 lib: add ram_check_nodie
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/532
-gerrit
commit 616b146ce9c61753407b061c18a687807e4ba238
Author: Sven Schnelle
Date: Fri Dec 2 16:23:06 2011 +0100
lib: add ram_check_nodie
The current implementation calls die() if memory checking fails.
This isn't always what we want: one might want to print error registers,
or do some other error handling. Introduce ram_check_nodie() for that
reason. It returns 0 if ram check succeeded, otherwise 1.
Change-Id: Ib9a9279120755cf63b5b3ba5e0646492c3c29ac2
Signed-off-by: Sven Schnelle
---
src/include/lib.h |1 +
src/lib/ramtest.c | 40 +---
2 files changed, 38 insertions(+), 3 deletions(-)
diff --git a/src/include/lib.h b/src/include/lib.h
index ba9684a..bbe735f 100644
--- a/src/include/lib.h
+++ b/src/include/lib.h
@@ -37,6 +37,7 @@ void move_gdt(void);
/* Defined in src/lib/ramtest.c */
void ram_check(unsigned long start, unsigned long stop);
+int ram_check_nodie(unsigned long start, unsigned long stop);
void quick_ram_check(void);
/* Defined in romstage.c */
diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c
index b35c36d..e118062 100644
--- a/src/lib/ramtest.c
+++ b/src/lib/ramtest.c
@@ -83,7 +83,7 @@ static void ram_fill(unsigned long start, unsigned long stop)
#endif
}
-static void ram_verify(unsigned long start, unsigned long stop)
+static int ram_verify_nodie(unsigned long start, unsigned long stop)
{
unsigned long addr;
int i = 0;
@@ -146,15 +146,17 @@ static void ram_verify(unsigned long start, unsigned long
stop)
#else
print_debug("\nDRAM did _NOT_ verify!\n");
#endif
- die("DRAM ERROR");
+ return 1;
}
else {
#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "\nDRAM range verified.\n");
#else
print_debug("\nDRAM range verified.\n");
+ return 0;
#endif
}
+ return 0;
}
@@ -177,12 +179,44 @@ void ram_check(unsigned long start, unsigned long stop)
ram_fill(start, stop);
/* Make sure we don't read before we wrote */
phys_memory_barrier();
- ram_verify(start, stop);
+ if (ram_verify_nodie(start, stop))
+ die("DRAM ERROR");
+#if !defined(__ROMCC__)
+ printk(BIOS_DEBUG, "Done.\n");
+#else
+ print_debug("Done.\n");
+#endif
+}
+
+
+int ram_check_nodie(unsigned long start, unsigned long stop)
+{
+ int ret;
+ /*
+* This is much more of a "Is my DRAM properly configured?"
+* test than a "Is my DRAM faulty?" test. Not all bits
+* are tested. -Tyson
+*/
+#if !defined(__ROMCC__)
+ printk(BIOS_DEBUG, "Testing DRAM : %08lx - %08lx\n", start, stop);
+#else
+ print_debug("Testing DRAM : ");
+ print_debug_hex32(start);
+ print_debug("-");
+ print_debug_hex32(stop);
+ print_debug("\n");
+#endif
+ ram_fill(start, stop);
+ /* Make sure we don't read before we wrote */
+ phys_memory_barrier();
+ ret = ram_verify_nodie(start, stop);
+
#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "Done.\n");
#else
print_debug("Done.\n");
#endif
+ return ret;
}
void quick_ram_check(void)
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review for coreboot: 20a412d W83627HF: remove unused function
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/533
-gerrit
commit 20a412d99c1a2f2c95a7c5db997c4f6a570a4d1c
Author: Sven Schnelle
Date: Tue Jan 10 22:33:01 2012 +0100
W83627HF: remove unused function
When CONFIG_EXPERT is set, compilation fails with:
src/superio/winbond/w83627hf/superio.c:61:13: error:
‘w83627hf_16_bit_addr_qual’ defined but not used [-Werror=unused-function]
cc1: all warnings being treated as errors
This function isn't used in the code, so just remove it.
Change-Id: I117e221fb3c3a20a7d7e7e2e86d7dbfdffc2cbff
Signed-off-by: Sven Schnelle
---
src/superio/winbond/w83627hf/superio.c | 14 --
1 files changed, 0 insertions(+), 14 deletions(-)
diff --git a/src/superio/winbond/w83627hf/superio.c
b/src/superio/winbond/w83627hf/superio.c
index 8ecec62..1d1b169 100644
--- a/src/superio/winbond/w83627hf/superio.c
+++ b/src/superio/winbond/w83627hf/superio.c
@@ -57,20 +57,6 @@ static u8 pnp_read_index(u16 port, u8 reg)
return inb(port + 1);
}
-#if CONFIG_EXPERT
-static void w83627hf_16_bit_addr_qual(device_t dev)
-{
- u8 reg8;
-
- /* Enable 16 bit address qualification. */
- pnp_enter_ext_func_mode(dev);
- reg8 = pnp_read_config(dev, 0x24);
- reg8 |= (1 << 7);
- pnp_write_config(dev, 0x24, reg8);
- pnp_exit_ext_func_mode(dev);
-}
-#endif
-
static void enable_hwm_smbus(device_t dev)
{
u8 reg8;
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review for coreboot: 715643f X60/T60: fix default baudrate
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/592
-gerrit
commit 715643ffb2595fb7efb8f6d59fff2dd9634a9a96
Author: Sven Schnelle
Date: Tue Jan 31 12:33:01 2012 +0100
X60/T60: fix default baudrate
Value required to get 115200 is actually 0, not 5.
Change-Id: Id1385822bf2213c035c4f378a72168ed6676ad03
Signed-off-by: Sven Schnelle
---
src/mainboard/lenovo/t60/mainboard.c |2 +-
src/mainboard/lenovo/x60/mainboard.c |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/lenovo/t60/mainboard.c
b/src/mainboard/lenovo/t60/mainboard.c
index a1de756..1817b4b 100644
--- a/src/mainboard/lenovo/t60/mainboard.c
+++ b/src/mainboard/lenovo/t60/mainboard.c
@@ -91,7 +91,7 @@ static void mainboard_enable(device_t dev)
set_option("tft_brightness", &(u8[]){ 0xff });
set_option("volume", &(u8[]){ 0x03 });
/* set baudrate to 115200 baud */
- set_option("baud_rate", &(u8[]){ 0x05 });
+ set_option("baud_rate", &(u8[]){ 0x00 });
/* set default debug_level (DEFAULT_CONSOLE_LOGLEVEL starts at
1) */
set_option("debug_level", &(u8[]) {
CONFIG_DEFAULT_CONSOLE_LOGLEVEL+1 });
set_option("cmos_defaults_loaded", &(u8[]){ 0x01 });
diff --git a/src/mainboard/lenovo/x60/mainboard.c
b/src/mainboard/lenovo/x60/mainboard.c
index ee6ac14..89ac489 100644
--- a/src/mainboard/lenovo/x60/mainboard.c
+++ b/src/mainboard/lenovo/x60/mainboard.c
@@ -89,7 +89,7 @@ static void mainboard_enable(device_t dev)
set_option("tft_brightness", &(u8[]){ 0xff });
set_option("volume", &(u8[]){ 0x03 });
/* set baudrate to 115200 baud */
- set_option("baud_rate", &(u8[]){ 0x05 });
+ set_option("baud_rate", &(u8[]){ 0x00 });
/* set default debug_level (DEFAULT_CONSOLE_LOGLEVEL starts at
1) */
set_option("debug_level", &(u8[]) {
CONFIG_DEFAULT_CONSOLE_LOGLEVEL+1 });
set_option("cmos_defaults_loaded", &(u8[]){ 0x01 });
--
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[coreboot] New patch to review for coreboot: d2086a2 X60/T60: Disable Self refresh check
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/596 -gerrit commit d2086a2879a16b23a726bf361e8a160b5d5495e8 Author: Sven Schnelle Date: Tue Jan 31 14:54:13 2012 +0100 X60/T60: Disable Self refresh check commit faa6bebeaa2dbdacb9333d20e5a2f6f52b21a3f0 introduced CHECK_SLFRCS_ON_RESUME to explicit tell coreboot on what Boards to check for self refresh status. This check is not working on X60/T60, so remove those Kconfig options. Change-Id: I9e5d918d6dd1f88737b09252ed3a3d8e44357823 Signed-off-by: Sven Schnelle --- src/mainboard/lenovo/t60/Kconfig |1 - src/mainboard/lenovo/x60/Kconfig |1 - 2 files changed, 0 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 1e4afd1..d1abcf6 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945GM - select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_NSC_PC87382 select SUPERIO_NSC_PC87384 diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 64a3761..69f83a8 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945GM - select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_RICOH_RL5C476 select SUPERIO_NSC_PC87382 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review for coreboot: 53fe1f9 X60: fix docking
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/597
-gerrit
commit 53fe1f939c9f1b5ac8787c61f7c2fb285c3933fc
Author: Sven Schnelle
Date: Tue Jan 10 14:44:12 2012 +0100
X60: fix docking
Fix ordering of power/reset/undock procedure to prevent
crashes seen with the old code. Also call dlpc_init()
only once.
Change-Id: I27d1f42e845fcccde40e6ca5af4a7762edab5d36
Signed-off-by: Sven Schnelle
---
src/mainboard/lenovo/x60/dock.c | 33 +++--
src/mainboard/lenovo/x60/mainboard_smi.c |5 ++-
src/mainboard/lenovo/x60/romstage.c |4 +-
3 files changed, 26 insertions(+), 16 deletions(-)
diff --git a/src/mainboard/lenovo/x60/dock.c b/src/mainboard/lenovo/x60/dock.c
index eed00a1..37d5b76 100644
--- a/src/mainboard/lenovo/x60/dock.c
+++ b/src/mainboard/lenovo/x60/dock.c
@@ -107,6 +107,15 @@ int dlpc_init(void)
/* Activate DLPC */
dlpc_write_register(0x30, 0x01);
+ dlpc_gpio_init();
+
+ return 0;
+}
+
+int dock_connect(void)
+{
+ int timeout = 1000;
+
outb(0x07, 0x164c);
timeout = 1000;
@@ -121,26 +130,18 @@ int dlpc_init(void)
return 1;
}
- dlpc_gpio_init();
-
- return 0;
-}
-
-int dock_connect(void)
-{
- int timeout = 1000;
-
/* Assert D_PLTRST# */
outb(0xfe, 0x1680);
udelay(10);
/* Deassert D_PLTRST# */
outb(0xff, 0x1680);
- udelay(1000);
+ udelay(10);
/* startup 14.318MHz Clock */
dock_write_register(0x29, 0x06);
/* wait until clock is settled */
+ timeout = 1000;
while(!(dock_read_register(0x29) & 0x08) && timeout--)
udelay(1000);
@@ -243,12 +244,20 @@ int dock_connect(void)
void dock_disconnect(void)
{
- /* disable Ultrabay and USB Power */
- outb(0x00, 0x1628);
+ printk(BIOS_DEBUG, "%s enter\n", __func__);
/* disconnect LPC bus */
outb(0x00, 0x164c);
+ udelay(1);
+
/* Assert PLTRST and DLPCPD */
outb(0xfc, 0x1680);
+ udelay(1);
+
+ /* disable Ultrabay and USB Power */
+ outb(0x00, 0x1628);
+ udelay(1);
+
+ printk(BIOS_DEBUG, "%s finish\n", __func__);
}
int dock_present(void)
diff --git a/src/mainboard/lenovo/x60/mainboard_smi.c
b/src/mainboard/lenovo/x60/mainboard_smi.c
index 34f1d36..bd1333a 100644
--- a/src/mainboard/lenovo/x60/mainboard_smi.c
+++ b/src/mainboard/lenovo/x60/mainboard_smi.c
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
#include "dock.h"
#include "smi.h"
@@ -72,8 +73,8 @@ int mainboard_io_trap_handler(int smif)
switch (smif) {
case SMI_DOCK_CONNECT:
ec_clr_bit(0x03, 2);
- dlpc_init();
- if (!dlpc_init() && !dock_connect()) {
+ udelay(25);
+ if (!dock_connect()) {
ec_set_bit(0x03, 2);
/* set dock LED to indicate status */
ec_write(0x0c, 0x09);
diff --git a/src/mainboard/lenovo/x60/romstage.c
b/src/mainboard/lenovo/x60/romstage.c
index 44cde72..ee080ea 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -229,12 +229,12 @@ void main(unsigned long bist)
ich7_enable_lpc();
-
+ dlpc_init();
/* dock_init initializes the DLPC switch on
* thinpad side, so this is required even
* if we're undocked.
*/
- if (!dlpc_init() && dock_present()) {
+ if (dock_present()) {
dock_connect();
early_superio_config();
/* Set up the console */
--
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[coreboot] New patch to review for coreboot: 6e8ae90 X60/T60: Add option to enable/disable bluetooth
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/598
-gerrit
commit 6e8ae90bbb68e1caa9e0c55e30bc66c5e2fe2007
Author: Sven Schnelle
Date: Tue Jan 31 17:41:12 2012 +0100
X60/T60: Add option to enable/disable bluetooth
Change-Id: I9761a8a9a7cc708fe95169cb8b79b413b97ee523
Signed-off-by: Sven Schnelle
---
src/ec/lenovo/h8/h8.c| 11 +++
src/mainboard/lenovo/t60/cmos.layout |1 +
src/mainboard/lenovo/x60/cmos.layout |1 +
3 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c
index f20cd38..ecd34b2 100644
--- a/src/ec/lenovo/h8/h8.c
+++ b/src/ec/lenovo/h8/h8.c
@@ -27,6 +27,14 @@
#include "chip.h"
#include
+static void h8_bluetooth_enable(int on)
+{
+ if (on)
+ ec_set_bit(0x3a, 4);
+ else
+ ec_clr_bit(0x3a, 4);
+}
+
void h8_trackpoint_enable(int on)
{
ec_write(H8_TRACKPOINT_CTRL,
@@ -143,6 +151,9 @@ static void h8_enable(device_t dev)
ec_write(H8_VOLUME_CONTROL, val);
+ if (!get_option(&val, "bluetooth"))
+ h8_bluetooth_enable(val);
+
if (!get_option(&val, "first_battery")) {
tmp = ec_read(H8_CONFIG3);
tmp &= ~(1 << 4);
diff --git a/src/mainboard/lenovo/t60/cmos.layout
b/src/mainboard/lenovo/t60/cmos.layout
index 8d9dce4..7539b60 100644
--- a/src/mainboard/lenovo/t60/cmos.layout
+++ b/src/mainboard/lenovo/t60/cmos.layout
@@ -108,6 +108,7 @@ entries
1052 4 r 0C1DRT1
1060 1 e 1touchpad
+10611 e 1bluetooth
1064 8 h 0volume
1072 1 e 9first_battery
# -
diff --git a/src/mainboard/lenovo/x60/cmos.layout
b/src/mainboard/lenovo/x60/cmos.layout
index cae70cb..ab51a84 100644
--- a/src/mainboard/lenovo/x60/cmos.layout
+++ b/src/mainboard/lenovo/x60/cmos.layout
@@ -110,6 +110,7 @@ entries
1064 8 h 0volume
1072 8 h 0tft_brightness
1080 1 e 9first_battery
+10811 e 1bluetooth
# -
enumerations
--
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[coreboot] New patch to review for coreboot: 9f73df7 X86: fix cpu_phys_address_size()
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/599 -gerrit commit 9f73df7837c00d07a4f29527c2d10308d708209b Author: Sven Schnelle Date: Tue Jan 31 22:10:28 2012 +0100 X86: fix cpu_phys_address_size() CPUs with CPUID level >= 0x8008 can return the number of physical address bits. Change-Id: I1c0523b6a091c476af838d173ed9030280360d7f Signed-off-by: Sven Schnelle --- src/arch/x86/lib/cpu.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index aaa0a16..ada57e2 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -144,7 +144,7 @@ int cpu_phys_address_size(void) if (!(have_cpuid_p())) return 32; - if (cpu_cpuid_extended_level() > 0x8008) + if (cpu_cpuid_extended_level() >= 0x8008) return cpuid_eax(0x8008) & 0xff; if (cpuid_eax(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36)) -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review for coreboot: 00d2638 i3100: Add init sequence
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/600 -gerrit commit 00d263825b8deaddd8a6bf573bc97fb625f22bdf Author: Sven Schnelle Date: Tue Jan 31 22:40:50 2012 +0100 i3100: Add init sequence i3100 misses the magic SATA init sequence, which makes all requests fail. Captured from the vendor BIOS, which writes those bits on all configurations. Change-Id: I293b7d9cd681181311ecaced6d7df9b2706c711f Signed-off-by: Sven Schnelle --- src/southbridge/intel/i3100/sata.c | 18 ++ 1 files changed, 18 insertions(+), 0 deletions(-) diff --git a/src/southbridge/intel/i3100/sata.c b/src/southbridge/intel/i3100/sata.c index af22600..1925f88 100644 --- a/src/southbridge/intel/i3100/sata.c +++ b/src/southbridge/intel/i3100/sata.c @@ -81,6 +81,24 @@ static void sata_init(struct device *dev) pci_write_config8(dev, SATA_PCS + 1, 0x0f); } + + /* secret init sequence, required */ + pci_write_config32(dev, 0x94, 0x00400180); + pci_write_config32(dev, 0xa0, 0x18); + pci_write_config32(dev, 0xa4, 0x224); + pci_write_config32(dev, 0xa0, 0x42); + pci_write_config32(dev, 0xa4, 0x22006d); + pci_write_config32(dev, 0xa0, 0x84); + pci_write_config32(dev, 0xa4, 0x24); + pci_write_config32(dev, 0xa0, 0x7a); + pci_write_config32(dev, 0xa4, 0x22); + pci_write_config32(dev, 0xa0, 0x9c); + pci_write_config32(dev, 0xa4, 0x24); + pci_write_config32(dev, 0xa0, 0x90); + pci_write_config32(dev, 0xa4, 0x22); + pci_write_config32(dev, 0xa0, 0xa0); + pci_write_config32(dev, 0xa4, 0x12492aa); + printk(BIOS_DEBUG, "SATA Enabled\n"); } -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review for coreboot: cb54abe i3100: add sata_ports_implemented option
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/601
-gerrit
commit cb54abee3ffa57e67f2803a79ed2ce8a612fa2b9
Author: Sven Schnelle
Date: Tue Jan 31 22:44:53 2012 +0100
i3100: add sata_ports_implemented option
BIOS needs to set the bit mask which ports are iplemented on the
board. Without setting this option, seabios fails to boot from
SATA.
Change-Id: I21de3fde3a9cff7c590226f70fa549274f36e2a8
Signed-off-by: Sven Schnelle
---
src/southbridge/intel/i3100/chip.h |1 +
src/southbridge/intel/i3100/sata.c | 11 ++-
2 files changed, 11 insertions(+), 1 deletions(-)
diff --git a/src/southbridge/intel/i3100/chip.h
b/src/southbridge/intel/i3100/chip.h
index f35e4a8..7e58674 100644
--- a/src/southbridge/intel/i3100/chip.h
+++ b/src/southbridge/intel/i3100/chip.h
@@ -43,6 +43,7 @@ struct southbridge_intel_i3100_config
/* GPIO use select */
u8 gpio[64];
+ int sata_ports_implemented;
u32 pirq_a_d;
u32 pirq_e_h;
};
diff --git a/src/southbridge/intel/i3100/sata.c
b/src/southbridge/intel/i3100/sata.c
index 1925f88..2341ca1 100644
--- a/src/southbridge/intel/i3100/sata.c
+++ b/src/southbridge/intel/i3100/sata.c
@@ -31,7 +31,14 @@ typedef struct southbridge_intel_i3100_config config_t;
static void sata_init(struct device *dev)
{
-u8 ahci;
+ u8 ahci;
+ u32 *ahci_bar;
+ config_t *config = dev->chip_info;
+
+ if (config == NULL) {
+ printk(BIOS_ERR, "i3100_sata: error: device not in
devicetree.cb!\n");
+ return;
+ }
/* Get the chip configuration */
ahci = (pci_read_config8(dev, SATA_MAP) >> 6) & 0x03;
@@ -58,6 +65,8 @@ static void sata_init(struct device *dev)
/* IDE I/O configuration */
pci_write_config32(dev, SATA_IIOC, 0);
+ ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff);
+ ahci_bar[3] = config->sata_ports_implemented;
} else {
/* SATA configuration */
pci_write_config8(dev, SATA_CMD, 0x07);
--
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[coreboot] New patch to review for coreboot: f81d7bd i3100: configure pci irqs
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/603
-gerrit
commit f81d7bd250944c585a0cdcdf614f4ba4878b22db
Author: Sven Schnelle
Date: Wed Feb 1 11:47:29 2012 +0100
i3100: configure pci irqs
without it, you can't boot from PCI devices like scsi controllers
which require an interrupt set. So preconfigure all pci devices.
Change-Id: I2cd781227701e8363d83bd90e0e36994359fc194
Signed-off-by: Sven Schnelle
---
src/southbridge/intel/i3100/lpc.c | 46 +---
1 files changed, 42 insertions(+), 4 deletions(-)
diff --git a/src/southbridge/intel/i3100/lpc.c
b/src/southbridge/intel/i3100/lpc.c
index 1544ecd..2dcdb04 100644
--- a/src/southbridge/intel/i3100/lpc.c
+++ b/src/southbridge/intel/i3100/lpc.c
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
#include
#include
#include "i3100.h"
@@ -196,17 +197,51 @@ static void set_i3100_gpio_inv(
static void i3100_pirq_init(device_t dev)
{
+ device_t irq_dev;
config_t *config;
/* Get the chip configuration */
config = dev->chip_info;
- if(config->pirq_a_d) {
+ if(config->pirq_a_d)
pci_write_config32(dev, 0x60, config->pirq_a_d);
- }
- if(config->pirq_e_h) {
+
+ if(config->pirq_e_h)
pci_write_config32(dev, 0x68, config->pirq_e_h);
- }
+
+for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+u8 int_pin=0, int_line=0;
+
+if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
+continue;
+
+int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
+switch (int_pin) {
+case 1: /* INTA# */
+ int_line = config->pirq_a_d & 0xff;
+ break;
+
+case 2: /* INTB# */
+ int_line = (config->pirq_a_d >> 8) & 0xff;
+ break;
+
+ case 3: /* INTC# */
+ int_line = (config->pirq_a_d >> 16) & 0xff;
+ break;
+
+case 4: /* INTD# */
+ int_line = (config->pirq_a_d >> 24) & 0xff;
+ break;
+}
+
+if (!int_line)
+continue;
+
+ printk(BIOS_DEBUG, "%s: irq pin %d, irq line %d\n",
dev_path(irq_dev), int_pin, int_line);
+pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
+}
+
+
}
static void i3100_power_options(device_t dev) {
@@ -343,6 +378,9 @@ static void lpc_init(struct device *dev)
/* Initialize isa dma */
isa_dma_init();
+
+ setup_i8259();
+ i8259_configure_irq_trigger(9, 1);
}
static void i3100_lpc_read_resources(device_t dev)
--
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[coreboot] New patch to review for coreboot: e5ce5d2 i5000: halt second BSP
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/615 -gerrit commit e5ce5d2160acc69fae296c1fcf89f2c12dadd1e3 Author: Sven Schnelle Date: Thu Feb 9 21:05:20 2012 +0100 i5000: halt second BSP If both FSBs on i5000 are equipped with CPU packages, one CPU from each package is elected as BSP. To prevent races between both BSPs, hlt the second BSP. Change-Id: I6bfcb17d34e9f028280acff1694309e37307ec21 Signed-off-by: Sven Schnelle --- src/northbridge/intel/i5000/Makefile.inc |1 + src/northbridge/intel/i5000/halt_second_bsp.S | 23 +++ 2 files changed, 24 insertions(+), 0 deletions(-) diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc index a5623c0..0c3ce0d 100644 --- a/src/northbridge/intel/i5000/Makefile.inc +++ b/src/northbridge/intel/i5000/Makefile.inc @@ -19,3 +19,4 @@ driver-y += northbridge.c romstage-y += raminit.c udelay.c +cpu_incs += src/northbridge/intel/i5000/halt_second_bsp.S \ No newline at end of file diff --git a/src/northbridge/intel/i5000/halt_second_bsp.S b/src/northbridge/intel/i5000/halt_second_bsp.S new file mode 100644 index 000..da13178 --- /dev/null +++ b/src/northbridge/intel/i5000/halt_second_bsp.S @@ -0,0 +1,23 @@ + /* Save BIST result */ + + movl%eax, %ebp + + /* Read the semaphore register of i5000 (BOFL0). + If it returns zero, it means there was already + another read by another CPU */ + + movl$0x800080c0, %eax + movw$0xcf8, %dx + outl%eax, %dx + + addw$4, %dx + inl %dx, %eax + cmp $0, %eax + jne 1f + + cli + hlt +tloop: jmp tloop + +1: /* Restore BIST */ + mov %ebp, %eax -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch set updated for coreboot: 8c64567 i5000: halt second BSP
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/615 -gerrit commit 8c64567a2309229fba3a891fe15b0d55da2ff0b0 Author: Sven Schnelle Date: Thu Feb 9 21:05:20 2012 +0100 i5000: halt second BSP If both FSBs on i5000 are equipped with CPU packages, one CPU from each package is elected as BSP. To prevent races between both BSPs, hlt the second BSP. Change-Id: I6bfcb17d34e9f028280acff1694309e37307ec21 Signed-off-by: Sven Schnelle --- src/northbridge/intel/i5000/Makefile.inc |1 + src/northbridge/intel/i5000/halt_second_bsp.S | 29 + 2 files changed, 30 insertions(+), 0 deletions(-) diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc index a5623c0..5e75159 100644 --- a/src/northbridge/intel/i5000/Makefile.inc +++ b/src/northbridge/intel/i5000/Makefile.inc @@ -19,3 +19,4 @@ driver-y += northbridge.c romstage-y += raminit.c udelay.c +cpu_incs += src/northbridge/intel/i5000/halt_second_bsp.S diff --git a/src/northbridge/intel/i5000/halt_second_bsp.S b/src/northbridge/intel/i5000/halt_second_bsp.S new file mode 100644 index 000..4d52224 --- /dev/null +++ b/src/northbridge/intel/i5000/halt_second_bsp.S @@ -0,0 +1,29 @@ + /* Save BIST result */ + + movl%eax, %ebp + + /* Read the semaphore register of i5000 (BOFL0). + If it returns zero, it means there was already + another read by another CPU */ + + movl$0x800080c0, %eax + movw$0xcf8, %dx + outl%eax, %dx + + addw$4, %dx + inl %dx, %eax + cmp $0, %eax + jne 1f + + /* degrade BSP to AP */ + mov $0x1b, %ecx + rdmsr + andl $(~0x100), %eax + wrmsr + + cli + hlt +tloop: jmp tloop + +1: /* Restore BIST */ + mov %ebp, %eax -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch set updated for coreboot: 74c0819 i5000: halt second BSP
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/615 -gerrit commit 74c0819a95be57196d9f25aebbf9f61aa8114749 Author: Sven Schnelle Date: Thu Feb 9 21:05:20 2012 +0100 i5000: halt second BSP If both FSBs on i5000 are equipped with CPU packages, one CPU from each package is elected as BSP. To prevent races between both BSPs, hlt the second BSP. Change-Id: I6bfcb17d34e9f028280acff1694309e37307ec21 Signed-off-by: Sven Schnelle --- src/northbridge/intel/i5000/Makefile.inc |1 + src/northbridge/intel/i5000/halt_second_bsp.S | 29 + 2 files changed, 30 insertions(+), 0 deletions(-) diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc index a5623c0..5e75159 100644 --- a/src/northbridge/intel/i5000/Makefile.inc +++ b/src/northbridge/intel/i5000/Makefile.inc @@ -19,3 +19,4 @@ driver-y += northbridge.c romstage-y += raminit.c udelay.c +cpu_incs += src/northbridge/intel/i5000/halt_second_bsp.S diff --git a/src/northbridge/intel/i5000/halt_second_bsp.S b/src/northbridge/intel/i5000/halt_second_bsp.S new file mode 100644 index 000..a1a1b15 --- /dev/null +++ b/src/northbridge/intel/i5000/halt_second_bsp.S @@ -0,0 +1,29 @@ + /* Save BIST result */ + + movl%eax, %ebp + + /* Read the semaphore register of i5000 (BOFL0). + If it returns zero, it means there was already + another read by another CPU */ + + movl$0x800080c0, %eax + movw$0xcf8, %dx + outl%eax, %dx + + addw$4, %dx + inl %dx, %eax + cmp $0, %eax + jne 1f + + /* degrade BSP to AP */ + mov $0x1b, %ecx + rdmsr + andl $(~0x100), %eax + wrmsr + + cli +loop: hlt + jmp loop + +1: /* Restore BIST */ + mov %ebp, %eax -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review for coreboot: be0e1ca Remove non-existent include
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/619 -gerrit commit be0e1ca4c628ec4ae65f43fa28a035441ad0ebb3 Author: Sven Schnelle Date: Fri Feb 10 14:36:27 2012 +0100 Remove non-existent include Change-Id: I702d59371b4a57ce22623cbab6e936b653d57edf Signed-off-by: Sven Schnelle --- src/northbridge/intel/i5000/raminit.c |1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c index 95610ce..139a33c 100644 --- a/src/northbridge/intel/i5000/raminit.c +++ b/src/northbridge/intel/i5000/raminit.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review: 46cc5bc CMOS: add set_option()
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at
http://review.coreboot.org/23
-gerrit
commit 46cc5bc80381e9ef4d1bde0a02e0e0e953f6900f
Author: Sven Schnelle
Date: Mon Jun 6 15:58:54 2011 +0200
CMOS: add set_option()
Change-Id: I584189d9fcf7c9b831d9c020ee7ed59bb5ae08e8
Signed-off-by: Sven Schnelle
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index 7be552d..fda437f 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -109,9 +109,11 @@ static inline void cmos_write(unsigned char val, unsigned char addr)
#if !defined(__ROMCC__)
void rtc_init(int invalid);
#if CONFIG_USE_OPTION_TABLE
+int set_option(const char *name, void *val);
int get_option(void *dest, const char *name);
unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def);
#else
+int set_option(const char *name __attribute__((unused)), void *val __attribute__((unused))) { return -2; };
static inline int get_option(void *dest __attribute__((unused)),
const char *name __attribute__((unused))) { return -2; }
static inline unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def)
diff --git a/src/pc80/mc146818rtc.c b/src/pc80/mc146818rtc.c
index 5850ec6..50543d2 100644
--- a/src/pc80/mc146818rtc.c
+++ b/src/pc80/mc146818rtc.c
@@ -252,4 +252,74 @@ int get_option(void *dest, const char *name)
return(-4);
return(0);
}
+
+static int set_cmos_value(unsigned long bit, unsigned long length, void *vret)
+{
+ unsigned char *ret;
+ unsigned long byte,byte_bit;
+ unsigned long i;
+ unsigned char uchar, mask;
+ unsigned int chksum_update_needed = 0;
+
+ ret = vret;
+ byte = bit / 8; /* find the byte where the data starts */
+ byte_bit = bit % 8; /* find the bit in the byte where the data starts */
+ if(length <= 8) { /* one byte or less */
+ mask = (1 << length) - 1;
+ mask <<= byte_bit;
+
+ uchar = cmos_read(byte);
+ uchar &= ~mask;
+ uchar |= (ret[0] << byte_bit);
+ cmos_write(uchar, byte);
+ if (byte >= PC_CKS_RANGE_START && byte <= PC_CKS_RANGE_END)
+ chksum_update_needed = 1;
+ } else { /* more that one byte so transfer the whole bytes */
+ for(i=0; length; i++, length-=8, byte++)
+ cmos_write(ret[i], byte);
+ if (byte >= PC_CKS_RANGE_START && byte <= PC_CKS_RANGE_END)
+chksum_update_needed = 1;
+ }
+
+ if (chksum_update_needed) {
+ rtc_set_checksum(PC_CKS_RANGE_START,
+ PC_CKS_RANGE_END,PC_CKS_LOC);
+ }
+ return 0;
+}
+
+
+int set_option(const char *name, void *value)
+{
+ struct cmos_option_table *ct;
+ struct cmos_entries *ce;
+ size_t namelen;
+ int found=0;
+
+ /* Figure out how long name is */
+ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH);
+
+ /* find the requested entry record */
+ ct=cbfs_find_file("cmos_layout.bin", CBFS_COMPONENT_CMOS_LAYOUT);
+ if (!ct) {
+ printk(BIOS_ERR, "cmos_layout.bin could not be found. Options are disabled\n");
+ return(-2);
+ }
+ ce=(struct cmos_entries*)((unsigned char *)ct + ct->header_length);
+ for(;ce->tag==LB_TAG_OPTION;
+ ce=(struct cmos_entries*)((unsigned char *)ce + ce->size)) {
+ if (memcmp(ce->name, name, namelen) == 0) {
+ found=1;
+ break;
+ }
+ }
+ if(!found) {
+ printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name);
+ return(-2);
+ }
+
+ if(set_cmos_value(ce->bit, ce->length, value))
+ return(-3);
+ return(0);
+}
#endif /* CONFIG_USE_OPTION_TABLE */
--
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[coreboot] New patch to review: 0645233 i945 GMA: restore tft brightness from cmos
Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at
http://review.coreboot.org/24
-gerrit
commit 064523307500960ef9f4f583755db418256783cd
Author: Sven Schnelle
Date: Sun Jun 12 14:30:10 2011 +0200
i945 GMA: restore tft brightness from cmos
Change-Id: Iaf10f125425a1abcf17ffca1d6e246f955f941cc
Signed-off-by: Sven Schnelle
diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout
index a946b4b..b5e3e2c 100644
--- a/src/mainboard/lenovo/t60/cmos.layout
+++ b/src/mainboard/lenovo/t60/cmos.layout
@@ -109,6 +109,7 @@ entries
1060 1 e 1touchpad
1064 8 h 0volume
+1072 8 h 0tft_brightness
# -
enumerations
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index b659aa8..11283fc 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -336,6 +336,4 @@ void main(unsigned long bist)
pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
}
#endif
- /* Set legacy Brightness control to full brightness */
- pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, 0xff);
}
diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout
index 1875e59..b6914c8 100644
--- a/src/mainboard/lenovo/x60/cmos.layout
+++ b/src/mainboard/lenovo/x60/cmos.layout
@@ -107,7 +107,9 @@ entries
1048 4 r 0C0DRT1
1052 4 r 0C1DRT1
+# keep those offsets in sync with ACPI code!
1064 8 h 0volume
+1072 8 h 0tft_brightness
# -
enumerations
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 9d01bf2..6219da4 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -338,6 +338,4 @@ void main(unsigned long bist)
pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
}
#endif
- /* Set legacy Brightness control to full brightness */
- pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, 0xff);
}
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index a43ef25..340ddcd 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
static void gma_func0_init(struct device *dev)
{
@@ -36,11 +37,17 @@ static void gma_func0_init(struct device *dev)
static void gma_func1_init(struct device *dev)
{
u32 reg32;
+ u8 val;
/* IGD needs to be Bus Master, also enable IO accesss */
reg32 = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, reg32 |
PCI_COMMAND_MASTER | PCI_COMMAND_IO);
+
+ if (!get_option(&val, "tft_brightness"))
+ pci_write_config8(dev, 0xf4, val);
+ else
+ pci_write_config8(dev, 0xf4, 0xff);
}
static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
--
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