RE: [PATCH] DAxx: export da8xx_syscfg0_base

[Nori, Sekhar]

Hi Sergei,

On Mon, May 03, 2010 at 21:52:18, Sergei Shtylyov wrote:
 Hello

 Kevin Hilman wrote:

  Hi Sergei,
 
  [...]
 
 
   void __iomem *da8xx_syscfg0_base;
   void __iomem *da8xx_syscfg1_base;
  +EXPORT_SYMBOL_GPL(da8xx_syscfg0_base);
 
 
  Would it be an overkill to pass as a resource and ioremap in
  usb_hcd_da8xx_probe() instead?
 
 
Passing a resource is certainly an overkill.
 

Do you really want me to pass the single CFGCHIP2 register as a
 resource?! Since the rest of the system config. registers don't belong
 to USB...

You could have platform data callback function pointers
to for the various functionality that CFGCHIP2 provides.

Something like:

pdata-setup_phy_clk()
pdata-phy_{enable|disable}()
...

Future platforms doing these operations in a different manner
can re-define these functions (or not define them at all as the
case may be).

Thanks,
Sekhar

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RE: [RFC 00/22] Davinci: pre-tnetv107x ioremap() cleanup

[Nori, Sekhar]

On Sat, May 01, 2010 at 21:50:03, Chemparathy, Cyril wrote:
 Hi Kevin,

 [...]
  This is something that's been on my TODO for some time and I've been
  ignoring it.   Thanks a ton for tackling it.

 Unless this has been covered elsewhere, what does the davinci TODO list
 look like?  Pet peeves with the code?

The closest information to what you ask for is here: 
http://processors.wiki.ti.com/index.php/DaVinci_GIT_Linux_Kernel

Thanks,
Sekhar

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Re: UBL Question

[Raffaele Recalcati]

I'm defining the situation for ubl+u-boot programming.
First of all I haven't yet found a git tree of ubl.
This is not so nice, because I'd like that ubl project could become better
day by day.

From
http://processors.wiki.ti.com/index.php/SD_card_boot_and_flashing_tool_for_DM355_and_DM365I
can't find a project on ubl.

Any suggestion?
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DM6467 McASP

[Jaya krishnan]

Hi  ,
I want  to use McASP  port  0 for  transmit data  and port 1  to  generate high 
frequency clock (AHCLKX) (to be used as  master clock for  another audio DAC  
in the  system.)  Is there  any  limitation to use  both  ports  
simultaneously?Pls  reply
Regards
JK

 

Jayakrishnan M M
Research Engineer
RD Team-2 , Group-5
Security Solutions  Division
SAMSUNG TECHWIN CO.,LTD

TEL +82-70-7147-8482
FAX +82-31-8018-3712
Mobile +82-10-6409-3619
E-mail:jaya.krish...@samsung.com
 
  
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RE: UBL Question

[Jon Povey]

Raffaele Recalcati wrote:
 I'm defining the situation for ubl+u-boot programming.
 First of all I haven't yet found a git tree of ubl.
 This is not so nice, because I'd like that ubl project could become
 better day by day.

 From
 http://processors.wiki.ti.com/index.php/SD_card_boot_and_flashing_tool_for_DM355_and_DM365
 I can't find a project on ubl.

 Any suggestion?

This would be of great interest to me, too. I need to look into this soon.

There are some pointers to UBL versions here:
http://processors.wiki.ti.com/index.php/RBL_UBL_and_host_program
But I am not aware of any active community UBL. I would be interested in 
contributing to one.

--
Jon Povey
jon.po...@racelogic.co.uk

Racelogic is a limited company registered in England. Registered number 2743719 
.
Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, 
MK18 1TB .

The information contained in this electronic mail transmission is intended by 
Racelogic Ltd for the use of the named individual or entity to which it is 
directed and may contain information that is confidential or privileged. If you 
have received this electronic mail transmission in error, please delete it from 
your system without copying or forwarding it, and notify the sender of the 
error by reply email so that the sender's address records can be corrected. The 
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to monitor e-mail communications passing through its network


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i2c problem with TVP514x

[Andreas Auer]

Hello,

currently I'm using the 2.6.32 kernel from the arago project on a 
customized board similar to the TI EVM with the DM6446 processor. Right 
now, I have an application running which uses the TVP5146 to capture 
video from an analog camera.

The problem is that I'm getting the message:
   tvp514x 1-005d: Write: retry ... 1

I already added the fix to recover the i2c bus. So, after the above 
message the kernel prints:

   i2c_davinci i2c_davinci.1: initiating i2c bus recovery

I get the messages very often! Is it possible that some other i2c 
devices (AIC33, MSP430, KSZ8893M Ethernet Switch) cause this problem??


Thanks,
Andreas

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[PATCH 4/5] davinci: edma: fix coding style issues related to long lines

[Sekhar Nori]

In the edma driver, some lines are broken up at really
odd places to meet the 80 chars per line rule. This make
reading those parts particularly difficult.

This patch fixes that by creating a few lines over 80
characters, but I feel it still improves readability over
what is existing currently.

Here are the checkpatch warnings:

WARNING: line over 80 characters
+   
edma_cc[ctlr]-intr_data[k].data);

WARNING: line over 80 characters
+   if 
(edma_cc[ctlr]-intr_data[k].callback) {

WARNING: line over 80 characters
+   
edma_cc[ctlr]-intr_data[k].callback(k,

WARNING: line over 80 characters
+   
edma_cc[ctlr]-intr_data[k].data);

WARNING: line over 80 characters
+   count  (edma_cc[ctlr]-num_slots - 
edma_cc[ctlr]-num_channels))

Signed-off-by: Sekhar Nori nsek...@ti.com
---
 arch/arm/mach-davinci/dma.c |   22 +-
 1 files changed, 9 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 2734de9..3c89dd8 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -376,10 +376,9 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
edma_shadow0_write_array(ctlr, SH_ICR, j,
(1  i));
if (edma_cc[ctlr]-intr_data[k].callback)
-   edma_cc[ctlr]-intr_data[k].callback(
-   k, DMA_COMPLETE,
-   edma_cc[ctlr]-intr_data[k].
-   data);
+   edma_cc[ctlr]-intr_data[k].callback(k,
+   DMA_COMPLETE,
+   
edma_cc[ctlr]-intr_data[k].data);
}
}
cnt++;
@@ -430,13 +429,10 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
/* Clear any SER */
edma_shadow0_write_array(ctlr, SH_SECR,
j, (1  i));
-   if (edma_cc[ctlr]-intr_data[k].
-   callback) {
-   edma_cc[ctlr]-intr_data[k].
-   callback(k,
-   DMA_CC_ERROR,
-   edma_cc[ctlr]-intr_data
-   [k].data);
+   if 
(edma_cc[ctlr]-intr_data[k].callback) {
+   
edma_cc[ctlr]-intr_data[k].callback(k,
+   DMA_CC_ERROR,
+   
edma_cc[ctlr]-intr_data[k].data);
}
}
}
@@ -825,8 +821,8 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, 
int slot, int count)
 * and cannot be more than the number of slots minus the number of
 * channels
 */
-   if (count  1 || count 
-   (edma_cc[ctlr]-num_slots - edma_cc[ctlr]-num_channels))
+   if (count  1 ||
+   count  (edma_cc[ctlr]-num_slots - 
edma_cc[ctlr]-num_channels))
return -EINVAL;
 
switch (id) {
-- 
1.6.2.4

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[PATCH 3/5] davinci: edma: fix coding style issues related to indentation

[Sekhar Nori]

In the edma driver some if statememnts are broken up such that
the condition code is at the same indentation level as the
statement block. This makes reading it particularly difficult.

This patch fixes that issue.

Signed-off-by: Sekhar Nori nsek...@ti.com
---
 arch/arm/mach-davinci/dma.c |   26 +-
 1 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index cc5fcda..2734de9 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -330,7 +330,7 @@ static int irq2ctlr(int irq)
if (irq = edma_cc[0]-irq_res_start  irq = edma_cc[0]-irq_res_end)
return 0;
else if (irq = edma_cc[1]-irq_res_start 
-   irq = edma_cc[1]-irq_res_end)
+   irq = edma_cc[1]-irq_res_end)
return 1;
 
return -1;
@@ -352,7 +352,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
dev_dbg(data, dma_irq_handler\n);
 
if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0)
-(edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
+(edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
return IRQ_NONE;
 
while (1) {
@@ -406,9 +406,9 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
dev_dbg(data, dma_ccerr_handler\n);
 
if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) 
-   (edma_read_array(ctlr, EDMA_EMR, 1) == 0) 
-   (edma_read(ctlr, EDMA_QEMR) == 0) 
-   (edma_read(ctlr, EDMA_CCERR) == 0))
+   (edma_read_array(ctlr, EDMA_EMR, 1) == 0) 
+   (edma_read(ctlr, EDMA_QEMR) == 0) 
+   (edma_read(ctlr, EDMA_CCERR) == 0))
return IRQ_NONE;
 
while (1) {
@@ -469,9 +469,9 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
}
}
if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0)
-(edma_read_array(ctlr, EDMA_EMR, 1) == 0)
-(edma_read(ctlr, EDMA_QEMR) == 0)
-(edma_read(ctlr, EDMA_CCERR) == 0))
+(edma_read_array(ctlr, EDMA_EMR, 1) == 0)
+(edma_read(ctlr, EDMA_QEMR) == 0)
+(edma_read(ctlr, EDMA_CCERR) == 0))
break;
cnt++;
if (cnt  10)
@@ -773,7 +773,7 @@ void edma_free_slot(unsigned slot)
slot = EDMA_CHAN_SLOT(slot);
 
if (slot  edma_cc[ctlr]-num_channels ||
-   slot = edma_cc[ctlr]-num_slots)
+   slot = edma_cc[ctlr]-num_slots)
return;
 
memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
@@ -816,8 +816,8 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, 
int slot, int count)
 * of slots
 */
if ((id != EDMA_CONT_PARAMS_ANY) 
-   (slot  edma_cc[ctlr]-num_channels ||
-   slot = edma_cc[ctlr]-num_slots))
+   (slot  edma_cc[ctlr]-num_channels ||
+   slot = edma_cc[ctlr]-num_slots))
return -EINVAL;
 
/*
@@ -865,8 +865,8 @@ int edma_free_cont_slots(unsigned slot, int count)
slot = EDMA_CHAN_SLOT(slot);
 
if (slot  edma_cc[ctlr]-num_channels ||
-   slot = edma_cc[ctlr]-num_slots ||
-   count  1)
+   slot = edma_cc[ctlr]-num_slots ||
+   count  1)
return -EINVAL;
 
for (i = slot; i  slot + count; ++i) {
-- 
1.6.2.4

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[PATCH 2/5] davinci: edma: fix coding style issue related to usage of braces

[Sekhar Nori]

In the edma driver, there are couple of instances where braces
are used for a single statement 'if' construct.

There are other instances where 'else' part of the if-else construct
does not use braces even if the 'if' part is a multi-line statement.

This patch fixes both.

Signed-off-by: Sekhar Nori nsek...@ti.com
---
 arch/arm/mach-davinci/dma.c |   15 +++
 1 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index b705089..cc5fcda 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -310,10 +310,9 @@ setup_dma_interrupt(unsigned lch,
ctlr = EDMA_CTLR(lch);
lch = EDMA_CHAN_SLOT(lch);
 
-   if (!callback) {
+   if (!callback)
edma_shadow0_write_array(ctlr, SH_IECR, lch  5,
(1  (lch  0x1f)));
-   }
 
edma_cc[ctlr]-intr_data[lch].callback = callback;
edma_cc[ctlr]-intr_data[lch].data = data;
@@ -376,12 +375,11 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
/* Clear the corresponding IPR bits */
edma_shadow0_write_array(ctlr, SH_ICR, j,
(1  i));
-   if (edma_cc[ctlr]-intr_data[k].callback) {
+   if (edma_cc[ctlr]-intr_data[k].callback)
edma_cc[ctlr]-intr_data[k].callback(
k, DMA_COMPLETE,
edma_cc[ctlr]-intr_data[k].
data);
-   }
}
}
cnt++;
@@ -473,9 +471,8 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0)
 (edma_read_array(ctlr, EDMA_EMR, 1) == 0)
 (edma_read(ctlr, EDMA_QEMR) == 0)
-(edma_read(ctlr, EDMA_CCERR) == 0)) {
+(edma_read(ctlr, EDMA_CCERR) == 0))
break;
-   }
cnt++;
if (cnt  10)
break;
@@ -531,8 +528,9 @@ static int reserve_contiguous_slots(int ctlr, unsigned int 
id,
if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
stop_slot = i;
break;
-   } else
+   } else {
count = num_slots;
+   }
}
}
 
@@ -1402,8 +1400,9 @@ static int __init edma_probe(struct platform_device *pdev)
break;
else
return -ENODEV;
-   } else
+   } else {
found = 1;
+   }
 
len[j] = resource_size(r[j]);
 
-- 
1.6.2.4

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[PATCH 5/5] davinci: edma: use BIT() wherever possible

[Sekhar Nori]

This patch replaces occurences of (1  x) with
BIT(x) as it makes for much better reading.

Signed-off-by: Sekhar Nori nsek...@ti.com
---
 arch/arm/mach-davinci/dma.c |   42 +-
 1 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 3c89dd8..3475058 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -312,16 +312,16 @@ setup_dma_interrupt(unsigned lch,
 
if (!callback)
edma_shadow0_write_array(ctlr, SH_IECR, lch  5,
-   (1  (lch  0x1f)));
+   BIT(lch  0x1f));
 
edma_cc[ctlr]-intr_data[lch].callback = callback;
edma_cc[ctlr]-intr_data[lch].data = data;
 
if (callback) {
edma_shadow0_write_array(ctlr, SH_ICR, lch  5,
-   (1  (lch  0x1f)));
+   BIT(lch  0x1f));
edma_shadow0_write_array(ctlr, SH_IESR, lch  5,
-   (1  (lch  0x1f)));
+   BIT(lch  0x1f));
}
 }
 
@@ -374,7 +374,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
SH_IER, j)  BIT(i))) {
/* Clear the corresponding IPR bits */
edma_shadow0_write_array(ctlr, SH_ICR, j,
-   (1  i));
+   BIT(i));
if (edma_cc[ctlr]-intr_data[k].callback)
edma_cc[ctlr]-intr_data[k].callback(k,
DMA_COMPLETE,
@@ -422,13 +422,13 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
for (i = 0; i  32; i++) {
int k = (j  5) + i;
if (edma_read_array(ctlr, EDMA_EMR, j) 
-   (1  i)) {
+   BIT(i)) {
/* Clear the corresponding EMR bits */
edma_write_array(ctlr, EDMA_EMCR, j,
-   1  i);
+   BIT(i));
/* Clear any SER */
edma_shadow0_write_array(ctlr, SH_SECR,
-   j, (1  i));
+   j, BIT(i));
if 
(edma_cc[ctlr]-intr_data[k].callback) {

edma_cc[ctlr]-intr_data[k].callback(k,
DMA_CC_ERROR,
@@ -440,11 +440,11 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
dev_dbg(data, QEMR %02x\n,
edma_read(ctlr, EDMA_QEMR));
for (i = 0; i  8; i++) {
-   if (edma_read(ctlr, EDMA_QEMR)  (1  i)) {
+   if (edma_read(ctlr, EDMA_QEMR)  BIT(i)) {
/* Clear the corresponding IPR bits */
-   edma_write(ctlr, EDMA_QEMCR, 1  i);
+   edma_write(ctlr, EDMA_QEMCR, BIT(i));
edma_shadow0_write(ctlr, SH_QSECR,
-   (1  i));
+   BIT(i));
 
/* NOTE:  not reported!! */
}
@@ -456,9 +456,9 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
 * to just write CCERRCLR with CCERR value...
 */
for (i = 0; i  8; i++) {
-   if (edma_read(ctlr, EDMA_CCERR)  (1  i)) {
+   if (edma_read(ctlr, EDMA_CCERR)  BIT(i)) {
/* Clear the corresponding IPR bits */
-   edma_write(ctlr, EDMA_CCERRCLR, 1  i);
+   edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
 
/* NOTE:  not reported!! */
}
@@ -662,7 +662,7 @@ int edma_alloc_channel(int channel,
}
 
/* ensure access through shadow region 0 */
-   edma_or_array2(ctlr, EDMA_DRAE, 0, channel  5, 1  (channel  0x1f));
+   edma_or_array2(ctlr, EDMA_DRAE, 0, channel  5, BIT(channel  0x1f));
 
/* ensure no events are pending */

[PATCH 0/5] coding style fixes for edma driver

[Sekhar Nori]

While working on adding resource reservation feature to EDMA
driver, I found some places where the code could be made more
readable. 

The result is this 5 part series which attempts to improve its
readability.

The series is tested on DM6467 EVM using audio playback as edma
usage example.

Sekhar Nori (5):
  davinci: edma: use a more intuitive name for edma_info
  davinci: edma: fix coding style issue related to usage of braces
  davinci: edma: fix coding style issues related to indentation
  davinci: edma: fix coding style issues related to long lines
  davinci: edma: use BIT() wherever possible

 arch/arm/mach-davinci/dma.c |  237 +--
 1 files changed, 114 insertions(+), 123 deletions(-)

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[PATCH 1/5] davinci: edma: use a more intuitive name for edma_info

[Sekhar Nori]

'edma_info' structure inside the edma driver represents
a single instance of edma channel controller. Call it
'edma_cc' instead. This also avoids readers confusing
it with an instance of edma_soc_info structre which
carries the platform data for a single channel controller
instance.

Signed-off-by: Sekhar Nori nsek...@ti.com
---
 arch/arm/mach-davinci/dma.c |  158 +--
 1 files changed, 77 insertions(+), 81 deletions(-)

diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 0bf290b..b705089 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -243,7 +243,7 @@ struct edma {
} intr_data[EDMA_MAX_DMACH];
 };
 
-static struct edma *edma_info[EDMA_MAX_CC];
+static struct edma *edma_cc[EDMA_MAX_CC];
 static int arch_num_cc;
 
 /* dummy param set used to (re)initialize parameter RAM slots */
@@ -261,7 +261,7 @@ static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
 
/* default to low priority queue */
if (queue_no == EVENTQ_DEFAULT)
-   queue_no = edma_info[ctlr]-default_queue;
+   queue_no = edma_cc[ctlr]-default_queue;
 
queue_no = 7;
edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no  3),
@@ -315,8 +315,8 @@ setup_dma_interrupt(unsigned lch,
(1  (lch  0x1f)));
}
 
-   edma_info[ctlr]-intr_data[lch].callback = callback;
-   edma_info[ctlr]-intr_data[lch].data = data;
+   edma_cc[ctlr]-intr_data[lch].callback = callback;
+   edma_cc[ctlr]-intr_data[lch].data = data;
 
if (callback) {
edma_shadow0_write_array(ctlr, SH_ICR, lch  5,
@@ -328,11 +328,10 @@ setup_dma_interrupt(unsigned lch,
 
 static int irq2ctlr(int irq)
 {
-   if (irq = edma_info[0]-irq_res_start 
-   irq = edma_info[0]-irq_res_end)
+   if (irq = edma_cc[0]-irq_res_start  irq = edma_cc[0]-irq_res_end)
return 0;
-   else if (irq = edma_info[1]-irq_res_start 
-   irq = edma_info[1]-irq_res_end)
+   else if (irq = edma_cc[1]-irq_res_start 
+   irq = edma_cc[1]-irq_res_end)
return 1;
 
return -1;
@@ -377,10 +376,10 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
/* Clear the corresponding IPR bits */
edma_shadow0_write_array(ctlr, SH_ICR, j,
(1  i));
-   if (edma_info[ctlr]-intr_data[k].callback) {
-   edma_info[ctlr]-intr_data[k].callback(
+   if (edma_cc[ctlr]-intr_data[k].callback) {
+   edma_cc[ctlr]-intr_data[k].callback(
k, DMA_COMPLETE,
-   edma_info[ctlr]-intr_data[k].
+   edma_cc[ctlr]-intr_data[k].
data);
}
}
@@ -433,12 +432,12 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
/* Clear any SER */
edma_shadow0_write_array(ctlr, SH_SECR,
j, (1  i));
-   if (edma_info[ctlr]-intr_data[k].
+   if (edma_cc[ctlr]-intr_data[k].
callback) {
-   edma_info[ctlr]-intr_data[k].
+   edma_cc[ctlr]-intr_data[k].
callback(k,
DMA_CC_ERROR,
-   edma_info[ctlr]-intr_data
+   edma_cc[ctlr]-intr_data
[k].data);
}
}
@@ -514,9 +513,9 @@ static int reserve_contiguous_slots(int ctlr, unsigned int 
id,
int stop_slot = start_slot;
DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
 
-   for (i = start_slot; i  edma_info[ctlr]-num_slots; ++i) {
+   for (i = start_slot; i  edma_cc[ctlr]-num_slots; ++i) {
j = EDMA_CHAN_SLOT(i);
-   if (!test_and_set_bit(j, edma_info[ctlr]-edma_inuse)) {
+   if (!test_and_set_bit(j, edma_cc[ctlr]-edma_inuse)) {
/* Record our current beginning slot */
if (count == num_slots)
stop_slot = i;
@@ -543,12 +542,12 @@ static int reserve_contiguous_slots(int ctlr, unsigned 
int id,
 * of contiguous parameter RAM slots but do not 

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RE: UBL Question

[Nori, Sekhar]

Hello,

On Tue, May 04, 2010 at 13:48:57, Jon Povey wrote:
 Raffaele Recalcati wrote:
  I'm defining the situation for ubl+u-boot programming.
  First of all I haven't yet found a git tree of ubl.
  This is not so nice, because I'd like that ubl project could become
  better day by day.
 
  From
  http://processors.wiki.ti.com/index.php/SD_card_boot_and_flashing_tool_for_DM355_and_DM365
  I can't find a project on ubl.
 
  Any suggestion?

 This would be of great interest to me, too. I need to look into this soon.

 There are some pointers to UBL versions here:
 http://processors.wiki.ti.com/index.php/RBL_UBL_and_host_program
 But I am not aware of any active community UBL. I would be interested in 
 contributing to one.


There is a sourceforge project for UBL and serial flashing tools:

http://sourceforge.net/projects/dvflashutils/

You could join this project to contribute.

Thanks,
Sekhar

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RE: i2c problem with TVP514x

[Nori, Sekhar]

Hello,

On Tue, May 04, 2010 at 13:57:10, Andreas Auer wrote:
 Hello,

 currently I'm using the 2.6.32 kernel from the arago project on a
 customized board similar to the TI EVM with the DM6446 processor. Right
 now, I have an application running which uses the TVP5146 to capture
 video from an analog camera.
 The problem is that I'm getting the message:
 tvp514x 1-005d: Write: retry ... 1

 I already added the fix to recover the i2c bus. So, after the above
 message the kernel prints:
 i2c_davinci i2c_davinci.1: initiating i2c bus recovery

 I get the messages very often! Is it possible that some other i2c
 devices (AIC33, MSP430, KSZ8893M Ethernet Switch) cause this problem??

I think this can happen because of slave holding
the SCL low for inordinately long periods of time.

Does the problem disappear if the other slaves
aren't accessed at all?

Thanks,
Sekhar
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Re: UBL Question

[Raffaele Recalcati]

Hi Nori,

There is a sourceforge project for UBL and serial flashing tools:

 http://sourceforge.net/projects/dvflashutils/

 You could join this project to contribute.

 Thanks,
 Sekhar


Is this project good also for dm365?



-- 
www.opensurf.it
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Re: [PATCH 3/5] davinci: edma: fix coding style issues related to indentation

[Sergei Shtylyov]

Hello.

Sekhar Nori wrote:

In the edma driver some if statememnts are broken up such that
the condition code is at the same indentation level as the
statement block. This makes reading it particularly difficult.

This patch fixes that issue.

Signed-off-by: Sekhar Nori nsek...@ti.com
---
 arch/arm/mach-davinci/dma.c |   26 +-
 1 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index cc5fcda..2734de9 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -352,7 +352,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
dev_dbg(data, dma_irq_handler\n);
 
 	if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0)

-(edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
  


  IMHO this level of indentation doesn't affect the readability.


+(edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
return IRQ_NONE;
 
 	while (1) {

@@ -406,9 +406,9 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
dev_dbg(data, dma_ccerr_handler\n);
 
 	if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) 

-   (edma_read_array(ctlr, EDMA_EMR, 1) == 0) 
-   (edma_read(ctlr, EDMA_QEMR) == 0) 
-   (edma_read(ctlr, EDMA_CCERR) == 0))
  


  What's up with these too?


+   (edma_read_array(ctlr, EDMA_EMR, 1) == 0) 
+   (edma_read(ctlr, EDMA_QEMR) == 0) 
+   (edma_read(ctlr, EDMA_CCERR) == 0))
  


  Your increased indentation looks rather ugly to me... matter of 
taste, of course.



@@ -469,9 +469,9 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
}
}
if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0)
-(edma_read_array(ctlr, EDMA_EMR, 1) == 0)
-(edma_read(ctlr, EDMA_QEMR) == 0)
-(edma_read(ctlr, EDMA_CCERR) == 0))
  


  Again, I don't find anything bad about this, except I'd put  at the 
end of lines, no at the start...



+(edma_read_array(ctlr, EDMA_EMR, 1) == 0)
+(edma_read(ctlr, EDMA_QEMR) == 0)
+(edma_read(ctlr, EDMA_CCERR) == 0))


WBR, Sergei

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Re: [PATCH] DAxx: export da8xx_syscfg0_base

[Sergei Shtylyov]

Hello.

Kevin Hilman wrote:


Hi Sergei,

[...]
  
  

 void __iomem *da8xx_syscfg0_base;
 void __iomem *da8xx_syscfg1_base;
+EXPORT_SYMBOL_GPL(da8xx_syscfg0_base);



Would it be an overkill to pass as a resource and ioremap in
usb_hcd_da8xx_probe() instead?
  
  

  Passing a resource is certainly an overkill.



  Do you really want me to pass the single CFGCHIP2 register as a
resource?! Since the rest of the system config. registers don't belong
to USB...



Yes.
  
  

  Oh horror... can't the patch be accepted as a short-term fix at least?



Not by me, sorry.

This kind of short-term fix tends to last a really long time, so is
better prevented early.
  


  It's too late to prevent it -- I've already used the 
da8xx_syscfg0_base in the OHCI glue. :-)



Also, I don't see the OHCI driver that uses this variable in mainline
or in linux-next.
  


  Look ar drivers/usb/host/ohci-da8xx.c, it's used via 
DA8XX_SYSCFG0_VIRT() macro.



More specifically I'd rather see this address/region passed in a more
normal way: use a resource, a platform_data callback etc.  Passing
  
  

  Platform data callback won't do -- there is no board specifics here.


  Well, considering that CFGCHIP2 is shared between MUSB and OHCI, 
passing it as a resource is out of question for me. So, platfrom data 
callback has to be considered.



Disagree.

I would much rather see this as a resource than as a global variable.

  

  But it's already a global variable!



Yes, and that will hopefully be remedied that can be fixed after
Cyril's ioremap rework.
  
  

  How Cyril's ioremap() work can help here? You will still need to
ioremap() system config. register range...



Yes, but the base address varible will no longer need to be global
since those DA8XX_SYSCFGx_VIRT() macros can disappear.

Kevin
  


  Ah, you're going tio kill the macros... OHCI glue should stop using 
them before that can happen.


WBR, Sergei

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Re: i2c problem with TVP514x

[Philby John]

On 05/04/2010 01:57 PM, Andreas Auer wrote:

Hello,

currently I'm using the 2.6.32 kernel from the arago project on a
customized board similar to the TI EVM with the DM6446 processor. Right
now, I have an application running which uses the TVP5146 to capture
video from an analog camera.
The problem is that I'm getting the message:
tvp514x 1-005d: Write: retry ... 1

I already added the fix to recover the i2c bus. So, after the above
message the kernel prints:
i2c_davinci i2c_davinci.1: initiating i2c bus recovery

I get the messages very often! Is it possible that some other i2c
devices (AIC33, MSP430, KSZ8893M Ethernet Switch) cause this problem??


Hello,
	I am curious, does the bus recover after a failure? That is, are you 
able to capture video after the i2c recovery code does its job? What 
happens without the i2c bus recovery patch?



Regards,
Philby
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Codec Stalled on DM365 2.6.32 Kernel

[Kieran Bingham]

Hi Guys,

I'm trying to get our code running on an arago kernel from the 2.6.18 
Montavista kernel.


We're running a DM365, and an MPEG2 Codec, but the same occurs with the 
H264 codec too.


With CE_TRACE turned on shows the following:

ENCODE: Ch 0 InBuf 0 OutBuf 0
ENCODE: pOutBuf-virtAddr 0x4615
@0x01365d41:[T:0x451aa490] ti.sdo.ce.video1.VIDENC1 - VIDENC1_process 
Enter (handle=0x29ddb0, inBufs=0x451a9be8, outBufs=0x451a9d4c, 
inArgs=0x451a9d40, outArgs=0x451a9cb8)
@0x01365fb1:[T:0x451aa490] CV - VISA_enter(visa=0x29ddb0): algHandle = 
0x29dde8
@0x01366127:[T:0x451aa490] ti.sdo.ce.alg.Algorithm - Algorithm_activate 
Enter(alg=0x29dde8)
@0x0136627c:[T:0x451aa490] ti.sdo.ce.osal.SemMP - Entered SemMP_pend 
sem[0x29d338] timeout[0x]
@0x013664aa:[T:0x451aa490] ti.sdo.ce.osal.SemMP - Leaving SemMP_pend 
sem[0x29d338] status[0]
@0x013666e7:[T:0x451aa490] ti.sdo.ce.alg.Algorithm - Algorithm_activate 
Exit


So I can see that the thread enters the VISA VIDENC1_process call into 
the MPEG2 codec, but never exits.


I've traced this down and can see that it is waiting on an interrupt 
from the co-processor


MPEG2 Encode :
#0  0x4062e27c in ioctl () from /lib/libc.so.6
#1  0x000e7314 in VICP_wait ()
#2  0x000e332c in HDVICPSYNC_wait ()
#3  0x000ddf44 in MPEG2VENC_TI_Encode ()
#4  0x0007c91c in VIDENC1_process ()

I traced this down as Interrupt 10 - and I have verified that the 
interrupt is both enabled - and muxed correctly.


However the interrupt never arrives - - and we're always waiting on 
VICP_wait. :(


Can anyone suggest any reasons why the codec would not be starting on 
the new kernel ?
Would the memory maps of shared DTCM be different and prevent the 
co-processor loading?


Would there be any other muxings that might prevent the co-processor 
running?


I'm stuck - and can't get it to run - so just hoping someone might have 
some ideas !
I don't think there's any way I can debug the state of the codec further 
than the CE_TRACE - so I can't tell why the codec isn't running or 
what's wrong with it.


Regards
Kieran
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RE: [PATCH 3/5] davinci: edma: fix coding style issues related to indentation

[Nori, Sekhar]

Hello,

On Tue, May 04, 2010 at 14:57:05, Sergei Shtylyov wrote:
 Hello.

 Sekhar Nori wrote:
  In the edma driver some if statememnts are broken up such that
  the condition code is at the same indentation level as the
  statement block. This makes reading it particularly difficult.
 
  This patch fixes that issue.
 
  Signed-off-by: Sekhar Nori nsek...@ti.com
  ---
   arch/arm/mach-davinci/dma.c |   26 +-
   1 files changed, 13 insertions(+), 13 deletions(-)
 
  diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
  index cc5fcda..2734de9 100644
  --- a/arch/arm/mach-davinci/dma.c
  +++ b/arch/arm/mach-davinci/dma.c
  @@ -352,7 +352,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
  dev_dbg(data, dma_irq_handler\n);
 
  if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0)
  -(edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
 

IMHO this level of indentation doesn't affect the readability.

The original code was indented using spaces so the level of
indentation can change depending on your tabstop setting.


  +(edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
  return IRQ_NONE;
 
  while (1) {
  @@ -406,9 +406,9 @@ static irqreturn_t dma_ccerr_handler(int irq, void 
  *data)
  dev_dbg(data, dma_ccerr_handler\n);
 
  if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) 
  -   (edma_read_array(ctlr, EDMA_EMR, 1) == 0) 
  -   (edma_read(ctlr, EDMA_QEMR) == 0) 
  -   (edma_read(ctlr, EDMA_CCERR) == 0))
 

What's up with these too?

  +   (edma_read_array(ctlr, EDMA_EMR, 1) == 0) 
  +   (edma_read(ctlr, EDMA_QEMR) == 0) 
  +   (edma_read(ctlr, EDMA_CCERR) == 0))
 

Your increased indentation looks rather ugly to me... matter of
 taste, of course.

Same here, spaces were being used for indentation. I realize
now I should have rather stated this issue in patch description.

Also, broken condition expressions at the same indentation level
as the actual statement are tough to read. Hence the increased
indentation.


  @@ -469,9 +469,9 @@ static irqreturn_t dma_ccerr_handler(int irq, void 
  *data)
  }
  }
  if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0)
  -(edma_read_array(ctlr, EDMA_EMR, 1) == 0)
  -(edma_read(ctlr, EDMA_QEMR) == 0)
  -(edma_read(ctlr, EDMA_CCERR) == 0))
 

Again, I don't find anything bad about this, except I'd put  at the
 end of lines, no at the start...

Spaces at play again. I agree on the  part. But that's
out of scope for $SUBJECT.

Thanks,
Sekhar
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RE: Codec Stalled on DM365 2.6.32 Kernel

[Nori, Sekhar]

Hi Kieran,

On Tue, May 04, 2010 at 15:36:38, Kieran Bingham wrote:
 Hi Guys,

 I'm trying to get our code running on an arago kernel from the 2.6.18
 Montavista kernel.

 We're running a DM365, and an MPEG2 Codec, but the same occurs with the
 H264 codec too.

There is a DVSDK available built on the arago kernel:

http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/dvsdk/DVSDK_3_10/latest/index_FDS.html

You could start here instead of starting from ground up.

You can get help regarding the DVSDK from e2e.ti.com

Thanks,
Sekhar

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RE: Bluetooth on Davinci DM355

[Subbrathnam, Swaminathan]

Kapil,
Would you try the same scenario on Davinci Staging Git tree

Regards
swami


From: davinci-linux-open-source-boun...@linux.davincidsp.com 
[mailto:davinci-linux-open-source-boun...@linux.davincidsp.com] On Behalf Of 
Kapil Pendse
Sent: Wednesday, April 28, 2010 5:20 PM
To: davinci-linux-open-source@linux.davincidsp.com
Subject: Bluetooth on Davinci DM355


Hello,

I've been trying to get Bluetooth to work with DM355 based board. My kernel is 
2.6.10 with patchset PSP 01.20.01.004.

I've compiled BlueZ packages bluez-libs-2.10 and bluez-utils-2.10 for the 
DaVinci. I know this is a very old version of BlueZ, but someone had 
recommended this one as it doesn't depend on the D-Bus package.

So with this setup, when I connect my old Bluetooth USB dongle to the DM355 
board (note that it is not the EVM), the device gets detected as a full speed 
(12Mbps) USB device, and HCI interface is set up for it as hci0.

r...@192.168.0.4:~# lsusb
Bus 001 Device 013: ID 0a12:0001 Cambridge Silicon Radio, Ltd Bluetooth Dongle
Bus 001 Device 001: ID 04d6: Mentor Graphics

r...@192.168.0.4:~# hciconfig -a
hci0:   Type: USB
BD Address: 00:10:60:AB:D0:5C ACL MTU: 192:8  SCO MTU: 64:8
UP RUNNING PSCAN ISCAN
RX bytes:105 acl:0 sco:0 events:10 errors:0
TX bytes:42 acl:0 sco:0 commands:10 errors:0
Features: 0xff 0xff 0x0f 0x00 0x00 0x00 0x00 0x00
Packet type: DM1 DM3 DM5 DH1 DH3 DH5 HV1 HV2 HV3
Link policy:
Link mode: SLAVE ACCEPT
Name: ''
Can't read class of device on hci0. Connection timed out(110)

But when I try to scan for remote BT devices, I get timeout error like below:

r...@192.168.0.4:~# hcitool scan
Scanning ...
hci_cmd_task: hci0 command tx timeout
hci_usb_rx_complete: hci0 corrupted packet: type 4 count 16

I do remember that the scan DID WORK one or two times. It did manage to detect 
my cellphone's BT. But that's about it, so I'd say that it is unable to scan 
for devices 99% of the time.

I've tested this BT dongle on my LinuxMint based host PC, it works fine. So 
although very old, the BT dongle is just fine. Looks like I need to fix 
something in the BlueZ kernel modules or userspace libraries.

Could someone help me figure out what is wrong and what would be the way to fix 
this?

Thanks and best regards,

Kapil

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RE: can't detect video input

[Chris Jackson]

thank you suhas, 

I am familiar with that document, and I've worked through it
successfully.

But after changing the bootargs in section 4.3.7, and saveenv
overwriting the original bootargs, I haven't been able to run the encode
demo when booting from the NAND.

I think the problem is where I have changed the video bootargs in 4.3.7,
but I can't find anywhere the default. out of box settings that I can
revert too.  I should have saved that info before overwriting.  

I have successfully run the encode demo before setting up the board to
NFS mount, and now I just want to do that again but I cant seem to get
the board to take video input.  

any ideas???  I still get the following error msg when i run the encode
demo from the command line:

Encode demo started.
Error: Failed to detect video standard, video input
connected?6/data/videos/demo.
Error: Failed to create video encoder: mpeg4enc


thank you, 

Chris Jackson




On Tue, 2010-05-04 at 12:16 +0530, Suhas Jain wrote:
 Hi Chris,
 
 You can find the complete setup for DM6446 EVM board at following link.
 
 http://focus.ti.com/lit/ug/sprue66e/sprue66e.pdf
 
 Regards,
 Suhas Jain
 
 -Original Message-
 From: davinci-linux-open-source-boun...@linux.davincidsp.com
 [mailto:davinci-linux-open-source-boun...@linux.davincidsp.com] On Behalf Of
 Jon Povey
 Sent: 04 May 2010 07:02
 To: Chris; davinci-linux-open-source@linux.davincidsp.com
 Subject: RE: can't detect video input
 
 Chris wrote:
  I want to revert to the default bootargs that ship with the board,
  but I can't find that info anywhere, and I've written over the NAND
  with new bootargs for the NFS mount.  Does anybody know what the
  default bootarg string is?
 
 With DM355 EVM, I think that info was printed in the getting started or
 technical reference dead tree guides that came with the EVM. Not sure about
 6446. Hope that helps or someone else answers..
 
 --
 Jon Povey
 jon.po...@racelogic.co.uk
 
 Racelogic is a limited company registered in England. Registered number
 2743719 .
 Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham,
 Bucks, MK18 1TB .
 
 The information contained in this electronic mail transmission is intended
 by Racelogic Ltd for the use of the named individual or entity to which it
 is directed and may contain information that is confidential or privileged.
 If you have received this electronic mail transmission in error, please
 delete it from your system without copying or forwarding it, and notify the
 sender of the error by reply email so that the sender's address records can
 be corrected. The views expressed by the sender of this communication do not
 necessarily represent those of Racelogic Ltd. Please note that Racelogic
 reserves the right to monitor e-mail communications passing through its
 network
 
 
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RE: DM6467 McASP

[Bedia, Vaibhav]

Jayakrishnan,

The McASP transmit bit clock, ACLKX can be either externally sourced or 
internally generated. 

In case ALCLKX is internally generated from AUXCLK, then you have the option of 
sending the intermediate high frequency master clock (AHCLKX) to the AHCLKX pin 
to be used by other devices in the system. In such a situation you don't need 
to use the 2nd McASP just for generating AHCLKX.

However, if your use-case needs two McASPs that can also be done as both can be 
used simultaneously.

Regards,
Vaibhav

-Original Message-
From: davinci-linux-open-source-boun...@linux.davincidsp.com 
[mailto:davinci-linux-open-source-boun...@linux.davincidsp.com] On Behalf Of 
Jaya krishnan
Sent: Tuesday, May 04, 2010 1:44 PM
To: davinci-linux-open-source@linux.davincidsp.com
Subject: DM6467 McASP


Hi  ,
I want  to use McASP  port  0 for  transmit data  and port 1  to  generate high 
frequency clock (AHCLKX) (to be used as  master clock for  another audio DAC  
in the  system.)  Is there  any  limitation to use  both  ports  
simultaneously?Pls  reply
Regards
JK

 

Jayakrishnan M M
Research Engineer
RD Team-2 , Group-5
Security Solutions  Division
SAMSUNG TECHWIN CO.,LTD

TEL +82-70-7147-8482
FAX +82-31-8018-3712
Mobile +82-10-6409-3619
E-mail:jaya.krish...@samsung.com
 
  
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Re: cppi_dma.c : channel_abort

[Kieran Bingham]

Thanks Sergei,

I'm trying to move to the later kernel to see if we can get things
running there - then that patch should be included and also better SD
card performance :)

Not getting very far with it as the Codec's won't encode :( so I may
look to merge those patches into our older kernel.

Thanks for the heads up :)

Regards
 Kieran

On 27 April 2010 14:00, Sergei Shtylyov sshtyl...@mvista.com wrote:
 Hello.

 Kieran Bingham wrote:

 We're running a DM365, with Montavista 2.6.18_pro500 kernel.

 With a USB Flash drive, and a USB Connected DVD Drive, we're experiencing
 kernel lockups

 Having connected the JTAG, and stepping through the assembly, it would
 appear that it is cycling through one of the two while loops in the function
 channel_abort, in drivers/usb/musb/cppi_dma.c

 Unfortunately its doing this with interrupts off!! and it never leaves!

 Has anyone else experienced Kernel Lockups with USB devices connected ?

  See if the following patch can fix it for you:

 http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=patch;h=565969237ab6e73ce7192684d00d5b890ee308fa

 WBR, Sergei


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DM355+MSP430+push buttons

[Idriss Ghodhbane]

Hi everybody,

I am stuck at the level of controlling the push buttons of my EVM DM355
(SW10/11/12/13/14).
After searching on the net, I had discovered that I haven't the nexassary
libraries for the microcontroller MSP430 neither integrated in my
DVSDK_2_00_00_22 nor in the LSP linux-2.6.18_pro500 which is the kernel.
Have you a solution for this issue?
Big thanks

Best Regards
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RE: can't detect video input

[Chris Jackson]

thanks for the help all.  the camera that shipped with the board is
defective, therein lies the problem!

chris

On Tue, 2010-05-04 at 12:16 +0530, Suhas Jain wrote:
 Hi Chris,
 
 You can find the complete setup for DM6446 EVM board at following link.
 
 http://focus.ti.com/lit/ug/sprue66e/sprue66e.pdf
 
 Regards,
 Suhas Jain
 
 -Original Message-
 From: davinci-linux-open-source-boun...@linux.davincidsp.com
 [mailto:davinci-linux-open-source-boun...@linux.davincidsp.com] On Behalf Of
 Jon Povey
 Sent: 04 May 2010 07:02
 To: Chris; davinci-linux-open-source@linux.davincidsp.com
 Subject: RE: can't detect video input
 
 Chris wrote:
  I want to revert to the default bootargs that ship with the board,
  but I can't find that info anywhere, and I've written over the NAND
  with new bootargs for the NFS mount.  Does anybody know what the
  default bootarg string is?
 
 With DM355 EVM, I think that info was printed in the getting started or
 technical reference dead tree guides that came with the EVM. Not sure about
 6446. Hope that helps or someone else answers..
 
 --
 Jon Povey
 jon.po...@racelogic.co.uk
 
 Racelogic is a limited company registered in England. Registered number
 2743719 .
 Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham,
 Bucks, MK18 1TB .
 
 The information contained in this electronic mail transmission is intended
 by Racelogic Ltd for the use of the named individual or entity to which it
 is directed and may contain information that is confidential or privileged.
 If you have received this electronic mail transmission in error, please
 delete it from your system without copying or forwarding it, and notify the
 sender of the error by reply email so that the sender's address records can
 be corrected. The views expressed by the sender of this communication do not
 necessarily represent those of Racelogic Ltd. Please note that Racelogic
 reserves the right to monitor e-mail communications passing through its
 network
 
 
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[PATCH 1/1] Davinci SDIO Support

[Alagu Sankar]

Added SDIO Support for Davinci.  Tested on DM355 EVM with Marvell SD8385 and
SD8686 cards using Libertas SDIO driver. This requires additional patches for
Libertas SDIO interface as indicated in the linux-wireless mailing list and
as referenced in the following links

http://marc.info/?l=linux-wirelessm=127136330220026w=2
http://marc.info/?l=linux-wirelessm=127136362020814w=2

Signed-off-by: Alagu Sankar alagusan...@embwise.com
---
 drivers/mmc/host/davinci_mmc.c |   98 +--
 1 files changed, 93 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/host/davinci_mmc.c b/drivers/mmc/host/davinci_mmc.c
index e4d1591..4afa6bf 100644
--- a/drivers/mmc/host/davinci_mmc.c
+++ b/drivers/mmc/host/davinci_mmc.c
@@ -66,8 +66,8 @@
 #define DAVINCI_MMCBLNC  0x60
 #define DAVINCI_SDIOCTL  0x64
 #define DAVINCI_SDIOST0  0x68
-#define DAVINCI_SDIOEN   0x6C
-#define DAVINCI_SDIOST   0x70
+#define DAVINCI_SDIOIEN  0x6C
+#define DAVINCI_SDIOIST  0x70
 #define DAVINCI_MMCFIFOCTL   0x74 /* FIFO Control Register */
 
 /* DAVINCI_MMCCTL definitions */
@@ -135,6 +135,23 @@
 /* MMCSD Init clock in Hz in opendrain mode */
 #define MMCSD_INIT_CLOCK   20
 
+/* DAVINCI_SDIOCTL definitions */
+#define SDIOCTL_RDWTRQ_SETBIT(0)
+#define SDIOCTL_RDWTCR_SETBIT(1)
+
+/* DAVINCI_SDIOST0 definitions */
+#define SDIOST0_DAT1_HI   BIT(0)
+#define SDIOST0_INTPRDBIT(1)
+#define SDIOST0_RDWTSTBIT(2)
+
+/* DAVINCI_SDIOIEN definitions */
+#define SDIOIEN_IOINTEN   BIT(0)
+#define SDIOIEN_RWSEN BIT(1)
+
+/* DAVINCI_SDIOIST definitions */
+#define SDIOIST_IOINT BIT(0)
+#define SDIOIST_RWS   BIT(1)
+
 /*
  * One scatterlist dma segment is at most MAX_CCNT rw_threshold units,
  * and we handle up to MAX_NR_SG segments.  MMC_BLOCK_BOUNCE kicks in only
@@ -147,6 +164,8 @@
 
 #define MAX_NR_SG  16
 
+#define DAVINCI_SDIO_IRQ(dev_id)   (((dev_id) == 0) ? sdio0 : sdio1)
+
 static unsigned rw_threshold = 32;
 module_param(rw_threshold, uint, S_IRUGO);
 MODULE_PARM_DESC(rw_threshold,
@@ -164,7 +183,7 @@ struct mmc_davinci_host {
unsigned int mmc_input_clk;
void __iomem *base;
struct resource *mem_res;
-   int irq;
+   int mmc_irq, sdio_irq;
unsigned char bus_mode;
 
 #define DAVINCI_MMC_DATADIR_NONE   0
@@ -184,6 +203,7 @@ struct mmc_davinci_host {
u32 rxdma, txdma;
bool use_dma;
bool do_dma;
+   bool sdio_int;
 
/* Scatterlist DMA uses one or more parameter RAM entries:
 * the main one (associated with rxdma or txdma) plus zero or
@@ -866,6 +886,19 @@ mmc_davinci_xfer_done(struct mmc_davinci_host *host, 
struct mmc_data *data)
 {
host-data = NULL;
 
+   if (host-mmc-caps  MMC_CAP_SDIO_IRQ) {
+   /* SDIO Interrupt Detection work-around as suggested by
+* Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata
+* 2.1.5)
+* Signal SDIO interrupt only if it is enabled by core
+*/
+   if (host-sdio_int  (!((readl(host-base + DAVINCI_SDIOST0))
+SDIOST0_DAT1_HI))) {
+   writel(SDIOIST_IOINT, host-base + DAVINCI_SDIOIST);
+   mmc_signal_sdio_irq(host-mmc);
+   }
+   }
+
if (host-do_dma) {
davinci_abort_dma(host);
 
@@ -932,6 +965,22 @@ davinci_abort_data(struct mmc_davinci_host *host, struct 
mmc_data *data)
mmc_davinci_reset_ctrl(host, 0);
 }
 
+static irqreturn_t mmc_davinci_sdio_irq(int irq, void *dev_id)
+{
+   struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id;
+   unsigned int status;
+
+   status = readl(host-base + DAVINCI_SDIOIST);
+   if (status  SDIOIST_IOINT) {
+   dev_dbg(mmc_dev(host-mmc),
+   SDIO interrupt status %x\n, status);
+   writel(status | SDIOIST_IOINT,
+   host-base + DAVINCI_SDIOIST);
+   mmc_signal_sdio_irq(host-mmc);
+   }
+   return IRQ_HANDLED;
+}
+
 static irqreturn_t mmc_davinci_irq(int irq, void *dev_id)
 {
struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id;
@@ -1076,11 +1125,34 @@ static int mmc_davinci_get_ro(struct mmc_host *mmc)
return config-get_ro(pdev-id);
 }
 
+static void mmc_davinci_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+   struct mmc_davinci_host *host = mmc_priv(mmc);
+
+   if (enable) {
+   if (!((readl(host-base + DAVINCI_SDIOST0))
+SDIOST0_DAT1_HI)) {
+   writel(SDIOIST_IOINT, host-base + DAVINCI_SDIOIST);
+   mmc_signal_sdio_irq(host-mmc);
+   } else {
+   host-sdio_int = 1;
+   writel(readl(host-base + DAVINCI_SDIOIEN) |
+

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[PATCH 0/4] DM365 patches

[thomas . koeller]

From: Thomas Koeller thomas.koel...@baslerweb.com

This is an updated patch series for DM365. Patches 0 and 1
are reworked versions of patches submitted earlier, 2 and 3
are new.

Thomas Koeller (4):
  DM365: Make all SPI units SPI0..SPI4 available
  DM365: Add platform resource management
  DAVINCI: Added missing includes
  DM365: Added PINMUX definitions for GPIO30..32

 arch/arm/mach-davinci/Makefile  |   10 +-
 arch/arm/mach-davinci/board-dm365-evm.c |   47 +++-
 arch/arm/mach-davinci/devices.c |  108 ++---
 arch/arm/mach-davinci/dm365.c   |  216 +
 arch/arm/mach-davinci/dm365_spi.c   |  338 +++
 arch/arm/mach-davinci/dma.c |8 -
 arch/arm/mach-davinci/include/mach/common.h |3 +
 arch/arm/mach-davinci/include/mach/dm365.h  |5 +-
 arch/arm/mach-davinci/include/mach/mux.h|3 +
 arch/arm/mach-davinci/platform-resources.c  |   90 +++
 arch/arm/mach-davinci/platform-resources.h  |   30 +++
 arch/arm/mach-davinci/spi.h |   35 +++
 drivers/i2c/busses/i2c-davinci.c|9 +-
 drivers/mmc/host/davinci_mmc.c  |4 +-
 drivers/spi/davinci_spi.c   |   16 +-
 drivers/watchdog/davinci_wdt.c  |   15 --
 16 files changed, 740 insertions(+), 197 deletions(-)
 create mode 100644 arch/arm/mach-davinci/dm365_spi.c
 create mode 100644 arch/arm/mach-davinci/platform-resources.c
 create mode 100644 arch/arm/mach-davinci/platform-resources.h
 create mode 100644 arch/arm/mach-davinci/spi.h

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[PATCH 1/4] DM365: Make all SPI units SPI0..SPI4 available

[thomas . koeller]

From: Thomas Koeller thomas.koel...@baslerweb.com

Change the SPI setup code to allow use of all SPI units. Also,
move some resource assignments (DMA channels, interrupts)
to the board code, where they belong. These really should not
be hard-coded in dm365.c.

The spi setup stuff has been moved to a separate file
'arch/arm/mach-davinci/dm365_spi.c' to increase modularity.
I am not currently able to address the DM355, but it should be
easy to write a dm355_spi.c file.

Signed-off-by: Thomas Koeller thomas.koel...@baslerweb.com
---
 arch/arm/mach-davinci/Makefile |2 +-
 arch/arm/mach-davinci/board-dm365-evm.c|   47 -
 arch/arm/mach-davinci/dm365.c  |   68 ---
 arch/arm/mach-davinci/dm365_spi.c  |  276 
 arch/arm/mach-davinci/include/mach/dm365.h |5 +-
 arch/arm/mach-davinci/spi.h|   35 
 6 files changed, 350 insertions(+), 83 deletions(-)
 create mode 100644 arch/arm/mach-davinci/dm365_spi.c
 create mode 100644 arch/arm/mach-davinci/spi.h

diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index f6c7e4c..b9c497c 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -32,6 +32,6 @@ obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o
 obj-$(CONFIG_MACH_DAVINCI_DM355_EVM)   += board-dm355-evm.o
 obj-$(CONFIG_MACH_DM355_LEOPARD)   += board-dm355-leopard.o
 obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM)  += board-dm646x-evm.o cdce949.o
-obj-$(CONFIG_MACH_DAVINCI_DM365_EVM)   += board-dm365-evm.o
+obj-$(CONFIG_MACH_DAVINCI_DM365_EVM)   += board-dm365-evm.o dm365_spi.o
 obj-$(CONFIG_MACH_DAVINCI_DA830_EVM)   += board-da830-evm.o
 obj-$(CONFIG_MACH_DAVINCI_DA850_EVM)   += board-da850-evm.o
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c 
b/arch/arm/mach-davinci/board-dm365-evm.c
index ab3b0e2..96dd72f 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -49,6 +49,8 @@
 #include media/tvp7002.h
 #include media/davinci/videohd.h
 
+#include spi.h
+
 
 
 /* have_imager() - Check if we have support for imager interface */
@@ -337,18 +339,18 @@ static struct i2c_driver pca9543a_driver = {
 static void dm365evm_reset_imager(int rst)
 {
u8 val;
-   
+
/* Reset bit6 of CPLD_IMG_DIR2 */
val = __raw_readb(cpld + CPLD_IMG_DIR2)  ~BIT(6);
-   __raw_writeb(val, (cpld + CPLD_IMG_DIR2));  
+   __raw_writeb(val, (cpld + CPLD_IMG_DIR2));
 
/* Set bit5 of CPLD_IMG_MUX5 */
val = __raw_readb(cpld + CPLD_IMG_MUX5) | BIT(5);
-   __raw_writeb(val, (cpld + CPLD_IMG_MUX5));  
+   __raw_writeb(val, (cpld + CPLD_IMG_MUX5));
 
/* Reset bit 0 of CPLD_IMG_MUX5 */
val = __raw_readb(cpld + CPLD_IMG_MUX5)  ~BIT(0);
-   __raw_writeb(val, (cpld + CPLD_IMG_MUX5));  
+   __raw_writeb(val, (cpld + CPLD_IMG_MUX5));
 
/**
 * Configure GPIO40 to be output and high. This has dependency on MMC1
@@ -375,7 +377,7 @@ static int dm365evm_enable_pca9543a(int en)
.buf = val,
};
 
-   printk(dm365evm_enable_pca9543a\n);   
+   printk(dm365evm_enable_pca9543a\n);
if (!en)
val = 0;
 
@@ -385,7 +387,7 @@ static int dm365evm_enable_pca9543a(int en)
msg.addr = pca9543a-addr;
/* turn i2c switch, pca9543a, on/off */
status = i2c_transfer(pca9543a-adapter, msg, 1);
-   printk(dm365evm_enable_pca9543a, status = %d\n, status);  
+   printk(dm365evm_enable_pca9543a, status = %d\n, status);
return status;
return 0;
 }
@@ -832,7 +834,7 @@ static struct spi_eeprom at25640 = {
.flags  = EE_ADDR2,
 };
 
-static struct spi_board_info dm365_evm_spi_info[] __initconst = {
+static const struct spi_board_info dm365_evm_spi_info[] __initconst = {
{
.modalias   = at25,
.platform_data  = at25640,
@@ -840,9 +842,32 @@ static struct spi_board_info dm365_evm_spi_info[] 
__initconst = {
.bus_num= 0,
.chip_select= 0,
.mode   = SPI_MODE_0,
-   },
+   }
+};
+
+static struct davinci_spi_unit_desc dm365_evm_spi_udesc_at25 = {
+   .spi_hwunit = 0,
+   .chipsel= BIT(0),
+   .irq= IRQ_DM365_SPIINT0_0,
+   .dma_tx_chan= 16,
+   .dma_rx_chan= 17,
+   .dma_evtq   = EVENTQ_3,
+   .pdata  = {
+   .version= SPI_VERSION_1,
+   .num_chipselect = 2,
+   .clk_internal   = 1,
+   .cs_hold= 1,
+   .intr_level = 0,
+   .poll_mode  = 1,/* 0 - interrupt mode 1- polling mode 
*/
+   .use_dma= 1,/* when 1, value in poll_mode is 
ignored */
+   .c2tdelay   = 0,
+   .t2cdelay   = 0
+   }
 };
 
+
+
+
 static __init void 

[PATCH 3/4] DAVINCI: Added missing includes

[thomas . koeller]

From: Thomas Koeller thomas.koel...@baslerweb.com

linux/compiler.h is required for __iomem
linux/types.h is required u32

Signed-off-by: Thomas Koeller thomas.koel...@baslerweb.com
---
 arch/arm/mach-davinci/include/mach/common.h |3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/common.h 
b/arch/arm/mach-davinci/include/mach/common.h
index 1fd3917..f56fd5a 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -12,6 +12,9 @@
 #ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H
 #define __ARCH_ARM_MACH_DAVINCI_COMMON_H
 
+#include linux/compiler.h
+#include linux/types.h
+
 struct sys_timer;
 
 extern struct sys_timer davinci_timer;
-- 
1.7.0.3

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[PATCH 2/4] DM365: Add platform resource management

[thomas . koeller]

From: Thomas Koeller thomas.koel...@baslerweb.com

Keeping track of resource assignments greatly simplifies
the task of writing board support code. Many drivers for
DaVinci peripherals were using resources that had never
been allocated, with the notable exception of memory
resources.

Non-conflicting resource assignment is a responsibility
of the bus the devices are on, in this case, the platform bus.

The resource management scheme implemented by this patch is not
perfect. The SoC code really has no business managing resources,
it should only provide them to the platform (board support) code.
The board support is the only place where information about the
intended use of the various hardware resources is available.

Signed-off-by: Thomas Koeller thomas.koel...@baslerweb.com
---
 arch/arm/mach-davinci/Makefile |8 +-
 arch/arm/mach-davinci/devices.c|  108 +++--
 arch/arm/mach-davinci/dm365.c  |  145 ++--
 arch/arm/mach-davinci/dm365_spi.c  |  126 ++--
 arch/arm/mach-davinci/dma.c|8 --
 arch/arm/mach-davinci/platform-resources.c |   90 +
 arch/arm/mach-davinci/platform-resources.h |   30 ++
 drivers/i2c/busses/i2c-davinci.c   |9 +--
 drivers/mmc/host/davinci_mmc.c |4 +-
 drivers/spi/davinci_spi.c  |   16 +---
 drivers/watchdog/davinci_wdt.c |   15 ---
 11 files changed, 413 insertions(+), 146 deletions(-)
 create mode 100644 arch/arm/mach-davinci/platform-resources.c
 create mode 100644 arch/arm/mach-davinci/platform-resources.h

diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index b9c497c..2e3d4ff 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -11,10 +11,10 @@ obj-$(CONFIG_DAVINCI_MUX)   += mux.o
 obj-$(CONFIG_PCI)  += pci-generic.o
 
 # Chip specific
-obj-$(CONFIG_ARCH_DAVINCI_DM644x)   += dm644x.o devices.o
-obj-$(CONFIG_ARCH_DAVINCI_DM355)+= dm355.o devices.o
-obj-$(CONFIG_ARCH_DAVINCI_DM646x)   += dm646x.o devices.o
-obj-$(CONFIG_ARCH_DAVINCI_DM365)   += dm365.o devices.o
+obj-$(CONFIG_ARCH_DAVINCI_DM644x)   += dm644x.o devices.o 
platform-resources.o
+obj-$(CONFIG_ARCH_DAVINCI_DM355)+= dm355.o devices.o 
platform-resources.o
+obj-$(CONFIG_ARCH_DAVINCI_DM646x)   += dm646x.o devices.o 
platform-resources.o
+obj-$(CONFIG_ARCH_DAVINCI_DM365)   += dm365.o devices.o 
platform-resources.o
 obj-$(CONFIG_ARCH_DAVINCI_DA830)+= da830.o devices-da8xx.o
 obj-$(CONFIG_ARCH_DAVINCI_DA850)+= da850.o devices-da8xx.o
 
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 34dc0e9..53aaeb5 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -27,6 +27,9 @@
 #include mach/mmc.h
 #include mach/time.h
 
+#include clock.h
+#include platform-resources.h
+
 #define DAVINCI_I2C_BASE0x01C21000
 #define DAVINCI_MMCSD0_BASE 0x01E1
 #define DM355_MMCSD0_BASE   0x01E11000
@@ -34,20 +37,27 @@
 #define DM365_MMCSD0_BASE   0x01D11000
 #define DM365_MMCSD1_BASE   0x01D0
 
+static const char i2c_name[] = i2c_davinci;
+
 static struct resource i2c_resources[] = {
{
+   .parent = resource_cfg_root,
+   .name   = i2c_name,
.start  = DAVINCI_I2C_BASE,
.end= DAVINCI_I2C_BASE + 0x40,
.flags  = IORESOURCE_MEM,
},
{
+   .parent = resource_irq_root,
+   .name   = i2c_name,
.start  = IRQ_I2C,
+   .end= IRQ_I2C,
.flags  = IORESOURCE_IRQ,
},
 };
 
 static struct platform_device davinci_i2c_device = {
-   .name   = i2c_davinci,
+   .name   = i2c_name,
.id = 1,
.num_resources  = ARRAY_SIZE(i2c_resources),
.resource   = i2c_resources,
@@ -58,42 +68,59 @@ void __init davinci_init_i2c(struct 
davinci_i2c_platform_data *pdata)
if (cpu_is_davinci_dm644x())
davinci_cfg_reg(DM644X_I2C);
 
-   davinci_i2c_device.dev.platform_data = pdata;
-   (void) platform_device_register(davinci_i2c_device);
+   if (likely(!alloc_platform_resources(davinci_i2c_device))) {
+   davinci_i2c_device.dev.platform_data = pdata;
+   (void) platform_device_register(davinci_i2c_device);
+   }
 }
 
 #ifdefined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE)
 
 static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32);
+static const char mmc_name[] = davinci_mmc;
 
 static struct resource mmcsd0_resources[] = {
{
/* different on dm355 */
-   .start = DAVINCI_MMCSD0_BASE,
-   .end   = 

[PATCH 4/4] DM365: Added PINMUX definitions for GPIO30..32

[thomas . koeller]

From: Thomas Koeller thomas.koel...@baslerweb.com

Signed-off-by: Thomas Koeller thomas.koel...@baslerweb.com
---
 arch/arm/mach-davinci/dm365.c|3 +++
 arch/arm/mach-davinci/include/mach/mux.h |3 +++
 2 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 0aea612..8fb7578 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -579,6 +579,9 @@ MUX_CFG(DM365,  SPI4_SDENA0,4,   20,3,1,
 false)
 MUX_CFG(DM365, SPI4_SDENA1,4,   16,3,2, false)
 
 MUX_CFG(DM365, GPIO20, 3,   21,3,0, false)
+MUX_CFG(DM365, GPIO30, 4,   6, 3,0, false)
+MUX_CFG(DM365, GPIO31, 4,   8, 3,0, false)
+MUX_CFG(DM365, GPIO32, 4,   10,3,0, false)
 MUX_CFG(DM365, GPIO33, 4,   12,3,0, false)
 MUX_CFG(DM365, GPIO40, 4,   26,3,0, false)
 
diff --git a/arch/arm/mach-davinci/include/mach/mux.h 
b/arch/arm/mach-davinci/include/mach/mux.h
index 05e35fa..49a2f57 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -293,6 +293,9 @@ enum davinci_dm365_index {
 
/* GPIO */
DM365_GPIO20,
+   DM365_GPIO30,
+   DM365_GPIO31,
+   DM365_GPIO32,
DM365_GPIO33,
DM365_GPIO40,
 
-- 
1.7.0.3

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kernel cache APIs

[Tivy, Robert]

I need to port CMEM to the newer 2.6.34 Linux kernel but am having trouble with 
the cache functions.  This is for the TI ARM, in general.

CMEM provides general capability to user programs to initiate a cache 
operation, mostly for the purpose of affecting the cache contents pertaining to 
the CMEM buffers.  CMEM allows the user to specify either a writeback, an 
invalidate, or a writeback/invalidate.  These operations are always for user 
virtual addresses.

Previously I was calling dmac_{clean,inv,flush}_range() to do the wb/inv/wbinv, 
respectively.  Now it seems that only dmac_flush_range() exists (at least, 
that's the only one of the 3 that doesn't get an implicit declaration error 
when compiling).  There was some talk a while back on this maillist of having 
to change to use dma_map_single(), but in 2.6.34 that API appears to be much 
different than before, and not appropriate for just triggering an operation on 
the cache.

Can anyone please point me to the appropriate cache APIs?  (I don't want to 
call all type operations, just range type)

Thanks  Regards,

- Rob
Texas Instruments, Santa Barbara

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Re: UBL Question

[John Tobias]

Caglar,

In sprue20c http://www-s.ti.com/sc/techlit/sprue20.pdf documentation,
discusses the 3 types of mode. One of them is the NAND Flash mode, which is
the mode  to function the NAND Flash ECC generator.

My question is, if the device is running linux, what mode does the NAND
is?.

I am start playing to add some routines in nand drivers and see how far I
can go. But, need additional information and maybe you can help me.

1. Do you know how the ubl data laid out on the block?.
2.The ubl image should not exist 0x3800 bytes and seems DVFlasher removes
some Srec. Do you know what was the reason?.


Best Regards,

John


On Sat, May 1, 2010 at 11:52 PM, Caglar Akyuz caglarak...@gmail.com wrote:

 On Saturday 01 May 2010 01:19:56 am John Tobias wrote:
  I've used the following commands and didn't get any success.
 
  1. nanddump -n -f /ubl.bin /dev/mtd5
  Block size 16384, page size 512, OOB size 16
  Dumping data starting at 0x and ending at 0x4000
 
  2. flash_erase /dev/mtd1
 
  3. nandwrite -n -o /dev/mtd1 /ubl.bin
 
  4. flash_erase /dev/mtd5
 
  Any more idea?
 

 AFAIK, rbl/ubl pair uses different ECC layout than u-boot/Linux pair. For
 instance, I do not use u-boot in some cases and boot Linux directly from
 UBL
 in which I write Linux to NAND from userspace. In those cases, I read Linux
 without any ECC in UBL. But you do not have any access to RBL so you cannot
 program UBL from userspace without changing Linux ECC handling.

 Best Regards,
 Caglar

  Thanks,
 
  John
 
  On Fri, Apr 30, 2010 at 2:57 PM, Siddharth Choudhuri
 s...@dsicentral.comwrote:
   Does dd also take care of writing the OOB area along with the actual
 data
   ? The OOB layout where the ECC is written could be an issue IMO. You
   might want to look at nandwrite i.e., read using nanddump - erase -
   nandwrite to see if it works. Also, nanddump and nandwrite might have
 an
   option to read page data and/or OOB.
  
   -sid
  
   On Apr 30, 2010, at 1:15 PM, John Tobias wrote:
  
   Hi Mike,
  
   I've used this two commands to copy the image on block 5 then, copy it
   over to block 1.
  
   dd if=/dev/mtd5 of=/ubl.bin bs=512 count=32
   dd if=/ubl.bin of=/dev/mtd1 bs=512 count=32
   (My NAND flash has 512 bytes per page with 32 pages per block or
 16Kbytes
   in  1 block).
  
   In order to test the block 1 if it's working, I erased the block 5 and
   boot my device but, it doesn't work.
  
   Any idea?
  
   Thanks,
  
   John
  
   On Fri, Apr 30, 2010 at 11:51 AM, John Tobias jtob...@viaas.com
 wrote:
   Hi Mike,
  
   Yes, that's my plan. I will expose the ubl blocks from linux userspace
   and become writable.
   And, I like the idea of using dd so no need to worry about the CRC
   issue.
  
   Thanks,
  
   John
  
   On Fri, Apr 30, 2010 at 11:34 AM, Mike Williamson 
  
   michael.william...@criticallink.com wrote:
   Hi John,
  
   In the past, we've used the /dev/mtd* devices to write data back to
 NOR
   (spi / parallel) devices for updating firmware using something like:
  
   dd if=newimage.bin of=/dev/mtd0
  
   Of course, you need to have your kernel configured to have the mtd
   drivers loaded and you need to make these areas writable (most linux
   board packages set these to read-only, given the sizeable gun you
 have
   pointed at your shoes)
  
   -Mike
  
   On Fri, Apr 30, 2010 at 2:14 PM, John Tobias jtob...@viaas.com
 wrote:
   Hi,
  
   Does anyone successfully written the UBL image in block 1/5 from
 linux
   userspace? I need a way to write the ubl image for the firmware
   upgrade and the only access that I have is the linux userspace.
  
  
   Thanks,
  
   John
  
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DM365 audio -- bad PLL setting in tlv320aic3x driver

[Jimmy Blair]

44100 Hz audio plays slightly fast on the DM365.
This is because the tlv320aic3x driver is calculating
invalid PLL parameters for the WCLK.  The parameters
it calculates are:

pll_p = 1, pll_r = 1, pll_j = 3, pll_d = 3450

According to the codec datasheet, the value of J
should be greater than 3.  The datasheet is correct.
The WCLK signal is unstable, bouncing between 44200 and 44500 Hz.

I recalculated the parameters by hand, setting P to 2
and got the following values:

pll_p = 2, pll_r = 1, pll_j = 6, pll_d = 6901

These values gave a clean 44100 WCLK.
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RE: UBL Question

[Nori, Sekhar]

Hi Raffaele,

On Tue, May 04, 2010 at 14:32:31, Raffaele Recalcati wrote:
 Hi Nori,



   There is a sourceforge project for UBL and serial flashing
 tools:

   http://sourceforge.net/projects/dvflashutils/

   You could join this project to contribute.

   Thanks,
   Sekhar



 Is this project good also for dm365?

Hmm, right. I can only find DM355 files here.
DM365 seems missing. Not sure if the files
just aren't showing up or DM365 support is
yet to be added. Let me ask around.

Thanks,
Sekhar

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