date:20210806

Re: [edk2-devel] [RFC PATCH 0/7] OVMF: Disable the TPM2 platform hierarchy

2021-08-06 Thread Yao, Jiewen

Hi Stefan
It seems this patch series is not a production fix. It is more like a 
prototype, my personally feeling.

A common issue in patch 2, 3, 4, 5, is that using "comment" to remove the code. 
Please remove the unnecessary code directly without // or /**/ in C, and # in 
INF.

For patch 1, if you want to move the code to SecurityPkg, that is fine. Please 
move the whole driver their and you should not remove and code by comment. 
Please fix the issue to make it pass build, instead of commenting the code like 
work-around.
Otherwise, you may copy the module to OvmfPkg. Then you can modify it as you 
need.

Please also merge 2, 3, 4 into 1. I don’t think we want a broken patch in 1, 
then add fix in 2, 3, 4.

Thank you
Yao Jiewen

> -Original Message-
> From: Stefan Berger 
> Sent: Friday, August 6, 2021 11:33 PM
> To: devel@edk2.groups.io; Yao, Jiewen 
> Cc: marcandre.lur...@redhat.com; ler...@redhat.com;
> dick_wilk...@phoenix.com; Stefan Berger 
> Subject: [RFC PATCH 0/7] OVMF: Disable the TPM2 platform hierarchy
> 
> This series imports code from the edk2-platforms project related to
> changing the password of the TPM2 platform hierarchy and uses it to
> disable the TPM2 platform hierarchy in OVMF. It addresses the OVMF
> aspects of the following bugs:
> 
> https://bugzilla.tianocore.org/show_bug.cgi?id=3510
> https://bugzilla.tianocore.org/show_bug.cgi?id=3499
> 
> There's no doubt that my struggles with the build system and handling
> of dependencies are visible in this series. Quite a few aspects of
> getting things right are more or less guesswork and I am often not sure
> what the correct way of doing things are. If 'you' wanted to fix
> things up and repost it, please go ahead...
> 
> Stefan
> 
> Stefan Berger (7):
>   SecurityPkg/TPM: Import PeiDxeTpmPlatformHierarchyLib.c from
> edk2-platforms
>   SecruityPkg/TPM: Disable dependency on MinPlatformPkg
>   SecurityPkg/TPM: Disable PcdGetBool (PcdRandomizePlatformHierarchy)
>   SecurityPkg/TPM: Disable a Pcd
>   SecurityPkg/TPM: Add a NULL implementation of
> PeiDxeTpmPlatformHierarchyLib
>   OVMF: Reference new classes in the build system for compilation
>   OVMF: Disable the TPM2 platform hierarchy
> 
>  OvmfPkg/AmdSev/AmdSevX64.dsc  |   3 +
>  .../PlatformBootManagerLib/BdsPlatform.c  |   6 +
>  .../PlatformBootManagerLib.inf|   1 +
>  .../PlatformBootManagerLibBhyve/BdsPlatform.c |   6 +
>  .../PlatformBootManagerLibGrub/BdsPlatform.c  |   6 +
>  OvmfPkg/OvmfPkgIa32.dsc   |   3 +
>  OvmfPkg/OvmfPkgIa32X64.dsc|   3 +
>  OvmfPkg/OvmfPkgX64.dsc|   3 +
>  .../Include/Library/TpmPlatformHierarchyLib.h |  27 ++
>  .../PeiDxeTpmPlatformHierarchyLib.c   | 266 ++
>  .../PeiDxeTpmPlatformHierarchyLib.inf |  46 +++
>  .../PeiDxeTpmPlatformHierarchyLib.c   |  23 ++
>  .../PeiDxeTpmPlatformHierarchyLib.inf |  39 +++
>  13 files changed, 432 insertions(+)
>  create mode 100644 SecurityPkg/Include/Library/TpmPlatformHierarchyLib.h
>  create mode 100644
> SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierar
> chyLib.c
>  create mode 100644
> SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierar
> chyLib.inf
>  create mode 100644
> SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHi
> erarchyLib.c
>  create mode 100644
> SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHi
> erarchyLib.inf
> 
> --
> 2.31.1



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Re: [edk2-devel] [RFC PATCH 3/7] SecurityPkg/TPM: Disable PcdGetBool (PcdRandomizePlatformHierarchy)

2021-08-06 Thread Yao, Jiewen

Stefan
This patch is NOT acceptable.

> +  if (1 /*PcdGetBool (PcdRandomizePlatformHierarchy)*/) {

Nacked-by: Jiewen Yao 

Thank you
Yao Jiewen


> -Original Message-
> From: Stefan Berger 
> Sent: Friday, August 6, 2021 11:33 PM
> To: devel@edk2.groups.io; Yao, Jiewen 
> Cc: marcandre.lur...@redhat.com; ler...@redhat.com;
> dick_wilk...@phoenix.com; Stefan Berger ;
> Stefan Berger 
> Subject: [RFC PATCH 3/7] SecurityPkg/TPM: Disable PcdGetBool
> (PcdRandomizePlatformHierarchy)
> 
> To avoid this type of build errors, disable
> 'PcdGetBool (PcdRandomizePlatformHierarchy)'.
> 
> Building ...
> /home/stefanb/dev/edk2/SecurityPkg/Library/SecureBootVariableProvisionLib/
> SecureBootVariableProvisionLib.inf [X64]
> In file included from
> /home/stefanb/dev/edk2/Build/OvmfX64/DEBUG_GCC5/X64/SecurityPkg/Librar
> y/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib/DEBUG/Aut
> oGen.h:17,
>  from :
> /home/stefanb/dev/edk2/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/
> PeiDxeTpmPlatformHierarchyLib.c: In function
> ‘ConfigureTpmPlatformHierarchy’:
> /home/stefanb/dev/edk2/MdePkg/Include/Library/PcdLib.h:424:45: error:
> ‘_PCD_GET_MODE_BOOL_PcdRandomizePlatformHierarchy’ undeclared (first
> use in this function)
>   424 | #define PcdGetBool(TokenName)
> _PCD_GET_MODE_BOOL_##TokenName
>   | ^~~
> 
> Signed-off-by: Stefan Berger 
> ---
>  .../PeiDxeTpmPlatformHierarchyLib.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git
> a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHier
> archyLib.c
> b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHier
> archyLib.c
> index 9812ab99ab..bea10d37a4 100644
> ---
> a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHier
> archyLib.c
> +++
> b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHier
> archyLib.c
> @@ -252,7 +252,7 @@ EFIAPI
>  ConfigureTpmPlatformHierarchy (
> 
>)
> 
>  {
> 
> -  if (PcdGetBool (PcdRandomizePlatformHierarchy)) {
> 
> +  if (1 /*PcdGetBool (PcdRandomizePlatformHierarchy)*/) {
> 
>  //
> 
>  // Send Tpm2HierarchyChange Auth with random value to avoid PlatformAuth
> being null
> 
>  //
> 
> --
> 2.31.1



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[edk2-devel] [edk2-platforms PATCH 3/3] SolidRun/Cn913xCEx7Eval: Add platform support

2021-08-06 Thread Marcin Wojtas

This patch adds the required platform description files, along with
the hardware configuration libraries, for the SolidRun
CN913x CEx7 Evaluation Board. Supported interfaces:

* SPI flash & memory-mapped variable storage access
* uSD
* eMMC
* 7x PCIE root complex
* USB
* Networking:
  * 1Gbps RGMII via PHY
  * 2500Base-X via quad 1Gpbs switch
  * 5Gbps via SFP cage and PHY

Signed-off-by: Marcin Wojtas 
---
 Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc
|  54 
 Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc
|  64 +
 Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc
|  64 +
 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc
|  68 +
 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc
|  57 
 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf   
|  30 ++
 
Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
 |  38 +++
 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.h 
|  30 ++
 
Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.h
   |  13 +
 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.c 
| 294 
 
Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.c
   |  89 ++
 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc
|  17 ++
 12 files changed, 818 insertions(+)
 create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc
 create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc
 create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc
 create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc
 create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc
 create mode 100644 
Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf
 create mode 100644 
Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
 create mode 100644 
Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.h
 create mode 100644 
Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.h
 create mode 100644 
Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.c
 create mode 100644 
Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.c
 create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc

diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc 
b/Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc
new file mode 100644
index 00..ad0983087d
--- /dev/null
+++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc
@@ -0,0 +1,54 @@
+## @file
+#  Component description file for the CN9130 Development Board (variant A)
+#
+#  Copyright (c) 2019 Marvell International Ltd.
+#  Copyright (c) 2021 Semihalf.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+
+[PcdsFixedAtBuild.common]
+  # ComPhy
+  gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
+  # ComPhy0
+  # 0: PCIE0 5 Gbps
+  # 1: PCIE0 5 Gbps
+  # 2: PCIE0 5 Gbps
+  # 3: PCIE0 5 Gbps
+  # 4: SFI   10.31 Gbps
+  # 5: SGMII23.125 Gbps
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), 
$(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SGMII2)}
+  gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), 
$(CP_5G), $(CP_10_3125G), $(CP_3_125G) }
+
+  # UtmiPhy
+  gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }
+  gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), 
$(UTMI_USB_HOST1) }
+
+  # MDIO
+  gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1 }
+
+  # PHY
+  gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }
+  gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }
+  gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }
+  gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+
+  # NET
+  gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }
+  gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1 }
+  gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_1), 
$(PHY_SPEED_1000), $(PHY_SPEED_2500) }
+  gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), 
$(PHY_SGMII) }
+  gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF }
+  gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 }
+  gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }
+  gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 }
+
+  # NonDiscoverableDevices
+  gMarvell

[edk2-devel] [edk2-non-osi PATCH] SolidRun/Cn913xCEx7Eval: Add DeviceTree

2021-08-06 Thread Marcin Wojtas

This patch introduces the top device tree for the CN913x CEx7
Evaluation Board, based on the sources which are common for the
Cn913x SoCs. Also an .inf file is added to allow its compilation.

Signed-off-by: Marcin Wojtas 
---
 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn913xCEx7Eval.inf |  22 +
 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts| 435 

 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-cex7.dts| 180 
 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-cex7.dts| 183 
 4 files changed, 820 insertions(+)
 create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn913xCEx7Eval.inf
 create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts
 create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-cex7.dts
 create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-cex7.dts

diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn913xCEx7Eval.inf 
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn913xCEx7Eval.inf
new file mode 100644
index 000..3c99227
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn913xCEx7Eval.inf
@@ -0,0 +1,22 @@
+## @file
+#
+#  Device tree description of the Marvell CN9130-DB-A platform
+#
+#  Copyright (c) 2021, Semihalf. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 0x0001001B
+  BASE_NAME  = Cn913xCEx7EvalDeviceTree
+  FILE_GUID  = 25462CDA-221F-47DF-AC1D-259CFAA4E326 # 
gDtPlatformDefaultDtbFileGuid
+  MODULE_TYPE= USER_DEFINED
+  VERSION_STRING = 1.0
+
+[Sources]
+  cn9132-cex7.dts
+
+[Packages]
+  MdePkg/MdePkg.dec
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts 
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts
new file mode 100644
index 000..50e6d69
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-cex7.dts
@@ -0,0 +1,435 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright SolidRun Ltd.
+ *
+ * Device tree for the  CN9130 based COM Express type 7 board.
+ */
+
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW  1
+
+#include "cn9130.dtsi"
+
+/ {
+model = "SolidRun CN9130 based COM Express type 7";
+
+chosen {
+stdout-path = "serial0:115200n8";
+};
+
+aliases {
+gpio1 = &cp0_gpio1;
+gpio2 = &cp0_gpio2;
+i2c0 = &cp0_i2c0;
+ethernet0 = &cp0_eth0; // SFP+ Port
+ethernet1 = &cp0_eth1; // RGMII
+ethernet2 = &cp0_eth2; // HS-SGMII
+spi1 = &cp0_spi0;
+spi2 = &cp0_spi1;
+};
+
+memory@ {
+device_type = "memory";
+reg = <0x0 0x0 0x0 0x8000>;
+};
+v_3_3: regulator-3-3v {
+compatible = "regulator-fixed";
+regulator-name = "v_3_3";
+regulator-min-microvolt = <330>;
+regulator-max-microvolt = <330>;
+regulator-always-on;
+status = "okay";
+};
+ap0_reg_sd_vccq: ap0_sd_vccq@0 {
+compatible = "regulator-gpio";
+regulator-name = "ap0_sd_vccq";
+regulator-min-microvolt = <180>;
+regulator-max-microvolt = <180>;
+states = <180 0x1 330 0x0>;
+};
+
+cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
+compatible = "regulator-fixed";
+regulator-name = "cp0-xhci0-vbus";
+regulator-min-microvolt = <500>;
+regulator-max-microvolt = <500>;
+enable-active-high;
+};
+
+cp0_usb3_0_phy0: cp0_usb3_phy@0 {
+compatible = "usb-nop-xceiv";
+vcc-supply = <&cp0_reg_usb3_vbus0>;
+};
+
+cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
+compatible = "regulator-fixed";
+regulator-name = "cp0-xhci1-vbus";
+regulator-min-microvolt = <500>;
+regulator-max-microvolt = <500>;
+enable-active-high;
+};
+
+cp0_usb3_0_phy1: cp0_usb3_phy@1 {
+compatible = "usb-nop-xceiv";
+vcc-supply = <&cp0_reg_usb3_vbus1>;
+};
+
+cp0_reg_sd_vccq: cp0_sd_vccq@0 {
+compatible = "regulator-gpio";
+regulator-name = "cp0_sd_vccq";
+regulator-min-microvolt = <180>;
+regulator-max-microvolt = <330>;
+states = <180 0x1
+330 0x0>;
+};
+
+cp0_reg_sd_vcc: cp0_sd_vcc@0 {
+compatible = "regulator-fixed";
+regulator-name = "cp0_sd_vcc";
+regulator-min-microvolt = <330>;
+regulator-max-microvolt = <330>;
+enable-active-high;
+regu

[edk2-devel] [edk2-platforms PATCH 2/3] SolidRun/Cn913xCEx7Eval: Add ACPI support

2021-08-06 Thread Marcin Wojtas

This patch adds ACPI tables description for the SolidRun
CN913x CEx7 Evaluation Board platform.

Signed-off-by: Marcin Wojtas 
---
 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf|  
61 +++
 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h |   
9 +
 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h | 
114 +
 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt.asl | 
383 +++
 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt.asl | 
493 +++
 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt.asl | 
515 
 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl | 
120 +
 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc  |  
74 +++
 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc  |  
87 
 9 files changed, 1856 insertions(+)
 create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf
 create mode 100644 
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h
 create mode 100644 
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h
 create mode 100644 
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt.asl
 create mode 100644 
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt.asl
 create mode 100644 
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt.asl
 create mode 100644 
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl
 create mode 100644 
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc
 create mode 100644 
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc

diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf 
b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf
new file mode 100644
index 00..27e7294014
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf
@@ -0,0 +1,61 @@
+## @file
+#  Component description file for PlatformAcpiTables module.
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2018, Linaro, Ltd. All rights reserved.
+#  Copyright (c) 2019, Marvell International Ltd. and its affiliates.
+#  Copyright (c) 2021, Semihalf.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 0x0001001B
+  BASE_NAME  = PlatformAcpiTables
+  FILE_GUID  = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE= USER_DEFINED
+  VERSION_STRING = 1.0
+
+[Sources]
+  Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl
+  Cn913xCEx7Eval/Cn9130EvalSsdt.asl
+  Cn913xCEx7Eval/Cn9131EvalSsdt.asl
+  Cn913xCEx7Eval/Cn9132EvalSsdt.asl
+  Cn913xCEx7Eval/Dbg2.aslc
+  Cn913xCEx7Eval/Mcfg.aslc
+  Fadt.aslc
+  Gtdt.aslc
+  Madt.aslc
+  Pptt.aslc
+  Spcr.aslc
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Marvell/Marvell.dec
+
+[FixedPcd]
+  gArmPlatformTokenSpaceGuid.PcdCoreCount
+
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+
+  gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+  gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum
+  gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+
+[BuildOptions]
+  *_*_*_ASLCC_FLAGS = -DCN9131
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h 
b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h
new file mode 100644
index 00..a18b7c1396
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h
@@ -0,0 +1,9 @@
+/**
+
+  Copyright (C) 2021, Semihalf.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#define CN913X_DBG2_UART_REG_BASE0xF2702200
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h 
b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h
new file mode 100644
index 00..592e47d0c4
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h
@@ -0,0 +1,114 @@
+/**
+
+  Copyright (C) 2019, Marvell International Ltd. and its affiliates.
+  Copyright (C) 2021, Semihalf.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#define CP0_PCI0_BUS_MIN0x0
+#define CP0_PCI0_BUS_MAX0x0
+#define CP0_PCI0_BUS_COUNT  0x1
+#define CP0_PCI0_MMIO32_BASE0xC000
+#define CP0_PCI0_MMIO32_SIZE0x2000
+#define CP0_PCI0_MMIO32_MAX 0xDFFF
+#define CP

[edk2-devel] [edk2-platforms PATCH 0/4] SolidRun CEx7 Evaluation Board support

2021-08-06 Thread Marcin Wojtas

Hi,

This patchset introduces support for the CEx7 Evaluation Board
Support, together with the ACPI tables and DT (edk2-non-osi patch).
Additional patch toggles the default HW description to ACPI for
all platforms based on SoCs.

Supported interaces:
* SPI flash & memory-mapped variable storage access
* uSD
* eMMC
* 7x PCIE root complex
* USB
* Networking:
  * 1Gbps RGMII via PHY
  * 2500Base-X via quad 1Gpbs switch
  * 5Gbps via SFP cage and PHY

The patches are also available on public branches:
https://github.com/semihalf-wojtas-marcin/edk2-platforms/commits/cex7-r20210806
https://github.com/semihalf-wojtas-marcin/edk2-non-osi/commits/cex7-r20210806

I would appreciate any comments or remarks.

Best regards,
Marcin

Marcin Wojtas (3):
edk2-platforms:
  Marvell: Armada7k8k/OcteonTx: Select ACPI description as a default
  SolidRun/Cn913xCEx7Eval: Add ACPI support
  SolidRun/Cn913xCEx7Eval: Add platform support

edk2-non-osi:
  SolidRun/Cn913xCEx7Eval: Add DeviceTree

 Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc
|  54 ++
 Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc
|  64 +++
 Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc
|  64 +++
 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc
|  68 +++
 Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc  
|   7 +
 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc
|  57 +++
 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf   
|  30 ++
 
Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
 |  38 ++
 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf 
|  61 +++
 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.h 
|  30 ++
 
Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.h
   |  13 +
 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h  
|   9 +
 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h  
| 114 +
 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.c 
| 294 +++
 
Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.c
   |  89 
 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc
|  17 +
 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt.asl  
| 383 +++
 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt.asl  
| 493 +++
 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt.asl  
| 515 
 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl  
| 120 +
 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc   
|  74 +++
 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc   
|  87 
 22 files changed, 2681 insertions(+)
 create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc
 create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc
 create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc
 create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc
 create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc
 create mode 100644 
Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf
 create mode 100644 
Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
 create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf
 create mode 100644 
Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.h
 create mode 100644 
Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.h
 create mode 100644 
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h
 create mode 100644 
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h
 create mode 100644 
Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.c
 create mode 100644 
Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.c
 create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc
 create mode 100644 
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt.asl
 create mode 100644 
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt.asl
 create mode 100644 
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt.asl
 create mode 100644 
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl
 create mode 100644 
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc
 create mode 100644 
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc

-- 
2.

[edk2-devel] [edk2-platforms PATCH 1/3] Marvell: Armada7k8k/OcteonTx: Select ACPI description as a default

2021-08-06 Thread Marcin Wojtas

All currently supported platforms based on the Marvell SoCs offer
both DT and ACPI. Reverse the default setting and pick ACPI as the main
HW description.

Signed-off-by: Marcin Wojtas 
---
 Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc 
b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
index 25f3fc8dd8..d27e582b54 100644
--- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
@@ -240,6 +240,13 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0xF93E
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0xF93D
 
+  #
+  # Select ACPI as a default HW description
+  #
+!if $(ARCH) == AARCH64
+  gEmbeddedTokenSpaceGuid.PcdDefaultDtPref|FALSE
+!endif
+
 [PcdsFixedAtBuild.common]
   gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"EDK2 SH 1.0"
   gArmPlatformTokenSpaceGuid.PcdCoreCount|4
-- 
2.29.0



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Re: [edk2-devel] [PATCH 1/1] Platform/RaspberryPi: Add linux quirk support

2021-08-06 Thread Jeremy Linton


Hi,

On 8/6/21 10:47 AM, Andrei Warkentin wrote:

Hi Jeremy,

Reviewed-by: Andrei Warkentin 

MADT -> MCFG


Yah, I have to start thinking about what I'm typing :)



Root port registers would be NonCacheable just like the outbound mapping. 
(Also, with https://mantis.uefi.org/mantis/view.php?id=2220, _MEM attributes 
aside from  NonCacheable and Prefetchable are effectively deprecated).

Note: I really wish we had sorted out the HID/CID story for the PCIe RC... i.e. 
at least to make the HID custom for non-ECAM implementations and push 
PNP0A08/PNP0A03 in the CID... this would make linux,pcie-quirk unnecessary, 
using standard ACPI driver binding mechanisms to separate quirks from proper 
ECAM. Sadly, I think the train to do that has long left the station (with so 
many ACPI Arm systems out there and non-ECAM or not-quite-ECAM RCs using 
PNP0A08/PNP0A03 alone. ESXi, for example, ends up keying on the Table Ids 
(which is arguably even worse than the DT props)


This isn't a bad idea (changing the HID), but I think your right that 
ship might have sailed, although it might be still be an alternative for 
the SMC.





Note 2: Given that DT has users in U-Boot and the BSDs (and potentially anywhere else), there's a 
long term hope to make DT bindings separate from Linux. To that end "linux,pcie-quirk" 
and "linux,pcie-nomsi" should probably be named something else (although I recognise that 
you're probably just wiring up something that already exists).


Well I want this one to be linux specific, because hopefully everyone 
else realizes that the SMC is a better plan and ignores the property. 
Its not set anywhere so I can potentially change it. The linux posting 
is here:


https://lkml.org/lkml/2021/8/5/1109

(where I apparently typed MCFG instead of MADT correctly, well at least 
most of the time :) .


But I don't have a problem dropping the linux bit, although I would like 
that part to be generic so future SMC+quirked platforms don't have to 
modify the quirk detection code. Although lets see what Lorenzo/etc say 
about what i'm doing in that patch. Thats why I left this patch off the 
other set.






--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware

From: Jeremy Linton 
Sent: Thursday, August 5, 2021 7:40 PM
To: devel@edk2.groups.io 
Cc: p...@akeo.ie ; ardb+tianoc...@kernel.org ; Andrei 
Warkentin ; sunny.w...@arm.com ; 
samer.el-haj-mahm...@arm.com ; Jeremy Linton 
Subject: [PATCH 1/1] Platform/RaspberryPi: Add linux quirk support

Linux, for the time being has refused to support the Arm
standard SMCCC for PCIe configuration. Instead they
want to continue to maintain per device "quirks".

As the RPI isn't really ECAM this is a bit more
involved because the MADT can't really describe
the root port+config registers situation. Further
platforms which support the SMCCC shouldn't have
a MADT, so we need an additional way to tell linux
what it needs to know about this platform.

Signed-off-by: Jeremy Linton 
---
  Platform/RaspberryPi/AcpiTables/Pci.asl | 21 +
  1 file changed, 21 insertions(+)

diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl 
b/Platform/RaspberryPi/AcpiTables/Pci.asl
index 34474f13ef..3e7fd0d5b7 100644
--- a/Platform/RaspberryPi/AcpiTables/Pci.asl
+++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
@@ -123,6 +123,15 @@ DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", 
"RPI4PCIE", 2)
  Name(_BBN, Zero) // PCI Base Bus Number
  Name(_CCA, 0)// Mark the PCI noncoherent

+Name (_DSD, Package () {
+  ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+Package () {
+  Package () { "linux,pcie-quirk", "bcm2711" },
+  Package () { "linux,pcie-nomsi", 1 },
+}
+})
+
+
  // Root Complex 0
  Device (RP0) {
   Name(_ADR, 0xF000)// Dev 0, Func 0
@@ -176,6 +185,18 @@ DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", 
"RPI4PCIE", 2)
2   // SANITIZED_PCIE_MMIO_LEN + 1
,,,MMI1,,TypeTranslation
  )
+
+QWordMemory ( // Root port registers, not to be used if SMCCC is 
utilized
+  ResourceConsumer, ,
+  MinFixed, MaxFixed,
+  NonCacheable, ReadWrite,// cacheable? is that right?
+  0x, // Granularity
+  0xFD50, // Root port begin
+  0xFD509FFF, // Root port end
+  0x, // no translation
+  0xA000, // size
+  ,,
+)
}) // end Name(RBUF)

// Work around ASL's inability to add in a resource definition
--
2.13.7






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Re: [edk2-devel] [RFC] MemoryProtectionLib for Dynamic Memory Guard Settings

2021-08-06 Thread Andrew Fish via groups.io



> On Aug 1, 2021, at 7:35 PM, Ni, Ray  wrote:
> 
> I also vote "using HOB passing policy". This design helps the new 
> bootloader/payload architecture.
> 
> EDKII library class design was a good design which mimics C++ class to 
> provide same interface for:
> 1. different phases (PEI, DXE, runtime. E.g.: HobLib, PcdLib, 
> MemoryAllocationLib)
> 2. different source of policy (e.g.: DebugLib.)
> 3. different optimization mechanism (e.g.: BaseMemoryLib)
> 4. more...
> 

I also like to think of this in terms on static and dynamic linking. For things 
that would be statically linked we use EDKII library classes. For dynamic 
linking we use Protocol/PPI and the required the coder to write code, vs having 
a dynamic linker resolve it for you. 

> However, the extensive usage of lib class brings difficulty of understanding 
> the code. There are so many instances of a library class and it's hard to 
> know which one is being used by a certain module by just looking at the 
> source code. (Sometimes even I need to build the code base and check the 
> files in build directory to understand which lib instance is used for which 
> module.)
> 

The build log that can optionally be created by the tools is very useful for 
figuring all this kind of stuff out. Maybe we should come up with a best 
practice place to put those and turn it one for platforms that have scripts 
wrapping the build?

We could also build tooling to help with this? It is possible to add custom git 
commands to help in grepping code etc. So if people have ideas about tools we 
should discuss them….

Thanks,

Andrew Fish

> It's a common issue in projects using OO programing language. But most of 
> these projects are for application level needs and the app debugger is very 
> easy to use. This is the difference between EDKII projects and other OO 
> projects.
> 
> Thanks,
> Ray
> 
> -Original Message-
> From: devel@edk2.groups.io  
> mailto:devel@edk2.groups.io>> On Behalf Of Sean
> Sent: Saturday, July 31, 2021 2:42 AM
> To: devel@edk2.groups.io ; Yao, Jiewen 
> mailto:jiewen@intel.com>>; Taylor Beebe 
> mailto:t...@taylorbeebe.com>>; Wang, Jian J 
> mailto:jian.j.w...@intel.com>>
> Cc: Dong, Eric mailto:eric.d...@intel.com>>; Ni, Ray 
> mailto:ray...@intel.com>>; Kumar, Rahul1 
> mailto:rahul1.ku...@intel.com>>; 
> mikub...@linux.microsoft.com ; Wu, Hao A 
> mailto:hao.a...@intel.com>>; Bi, Dandan 
> mailto:dandan...@intel.com>>; gaolim...@byosoft.com.cn 
> ; Dong, Guo  >; Ma, Maurice  >; You, Benjamin  >
> Subject: Re: [edk2-devel] [RFC] MemoryProtectionLib for Dynamic Memory Guard 
> Settings
> 
> Jiewen,
> 
> **Slight rant**
> 
> I agree with libraries as an effective abstraction method.  But I think there 
> needs to be a broad discussion about the order of preference for methods of 
> abstraction.  Today the edk2 code base is a mix and often there are numerous 
> methods abstracting the same thing which leads to confusion, 
> misconfiguration, and error.
> 
> In the UEFI specification we have PPIs/Protocols/Events for functional 
> abstraction.  We have variables, guided config tables, and HII for data 
> abstraction.
> 
> In the PI specification we add HOBs and PCDs for data abstractions.
> 
> Finally, in EDKII we add the library class concept and leverage it heavily 
> for arch, phase, and platform/behavioral abstractions.
> 
> Without clear guidance for how and when to use the above it is hard to keep 
> code being developed by the larger community consistent.
> 
> **End**
> 
> I was leaning towards something closer to
> 
>>> Option 1: 
> https://github.com/TaylorBeebe/edk2/tree/memory_protection_lib_2
> 
> the HOB method and internally as we develop more code we are preferring HOB 
> and data abstractions more than functional abstraction.  Data abstractions 
> can be used to control functional differences as well if needed.  Data 
> abstractions allow for easier validation and support diverse code 
> environments.  For example standalone MM and payloadpkg/payload concepts.  
> Finally, data abstractions break the need 
> for a monolithic code base.   But as you can see in option 1 it actually 
> uses a library class abstraction as well because no one wants to write the 
> same code over and over again to get the HOB.  The contract of the library is 
> just data but it still requires library mappings.  Maybe these types of 
> libraries need to be treated differently.
> 
> Anyway it would be great to hear from other members of the community around 
> not just the memory protections RFC (this RFC) but around preferences for 
> abstraction techniques (pro/con).  If an actual discussion starts it could 
> move to design meeting.
> 
> Thanks
> Sean
> 
> 
> 
> 
> 
> 
> 
> On 7/29/2021 7:34 PM, Yao, Jiewen wrote:
>> Th

Re: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4

2021-08-06 Thread Jeremy Linton


Hi,

On 8/6/21 11:04 AM, Andrei Warkentin wrote:

Ok, I misunderstood the patch set (I thought the PciHostBridgeLib itself would 
eventually move to DEN0115).

I still think that (in general) would be a good idea - if not for the benefit 
of the Pi, then for the next upstreamed platform where you could avoid 
implementing custom config access code...


Right, the only bit that goes away is the PciSegmentLibGetConfigBase() 
code to be replaced by the SMC call. Which I will do, but I think its 
better to fix to this one and make that a separate patch-set ideally 
with another platform in parallel.





Reviewed-by: Andrei Warkentin 

--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware

From: Andrei Warkentin 
Sent: Friday, August 6, 2021 7:02 PM
To: devel@edk2.groups.io ; jeremy.lin...@arm.com 

Cc: p...@akeo.ie ; ardb+tianoc...@kernel.org ; 
sunny.w...@arm.com ; samer.el-haj-mahm...@arm.com 
; René Treffer 
Subject: Re: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for 
CM4

Hi Jeremy,

Is any of this still conceptually necessary if we adopt the SMCCC interface 
within UEFI?

Instead of assuming the first downstream bus is bus 1, could you read the 
secondary BN from the RP?

--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware

From: devel@edk2.groups.io  on behalf of Jeremy Linton via 
groups.io 
Sent: Thursday, August 5, 2021 7:35 PM
To: devel@edk2.groups.io 
Cc: p...@akeo.ie ; ardb+tianoc...@kernel.org ; Andrei Warkentin 
; sunny.w...@arm.com ; samer.el-haj-mahm...@arm.com 
; Jeremy Linton ; René Treffer 

Subject: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4

The CM4 has an actual pcie slot, so we need to move the linkup
check to the configuration probe logic. Further the device
restriction logic needs to be relaxed to support downstream
PCIe switches.

Suggested-by: René Treffer 
Signed-off-by: Jeremy Linton 
---
  .../Bcm2711PciHostBridgeLibConstructor.c   |  5 -
  .../Library/Bcm2711PciSegmentLib/PciSegmentLib.c   | 24 +++---
  2 files changed, 17 insertions(+), 12 deletions(-)

diff --git 
a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
 
b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
index 8587d2d36d..4d4c584726 100644
--- 
a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
+++ 
b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
@@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor (
} while (((Data & 0x30) != 0x030) && (Timeout));
DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, 
Timeout));

-  if ((Data & 0x30) != 0x30) {
-DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
-return EFI_DEVICE_ERROR;
-  }
-
if ((Data & 0x80) != 0x80) {
  DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data));
  return EFI_UNSUPPORTED;
diff --git 
a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c 
b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
index 44ce3b4b99..3ccc131eab 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
@@ -78,6 +78,8 @@ PciSegmentLibGetConfigBase (
UINT64Base;
UINT64Offset;
UINT32Dev;
+  UINT32Bus;
+  UINT32Data;

Base = PCIE_REG_BASE;
Offset = Address & 0xFFF; /* Pick off the 4k register offset */
@@ -89,17 +91,25 @@ PciSegmentLibGetConfigBase (
  Base += PCIE_EXT_CFG_DATA;
  if (mPciSegmentLastAccess != Address) {
Dev = EFI_PCI_ADDR_DEV (Address);
+  Bus = EFI_PCI_ADDR_BUS (Address);
+
/*
-   * Scan things out directly rather than translating the "bus" to a 
device, etc..
-   * only we need to limit each bus to a single device.
+   * There can only be a single device on bus 1 (downstream of root).
+   * Subsequent busses (behind a PCIe switch) can have more.
 */
-  if (Dev < 1) {
-  MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
-  mPciSegmentLastAccess = Address;
-  } else {
-  mPciSegmentLastAccess = 0;
+  if (Dev > 0 && (Bus < 2)) {
return 0x;
}
+
+  /* Don't probe slots if the link is down */
+  Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS);
+  if ((Data & 0x30) != 0x30) {
+  DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
+  return 0x;
+  }
+
+  MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
+  mPciSegmentLastAccess = Address;
  }
}
return Base + Offset;
--
2.13.7











-=-=-=-=-=

Re: [edk2-devel] [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT

2021-08-06 Thread Jeremy Linton


Hi,


So I've tested with all the comments below and everything seems to be 
working fine, so no issues there. I will re-post RSN.


Thanks,


On 8/6/21 8:42 AM, Ard Biesheuvel via groups.io wrote:

On Thu, 5 Aug 2021 at 18:36, Jeremy Linton  wrote:


Since we plan on toggling between XHCI and PCI the PCI
root needs to be in its own SSDT. This is all thats needed
of UEFI. The SMC conduit is provided directly to the running
OS. When the OS detects this PCIe port, on a machine without
a MADT it attempts to connect to the SMC conduit. The RPi
definition doesn't have any power mgmt, and only provides
a description of the root port.

Signed-off-by: Jeremy Linton 
---
  Platform/RaspberryPi/AcpiTables/AcpiTables.inf |   3 +
  Platform/RaspberryPi/AcpiTables/Pci.asl| 237 +
  Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c |   6 +
  3 files changed, 246 insertions(+)
  create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl

diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf 
b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
index f3e8d950c1..da2a6db85f 100644
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
@@ -39,6 +39,7 @@
Pptt.aslc
SsdtThermal.asl
Xhci.asl
+  Pci.asl

  [Packages]
ArmPkg/ArmPkg.dec
@@ -59,6 +60,8 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr
+  gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr
+  gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen
gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase
gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress
gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress
diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl 
b/Platform/RaspberryPi/AcpiTables/Pci.asl
new file mode 100644
index 00..34474f13ef
--- /dev/null
+++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
@@ -0,0 +1,237 @@
+/** @file
+ *
+ *  Copyright (c) 2019 Linaro, Limited. All rights reserved.
+ *  Copyright (c) 2021 Arm
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include 
+
+#include "AcpiTables.h"
+
+/*
+ * The following can be used to remove parenthesis from
+ * defined macros that the compiler complains about.
+ */
+#define ISOLATE_ARGS(...)   __VA_ARGS__
+#define REMOVE_PARENTHESES(x)   ISOLATE_ARGS x
+
+#define SANITIZED_PCIE_CPU_MMIO_WINDOW  
REMOVE_PARENTHESES(PCIE_CPU_MMIO_WINDOW)
+#define SANITIZED_PCIE_MMIO_LEN 
REMOVE_PARENTHESES(PCIE_BRIDGE_MMIO_LEN)
+#define SANITIZED_PCIE_PCI_MMIO_BEGIN   REMOVE_PARENTHESES(PCIE_TOP_OF_MEM_WIN)
+
+/*
+ * According to UEFI boot log for the VLI device on Pi 4.
+ */
+#define RT_REG_LENGTH 0x1000
+
+// copy paste job from juno
+#define LNK_DEVICE(Unique_Id, Link_Name, irq) \
+  Device(Link_Name) { \
+  Name(_HID, EISAID("PNP0C0F"))   \
+  Name(_UID, Unique_Id)   \
+  Name(_PRS, ResourceTemplate() { \
+  Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq }   \
+  })  \
+  Method (_CRS, 0) { Return (_PRS) }  \
+  Method (_SRS, 1) { }\
+  Method (_DIS) { }   \
+  }
+
+#define PRT_ENTRY(Address, Pin, Link)  
  \
+Package (4) {  
  \
+Address,/* uses the same format as _ADR */ 
  \
+Pin,/* The PCI pin number of the device (0-INTA, 1-INTB, 
2-INTC, 3-INTD). */ \
+Link,   /* Interrupt allocated via Link device. */ 
  \
+Zero/* global system interrupt number (no used) */ 
  \
+  }
+#define ROOT_PRT_ENTRY(Pin, Link)   PRT_ENTRY(0x, Pin, Link)
+


This can be done in a much simpler way - SynQuacer uses this, for instance

 Name (_PRT, Package () {
 Package () { 0x, 0, Zero, 222 },   // INTA
 Package () { 0x, 1, Zero, 222 },   // INTB
 Package () { 0x, 2, Zero, 222 },   // INTC
 Package () { 0x, 3, Zero, 222 },   // INTD
 })


+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)
+{
+  Scope (\_SB_)
+  {
+
+Device (SCB0) {
+  Name (_HID, "ACPI0004")
+  Name (_UID, 0x0)


Even if this file and the xhci one should never be exposed to the OS
at the same time, can we please use unique UIDs?



+  Name (_

Re: [edk2-devel] [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT

2021-08-06 Thread Jeremy Linton


Hi,

On 8/6/21 10:37 AM, Andrei Warkentin wrote:

Hi Jeremy,

MADT -> MCFG (and in other patches as well, where you refer to MADT)


I will take 4 letter acronyms that start with an M... 

Thanks,



The other feedback that Ard provided makes sense to me as well.

A

--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware

From: devel@edk2.groups.io  on behalf of Jeremy Linton via 
groups.io 
Sent: Thursday, August 5, 2021 7:35 PM
To: devel@edk2.groups.io 
Cc: p...@akeo.ie ; ardb+tianoc...@kernel.org ; Andrei 
Warkentin ; sunny.w...@arm.com ; 
samer.el-haj-mahm...@arm.com ; Jeremy Linton 
Subject: [edk2-devel] [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT

Since we plan on toggling between XHCI and PCI the PCI
root needs to be in its own SSDT. This is all thats needed
of UEFI. The SMC conduit is provided directly to the running
OS. When the OS detects this PCIe port, on a machine without
a MADT it attempts to connect to the SMC conduit. The RPi
definition doesn't have any power mgmt, and only provides
a description of the root port.

Signed-off-by: Jeremy Linton 
---
  Platform/RaspberryPi/AcpiTables/AcpiTables.inf |   3 +
  Platform/RaspberryPi/AcpiTables/Pci.asl| 237 +
  Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c |   6 +
  3 files changed, 246 insertions(+)
  create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl

diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf 
b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
index f3e8d950c1..da2a6db85f 100644
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
@@ -39,6 +39,7 @@
Pptt.aslc
SsdtThermal.asl
Xhci.asl
+  Pci.asl

  [Packages]
ArmPkg/ArmPkg.dec
@@ -59,6 +60,8 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr
+  gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr
+  gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen
gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase
gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress
gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress
diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl 
b/Platform/RaspberryPi/AcpiTables/Pci.asl
new file mode 100644
index 00..34474f13ef
--- /dev/null
+++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
@@ -0,0 +1,237 @@
+/** @file
+ *
+ *  Copyright (c) 2019 Linaro, Limited. All rights reserved.
+ *  Copyright (c) 2021 Arm
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include 
+
+#include "AcpiTables.h"
+
+/*
+ * The following can be used to remove parenthesis from
+ * defined macros that the compiler complains about.
+ */
+#define ISOLATE_ARGS(...)   __VA_ARGS__
+#define REMOVE_PARENTHESES(x)   ISOLATE_ARGS x
+
+#define SANITIZED_PCIE_CPU_MMIO_WINDOW  
REMOVE_PARENTHESES(PCIE_CPU_MMIO_WINDOW)
+#define SANITIZED_PCIE_MMIO_LEN 
REMOVE_PARENTHESES(PCIE_BRIDGE_MMIO_LEN)
+#define SANITIZED_PCIE_PCI_MMIO_BEGIN   REMOVE_PARENTHESES(PCIE_TOP_OF_MEM_WIN)
+
+/*
+ * According to UEFI boot log for the VLI device on Pi 4.
+ */
+#define RT_REG_LENGTH 0x1000
+
+// copy paste job from juno
+#define LNK_DEVICE(Unique_Id, Link_Name, irq) \
+  Device(Link_Name) { \
+  Name(_HID, EISAID("PNP0C0F"))   \
+  Name(_UID, Unique_Id)   \
+  Name(_PRS, ResourceTemplate() { \
+  Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq }   \
+  })  \
+  Method (_CRS, 0) { Return (_PRS) }  \
+  Method (_SRS, 1) { }\
+  Method (_DIS) { }   \
+  }
+
+#define PRT_ENTRY(Address, Pin, Link)  
  \
+Package (4) {  
  \
+Address,/* uses the same format as _ADR */ 
  \
+Pin,/* The PCI pin number of the device (0-INTA, 1-INTB, 
2-INTC, 3-INTD). */ \
+Link,   /* Interrupt allocated via Link device. */ 
  \
+Zero/* global system interrupt number (no used) */ 
  \
+  }
+#define ROOT_PRT_ENTRY(Pin, Link)   PRT_ENTRY(0x, Pin, Link)
+
+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)
+{
+  Scope (\_SB_)
+  {
+
+Device (SCB0) {
+  Name (_HID, "ACPI0004")
+  Name (_UID, 0x0)
+  Name (_CCA, 0x0)
+
+

Re: [edk2-devel] [PATCH v7 1/3] BaseTools: Remove COMMON section from the GCC discard list

2021-08-06 Thread Christopher Zurcher

Ard,
Is the removal of the COMMON section during the build not redundant to the 
-fno-common option? Do you expect cases where we will still see the undesired 
variable collisions?

Thanks,
Christopher Zurcher

-Original Message-
From: devel@edk2.groups.io  On Behalf Of gaoliming
Sent: Wednesday, August 4, 2021 22:04
To: 'Ard Biesheuvel' ; 'Yao, Jiewen' 
Cc: devel@edk2.groups.io; christopher.zurc...@outlook.com; 'Feng, Bob C' 

Subject: 回复: [edk2-devel] [PATCH v7 1/3] BaseTools: Remove COMMON section from 
the GCC discard list

Ard:
  Chris explains this change in https://edk2.groups.io/g/devel/message/77662. 
And, he also verifies the patch in OVMF with GCC5 tool chain. 

Thanks
Liming
> -邮件原件-
> 发件人: Ard Biesheuvel 
> 发送时间: 2021年8月4日 20:27
> 收件人: Yao, Jiewen 
> 抄送: devel@edk2.groups.io; christopher.zurc...@outlook.com; Feng, Bob C 
> ; Liming Gao 
> 主题: Re: [edk2-devel] [PATCH v7 1/3] BaseTools: Remove COMMON section 
> from the GCC discard list
> 
> On Wed, 21 Jul 2021 at 13:44, Yao, Jiewen  wrote:
> >
> > Acked-by: Jiewen Yao 
> >
> 
> I don't think this is a good idea tbh. We have already identified that
> EDK2 code often fails to use the STATIC keyword when possible for 
> global variables, and that unrelated variables that happen to have the 
> same name will be collapsed into the same storage unit in the program 
> image. (see commit 214a3b79417f64bf2faae74af42c1b9d23f50dc8 for
> details)
> 
> Was this considered? Is this no longer an issue?
> 
> 
> 
> > > -Original Message-
> > > From: devel@edk2.groups.io  On Behalf Of
> Christopher
> > > Zurcher
> > > Sent: Wednesday, July 21, 2021 6:07 AM
> > > To: devel@edk2.groups.io
> > > Cc: Ard Biesheuvel ; Feng, Bob C
> ;
> > > Liming Gao 
> > > Subject: [edk2-devel] [PATCH v7 1/3] BaseTools: Remove COMMON
> section
> > > from the GCC discard list
> > >
> > > From: Christopher Zurcher 
> > >
> > > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2507
> > >
> > > The COMMON section is used by OpenSSL assembly-optimized crypto 
> > > functions. OpenSSL assembly code is auto-generated from the 
> > > submodule and cannot be modified to remove dependence on the COMMON 
> > > section.
> > > The default -fno-common compiler flag should still prevent 
> > > variable from being emitted into the COMMON section.
> > >
> > > Cc: Ard Biesheuvel 
> > > Cc: Bob Feng 
> > > Cc: Liming Gao 
> > > Signed-off-by: Christopher Zurcher 
> > > 
> > > ---
> > >  BaseTools/Scripts/GccBase.lds | 1 -
> > >  1 file changed, 1 deletion(-)
> > >
> > > diff --git a/BaseTools/Scripts/GccBase.lds
> b/BaseTools/Scripts/GccBase.lds
> > > index a9dd2138d4..83cebd29d5 100644
> > > --- a/BaseTools/Scripts/GccBase.lds
> > > +++ b/BaseTools/Scripts/GccBase.lds
> > > @@ -74,6 +74,5 @@ SECTIONS {
> > >  *(.dynamic)
> > >  *(.hash .gnu.hash)
> > >  *(.comment)
> > > -*(COMMON)
> > >}
> > >  }
> > > --
> > > 2.32.0.windows.1
> > >
> > >
> > >
> > > 
> > >
> >









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[edk2-devel] [edk2-platforms][PATCH v1 1/1] MinPlatformPkg/AcpiTables: Update structures for ACPI 6.3

2021-08-06 Thread Michael Kubacki

From: Daniel Maddy 

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3535

Updates ACPI table structures in MinPlatformPkg for ACPI 6.3.

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Eric Dong 
Cc: Daniel Maddy 
Co-authored-by: Michael Kubacki 
Signed-off-by: Michael Kubacki 
---
 Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 203 
++--
 Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Facs/Facs.c|  11 +-
 Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.c|  74 ---
 3 files changed, 150 insertions(+), 138 deletions(-)

diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c 
b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
index 2b51c34ef2fd..5e3c4c0672f9 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
@@ -2,6 +2,7 @@
   ACPI Platform Driver
 
 Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) Microsoft Corporation.
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -13,7 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #pragma pack(1)
 
 typedef struct {
-  UINT32   AcpiProcessorId;
+  UINT32   AcpiProcessorUid;
   UINT32   ApicId;
   UINT32   Flags;
   UINT32   SwProcApicId;
@@ -27,9 +28,9 @@ typedef struct {
 // Define Union of IO APIC & Local APIC structure;
 //
 typedef union {
-  EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_STRUCTURE AcpiLocalApic;
-  EFI_ACPI_4_0_IO_APIC_STRUCTURE  AcpiIoApic;
-  EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE AcpiLocalx2Apic;
+  EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE   AcpiLocalApic;
+  EFI_ACPI_6_3_IO_APIC_STRUCTUREAcpiIoApic;
+  EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE AcpiLocalx2Apic;
   struct {
 UINT8 Type;
 UINT8 Length;
@@ -38,9 +39,9 @@ typedef union {
 
 #pragma pack()
 
-extern EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE  Facs;
-extern EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt;
-extern EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER  Hpet;
+extern EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs;
+extern EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLEFadt;
+extern EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER Hpet;
 extern EFI_ACPI_WSMT_TABLE Wsmt;
 
 VOID  *mLocalTable[] = {
@@ -217,7 +218,7 @@ DebugDisplayReOrderTable(
   DEBUG ((EFI_D_ERROR, "Index  AcpiProcId  ApicId  Flags  SwApicId  Skt\n"));
   for (Index=0; IndexAcpiApicCommon.Type;
-  LocalApicPtr = (EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_STRUCTURE 
*)(&((ACPI_APIC_STRUCTURE_PTR *)ApicPtr)->AcpiLocalApic);
-  LocalX2ApicPtr = (EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE 
*)(&((ACPI_APIC_STRUCTURE_PTR *)ApicPtr)->AcpiLocalx2Apic);
+  LocalApicPtr = (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE 
*)(&((ACPI_APIC_STRUCTURE_PTR *)ApicPtr)->AcpiLocalApic);
+  LocalX2ApicPtr = (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE 
*)(&((ACPI_APIC_STRUCTURE_PTR *)ApicPtr)->AcpiLocalx2Apic);
 
-  if(Type == EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC) {
+  if(Type == EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC) {
 if(!mX2ApicEnabled) {
-  LocalApicPtr->Flags   = 
(UINT8)mCpuApicIdOrderTable[LocalApicCounter].Flags;
-  LocalApicPtr->ApicId  = 
(UINT8)mCpuApicIdOrderTable[LocalApicCounter].ApicId;
-  LocalApicPtr->AcpiProcessorId = 
(UINT8)mCpuApicIdOrderTable[LocalApicCounter].AcpiProcessorId;
+  LocalApicPtr->Flags= 
(UINT8)mCpuApicIdOrderTable[LocalApicCounter].Flags;
+  LocalApicPtr->ApicId   = 
(UINT8)mCpuApicIdOrderTable[LocalApicCounter].ApicId;
+  LocalApicPtr->AcpiProcessorUid = 
(UINT8)mCpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
 } else {
-  LocalApicPtr->Flags   = 0;
-  LocalApicPtr->ApicId  = 0xFF;
-  LocalApicPtr->AcpiProcessorId = (UINT8)0xFF;
+  LocalApicPtr->Flags= 0;
+  LocalApicPtr->ApicId   = 0xFF;
+  LocalApicPtr->AcpiProcessorUid = (UINT8)0xFF;
   Status = EFI_UNSUPPORTED;
 }
-  } else if(Type == EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC) {
+  } else if(Type == EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC) {
 if(mX2ApicEnabled) {
   LocalX2ApicPtr->Flags= 
(UINT8)mCpuApicIdOrderTable[LocalApicCounter].Flags;
   LocalX2ApicPtr->X2ApicId = 
mCpuApicIdOrderTable[LocalApicCounter].ApicId;
-  LocalX2ApicPtr->AcpiProcessorUid = 
mCpuApicIdOrderTable[LocalApicCounter].AcpiProcessorId;
+  LocalX2ApicPtr->AcpiProcessorUid = 
mCpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
 } else {
   LocalX2ApicPtr->Flags= 0;
   LocalX2ApicPtr->X2ApicId = (UINT32)-1;
@@ -311,8 +312,8 @@ SortCpuLocalApicInTable (
 CpuIdMapPtr->ApicId  = (UINT32)ProcessorInfoBuffer.ProcessorId;
 CpuIdMapPtr->Flags   = ((ProcessorInfoBuffer.StatusFlag & 
PROCESSOR_ENABLED_BIT) != 0);
 CpuIdMapPtr->SocketNum = (UINT32)ProcessorInfoBuffer.Location.Packag

Re: [edk2-devel] [PATCH 1/4] UefiPayloadPkg: Add Fixed PCDs and use Macro to define the default value.

2021-08-06 Thread Guo Dong



Reviewed-by: Guo Dong 

-Original Message-
From: devel@edk2.groups.io  On Behalf Of Zhiguang Liu
Sent: Thursday, August 5, 2021 9:31 PM
To: devel@edk2.groups.io
Cc: Dong, Guo ; Ni, Ray ; Ma, Maurice 
; You, Benjamin 
Subject: [edk2-devel] [PATCH 1/4] UefiPayloadPkg: Add Fixed PCDs and use Macro 
to define the default value.

Add the three PCDs as fixed at build PCD:
  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule
  gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister
  gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister
The default value is defined as Macro, so it can be passed in at build command.

Cc: Guo Dong 
Cc: Ray Ni 
Cc: Maurice Ma 
Cc: Benjamin You 

Signed-off-by: Zhiguang Liu 
---
 UefiPayloadPkg/UefiPayloadPkg.dsc | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc 
b/UefiPayloadPkg/UefiPayloadPkg.dsc
index bcedf1c746..ba54f2057f 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -91,6 +91,13 @@
   DEFINE EMU_VARIABLE_ENABLE   = TRUE   DEFINE DISABLE_RESET_SYSTEM  = FALSE + 
 # Dfine the maximum size of the capsule image without a reset flag that the 
platform can support.+  DEFINE MAX_SIZE_NON_POPULATE_CAPSULE = 0xa0++  # 
Define RTC related register.+  DEFINE RTC_INDEX_REGISTER = 0x70+  DEFINE 
RTC_TARGET_REGISTER = 0x71+ [BuildOptions]   *_*_*_CC_FLAGS = 
-D DISABLE_NEW_DEPRECATED_INTERFACES   GCC:*_UNIXGCC_*_CC_FLAGS   = 
-DMDEPKG_NDEBUG@@ -324,7 +331,9 @@
 !else   gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F !endif-+  
gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|$(MAX_SIZE_NON_POPULATE_CAPSULE)+
  gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|$(RTC_INDEX_REGISTER)+  
gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister|$(RTC_TARGET_REGISTER)   #   
# The following parameters are set by Library/PlatformHookLib   #-- 
2.32.0.windows.2



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Re: [edk2-devel] [PATCH 2/4] UefiPayloadPkg: define some PCD as DynamicEX PCD

2021-08-06 Thread Guo Dong

Reviewed-by: Guo Dong 

-Original Message-
From: Liu, Zhiguang  
Sent: Thursday, August 5, 2021 9:31 PM
To: devel@edk2.groups.io
Cc: Dong, Guo ; Ni, Ray ; Ma, Maurice 
; You, Benjamin 
Subject: [PATCH 2/4] UefiPayloadPkg: define some PCD as DynamicEX PCD

Define some PCDs as DynamicEX PCD to be used as global variable.
Because PcdUartDefaultBaudRate is defined as DynamicEX, remove the code to set 
it in platformlib. That code was actually redundant.

Cc: Guo Dong 
Cc: Ray Ni 
Cc: Maurice Ma 
Cc: Benjamin You 

Signed-off-by: Zhiguang Liu 
---
 UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c   |  
5 -
 UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf |  
1 -
 UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.c   |  
4 
 UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.inf |  
1 -
 UefiPayloadPkg/UefiPayloadPkg.dsc  | 
28 ++--
 5 files changed, 18 insertions(+), 21 deletions(-)

diff --git a/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c 
b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
index 72a17dc8a7..d8453e5957 100644
--- a/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
+++ b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
@@ -75,11 +75,6 @@ PlatformHookSerialPortInitialize (
 return Status;   } -  Status = PcdSet64S (PcdUartDefaultBaudRate, 
SerialPortInfo.Baud);-  if (RETURN_ERROR (Status)) {-return Status;-  }-   
Status = PcdSet32S (PcdSerialClockRate, SerialPortInfo.InputHertz);   if 
(RETURN_ERROR (Status)) { return Status;diff --git 
a/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf 
b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
index 2415d99c64..3eeb94d8fa 100644
--- a/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
+++ b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
@@ -35,5 +35,4 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate## PRODUCES   
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride  ## PRODUCES   
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate   ## PRODUCES-  
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate ## PRODUCES   
gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters   ## PRODUCESdiff --git 
a/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.c 
b/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.c
index 6705f29505..bd433bdbe0 100644
--- a/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.c
+++ b/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHoo
+++ kLib.c
@@ -70,10 +70,6 @@ PlatformHookSerialPortInitialize (
 if (RETURN_ERROR (Status)) {   return Status; }-Status = 
PcdSet64S (PcdUartDefaultBaudRate, SerialPortInfo->BaudRate);-if 
(RETURN_ERROR (Status)) {-  return Status;-}  return 
RETURN_SUCCESS;   }diff --git 
a/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.inf 
b/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.inf
index 41e05ddf54..2dfd8b1216 100644
--- a/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.inf
+++ b/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHoo
+++ kLib.inf
@@ -38,4 +38,3 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase## PRODUCES   
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate## PRODUCES   
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride  ## PRODUCES-  
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate ## PRODUCESdiff --git 
a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayloadPkg.dsc
index ba54f2057f..d293211e46 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -308,11 +308,6 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0-!if $(TARGET) == DEBUG-  
gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE-!else-  
gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE-!endif   
gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE   
gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE @@ -352,11 +347,6 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|$(SERIAL_FIFO_CONTROL)   
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|$(SERIAL_EXTENDED_TX_FIFO_SIZE)
 -  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(UART_DEFAULT_BAUD_RATE)-  
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|$(UART_DEFAULT_DATA_BITS)-  
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|$(UART_DEFAULT_PARITY)-  
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|$(UART_DEFAULT_STOP_BITS)-  
gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|$(DEFAULT_TERMINAL_TYPE)   
gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|$(PCI_SERIAL_PARAMETERS)  
  
gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalPr

Re: [edk2-devel] [PATCH 3/4] UefiPayloadPkg: change the default value of some PCDs.

2021-08-06 Thread Guo Dong



Reviewed-by: Guo Dong 

-Original Message-
From: Liu, Zhiguang  
Sent: Thursday, August 5, 2021 9:31 PM
To: devel@edk2.groups.io
Cc: Dong, Guo ; Ni, Ray ; Ma, Maurice 
; You, Benjamin 
Subject: [PATCH 3/4] UefiPayloadPkg: change the default value of some PCDs.

Change the default value of the below PCDs to diable some legacy feature.
  gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE
  gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceForOptionRom|FALSE
  gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0

Cc: Guo Dong 
Cc: Ray Ni 
Cc: Maurice Ma 
Cc: Benjamin You 

Signed-off-by: Zhiguang Liu 
---
 UefiPayloadPkg/UefiPayloadPkg.dsc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc 
b/UefiPayloadPkg/UefiPayloadPkg.dsc
index d293211e46..002d2a8fa7 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -297,6 +297,8 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE

   ## This PCD specified whether ACPI SDT protocol is installed.

   gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE

+  gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE

+  gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceForOptionRom|FALSE

 

 [PcdsFixedAtBuild]

   gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x1

@@ -350,7 +352,7 @@
   
gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|$(PCI_SERIAL_PARAMETERS)

 

   
gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|$(MAX_LOGICAL_PROCESSORS)

-

+  gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0

 

 


 #

-- 
2.32.0.windows.2



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Re: [edk2-devel] [PATCH 4/4] UefiPayloadPkg: Add a macro to enable or diable the serial driver.

2021-08-06 Thread Guo Dong



Reviewed-by: Guo Dong 

-Original Message-
From: Liu, Zhiguang  
Sent: Thursday, August 5, 2021 9:31 PM
To: devel@edk2.groups.io
Cc: Dong, Guo ; Ni, Ray ; Ma, Maurice 
; You, Benjamin 
Subject: [PATCH 4/4] UefiPayloadPkg: Add a macro to enable or diable the serial 
driver.

This patch doesn't change the default behavior.

Cc: Guo Dong 
Cc: Ray Ni 
Cc: Maurice Ma 
Cc: Benjamin You 

Signed-off-by: Zhiguang Liu 
---
 UefiPayloadPkg/UefiPayloadPkg.dsc | 4   UefiPayloadPkg/UefiPayloadPkg.fdf 
| 2 ++
 2 files changed, 6 insertions(+)

diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc 
b/UefiPayloadPkg/UefiPayloadPkg.dsc
index 002d2a8fa7..b4a30be381 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -98,6 +98,8 @@
   DEFINE RTC_INDEX_REGISTER = 0x70   DEFINE RTC_TARGET_REGISTER = 0x71 +  
DEFINE SERIAL_DRIVER_ENABLE = TRUE+ [BuildOptions]   *_*_*_CC_FLAGS 
= -D DISABLE_NEW_DEPRECATED_INTERFACES   GCC:*_UNIXGCC_*_CC_FLAGS   = 
-DMDEPKG_NDEBUG@@ -536,7 +538,9 @@
   #   # ISA Support   #+!if $(SERIAL_DRIVER_ENABLE) == TRUE   
MdeModulePkg/Universal/SerialDxe/SerialDxe.inf+!endif !if 
$(PS2_KEYBOARD_ENABLE) == TRUE   OvmfPkg/SioBusDxe/SioBusDxe.inf   
MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.infdiff --git 
a/UefiPayloadPkg/UefiPayloadPkg.fdf b/UefiPayloadPkg/UefiPayloadPkg.fdf
index 041fed842c..b2cfb6b405 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.fdf
+++ b/UefiPayloadPkg/UefiPayloadPkg.fdf
@@ -136,7 +136,9 @@ INF 
MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
 # # ISA Support #+!if $(SERIAL_DRIVER_ENABLE) == TRUE INF 
MdeModulePkg/Universal/SerialDxe/SerialDxe.inf+!endif !if 
$(PS2_KEYBOARD_ENABLE) == TRUE INF OvmfPkg/SioBusDxe/SioBusDxe.inf INF 
MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf--
2.32.0.windows.2



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Re: [edk2-devel] [PATCH] UefiPayloadPkg/PayloadEntry: Inherit 4/5-level paging from bootloader

2021-08-06 Thread Guo Dong



Reviewed-by: Guo Dong 

-Original Message-
From: Ni, Ray  
Sent: Friday, August 6, 2021 1:16 AM
To: devel@edk2.groups.io
Cc: Dong, Guo ; Ma, Maurice ; You, 
Benjamin 
Subject: [PATCH] UefiPayloadPkg/PayloadEntry: Inherit 4/5-level paging from 
bootloader

The patch removes the dep on PcdUse5LevelPageTable.
Now the payload inherits the 5-level paging setting from bootloader in IA-32e 
mode and uses 4-level paging in legacy protected mode.

This fix the potential issue when bootloader enables 5-level paging but 64bit 
payload sets 4-level page table to CR3 resulting CPU exception because 
PcdUse5LevelPageTable is FALSE.

Signed-off-by: Ray Ni 
Cc: Guo Dong 
Cc: Ray Ni 
Cc: Maurice Ma 
Cc: Benjamin You 
---
 .../UefiPayloadEntry/UefiPayloadEntry.inf |  1 -
 .../UniversalPayloadEntry.inf |  1 -
 .../UefiPayloadEntry/X64/VirtualMemory.c  | 38 ---
 3 files changed, 16 insertions(+), 24 deletions(-)

diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf 
b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
index 8d42925fcd..9b6fab66a1 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
+++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
@@ -80,7 +80,6 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask## 
CONSUMES   gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask  
 ## CONSUMES   gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard  
 ## CONSUMES-  gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable 
 ## SOMETIMES_CONSUMES   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase 
   ## CONSUMES   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize 
   ## CONSUMES diff --git 
a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf 
b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
index 416a620598..aae62126e9 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
+++ b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
@@ -85,7 +85,6 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask## 
CONSUMES   gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask  
 ## CONSUMES   gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard  
 ## CONSUMES-  gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable 
 ## SOMETIMES_CONSUMES   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase 
   ## CONSUMES   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize 
   ## CONSUMES diff --git 
a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c 
b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
index a1c4ad6ff4..9daa46c12c 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
@@ -15,7 +15,7 @@
 2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 
2:Instruction Set Reference, Intel 3) IA-32 Intel(R) Architecture Software 
Developer's Manual Volume 3:System Programmer's Guide, Intel -Copyright (c) 
2006 - 2020, Intel Corporation. All rights reserved.+Copyright (c) 2006 - 
2021, Intel Corporation. All rights reserved. Copyright (c) 2017, AMD 
Incorporated. All rights reserved.  SPDX-License-Identifier: 
BSD-2-Clause-Patent@@ -668,7 +668,6 @@ CreateIdentityMappingPageTables (
   ) {   UINT32RegEax;-  
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX   EcxFlags;   UINT32
RegEdx;   UINT8 
PhysicalAddressBits;   EFI_PHYSICAL_ADDRESS  
PageAddress;@@ -687,7 +686,7 @@ CreateIdentityMappingPageTables (
   UINTN TotalPagesNum;   UINTN 
BigPageAddress;   VOID  
*Hob;-  BOOLEAN   
Page5LevelSupport;+  BOOLEAN   
Enable5LevelPaging;   BOOLEAN   
Page1GSupport;   PAGE_TABLE_1G_ENTRY   
*PageDirectory1GEntry;   UINT64
AddressEncMask;@@ -730,18 +729,16 @@ CreateIdentityMappingPageTables (
 }   } -  Page5LevelSupport = FALSE;-  if (PcdGetBool 
(PcdUse5LevelPageTable)) {-AsmCpuidEx (-  
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, NULL,-  
&EcxFlags.Uint32, NULL, NULL-  );-if (EcxFlags.Bits.FiveLevelPage != 0) 
{-  Page5LevelSupport = TRUE;-}-  }+  //+  // Check CR4.LA57[bit12] to 
determin whether 5-Level Paging is enabled.+  // Because this code runs at both 
IA-32e (64bit) mode and legacy protected (32bit) mode,+  // below logic 
inherits the 5-level paging setting from bootloader in IA-32e mode+  // and 
uses 4-level paging in legacy protect

[edk2-devel] [RFC PATCH 3/7] SecurityPkg/TPM: Disable PcdGetBool (PcdRandomizePlatformHierarchy)

2021-08-06 Thread Stefan Berger

To avoid this type of build errors, disable
'PcdGetBool (PcdRandomizePlatformHierarchy)'.

Building ... 
/home/stefanb/dev/edk2/SecurityPkg/Library/SecureBootVariableProvisionLib/SecureBootVariableProvisionLib.inf
 [X64]
In file included from 
/home/stefanb/dev/edk2/Build/OvmfX64/DEBUG_GCC5/X64/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib/DEBUG/AutoGen.h:17,
 from :
/home/stefanb/dev/edk2/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c:
 In function ‘ConfigureTpmPlatformHierarchy’:
/home/stefanb/dev/edk2/MdePkg/Include/Library/PcdLib.h:424:45: error: 
‘_PCD_GET_MODE_BOOL_PcdRandomizePlatformHierarchy’ undeclared (first use in 
this function)
  424 | #define PcdGetBool(TokenName)   
_PCD_GET_MODE_BOOL_##TokenName
  | ^~~

Signed-off-by: Stefan Berger 
---
 .../PeiDxeTpmPlatformHierarchyLib.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git 
a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c
 
b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c
index 9812ab99ab..bea10d37a4 100644
--- 
a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c
+++ 
b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c
@@ -252,7 +252,7 @@ EFIAPI
 ConfigureTpmPlatformHierarchy (

   )

 {

-  if (PcdGetBool (PcdRandomizePlatformHierarchy)) {

+  if (1 /*PcdGetBool (PcdRandomizePlatformHierarchy)*/) {

 //

 // Send Tpm2HierarchyChange Auth with random value to avoid PlatformAuth 
being null

 //

-- 
2.31.1



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[edk2-devel] [RFC PATCH 6/7] OVMF: Reference new classes in the build system for compilation

2021-08-06 Thread Stefan Berger

Compile the added code now.

Signed-off-by: Stefan Berger 
---
 OvmfPkg/AmdSev/AmdSevX64.dsc   | 3 +++
 .../Library/PlatformBootManagerLib/PlatformBootManagerLib.inf  | 1 +
 OvmfPkg/OvmfPkgIa32.dsc| 3 +++
 OvmfPkg/OvmfPkgIa32X64.dsc | 3 +++
 OvmfPkg/OvmfPkgX64.dsc | 3 +++
 5 files changed, 13 insertions(+)

diff --git a/OvmfPkg/AmdSev/AmdSevX64.dsc b/OvmfPkg/AmdSev/AmdSevX64.dsc
index e6cd10b759..6b582626ff 100644
--- a/OvmfPkg/AmdSev/AmdSevX64.dsc
+++ b/OvmfPkg/AmdSev/AmdSevX64.dsc
@@ -209,9 +209,11 @@
   
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibQemu/DxeTcg2PhysicalPresenceLib.inf
   
Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorLibNull.inf
   
TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf
+  
TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf
 !else
   
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibNull/DxeTcg2PhysicalPresenceLib.inf
   
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+  
TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.inf
 !endif
 
 [LibraryClasses.common]
@@ -836,6 +838,7 @@
   SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf {
 
   
Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibRouterDxe.inf
+  
TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf
   NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf
   
HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCryptoRouterDxe.inf
   NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf
diff --git a/OvmfPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf 
b/OvmfPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
index e470b9a6a3..e7d1917022 100644
--- a/OvmfPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+++ b/OvmfPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -56,6 +56,7 @@
   PlatformBmPrintScLib
   Tcg2PhysicalPresenceLib
   XenPlatformLib
+  TpmPlatformHierarchyLib
 
 [Pcd]
   gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent
diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index d1d92c97ba..374a1ea652 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -235,9 +235,11 @@
   
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibQemu/DxeTcg2PhysicalPresenceLib.inf
   
Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorLibNull.inf
   
TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf
+  
TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf
 !else
   
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibNull/DxeTcg2PhysicalPresenceLib.inf
   
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+  
TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.inf
 !endif
 
 [LibraryClasses.common]
@@ -711,6 +713,7 @@
   SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.inf {
 
   
HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCryptoRouterPei.inf
+  
TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf
   NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf
   NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.inf
   NULL|SecurityPkg/Library/HashInstanceLibSha384/HashInstanceLibSha384.inf
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index a467ab7090..7b7dffcd94 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -239,9 +239,11 @@
   
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibQemu/DxeTcg2PhysicalPresenceLib.inf
   
Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorLibNull.inf
   
TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf
+  
TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf
 !else
   
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibNull/DxeTcg2PhysicalPresenceLib.inf
   
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+  
TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.inf
 !endif
 
 [LibraryClasses.common]
@@ -1034,6 +1036,7 @@
   SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf {
 
   
Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibRouterDxe.inf
+  
TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHi

[edk2-devel] [RFC PATCH 7/7] OVMF: Disable the TPM2 platform hierarchy

2021-08-06 Thread Stefan Berger

Use the newly added functions to disable the TPM2 platform hierarchy.

Signed-off-by: Stefan Berger 
---
 OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c  | 6 ++
 OvmfPkg/Library/PlatformBootManagerLibBhyve/BdsPlatform.c | 6 ++
 OvmfPkg/Library/PlatformBootManagerLibGrub/BdsPlatform.c  | 6 ++
 3 files changed, 18 insertions(+)

diff --git a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c 
b/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c
index b0e9742937..5bf145ba25 100644
--- a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c
+++ b/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 
@@ -1516,6 +1517,11 @@ PlatformBootManagerAfterConsole (
   //
   Tcg2PhysicalPresenceLibProcessRequest (NULL);
 
+  //
+  // Disable the TPM 2 platform hierarchy
+  //
+  ConfigureTpmPlatformHierarchy ();
+
   //
   // Process QEMU's -kernel command line option
   //
diff --git a/OvmfPkg/Library/PlatformBootManagerLibBhyve/BdsPlatform.c 
b/OvmfPkg/Library/PlatformBootManagerLibBhyve/BdsPlatform.c
index eaade4adea..09418dc4ff 100644
--- a/OvmfPkg/Library/PlatformBootManagerLibBhyve/BdsPlatform.c
+++ b/OvmfPkg/Library/PlatformBootManagerLibBhyve/BdsPlatform.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -1450,6 +1451,11 @@ PlatformBootManagerAfterConsole (
   //
   Tcg2PhysicalPresenceLibProcessRequest (NULL);
 
+  //
+  // Disable the TPM 2 platform hierarchy
+  //
+  ConfigureTpmPlatformHierarchy ();
+
   //
   // Perform some platform specific connect sequence
   //
diff --git a/OvmfPkg/Library/PlatformBootManagerLibGrub/BdsPlatform.c 
b/OvmfPkg/Library/PlatformBootManagerLibGrub/BdsPlatform.c
index 7cceeea487..508e2b6403 100644
--- a/OvmfPkg/Library/PlatformBootManagerLibGrub/BdsPlatform.c
+++ b/OvmfPkg/Library/PlatformBootManagerLibGrub/BdsPlatform.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 
 
 //
@@ -1315,6 +1316,11 @@ PlatformBootManagerAfterConsole (
   //
   Tcg2PhysicalPresenceLibProcessRequest (NULL);
 
+  //
+  // Disable the TPM 2 platform hierachy
+  //
+  ConfigureTpmPlatformHierarchy ();
+
   //
   // Process QEMU's -kernel command line option
   //
-- 
2.31.1



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[edk2-devel] [RFC PATCH 1/7] SecurityPkg/TPM: Import PeiDxeTpmPlatformHierarchyLib.c from edk2-platforms

2021-08-06 Thread Stefan Berger

Signed-off-by: Stefan Berger 
---
 .../Include/Library/TpmPlatformHierarchyLib.h |  27 ++
 .../PeiDxeTpmPlatformHierarchyLib.c   | 266 ++
 .../PeiDxeTpmPlatformHierarchyLib.inf |  45 +++
 3 files changed, 338 insertions(+)
 create mode 100644 SecurityPkg/Include/Library/TpmPlatformHierarchyLib.h
 create mode 100644 
SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c
 create mode 100644 
SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf

diff --git a/SecurityPkg/Include/Library/TpmPlatformHierarchyLib.h 
b/SecurityPkg/Include/Library/TpmPlatformHierarchyLib.h
new file mode 100644
index 00..a872fa09dc
--- /dev/null
+++ b/SecurityPkg/Include/Library/TpmPlatformHierarchyLib.h
@@ -0,0 +1,27 @@
+/** @file
+TPM Platform Hierarchy configuration library.
+
+This library provides functions for customizing the TPM's Platform 
Hierarchy
+Authorization Value (platformAuth) and Platform Hierarchy Authorization
+Policy (platformPolicy) can be defined through this function.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.
+Copyright (c) Microsoft Corporation.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _TPM_PLATFORM_HIERARCHY_LIB_H_
+#define _TPM_PLATFORM_HIERARCHY_LIB_H_
+
+/**
+   This service will perform the TPM Platform Hierarchy configuration at the 
SmmReadyToLock event.
+
+**/
+VOID
+EFIAPI
+ConfigureTpmPlatformHierarchy (
+  VOID
+  );
+
+#endif
diff --git 
a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c
 
b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c
new file mode 100644
index 00..9812ab99ab
--- /dev/null
+++ 
b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c
@@ -0,0 +1,266 @@
+/** @file
+TPM Platform Hierarchy configuration library.
+
+This library provides functions for customizing the TPM's Platform 
Hierarchy
+Authorization Value (platformAuth) and Platform Hierarchy Authorization
+Policy (platformPolicy) can be defined through this function.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.
+Copyright (c) Microsoft Corporation.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+@par Specification Reference:
+
https://trustedcomputinggroup.org/resource/tcg-tpm-v2-0-provisioning-guidance/
+**/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+//
+// The authorization value may be no larger than the digest produced by the 
hash
+//   algorithm used for context integrity.
+//
+#define  MAX_NEW_AUTHORIZATION_SIZE SHA512_DIGEST_SIZE
+
+UINT16   mAuthSize;
+
+/**
+  Generate high-quality entropy source through RDRAND.
+
+  @param[in]   LengthSize of the buffer, in bytes, to fill with.
+  @param[out]  Entropy   Pointer to the buffer to store the entropy data.
+
+  @retval EFI_SUCCESSEntropy generation succeeded.
+  @retval EFI_NOT_READY  Failed to request random data.
+
+**/
+EFI_STATUS
+EFIAPI
+RdRandGenerateEntropy (
+  IN UINTN Length,
+  OUT UINT8*Entropy
+  )
+{
+  EFI_STATUS  Status;
+  UINTN   BlockCount;
+  UINT64  Seed[2];
+  UINT8   *Ptr;
+
+  Status = EFI_NOT_READY;
+  BlockCount = Length / 64;
+  Ptr = (UINT8 *)Entropy;
+
+  //
+  // Generate high-quality seed for DRBG Entropy
+  //
+  while (BlockCount > 0) {
+Status = GetRandomNumber128 (Seed);
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+CopyMem (Ptr, Seed, 64);
+
+BlockCount--;
+Ptr = Ptr + 64;
+  }
+
+  //
+  // Populate the remained data as request.
+  //
+  Status = GetRandomNumber128 (Seed);
+  if (EFI_ERROR (Status)) {
+return Status;
+  }
+  CopyMem (Ptr, Seed, (Length % 64));
+
+  return Status;
+}
+
+/**
+  This function returns the maximum size of TPM2B_AUTH; this structure is used 
for an authorization value
+  and limits an authValue to being no larger than the largest digest produced 
by a TPM.
+
+  @param[out] AuthSize Tpm2 Auth size
+
+  @retval EFI_SUCCESS  Auth size returned.
+  @retval EFI_DEVICE_ERROR Can not return platform auth due to 
device error.
+
+**/
+EFI_STATUS
+EFIAPI
+GetAuthSize (
+  OUT UINT16*AuthSize
+  )
+{
+  EFI_STATUSStatus;
+  TPML_PCR_SELECTIONPcrs;
+  UINTN Index;
+  UINT16DigestSize;
+
+  Status = EFI_SUCCESS;
+
+  while (mAuthSize == 0) {
+
+mAuthSize = SHA1_DIGEST_SIZE;
+ZeroMem (&Pcrs, sizeof (TPML_PCR_SELECTION));
+Status = Tpm2GetCapabilityPcrs (&Pcrs);
+
+if (EFI_ERROR (Status)) {
+  DEBUG ((DEBUG_ERROR, "Tpm2GetCapabilityPcrs fail!\n"));
+  break;
+}
+
+DEBUG ((DEBUG_ERROR, "Tpm2GetCapabilityPcrs - %08x\n", Pcrs.count));
+
+for (Index = 0; Index < Pcrs.count; Index++) {
+  DEBUG ((DEBUG_ERROR, "alg - %x\n", Pcr

[edk2-devel] [RFC PATCH 0/7] OVMF: Disable the TPM2 platform hierarchy

2021-08-06 Thread Stefan Berger

This series imports code from the edk2-platforms project related to
changing the password of the TPM2 platform hierarchy and uses it to
disable the TPM2 platform hierarchy in OVMF. It addresses the OVMF
aspects of the following bugs:

https://bugzilla.tianocore.org/show_bug.cgi?id=3510
https://bugzilla.tianocore.org/show_bug.cgi?id=3499

There's no doubt that my struggles with the build system and handling
of dependencies are visible in this series. Quite a few aspects of
getting things right are more or less guesswork and I am often not sure
what the correct way of doing things are. If 'you' wanted to fix
things up and repost it, please go ahead...

Stefan

Stefan Berger (7):
  SecurityPkg/TPM: Import PeiDxeTpmPlatformHierarchyLib.c from
edk2-platforms
  SecruityPkg/TPM: Disable dependency on MinPlatformPkg
  SecurityPkg/TPM: Disable PcdGetBool (PcdRandomizePlatformHierarchy)
  SecurityPkg/TPM: Disable a Pcd
  SecurityPkg/TPM: Add a NULL implementation of
PeiDxeTpmPlatformHierarchyLib
  OVMF: Reference new classes in the build system for compilation
  OVMF: Disable the TPM2 platform hierarchy

 OvmfPkg/AmdSev/AmdSevX64.dsc  |   3 +
 .../PlatformBootManagerLib/BdsPlatform.c  |   6 +
 .../PlatformBootManagerLib.inf|   1 +
 .../PlatformBootManagerLibBhyve/BdsPlatform.c |   6 +
 .../PlatformBootManagerLibGrub/BdsPlatform.c  |   6 +
 OvmfPkg/OvmfPkgIa32.dsc   |   3 +
 OvmfPkg/OvmfPkgIa32X64.dsc|   3 +
 OvmfPkg/OvmfPkgX64.dsc|   3 +
 .../Include/Library/TpmPlatformHierarchyLib.h |  27 ++
 .../PeiDxeTpmPlatformHierarchyLib.c   | 266 ++
 .../PeiDxeTpmPlatformHierarchyLib.inf |  46 +++
 .../PeiDxeTpmPlatformHierarchyLib.c   |  23 ++
 .../PeiDxeTpmPlatformHierarchyLib.inf |  39 +++
 13 files changed, 432 insertions(+)
 create mode 100644 SecurityPkg/Include/Library/TpmPlatformHierarchyLib.h
 create mode 100644 
SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c
 create mode 100644 
SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf
 create mode 100644 
SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.c
 create mode 100644 
SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.inf

-- 
2.31.1



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[edk2-devel] [RFC PATCH 4/7] SecurityPkg/TPM: Disable a Pcd

2021-08-06 Thread Stefan Berger

Fix the following build issue.

/home/stefanb/dev/edk2/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf(46):
 error 4000: Value of Guid [gMinPlatformPkgTokenSpaceGuid] is not found under 
[Guids] section in
/home/stefanb/dev/edk2/MdePkg/MdePkg.dec
/home/stefanb/dev/edk2/MdeModulePkg/MdeModulePkg.dec
/home/stefanb/dev/edk2/SecurityPkg/SecurityPkg.dec
/home/stefanb/dev/edk2/CryptoPkg/CryptoPkg.dec

Signed-off-by: Stefan Berger 
---
 .../PeiDxeTpmPlatformHierarchyLib.inf | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git 
a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf
 
b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf
index 1f23032e46..f1effd3ffb 100644
--- 
a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf
+++ 
b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf
@@ -42,5 +42,5 @@
 [Sources]
   PeiDxeTpmPlatformHierarchyLib.c
 
-[Pcd]
-  gMinPlatformPkgTokenSpaceGuid.PcdRandomizePlatformHierarchy
+#[Pcd]
+#  gMinPlatformPkgTokenSpaceGuid.PcdRandomizePlatformHierarchy
-- 
2.31.1



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[edk2-devel] [RFC PATCH 5/7] SecurityPkg/TPM: Add a NULL implementation of PeiDxeTpmPlatformHierarchyLib

2021-08-06 Thread Stefan Berger

Signed-off-by: Stefan Berger 
---
 .../PeiDxeTpmPlatformHierarchyLib.c   | 23 +++
 .../PeiDxeTpmPlatformHierarchyLib.inf | 39 +++
 2 files changed, 62 insertions(+)
 create mode 100644 
SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.c
 create mode 100644 
SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.inf

diff --git 
a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.c
 
b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.c
new file mode 100644
index 00..e871ada230
--- /dev/null
+++ 
b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.c
@@ -0,0 +1,23 @@
+/** @file
+Null TPM Platform Hierarchy configuration library.
+
+This library provides stub functions for customizing the TPM's Platform 
Hierarchy
+Authorization Value (platformAuth) and Platform Hierarchy Authorization
+Policy (platformPolicy) can be defined through this function.
+
+Copyright (c) 2021, IBM Corporation.
+Copyright (c) 2019, Intel Corporation. All rights reserved.
+Copyright (c) Microsoft Corporation.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+
+VOID
+EFIAPI
+ConfigureTpmPlatformHierarchy (
+  )
+{
+  /* no nothing */
+}
diff --git 
a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.inf
 
b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.inf
new file mode 100644
index 00..678f38410a
--- /dev/null
+++ 
b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.inf
@@ -0,0 +1,39 @@
+### @file
+#
+#   TPM Platform Hierarchy configuration library.
+#
+#   This library provides functions for customizing the TPM's Platform 
Hierarchy
+#   Authorization Value (platformAuth) and Platform Hierarchy Authorization
+#   Policy (platformPolicy) can be defined through this function.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# Copyright (c) Microsoft Corporation.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = PeiDxeTpmPlatformHierarchyLibNull
+  FILE_GUID  = 7794F92C-4E8E-4E57-9E4A-49A0764C7D73
+  MODULE_TYPE= PEIM
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = TpmPlatformHierarchyLib|PEIM DXE_DRIVER
+
+[LibraryClasses]
+  BaseLib
+#  BaseMemoryLib
+#  DebugLib
+#  MemoryAllocationLib
+#  PcdLib
+#  RngLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  SecurityPkg/SecurityPkg.dec
+  CryptoPkg/CryptoPkg.dec
+
+[Sources]
+  PeiDxeTpmPlatformHierarchyLib.c
-- 
2.31.1



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[edk2-devel] [RFC PATCH 2/7] SecruityPkg/TPM: Disable dependency on MinPlatformPkg

2021-08-06 Thread Stefan Berger

Disable the dependency on the MinPlatformPkg to avoid this type of build
errors:

/home/stefanb/dev/edk2/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf(39):
 error 000E: File/directory not found in workspace
/home/stefanb/dev/edk2/MinPlatformPkg/MinPlatformPkg.dec

Signed-off-by: Stefan Berger 
---
 .../PeiDxeTpmPlatformHierarchyLib.inf  | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git 
a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf
 
b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf
index b7a7fb0a08..1f23032e46 100644
--- 
a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf
+++ 
b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf
@@ -36,7 +36,8 @@
   MdeModulePkg/MdeModulePkg.dec
   SecurityPkg/SecurityPkg.dec
   CryptoPkg/CryptoPkg.dec
-  MinPlatformPkg/MinPlatformPkg.dec
+
+#  MinPlatformPkg/MinPlatformPkg.dec
 
 [Sources]
   PeiDxeTpmPlatformHierarchyLib.c
-- 
2.31.1



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Re: [edk2-devel] [Patch 0/3] Ext4Pkg: Add Ext4Pkg

2021-08-06 Thread Michael D Kinney



> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Pedro Falcato
> Sent: Thursday, August 5, 2021 3:50 PM
> To: Kinney, Michael D ; devel@edk2.groups.io
> Cc: Leif Lindholm ; Bret Barkelew 
> 
> Subject: Re: [edk2-devel] [Patch 0/3] Ext4Pkg: Add Ext4Pkg
> 
> Hi Mike,
> 
> Thanks for the helpful pointers. I'll consider everything for V2,
> which I'll submit as soon as possible (hopefully tomorrow).
> 
> RE: Code style. I'll re-run ECC and try to solve the issues. One thing
> though: Is it possible to make an exception for the naming of
> ext4-specific struct members?
> Example: Members' names like "bg_block_bitmap_lo" in

This is ok since this is a structure that is based on the EXT4
documentation,

> EXT4_BLOCK_GROUP_DESC. I'd like to make a case for it; from my
> experience with my own hobby project's ext2 driver, having names
> similar to what's used in the documentation/other source code is
> incredibly helpful when trying to work on the code; with the original
> docs' names, which are admittedly not compliant with the EDK2 coding
> style, it really makes everything much clearer when using other code
> or documentation as reference. Of course, if it's not possible I'll
> rename them all.
> 
> Thanks,
> 
> Pedro
> 
> 
> On Thu, 5 Aug 2021 at 19:33, Kinney, Michael D
>  wrote:
> >
> > Hi Pedro,
> >
> > 1) Ext4Pkg/Ext4Dxe/Ext4Dxe.inf:
> >
> >   * To be consistent with other drivers, BASE_NAME should be changed from 
> > Ext4 to Ext4Dxe.
> >   * For proper dependency checking in incremental builds, please add the .h 
> > files to the [Sources] section
> >
> >   Ext4Disk.h
> >   Ext4Dxe.h
> >
> > 2) There are a number of code style issues that need to be addressed.  Can 
> > you fix those for V2?
> >
> > 3) I did a quick pass to find the IA32 NOOPT VS2019 issues.  With the 
> > following changes, I can get it to build.  Do not
> know if I introduced any functional changes by mistake.
> >
> > diff --git a/Features/Ext4Pkg/Ext4Dxe/BlockGroup.c 
> > b/Features/Ext4Pkg/Ext4Dxe/BlockGroup.c
> > index 10a82d40a0..f2db93f02c 100644
> > --- a/Features/Ext4Pkg/Ext4Dxe/BlockGroup.c
> > +++ b/Features/Ext4Pkg/Ext4Dxe/BlockGroup.c
> > @@ -61,7 +61,7 @@ Ext4ReadInode (
> >   Partition,
> >   Inode,
> >   Partition->InodeSize,
> > - Ext4BlockToByteOffset (Partition, InodeTableStart) + 
> > InodeOffset * Partition->InodeSize
> > + Ext4BlockToByteOffset (Partition, InodeTableStart) + 
> > MultU64x32 (InodeOffset, Partition->InodeSize)
> >   );
> >
> >if (EFI_ERROR (Status)) {
> > diff --git a/Features/Ext4Pkg/Ext4Dxe/DiskUtil.c 
> > b/Features/Ext4Pkg/Ext4Dxe/DiskUtil.c
> > index 1cafdd64cd..65109809c0 100644
> > --- a/Features/Ext4Pkg/Ext4Dxe/DiskUtil.c
> > +++ b/Features/Ext4Pkg/Ext4Dxe/DiskUtil.c
> > @@ -45,7 +45,7 @@ Ext4ReadBlocks (
> >IN EXT4_BLOCK_NR BlockNumber
> >)
> >  {
> > -  return Ext4ReadDiskIo (Partition, Buffer, NumberBlocks * 
> > Partition->BlockSize, BlockNumber * Partition->BlockSize);
> > +  return Ext4ReadDiskIo (Partition, Buffer, NumberBlocks * 
> > Partition->BlockSize, MultU64x32 (BlockNumber, Partition-
> >BlockSize));
> >  }
> >
> >  /**
> > diff --git a/Features/Ext4Pkg/Ext4Dxe/Ext4Disk.h 
> > b/Features/Ext4Pkg/Ext4Dxe/Ext4Disk.h
> > index d790e70be1..8aa584df14 100644
> > --- a/Features/Ext4Pkg/Ext4Dxe/Ext4Disk.h
> > +++ b/Features/Ext4Pkg/Ext4Dxe/Ext4Disk.h
> > @@ -445,6 +445,6 @@ typedef struct {
> >  typedef UINT64  EXT4_BLOCK_NR;
> >  typedef UINT32  EXT4_INO_NR;
> >
> > -#define EXT4_INODE_SIZE(ino)  (((UINT64)ino->i_size_hi << 32) | 
> > ino->i_size_lo)
> > +#define EXT4_INODE_SIZE(ino)  (LShiftU64 (ino->i_size_hi, 32) | 
> > ino->i_size_lo)
> >
> >  #endif
> > diff --git a/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.h 
> > b/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.h
> > index f6875c919e..a055a139e1 100644
> > --- a/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.h
> > +++ b/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.h
> > @@ -244,7 +244,7 @@ Ext4MakeBlockNumberFromHalfs (
> >)
> >  {
> >// High might have garbage if it's not a 64 bit filesystem
> > -  return Ext4Is64Bit (Partition) ? Low | ((UINT64)High << 32) : Low;
> > +  return Ext4Is64Bit (Partition) ? (Low | LShiftU64 (High, 32)) : Low;
> >  }
> >
> >  /**
> > @@ -297,7 +297,7 @@ Ext4BlockToByteOffset (
> >IN EXT4_BLOCK_NR Block
> >)
> >  {
> > -  return Partition->BlockSize * Block;
> > +  return MultU64x32 (Block, Partition->BlockSize);
> >  }
> >
> >  /**
> > @@ -333,7 +333,7 @@ Ext4InodeSize (
> >CONST EXT4_INODE *Inode
> >)
> >  {
> > -  return ((UINT64)Inode->i_size_hi << 32) | Inode->i_size_lo;
> > +  return (LShiftU64 (Inode->i_size_hi, 32) | Inode->i_size_lo);
> >  }
> >
> >  /**
> > diff --git a/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.inf 
> > b/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.inf
> > index 102b12d613..fc0185285e 100644
> > --- a/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.inf
> > +++ b/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.inf
> > @@ -111,6 +111,8

Re: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4

2021-08-06 Thread Andrei Warkentin

Ok, I misunderstood the patch set (I thought the PciHostBridgeLib itself would 
eventually move to DEN0115).

I still think that (in general) would be a good idea - if not for the benefit 
of the Pi, then for the next upstreamed platform where you could avoid 
implementing custom config access code...

Reviewed-by: Andrei Warkentin 

--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware

From: Andrei Warkentin 
Sent: Friday, August 6, 2021 7:02 PM
To: devel@edk2.groups.io ; jeremy.lin...@arm.com 

Cc: p...@akeo.ie ; ardb+tianoc...@kernel.org 
; sunny.w...@arm.com ; 
samer.el-haj-mahm...@arm.com ; René Treffer 

Subject: Re: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for 
CM4

Hi Jeremy,

Is any of this still conceptually necessary if we adopt the SMCCC interface 
within UEFI?

Instead of assuming the first downstream bus is bus 1, could you read the 
secondary BN from the RP?

--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware

From: devel@edk2.groups.io  on behalf of Jeremy Linton 
via groups.io 
Sent: Thursday, August 5, 2021 7:35 PM
To: devel@edk2.groups.io 
Cc: p...@akeo.ie ; ardb+tianoc...@kernel.org 
; Andrei Warkentin ; 
sunny.w...@arm.com ; samer.el-haj-mahm...@arm.com 
; Jeremy Linton ; René 
Treffer 
Subject: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4

The CM4 has an actual pcie slot, so we need to move the linkup
check to the configuration probe logic. Further the device
restriction logic needs to be relaxed to support downstream
PCIe switches.

Suggested-by: René Treffer 
Signed-off-by: Jeremy Linton 
---
 .../Bcm2711PciHostBridgeLibConstructor.c   |  5 -
 .../Library/Bcm2711PciSegmentLib/PciSegmentLib.c   | 24 +++---
 2 files changed, 17 insertions(+), 12 deletions(-)

diff --git 
a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
 
b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
index 8587d2d36d..4d4c584726 100644
--- 
a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
+++ 
b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
@@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor (
   } while (((Data & 0x30) != 0x030) && (Timeout));
   DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, 
Timeout));

-  if ((Data & 0x30) != 0x30) {
-DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
-return EFI_DEVICE_ERROR;
-  }
-
   if ((Data & 0x80) != 0x80) {
 DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data));
 return EFI_UNSUPPORTED;
diff --git 
a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c 
b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
index 44ce3b4b99..3ccc131eab 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
@@ -78,6 +78,8 @@ PciSegmentLibGetConfigBase (
   UINT64Base;
   UINT64Offset;
   UINT32Dev;
+  UINT32Bus;
+  UINT32Data;

   Base = PCIE_REG_BASE;
   Offset = Address & 0xFFF; /* Pick off the 4k register offset */
@@ -89,17 +91,25 @@ PciSegmentLibGetConfigBase (
 Base += PCIE_EXT_CFG_DATA;
 if (mPciSegmentLastAccess != Address) {
   Dev = EFI_PCI_ADDR_DEV (Address);
+  Bus = EFI_PCI_ADDR_BUS (Address);
+
   /*
-   * Scan things out directly rather than translating the "bus" to a 
device, etc..
-   * only we need to limit each bus to a single device.
+   * There can only be a single device on bus 1 (downstream of root).
+   * Subsequent busses (behind a PCIe switch) can have more.
*/
-  if (Dev < 1) {
-  MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
-  mPciSegmentLastAccess = Address;
-  } else {
-  mPciSegmentLastAccess = 0;
+  if (Dev > 0 && (Bus < 2)) {
   return 0x;
   }
+
+  /* Don't probe slots if the link is down */
+  Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS);
+  if ((Data & 0x30) != 0x30) {
+  DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
+  return 0x;
+  }
+
+  MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
+  mPciSegmentLastAccess = Address;
 }
   }
   return Base + Offset;
--
2.13.7








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Re: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4

2021-08-06 Thread Andrei Warkentin

Hi Jeremy,

Is any of this still conceptually necessary if we adopt the SMCCC interface 
within UEFI?

Instead of assuming the first downstream bus is bus 1, could you read the 
secondary BN from the RP?

--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware

From: devel@edk2.groups.io  on behalf of Jeremy Linton 
via groups.io 
Sent: Thursday, August 5, 2021 7:35 PM
To: devel@edk2.groups.io 
Cc: p...@akeo.ie ; ardb+tianoc...@kernel.org 
; Andrei Warkentin ; 
sunny.w...@arm.com ; samer.el-haj-mahm...@arm.com 
; Jeremy Linton ; René 
Treffer 
Subject: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4

The CM4 has an actual pcie slot, so we need to move the linkup
check to the configuration probe logic. Further the device
restriction logic needs to be relaxed to support downstream
PCIe switches.

Suggested-by: René Treffer 
Signed-off-by: Jeremy Linton 
---
 .../Bcm2711PciHostBridgeLibConstructor.c   |  5 -
 .../Library/Bcm2711PciSegmentLib/PciSegmentLib.c   | 24 +++---
 2 files changed, 17 insertions(+), 12 deletions(-)

diff --git 
a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
 
b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
index 8587d2d36d..4d4c584726 100644
--- 
a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
+++ 
b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
@@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor (
   } while (((Data & 0x30) != 0x030) && (Timeout));
   DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, 
Timeout));

-  if ((Data & 0x30) != 0x30) {
-DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
-return EFI_DEVICE_ERROR;
-  }
-
   if ((Data & 0x80) != 0x80) {
 DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data));
 return EFI_UNSUPPORTED;
diff --git 
a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c 
b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
index 44ce3b4b99..3ccc131eab 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
@@ -78,6 +78,8 @@ PciSegmentLibGetConfigBase (
   UINT64Base;
   UINT64Offset;
   UINT32Dev;
+  UINT32Bus;
+  UINT32Data;

   Base = PCIE_REG_BASE;
   Offset = Address & 0xFFF; /* Pick off the 4k register offset */
@@ -89,17 +91,25 @@ PciSegmentLibGetConfigBase (
 Base += PCIE_EXT_CFG_DATA;
 if (mPciSegmentLastAccess != Address) {
   Dev = EFI_PCI_ADDR_DEV (Address);
+  Bus = EFI_PCI_ADDR_BUS (Address);
+
   /*
-   * Scan things out directly rather than translating the "bus" to a 
device, etc..
-   * only we need to limit each bus to a single device.
+   * There can only be a single device on bus 1 (downstream of root).
+   * Subsequent busses (behind a PCIe switch) can have more.
*/
-  if (Dev < 1) {
-  MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
-  mPciSegmentLastAccess = Address;
-  } else {
-  mPciSegmentLastAccess = 0;
+  if (Dev > 0 && (Bus < 2)) {
   return 0x;
   }
+
+  /* Don't probe slots if the link is down */
+  Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS);
+  if ((Data & 0x30) != 0x30) {
+  DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
+  return 0x;
+  }
+
+  MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
+  mPciSegmentLastAccess = Address;
 }
   }
   return Base + Offset;
--
2.13.7








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Re: [edk2-devel] [PATCH 2/5] Platform/RaspberryPi: break XHCI into its own SSDT

2021-08-06 Thread Andrei Warkentin

Reviewed-by: Andrei Warkentin 

--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware

From: devel@edk2.groups.io  on behalf of Jeremy Linton 
via groups.io 
Sent: Thursday, August 5, 2021 7:35 PM
To: devel@edk2.groups.io 
Cc: p...@akeo.ie ; ardb+tianoc...@kernel.org 
; Andrei Warkentin ; 
sunny.w...@arm.com ; samer.el-haj-mahm...@arm.com 
; Jeremy Linton 
Subject: [edk2-devel] [PATCH 2/5] Platform/RaspberryPi: break XHCI into its own 
SSDT

Lets prepare to switch between XHCI and PCI by moving
the XHCI definition into its own SSDT. That way we can
select it based on the menu settings.

Signed-off-by: Jeremy Linton 
---
 Platform/RaspberryPi/AcpiTables/AcpiTables.inf |  1 +
 Platform/RaspberryPi/AcpiTables/Dsdt.asl   |  3 --
 Platform/RaspberryPi/AcpiTables/Xhci.asl   | 35 ++
 Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c |  8 +
 4 files changed, 31 insertions(+), 16 deletions(-)

diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf 
b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
index 1ddc9ca5fe..f3e8d950c1 100644
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
@@ -38,6 +38,7 @@
   SpcrPl011.aslc
   Pptt.aslc
   SsdtThermal.asl
+  Xhci.asl

 [Packages]
   ArmPkg/ArmPkg.dec
diff --git a/Platform/RaspberryPi/AcpiTables/Dsdt.asl 
b/Platform/RaspberryPi/AcpiTables/Dsdt.asl
index 1ee6379f46..b594d50bdf 100644
--- a/Platform/RaspberryPi/AcpiTables/Dsdt.asl
+++ b/Platform/RaspberryPi/AcpiTables/Dsdt.asl
@@ -64,9 +64,6 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
   Scope (\_SB_)
   {
 include ("Pep.asl")
-#if (RPI_MODEL == 4)
-include ("Xhci.asl")
-#endif

 Device (CPU0)
 {
diff --git a/Platform/RaspberryPi/AcpiTables/Xhci.asl 
b/Platform/RaspberryPi/AcpiTables/Xhci.asl
index bc3fea60f9..9b37277956 100644
--- a/Platform/RaspberryPi/AcpiTables/Xhci.asl
+++ b/Platform/RaspberryPi/AcpiTables/Xhci.asl
@@ -9,6 +9,8 @@

 #include 

+#include "AcpiTables.h"
+
 /*
  * The following can be used to remove parenthesis from
  * defined macros that the compiler complains about.
@@ -24,12 +26,17 @@
  */
 #define XHCI_REG_LENGTH 0x1000

-Device (SCB0) {
-Name (_HID, "ACPI0004")
-Name (_UID, 0x0)
-Name (_CCA, 0x0)
+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4XHCI", 2)
+{
+  Scope (\_SB_)
+  {
+
+Device (SCB0) {
+  Name (_HID, "ACPI0004")
+  Name (_UID, 0x0)
+  Name (_CCA, 0x0)

-Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings
+  Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings
 /*
  * Container devices with _DMA must have _CRS, meaning SCB0
  * to provide all resources that XHC0 consumes (except
@@ -57,15 +64,15 @@ Device (SCB0) {
 Add (MMBE, XHCI_REG_LENGTH - 1, MMBE)
 Add (MMLE, XHCI_REG_LENGTH - 1, MMLE)
 Return (RBUF)
-}
+  }

-Name (_DMA, ResourceTemplate() {
+  Name (_DMA, ResourceTemplate() {
 /*
  * XHC0 is limited to DMA to first 3GB. Note this
  * only applies to PCIe, not GENET or other devices
  * next to the A72.
  */
-QWordMemory (ResourceConsumer,
+QWordMemory (ResourceProducer,
 ,
 MinFixed,
 MaxFixed,
@@ -79,10 +86,10 @@ Device (SCB0) {
 ,
 ,
 )
-})
+  })

-Device (XHC0)
-{
+  Device (XHC0)
+  {
 Name (_HID, "PNP0D10")  // _HID: Hardware ID
 Name (_UID, 0x0)// _UID: Unique ID
 Name (_CCA, 0x0)// _CCA: Cache Coherency Attribute
@@ -131,5 +138,7 @@ Device (SCB0) {
 Debug = "xHCI enable"
 Store (0x6, CMND)
 }
-}
-}
+  } // end XHC0
+} //end SCB0
+  } //end scope sb
+} //end definition block
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c 
b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 87f6b4e7bb..7c5786303d 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -814,6 +814,14 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] = {
 PcdToken(PcdSdIsArasan),
 SsdtEmmcNameOpReplace
   },
+#if (RPI_MODEL == 4)
+  {
+SIGNATURE_64 ('R', 'P', 'I', '4', 'X', 'H', 'C', 'I'),
+0,
+PcdToken(PcdXhciPci),
+NULL
+  },
+#endif
   { // DSDT
 SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),
 0,
--
2.13.7



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Re: [edk2-devel] [PATCH 1/1] Platform/RaspberryPi: Add linux quirk support

2021-08-06 Thread Andrei Warkentin

Hi Jeremy,

Reviewed-by: Andrei Warkentin 

MADT -> MCFG

Root port registers would be NonCacheable just like the outbound mapping. 
(Also, with https://mantis.uefi.org/mantis/view.php?id=2220, _MEM attributes 
aside from  NonCacheable and Prefetchable are effectively deprecated).

Note: I really wish we had sorted out the HID/CID story for the PCIe RC... i.e. 
at least to make the HID custom for non-ECAM implementations and push 
PNP0A08/PNP0A03 in the CID... this would make linux,pcie-quirk unnecessary, 
using standard ACPI driver binding mechanisms to separate quirks from proper 
ECAM. Sadly, I think the train to do that has long left the station (with so 
many ACPI Arm systems out there and non-ECAM or not-quite-ECAM RCs using 
PNP0A08/PNP0A03 alone. ESXi, for example, ends up keying on the Table Ids 
(which is arguably even worse than the DT props)

Note 2: Given that DT has users in U-Boot and the BSDs (and potentially 
anywhere else), there's a long term hope to make DT bindings separate from 
Linux. To that end "linux,pcie-quirk" and "linux,pcie-nomsi" should probably be 
named something else (although I recognise that you're probably just wiring up 
something that already exists).

--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware

From: Jeremy Linton 
Sent: Thursday, August 5, 2021 7:40 PM
To: devel@edk2.groups.io 
Cc: p...@akeo.ie ; ardb+tianoc...@kernel.org 
; Andrei Warkentin ; 
sunny.w...@arm.com ; samer.el-haj-mahm...@arm.com 
; Jeremy Linton 
Subject: [PATCH 1/1] Platform/RaspberryPi: Add linux quirk support

Linux, for the time being has refused to support the Arm
standard SMCCC for PCIe configuration. Instead they
want to continue to maintain per device "quirks".

As the RPI isn't really ECAM this is a bit more
involved because the MADT can't really describe
the root port+config registers situation. Further
platforms which support the SMCCC shouldn't have
a MADT, so we need an additional way to tell linux
what it needs to know about this platform.

Signed-off-by: Jeremy Linton 
---
 Platform/RaspberryPi/AcpiTables/Pci.asl | 21 +
 1 file changed, 21 insertions(+)

diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl 
b/Platform/RaspberryPi/AcpiTables/Pci.asl
index 34474f13ef..3e7fd0d5b7 100644
--- a/Platform/RaspberryPi/AcpiTables/Pci.asl
+++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
@@ -123,6 +123,15 @@ DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", 
"RPI4PCIE", 2)
 Name(_BBN, Zero) // PCI Base Bus Number
 Name(_CCA, 0)// Mark the PCI noncoherent

+Name (_DSD, Package () {
+  ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+Package () {
+  Package () { "linux,pcie-quirk", "bcm2711" },
+  Package () { "linux,pcie-nomsi", 1 },
+}
+})
+
+
 // Root Complex 0
 Device (RP0) {
  Name(_ADR, 0xF000)// Dev 0, Func 0
@@ -176,6 +185,18 @@ DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", 
"RPI4PCIE", 2)
   2   // SANITIZED_PCIE_MMIO_LEN + 1
   ,,,MMI1,,TypeTranslation
 )
+
+QWordMemory ( // Root port registers, not to be used if SMCCC is 
utilized
+  ResourceConsumer, ,
+  MinFixed, MaxFixed,
+  NonCacheable, ReadWrite,// cacheable? is that right?
+  0x, // Granularity
+  0xFD50, // Root port begin
+  0xFD509FFF, // Root port end
+  0x, // no translation
+  0xA000, // size
+  ,,
+)
   }) // end Name(RBUF)

   // Work around ASL's inability to add in a resource definition
--
2.13.7



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Re: [edk2-devel] [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT

2021-08-06 Thread Andrei Warkentin

Hi Jeremy,

MADT -> MCFG (and in other patches as well, where you refer to MADT)

The other feedback that Ard provided makes sense to me as well.

A

--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware

From: devel@edk2.groups.io  on behalf of Jeremy Linton 
via groups.io 
Sent: Thursday, August 5, 2021 7:35 PM
To: devel@edk2.groups.io 
Cc: p...@akeo.ie ; ardb+tianoc...@kernel.org 
; Andrei Warkentin ; 
sunny.w...@arm.com ; samer.el-haj-mahm...@arm.com 
; Jeremy Linton 
Subject: [edk2-devel] [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT

Since we plan on toggling between XHCI and PCI the PCI
root needs to be in its own SSDT. This is all thats needed
of UEFI. The SMC conduit is provided directly to the running
OS. When the OS detects this PCIe port, on a machine without
a MADT it attempts to connect to the SMC conduit. The RPi
definition doesn't have any power mgmt, and only provides
a description of the root port.

Signed-off-by: Jeremy Linton 
---
 Platform/RaspberryPi/AcpiTables/AcpiTables.inf |   3 +
 Platform/RaspberryPi/AcpiTables/Pci.asl| 237 +
 Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c |   6 +
 3 files changed, 246 insertions(+)
 create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl

diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf 
b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
index f3e8d950c1..da2a6db85f 100644
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
@@ -39,6 +39,7 @@
   Pptt.aslc
   SsdtThermal.asl
   Xhci.asl
+  Pci.asl

 [Packages]
   ArmPkg/ArmPkg.dec
@@ -59,6 +60,8 @@
   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
   gArmTokenSpaceGuid.PcdGicDistributorBase
   gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr
+  gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr
+  gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen
   gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase
   gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress
   gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress
diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl 
b/Platform/RaspberryPi/AcpiTables/Pci.asl
new file mode 100644
index 00..34474f13ef
--- /dev/null
+++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
@@ -0,0 +1,237 @@
+/** @file
+ *
+ *  Copyright (c) 2019 Linaro, Limited. All rights reserved.
+ *  Copyright (c) 2021 Arm
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include 
+
+#include "AcpiTables.h"
+
+/*
+ * The following can be used to remove parenthesis from
+ * defined macros that the compiler complains about.
+ */
+#define ISOLATE_ARGS(...)   __VA_ARGS__
+#define REMOVE_PARENTHESES(x)   ISOLATE_ARGS x
+
+#define SANITIZED_PCIE_CPU_MMIO_WINDOW  
REMOVE_PARENTHESES(PCIE_CPU_MMIO_WINDOW)
+#define SANITIZED_PCIE_MMIO_LEN 
REMOVE_PARENTHESES(PCIE_BRIDGE_MMIO_LEN)
+#define SANITIZED_PCIE_PCI_MMIO_BEGIN   REMOVE_PARENTHESES(PCIE_TOP_OF_MEM_WIN)
+
+/*
+ * According to UEFI boot log for the VLI device on Pi 4.
+ */
+#define RT_REG_LENGTH 0x1000
+
+// copy paste job from juno
+#define LNK_DEVICE(Unique_Id, Link_Name, irq) \
+  Device(Link_Name) { \
+  Name(_HID, EISAID("PNP0C0F"))   \
+  Name(_UID, Unique_Id)   \
+  Name(_PRS, ResourceTemplate() { \
+  Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq }   \
+  })  \
+  Method (_CRS, 0) { Return (_PRS) }  \
+  Method (_SRS, 1) { }\
+  Method (_DIS) { }   \
+  }
+
+#define PRT_ENTRY(Address, Pin, Link)  
  \
+Package (4) {  
  \
+Address,/* uses the same format as _ADR */ 
  \
+Pin,/* The PCI pin number of the device (0-INTA, 1-INTB, 
2-INTC, 3-INTD). */ \
+Link,   /* Interrupt allocated via Link device. */ 
  \
+Zero/* global system interrupt number (no used) */ 
  \
+  }
+#define ROOT_PRT_ENTRY(Pin, Link)   PRT_ENTRY(0x, Pin, Link)
+
+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)
+{
+  Scope (\_SB_)
+  {
+
+Device (SCB0) {
+  Name (_HID, "ACPI0004")
+  Name (_UID, 0x0)
+  Name (_CCA, 0x0)
+
+  Method (_CRS, 0, Serialized) {
+// Container devices with _DMA must have _CRS,
+// meaning SCB0 to provide all re

[edk2-devel] [PATCH v3] UefiCpuPkg/CpuCacheInfoLib: Sort CpuCacheInfo array

2021-08-06 Thread Jason Lou

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3508

Sort the CpuCacheInfo array by CPU package ID, core type, cache level
and cache type.

Signed-off-by: Jason Lou 
Cc: Ray Ni 
Cc: Eric Dong 
Cc: Laszlo Ersek 
Cc: Rahul Kumar 
---
 UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c | 47 
+++-
 UefiCpuPkg/Include/Library/CpuCacheInfoLib.h |  2 +-
 UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf|  4 +-
 UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h | 27 +++
 UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf|  4 +-
 5 files changed, 80 insertions(+), 4 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c 
b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
index 126ee0da86..ae81ea9ce2 100644
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
@@ -37,6 +37,47 @@ CpuCacheInfoPrintCpuCacheInfoTable (
   DEBUG ((DEBUG_INFO, 
"+---+--+\n"));
 }
 
+/**
+  Function to compare CPU package ID, core type, cache level and cache type 
for use in QuickSort.
+
+  @param[in]  Buffer1 pointer to CPU_CACHE_INFO poiner to compare
+  @param[in]  Buffer2 pointer to second CPU_CACHE_INFO pointer to 
compare
+
+  @retval  0  Buffer1 equal to Buffer2
+  @retval  1  Buffer1 is greater than Buffer2
+  @retval  -1 Buffer1 is less than Buffer2
+**/
+INTN
+EFIAPI
+CpuCacheInfoCompare (
+  IN CONST VOID *Buffer1,
+  IN CONST VOID *Buffer2
+  )
+{
+  CPU_CACHE_INFO_COMPARATOR Comparator1, Comparator2;
+
+  ZeroMem (&Comparator1, sizeof (Comparator1));
+  ZeroMem (&Comparator2, sizeof (Comparator2));
+
+  Comparator1.Bits.Package= ((CPU_CACHE_INFO*)Buffer1)->Package;
+  Comparator1.Bits.CoreType   = ((CPU_CACHE_INFO*)Buffer1)->CoreType;
+  Comparator1.Bits.CacheLevel = ((CPU_CACHE_INFO*)Buffer1)->CacheLevel;
+  Comparator1.Bits.CacheType  = ((CPU_CACHE_INFO*)Buffer1)->CacheType;
+
+  Comparator2.Bits.Package= ((CPU_CACHE_INFO*)Buffer2)->Package;
+  Comparator2.Bits.CoreType   = ((CPU_CACHE_INFO*)Buffer2)->CoreType;
+  Comparator2.Bits.CacheLevel = ((CPU_CACHE_INFO*)Buffer2)->CacheLevel;
+  Comparator2.Bits.CacheType  = ((CPU_CACHE_INFO*)Buffer2)->CacheType;
+
+  if (Comparator1.Uint64 == Comparator2.Uint64) {
+return 0;
+  } else if (Comparator1.Uint64 > Comparator2.Uint64) {
+return 1;
+  } else {
+return -1;
+  }
+}
+
 /**
   Get the total number of package and package ID in the platform.
 
@@ -325,6 +366,10 @@ CpuCacheInfoCollectCpuCacheInfoData (
   if (*CacheInfoCount < LocalCacheInfoCount) {
 Status = EFI_BUFFER_TOO_SMALL;
   } else {
+//
+// Sort LocalCacheInfo array by CPU package ID, core type, cache level and 
cache type.
+//
+PerformQuickSort (LocalCacheInfo, LocalCacheInfoCount, sizeof 
(*LocalCacheInfo), (SORT_COMPARE) CpuCacheInfoCompare);
 CopyMem (CacheInfo, LocalCacheInfo, sizeof (*CacheInfo) * 
LocalCacheInfoCount);
 DEBUG_CODE (
   CpuCacheInfoPrintCpuCacheInfoTable (CacheInfo, LocalCacheInfoCount);
@@ -340,7 +385,7 @@ CpuCacheInfoCollectCpuCacheInfoData (
 }
 
 /**
-  Get CpuCacheInfo data array.
+  Get CpuCacheInfo data array. The array is sorted by CPU package ID, core 
type, cache level and cache type.
 
   @param[in, out] CpuCacheInfoPointer to the CpuCacheInfo array.
   @param[in, out] CpuCacheInfoCount   As input, point to the length of 
response CpuCacheInfo array.
diff --git a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h 
b/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
index a66152bce0..3422997f54 100644
--- a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
+++ b/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
@@ -59,7 +59,7 @@ typedef struct {
 } CPU_CACHE_INFO;
 
 /**
-  Get CpuCacheInfo data array.
+  Get CpuCacheInfo data array. The array is sorted by CPU package ID, core 
type, cache level and cache type.
 
   @param[in, out] CpuCacheInfoPointer to the CpuCacheInfo array.
   @param[in, out] CpuCacheInfoCount   As input, point to the length of 
response CpuCacheInfo array.
diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf 
b/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf
index c481080e49..c3d3f1e799 100644
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf
@@ -3,7 +3,7 @@
 #
 #  Provides cache info for each package, core type, cache level and cache type.
 #
-#  Copyright (c) 2020, Intel Corporation. All rights reserved.
+#  Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -25,6 +25,7 @@
 
 [Packages]
   MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
   UefiCpuPkg/UefiCpuPkg.dec

Re: [edk2-devel] [PATCH v2] UefiCpuPkg/CpuCacheInfoLib: Sort CpuCacheInfo array

2021-08-06 Thread Jason Lou

Sure, I will rename "Fields" and "Data64" in v3 patch.


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Re: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4

2021-08-06 Thread Jeremy Linton


Hi,

On 8/6/21 8:42 AM, Ard Biesheuvel wrote:

On Thu, 5 Aug 2021 at 18:36, Jeremy Linton  wrote:


The CM4 has an actual pcie slot, so we need to move the linkup
check to the configuration probe logic. Further the device
restriction logic needs to be relaxed to support downstream
PCIe switches.

Suggested-by: René Treffer 
Signed-off-by: Jeremy Linton 


Please split this into two patches.


Your talking about the linkup move, vs expanding the dev<0 check?

Ok.





---
  .../Bcm2711PciHostBridgeLibConstructor.c   |  5 -
  .../Library/Bcm2711PciSegmentLib/PciSegmentLib.c   | 24 +++---
  2 files changed, 17 insertions(+), 12 deletions(-)

diff --git 
a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
 
b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
index 8587d2d36d..4d4c584726 100644
--- 
a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
+++ 
b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
@@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor (
} while (((Data & 0x30) != 0x030) && (Timeout));
DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, 
Timeout));

-  if ((Data & 0x30) != 0x30) {
-DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
-return EFI_DEVICE_ERROR;
-  }
-
if ((Data & 0x80) != 0x80) {
  DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data));
  return EFI_UNSUPPORTED;
diff --git 
a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c 
b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
index 44ce3b4b99..3ccc131eab 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
@@ -78,6 +78,8 @@ PciSegmentLibGetConfigBase (
UINT64Base;
UINT64Offset;
UINT32Dev;
+  UINT32Bus;
+  UINT32Data;

Base = PCIE_REG_BASE;
Offset = Address & 0xFFF; /* Pick off the 4k register offset */
@@ -89,17 +91,25 @@ PciSegmentLibGetConfigBase (
  Base += PCIE_EXT_CFG_DATA;
  if (mPciSegmentLastAccess != Address) {
Dev = EFI_PCI_ADDR_DEV (Address);
+  Bus = EFI_PCI_ADDR_BUS (Address);
+
/*
-   * Scan things out directly rather than translating the "bus" to a 
device, etc..
-   * only we need to limit each bus to a single device.
+   * There can only be a single device on bus 1 (downstream of root).
+   * Subsequent busses (behind a PCIe switch) can have more.
 */
-  if (Dev < 1) {
-  MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
-  mPciSegmentLastAccess = Address;
-  } else {
-  mPciSegmentLastAccess = 0;
+  if (Dev > 0 && (Bus < 2)) {
return 0x;
}
+
+  /* Don't probe slots if the link is down */
+  Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS);
+  if ((Data & 0x30) != 0x30) {
+  DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
+  return 0x;
+  }
+
+  MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
+  mPciSegmentLastAccess = Address;
  }
}
return Base + Offset;
--
2.13.7





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Re: [edk2-devel] [PATCH v2] UefiCpuPkg/CpuCacheInfoLib: Sort CpuCacheInfo array

2021-08-06 Thread Ni, Ray

With the renaming, Reviewed-by: Ray Ni 

> -Original Message-
> From: Ni, Ray
> Sent: Friday, August 6, 2021 9:55 PM
> To: Lou, Yun ; devel@edk2.groups.io
> Cc: Dong, Eric ; Laszlo Ersek ; 
> Kumar, Rahul1 
> Subject: RE: [PATCH v2] UefiCpuPkg/CpuCacheInfoLib: Sort CpuCacheInfo array
> 
> The patch looks good to me. 2 minor comments:
> > +  } Fields;
> 1. Can you rename to "Bits" to align to existing naming convention?
> 
> >
> > +  UINT64Data64;
> 
> 2. Can you rename to "Uint64"?
> 



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Re: [edk2-devel] [PATCH 4/4] UefiPayloadPkg: Add a macro to enable or diable the serial driver.

2021-08-06 Thread Ni, Ray

Reviewed-by: Ray Ni 

> -Original Message-
> From: Liu, Zhiguang 
> Sent: Friday, August 6, 2021 12:31 PM
> To: devel@edk2.groups.io
> Cc: Dong, Guo ; Ni, Ray ; Ma, Maurice 
> ; You, Benjamin
> 
> Subject: [PATCH 4/4] UefiPayloadPkg: Add a macro to enable or diable the 
> serial driver.
> 
> This patch doesn't change the default behavior.
> 
> Cc: Guo Dong 
> Cc: Ray Ni 
> Cc: Maurice Ma 
> Cc: Benjamin You 
> 
> Signed-off-by: Zhiguang Liu 
> ---
>  UefiPayloadPkg/UefiPayloadPkg.dsc | 4 
>  UefiPayloadPkg/UefiPayloadPkg.fdf | 2 ++
>  2 files changed, 6 insertions(+)
> 
> diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc 
> b/UefiPayloadPkg/UefiPayloadPkg.dsc
> index 002d2a8fa7..b4a30be381 100644
> --- a/UefiPayloadPkg/UefiPayloadPkg.dsc
> +++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
> @@ -98,6 +98,8 @@
>DEFINE RTC_INDEX_REGISTER = 0x70
> 
>DEFINE RTC_TARGET_REGISTER = 0x71
> 
> 
> 
> +  DEFINE SERIAL_DRIVER_ENABLE = TRUE
> 
> +
> 
>  [BuildOptions]
> 
>*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
> 
>GCC:*_UNIXGCC_*_CC_FLAGS   = -DMDEPKG_NDEBUG
> 
> @@ -536,7 +538,9 @@
>#
> 
># ISA Support
> 
>#
> 
> +!if $(SERIAL_DRIVER_ENABLE) == TRUE
> 
>MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> 
> +!endif
> 
>  !if $(PS2_KEYBOARD_ENABLE) == TRUE
> 
>OvmfPkg/SioBusDxe/SioBusDxe.inf
> 
>MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf
> 
> diff --git a/UefiPayloadPkg/UefiPayloadPkg.fdf 
> b/UefiPayloadPkg/UefiPayloadPkg.fdf
> index 041fed842c..b2cfb6b405 100644
> --- a/UefiPayloadPkg/UefiPayloadPkg.fdf
> +++ b/UefiPayloadPkg/UefiPayloadPkg.fdf
> @@ -136,7 +136,9 @@ INF 
> MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
>  #
> 
>  # ISA Support
> 
>  #
> 
> +!if $(SERIAL_DRIVER_ENABLE) == TRUE
> 
>  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> 
> +!endif
> 
>  !if $(PS2_KEYBOARD_ENABLE) == TRUE
> 
>  INF OvmfPkg/SioBusDxe/SioBusDxe.inf
> 
>  INF MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf
> 
> --
> 2.32.0.windows.2



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Re: [edk2-devel] [PATCH 1/4] UefiPayloadPkg: Add Fixed PCDs and use Macro to define the default value.

2021-08-06 Thread Ni, Ray

Reviewed-by: Ray Ni 

> -Original Message-
> From: Liu, Zhiguang 
> Sent: Friday, August 6, 2021 12:31 PM
> To: devel@edk2.groups.io
> Cc: Dong, Guo ; Ni, Ray ; Ma, Maurice 
> ; You, Benjamin
> 
> Subject: [PATCH 1/4] UefiPayloadPkg: Add Fixed PCDs and use Macro to define 
> the default value.
> 
> Add the three PCDs as fixed at build PCD:
>   gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule
>   gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister
>   gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister
> The default value is defined as Macro, so it can be passed in at build
> command.
> 
> Cc: Guo Dong 
> Cc: Ray Ni 
> Cc: Maurice Ma 
> Cc: Benjamin You 
> 
> Signed-off-by: Zhiguang Liu 
> ---
>  UefiPayloadPkg/UefiPayloadPkg.dsc | 11 ++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc 
> b/UefiPayloadPkg/UefiPayloadPkg.dsc
> index bcedf1c746..ba54f2057f 100644
> --- a/UefiPayloadPkg/UefiPayloadPkg.dsc
> +++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
> @@ -91,6 +91,13 @@
>DEFINE EMU_VARIABLE_ENABLE   = TRUE
> 
>DEFINE DISABLE_RESET_SYSTEM  = FALSE
> 
> 
> 
> +  # Dfine the maximum size of the capsule image without a reset flag that 
> the platform can support.
> 
> +  DEFINE MAX_SIZE_NON_POPULATE_CAPSULE = 0xa0
> 
> +
> 
> +  # Define RTC related register.
> 
> +  DEFINE RTC_INDEX_REGISTER = 0x70
> 
> +  DEFINE RTC_TARGET_REGISTER = 0x71
> 
> +
> 
>  [BuildOptions]
> 
>*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
> 
>GCC:*_UNIXGCC_*_CC_FLAGS   = -DMDEPKG_NDEBUG
> 
> @@ -324,7 +331,9 @@
>  !else
> 
>gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
> 
>  !endif
> 
> -
> 
> +  
> gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|$(MAX_SIZE_NON_POPULATE_CAPSULE)
> 
> +  gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|$(RTC_INDEX_REGISTER)
> 
> +  gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister|$(RTC_TARGET_REGISTER)
> 
>#
> 
># The following parameters are set by Library/PlatformHookLib
> 
>#
> 
> --
> 2.32.0.windows.2



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Re: [edk2-devel] [PATCH 3/4] UefiPayloadPkg: change the default value of some PCDs.

2021-08-06 Thread Ni, Ray

Reviewed-by: Ray Ni 

> -Original Message-
> From: Liu, Zhiguang 
> Sent: Friday, August 6, 2021 12:31 PM
> To: devel@edk2.groups.io
> Cc: Dong, Guo ; Ni, Ray ; Ma, Maurice 
> ; You, Benjamin
> 
> Subject: [PATCH 3/4] UefiPayloadPkg: change the default value of some PCDs.
> 
> Change the default value of the below PCDs to diable some legacy feature.
>   gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE
>   gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceForOptionRom|FALSE
>   gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0
> 
> Cc: Guo Dong 
> Cc: Ray Ni 
> Cc: Maurice Ma 
> Cc: Benjamin You 
> 
> Signed-off-by: Zhiguang Liu 
> ---
>  UefiPayloadPkg/UefiPayloadPkg.dsc | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc 
> b/UefiPayloadPkg/UefiPayloadPkg.dsc
> index d293211e46..002d2a8fa7 100644
> --- a/UefiPayloadPkg/UefiPayloadPkg.dsc
> +++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
> @@ -297,6 +297,8 @@
>gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
> 
>## This PCD specified whether ACPI SDT protocol is installed.
> 
>gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
> 
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE
> 
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceForOptionRom|FALSE
> 
> 
> 
>  [PcdsFixedAtBuild]
> 
>gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x1
> 
> @@ -350,7 +352,7 @@
>
> gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|$(PCI_SERIAL_PARAMETERS)
> 
> 
> 
>
> gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|$(MAX_LOGICAL_PROCESSORS)
> 
> -
> 
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0
> 
> 
> 
>  
> 
> 
>  #
> 
> --
> 2.32.0.windows.2



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Re: [edk2-devel] [PATCH 2/4] UefiPayloadPkg: define some PCD as DynamicEX PCD

2021-08-06 Thread Ni, Ray

Reviewed-by: Ray Ni 

> -Original Message-
> From: Liu, Zhiguang 
> Sent: Friday, August 6, 2021 12:31 PM
> To: devel@edk2.groups.io
> Cc: Dong, Guo ; Ni, Ray ; Ma, Maurice 
> ; You, Benjamin
> 
> Subject: [PATCH 2/4] UefiPayloadPkg: define some PCD as DynamicEX PCD
> 
> Define some PCDs as DynamicEX PCD to be used as global variable.
> Because PcdUartDefaultBaudRate is defined as DynamicEX, remove the code
> to set it in platformlib. That code was actually redundant.
> 
> Cc: Guo Dong 
> Cc: Ray Ni 
> Cc: Maurice Ma 
> Cc: Benjamin You 
> 
> Signed-off-by: Zhiguang Liu 
> ---
>  UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c   | 
>  5 -
>  UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf | 
>  1 -
>  UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.c   | 
>  4 
>  UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.inf | 
>  1 -
>  UefiPayloadPkg/UefiPayloadPkg.dsc  | 
> 28 ++--
>  5 files changed, 18 insertions(+), 21 deletions(-)
> 
> diff --git a/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
> b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
> index 72a17dc8a7..d8453e5957 100644
> --- a/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
> +++ b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
> @@ -75,11 +75,6 @@ PlatformHookSerialPortInitialize (
>  return Status;
> 
>}
> 
> 
> 
> -  Status = PcdSet64S (PcdUartDefaultBaudRate, SerialPortInfo.Baud);
> 
> -  if (RETURN_ERROR (Status)) {
> 
> -return Status;
> 
> -  }
> 
> -
> 
>Status = PcdSet32S (PcdSerialClockRate, SerialPortInfo.InputHertz);
> 
>if (RETURN_ERROR (Status)) {
> 
>  return Status;
> 
> diff --git a/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
> b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
> index 2415d99c64..3eeb94d8fa 100644
> --- a/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
> +++ b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
> @@ -35,5 +35,4 @@
>gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate## PRODUCES
> 
>gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride  ## PRODUCES
> 
>gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate   ## PRODUCES
> 
> -  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate ## PRODUCES
> 
>gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters   ## PRODUCES
> 
> diff --git 
> a/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.c
> b/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.c
> index 6705f29505..bd433bdbe0 100644
> --- a/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.c
> +++ b/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.c
> @@ -70,10 +70,6 @@ PlatformHookSerialPortInitialize (
>  if (RETURN_ERROR (Status)) {
> 
>return Status;
> 
>  }
> 
> -Status = PcdSet64S (PcdUartDefaultBaudRate, SerialPortInfo->BaudRate);
> 
> -if (RETURN_ERROR (Status)) {
> 
> -  return Status;
> 
> -}
> 
> 
> 
>  return RETURN_SUCCESS;
> 
>}
> 
> diff --git 
> a/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.inf
> b/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.inf
> index 41e05ddf54..2dfd8b1216 100644
> --- 
> a/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.inf
> +++ 
> b/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.inf
> @@ -38,4 +38,3 @@
>gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase## PRODUCES
> 
>gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate## PRODUCES
> 
>gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride  ## PRODUCES
> 
> -  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate ## PRODUCES
> 
> diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc 
> b/UefiPayloadPkg/UefiPayloadPkg.dsc
> index ba54f2057f..d293211e46 100644
> --- a/UefiPayloadPkg/UefiPayloadPkg.dsc
> +++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
> @@ -308,11 +308,6 @@
>gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
> 
> 
> 
>gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
> 
> -!if $(TARGET) == DEBUG
> 
> -  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
> 
> -!else
> 
> -  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
> 
> -!endif
> 
>gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
> 
>gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE
> 
> 
> 
> @@ -352,11 +347,6 @@
>gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|$(SERIAL_FIFO_CONTROL)
> 
>
> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|$(SERIAL_EXTENDED_TX_FIFO_SIZE)
> 
> 
> 
> -  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(UART_DEFAULT_BAUD_RATE)
> 
> -  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|$(UART_DEFAULT_DA

Re: [edk2-devel] [PATCH v2] UefiCpuPkg/CpuCacheInfoLib: Sort CpuCacheInfo array

2021-08-06 Thread Ni, Ray

The patch looks good to me. 2 minor comments:
> +  } Fields;
1. Can you rename to "Bits" to align to existing naming convention?

> 
> +  UINT64Data64;

2. Can you rename to "Uint64"?




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Re: [edk2-devel] [PATCH] ArmPkg: Enable boot discovery policy for ARM package.

2021-08-06 Thread Ard Biesheuvel

On Fri, 6 Aug 2021 at 10:30, Grzegorz Bernacki  wrote:
>
> This commit adds code which check BootDiscoveryPolicy variable and
> calls Boot Policy Manager Protocol to connect device specified by
> the variable. To enable that mechanism for platform
> EfiMdeModulePkgTokenSpaceGuid.PcdBootDiscoveryPolicy PCD must be
> added to DSC file and BootDiscoveryPolicyUiLib should be added to
> UiApp libraries.
>

... or the platform will be broken once we apply this patch, right? If
so, please propose patches for all platforms in edk2-platforms that
use this library - we can't just break them.

> Signed-off-by: Grzegorz Bernacki 
> ---
>  ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf |  5 +
>  ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c   | 96 
> +++-
>  2 files changed, 100 insertions(+), 1 deletion(-)
>
> diff --git a/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf 
> b/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
> index 353d7a967b..86751b45f8 100644
> --- a/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
> +++ b/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
> @@ -65,11 +65,15 @@
>
>  [Pcd]
>gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdBootDiscoveryPolicy
>
>  [Guids]
> +  gBootDiscoveryPolicyMgrFormsetGuid
>gEdkiiNonDiscoverableEhciDeviceGuid
>gEdkiiNonDiscoverableUhciDeviceGuid
>gEdkiiNonDiscoverableXhciDeviceGuid
> +  gEfiBootManagerPolicyNetworkGuid
> +  gEfiBootManagerPolicyConnectAllGuid
>gEfiFileInfoGuid
>gEfiFileSystemInfoGuid
>gEfiFileSystemVolumeLabelInfoIdGuid
> @@ -79,6 +83,7 @@
>
>  [Protocols]
>gEdkiiNonDiscoverableDeviceProtocolGuid
> +  gEfiBootManagerPolicyProtocolGuid
>gEfiDevicePathProtocolGuid
>gEfiGraphicsOutputProtocolGuid
>gEfiLoadedImageProtocolGuid
> diff --git a/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c 
> b/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c
> index 5ceb23d822..4332c45bb7 100644
> --- a/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c
> +++ b/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c
> @@ -2,9 +2,10 @@
>Implementation for PlatformBootManagerLib library class interfaces.
>
>Copyright (C) 2015-2016, Red Hat, Inc.
> -  Copyright (c) 2014 - 2019, ARM Ltd. All rights reserved.
> +  Copyright (c) 2014 - 2021, ARM Ltd. All rights reserved.
>Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
>Copyright (c) 2016, Linaro Ltd. All rights reserved.
> +  Copyright (c) 2021, Semihalf All rights reserved.
>
>SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -19,6 +20,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -27,6 +29,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -703,6 +706,91 @@ HandleCapsules (
>
>  #define VERSION_STRING_PREFIXL"Tianocore/EDK2 firmware version "
>
> +/**
> +  This functions checks the value of BootDiscoverPolicy variable and
> +  connect devices of class specified by that variable. Then it refreshes
> +  Boot order for newly discovered boot device.
> +
> +  @retval  EFI_SUCCESS  Devices connected succesfully or connection
> +not required.
> +  @retval  others   Return values from GetVariable(), LocateProtocol()
> +and ConnectDeviceClass().
> +--*/
> +STATIC
> +EFI_STATUS
> +BootDiscoveryPolicyHandler (
> +  VOID
> +  )
> +{
> +  EFI_STATUS   Status;
> +  UINT32   DiscoveryPolicy;
> +  UINTNSize;
> +  EFI_BOOT_MANAGER_POLICY_PROTOCOL *BMPolicy;
> +  EFI_GUID *Class;
> +
> +  Size = sizeof (DiscoveryPolicy);
> +  Status = gRT->GetVariable (
> +  BOOT_DISCOVERY_POLICY_VAR,
> +  &gBootDiscoveryPolicyMgrFormsetGuid,
> +  NULL,
> +  &Size,
> +  &DiscoveryPolicy
> +  );
> +  if (Status == EFI_NOT_FOUND) {
> +Status = PcdSet32S (PcdBootDiscoveryPolicy, PcdGet32 
> (PcdBootDiscoveryPolicy));
> +if (Status == EFI_NOT_FOUND) {
> +  return EFI_SUCCESS;
> +} else if (EFI_ERROR (Status)) {
> +  return Status;
> +}
> +DiscoveryPolicy = PcdGet32 (PcdBootDiscoveryPolicy);
> +  } else if (EFI_ERROR (Status)) {
> +return Status;
> +  }
> +
> +  if (DiscoveryPolicy == BDP_CONNECT_MINIMAL) {
> +return EFI_SUCCESS;
> +  }
> +
> +  switch (DiscoveryPolicy) {
> +case BDP_CONNECT_NET:
> +  Class = &gEfiBootManagerPolicyNetworkGuid;
> +  break;
> +case BDP_CONNECT_ALL:
> +  Class = &gEfiBootManagerPolicyConnectAllGuid;
> +  break;
> +default:
> +  DEBUG ((
> +DEBUG_INFO,
> +"%a - Unexpected DiscoveryPolicy (0x%x). Run Minimal Discovery 
> Policy\n",
> +__FUNCTION__,
> +Disc

Re: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4

2021-08-06 Thread Ard Biesheuvel

On Thu, 5 Aug 2021 at 18:36, Jeremy Linton  wrote:
>
> The CM4 has an actual pcie slot, so we need to move the linkup
> check to the configuration probe logic. Further the device
> restriction logic needs to be relaxed to support downstream
> PCIe switches.
>
> Suggested-by: René Treffer 
> Signed-off-by: Jeremy Linton 

Please split this into two patches.

> ---
>  .../Bcm2711PciHostBridgeLibConstructor.c   |  5 -
>  .../Library/Bcm2711PciSegmentLib/PciSegmentLib.c   | 24 
> +++---
>  2 files changed, 17 insertions(+), 12 deletions(-)
>
> diff --git 
> a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
>  
> b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
> index 8587d2d36d..4d4c584726 100644
> --- 
> a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
> +++ 
> b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
> @@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor (
>} while (((Data & 0x30) != 0x030) && (Timeout));
>DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, 
> Timeout));
>
> -  if ((Data & 0x30) != 0x30) {
> -DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
> -return EFI_DEVICE_ERROR;
> -  }
> -
>if ((Data & 0x80) != 0x80) {
>  DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data));
>  return EFI_UNSUPPORTED;
> diff --git 
> a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c 
> b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
> index 44ce3b4b99..3ccc131eab 100644
> --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
> +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
> @@ -78,6 +78,8 @@ PciSegmentLibGetConfigBase (
>UINT64Base;
>UINT64Offset;
>UINT32Dev;
> +  UINT32Bus;
> +  UINT32Data;
>
>Base = PCIE_REG_BASE;
>Offset = Address & 0xFFF; /* Pick off the 4k register offset */
> @@ -89,17 +91,25 @@ PciSegmentLibGetConfigBase (
>  Base += PCIE_EXT_CFG_DATA;
>  if (mPciSegmentLastAccess != Address) {
>Dev = EFI_PCI_ADDR_DEV (Address);
> +  Bus = EFI_PCI_ADDR_BUS (Address);
> +
>/*
> -   * Scan things out directly rather than translating the "bus" to a 
> device, etc..
> -   * only we need to limit each bus to a single device.
> +   * There can only be a single device on bus 1 (downstream of root).
> +   * Subsequent busses (behind a PCIe switch) can have more.
> */
> -  if (Dev < 1) {
> -  MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
> -  mPciSegmentLastAccess = Address;
> -  } else {
> -  mPciSegmentLastAccess = 0;
> +  if (Dev > 0 && (Bus < 2)) {
>return 0x;
>}
> +
> +  /* Don't probe slots if the link is down */
> +  Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS);
> +  if ((Data & 0x30) != 0x30) {
> +  DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
> +  return 0x;
> +  }
> +
> +  MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
> +  mPciSegmentLastAccess = Address;
>  }
>}
>return Base + Offset;
> --
> 2.13.7
>


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Re: [edk2-devel] [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT

2021-08-06 Thread Ard Biesheuvel

On Thu, 5 Aug 2021 at 18:36, Jeremy Linton  wrote:
>
> Since we plan on toggling between XHCI and PCI the PCI
> root needs to be in its own SSDT. This is all thats needed
> of UEFI. The SMC conduit is provided directly to the running
> OS. When the OS detects this PCIe port, on a machine without
> a MADT it attempts to connect to the SMC conduit. The RPi
> definition doesn't have any power mgmt, and only provides
> a description of the root port.
>
> Signed-off-by: Jeremy Linton 
> ---
>  Platform/RaspberryPi/AcpiTables/AcpiTables.inf |   3 +
>  Platform/RaspberryPi/AcpiTables/Pci.asl| 237 
> +
>  Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c |   6 +
>  3 files changed, 246 insertions(+)
>  create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl
>
> diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf 
> b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
> index f3e8d950c1..da2a6db85f 100644
> --- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
> +++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
> @@ -39,6 +39,7 @@
>Pptt.aslc
>SsdtThermal.asl
>Xhci.asl
> +  Pci.asl
>
>  [Packages]
>ArmPkg/ArmPkg.dec
> @@ -59,6 +60,8 @@
>gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
>gArmTokenSpaceGuid.PcdGicDistributorBase
>gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr
> +  gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr
> +  gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen
>gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase
>gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress
>gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress
> diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl 
> b/Platform/RaspberryPi/AcpiTables/Pci.asl
> new file mode 100644
> index 00..34474f13ef
> --- /dev/null
> +++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
> @@ -0,0 +1,237 @@
> +/** @file
> + *
> + *  Copyright (c) 2019 Linaro, Limited. All rights reserved.
> + *  Copyright (c) 2021 Arm
> + *
> + *  SPDX-License-Identifier: BSD-2-Clause-Patent
> + *
> + **/
> +
> +#include 
> +
> +#include "AcpiTables.h"
> +
> +/*
> + * The following can be used to remove parenthesis from
> + * defined macros that the compiler complains about.
> + */
> +#define ISOLATE_ARGS(...)   __VA_ARGS__
> +#define REMOVE_PARENTHESES(x)   ISOLATE_ARGS x
> +
> +#define SANITIZED_PCIE_CPU_MMIO_WINDOW  
> REMOVE_PARENTHESES(PCIE_CPU_MMIO_WINDOW)
> +#define SANITIZED_PCIE_MMIO_LEN 
> REMOVE_PARENTHESES(PCIE_BRIDGE_MMIO_LEN)
> +#define SANITIZED_PCIE_PCI_MMIO_BEGIN   
> REMOVE_PARENTHESES(PCIE_TOP_OF_MEM_WIN)
> +
> +/*
> + * According to UEFI boot log for the VLI device on Pi 4.
> + */
> +#define RT_REG_LENGTH 0x1000
> +
> +// copy paste job from juno
> +#define LNK_DEVICE(Unique_Id, Link_Name, irq)
>  \
> +  Device(Link_Name) {
>  \
> +  Name(_HID, EISAID("PNP0C0F"))  
>  \
> +  Name(_UID, Unique_Id)  
>  \
> +  Name(_PRS, ResourceTemplate() {
>  \
> +  Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq }  
>  \
> +  }) 
>  \
> +  Method (_CRS, 0) { Return (_PRS) } 
>  \
> +  Method (_SRS, 1) { }   
>  \
> +  Method (_DIS) { }  
>  \
> +  }
> +
> +#define PRT_ENTRY(Address, Pin, Link)
> \
> +Package (4) {
> \
> +Address,/* uses the same format as _ADR */   
> \
> +Pin,/* The PCI pin number of the device (0-INTA, 1-INTB, 
> 2-INTC, 3-INTD). */ \
> +Link,   /* Interrupt allocated via Link device. */   
> \
> +Zero/* global system interrupt number (no used) */   
> \
> +  }
> +#define ROOT_PRT_ENTRY(Pin, Link)   PRT_ENTRY(0x, Pin, Link)
> +

This can be done in a much simpler way - SynQuacer uses this, for instance

Name (_PRT, Package () {
Package () { 0x, 0, Zero, 222 },   // INTA
Package () { 0x, 1, Zero, 222 },   // INTB
Package () { 0x, 2, Zero, 222 },   // INTC
Package () { 0x, 3, Zero, 222 },   // INTD
})

> +DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)
> +{
> +  Scope (\_SB_)
> +  {
> +
> +Device (SCB0) {
> +  Name (_HID, "ACPI0004")
> +  Name (_UID, 0x0)

Even if this file and the xhci one should never be exposed to the OS
at the same time, can we please us

Re: [edk2-devel] [PATCH v4 5/5] StandaloneMmPkg: build for 32bit arm machines

2021-08-06 Thread Etienne Carriere

Hello Liming

Thanks a lot for helping these patches to land.
I'm back on this and will address comments in a PATCH v5.

Regards,
etienne

On Wed, 28 Jul 2021 at 09:43, gaoliming  wrote:
>
> Etienne:
>
> I check the build log. Two build failure here. Can you update the patch to 
> fix them?
>
> 1. Two modules are only for AARCH64. They should be specified in 
> [Components.AARCH64] in ArmPkg\ArmPkg.dsc
>   ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf
>   ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf
>
> 2. StandaloneMmCoreEntryPoint library class header file is changed. It should 
> also be updated in StandaloneMmPkg\StandaloneMmPkg.dec
>
> ERROR - Library StandaloneMmCoreEntryPoint with path 
> Include/Library/AArch64/StandaloneMmCoreEntryPoint.h not found in package 
> filesystem
> ERROR - Library Header File Include/Library/Arm/StandaloneMmCoreEntryPoint.h 
> not declared in package DEC StandaloneMmPkg/StandaloneMmPkg.dec
>
> Thanks
> Liming
> > -邮件原件-
> > 发件人: devel@edk2.groups.io  代表 Ard
> > Biesheuvel
> > 发送时间: 2021年7月28日 14:52
> > 收件人: Sami Mujawar 
> > 抄送: gaoliming ; devel@edk2.groups.io;
> > Etienne Carriere ; Achin Gupta
> > ; Ard Biesheuvel ;
> > Jiewen Yao ; Leif Lindholm ;
> > Sughosh Ganu ; nd 
> > 主题: Re: [edk2-devel] [PATCH v4 5/5] StandaloneMmPkg: build for 32bit arm
> > machines
> >
> > On Wed, 28 Jul 2021 at 08:41, Sami Mujawar 
> > wrote:
> > >
> > > Hi Liming,
> > >
> > > I will look into this shortly.
> > >
> >
> > I submitted it here
> >
> > https://github.com/tianocore/edk2/pull/1823
> >
> > but it triggered a CI failure that was not immediately obvious to me,
> > and I haven't had time yet to dig into it.
> >
> >
> > >
> > > 
> > > From: gaoliming 
> > > Sent: Wednesday, 28 July 2021, 7:33 am
> > > To: devel@edk2.groups.io; gaolim...@byosoft.com.cn; a...@kernel.org
> > > Cc: Sami Mujawar; 'Etienne Carriere'; Achin Gupta; 'Ard Biesheuvel';
> > 'Jiewen Yao'; 'Leif Lindholm'; 'Sughosh Ganu'; nd
> > > Subject: 回复: [edk2-devel] [PATCH v4 5/5] StandaloneMmPkg: build for
> > 32bit arm machines
> > >
> > > Ard and Sami:
> > >   Will you help merge this patch set for 202108 stable tag?
> > >
> > > Thanks
> > > Liming
> > > > -邮件原件-
> > > > 发件人: devel@edk2.groups.io  代表 gaoliming
> > > > 发送时间: 2021年7月20日 17:21
> > > > 收件人: devel@edk2.groups.io; a...@kernel.org
> > > > 抄送: 'Sami Mujawar' ; 'Etienne Carriere'
> > > > ; 'Achin Gupta' ;
> > 'Ard
> > > > Biesheuvel' ; 'Jiewen Yao'
> > > > ; 'Leif Lindholm' ; 'Sughosh
> > > > Ganu' ; 'nd' 
> > > > 主题: 回复: [edk2-devel] [PATCH v4 5/5] StandaloneMmPkg: build for
> > 32bit
> > > > arm machines
> > > >
> > > > Ard:
> > > >   Thanks! I have added this feature into
> > > >
> > https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Release-Planni
> > > > ng.
> > > >
> > > > Thanks
> > > > Liming
> > > > > -邮件原件-
> > > > > 发件人: devel@edk2.groups.io  代表 Ard
> > > > > Biesheuvel
> > > > > 发送时间: 2021年7月20日 15:46
> > > > > 收件人: edk2-devel-groups-io ; Liming Gao
> > > > (Byosoft
> > > > > address) 
> > > > > 抄送: Sami Mujawar ; Etienne Carriere
> > > > > ; Achin Gupta ;
> > Ard
> > > > > Biesheuvel ; Jiewen Yao
> > > > > ; Leif Lindholm ; Sughosh
> > > > Ganu
> > > > > ; nd 
> > > > > 主题: Re: [edk2-devel] [PATCH v4 5/5] StandaloneMmPkg: build for
> > 32bit
> > > > arm
> > > > > machines
> > > > >
> > > > > On Tue, 20 Jul 2021 at 04:01, gaoliming 
> > > > wrote:
> > > > > >
> > > > > > Hi, all
> > > > > >   This patch set has passed code review. How about merge it for this
> > > > > stable tag edk2 202108?
> > > > > >
> > > > >
> > > > > OK, I will pick these up. Would you mind creating the entry for the
> > > > > release notes?
> > > > >
> > > > >
> > > > > > Thanks
> > > > > > Liming
> > > > > > > -邮件原件-
> > > > > > > 发件人: devel@edk2.groups.io  代表
> > Sami
> > > > > > > Mujawar
> > > > > > > 发送时间: 2021年5月19日 17:58
> > > > > > > 收件人: Etienne Carriere ;
> > > > > > > devel@edk2.groups.io
> > > > > > > 抄送: Achin Gupta ; Ard Biesheuvel
> > > > > > > ; Jiewen Yao ;
> > > > Leif
> > > > > > > Lindholm ; Sughosh Ganu
> > > > > ;
> > > > > > > n...@arm.com
> > > > > > > 主题: Re: [edk2-devel] [PATCH v4 5/5] StandaloneMmPkg: build for
> > > > 32bit
> > > > > arm
> > > > > > > machines
> > > > > > >
> > > > > > > Hi Etienn,
> > > > > > >
> > > > > > > This patch looks good to me.
> > > > > > >
> > > > > > > Reviewed-by: Sami Mujawar 
> > > > > > >
> > > > > > > Regards,
> > > > > > >
> > > > > > > Sami Mujawar
> > > > > > >
> > > > > > > On 19/05/2021 08:14 AM, Etienne Carriere wrote:
> > > > > > > > This change allows to build StandaloneMmPkg components for
> > 32bit
> > > > > Arm
> > > > > > > > StandaloneMm firmware.
> > > > > > > >
> > > > > > > > This change mainly moves AArch64/ source files to Arm/ side
> > directory
> > > > > > > > for several components:  StandaloneMmCpu,
> > > > > > > StandaloneMmCoreEntryPoint
> > > > > > > > and StandaloneMmMemLib. The source file is built for both 32b

[edk2-devel] [PATCH v2] UefiCpuPkg/CpuCacheInfoLib: Sort CpuCacheInfo array

2021-08-06 Thread Jason Lou

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3508

Sort the CpuCacheInfo array by CPU package ID, core type, cache level
and cache type.

Signed-off-by: Jason Lou 
Cc: Ray Ni 
Cc: Eric Dong 
Cc: Laszlo Ersek 
Cc: Rahul Kumar 
---
 UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c | 47 
+++-
 UefiCpuPkg/Include/Library/CpuCacheInfoLib.h |  2 +-
 UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf|  4 +-
 UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h | 27 +++
 UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf|  4 +-
 5 files changed, 80 insertions(+), 4 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c 
b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
index 126ee0da86..7474fe0f50 100644
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
@@ -37,6 +37,47 @@ CpuCacheInfoPrintCpuCacheInfoTable (
   DEBUG ((DEBUG_INFO, 
"+---+--+\n"));
 }
 
+/**
+  Function to compare CPU package ID, core type, cache level and cache type 
for use in QuickSort.
+
+  @param[in]  Buffer1 pointer to CPU_CACHE_INFO poiner to compare
+  @param[in]  Buffer2 pointer to second CPU_CACHE_INFO pointer to 
compare
+
+  @retval  0  Buffer1 equal to Buffer2
+  @retval  1  Buffer1 is greater than Buffer2
+  @retval  -1 Buffer1 is less than Buffer2
+**/
+INTN
+EFIAPI
+CpuCacheInfoCompare (
+  IN CONST VOID *Buffer1,
+  IN CONST VOID *Buffer2
+  )
+{
+  CPU_CACHE_INFO_COMPARATOR Comparator1, Comparator2;
+
+  ZeroMem (&Comparator1, sizeof (Comparator1));
+  ZeroMem (&Comparator2, sizeof (Comparator2));
+
+  Comparator1.Fields.Package= ((CPU_CACHE_INFO*)Buffer1)->Package;
+  Comparator1.Fields.CoreType   = ((CPU_CACHE_INFO*)Buffer1)->CoreType;
+  Comparator1.Fields.CacheLevel = ((CPU_CACHE_INFO*)Buffer1)->CacheLevel;
+  Comparator1.Fields.CacheType  = ((CPU_CACHE_INFO*)Buffer1)->CacheType;
+
+  Comparator2.Fields.Package= ((CPU_CACHE_INFO*)Buffer2)->Package;
+  Comparator2.Fields.CoreType   = ((CPU_CACHE_INFO*)Buffer2)->CoreType;
+  Comparator2.Fields.CacheLevel = ((CPU_CACHE_INFO*)Buffer2)->CacheLevel;
+  Comparator2.Fields.CacheType  = ((CPU_CACHE_INFO*)Buffer2)->CacheType;
+
+  if (Comparator1.Data64 == Comparator2.Data64) {
+return 0;
+  } else if (Comparator1.Data64 > Comparator2.Data64) {
+return 1;
+  } else {
+return -1;
+  }
+}
+
 /**
   Get the total number of package and package ID in the platform.
 
@@ -325,6 +366,10 @@ CpuCacheInfoCollectCpuCacheInfoData (
   if (*CacheInfoCount < LocalCacheInfoCount) {
 Status = EFI_BUFFER_TOO_SMALL;
   } else {
+//
+// Sort LocalCacheInfo array by CPU package ID, core type, cache level and 
cache type.
+//
+PerformQuickSort (LocalCacheInfo, LocalCacheInfoCount, sizeof 
(*LocalCacheInfo), (SORT_COMPARE) CpuCacheInfoCompare);
 CopyMem (CacheInfo, LocalCacheInfo, sizeof (*CacheInfo) * 
LocalCacheInfoCount);
 DEBUG_CODE (
   CpuCacheInfoPrintCpuCacheInfoTable (CacheInfo, LocalCacheInfoCount);
@@ -340,7 +385,7 @@ CpuCacheInfoCollectCpuCacheInfoData (
 }
 
 /**
-  Get CpuCacheInfo data array.
+  Get CpuCacheInfo data array. The array is sorted by CPU package ID, core 
type, cache level and cache type.
 
   @param[in, out] CpuCacheInfoPointer to the CpuCacheInfo array.
   @param[in, out] CpuCacheInfoCount   As input, point to the length of 
response CpuCacheInfo array.
diff --git a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h 
b/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
index a66152bce0..3422997f54 100644
--- a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
+++ b/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
@@ -59,7 +59,7 @@ typedef struct {
 } CPU_CACHE_INFO;
 
 /**
-  Get CpuCacheInfo data array.
+  Get CpuCacheInfo data array. The array is sorted by CPU package ID, core 
type, cache level and cache type.
 
   @param[in, out] CpuCacheInfoPointer to the CpuCacheInfo array.
   @param[in, out] CpuCacheInfoCount   As input, point to the length of 
response CpuCacheInfo array.
diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf 
b/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf
index c481080e49..c3d3f1e799 100644
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf
@@ -3,7 +3,7 @@
 #
 #  Provides cache info for each package, core type, cache level and cache type.
 #
-#  Copyright (c) 2020, Intel Corporation. All rights reserved.
+#  Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -25,6 +25,7 @@
 
 [Packages]
   MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
   UefiCpuPkg/Ue

[edk2-devel] [PATCH v1] UefiCpuPkg/CpuCacheInfoLib: Sort CpuCacheInfo array

2021-08-06 Thread Jason Lou

From: Jason 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3508

Sort the CpuCacheInfo array by the core type values from largest to
smallest.

Signed-off-by: Jason Lou 
Cc: Ray Ni 
Cc: Eric Dong 
Cc: Laszlo Ersek 
Cc: Rahul Kumar 
---
 UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c | 67 
+++-
 UefiCpuPkg/Include/Library/CpuCacheInfoLib.h |  3 +-
 UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf|  4 +-
 UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h |  1 +
 UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf|  4 +-
 5 files changed, 75 insertions(+), 4 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c 
b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
index 126ee0da86..fa4850c4fe 100644
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
@@ -37,6 +37,69 @@ CpuCacheInfoPrintCpuCacheInfoTable (
   DEBUG ((DEBUG_INFO, 
"+---+--+\n"));
 }
 
+/**
+  Function to compare core type for use in QuickSort.
+
+  @param[in]  Buffer1 pointer to core type poiner to compare
+  @param[in]  Buffer2 pointer to second core type pointer to 
compare
+
+  @retval  0  Buffer1 equal to Buffer2
+  @retval  1  Buffer1 is less than Buffer2
+  @retval  -1 Buffer1 is greater than Buffer2
+**/
+INTN
+EFIAPI
+CpuCacheInfoCompareCoreType (
+  IN CONST VOID *Buffer1,
+  IN CONST VOID *Buffer2
+  )
+{
+  if (((CPU_CACHE_INFO*)Buffer1)->CoreType == 
((CPU_CACHE_INFO*)Buffer2)->CoreType) {
+return 0;
+  } else if (((CPU_CACHE_INFO*)Buffer1)->CoreType < 
((CPU_CACHE_INFO*)Buffer2)->CoreType) {
+return 1;
+  } else {
+return -1;
+  }
+}
+
+/**
+  Sort CpuCacheInfo array by the core type values from largest to smallest.
+
+  @param[in, out] CpuCacheInfoPointer to the CpuCacheInfo array.
+  @param[in]  CpuCacheInfoCount   The length of CpuCacheInfo array.
+
+**/
+VOID
+CpuCacheInfoSort (
+  IN OUT CPU_CACHE_INFO *CpuCacheInfo,
+  IN UINTN  CpuCacheInfoCount
+  )
+{
+  UINTN Index;
+  UINTN NextIndex;
+  UINT32CurrentPackage;
+  UINT8 CacheInfoCountPerPackage;
+
+  for (Index = 0; Index < CpuCacheInfoCount; Index += 
CacheInfoCountPerPackage) {
+//
+// Calculate the number of CpuCacheInfo current processor has.
+//
+CurrentPackage = CpuCacheInfo[Index].Package;
+CacheInfoCountPerPackage = 1;
+for (NextIndex = Index + 1; NextIndex < CpuCacheInfoCount; NextIndex++) {
+  if (CurrentPackage == CpuCacheInfo[NextIndex].Package) {
+CacheInfoCountPerPackage++;
+  }
+}
+
+//
+// Sort CpuCacheInfo for current processor by the core type values from 
largest to smallest.
+//
+PerformQuickSort (&CpuCacheInfo[Index], CacheInfoCountPerPackage, sizeof 
(*CpuCacheInfo), (SORT_COMPARE) CpuCacheInfoCompareCoreType);
+  }
+}
+
 /**
   Get the total number of package and package ID in the platform.
 
@@ -325,6 +388,7 @@ CpuCacheInfoCollectCpuCacheInfoData (
   if (*CacheInfoCount < LocalCacheInfoCount) {
 Status = EFI_BUFFER_TOO_SMALL;
   } else {
+CpuCacheInfoSort (LocalCacheInfo, LocalCacheInfoCount);
 CopyMem (CacheInfo, LocalCacheInfo, sizeof (*CacheInfo) * 
LocalCacheInfoCount);
 DEBUG_CODE (
   CpuCacheInfoPrintCpuCacheInfoTable (CacheInfo, LocalCacheInfoCount);
@@ -340,7 +404,8 @@ CpuCacheInfoCollectCpuCacheInfoData (
 }
 
 /**
-  Get CpuCacheInfo data array.
+  Get CpuCacheInfo data array. The data array is sorted by CPU package ID from 
smallest to largest,
+  by core type from largest to smallest and by cache level from smallest to 
largest.
 
   @param[in, out] CpuCacheInfoPointer to the CpuCacheInfo array.
   @param[in, out] CpuCacheInfoCount   As input, point to the length of 
response CpuCacheInfo array.
diff --git a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h 
b/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
index a66152bce0..d813f53bf7 100644
--- a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
+++ b/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
@@ -59,7 +59,8 @@ typedef struct {
 } CPU_CACHE_INFO;
 
 /**
-  Get CpuCacheInfo data array.
+  Get CpuCacheInfo data array. The data array is sorted by CPU package ID from 
smallest to largest,
+  by core type from largest to smallest and by cache level from smallest to 
largest.
 
   @param[in, out] CpuCacheInfoPointer to the CpuCacheInfo array.
   @param[in, out] CpuCacheInfoCount   As input, point to the length of 
response CpuCacheInfo array.
diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf 
b/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf
index c481080e49..c3d3f1e799 100644
--- a/U

[edk2-devel] [PATCH EDK2 v1 1/1] BaseTools: Remove dependence of libuuid

2021-08-06 Thread wenyi,xie via groups.io

The uuid.h only included in file GenFvInternalLib.c,
but no interface from libuuid is used in this file.
So remove this include and link to libuuid.

Cc: Bob Feng 
Cc: Liming Gao 
Cc: Yuwei Chen 
Signed-off-by: Wenyi Xie 
---
 BaseTools/Source/C/GenFv/GenFvInternalLib.c | 5 -
 BaseTools/Source/C/DevicePath/GNUmakefile   | 4 
 BaseTools/Source/C/GenFv/GNUmakefile| 4 
 BaseTools/Source/C/GenFw/GNUmakefile| 4 
 BaseTools/Source/C/GenSec/GNUmakefile   | 4 
 5 files changed, 21 deletions(-)

diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c 
b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
index 6e296b8ad6b2..80bab7fb1381 100644
--- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
+++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
@@ -13,11 +13,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 // Include files
 //
 
-#if defined(__FreeBSD__)
-#include 
-#elif defined(__GNUC__)
-#include 
-#endif
 #ifdef __GNUC__
 #include 
 #endif
diff --git a/BaseTools/Source/C/DevicePath/GNUmakefile 
b/BaseTools/Source/C/DevicePath/GNUmakefile
index 7ca08af9662d..1271555df8d5 100644
--- a/BaseTools/Source/C/DevicePath/GNUmakefile
+++ b/BaseTools/Source/C/DevicePath/GNUmakefile
@@ -18,7 +18,3 @@ ifeq ($(CYGWIN), CYGWIN)
   LIBS += -L/lib/e2fsprogs -luuid
 endif
 
-ifeq ($(LINUX), Linux)
-  LIBS += -luuid
-endif
-
diff --git a/BaseTools/Source/C/GenFv/GNUmakefile 
b/BaseTools/Source/C/GenFv/GNUmakefile
index 7c7b95ba1be2..fd8f16903ade 100644
--- a/BaseTools/Source/C/GenFv/GNUmakefile
+++ b/BaseTools/Source/C/GenFv/GNUmakefile
@@ -17,7 +17,3 @@ ifeq ($(CYGWIN), CYGWIN)
   LIBS += -L/lib/e2fsprogs -luuid
 endif
 
-ifeq ($(LINUX), Linux)
-  LIBS += -luuid
-endif
-
diff --git a/BaseTools/Source/C/GenFw/GNUmakefile 
b/BaseTools/Source/C/GenFw/GNUmakefile
index 76cda7e7a3f6..3b9a781b5cf6 100644
--- a/BaseTools/Source/C/GenFw/GNUmakefile
+++ b/BaseTools/Source/C/GenFw/GNUmakefile
@@ -17,7 +17,3 @@ ifeq ($(CYGWIN), CYGWIN)
   LIBS += -L/lib/e2fsprogs -luuid
 endif
 
-ifeq ($(LINUX), Linux)
-  LIBS += -luuid
-endif
-
diff --git a/BaseTools/Source/C/GenSec/GNUmakefile 
b/BaseTools/Source/C/GenSec/GNUmakefile
index 9f0844c1b8fe..c2f440f21ebf 100644
--- a/BaseTools/Source/C/GenSec/GNUmakefile
+++ b/BaseTools/Source/C/GenSec/GNUmakefile
@@ -17,7 +17,3 @@ ifeq ($(CYGWIN), CYGWIN)
   LIBS += -L/lib/e2fsprogs -luuid
 endif
 
-ifeq ($(LINUX), Linux)
-  LIBS += -luuid
-endif
-
-- 
2.20.1.windows.1



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[edk2-devel] [PATCH EDK2 v1 0/1] BaseTools: Remove dependence of libuuid

2021-08-06 Thread wenyi,xie via groups.io

Main Changes :
1.remove include uuid.h and link to libuuid. And try to build under linux, the 
building is sucessful.

Wenyi Xie (1):
  BaseTools: Remove dependence of libuuid

 BaseTools/Source/C/GenFv/GenFvInternalLib.c | 5 -
 BaseTools/Source/C/DevicePath/GNUmakefile   | 4 
 BaseTools/Source/C/GenFv/GNUmakefile| 4 
 BaseTools/Source/C/GenFw/GNUmakefile| 4 
 BaseTools/Source/C/GenSec/GNUmakefile   | 4 
 5 files changed, 21 deletions(-)

-- 
2.20.1.windows.1



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Re: [edk2-devel] [PATCH v3 0/2] Relocate LINUX_EFI_INITRD_MEDIA_GUID to MdePkg

2021-08-06 Thread Ard Biesheuvel

On Thu, 5 Aug 2021 at 00:03, Jeff Brasen  wrote:
>
> Relocate LINUX_EFI_INITRD_MEDIA_GUID from OvmfPkg to MdePkg as it has
> use outside of Ovmf applications
>
> Jeff Brasen (2):
>   OvmfPkg: Remove Initrd LINUX_EFI_INITRD_MEDIA_GUID
>   MdePkg: add definition of LINUX_EFI_INITRD_MEDIA_GUID
>
>  MdePkg/MdePkg.dec  |  5 
>  OvmfPkg/OvmfPkg.dec|  1 -
>  MdePkg/Include/Guid/LinuxEfiInitrdMedia.h  | 31 ++
>  OvmfPkg/Include/Guid/LinuxEfiInitrdMedia.h | 17 
>  4 files changed, 36 insertions(+), 18 deletions(-)
>  create mode 100644 MdePkg/Include/Guid/LinuxEfiInitrdMedia.h
>  delete mode 100644 OvmfPkg/Include/Guid/LinuxEfiInitrdMedia.h
>


Merged as #1869

Thanks,


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Re: [edk2-devel] [PATCH] ArmPkg: Enable boot discovery policy for ARM package.

2021-08-06 Thread Sunny Wang

Looks good. Thanks, Greg.
Reviewed-by: Sunny Wang 

For others' reference, this patch is similar to the one below for Rasberry Pi 
that just got merged.
  - https://edk2.groups.io/g/devel/message/78514
After merging this change, we should be able to easily enable "boot discovery 
policy" on other ARM platforms.  For the platform that doesn't include 
BootManagerPolicyDxe driver but using ArmPkg PlatformBootManagerLib, it would 
just do nothing (the behavior will be kept the same as before).

Best Regards,
Sunny Wang

-Original Message-
From: Grzegorz Bernacki 
Sent: Friday, August 6, 2021 4:30 PM
To: devel@edk2.groups.io
Cc: l...@nuviainc.com; ardb+tianoc...@kernel.org; Samer El-Haj-Mahmoud 
; Sunny Wang ; 
m...@semihalf.com; upstr...@semihalf.com; Grzegorz Bernacki 
Subject: [PATCH] ArmPkg: Enable boot discovery policy for ARM package.

This commit adds code which check BootDiscoveryPolicy variable and
calls Boot Policy Manager Protocol to connect device specified by
the variable. To enable that mechanism for platform
EfiMdeModulePkgTokenSpaceGuid.PcdBootDiscoveryPolicy PCD must be
added to DSC file and BootDiscoveryPolicyUiLib should be added to
UiApp libraries.

Signed-off-by: Grzegorz Bernacki 
---
 ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf |  5 +
 ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c   | 96 
+++-
 2 files changed, 100 insertions(+), 1 deletion(-)

diff --git a/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf 
b/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
index 353d7a967b..86751b45f8 100644
--- a/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+++ b/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -65,11 +65,15 @@

 [Pcd]
   gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBootDiscoveryPolicy

 [Guids]
+  gBootDiscoveryPolicyMgrFormsetGuid
   gEdkiiNonDiscoverableEhciDeviceGuid
   gEdkiiNonDiscoverableUhciDeviceGuid
   gEdkiiNonDiscoverableXhciDeviceGuid
+  gEfiBootManagerPolicyNetworkGuid
+  gEfiBootManagerPolicyConnectAllGuid
   gEfiFileInfoGuid
   gEfiFileSystemInfoGuid
   gEfiFileSystemVolumeLabelInfoIdGuid
@@ -79,6 +83,7 @@

 [Protocols]
   gEdkiiNonDiscoverableDeviceProtocolGuid
+  gEfiBootManagerPolicyProtocolGuid
   gEfiDevicePathProtocolGuid
   gEfiGraphicsOutputProtocolGuid
   gEfiLoadedImageProtocolGuid
diff --git a/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c 
b/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c
index 5ceb23d822..4332c45bb7 100644
--- a/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c
+++ b/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c
@@ -2,9 +2,10 @@
   Implementation for PlatformBootManagerLib library class interfaces.

   Copyright (C) 2015-2016, Red Hat, Inc.
-  Copyright (c) 2014 - 2019, ARM Ltd. All rights reserved.
+  Copyright (c) 2014 - 2021, ARM Ltd. All rights reserved.
   Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
   Copyright (c) 2016, Linaro Ltd. All rights reserved.
+  Copyright (c) 2021, Semihalf All rights reserved.

   SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -19,6 +20,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -27,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -703,6 +706,91 @@ HandleCapsules (

 #define VERSION_STRING_PREFIXL"Tianocore/EDK2 firmware version "

+/**
+  This functions checks the value of BootDiscoverPolicy variable and
+  connect devices of class specified by that variable. Then it refreshes
+  Boot order for newly discovered boot device.
+
+  @retval  EFI_SUCCESS  Devices connected succesfully or connection
+not required.
+  @retval  others   Return values from GetVariable(), LocateProtocol()
+and ConnectDeviceClass().
+--*/
+STATIC
+EFI_STATUS
+BootDiscoveryPolicyHandler (
+  VOID
+  )
+{
+  EFI_STATUS   Status;
+  UINT32   DiscoveryPolicy;
+  UINTNSize;
+  EFI_BOOT_MANAGER_POLICY_PROTOCOL *BMPolicy;
+  EFI_GUID *Class;
+
+  Size = sizeof (DiscoveryPolicy);
+  Status = gRT->GetVariable (
+  BOOT_DISCOVERY_POLICY_VAR,
+  &gBootDiscoveryPolicyMgrFormsetGuid,
+  NULL,
+  &Size,
+  &DiscoveryPolicy
+  );
+  if (Status == EFI_NOT_FOUND) {
+Status = PcdSet32S (PcdBootDiscoveryPolicy, PcdGet32 
(PcdBootDiscoveryPolicy));
+if (Status == EFI_NOT_FOUND) {
+  return EFI_SUCCESS;
+} else if (EFI_ERROR (Status)) {
+  return Status;
+}
+DiscoveryPolicy = PcdGet32 (PcdBootDiscoveryPolicy);
+  } else if (EFI_ERROR (Status)) {
+return Status;
+  }
+
+  if (DiscoveryPolicy == BDP_CONNECT_MINIMAL) {
+return EFI_SUCCESS;
+  }
+
+  switch (DiscoveryPolicy) {
+case BDP

[edk2-devel] [PATCH] ArmPkg: Enable boot discovery policy for ARM package.

2021-08-06 Thread Grzegorz Bernacki

This commit adds code which check BootDiscoveryPolicy variable and
calls Boot Policy Manager Protocol to connect device specified by
the variable. To enable that mechanism for platform
EfiMdeModulePkgTokenSpaceGuid.PcdBootDiscoveryPolicy PCD must be
added to DSC file and BootDiscoveryPolicyUiLib should be added to
UiApp libraries.

Signed-off-by: Grzegorz Bernacki 
---
 ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf |  5 +
 ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c   | 96 
+++-
 2 files changed, 100 insertions(+), 1 deletion(-)

diff --git a/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf 
b/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
index 353d7a967b..86751b45f8 100644
--- a/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+++ b/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -65,11 +65,15 @@
 
 [Pcd]
   gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBootDiscoveryPolicy
 
 [Guids]
+  gBootDiscoveryPolicyMgrFormsetGuid
   gEdkiiNonDiscoverableEhciDeviceGuid
   gEdkiiNonDiscoverableUhciDeviceGuid
   gEdkiiNonDiscoverableXhciDeviceGuid
+  gEfiBootManagerPolicyNetworkGuid
+  gEfiBootManagerPolicyConnectAllGuid
   gEfiFileInfoGuid
   gEfiFileSystemInfoGuid
   gEfiFileSystemVolumeLabelInfoIdGuid
@@ -79,6 +83,7 @@
 
 [Protocols]
   gEdkiiNonDiscoverableDeviceProtocolGuid
+  gEfiBootManagerPolicyProtocolGuid
   gEfiDevicePathProtocolGuid
   gEfiGraphicsOutputProtocolGuid
   gEfiLoadedImageProtocolGuid
diff --git a/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c 
b/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c
index 5ceb23d822..4332c45bb7 100644
--- a/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c
+++ b/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c
@@ -2,9 +2,10 @@
   Implementation for PlatformBootManagerLib library class interfaces.
 
   Copyright (C) 2015-2016, Red Hat, Inc.
-  Copyright (c) 2014 - 2019, ARM Ltd. All rights reserved.
+  Copyright (c) 2014 - 2021, ARM Ltd. All rights reserved.
   Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
   Copyright (c) 2016, Linaro Ltd. All rights reserved.
+  Copyright (c) 2021, Semihalf All rights reserved.
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -19,6 +20,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -27,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -703,6 +706,91 @@ HandleCapsules (
 
 #define VERSION_STRING_PREFIXL"Tianocore/EDK2 firmware version "
 
+/**
+  This functions checks the value of BootDiscoverPolicy variable and
+  connect devices of class specified by that variable. Then it refreshes
+  Boot order for newly discovered boot device.
+
+  @retval  EFI_SUCCESS  Devices connected succesfully or connection
+not required.
+  @retval  others   Return values from GetVariable(), LocateProtocol()
+and ConnectDeviceClass().
+--*/
+STATIC
+EFI_STATUS
+BootDiscoveryPolicyHandler (
+  VOID
+  )
+{
+  EFI_STATUS   Status;
+  UINT32   DiscoveryPolicy;
+  UINTNSize;
+  EFI_BOOT_MANAGER_POLICY_PROTOCOL *BMPolicy;
+  EFI_GUID *Class;
+
+  Size = sizeof (DiscoveryPolicy);
+  Status = gRT->GetVariable (
+  BOOT_DISCOVERY_POLICY_VAR,
+  &gBootDiscoveryPolicyMgrFormsetGuid,
+  NULL,
+  &Size,
+  &DiscoveryPolicy
+  );
+  if (Status == EFI_NOT_FOUND) {
+Status = PcdSet32S (PcdBootDiscoveryPolicy, PcdGet32 
(PcdBootDiscoveryPolicy));
+if (Status == EFI_NOT_FOUND) {
+  return EFI_SUCCESS;
+} else if (EFI_ERROR (Status)) {
+  return Status;
+}
+DiscoveryPolicy = PcdGet32 (PcdBootDiscoveryPolicy);
+  } else if (EFI_ERROR (Status)) {
+return Status;
+  }
+
+  if (DiscoveryPolicy == BDP_CONNECT_MINIMAL) {
+return EFI_SUCCESS;
+  }
+
+  switch (DiscoveryPolicy) {
+case BDP_CONNECT_NET:
+  Class = &gEfiBootManagerPolicyNetworkGuid;
+  break;
+case BDP_CONNECT_ALL:
+  Class = &gEfiBootManagerPolicyConnectAllGuid;
+  break;
+default:
+  DEBUG ((
+DEBUG_INFO,
+"%a - Unexpected DiscoveryPolicy (0x%x). Run Minimal Discovery 
Policy\n",
+__FUNCTION__,
+DiscoveryPolicy
+));
+  return EFI_SUCCESS;
+  }
+
+  Status = gBS->LocateProtocol (
+  &gEfiBootManagerPolicyProtocolGuid,
+  NULL,
+  (VOID **)&BMPolicy
+  );
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_INFO, "%a - Failed to locate 
gEfiBootManagerPolicyProtocolGuid."
+  "Driver connect will be skipped.\n", __FUNCTION__));
+return Status;
+  }
+
+  Status = BMPolicy->ConnectDeviceClass (BMPolicy, Class);
+  if (EFI_ER

Re: [edk2-devel] [PATCH v2 00/13] Add ACPI 6.4 header file

2021-08-06 Thread Sami Mujawar

For this series.

Reviewed-by: Sami Mujawar 

Regards,

Sami Mujawar

On 05/08/2021, 17:25, "Chris Jones"  wrote:

Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516)

This patch series introduces a header file for the latest version of the
ACPI 6.4 specification, January 2021. This header contains all updates
to the ACPI specification in addition to addressing a few small errors
from the previous ACPI header files.

Changes since v1:
1. Patch 13/13
- Remove EFI_ACPI_6_4_GIC_STRUCTURE field name changes. [Liming]
- Add Acpi64.h to IgnoreFiles list in MdePkg.ci.yaml. [Liming]

The changes can be seen at: 
https://github.com/chris-jones-arm/edk2/tree/1661_add_acpi_64_header_v2

Chris Jones (13):
  MdePkg: Add ACPI 6.4 header file
  MdePkg: Increment FADT version
  MdePkg: Rename SBSA Generic Watchdog to Arm Generic Watchdog
  MdePkg: Update PMTT to ACPI 6.4
  MdePkg: Add SPA Location Cookie field to SPA Range structure
  MdePkg: Remove DPPT table
  MdePkg: Add flags and MinTransferSize to Generic Initiator
  MdePkg: Add 'Type 5' PCC structure
  MdePkg: Add Multiprocessor Wakeup structure
  MdePkg: Add the Platform Health Assessment Table (PHAT)
  MdePkg: Add Secure Access Components in the SDEV table
  MdePkg: Add Cache ID to PPTT
  MdePkg: Fix broken coding style in Acpi64.h

 MdePkg/Include/IndustryStandard/Acpi.h   |4 +-
 MdePkg/Include/IndustryStandard/Acpi64.h | 3148 
 MdePkg/MdePkg.ci.yaml|2 +
 3 files changed, 3152 insertions(+), 2 deletions(-)
 create mode 100644 MdePkg/Include/IndustryStandard/Acpi64.h

-- 
Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")




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[edk2-devel] [PATCH] UefiPayloadPkg/PayloadEntry: Inherit 4/5-level paging from bootloader

2021-08-06 Thread Ni, Ray

The patch removes the dep on PcdUse5LevelPageTable.
Now the payload inherits the 5-level paging setting from
bootloader in IA-32e mode and uses 4-level paging in
legacy protected mode.

This fix the potential issue when bootloader enables 5-level paging
but 64bit payload sets 4-level page table to CR3 resulting CPU
exception because PcdUse5LevelPageTable is FALSE.

Signed-off-by: Ray Ni 
Cc: Guo Dong 
Cc: Ray Ni 
Cc: Maurice Ma 
Cc: Benjamin You 
---
 .../UefiPayloadEntry/UefiPayloadEntry.inf |  1 -
 .../UniversalPayloadEntry.inf |  1 -
 .../UefiPayloadEntry/X64/VirtualMemory.c  | 38 ---
 3 files changed, 16 insertions(+), 24 deletions(-)

diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf 
b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
index 8d42925fcd..9b6fab66a1 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
+++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
@@ -80,7 +80,6 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask## 
CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask   ## 
CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard   ## 
CONSUMES
-  gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable  ## 
SOMETIMES_CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase## 
CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize## 
CONSUMES
 
diff --git a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf 
b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
index 416a620598..aae62126e9 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
+++ b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
@@ -85,7 +85,6 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask## 
CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask   ## 
CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard   ## 
CONSUMES
-  gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable  ## 
SOMETIMES_CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase## 
CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize## 
CONSUMES
 
diff --git a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c 
b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
index a1c4ad6ff4..9daa46c12c 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
@@ -15,7 +15,7 @@
 2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 
2:Instruction Set Reference, Intel
 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System 
Programmer's Guide, Intel
 
-Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
 Copyright (c) 2017, AMD Incorporated. All rights reserved.
 
 SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -668,7 +668,6 @@ CreateIdentityMappingPageTables (
   )
 {
   UINT32RegEax;
-  CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX   EcxFlags;
   UINT32RegEdx;
   UINT8 PhysicalAddressBits;
   EFI_PHYSICAL_ADDRESS  PageAddress;
@@ -687,7 +686,7 @@ CreateIdentityMappingPageTables (
   UINTN TotalPagesNum;
   UINTN BigPageAddress;
   VOID  *Hob;
-  BOOLEAN   Page5LevelSupport;
+  BOOLEAN   Enable5LevelPaging;
   BOOLEAN   Page1GSupport;
   PAGE_TABLE_1G_ENTRY   *PageDirectory1GEntry;
   UINT64AddressEncMask;
@@ -730,18 +729,16 @@ CreateIdentityMappingPageTables (
 }
   }
 
-  Page5LevelSupport = FALSE;
-  if (PcdGetBool (PcdUse5LevelPageTable)) {
-AsmCpuidEx (
-  CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, NULL,
-  &EcxFlags.Uint32, NULL, NULL
-  );
-if (EcxFlags.Bits.FiveLevelPage != 0) {
-  Page5LevelSupport = TRUE;
-}
-  }
+  //
+  // Check CR4.LA57[bit12] to determin whether 5-Level Paging is enabled.
+  // Because this code runs at both IA-32e (64bit) mode and legacy protected 
(32bit) mode,
+  // below logic inherits the 5-level paging setting from bootloader in IA-32e 
mode
+  // and uses 4-level paging in legacy protected mode.
+  //
+  Cr4.UintN = AsmReadCr4 ();
+  Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);
 
-  DEBUG ((DEBUG_INFO, "AddressBits=%u 5LevelPaging=%u 1GPage=%u\n", 
PhysicalAddressBits, Page5LevelSupport, Page1GSupport));
+  DEBUG

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