Re: [edk2-devel] 回复: [PATCH 3/8] MdePkg: Add definition of EFI_CC_EVENT_HOB_GUID
On March 2, 2022 9:53 AM, Gao Liming wrote: > Min: > Is this GUID from > intel-tdx-guest-hypervisor-communication-interface-1.0-344426-002.pdf? > > > EFI_CC_EVENT_HOB_GUID is the global ID of a GUIDed HOB used to pass > > TDX_DIGEST_VALUE from SEC to a DXE Driver ( This DXE driver will be > > introduced in the following commit in this patch-sets ). In that DXE > > driver this GUIDed HOB will be parsed and the TDX_DIGEST_VALUE then > > will be extracted. After that a EFI_CC_EVENT will be created based on > > it. Liming EFI_CC_EVENT_HOB_GUID is not defined in the GHCI spec. It is used internally by edk2. I will move its definition to SecurityPkg. Thanks Min -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87254): https://edk2.groups.io/g/devel/message/87254 Mute This Topic: https://groups.io/mt/89492913/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v2] MdeModulePkg: Add a check for metadata size in NvmExpress Driver
Reviewed-by: Hao A Wu
Best Regards,
Hao Wu
> -Original Message-
> From: Ma, Hua
> Sent: Thursday, March 3, 2022 1:06 PM
> To: devel@edk2.groups.io
> Cc: Wang, Jian J ; Gao, Liming
> ; Wu, Hao A ; Ni, Ray
> ; Ma, Hua
> Subject: [PATCH v2] MdeModulePkg: Add a check for metadata size in
> NvmExpress Driver
>
> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3856
>
> Currently this NvmeExpress Driver do not support metadata handling.
> According to the NVME specs, metadata may be transferred to the host after
> the logical block data. It can overrun the input buffer which may only
> be the size of logical block data.
>
> Add a check to return not support for the namespaces formatted with
> metadata.
>
> v2 changes:
> - Change debug log level from INFO to ERROR
> - Change to if (NamespaceData->LbaFormat[LbaFmtIdx].Ms != 0)
>
> v1: https://edk2.groups.io/g/devel/message/87242
>
> Cc: Jian J Wang
> Cc: Liming Gao
> Cc: Hao A Wu
> Cc: Ray Ni
>
> Signed-off-by: Hua Ma
> ---
> MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c | 15
> +++
> .../Bus/Pci/NvmExpressPei/NvmExpressPei.c | 15 +++
> 2 files changed, 30 insertions(+)
>
> diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c
> b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c
> index 5a1eda8e8d..388583e4d5 100644
> --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c
> +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c
> @@ -139,6 +139,21 @@ EnumerateNvmeDevNamespace (
>
> Flbas = NamespaceData->Flbas;
> LbaFmtIdx = Flbas & 0xF;
> +
> +//
> +// Currently this NVME driver only suport Metadata Size == 0
> +//
> +if (NamespaceData->LbaFormat[LbaFmtIdx].Ms != 0) {
> + DEBUG ((
> +DEBUG_ERROR,
> +"NVME IDENTIFY NAMESPACE [%d] Ms(%d) is not supported.\n",
> +NamespaceId,
> +NamespaceData->LbaFormat[LbaFmtIdx].Ms
> +));
> + Status = EFI_UNSUPPORTED;
> + goto Exit;
> +}
> +
> Lbads = NamespaceData->LbaFormat[LbaFmtIdx].Lbads;
> Device->Media.BlockSize = (UINT32)1 << Lbads;
>
> diff --git a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.c
> b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.c
> index f73053fc3f..e8a29f23c7 100644
> --- a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.c
> +++ b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.c
> @@ -104,6 +104,21 @@ EnumerateNvmeDevNamespace (
>//
>Flbas = NamespaceData->Flbas;
>LbaFmtIdx = Flbas & 0xF;
> +
> + //
> + // Currently this NVME driver only suport Metadata Size == 0
> + //
> + if (NamespaceData->LbaFormat[LbaFmtIdx].Ms != 0) {
> +DEBUG ((
> + DEBUG_ERROR,
> + "NVME IDENTIFY NAMESPACE [%d] Ms(%d) is not supported.\n",
> + NamespaceId,
> + NamespaceData->LbaFormat[LbaFmtIdx].Ms
> + ));
> +Status = EFI_UNSUPPORTED;
> +goto Exit;
> + }
> +
>Lbads = NamespaceData->LbaFormat[LbaFmtIdx].Lbads;
>
>NamespaceInfo->Media.InterfaceType = MSG_NVME_NAMESPACE_DP;
> --
> 2.32.0.windows.2
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Re: [edk2-devel] [PATCH 1/2] Reconfigure OpensslLib to add elliptic curve chipher algorithms
Sorry I missed the earlier feedback from You/Gerd/Jiewen and replied quickly with my updated patch set. I will try to look at them. -Vineel -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87252): https://edk2.groups.io/g/devel/message/87252 Mute This Topic: https://groups.io/mt/86257810/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH 1/2] Reconfigure OpensslLib to add elliptic curve chipher algorithms
Hi Yi Li, I am able to incorporate all your feedback regarding commit hygiene. Also able to validate them by firing an sample PR against EDK2 master https://github.com/tianocore/edk2/pull/2550/checks All of the checks passed expected 3 which seems to be infrastructure related. I would need your teams help in taking a look at them if its caused by my commits. Broken down the commits per area owner and CC'ed them. 0001-CryptoPkg-Reconfigure-OpensslLib-to-add-elliptic-cur.patch 0002-CryptoPkg-Reference-to-VsIntrincsicLib-to-build-Open.patch 0003-MdePkg-Add-VsIntrincsicLib-to-support-building-OpenS.patch 0004-EmulatorPkg-Reference-to-VsIntrincsicLib-to-build-Op.patch 0005-OvmfPkg-Reference-to-VsIntrincsicLib-to-build-OpenSS.patch 0006-OvmfPkg-Increase-DXEFV-size-to-accommodate-ECC-ciphe.patch Updated the bug https://bugzilla.tianocore.org/show_bug.cgi?id=3679 with the patch set. Thanks for your help, Vineel -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87251): https://edk2.groups.io/g/devel/message/87251 Mute This Topic: https://groups.io/mt/86257810/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH] MdeModulePkg/Usb/Keyboard.c: Don't request protocol before setting
Pushed via:
PR - https://github.com/tianocore/edk2/pull/2574
Commit -
https://github.com/tianocore/edk2/commit/589d51df260465e2561979b8a988e77b0f32a6e8
Best Regards,
Hao Wu
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Wu, Hao
> A
> Sent: Wednesday, March 2, 2022 10:10 AM
> To: Rhodes, Sean ; devel@edk2.groups.io
> Cc: Dong, Guo ; Rhodes, Sean
> ; Ni, Ray ; Matt DeVillier
> ; Patrick Rudolph
>
> Subject: Re: [edk2-devel] [PATCH] MdeModulePkg/Usb/Keyboard.c: Don't
> request protocol before setting
>
> Reviewed-by: Hao A Wu
>
> Best Regards,
> Hao Wu
>
> > -Original Message-
> > From: Sean Rhodes
> > Sent: Thursday, February 24, 2022 7:38 PM
> > To: devel@edk2.groups.io
> > Cc: Dong, Guo ; Rhodes, Sean
> > ; Wu, Hao A ; Ni, Ray
> > ; Matt DeVillier ; Patrick
> > Rudolph
> > Subject: [PATCH] MdeModulePkg/Usb/Keyboard.c: Don't request protocol
> > before setting
> >
> > No need to check the interface protocol then conditionally setting,
> > just set it to BOOT_PROTOCOL and check for error.
> >
> > This is what Linux does for HID devices as some don't follow the USB spec.
> > One example is the Aspeed BMC HID keyboard device, which adds a
> > massive boot delay without this patch as it doesn't respond to
> 'GetProtocolRequest'.
> >
> > Cc: Hao A Wu
> > Cc: Ray Ni
> > Signed-off-by: Matt DeVillier
> > Signed-off-by: Patrick Rudolph
> > Signed-off-by: Sean Rhodes
> > ---
> > MdeModulePkg/Bus/Usb/UsbKbDxe/KeyBoard.c | 18 +-
> > 1 file changed, 5 insertions(+), 13 deletions(-)
> >
> > diff --git a/MdeModulePkg/Bus/Usb/UsbKbDxe/KeyBoard.c
> > b/MdeModulePkg/Bus/Usb/UsbKbDxe/KeyBoard.c
> > index 5a94a4dda7..b5a6459a35 100644
> > --- a/MdeModulePkg/Bus/Usb/UsbKbDxe/KeyBoard.c
> > +++ b/MdeModulePkg/Bus/Usb/UsbKbDxe/KeyBoard.c
> > @@ -805,7 +805,6 @@ InitUSBKeyboard (
> >)
> >
> > {
> >
> >UINT16 ConfigValue;
> >
> > - UINT8 Protocol;
> >
> >EFI_STATUS Status;
> >
> >UINT32 TransferResult;
> >
> >
> >
> > @@ -854,22 +853,15 @@ InitUSBKeyboard (
> > }
> >
> >}
> >
> >
> >
> > - UsbGetProtocolRequest (
> >
> > -UsbKeyboardDevice->UsbIo,
> >
> > -UsbKeyboardDevice->InterfaceDescriptor.InterfaceNumber,
> >
> > -&Protocol
> >
> > -);
> >
> >//
> >
> >// Set boot protocol for the USB Keyboard.
> >
> >// This driver only supports boot protocol.
> >
> >//
> >
> > - if (Protocol != BOOT_PROTOCOL) {
> >
> > -UsbSetProtocolRequest (
> >
> > - UsbKeyboardDevice->UsbIo,
> >
> > - UsbKeyboardDevice->InterfaceDescriptor.InterfaceNumber,
> >
> > - BOOT_PROTOCOL
> >
> > - );
> >
> > - }
> >
> > + UsbSetProtocolRequest (
> >
> > +UsbKeyboardDevice->UsbIo,
> >
> > +UsbKeyboardDevice->InterfaceDescriptor.InterfaceNumber,
> >
> > +BOOT_PROTOCOL
> >
> > +);
> >
> >
> >
> >UsbKeyboardDevice->CtrlOn= FALSE;
> >
> >UsbKeyboardDevice->AltOn = FALSE;
> >
> > --
> > 2.32.0
>
>
>
>
>
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[edk2-devel] [PATCH v2] MdeModulePkg: Add a check for metadata size in NvmExpress Driver
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3856
Currently this NvmeExpress Driver do not support metadata handling.
According to the NVME specs, metadata may be transferred to the host after
the logical block data. It can overrun the input buffer which may only
be the size of logical block data.
Add a check to return not support for the namespaces formatted with
metadata.
v2 changes:
- Change debug log level from INFO to ERROR
- Change to if (NamespaceData->LbaFormat[LbaFmtIdx].Ms != 0)
v1: https://edk2.groups.io/g/devel/message/87242
Cc: Jian J Wang
Cc: Liming Gao
Cc: Hao A Wu
Cc: Ray Ni
Signed-off-by: Hua Ma
---
MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c | 15 +++
.../Bus/Pci/NvmExpressPei/NvmExpressPei.c | 15 +++
2 files changed, 30 insertions(+)
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c
b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c
index 5a1eda8e8d..388583e4d5 100644
--- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c
+++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c
@@ -139,6 +139,21 @@ EnumerateNvmeDevNamespace (
Flbas = NamespaceData->Flbas;
LbaFmtIdx = Flbas & 0xF;
+
+//
+// Currently this NVME driver only suport Metadata Size == 0
+//
+if (NamespaceData->LbaFormat[LbaFmtIdx].Ms != 0) {
+ DEBUG ((
+DEBUG_ERROR,
+"NVME IDENTIFY NAMESPACE [%d] Ms(%d) is not supported.\n",
+NamespaceId,
+NamespaceData->LbaFormat[LbaFmtIdx].Ms
+));
+ Status = EFI_UNSUPPORTED;
+ goto Exit;
+}
+
Lbads = NamespaceData->LbaFormat[LbaFmtIdx].Lbads;
Device->Media.BlockSize = (UINT32)1 << Lbads;
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.c
b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.c
index f73053fc3f..e8a29f23c7 100644
--- a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.c
+++ b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.c
@@ -104,6 +104,21 @@ EnumerateNvmeDevNamespace (
//
Flbas = NamespaceData->Flbas;
LbaFmtIdx = Flbas & 0xF;
+
+ //
+ // Currently this NVME driver only suport Metadata Size == 0
+ //
+ if (NamespaceData->LbaFormat[LbaFmtIdx].Ms != 0) {
+DEBUG ((
+ DEBUG_ERROR,
+ "NVME IDENTIFY NAMESPACE [%d] Ms(%d) is not supported.\n",
+ NamespaceId,
+ NamespaceData->LbaFormat[LbaFmtIdx].Ms
+ ));
+Status = EFI_UNSUPPORTED;
+goto Exit;
+ }
+
Lbads = NamespaceData->LbaFormat[LbaFmtIdx].Lbads;
NamespaceInfo->Media.InterfaceType = MSG_NVME_NAMESPACE_DP;
--
2.32.0.windows.2
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Re: [edk2-devel] [PATCH v2] MdeModulePkg/NonDiscoverablePciDeviceDxe: Allow partial FreeBuffer
Any thoughts on this patch, now that the stable tag is out?
> -Original Message-
> From: Ni, Ray
> Sent: Tuesday, February 15, 2022 11:52 PM
> To: Sindhu, Deepthi
> Cc: Wu, Hao A ; Jeff Brasen ;
> devel@edk2.groups.io
> Subject: RE: [edk2-devel] [PATCH v2]
> MdeModulePkg/NonDiscoverablePciDeviceDxe: Allow partial FreeBuffer
>
> External email: Use caution opening links or attachments
>
>
> Deepthi,
> Can you please help to review the changes and provide comments?
>
> Thanks,
> Ray
>
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Jeff
> Brasen via groups.io
> Sent: Tuesday, February 15, 2022 2:46 AM
> To: devel@edk2.groups.io
> Cc: Wu, Hao A ; Ni, Ray ; Jeff
> Brasen
> Subject: [edk2-devel] [PATCH v2]
> MdeModulePkg/NonDiscoverablePciDeviceDxe: Allow partial FreeBuffer
>
> Add support for partial free of non cached buffers.
> If a request for less than the full size is requested new allocations for the
> remaining head and tail of the buffer are added to the list.
> Added verification that Buffer is EFI_PAGE_SIZE aligned.
> The XHCI driver does this if the page size for the controller is >4KB.
>
> Signed-off-by: Jeff Brasen
> ---
> .../NonDiscoverablePciDeviceIo.c | 53 ++-
> 1 file changed, 51 insertions(+), 2 deletions(-)
>
> diff --git
> a/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverable
> PciDeviceIo.c
> b/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverable
> PciDeviceIo.c
> index c1c5c6267c..77809cfedf 100644
> ---
> a/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverable
> PciDeviceIo.c
> +++
> b/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverable
> Pc
> +++ iDeviceIo.c
> @@ -960,12 +960,23 @@ NonCoherentPciIoFreeBuffer (
>LIST_ENTRY *Entry;
>EFI_STATUS Status;
>NON_DISCOVERABLE_DEVICE_UNCACHED_ALLOCATION *Alloc;
> + NON_DISCOVERABLE_DEVICE_UNCACHED_ALLOCATION *AllocHead;
> + NON_DISCOVERABLE_DEVICE_UNCACHED_ALLOCATION *AllocTail;
>BOOLEAN Found;
> + UINTNStartPages;
> + UINTNEndPages;
> +
> + if (HostAddress != ALIGN_POINTER (HostAddress, EFI_PAGE_SIZE)) {
> +ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
> +return EFI_INVALID_PARAMETER;
> + }
>
>Dev = NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO (This);
>
>Found = FALSE;
>Alloc = NULL;
> + AllocHead = NULL;
> + AllocTail = NULL;
>
>//
>// Find the uncached allocation list entry associated @@ -976,9 +987,13 @@
> NonCoherentPciIoFreeBuffer (
> Entry = Entry->ForwardLink)
>{
> Alloc = BASE_CR (Entry,
> NON_DISCOVERABLE_DEVICE_UNCACHED_ALLOCATION, List);
> -if ((Alloc->HostAddress == HostAddress) && (Alloc->NumPages == Pages))
> {
> +StartPages = 0;
> +if (Alloc->HostAddress < HostAddress) {
> + StartPages = (HostAddress - Alloc->HostAddress) / EFI_PAGE_SIZE;
> +}
> +if ((Alloc->HostAddress <= HostAddress) && (Alloc->NumPages >=
> + (Pages + StartPages))) {
>//
> - // We are freeing the exact allocation we were given
> + // We are freeing at least part of what we were given
>// before by AllocateBuffer()
>//
>Found = TRUE;
> @@ -991,7 +1006,41 @@ NonCoherentPciIoFreeBuffer (
> return EFI_NOT_FOUND;
>}
>
> + EndPages = Alloc->NumPages - (Pages + StartPages);
> +
> + if (StartPages != 0) {
> +AllocHead = AllocatePool (sizeof *AllocHead);
> +if (AllocHead == NULL) {
> + return EFI_OUT_OF_RESOURCES;
> +}
> +
> +AllocHead->HostAddress = Alloc->HostAddress;
> +AllocHead->NumPages = StartPages;
> +AllocHead->Attributes = Alloc->Attributes; }
> +
> + if (EndPages != 0) {
> +AllocTail = AllocatePool (sizeof *AllocTail);
> +if (AllocTail == NULL) {
> + return EFI_OUT_OF_RESOURCES;
> +}
> +
> +AllocTail->HostAddress = Alloc->HostAddress + ((Pages + StartPages) *
> EFI_PAGE_SIZE);
> +AllocTail->NumPages = EndPages;
> +AllocTail->Attributes = Alloc->Attributes; }
> +
>RemoveEntryList (&Alloc->List);
> + //
> + // Record this new sub allocations in the linked list, so we // can
> + restore the memory space attributes later // if (AllocHead != NULL)
> + {
> +InsertHeadList (&Dev->UncachedAllocationList, &AllocHead->List); }
> + if (AllocTail != NULL) {
> +InsertHeadList (&Dev->UncachedAllocationList, &AllocTail->List); }
>
>Status = gDS->SetMemorySpaceAttributes (
>(EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress,
> --
> 2.17.1
>
>
>
>
>
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[edk2-devel] [PATCH v1 0/1] MdeModulePkg:Avoid Xhc cross 64K boundary
The current xhc implementation may exceed the 64K boundary, so must restrictions need to be added. Cc: Ray Ni Cc: Liming Gao Cc: Wang Jian J Reviewed-by: Wu Hao A Signed-off-by: Cheng Zhou zhoucheng (1): MdeModulePkg:Avoid Xhc cross 64K boundary MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 6 ++ 1 file changed, 6 insertions(+) -- 2.17.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87247): https://edk2.groups.io/g/devel/message/87247 Mute This Topic: https://groups.io/mt/89518746/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v1 1/1] MdeModulePkg:Avoid Xhc cross 64K boundary
The current xhc implementation may exceed the 64K boundary,
so must restrictions need to be added.
Cc: Ray Ni
Cc: Liming Gao
Cc: Wang Jian J
Reviewed-by: Wu Hao A
Signed-off-by: Cheng Zhou
---
MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
index c2906e06fd84..0fedc8cfced5 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
@@ -891,8 +891,14 @@ CreateTransferRing (
VOID *Buf;
LINK_TRB *EndTrb;
EFI_PHYSICAL_ADDRESS PhyAddr;
+ VOID *NewBuf;
Buf = UsbHcAllocateMem (Xhc->MemPool, sizeof (TRB_TEMPLATE) * TrbNum);
+ ifUINTN)Buf & ((1<<16)-1)) + sizeof (TRB_TEMPLATE) * TrbNum) & (1<<16)) {
+NewBuf = UsbHcAllocateMem (Xhc->MemPool,sizeof(TRB_TEMPLATE) * TrbNum);
+UsbHcFreeMem(Xhc->MemPool,Buf,sizeof(TRB_TEMPLATE)*TrbNum);
+Buf = NewBuf;
+ }
ASSERT (Buf != NULL);
ASSERT (((UINTN)Buf & 0x3F) == 0);
ZeroMem (Buf, sizeof (TRB_TEMPLATE) * TrbNum);
--
2.17.1
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Re: [edk2-devel] [PATCH V7 26/37] MdeModulePkg: Add PcdTdxSharedBitMask
Hi Min, Similar to patch 25, I don't see the needs to make this PCD dynamic only. Do you have any strong reasons? If not sure, maybe it'd be better to put it under following section. [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] Regards, Jian > -Original Message- > From: Xu, Min M > Sent: Monday, February 28, 2022 3:21 PM > To: devel@edk2.groups.io > Cc: Xu, Min M ; Wang, Jian J ; > Wu, Hao A ; Brijesh Singh ; > Aktas, Erdem ; James Bottomley > ; Yao, Jiewen ; Tom Lendacky > ; Gerd Hoffmann > Subject: [PATCH V7 26/37] MdeModulePkg: Add PcdTdxSharedBitMask > > RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429 > > Guest Physical Address (GPA) space in Td guest is divided into private > and shared sub-spaces, determined by the SHARED bit of GPA. This PCD > holds the shared bit mask. Its default value is 0 and it will be set > in PlatformPei driver if it is of Td guest. > > Cc: Jian J Wang > Cc: Hao A Wu > Cc: Brijesh Singh > Cc: Erdem Aktas > Cc: James Bottomley > Cc: Jiewen Yao > Cc: Tom Lendacky > Cc: Gerd Hoffmann > Acked-by: Gerd Hoffmann > Signed-off-by: Min Xu > --- > MdeModulePkg/MdeModulePkg.dec | 4 > 1 file changed, 4 insertions(+) > > diff --git a/MdeModulePkg/MdeModulePkg.dec > b/MdeModulePkg/MdeModulePkg.dec > index 453f2a74b11d..e90a7f38708c 100644 > --- a/MdeModulePkg/MdeModulePkg.dec > +++ b/MdeModulePkg/MdeModulePkg.dec > @@ -2143,6 +2143,10 @@ ># @Prompt The flag which indicates if IA32_EFER is allowed to be changed. > > gEfiMdeModulePkgTokenSpaceGuid.PcdIa32EferChangeAllowed|TRUE|BOOLEA > N|0x00030009 > > + ## This PCD holds the shared bit mask for page table entries when Tdx is > enabled. > + # @Prompt The shared bit mask when Intel Tdx is enabled. > + > gEfiMdeModulePkgTokenSpaceGuid.PcdTdxSharedBitMask|0x0|UINT64|0x000 > 3000a > + > [PcdsDynamicEx] >## This dynamic PCD enables the default variable setting. ># Its value is the default store ID value. The default value is zero as > Standard > default. > -- > 2.29.2.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87245): https://edk2.groups.io/g/devel/message/87245 Mute This Topic: https://groups.io/mt/89446176/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH V7 25/37] MdeModulePkg: EFER should not be changed in TDX
Hi Min,
I think the PCD should not be dynamic. Dynamic PCD is used for those features
which can be changed at boot time. But, for Intel processor, it should always
stay as FALSE. So there's no need to make it dynamic. FixedAtBuild should be
fine.
Regards,
Jian
> -Original Message-
> From: Xu, Min M
> Sent: Monday, February 28, 2022 3:21 PM
> To: devel@edk2.groups.io
> Cc: Xu, Min M ; Wang, Jian J ;
> Wu, Hao A ; Brijesh Singh ;
> Aktas, Erdem ; James Bottomley
> ; Yao, Jiewen ; Tom Lendacky
> ; Gerd Hoffmann
> Subject: [PATCH V7 25/37] MdeModulePkg: EFER should not be changed in TDX
>
> RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
>
> In TDX IA32_ERER is RO to host VMM. It could not be changed.
> PcdIa32EferChangeAllowed is added in MdeModulePkg.dec and it is
> to be set to FALSE in Tdx guest.
>
> Cc: Jian J Wang
> Cc: Hao A Wu
> Cc: Brijesh Singh
> Cc: Erdem Aktas
> Cc: James Bottomley
> Cc: Jiewen Yao
> Cc: Tom Lendacky
> Cc: Gerd Hoffmann
> Acked-by: Gerd Hoffmann
> Signed-off-by: Min Xu
> ---
> MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 1 +
> MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 7 +++
> MdeModulePkg/MdeModulePkg.dec| 5 +
> 3 files changed, 13 insertions(+)
>
> diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> index 19b8a4c8aefa..106b679b6bd0 100644
> --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> @@ -117,6 +117,7 @@
>gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ##
> SOMETIMES_CONSUMES
>gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase##
> CONSUMES
>gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize##
> CONSUMES
> + gEfiMdeModulePkgTokenSpaceGuid.PcdIa32EferChangeAllowed ##
> CONSUMES
>
> [Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64]
>gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack ##
> SOMETIMES_CONSUMES
> diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> index 0700f310b203..5c647c74e773 100644
> --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> @@ -159,6 +159,13 @@ IsEnableNonExecNeeded (
> return FALSE;
>}
>
> + //
> + // Intel TDX sets this flag to FALSE.
> + //
> + if (!PcdGetBool (PcdIa32EferChangeAllowed)) {
> +return FALSE;
> + }
> +
>//
>// XD flag (BIT63) in page table entry is only valid if IA32_EFER.NXE is
> set.
>// Features controlled by Following PCDs need this feature to be enabled.
> diff --git a/MdeModulePkg/MdeModulePkg.dec
> b/MdeModulePkg/MdeModulePkg.dec
> index 463e889e9a68..453f2a74b11d 100644
> --- a/MdeModulePkg/MdeModulePkg.dec
> +++ b/MdeModulePkg/MdeModulePkg.dec
> @@ -2138,6 +2138,11 @@
># @Prompt GHCB Pool Size
>gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0|UINT64|0x00030008
>
> + ## This dynamic PCD indicates if IA32_EFER can be changed. The default
> value
> is TRUE but in
> + # Intel TDX change of IA32_EFER is not allowed.
> + # @Prompt The flag which indicates if IA32_EFER is allowed to be changed.
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdIa32EferChangeAllowed|TRUE|BOOLEA
> N|0x00030009
> +
> [PcdsDynamicEx]
>## This dynamic PCD enables the default variable setting.
># Its value is the default store ID value. The default value is zero as
> Standard
> default.
> --
> 2.29.2.windows.2
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Re: [edk2-devel] [PATCH v1] MdeModulePkg: Add a check for metadata size in NvmExpress Driver
Thanks for the patch, a couple of inline comments below:
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Ma, Hua
> Sent: Thursday, March 3, 2022 10:06 AM
> To: devel@edk2.groups.io
> Cc: Wang, Jian J ; Gao, Liming
> ; Wu, Hao A ; Ni, Ray
> ; Ma, Hua
> Subject: [edk2-devel] [PATCH v1] MdeModulePkg: Add a check for metadata
> size in NvmExpress Driver
>
> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3856
>
> Currently this NvmeExpress Driver do not support metadata handling.
> According to the NVME specs, metadata may be transferred to the host after
> the logical block data. It can overrun the input buffer which may only be the
> size of logical block data.
>
> Add a check to return not support for the namespaces formatted with
> metadata.
>
> Cc: Jian J Wang
> Cc: Liming Gao
> Cc: Hao A Wu
> Cc: Ray Ni
>
> Signed-off-by: Hua Ma
> ---
> MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c | 15
> +++
> .../Bus/Pci/NvmExpressPei/NvmExpressPei.c | 15 +++
> 2 files changed, 30 insertions(+)
>
> diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c
> b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c
> index 5a1eda8e8d..46b7dcba20 100644
> --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c
> +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c
> @@ -139,6 +139,21 @@ EnumerateNvmeDevNamespace (
>
> Flbas = NamespaceData->Flbas;
> LbaFmtIdx = Flbas & 0xF;
> +
> +//
> +// Currently this NVME driver only suport Metadata Size == 0
> +//
> +if (NamespaceData->LbaFormat[LbaFmtIdx].Ms) {
1. Please help to update to:
if (NamespaceData->LbaFormat[LbaFmtIdx].Ms != 0) {
(Similar comment applies to NvmExpressPei)
> + DEBUG ((
> +DEBUG_INFO,
2. My preference is to use DEBUG_ERROR level here. Could you help to update
debug output level?
(Similar comment applies to NvmExpressPei)
Best Regards,
Hao Wu
> +"NVME IDENTIFY NAMESPACE [%d] Ms(%d) is not supported.\n",
> +NamespaceId,
> +NamespaceData->LbaFormat[LbaFmtIdx].Ms
> +));
> + Status = EFI_UNSUPPORTED;
> + goto Exit;
> +}
> +
> Lbads = NamespaceData->LbaFormat[LbaFmtIdx].Lbads;
> Device->Media.BlockSize = (UINT32)1 << Lbads;
>
> diff --git a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.c
> b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.c
> index f73053fc3f..6e27950648 100644
> --- a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.c
> +++ b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.c
> @@ -104,6 +104,21 @@ EnumerateNvmeDevNamespace (
>//
>Flbas = NamespaceData->Flbas;
>LbaFmtIdx = Flbas & 0xF;
> +
> + //
> + // Currently this NVME driver only suport Metadata Size == 0 // if
> + (NamespaceData->LbaFormat[LbaFmtIdx].Ms) {
> +DEBUG ((
> + DEBUG_INFO,
> + "NVME IDENTIFY NAMESPACE [%d] Ms(%d) is not supported.\n",
> + NamespaceId,
> + NamespaceData->LbaFormat[LbaFmtIdx].Ms
> + ));
> +Status = EFI_UNSUPPORTED;
> +goto Exit;
> + }
> +
>Lbads = NamespaceData->LbaFormat[LbaFmtIdx].Lbads;
>
>NamespaceInfo->Media.InterfaceType = MSG_NVME_NAMESPACE_DP;
> --
> 2.32.0.windows.2
>
>
>
>
>
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[edk2-devel] [PATCH v1] MdeModulePkg: Add a check for metadata size in NvmExpress Driver
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3856
Currently this NvmeExpress Driver do not support metadata handling.
According to the NVME specs, metadata may be transferred to the host after
the logical block data. It can overrun the input buffer which may only
be the size of logical block data.
Add a check to return not support for the namespaces formatted with
metadata.
Cc: Jian J Wang
Cc: Liming Gao
Cc: Hao A Wu
Cc: Ray Ni
Signed-off-by: Hua Ma
---
MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c | 15 +++
.../Bus/Pci/NvmExpressPei/NvmExpressPei.c | 15 +++
2 files changed, 30 insertions(+)
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c
b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c
index 5a1eda8e8d..46b7dcba20 100644
--- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c
+++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c
@@ -139,6 +139,21 @@ EnumerateNvmeDevNamespace (
Flbas = NamespaceData->Flbas;
LbaFmtIdx = Flbas & 0xF;
+
+//
+// Currently this NVME driver only suport Metadata Size == 0
+//
+if (NamespaceData->LbaFormat[LbaFmtIdx].Ms) {
+ DEBUG ((
+DEBUG_INFO,
+"NVME IDENTIFY NAMESPACE [%d] Ms(%d) is not supported.\n",
+NamespaceId,
+NamespaceData->LbaFormat[LbaFmtIdx].Ms
+));
+ Status = EFI_UNSUPPORTED;
+ goto Exit;
+}
+
Lbads = NamespaceData->LbaFormat[LbaFmtIdx].Lbads;
Device->Media.BlockSize = (UINT32)1 << Lbads;
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.c
b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.c
index f73053fc3f..6e27950648 100644
--- a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.c
+++ b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.c
@@ -104,6 +104,21 @@ EnumerateNvmeDevNamespace (
//
Flbas = NamespaceData->Flbas;
LbaFmtIdx = Flbas & 0xF;
+
+ //
+ // Currently this NVME driver only suport Metadata Size == 0
+ //
+ if (NamespaceData->LbaFormat[LbaFmtIdx].Ms) {
+DEBUG ((
+ DEBUG_INFO,
+ "NVME IDENTIFY NAMESPACE [%d] Ms(%d) is not supported.\n",
+ NamespaceId,
+ NamespaceData->LbaFormat[LbaFmtIdx].Ms
+ ));
+Status = EFI_UNSUPPORTED;
+goto Exit;
+ }
+
Lbads = NamespaceData->LbaFormat[LbaFmtIdx].Lbads;
NamespaceInfo->Media.InterfaceType = MSG_NVME_NAMESPACE_DP;
--
2.32.0.windows.2
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Re: [edk2-devel] [PATCH edk2-platforms v2 1/1] Platform/VExpressPkg: Avoid overriding defines
Hi Patrik, Thank you for this patch. These changes look good to me. Reviewed-by: Sami Mujawar Regards, Sami Mujawar On 28/02/2022 05:57 PM, patrik.bergl...@arm.com wrote: From: Patrik Berglund The definition of macros (e.g. SECURE_BOOT_ENABLE and others) in ArmVExpress.dsc.inc overrides the setting configured in the platform DSC file, thereby preventing the configurations from being enabled. Therefore, add checks to only define the macros if not already defined in the platform DSC file. Signed-off-by: Patrik Berglund --- Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc | 14 +- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc b/Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc index d6f31ecda42f..c75efe0ccf0a 100644 --- a/Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc +++ b/Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc @@ -1,21 +1,33 @@ # -# Copyright (c) 2011-2020, Arm Limited. All rights reserved. +# Copyright (c) 2011-2022, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # # [Defines] +!ifndef SECURE_BOOT_ENABLE SECURE_BOOT_ENABLE= FALSE +!endif +!ifndef INCLUDE_TFTP_COMMAND INCLUDE_TFTP_COMMAND = TRUE +!endif # # Network definition # +!ifndef NETWORK_SNP_ENABLE DEFINE NETWORK_SNP_ENABLE = FALSE +!endif +!ifndef NETWORK_IP6_ENABLE DEFINE NETWORK_IP6_ENABLE = FALSE +!endif +!ifndef NETWORK_TLS_ENABLE DEFINE NETWORK_TLS_ENABLE = FALSE +!endif +!ifndef NETWORK_HTTP_BOOT_ENABLE DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE +!endif [BuildOptions.common] *_*_*_CC_FLAGS = -DDISABLE_NEW_DEPRECATED_INTERFACES IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87241): https://edk2.groups.io/g/devel/message/87241 Mute This Topic: https://groups.io/mt/89456767/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v1 7/7] UefiPayloadPkg: Invoke GetPhysicalAddressBits() and remove the duplicated code
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3394
Invoke GetPhysicalAddressBits() defined in UefiCpuPkg for CPU physical address
mask calculation and remove the duplicated code in
UefiPayloadPkg\UefiPayloadEntry
Cc: Guo Dong
Cc: Ray Ni
Signed-off-by: Yu Pu
---
UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c | 10 ++
UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c | 9 ++---
2 files changed, 4 insertions(+), 15 deletions(-)
diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c
b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c
index 0fed1e36918a..4378aa4f1d97 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c
@@ -4,6 +4,7 @@
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
+#include
#include "UefiPayloadEntry.h"
@@ -341,7 +342,6 @@ BuildGenericHob (
VOID
)
{
- UINT32 RegEax;
UINT8PhysicalAddressBits;
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
@@ -351,13 +351,7 @@ BuildGenericHob (
//
// Build CPU memory space and IO space hob
//
- AsmCpuid (0x8000, &RegEax, NULL, NULL, NULL);
- if (RegEax >= 0x8008) {
-AsmCpuid (0x8008, &RegEax, NULL, NULL, NULL);
-PhysicalAddressBits = (UINT8)RegEax;
- } else {
-PhysicalAddressBits = 36;
- }
+ PhysicalAddressBits = GetPhysicalAddressBits(NULL, NULL);
BuildCpuHob (PhysicalAddressBits, 16);
diff --git a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
index ac0d58e685c8..c61aeeda7f2e 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
@@ -25,6 +25,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include
#include
#include
+#include
#include
#include
#include
@@ -738,13 +739,7 @@ CreateIdentityMappingPageTables (
if (Hob != NULL) {
PhysicalAddressBits = ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;
} else {
-AsmCpuid (0x8000, &RegEax, NULL, NULL, NULL);
-if (RegEax >= 0x8008) {
- AsmCpuid (0x8008, &RegEax, NULL, NULL, NULL);
- PhysicalAddressBits = (UINT8)RegEax;
-} else {
- PhysicalAddressBits = 36;
-}
+PhysicalAddressBits = GetPhysicalAddressBits (NULL, NULL);
}
//
--
2.30.0.windows.2
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[edk2-devel] [PATCH v1 6/7] EmulatorPkg: fixed a bug caused by Invoking GetPhysicalAddressBits()
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3394 add the defination of UefiCpuLib in EmulatorPkg\EmulatorPkg.dsc Cc: Andrew Fish Cc: Ray Ni Signed-off-by: Yu Pu --- EmulatorPkg/EmulatorPkg.dsc | 1 + 1 file changed, 1 insertion(+) diff --git a/EmulatorPkg/EmulatorPkg.dsc b/EmulatorPkg/EmulatorPkg.dsc index 554c13ddb500..e33b98a4b682 100644 --- a/EmulatorPkg/EmulatorPkg.dsc +++ b/EmulatorPkg/EmulatorPkg.dsc @@ -78,6 +78,7 @@ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf + UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf -- 2.30.0.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87239): https://edk2.groups.io/g/devel/message/87239 Mute This Topic: https://groups.io/mt/89503329/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v1 3/7] IntelFsp2Pkg: Invoke GetPhysicalAddressBits() and remove the duplicated code
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3394
Invoke GetPhysicalAddressBits() defined in UefiCpuPkg for CPU
physical address mask calculation and remove the duplicated
code in edk2\IntelFsp2Pkg\Library\BaseCacheLib\CacheLib.c.
Cc: Chasel Chiu
Signed-off-by: Yu Pu
---
IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c | 10 ++
IntelFsp2Pkg/Library/BaseCacheLib/BaseCacheLib.inf | 2 ++
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c
b/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c
index f879c268e7ec..3f8ed122b2be 100644
--- a/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c
+++ b/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include "CacheLibInternal.h"
/**
@@ -388,15 +389,8 @@ SetCacheAttributes (
UINT32 UsedMsrNum;
EFI_MEMORY_CACHE_TYPE UsedMemoryCacheType;
UINT64 ValidMtrrAddressMask;
- UINT32 Cpuid_RegEax;
- AsmCpuid (CPUID_EXTENDED_FUNCTION, &Cpuid_RegEax, NULL, NULL, NULL);
- if (Cpuid_RegEax >= CPUID_VIR_PHY_ADDRESS_SIZE) {
-AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Cpuid_RegEax, NULL, NULL, NULL);
-ValidMtrrAddressMask = (LShiftU64 ((UINT64)1, (Cpuid_RegEax & 0xFF)) - 1)
& (~(UINT64)0x0FFF);
- } else {
-ValidMtrrAddressMask = (LShiftU64 ((UINT64)1, 36) - 1) & (~(UINT64)0x0FFF);
- }
+ GetPhysicalAddressBits(NULL, &ValidMtrrAddressMask);
//
// Check for invalid parameter
diff --git a/IntelFsp2Pkg/Library/BaseCacheLib/BaseCacheLib.inf
b/IntelFsp2Pkg/Library/BaseCacheLib/BaseCacheLib.inf
index 9a513fb6df77..e6b14ae4a802 100644
--- a/IntelFsp2Pkg/Library/BaseCacheLib/BaseCacheLib.inf
+++ b/IntelFsp2Pkg/Library/BaseCacheLib/BaseCacheLib.inf
@@ -21,9 +21,11 @@
[Packages]
MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
IntelFsp2Pkg/IntelFsp2Pkg.dec
[LibraryClasses]
BaseMemoryLib
CacheAsRamLib
+ UefiCpuLib
--
2.30.0.windows.2
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[edk2-devel] [PATCH v1 4/7] StandaloneMmPkg: Invoke GetPhysicalAddressBits() and remove the duplicated code
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3394
Invoke GetPhysicalAddressBits() defined in UefiCpuPkg for CPU physical address
mask calculation and remove the duplicated code in
StandaloneMmPkg\Library\StandaloneMmMemLib\X86StandaloneMmMemLibInternal.c
Cc: Ard Biesheuvel
Cc: Sami Mujawar
Cc: Jiewen Yao
Signed-off-by: Yu Pu
---
StandaloneMmPkg/Library/StandaloneMmMemLib/X86StandaloneMmMemLibInternal.c |
10 ++
StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.inf |
2 ++
StandaloneMmPkg/StandaloneMmPkg.dsc|
1 +
3 files changed, 5 insertions(+), 8 deletions(-)
diff --git
a/StandaloneMmPkg/Library/StandaloneMmMemLib/X86StandaloneMmMemLibInternal.c
b/StandaloneMmPkg/Library/StandaloneMmMemLib/X86StandaloneMmMemLibInternal.c
index c309d1bc6a56..4afd9b938934 100644
--- a/StandaloneMmPkg/Library/StandaloneMmMemLib/X86StandaloneMmMemLibInternal.c
+++ b/StandaloneMmPkg/Library/StandaloneMmMemLib/X86StandaloneMmMemLibInternal.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
#include
#include
@@ -40,7 +41,6 @@ MmMemLibInternalCalculateMaximumSupportAddress (
)
{
VOID*Hob;
- UINT32 RegEax;
UINT8 PhysicalAddressBits;
//
@@ -50,13 +50,7 @@ MmMemLibInternalCalculateMaximumSupportAddress (
if (Hob != NULL) {
PhysicalAddressBits = ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;
} else {
-AsmCpuid (0x8000, &RegEax, NULL, NULL, NULL);
-if (RegEax >= 0x8008) {
- AsmCpuid (0x8008, &RegEax, NULL, NULL, NULL);
- PhysicalAddressBits = (UINT8)RegEax;
-} else {
- PhysicalAddressBits = 36;
-}
+PhysicalAddressBits = GetPhysicalAddressBits (NULL, NULL);
}
//
diff --git a/StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.inf
b/StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.inf
index b29d97a74607..94f7fbb1c4f7 100644
--- a/StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.inf
+++ b/StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.inf
@@ -43,12 +43,14 @@
[Packages]
MdePkg/MdePkg.dec
StandaloneMmPkg/StandaloneMmPkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
[LibraryClasses]
BaseMemoryLib
DebugLib
HobLib
MemoryAllocationLib
+ UefiCpuLib
[Guids]
gMmCoreDataHobGuid ## SOMETIMES_CONSUMES ## HOB
diff --git a/StandaloneMmPkg/StandaloneMmPkg.dsc
b/StandaloneMmPkg/StandaloneMmPkg.dsc
index 8012f93b7dcc..41449046799f 100644
--- a/StandaloneMmPkg/StandaloneMmPkg.dsc
+++ b/StandaloneMmPkg/StandaloneMmPkg.dsc
@@ -59,6 +59,7 @@
StandaloneMmCoreEntryPoint|StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
StandaloneMmDriverEntryPoint|MdePkg/Library/StandaloneMmDriverEntryPoint/StandaloneMmDriverEntryPoint.inf
VariableMmDependency|StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependency.inf
+ UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
[LibraryClasses.AARCH64, LibraryClasses.ARM]
ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
--
2.30.0.windows.2
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[edk2-devel] [PATCH v1 5/7] OvmfPkg: Invoke GetPhysicalAddressBits() and remove the duplicated code
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3394
Invoke GetPhysicalAddressBits() defined in UefiCpuPkg for CPU physical address
mask calculation and remove the duplicated code in
OvmfPkg\XenPlatformPei\MemDetect.c.
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Signed-off-by: Yu Pu
---
OvmfPkg/XenPlatformPei/MemDetect.c | 11 ++-
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/OvmfPkg/XenPlatformPei/MemDetect.c
b/OvmfPkg/XenPlatformPei/MemDetect.c
index d412d1f4db6f..bd24612c21ef 100644
--- a/OvmfPkg/XenPlatformPei/MemDetect.c
+++ b/OvmfPkg/XenPlatformPei/MemDetect.c
@@ -30,6 +30,7 @@ Module Name:
#include
#include
#include
+#include
#include "Platform.h"
#include "Cmos.h"
@@ -180,15 +181,7 @@ AddressWidthInitialization (
VOID
)
{
- UINT32 RegEax;
-
- AsmCpuid (0x8000, &RegEax, NULL, NULL, NULL);
- if (RegEax >= 0x8008) {
-AsmCpuid (0x8008, &RegEax, NULL, NULL, NULL);
-mPhysMemAddressWidth = (UINT8)RegEax;
- } else {
-mPhysMemAddressWidth = 36;
- }
+ mPhysMemAddressWidth = GetPhysicalAddressBits(NULL, NULL);
//
// IA-32e paging translates 48-bit linear addresses to 52-bit physical
addresses.
--
2.30.0.windows.2
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[edk2-devel] [PATCH v1 2/7] MdeModulePkg: Invoke GetPhysicalAddressBits() and remove the duplicated code
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3394
Invoke GetPhysicalAddressBits() defined in UefiCpuPkg for CPU physical address
mask calculation and remove the duplicated code in MdeModulePkg.
Cc: Jian J Wang
Cc: Liming Gao
Signed-off-by: Yu Pu
---
MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c|
9 ++---
MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c |
14 ++
MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c|
14 ++
MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf |
2 ++
MdeModulePkg/MdeModulePkg.dsc |
1 +
MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf |
2 ++
MdeModulePkg/Universal/CapsulePei/CapsuleX64.inf|
2 ++
7 files changed, 13 insertions(+), 31 deletions(-)
diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
index 0700f310b203..78e91e6e9024 100644
--- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
+++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
@@ -22,6 +22,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
+#include
#include
#include "DxeIpl.h"
#include "VirtualMemory.h"
@@ -733,13 +734,7 @@ CreateIdentityMappingPageTables (
if (Hob != NULL) {
PhysicalAddressBits = ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;
} else {
-AsmCpuid (0x8000, &RegEax, NULL, NULL, NULL);
-if (RegEax >= 0x8008) {
- AsmCpuid (0x8008, &RegEax, NULL, NULL, NULL);
- PhysicalAddressBits = (UINT8)RegEax;
-} else {
- PhysicalAddressBits = 36;
-}
+PhysicalAddressBits = GetPhysicalAddressBits(NULL, NULL);
}
Page5LevelSupport = FALSE;
diff --git
a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c
b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c
index 6b44f50bac70..367bf8cdd1e6 100644
--- a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c
+++ b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c
@@ -10,6 +10,7 @@ Copyright (c) 2017, AMD Incorporated. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
+#include
#include "ScriptExecute.h"
//
@@ -51,20 +52,9 @@ HookPageFaultHandler (
IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry
)
{
- UINT32 RegEax;
- UINT8 PhysicalAddressBits;
UINTN PageFaultHandlerHookAddress;
- AsmCpuid (0x8000, &RegEax, NULL, NULL, NULL);
- if (RegEax >= 0x8008) {
-AsmCpuid (0x8008, &RegEax, NULL, NULL, NULL);
-PhysicalAddressBits = (UINT8)RegEax;
- } else {
-PhysicalAddressBits = 36;
- }
-
- mPhyMask = LShiftU64 (1, PhysicalAddressBits) - 1;
- mPhyMask &= (1ull << 48) - SIZE_4KB;
+ GetPhysicalAddressBits(NULL, &mPhyMask);
//
// Set Page Fault entry to catch >4G access
diff --git a/MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c
b/MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c
index 05941f9f8d56..06d6129c5e6d 100644
--- a/MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c
+++ b/MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c
@@ -12,6 +12,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include
#include
#include
+#include
#include "CommonHeader.h"
#define EXCEPTION_VECTOR_NUMBER 0x22
@@ -61,20 +62,9 @@ HookPageFaultHandler (
IN OUT PAGE_FAULT_CONTEXT*PageFaultContext
)
{
- UINT32 RegEax;
- UINT8 PhysicalAddressBits;
UINTN PageFaultHandlerHookAddress;
- AsmCpuid (0x8000, &RegEax, NULL, NULL, NULL);
- if (RegEax >= 0x8008) {
-AsmCpuid (0x8008, &RegEax, NULL, NULL, NULL);
-PhysicalAddressBits = (UINT8)RegEax;
- } else {
-PhysicalAddressBits = 36;
- }
-
- PageFaultContext->PhyMask = LShiftU64 (1, PhysicalAddressBits) - 1;
- PageFaultContext->PhyMask &= (1ull << 48) - SIZE_4KB;
+ GetPhysicalAddressBits(NULL, &(PageFaultContext->PhyMask));
//
// Set Page Fault entry to catch >4G access
diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
index 19b8a4c8aefa..45808bcdcd6c 100644
--- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
@@ -55,6 +55,7 @@
[Packages]
MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
MdeModulePkg/MdeModulePkg.dec
[Packages.ARM, Packages.AARCH64]
@@ -75,6 +76,7 @@
DebugAgentLib
PeiServicesTablePointerLib
PerformanceLib
+ UefiCpuLib
[LibraryClasses.ARM, LibraryClasses.AARCH64]
ArmMmuLib
diff --git a/MdeModulePkg/MdeModulePkg.dsc b/MdeModulePkg/MdeModulePkg.dsc
index b1d83461865e..da6213c02da0 100644
--- a/MdeModulePkg/MdeModulePkg.dsc
+++ b/MdeModulePkg/MdeModulePkg.dsc
@@ -62,6 +62,7 @@
DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerL
[edk2-devel] [PATCH v1 0/7] *** SUBJECT HERE ***
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3394 Signed-off-by: Yu Pu *** BLURB HERE *** Yu Pu (7): UefiCpuPackage: Add APIs for CPU physical address mask calculation MdeModulePkg: Invoke GetPhysicalAddressBits() and remove the duplicated code IntelFsp2Pkg: Invoke GetPhysicalAddressBits() and remove the duplicated code StandaloneMmPkg: Invoke GetPhysicalAddressBits() and remove the duplicated code OvmfPkg: Invoke GetPhysicalAddressBits() and remove the duplicated code EmulatorPkg: fixed a bug caused by Invoking GetPhysicalAddressBits() UefiPayloadPkg: Invoke GetPhysicalAddressBits() and remove the duplicated code IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c| 10 + MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c| 9 +--- MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c | 14 +- MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c| 14 +- OvmfPkg/XenPlatformPei/MemDetect.c | 11 + StandaloneMmPkg/Library/StandaloneMmMemLib/X86StandaloneMmMemLibInternal.c | 10 + UefiCpuPkg/CpuDxe/CpuDxe.c | 16 +-- UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c | 47 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 9 +--- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 9 +--- UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 9 +--- UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c | 10 + UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c | 9 +--- EmulatorPkg/EmulatorPkg.dsc | 1 + IntelFsp2Pkg/Library/BaseCacheLib/BaseCacheLib.inf | 2 + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 2 + MdeModulePkg/MdeModulePkg.dsc | 1 + MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf | 2 + MdeModulePkg/Universal/CapsulePei/CapsuleX64.inf| 2 + StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.inf | 2 + StandaloneMmPkg/StandaloneMmPkg.dsc | 1 + UefiCpuPkg/Include/Library/UefiCpuLib.h | 17 +++ 22 files changed, 99 insertions(+), 108 deletions(-) -- 2.30.0.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87233): https://edk2.groups.io/g/devel/message/87233 Mute This Topic: https://groups.io/mt/89503323/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v1 1/7] UefiCpuPackage: Add APIs for CPU physical address mask calculation
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3394
Add API named GetPhysicalAddressBits() for CPU physical address mask
calculation, and remove the duplicated code in UefiCpuPackage.
Cc: Eric Dong
Cc: Ray Ni
Signed-off-by: Yu Pu
---
UefiCpuPkg/CpuDxe/CpuDxe.c | 16 +--
UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c | 47
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 9 +---
UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c| 9 +---
UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 9 +---
UefiCpuPkg/Include/Library/UefiCpuLib.h| 17 +++
6 files changed, 70 insertions(+), 37 deletions(-)
diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.c b/UefiCpuPkg/CpuDxe/CpuDxe.c
index 00f3cb09572c..8aca1bf72b4c 100644
--- a/UefiCpuPkg/CpuDxe/CpuDxe.c
+++ b/UefiCpuPkg/CpuDxe/CpuDxe.c
@@ -503,21 +503,7 @@ InitializeMtrrMask (
VOID
)
{
- UINT32 RegEax;
- UINT8 PhysicalAddressBits;
-
- AsmCpuid (0x8000, &RegEax, NULL, NULL, NULL);
-
- if (RegEax >= 0x8008) {
-AsmCpuid (0x8008, &RegEax, NULL, NULL, NULL);
-
-PhysicalAddressBits = (UINT8)RegEax;
- } else {
-PhysicalAddressBits = 36;
- }
-
- mValidMtrrBitsMask= LShiftU64 (1, PhysicalAddressBits) - 1;
- mValidMtrrAddressMask = mValidMtrrBitsMask & 0xf000ULL;
+ GetPhysicalAddressBits(&mValidMtrrBitsMask, &mValidMtrrAddressMask);
}
/**
diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c
b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c
index 5d925bc273f8..bb1343f3cd21 100644
--- a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c
+++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c
@@ -79,3 +79,50 @@ GetCpuSteppingId (
return (UINT8)Eax.Bits.SteppingId;
}
+
+/**
+ Get the physical address width supported by the processor.
+ @param[out] ValidAddressMask Bitmask with valid address bits set to
+one; other bits are clear. Optional
+parameter.
+ @param[out] ValidPageBaseAddressMask Bitmask with valid page base address
+bits set to one; other bits are clear.
+Optional parameter.
+ @return The physical address width supported by the processor.
+**/
+UINT8
+EFIAPI
+GetPhysicalAddressBits (
+ OUT UINT64 *ValidAddressMask OPTIONAL,
+ OUT UINT64 *ValidPageBaseAddressMask OPTIONAL
+ )
+{
+ UINT32 MaxExtendedFunction;
+ CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize;
+ UINT64 AddressMask;
+ UINT64 PageBaseAddressMask;
+
+ AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NULL);
+ if (MaxExtendedFunction >= CPUID_VIR_PHY_ADDRESS_SIZE) {
+AsmCpuid (
+ CPUID_VIR_PHY_ADDRESS_SIZE,
+ &VirPhyAddressSize.Uint32,
+ NULL,
+ NULL,
+ NULL
+ );
+ } else {
+VirPhyAddressSize.Bits.PhysicalAddressBits = 36;
+ }
+
+ AddressMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1;
+ PageBaseAddressMask = AddressMask & ~(UINT64)0xFFF;
+
+ if (ValidAddressMask != NULL) {
+*ValidAddressMask = AddressMask;
+ }
+ if (ValidPageBaseAddressMask != NULL) {
+*ValidPageBaseAddressMask = PageBaseAddressMask;
+ }
+ return (UINT8)VirPhyAddressSize.Bits.PhysicalAddressBits;
+}
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
index 4e8f897f5e9c..ec7cd4013132 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -330,13 +331,7 @@ SmmCpuFeaturesInstallSmiHandler (
if (Hob != NULL) {
Psd->PhysicalAddressBits = ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;
} else {
-AsmCpuid (0x8000, &RegEax, NULL, NULL, NULL);
-if (RegEax >= 0x8008) {
- AsmCpuid (0x8008, &RegEax, NULL, NULL, NULL);
- Psd->PhysicalAddressBits = (UINT8)RegEax;
-} else {
- Psd->PhysicalAddressBits = 36;
-}
+Psd->PhysicalAddressBits = GetPhysicalAddressBits (NULL, NULL);
}
if (!mStmConfigurationTableInitialized) {
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
index 538394f23910..de1385a86948 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
@@ -194,7 +194,6 @@ CalculateMaximumSupportAddress (
VOID
)
{
- UINT32 RegEax;
UINT8 PhysicalAddressBits;
VOID*Hob;
@@ -205,13 +204,7 @@ CalculateMaximumSupportAddress (
if (Hob != NULL) {
PhysicalAddressBits = ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;
} else {
-AsmCpuid (0x8000, &RegEax, NULL, NULL, NULL);
-if (RegEax >= 0x8008) {
- AsmCpuid (0x8008, &RegEax, NULL, NULL, NULL);
-
[edk2-devel] [PATCH v6 7/8] OvmfPkg: CloudHv: Rely on PVH memmap instead of CMOS
From: Sebastien Boeuf
Instead of using the CMOS, the CloudHv platform relies on the list of
memmap entries provided through the PVH boot protocol to determine the
last RAM address below 4G.
Acked-by: Gerd Hoffmann
Signed-off-by: Sebastien Boeuf
---
OvmfPkg/PlatformPei/MemDetect.c | 73 +
OvmfPkg/PlatformPei/PlatformPei.inf | 2 +
2 files changed, 75 insertions(+)
diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c
index 1bcb5a08bc..8ecc8257f9 100644
--- a/OvmfPkg/PlatformPei/MemDetect.c
+++ b/OvmfPkg/PlatformPei/MemDetect.c
@@ -17,6 +17,7 @@ Module Name:
#include
#include
#include
+#include
#include
#include
@@ -315,6 +316,73 @@ ScanOrAdd64BitE820Ram (
return EFI_SUCCESS;
}
+/**
+ Returns PVH memmap
+
+ @param Entries Pointer to PVH memmap
+ @param CountNumber of entries
+
+ @return EFI_STATUS
+**/
+EFI_STATUS
+GetPvhMemmapEntries (
+ struct hvm_memmap_table_entry **Entries,
+ UINT32 *Count
+ )
+{
+ UINT32 *PVHResetVectorData;
+ struct hvm_start_info *pvh_start_info;
+
+ PVHResetVectorData = (VOID *)(UINTN)PcdGet32 (PcdXenPvhStartOfDayStructPtr);
+ if (PVHResetVectorData == 0) {
+return EFI_NOT_FOUND;
+ }
+
+ pvh_start_info = (struct hvm_start_info *)(UINTN)PVHResetVectorData[0];
+
+ *Entries = (struct hvm_memmap_table_entry
*)(UINTN)pvh_start_info->memmap_paddr;
+ *Count = pvh_start_info->memmap_entries;
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+UINT64
+GetHighestSystemMemoryAddressFromPvhMemmap (
+ BOOLEAN Below4gb
+ )
+{
+ struct hvm_memmap_table_entry *Memmap;
+ UINT32 MemmapEntriesCount;
+ struct hvm_memmap_table_entry *Entry;
+ EFI_STATUS Status;
+ UINT32 Loop;
+ UINT64 HighestAddress;
+ UINT64 EntryEnd;
+
+ HighestAddress = 0;
+
+ Status = GetPvhMemmapEntries (&Memmap, &MemmapEntriesCount);
+ ASSERT_EFI_ERROR (Status);
+
+ for (Loop = 0; Loop < MemmapEntriesCount; Loop++) {
+Entry= Memmap + Loop;
+EntryEnd = Entry->addr + Entry->size;
+
+if ((Entry->type == XEN_HVM_MEMMAP_TYPE_RAM) &&
+(EntryEnd > HighestAddress))
+{
+ if (Below4gb && (EntryEnd <= BASE_4GB)) {
+HighestAddress = EntryEnd;
+ } else if (!Below4gb && (EntryEnd >= BASE_4GB)) {
+HighestAddress = EntryEnd;
+ }
+}
+ }
+
+ return HighestAddress;
+}
+
UINT32
GetSystemMemorySizeBelow4gb (
VOID
@@ -325,6 +393,11 @@ GetSystemMemorySizeBelow4gb (
UINT8 Cmos0x34;
UINT8 Cmos0x35;
+ if (mHostBridgeDevId == CLOUDHV_DEVICE_ID) {
+// Get the information from PVH memmap
+return (UINT32)GetHighestSystemMemoryAddressFromPvhMemmap (TRUE);
+ }
+
Status = ScanOrAdd64BitE820Ram (FALSE, &LowerMemorySize, NULL);
if ((Status == EFI_SUCCESS) && (LowerMemorySize > 0)) {
return (UINT32)LowerMemorySize;
diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf
b/OvmfPkg/PlatformPei/PlatformPei.inf
index 8ef404168c..212aa7b047 100644
--- a/OvmfPkg/PlatformPei/PlatformPei.inf
+++ b/OvmfPkg/PlatformPei/PlatformPei.inf
@@ -91,6 +91,8 @@
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd
gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes
gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase
+ gUefiOvmfPkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtr
+ gUefiOvmfPkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtrSize
gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
--
2.32.0
-
Intel Corporation SAS (French simplified joint stock company)
Registered headquarters: "Les Montalets"- 2, rue de Paris,
92196 Meudon Cedex, France
Registration Number: 302 456 199 R.C.S. NANTERRE
Capital: 4,572,000 Euros
This e-mail and any attachments may contain confidential material for
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by others is strictly prohibited. If you are not the intended
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[edk2-devel] [PATCH v6 8/8] OvmfPkg: CloudHv: Add README
From: Sebastien Boeuf Add some documentation to the CloudHv target in order to clarify how to use it and what to expect from it. Signed-off-by: Sebastien Boeuf --- OvmfPkg/CloudHv/README | 67 ++ 1 file changed, 67 insertions(+) create mode 100644 OvmfPkg/CloudHv/README diff --git a/OvmfPkg/CloudHv/README b/OvmfPkg/CloudHv/README new file mode 100644 index 00..63e28860e0 --- /dev/null +++ b/OvmfPkg/CloudHv/README @@ -0,0 +1,67 @@ + +CloudHv is a port of OVMF for the Cloud Hypervisor project. + +The Cloud Hypervisor project + + +Cloud Hypervisor is a Virtual Machine Monitor that runs on top of KVM. The +project focuses on exclusively running modern, cloud workloads, on top of a +limited set of hardware architectures and platforms. Cloud workloads refers to +those that are usually run by customers inside a cloud provider. This means +modern operating systems with most I/O handled by paravirtualised devices +(i.e. virtio), no requirement for legacy devices, and 64-bit CPUs. + +https://github.com/cloud-hypervisor/cloud-hypervisor + +Design +-- + +Based on Cloud Hypervisor's motto to reduce the emulation as much as possible, +the project logically decided to support the PVH boot specification as the only +way of booting virtual machines. That includes both direct kernel boot and OVMF +firmware which must be generated as PVH ELF binaries. +PVH allows information like location of ACPI tables and location of guest RAM +ranges to be shared without the need of an extra emulated device like a CMOS. + +Features + + +* Serial console +* EFI shell +* virtio-pci + +Build +- + +The way to build the CloudHv target is as follows: + +OvmfPkg/build.sh -p OvmfPkg/CloudHv/CloudHvX64.dsc -a X64 -b DEBUG + +Usage +- + +Assuming Cloud Hypervisor is already built, one can start a virtual machine as +follows: + +./cloud-hypervisor \ +--cpus boot=1 \ +--memory size=1G \ +--kernel Build/CloudHvX64/DEBUG_GCC5/FV/CLOUDHV.fd \ +--disk path=/path/to/disk.raw + +Releases + + +In edk2-stable202202, CloudHv is generated as data-only binary. +Starting with edk2-stable202205, CloudHv is generated as a PVH ELF binary to +reduce the amount of emulation needed from Cloud Hypervisor. +For TDX, things are handled differently and PVH is not used, which is why the +firmware is always generated as a data-only binary. + ++---++ +| |CloudHv | ++---++ +| edk2-stable202202 | Data binary| ++---++ +| edk2-stable202205 | PVH ELF binary | ++---++ -- 2.32.0 - Intel Corporation SAS (French simplified joint stock company) Registered headquarters: "Les Montalets"- 2, rue de Paris, 92196 Meudon Cedex, France Registration Number: 302 456 199 R.C.S. NANTERRE Capital: 4,572,000 Euros This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87232): https://edk2.groups.io/g/devel/message/87232 Mute This Topic: https://groups.io/mt/89500846/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v6 6/8] OvmfPkg: CloudHv: Retrieve RSDP address from PVH
From: Sebastien Boeuf
Instead of hardcoding the address of the RSDP in the firmware, let's
rely on the PVH structure hvm_start_info to retrieve this information.
Acked-by: Gerd Hoffmann
Signed-off-by: Sebastien Boeuf
---
OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf | 2 ++
OvmfPkg/AcpiPlatformDxe/CloudHvAcpi.c | 39 ++---
OvmfPkg/CloudHv/CloudHvX64.fdf | 3 ++
OvmfPkg/Include/IndustryStandard/CloudHv.h | 5 ---
4 files changed, 32 insertions(+), 17 deletions(-)
diff --git a/OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf
b/OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf
index b36b8413e0..f22bd7cb6d 100644
--- a/OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf
+++ b/OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf
@@ -56,6 +56,8 @@
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId
+ gUefiOvmfPkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtr
+ gUefiOvmfPkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtrSize
[Depex]
gEfiAcpiTableProtocolGuid
diff --git a/OvmfPkg/AcpiPlatformDxe/CloudHvAcpi.c
b/OvmfPkg/AcpiPlatformDxe/CloudHvAcpi.c
index 44a6bb70fe..ff59600d3e 100644
--- a/OvmfPkg/AcpiPlatformDxe/CloudHvAcpi.c
+++ b/OvmfPkg/AcpiPlatformDxe/CloudHvAcpi.c
@@ -7,9 +7,11 @@
**/
-#include // CLOUDHV_RSDP_ADDRESS
-#include // CpuDeadLoop()
-#include // DEBUG()
+#include //
CLOUDHV_RSDP_ADDRESS
+#include // hvm_start_info
+#include // CpuDeadLoop()
+#include // DEBUG()
+#include// PcdGet32()
#include "AcpiPlatform.h"
@@ -23,20 +25,33 @@ InstallCloudHvTables (
EFI_STATUS Status;
UINTN TableHandle;
- EFI_ACPI_DESCRIPTION_HEADER*Xsdt;
- VOID *CurrentTableEntry;
- UINTN CurrentTablePointer;
- EFI_ACPI_DESCRIPTION_HEADER*CurrentTable;
- UINTN Index;
- UINTN NumberOfTableEntries;
- EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *Fadt2Table;
- EFI_ACPI_DESCRIPTION_HEADER*DsdtTable;
+ EFI_ACPI_DESCRIPTION_HEADER *Xsdt;
+ VOID *CurrentTableEntry;
+ UINTN CurrentTablePointer;
+ EFI_ACPI_DESCRIPTION_HEADER *CurrentTable;
+ UINTN Index;
+ UINTN NumberOfTableEntries;
+ EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *Fadt2Table;
+ EFI_ACPI_DESCRIPTION_HEADER *DsdtTable;
+ EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER *AcpiRsdpStructurePtr;
+ UINT32*PVHResetVectorData;
+ struct hvm_start_info *pvh_start_info;
Fadt2Table = NULL;
DsdtTable= NULL;
TableHandle = 0;
NumberOfTableEntries = 0;
- EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER *AcpiRsdpStructurePtr = (VOID
*)CLOUDHV_RSDP_ADDRESS;
+ AcpiRsdpStructurePtr = NULL;
+ PVHResetVectorData = NULL;
+ pvh_start_info = NULL;
+
+ PVHResetVectorData = (VOID *)(UINTN)PcdGet32 (PcdXenPvhStartOfDayStructPtr);
+ if (PVHResetVectorData == 0) {
+return EFI_NOT_FOUND;
+ }
+
+ pvh_start_info = (struct hvm_start_info *)(UINTN)PVHResetVectorData[0];
+ AcpiRsdpStructurePtr = (EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER
*)(UINTN)pvh_start_info->rsdp_paddr;
// If XSDT table is found, just install its tables.
// Otherwise, try to find and install the RSDT tables.
diff --git a/OvmfPkg/CloudHv/CloudHvX64.fdf b/OvmfPkg/CloudHv/CloudHvX64.fdf
index 282bcf8634..d80e13ae90 100644
--- a/OvmfPkg/CloudHv/CloudHvX64.fdf
+++ b/OvmfPkg/CloudHv/CloudHvX64.fdf
@@ -73,6 +73,9 @@
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSnpSecretsBase|gUefiOvmfPkgTokenSpaceGuid.PcdO
0x00E000|0x001000
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidSize
+0x00F000|0x001000
+gUefiOvmfPkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtr|gUefiOvmfPkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtrSize
+
0x01|0x01
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize
diff --git a/OvmfPkg/Include/IndustryStandard/CloudHv.h
b/OvmfPkg/Include/IndustryStandard/CloudHv.h
index 86404cc97e..d31ecc9eec 100644
--- a/OvmfPkg/Include/IndustryStandard/CloudHv.h
+++ b/OvmfPkg/Include/IndustryStandard/CloudHv.h
@@ -38,9 +38,4 @@
//
#define CLOUDHV_SMBIOS_ADDRESS 0xf
-//
-// RSDP address
-//
-#define CLOUDHV_RSDP_ADDRESS 0xa
-
#endif // __CLOUDHV_H__
--
2.32.0
-
Intel Corporation SAS (French simplified joint stock company)
Registered headquarters: "Les Montalets"- 2,
[edk2-devel] [PATCH v6 5/8] OvmfPkg: Generate CloudHv as a PVH ELF binary
From: Sebastien Boeuf
Following the model from the Xen target, CloudHv is generated as a PVH
ELF binary to take advantage of the PVH specification, which requires
less emulation from the VMM.
The fdf include file CloudHvElfHeader.fdf.inc has been generated from
the following commands:
$ gcc -D PVH64 -o elf_gen OvmfPkg/OvmfXenElfHeaderGenerator.c
$ ./elf_gen 4194304 OvmfPkg/CloudHv/CloudHvElfHeader.fdf.inc
Signed-off-by: Sebastien Boeuf
---
OvmfPkg/CloudHv/CloudHvElfHeader.fdf.inc | 54
OvmfPkg/CloudHv/CloudHvX64.dsc | 2 +-
OvmfPkg/CloudHv/CloudHvX64.fdf | 15 +--
3 files changed, 66 insertions(+), 5 deletions(-)
create mode 100644 OvmfPkg/CloudHv/CloudHvElfHeader.fdf.inc
diff --git a/OvmfPkg/CloudHv/CloudHvElfHeader.fdf.inc
b/OvmfPkg/CloudHv/CloudHvElfHeader.fdf.inc
new file mode 100644
index 00..8377e30bdc
--- /dev/null
+++ b/OvmfPkg/CloudHv/CloudHvElfHeader.fdf.inc
@@ -0,0 +1,54 @@
+## @file
+# FDF include file that defines a PVH ELF header.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+DATA = {
+ # ELF file header
+ 0x7f, 0x45, 0x4c, 0x46, 0x02, 0x01, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x03, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0xd0, 0xff, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, # hdr.e_entry
+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x38, 0x00, 0x02,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+ # ELF Program segment headers
+ # - Load segment
+ 0x01, 0x00, 0x00, 0x00,
+ 0x07, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x10, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x10, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x40, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x40, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x04, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ # - ELFNOTE segment
+ 0x04, 0x00, 0x00, 0x00,
+ 0x04, 0x00, 0x00, 0x00,
+ 0xb0, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0xb0, 0x00, 0x10, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0xb0, 0x00, 0x10, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x14, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x14, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x04, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+
+ # XEN_ELFNOTE_PHYS32_ENTRY
+ 0x04, 0x00, 0x00, 0x00,
+ 0x04, 0x00, 0x00, 0x00,
+ 0x12, 0x00, 0x00, 0x00,
+ 0x58, 0x65, 0x6e, 0x00,
+ 0xd0, 0xff, 0x4f, 0x00
+}
diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc
index 3172100310..b4d855d80f 100644
--- a/OvmfPkg/CloudHv/CloudHvX64.dsc
+++ b/OvmfPkg/CloudHv/CloudHvX64.dsc
@@ -631,7 +631,7 @@
#
[Components]
- OvmfPkg/ResetVector/ResetVector.inf
+ OvmfPkg/XenResetVector/XenResetVector.inf
#
# SEC Phase modules
diff --git a/OvmfPkg/CloudHv/CloudHvX64.fdf b/OvmfPkg/CloudHv/CloudHvX64.fdf
index 0974e76ac8..282bcf8634 100644
--- a/OvmfPkg/CloudHv/CloudHvX64.fdf
+++ b/OvmfPkg/CloudHv/CloudHvX64.fdf
@@ -14,8 +14,8 @@
!include OvmfPkg/OvmfPkgDefines.fdf.inc
#
-# Build the variable store and the firmware code as one unified flash device
-# image.
+# This will allow the flash device image to be recognize as an ELF, with first
+# an ELF headers, then the firmware code.
#
[FD.CLOUDHV]
BaseAddress = $(FW_BASE_ADDRESS)
@@ -24,7 +24,14 @@ ErasePolarity = 1
BlockSize = $(BLOCK_SIZE)
NumBlocks = $(FW_BLOCKS)
-0x|$(FVMAIN_SIZE)
+#
+# Leaving 4kiB for the PVH ELF header. This is more than enough.
+#
+0x|0x1000
+
+!include CloudHvElfHeader.fdf.inc
+
+0x1000|$(FVMAIN_SIZE)
FV = FVMAIN_COMPACT
$(SECFV_OFFSET)|$(SECFV_SIZE)
@@ -114,7 +121,7 @@ READ_LOCK_STATUS = TRUE
#
INF OvmfPkg/Sec/SecMain.inf
-INF RuleOverride=RESET_VECTOR OvmfPkg/ResetVector/ResetVector.inf
+INF RuleOverride=RESET_VECTOR OvmfPkg/XenResetVector/XenResetVector.inf
[FV.PEIFV]
--
2.32.0
-
Intel Corporation SAS (French simplified joint stock company)
Registered headquarters: "Les Montalets"- 2, rue de Paris,
92196 Meudon Cedex, France
Registration Number: 302 456 199 R.C.S. NANTERRE
Capital: 4,572,000 Euros
This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.
-=-=-=-=-=-=-=-=-=-=-=-
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[edk2-devel] [PATCH v6 2/8] OvmfPkg: Xen: Use a new fdf include for the PVH ELF header
From: Sebastien Boeuf
Instead of having the PVH ELF header part of the fdf file directly, we
move it to a dedicated include file. This is the first step in
automating the generation of the header.
Acked-by: Gerd Hoffmann
Signed-off-by: Sebastien Boeuf
---
OvmfPkg/OvmfXen.fdf | 57 ++--
OvmfPkg/XenElfHeader.fdf.inc | 64
2 files changed, 66 insertions(+), 55 deletions(-)
create mode 100644 OvmfPkg/XenElfHeader.fdf.inc
diff --git a/OvmfPkg/OvmfXen.fdf b/OvmfPkg/OvmfXen.fdf
index a6acf3b835..2e67db5d32 100644
--- a/OvmfPkg/OvmfXen.fdf
+++ b/OvmfPkg/OvmfXen.fdf
@@ -31,61 +31,8 @@ NumBlocks = $(FW_BLOCKS)
!if $(FD_SIZE_IN_KB) == 4096
0x|0x0004
!endif
-DATA = {
- #
- # This hex array have been generated by OvmfPkg/OvmfXenElfHeaderGenerator.c
- # and copied manually.
- #
- # ELF file header
- 0x7f, 0x45, 0x4c, 0x46, # e_ident[0..3]: Magic number
- 0x01, # File class: 32-bit objects
- 0x01, # Data encoding: 2's complement, little endian
- 0x01, # File version
- 0x03, # OS ABI identification: Object uses GNU ELF extensions
- 0x00, # ABI version
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # e_ident[EI_PAD...]
- 0x02, 0x00, # e_type = Executable file
- 0x03, 0x00, # e_machine = Intel 80386
- 0x01, 0x00, 0x00, 0x00, # e_version
- 0xd0, 0xff, 0x2f, 0x00, # e_entry: Entry point virtual address
- 0x34, 0x00, 0x00, 0x00, # e_phoff: Program header table file offset
- 0x00, 0x00, 0x00, 0x00, # e_shoff: Section header table file offset
- 0x00, 0x00, 0x00, 0x00, # e_flags: Processor-specific flags
- 0x34, 0x00, #e_ehsize: ELF header size
- 0x20, 0x00, # e_phentsize: Program header table entry size
- 0x02, 0x00, # e_phnum: Program header table entry count
- 0x00, 0x00, # e_shentsize: Section header table entry size
- 0x00, 0x00, # e_shnum: Section header table entry count
- 0x00, 0x00, # e_shstrndx
-
- # ELF Program segment headers
- # - Load segment
- 0x01, 0x00, 0x00, 0x00, # p_type = Loadable program segment
- 0x00, 0x00, 0x00, 0x00, # p_offset
- 0x00, 0x00, 0x10, 0x00, # p_vaddr: Segment virtual address
- 0x00, 0x00, 0x10, 0x00, # p_paddr: Segment physical address
- 0x00, 0x00, 0x20, 0x00, # p_filesz: Segment size in file
- 0x00, 0x00, 0x20, 0x00, # p_memsz: Segment size in memory
- 0x07, 0x00, 0x00, 0x00, # p_flags = Segment is executable | writable |
readable
- 0x00, 0x00, 0x00, 0x00, # p_align
- # - ELFNOTE segment
- 0x04, 0x00, 0x00, 0x00, # p_type = PT_NOTE
- 0x74, 0x00, 0x00, 0x00, # p_offset = point to XEN_ELFNOTE_PHYS32_ENTRY below
- 0x74, 0x00, 0x10, 0x00,
- 0x74, 0x00, 0x10, 0x00,
- 0x14, 0x00, 0x00, 0x00,
- 0x14, 0x00, 0x00, 0x00,
- 0x04, 0x00, 0x00, 0x00, # p_flags = Segment is readable
- 0x00, 0x00, 0x00, 0x00,
-
- # XEN_ELFNOTE_PHYS32_ENTRY
- 0x04, 0x00, 0x00, 0x00, # name size
- 0x04, 0x00, 0x00, 0x00, # desc size
- 0x12, 0x00, 0x00, 0x00, # type = XEN_ELFNOTE_PHYS32_ENTRY
- 0x58, 0x65, 0x6e, 0x00, # name = "Xen"
- 0xd0, 0xff, 0x2f, 0x00, # desc: PVH entry point
- 0x00
-}
+
+!include XenElfHeader.fdf.inc
!if ($(FD_SIZE_IN_KB) == 1024) || ($(FD_SIZE_IN_KB) == 2048)
0xe000|0x1000
diff --git a/OvmfPkg/XenElfHeader.fdf.inc b/OvmfPkg/XenElfHeader.fdf.inc
new file mode 100644
index 00..dbc1305d25
--- /dev/null
+++ b/OvmfPkg/XenElfHeader.fdf.inc
@@ -0,0 +1,64 @@
+## @file
+# FDF include file that defines a PVH ELF header.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+DATA = {
+ #
+ # This hex array have been generated by OvmfPkg/OvmfXenElfHeaderGenerator.c
+ # and copied manually.
+ #
+ # ELF file header
+ 0x7f, 0x45, 0x4c, 0x46, # e_ident[0..3]: Magic number
+ 0x01, # File class: 32-bit objects
+ 0x01, # Data encoding: 2's complement, little endian
+ 0x01, # File version
+ 0x03, # OS ABI identification: Object uses GNU ELF extensions
+ 0x00, # ABI version
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # e_ident[EI_PAD...]
+ 0x02, 0x00, # e_type = Executable file
+ 0x03, 0x00, # e_machine = Intel 80386
+ 0x01, 0x00, 0x00, 0x00, # e_version
+ 0xd0, 0xff, 0x2f, 0x00, # e_entry: Entry point virtual address
+ 0x34, 0x00, 0x00, 0x00, # e_phoff: Program header table file offset
+ 0x00, 0x00, 0x00, 0x00, # e_shoff: Section header table file offset
+ 0x00, 0x00, 0x00, 0x00, # e_flags: Processor-specific flags
+ 0x34, 0x00, #e_ehsize: ELF header size
+ 0x20, 0x00, # e_phentsize: Program header table entry size
+ 0x02, 0x00, # e_phnum: Program header table entry count
+ 0x00, 0x00, # e_shentsize: Section header table entry size
+ 0x00, 0x00, # e_shnum: Section header table entry count
+ 0x00, 0x00, # e_shstrndx
+
+ # ELF Program segment headers
+ # - Load segment
+ 0x01, 0x00, 0x00, 0x00, # p_type = Loadable program segment
+ 0x00, 0x00, 0x00, 0x00, # p_offset
+ 0x00, 0x00, 0x10, 0x00, # p_vaddr: Segment virtual address
[edk2-devel] [PATCH v6 4/8] OvmfPkg: CloudHv: Remove VARS and CODE sections
From: Sebastien Boeuf CloudHv doesn't need any VARS store, and it doesn't need the CODE section to be generated separately either. The only thing needed is to generate a firmware binary that can be used by Cloud Hypervisor. Signed-off-by: Sebastien Boeuf --- OvmfPkg/CloudHv/CloudHvX64.fdf | 30 +- 1 file changed, 1 insertion(+), 29 deletions(-) diff --git a/OvmfPkg/CloudHv/CloudHvX64.fdf b/OvmfPkg/CloudHv/CloudHvX64.fdf index ce3302c6d6..0974e76ac8 100644 --- a/OvmfPkg/CloudHv/CloudHvX64.fdf +++ b/OvmfPkg/CloudHv/CloudHvX64.fdf @@ -24,38 +24,10 @@ ErasePolarity = 1 BlockSize = $(BLOCK_SIZE) NumBlocks = $(FW_BLOCKS) -!include OvmfPkg/VarStore.fdf.inc - -$(VARS_SIZE)|$(FVMAIN_SIZE) -FV = FVMAIN_COMPACT - -$(SECFV_OFFSET)|$(SECFV_SIZE) -FV = SECFV - -# -# Build the variable store and the firmware code as separate flash device -# images. -# -[FD.CLOUDHV_VARS] -BaseAddress = $(FW_BASE_ADDRESS) -Size = $(VARS_SIZE) -ErasePolarity = 1 -BlockSize = $(BLOCK_SIZE) -NumBlocks = $(VARS_BLOCKS) - -!include OvmfPkg/VarStore.fdf.inc - -[FD.CLOUDHV_CODE] -BaseAddress = $(CODE_BASE_ADDRESS) -Size = $(CODE_SIZE) -ErasePolarity = 1 -BlockSize = $(BLOCK_SIZE) -NumBlocks = $(CODE_BLOCKS) - 0x|$(FVMAIN_SIZE) FV = FVMAIN_COMPACT -$(FVMAIN_SIZE)|$(SECFV_SIZE) +$(SECFV_OFFSET)|$(SECFV_SIZE) FV = SECFV -- 2.32.0 - Intel Corporation SAS (French simplified joint stock company) Registered headquarters: "Les Montalets"- 2, rue de Paris, 92196 Meudon Cedex, France Registration Number: 302 456 199 R.C.S. NANTERRE Capital: 4,572,000 Euros This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87227): https://edk2.groups.io/g/devel/message/87227 Mute This Topic: https://groups.io/mt/89500829/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v6 3/8] OvmfPkg: Xen: Generate fdf include file from ELF header generator
From: Sebastien Boeuf
Updating the fdf include file based on the run of the ELF header
generator. The diff from this patch is the result of:
$ gcc -o elf_gen OvmfPkg/OvmfXenElfHeaderGenerator.c
$ ./elf_gen 2097152 OvmfPkg/XenElfHeader.fdf.inc
Acked-by: Gerd Hoffmann
Signed-off-by: Sebastien Boeuf
---
OvmfPkg/XenElfHeader.fdf.inc | 60
1 file changed, 19 insertions(+), 41 deletions(-)
diff --git a/OvmfPkg/XenElfHeader.fdf.inc b/OvmfPkg/XenElfHeader.fdf.inc
index dbc1305d25..c4f04ad28b 100644
--- a/OvmfPkg/XenElfHeader.fdf.inc
+++ b/OvmfPkg/XenElfHeader.fdf.inc
@@ -8,57 +8,35 @@
##
DATA = {
- #
- # This hex array have been generated by OvmfPkg/OvmfXenElfHeaderGenerator.c
- # and copied manually.
- #
# ELF file header
- 0x7f, 0x45, 0x4c, 0x46, # e_ident[0..3]: Magic number
- 0x01, # File class: 32-bit objects
- 0x01, # Data encoding: 2's complement, little endian
- 0x01, # File version
- 0x03, # OS ABI identification: Object uses GNU ELF extensions
- 0x00, # ABI version
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, # e_ident[EI_PAD...]
- 0x02, 0x00, # e_type = Executable file
- 0x03, 0x00, # e_machine = Intel 80386
- 0x01, 0x00, 0x00, 0x00, # e_version
- 0xd0, 0xff, 0x2f, 0x00, # e_entry: Entry point virtual address
- 0x34, 0x00, 0x00, 0x00, # e_phoff: Program header table file offset
- 0x00, 0x00, 0x00, 0x00, # e_shoff: Section header table file offset
- 0x00, 0x00, 0x00, 0x00, # e_flags: Processor-specific flags
- 0x34, 0x00, #e_ehsize: ELF header size
- 0x20, 0x00, # e_phentsize: Program header table entry size
- 0x02, 0x00, # e_phnum: Program header table entry count
- 0x00, 0x00, # e_shentsize: Section header table entry size
- 0x00, 0x00, # e_shnum: Section header table entry count
- 0x00, 0x00, # e_shstrndx
+ 0x7f, 0x45, 0x4c, 0x46, 0x01, 0x01, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x03, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0xd0, 0xff, 0x2f, 0x00, # hdr.e_entry
+ 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x34, 0x00, 0x20, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
# ELF Program segment headers
# - Load segment
- 0x01, 0x00, 0x00, 0x00, # p_type = Loadable program segment
- 0x00, 0x00, 0x00, 0x00, # p_offset
- 0x00, 0x00, 0x10, 0x00, # p_vaddr: Segment virtual address
- 0x00, 0x00, 0x10, 0x00, # p_paddr: Segment physical address
- 0x00, 0x00, 0x20, 0x00, # p_filesz: Segment size in file
- 0x00, 0x00, 0x20, 0x00, # p_memsz: Segment size in memory
- 0x07, 0x00, 0x00, 0x00, # p_flags = Segment is executable | writable |
readable
- 0x00, 0x00, 0x00, 0x00, # p_align
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x10, 0x00,
+ 0x00, 0x00, 0x10, 0x00,
+ 0x00, 0x00, 0x20, 0x00,
+ 0x00, 0x00, 0x20, 0x00,
+ 0x07, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
# - ELFNOTE segment
- 0x04, 0x00, 0x00, 0x00, # p_type = PT_NOTE
- 0x74, 0x00, 0x00, 0x00, # p_offset = point to XEN_ELFNOTE_PHYS32_ENTRY below
+ 0x04, 0x00, 0x00, 0x00,
+ 0x74, 0x00, 0x00, 0x00,
0x74, 0x00, 0x10, 0x00,
0x74, 0x00, 0x10, 0x00,
0x14, 0x00, 0x00, 0x00,
0x14, 0x00, 0x00, 0x00,
- 0x04, 0x00, 0x00, 0x00, # p_flags = Segment is readable
+ 0x04, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
# XEN_ELFNOTE_PHYS32_ENTRY
- 0x04, 0x00, 0x00, 0x00, # name size
- 0x04, 0x00, 0x00, 0x00, # desc size
- 0x12, 0x00, 0x00, 0x00, # type = XEN_ELFNOTE_PHYS32_ENTRY
- 0x58, 0x65, 0x6e, 0x00, # name = "Xen"
- 0xd0, 0xff, 0x2f, 0x00, # desc: PVH entry point
- 0x00
+ 0x04, 0x00, 0x00, 0x00,
+ 0x04, 0x00, 0x00, 0x00,
+ 0x12, 0x00, 0x00, 0x00,
+ 0x58, 0x65, 0x6e, 0x00,
+ 0xd0, 0xff, 0x2f, 0x00
}
--
2.32.0
-
Intel Corporation SAS (French simplified joint stock company)
Registered headquarters: "Les Montalets"- 2, rue de Paris,
92196 Meudon Cedex, France
Registration Number: 302 456 199 R.C.S. NANTERRE
Capital: 4,572,000 Euros
This e-mail and any attachments may contain confidential material for
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[edk2-devel] [PATCH v6 1/8] OvmfPkg: Make the Xen ELF header generator more flexible
From: Sebastien Boeuf
Adding some flexibility to the program through optional parameters and
global define, so that other targets can use the generator.
* A global define is added so that we can choose at build time if we
want to use 32-bit or 64-bit base structures.
* A first optional parameter is added so the user can provide the
expected blob size of the generated binary.
* A second optional parameter is added so the user can specify an output
file to which the generated output will be printed.
The default behavior isn't modified.
Acked-by: Gerd Hoffmann
Signed-off-by: Sebastien Boeuf
---
OvmfPkg/OvmfXenElfHeaderGenerator.c | 141 +---
1 file changed, 109 insertions(+), 32 deletions(-)
diff --git a/OvmfPkg/OvmfXenElfHeaderGenerator.c
b/OvmfPkg/OvmfXenElfHeaderGenerator.c
index 489060cdad..672129b85d 100644
--- a/OvmfPkg/OvmfXenElfHeaderGenerator.c
+++ b/OvmfPkg/OvmfXenElfHeaderGenerator.c
@@ -10,19 +10,31 @@
**/
#include "elf.h"
-#include "stdio.h"
+#include "fcntl.h"
+#include "stdbool.h"
#include "stddef.h"
+#include "stdio.h"
+#include "stdlib.h"
void
print_hdr (
+ FILE*file,
void*s,
- size_t size
+ size_t size,
+ boolend_delimiter
)
{
char *c = s;
- while (size--) {
-printf ("0x%02hhx, ", *(c++));
+ fprintf (file, " ");
+ while (size-- > 1) {
+fprintf (file, "0x%02hhx, ", *(c++));
+ }
+
+ if (end_delimiter) {
+fprintf (file, "0x%02hhx,", *c);
+ } else {
+fprintf (file, "0x%02hhx", *c);
}
}
@@ -36,34 +48,79 @@ typedef struct {
uint32_tdesc;
} xen_elfnote_phys32_entry;
+#define LICENSE_HDR "\
+## @file\r\n\
+# FDF include file that defines a PVH ELF header.\r\n\
+#\r\n\
+# Copyright (c) 2022, Intel Corporation. All rights reserved.\r\n\
+#\r\n\
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r\n\
+#\r\n\
+##\r\n\
+\r\n\
+"
+
int
main (
- void
+ int argc,
+ char *argv[]
)
{
/* FW_SIZE */
size_t ovmf_blob_size = 0x0020;
/* Load OVMF at 1MB when running as PVH guest */
uint32_t ovmf_base_address = 0x0010;
+ uint32_t ovmfxen_pvh_entry_point;
+ size_toffset_into_file = 0;
+ char *endptr, *str;
+ long param;
+ FILE *file = stdout;
+
+ /* Parse the size parameter */
+ if (argc > 1) {
+str = argv[1];
+param = strtol (str, &endptr, 10);
+if (endptr != str) {
+ ovmf_blob_size = (size_t)param;
+}
+ }
+
+ /* Parse the filepath parameter */
+ if (argc > 2) {
+file = fopen (argv[2], "w");
+fprintf (file, LICENSE_HDR);
+ }
+
/* Xen PVH entry point */
- uint32_t ovmfxen_pvh_entry_point = ovmf_base_address + ovmf_blob_size -
0x30;
- size_toffset_into_file= 0;
+ ovmfxen_pvh_entry_point = ovmf_base_address + ovmf_blob_size - 0x30;
/* ELF file header */
+ #ifdef PVH64
+ Elf64_Ehdr hdr = {
+ #else
Elf32_Ehdr hdr = {
-.e_ident = ELFMAG,
-.e_type = ET_EXEC,
-.e_machine = EM_386,
-.e_version = EV_CURRENT,
-.e_entry = ovmfxen_pvh_entry_point,
-.e_flags = R_386_NONE,
-.e_ehsize= sizeof (hdr),
+ #endif
+.e_ident = ELFMAG,
+.e_type= ET_EXEC,
+.e_machine = EM_386,
+.e_version = EV_CURRENT,
+.e_entry = ovmfxen_pvh_entry_point,
+.e_flags = R_386_NONE,
+.e_ehsize = sizeof (hdr),
+ #ifdef PVH64
+.e_phentsize = sizeof (Elf64_Phdr),
+ #else
.e_phentsize = sizeof (Elf32_Phdr),
+ #endif
};
offset_into_file += sizeof (hdr);
- hdr.e_ident[EI_CLASS] = ELFCLASS32;
+ #ifdef PVH64
+ hdr.e_ident[EI_CLASS] = ELFCLASS64;
+ #else
+ hdr.e_ident[EI_CLASS] = ELFCLASS32;
+ #endif
hdr.e_ident[EI_DATA]= ELFDATA2LSB;
hdr.e_ident[EI_VERSION] = EV_CURRENT;
hdr.e_ident[EI_OSABI] = ELFOSABI_LINUX;
@@ -71,14 +128,22 @@ main (
hdr.e_phoff = sizeof (hdr);
/* program header */
+ #ifdef PVH64
+ Elf64_Phdr phdr_load = {
+ #else
Elf32_Phdr phdr_load = {
+ #endif
.p_type = PT_LOAD,
.p_offset = 0, /* load everything */
.p_paddr = ovmf_base_address,
.p_filesz = ovmf_blob_size,
.p_memsz = ovmf_blob_size,
.p_flags = PF_X | PF_W | PF_R,
+ #ifdef PVH64
+.p_align = 4,
+ #else
.p_align = 0,
+ #endif
};
phdr_load.p_vaddr = phdr_load.p_paddr;
@@ -98,12 +163,20 @@ main (
sizeof (xen_elfnote_phys32_entry) -
offsetof (xen_elfnote_phys32_entry, desc),
};
- Elf32_Phdrphdr_note = {
+ #ifdef PVH64
+ Elf64_Phdr phdr_note = {
+ #else
+ Elf32_Phdr phdr_note = {
+ #endif
.p_type = PT_NOTE,
.p_filesz = sizeof (xen_elf_note),
.p_memsz = sizeof (xen_elf_note),
.p_flags = PF_R,
+ #ifdef PVH64
+.p_align = 4,
+ #else
.p_align = 0,
+ #endif
};
hdr.e_phnum += 1;
@@ -120,31 +193,35 @@ main (
size_t hdr_size = sizeof (hdr);
size_t entry_off = offsetof (typeof(hdr), e_entry);
- printf ("# ELF file header\n");
- print_hdr (&hdr, entry_off);
- printf ("\n");
-
[edk2-devel] [PATCH v6 0/8] CloudHv: Rely on PVH boot specification
From: Sebastien Boeuf Cloud Hypervisor aims at emulating the minimal amount of legacy devices and this is why the PVH boot specification is supported. The point is to be able to share some information with the guest without the need for emulating devices that would be present on real hardware. Since Cloud Hypervisor supports loading a PVH ELF binary, the CloudHv target is updated to be generated as such. Relying on the PVH boot specification, we don't need to hardcode the location of the ACPI tables anymore since we can retrieve the RSDP address from the hvm_start_info structure. Same thing for the RAM below 4G, we can find this information through the PVH memmap entries rather than relying on the emulated CMOS. Signed-off-by: Sebastien Boeuf Sebastien Boeuf (8): OvmfPkg: Make the Xen ELF header generator more flexible OvmfPkg: Xen: Use a new fdf include for the PVH ELF header OvmfPkg: Xen: Generate fdf include file from ELF header generator OvmfPkg: CloudHv: Remove VARS and CODE sections OvmfPkg: Generate CloudHv as a PVH ELF binary OvmfPkg: CloudHv: Retrieve RSDP address from PVH OvmfPkg: CloudHv: Rely on PVH memmap instead of CMOS OvmfPkg: CloudHv: Add README OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf | 2 + OvmfPkg/AcpiPlatformDxe/CloudHvAcpi.c | 39 -- OvmfPkg/CloudHv/CloudHvElfHeader.fdf.inc| 54 OvmfPkg/CloudHv/CloudHvX64.dsc | 2 +- OvmfPkg/CloudHv/CloudHvX64.fdf | 40 ++ OvmfPkg/CloudHv/README | 67 ++ OvmfPkg/Include/IndustryStandard/CloudHv.h | 5 - OvmfPkg/OvmfXen.fdf | 57 +--- OvmfPkg/OvmfXenElfHeaderGenerator.c | 141 +++- OvmfPkg/PlatformPei/MemDetect.c | 73 ++ OvmfPkg/PlatformPei/PlatformPei.inf | 2 + OvmfPkg/XenElfHeader.fdf.inc| 42 ++ 12 files changed, 390 insertions(+), 134 deletions(-) create mode 100644 OvmfPkg/CloudHv/CloudHvElfHeader.fdf.inc create mode 100644 OvmfPkg/CloudHv/README create mode 100644 OvmfPkg/XenElfHeader.fdf.inc -- 2.32.0 - Intel Corporation SAS (French simplified joint stock company) Registered headquarters: "Les Montalets"- 2, rue de Paris, 92196 Meudon Cedex, France Registration Number: 302 456 199 R.C.S. NANTERRE Capital: 4,572,000 Euros This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87224): https://edk2.groups.io/g/devel/message/87224 Mute This Topic: https://groups.io/mt/89500817/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH 1/2] Reconfigure OpensslLib to add elliptic curve chipher algorithms
>From requirement perspective, I am thinking more broadly than just ECC. Looking at https://github.com/tianocore/edk2/blob/master/CryptoPkg/Library/Include/openssl/opensslconf.h today, we disabled lots of thing, ECDH, ECDSA, TLS1_3, which might be potential useful. While the algorithm we used today such as FFDHE, MD5, SHA1, might be not useful. Even for ECC, some platform may need normal ECDH/ECDSA. However, some platform may or might not need EdDSA or X-Curve DH. I am not sure if we really need to enable all of them in previous patch set. SM3 and SM2 are another category. It might be useful for one particular segment, but not useful for others. For example, a SMx-compliant only platform may only requires SM2/SM3 (no RSA/ECC), which a NIST-compliant only platform might not required SMx. If a platform does have flash size constrain, why it cannot do customization? Why we enforce every platform, from an embedded system to a server use the same default configuration ? openssl exposes a config file, other crypto lib (mbedtls, wolfssl) also does same thing, such as https://github.com/ARMmbed/mbedtls/blob/development/include/mbedtls/mbedtls_config.h, https://github.com/wolfSSL/wolfssl/tree/master/examples/configs Why we cannot allow a platform override such configuration ? I am not saying we must do it. But I believe it is worth to revisit, to see if any platform has such need, before draw the conclusion so quick. Thank you Yao Jiewen > -Original Message- > From: Gerd Hoffmann > Sent: Wednesday, March 2, 2022 3:42 PM > To: Yao, Jiewen > Cc: Li, Yi1 ; devel@edk2.groups.io; Kovvuri, Vineel > ; Luo, Heng > Subject: Re: [edk2-devel] [PATCH 1/2] Reconfigure OpensslLib to add elliptic > curve chipher algorithms > > On Wed, Mar 02, 2022 at 06:59:48AM +, Yao, Jiewen wrote: > > I think another option to pursue is to how to control the openssl > > configuration > from module or platform level. > > > > E.g. what if platform-A has enough size and wants to use ECC, while > > platform- > B has size constrain and wants to disable ECC ? > > > > We can let platform choose if ECC is needed or not? I hope so. > > Not so easy. Would require to put the way openssl is integrated upside > down. Today openssl is configured and the results (header files etc) > are committed to the repo, so the openssl config is the same for > everybody. > > Also I expect there is no way around ecc long-term. WPA3 was mentioned > elsewhere in the thread. For TLS it will most likely be a requirement > too at some point in the future. With TLS 1.2 it is possible to choose > ciphers not requiring ECC, for TLS 1.3 ECC is mandatory though. > > So I doubt making ECC optional is worth the trouble. > > take care, > Gerd -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87223): https://edk2.groups.io/g/devel/message/87223 Mute This Topic: https://groups.io/mt/86257810/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v5 4/7] OvmfPkg: Generate CloudHv as a PVH ELF binary
On Wed, 2022-03-02 at 08:17 +0100, Gerd Hoffmann wrote:
> > -[FD.CLOUDHV_VARS]
> > -[FD.CLOUDHV_CODE]
>
> Dropping these two should be a separate patch,
> so this patch becomes more readable.
Sounds good.
>
> > -0x|$(FVMAIN_SIZE)
> > +0x1000|$(FVMAIN_SIZE)
>
> FVMAIN_SIZE is not changes anywhere it seems.
> So CLOUDHV.fd ends up with some odd size (instead of 2M or 4M) I
> guess?
No the total size is still 4M because of the FW_SIZE.
>
> (not much of a problem though if cloudhv doesn't care ...)
>
> > diff --git a/OvmfPkg/VarStore.fdf.inc b/OvmfPkg/VarStore.fdf.inc
> > index a1e524e393..a1cbc74fbb 100644
> > --- a/OvmfPkg/VarStore.fdf.inc
> > +++ b/OvmfPkg/VarStore.fdf.inc
> > @@ -15,6 +15,7 @@
> > 0x|0x0004
> > !endif
> > #NV_VARIABLE_STORE
> > +
> > DATA = {
> > ## This is the EFI_FIRMWARE_VOLUME_HEADER
> > # ZeroVector []
>
> leftover whitespace update
Ok I'll remove it.
>
> take care,
> Gerd
>
-
Intel Corporation SAS (French simplified joint stock company)
Registered headquarters: "Les Montalets"- 2, rue de Paris,
92196 Meudon Cedex, France
Registration Number: 302 456 199 R.C.S. NANTERRE
Capital: 4,572,000 Euros
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Re: [edk2-devel] [PATCH 1/2] Reconfigure OpensslLib to add elliptic curve chipher algorithms
On Wed, Mar 02, 2022 at 06:59:48AM +, Yao, Jiewen wrote: > I think another option to pursue is to how to control the openssl > configuration from module or platform level. > > E.g. what if platform-A has enough size and wants to use ECC, while > platform-B has size constrain and wants to disable ECC ? > > We can let platform choose if ECC is needed or not? I hope so. Not so easy. Would require to put the way openssl is integrated upside down. Today openssl is configured and the results (header files etc) are committed to the repo, so the openssl config is the same for everybody. Also I expect there is no way around ecc long-term. WPA3 was mentioned elsewhere in the thread. For TLS it will most likely be a requirement too at some point in the future. With TLS 1.2 it is possible to choose ciphers not requiring ECC, for TLS 1.3 ECC is mandatory though. So I doubt making ECC optional is worth the trouble. take care, Gerd -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87221): https://edk2.groups.io/g/devel/message/87221 Mute This Topic: https://groups.io/mt/86257810/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v5 4/7] OvmfPkg: Generate CloudHv as a PVH ELF binary
> -[FD.CLOUDHV_VARS]
> -[FD.CLOUDHV_CODE]
Dropping these two should be a separate patch,
so this patch becomes more readable.
> -0x|$(FVMAIN_SIZE)
> +0x1000|$(FVMAIN_SIZE)
FVMAIN_SIZE is not changes anywhere it seems.
So CLOUDHV.fd ends up with some odd size (instead of 2M or 4M) I guess?
(not much of a problem though if cloudhv doesn't care ...)
> diff --git a/OvmfPkg/VarStore.fdf.inc b/OvmfPkg/VarStore.fdf.inc
> index a1e524e393..a1cbc74fbb 100644
> --- a/OvmfPkg/VarStore.fdf.inc
> +++ b/OvmfPkg/VarStore.fdf.inc
> @@ -15,6 +15,7 @@
> 0x|0x0004
> !endif
> #NV_VARIABLE_STORE
> +
> DATA = {
>## This is the EFI_FIRMWARE_VOLUME_HEADER
># ZeroVector []
leftover whitespace update
take care,
Gerd
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Re: [edk2-devel] [PATCH v5 7/7] OvmfPkg: CloudHv: Add README
On Tue, Mar 01, 2022 at 02:29:17PM +0100, sebastien.bo...@intel.com wrote: > From: Sebastien Boeuf > > Add some documentation to the CloudHv target in order to clarify how to > use it and what to expect from it. > > Signed-off-by: Sebastien Boeuf Acked-by: Gerd Hoffmann -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87219): https://edk2.groups.io/g/devel/message/87219 Mute This Topic: https://groups.io/mt/89475277/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH V7 19/37] OvmfPkg/PlatformInitLib: Add memory functions
Hi, > > Hmm. Unlike patches 17+18 which are pure code motion (except the > > function renaming but that doesn't change the workflow) this patch mixes > > code changes and code moving which makes it hard to review. > > > > It should be splitted into one (or more) patches changing the functions as > > needed (and keeping the code in PlatformPei), and one patch moving things > > over to PlatformInitLib without functional changes. > Ok. Looks like #21 & #22 in tdvf_wave2.v6? > https://github.com/mxu9/edk2/commit/ef0615ca5665b2058e4352a322dfa74d258f9f31 > https://github.com/mxu9/edk2/commit/25f356a0bf7ee347be30e270aeffe6cbd8e0b464 No. The idea is to changes to the code in PlatformPei with small & one-patch-per-update patches, which allow easy review. Also helps debugging in case something go wrong, when bisecting found the broken patch it's *much* easier to find the actual bug when the patch is small. Rough plan: (1) a patch allocating PLATFORM_INFO struct in PlatformPei. (2) one or more patches moving global variables into PLATFORM_INFO struct. (3) one or more patches restructing functions. Stuff like like splitting functions which set PCDs into two, one for PlatformInitLib and one for PlatformPei. Final step is a pure move from PlatformPei to PlatformInitLib without changing code. > > > + // Fetch the lower memory size (Below 4G) // mLowerMemorySize = > > > + PlatformGetSystemMemorySizeBelow4gb (); > This is in function InitializePlatform(). > > > > Can't you just use TopOfLowRam here? > TopOfLowRam is a local variable in function MemMapInitialization(). It cannot > be used in function InitialziePlatform(). Ah, didn't notice it is another function. High time to introduce PLATFORM_INFO->TopOfLowRam ;) take care, Gerd -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87218): https://edk2.groups.io/g/devel/message/87218 Mute This Topic: https://groups.io/mt/89446168/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH 0/3] [RFC] consolidate compiler intrinsics
On Wed, Mar 02, 2022 at 08:39:28AM +, Kilian Kegel wrote: > Hi Gerd, > > additionally I would suggest once more to adjust the DLINK_FLAGS in > tools_def.txt to hold CompilerNameINTRIN32/64.LIB as a search library > as already introduced in > https://edk2.groups.io/g/devel/message/86072?p=%2C%2C%2C20%2C0%2C0%2C0%3A%3ACreated%2C%2Ckilian%2C20%2C2%2C0%2C87479913 > (here is the entire thread > https://edk2.groups.io/g/devel/message/86334?p=%2C%2C%2C20%2C0%2C0%2C0%3A%3ACreated%2C%2Cposterid%3A2193857%2C20%2C2%2C0%2C87479913) > > In that case you don’t need to take the IntrinsicLibrary into the .INF file, > because the intrinsic library is in the compiler’s library search path. > That has annoyed UEFI developers world wide for more that a decade. Having to add the IntrinsicLibrary to the .inf file is annoying indeed. Just using the compiler intrinsics doesn't work in all cases though, so I see no way around providing our own intrinsics library. > With your solution can you compile + link the body of main() given below in a > PEI driver on all targets? > Really? Nope. These patches simply move the existing intrinsics from ArmPkg and CryptoPkg as starting point. They are known to be incomplete. I expect we'll add more functions as needed in the future. We can surely debate if and how we can use the compiler's intrinsic library instead our own implementation for the cases where it works. Having a core intrinsics lib should actually make that kind changes easier, There will be one central place where you can tweak which intrinsic functions are provided by edk2, so coordinating that with DLINK_FLAGS updates should be easier than today. take care, Gerd -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87217): https://edk2.groups.io/g/devel/message/87217 Mute This Topic: https://groups.io/mt/89493375/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH 1/2] Reconfigure OpensslLib to add elliptic curve chipher algorithms
Hi, > 2. Jiewen (Cc'ed) suggested to look into using CryptoPkg/Driver instead of > linking openssl as Library, so we have only one copy of the code. Not > investigated yet. > > Does it means OvmfPkg will use CryptDxe instead of BaseCryptoLib and > OpensslLib directly? Sounds will be a big change. Havn't checked yet how much of a change that would be. Looks like CryptoPkg/Library/BaseCryptLibOnProtocolPpi is a drop-in replacement for CryptoPkg/Library/BaseCryptLib, which will call EDKII_CRYPTO_PROTOCOL provided by CryptoPkg/Driver instead of linking in the crypto bits from openssl. Apparently there isn't something simliar for OpensslLib though. > Or a separate ECC Driver such CryptEcDxe and still use BaseCryptoLib and > OpensslLib? Would probably make sense to just add ecc support to the existing CryptoPkg/Driver. take care, Gerd -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87216): https://edk2.groups.io/g/devel/message/87216 Mute This Topic: https://groups.io/mt/86257810/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v1 3/7] IntelFsp2Pkg: Invoke GetPhysicalAddressBits() and remove the duplicated code
Thanks Yu!
Reviewed-by: Chasel Chiu
> -Original Message-
> From: Pu, Yu
> Sent: Wednesday, March 2, 2022 5:19 PM
> To: devel@edk2.groups.io
> Cc: Pu, Yu ; Chiu, Chasel
> Subject: [PATCH v1 3/7] IntelFsp2Pkg: Invoke GetPhysicalAddressBits() and
> remove the duplicated code
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3394
>
> Invoke GetPhysicalAddressBits() defined in UefiCpuPkg for CPU physical address
> mask calculation and remove the duplicated code in
> edk2\IntelFsp2Pkg\Library\BaseCacheLib\CacheLib.c.
>
> Cc: Chasel Chiu
>
> Signed-off-by: Yu Pu
> ---
> IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c | 10 ++
> IntelFsp2Pkg/Library/BaseCacheLib/BaseCacheLib.inf | 2 ++
> 2 files changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c
> b/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c
> index f879c268e7ec..3f8ed122b2be 100644
> --- a/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c
> +++ b/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c
> @@ -9,6 +9,7 @@
> #include #include #include
> +#include #include
> "CacheLibInternal.h" /**@@ -388,15 +389,8 @@ SetCacheAttributes (
>UINT32 UsedMsrNum; EFI_MEMORY_CACHE_TYPE
> UsedMemoryCacheType; UINT64 ValidMtrrAddressMask;- UINT32
> Cpuid_RegEax; - AsmCpuid (CPUID_EXTENDED_FUNCTION, &Cpuid_RegEax,
> NULL, NULL, NULL);- if (Cpuid_RegEax >= CPUID_VIR_PHY_ADDRESS_SIZE) {-
> AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Cpuid_RegEax, NULL, NULL,
> NULL);-ValidMtrrAddressMask = (LShiftU64 ((UINT64)1, (Cpuid_RegEax &
> 0xFF)) - 1) & (~(UINT64)0x0FFF);- } else {-ValidMtrrAddressMask =
> (LShiftU64
> ((UINT64)1, 36) - 1) & (~(UINT64)0x0FFF);- }+ GetPhysicalAddressBits(NULL,
> &ValidMtrrAddressMask);// // Check for invalid parameterdiff --git
> a/IntelFsp2Pkg/Library/BaseCacheLib/BaseCacheLib.inf
> b/IntelFsp2Pkg/Library/BaseCacheLib/BaseCacheLib.inf
> index 9a513fb6df77..e6b14ae4a802 100644
> --- a/IntelFsp2Pkg/Library/BaseCacheLib/BaseCacheLib.inf
> +++ b/IntelFsp2Pkg/Library/BaseCacheLib/BaseCacheLib.inf
> @@ -21,9 +21,11 @@
> [Packages] MdePkg/MdePkg.dec+ UefiCpuPkg/UefiCpuPkg.dec
> IntelFsp2Pkg/IntelFsp2Pkg.dec [LibraryClasses] BaseMemoryLib
> CacheAsRamLib+ UefiCpuLib --
> 2.30.0.windows.2
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[edk2-devel] [PATCH v4 1/1] CryptoPkg: Add new hash algorithm ParallelHash256HashAll in BaseCryptLib.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3596
Parallel hash function ParallelHash256HashAll, as defined in NIST's
Special Publication 800-185, published December 2016. It utilizes
multi-process to calculate the digest.
Some modifications to pass CI test.
Cc: Jiewen Yao
Cc: Jian J Wang
Cc: Xiaoyu Lu
Cc: Guomin Jiang
Cc: Siyuan Fu
Cc: Zhihao Li
Signed-off-by: Zhihao Li
---
CryptoPkg/Library/BaseCryptLib/Hash/CryptCShake256.c | 381
CryptoPkg/Library/BaseCryptLib/Hash/CryptParallelHash.c | 350
++
CryptoPkg/Library/BaseCryptLib/Hash/CryptSha3.c | 166
+
CryptoPkg/Library/BaseCryptLib/Hash/CryptXkcp.c | 107
++
CryptoPkg/Test/UnitTest/Library/BaseCryptLib/ParallelhashTests.c | 145
CryptoPkg/Include/Library/BaseCryptLib.h | 31 +-
CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf| 8 +-
CryptoPkg/Library/Include/CrtLibSupport.h | 38 +-
CryptoPkg/Test/CryptoPkgHostUnitTest.dsc | 3 +
CryptoPkg/Test/UnitTest/Library/BaseCryptLib/TestBaseCryptLibHost.inf | 4 +
10 files changed, 1230 insertions(+), 3 deletions(-)
diff --git a/CryptoPkg/Library/BaseCryptLib/Hash/CryptCShake256.c
b/CryptoPkg/Library/BaseCryptLib/Hash/CryptCShake256.c
new file mode 100644
index ..6b26d74d5413
--- /dev/null
+++ b/CryptoPkg/Library/BaseCryptLib/Hash/CryptCShake256.c
@@ -0,0 +1,381 @@
+/** @file
+ cSHAKE-256 Digest Wrapper Implementations.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "InternalCryptLib.h"
+
+#define CSHAKE256_SECURITY_STRENGTH 256
+#define CSHAKE256_RATE_IN_BYTES 136
+
+const CHAR8 mZeroPadding[CSHAKE256_RATE_IN_BYTES] = { 0 };
+
+/**
+ Encode function from XKCP.
+
+ Encodes the input as a byte string in a way that can be unambiguously parsed
+ from the beginning of the string by inserting the length of the byte string
+ before the byte string representation of input.
+
+ @param[out] EncBuf Result of left encode.
+ @param[in] Value Input of left encode.
+
+ @retval EncLen Size of encode result in bytes.
+**/
+UINTN
+EFIAPI
+LeftEncode (
+ OUT UINT8 *EncBuf,
+ IN UINTN Value
+ );
+
+/**
+ Encode function from XKCP.
+
+ Encodes the input as a byte string in a way that can be unambiguously parsed
+ from the end of the string by inserting the length of the byte string after
+ the byte string representation of input.
+
+ @param[out] EncBuf Result of right encode.
+ @param[in] Value Input of right encode.
+
+ @retval EncLen Size of encode result in bytes.
+**/
+UINTN
+EFIAPI
+RightEncode (
+ OUT UINT8 *EncBuf,
+ IN UINTN Value
+ );
+
+/**
+ Keccak initial fuction.
+
+ Set up state with specified capacity.
+
+ @param[out] Context Pointer to the context being initialized.
+ @param[in] Pad Delimited Suffix.
+ @param[in] BlockSize Size of context block.
+ @param[in] MessageDigestLen Size of message digest in bytes.
+
+ @retval 1 Initialize successfully.
+ @retval 0 Fail to initialize.
+**/
+UINT8
+EFIAPI
+KeccakInit (
+ OUT Keccak1600_Ctx *Context,
+ IN UINT8 Pad,
+ IN UINTN BlockSize,
+ IN UINTN MessageDigstLen
+ );
+
+/**
+ Sha3 update fuction.
+
+ This function performs Sha3 digest on a data buffer of the specified size.
+ It can be called multiple times to compute the digest of long or
discontinuous data streams.
+
+ @param[in,out] Context Pointer to the Keccak context.
+ @param[in] Data Pointer to the buffer containing the data to be
hashed.
+ @param[in] DataSize Size of Data buffer in bytes.
+
+ @retval 1 Update successfully.
+**/
+UINT8
+EFIAPI
+Sha3Update (
+ IN OUT Keccak1600_Ctx *Context,
+ IN const VOID *Data,
+ IN UINTN DataSize
+ );
+
+/**
+ Completes computation of Sha3 message digest.
+
+ This function completes sha3 hash computation and retrieves the digest value
into
+ the specified memory. After this function has been called, the keccak
context cannot
+ be used again.
+
+ @param[in, out] ContextPointer to the keccak context.
+ @param[out] MessageDigest Pointer to a buffer that receives the
message digest.
+
+ @retval 1 Meaasge digest computation succeeded.
+**/
+UINT8
+EFIAPI
+Sha3Final (
+ IN OUT Keccak1600_Ctx *Context,
+ OUTUINT8 *MessageDigest
+ );
+
+/**
+ CShake256 initial function.
+
+ Initializes user-supplied memory pointed by CShake256Context as cSHAKE-256
hash context for
+ subsequent use.
+
+ @param[out] CShake256Context Pointer to cSHAKE-256 context being
initialized.
+ @param[in] OutputLen The desired number of output length in bytes.
+ @param[in] Name Pointer to th
Re: [edk2-devel] [PATCH v5 1/1] UefiCpuPkg: Extend SMM CPU Service with rendezvous support.
Reviewed-by: Ray Ni
-Original Message-
From: Li, Zhihao
Sent: Tuesday, March 1, 2022 7:22 PM
To: devel@edk2.groups.io
Cc: Dong, Eric ; Ni, Ray ; Kumar, Rahul1
; Fu, Siyuan
Subject: [PATCH v5 1/1] UefiCpuPkg: Extend SMM CPU Service with rendezvous
support.
REF： https://bugzilla.tianocore.org/show_bug.cgi?id=3815
This patch define a new Protocol with the new services
SmmWaitForAllProcessor(), which can be used by SMI handler
to optionally wait for other APs to complete SMM rendezvous in
relaxed AP mode.
A new library SmmCpuRendezvousLib is provided to abstract the service
into library API to simple SMI handler code.
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Siyuan Fu
Cc: Zhihao Li
Signed-off-by: Zhihao Li
---
UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.c | 103
UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c | 69
-
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 20 +++-
UefiCpuPkg/Include/Library/SmmCpuRendezvousLib.h | 27 +
UefiCpuPkg/Include/Protocol/SmmCpuService.h| 36 ++-
UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf | 35 +++
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 29 +-
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 5 +-
UefiCpuPkg/UefiCpuPkg.dec | 8 +-
UefiCpuPkg/UefiCpuPkg.dsc | 2 +
10 files changed, 322 insertions(+), 12 deletions(-)
diff --git a/UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.c
b/UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.c
new file mode 100644
index ..e573c2ecfb51
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.c
@@ -0,0 +1,103 @@
+/** @file
+ SMM CPU Rendezvous sevice implement.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+STATIC EDKII_SMM_CPU_RENDEZVOUS_PROTOCOL *mSmmCpuRendezvous = NULL;
+STATIC VOID *mRegistration = NULL;
+
+/**
+ Callback function to wait Smm cpu rendezvous service located.
+
+ SmmCpuRendezvousLib need to support MM_STANDALONE and DXE_SMM_DRIVER driver.
+ So do not use library constructor to locate the protocol.
+
+ @param[in] Protocol Points to the protocol's unique identifier.
+ @param[in] Interface Points to the interface instance.
+ @param[in] Handle The handle on which the interface was installed.
+
+ @retval EFI_SUCCESS Notification runs successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+SmmCpuRendezvousProtocolNotify (
+ IN CONST EFI_GUID*Protocol,
+ IN VOID*Interface,
+ IN EFI_HANDLE Handle
+ )
+{
+ EFI_STATUS Status;
+
+ Status = gMmst->MmLocateProtocol (
+&gEdkiiSmmCpuRendezvousProtocolGuid,
+NULL,
+(VOID **)&mSmmCpuRendezvous
+);
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This routine wait for all AP processors to arrive in SMM.
+
+ @param[in] BlockingMode Blocking mode or non-blocking mode.
+
+ @retval EFI_SUCCESS All avaiable APs arrived.
+ @retval EFI_TIMEOUT Wait for all APs until timeout.
+ @retval OTHERFail to register SMM CPU Rendezvous service Protocol.
+**/
+EFI_STATUS
+EFIAPI
+SmmWaitForAllProcessor (
+ IN BOOLEAN BlockingMode
+ )
+{
+ EFI_STATUS Status;
+
+ if ((mRegistration == NULL) && (mSmmCpuRendezvous == NULL)) {
+//
+// Locate SMM cpu rendezvous protocol for the first time execute the
function.
+//
+Status = gMmst->MmLocateProtocol (
+ &gEdkiiSmmCpuRendezvousProtocolGuid,
+ NULL,
+ (VOID **)&mSmmCpuRendezvous
+ );
+if (EFI_ERROR (Status)) {
+ Status = gMmst->MmRegisterProtocolNotify (
+&gEdkiiSmmCpuRendezvousProtocolGuid,
+SmmCpuRendezvousProtocolNotify,
+&mRegistration
+);
+ if (EFI_ERROR (Status)) {
+return Status;
+ }
+}
+ }
+
+ //
+ // The platform have not set up. It doesn't need smm cpu rendezvous.
+ //
+ if (mSmmCpuRendezvous == NULL) {
+return EFI_SUCCESS;
+ }
+
+ Status = mSmmCpuRendezvous->WaitForAllProcessor (
+mSmmCpuRendezvous,
+BlockingMode
+);
+ return Status;
+}
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
index 5d624f8e9ed6..2ebf4543c3ed 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
+++ b/UefiCpuPk
[edk2-devel] [edk2-platforms][PATCH V1 04/15] Platform/Loongson: Add QemuFwCfgLib.
QemuFwCfgLib for PEI phase.
This library obtains the QemuFWCfg base address by
directly parsing the fdt, and reads and writes the data
in the QemuFWCfg by operating on the QemuFWCfg base address.
Signed-off-by: xianglai li
---
.../Include/IndustryStandard/QemuFwCfg.h | 95
.../Include/Library/QemuFwCfgLib.h| 179 +++
.../Library/QemuFwCfgLib/QemuFwCfg.c | 119 +
.../Library/QemuFwCfgLib/QemuFwCfgLib.c | 477 ++
.../Library/QemuFwCfgLib/QemuFwCfgLib.inf | 44 ++
.../QemuFwCfgLib/QemuFwCfgLibInternal.h | 64 +++
6 files changed, 978 insertions(+)
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Include/IndustryStandard/QemuFwCfg.h
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Include/Library/QemuFwCfgLib.h
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Library/QemuFwCfgLib/QemuFwCfg.c
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Library/QemuFwCfgLib/QemuFwCfgLib.c
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Library/QemuFwCfgLib/QemuFwCfgLib.inf
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Library/QemuFwCfgLib/QemuFwCfgLibInternal.h
diff --git
a/Platform/Loongson/LoongArchQemuPkg/Include/IndustryStandard/QemuFwCfg.h
b/Platform/Loongson/LoongArchQemuPkg/Include/IndustryStandard/QemuFwCfg.h
new file mode 100644
index 00..175da61816
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Include/IndustryStandard/QemuFwCfg.h
@@ -0,0 +1,95 @@
+/** @file
+ Macro and type definitions corresponding to the QEMU fw_cfg interface.
+
+ Copyright (c) 2021 Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Glossary:
+- FW - FireWare
+- CFG- Configure
+- FNAME- File Name
+- CTL- Contorl
+**/
+
+#ifndef QEMU_FW_CFG_H_
+#define QEMU_FW_CFG_H_
+
+#include
+
+//
+// The size, in bytes, of names of firmware configuration files, including at
+// least one terminating NUL byte.
+//
+#define QEMU_FW_CFG_FNAME_SIZE 56
+
+//
+// If the following bit is set in the UINT32 fw_cfg revision / feature bitmap
+// -- read from key 0x0001 with the basic IO Port or MMIO method --, then the
+// DMA interface is available.
+//
+#define FW_CFG_F_DMA BIT1
+
+//
+// Macros for the FW_CFG_DMA_ACCESS.Control bitmap (in native encoding).
+//
+#define FW_CFG_DMA_CTL_ERROR BIT0
+#define FW_CFG_DMA_CTL_READ BIT1
+#define FW_CFG_DMA_CTL_SKIP BIT2
+#define FW_CFG_DMA_CTL_SELECT BIT3
+#define FW_CFG_DMA_CTL_WRITE BIT4
+
+//
+// The fw_cfg registers can be found at these IO Ports, on the IO-mapped
+// platforms (Ia32 and X64).
+//
+#define FW_CFG_IO_SELECTOR0x510
+#define FW_CFG_IO_DATA0x511
+#define FW_CFG_IO_DMA_ADDRESS 0x514
+
+//
+// Numerically defined keys.
+//
+typedef enum {
+ QemuFwCfgItemSignature= 0x,
+ QemuFwCfgItemInterfaceVersion = 0x0001,
+ QemuFwCfgItemSystemUuid = 0x0002,
+ QemuFwCfgItemRamSize = 0x0003,
+ QemuFwCfgItemGraphicsEnabled = 0x0004,
+ QemuFwCfgItemSmpCpuCount = 0x0005,
+ QemuFwCfgItemMachineId= 0x0006,
+ QemuFwCfgItemKernelAddress= 0x0007,
+ QemuFwCfgItemKernelSize = 0x0008,
+ QemuFwCfgItemKernelCommandLine= 0x0009,
+ QemuFwCfgItemInitrdAddress= 0x000a,
+ QemuFwCfgItemInitrdSize = 0x000b,
+ QemuFwCfgItemBootDevice = 0x000c,
+ QemuFwCfgItemNumaData = 0x000d,
+ QemuFwCfgItemBootMenu = 0x000e,
+ QemuFwCfgItemMaximumCpuCount = 0x000f,
+ QemuFwCfgItemKernelEntry = 0x0010,
+ QemuFwCfgItemKernelData = 0x0011,
+ QemuFwCfgItemInitrdData = 0x0012,
+ QemuFwCfgItemCommandLineAddress = 0x0013,
+ QemuFwCfgItemCommandLineSize = 0x0014,
+ QemuFwCfgItemCommandLineData = 0x0015,
+ QemuFwCfgItemKernelSetupAddress = 0x0016,
+ QemuFwCfgItemKernelSetupSize = 0x0017,
+ QemuFwCfgItemKernelSetupData = 0x0018,
+ QemuFwCfgItemFileDir = 0x0019,
+
+} FIRMWARE_CONFIG_ITEM;
+
+//
+// Communication structure for the DMA access method. All fields are encoded in
+// big endian.
+//
+#pragma pack (1)
+typedef struct {
+ UINT32 Control;
+ UINT32 Length;
+ UINT64 Address;
+} FW_CFG_DMA_ACCESS;
+#pragma pack ()
+
+#endif
diff --git a/Platform/Loongson/LoongArchQemuPkg/Include/Library/QemuFwCfgLib.h
b/Platform/Loongson/LoongArchQemuPkg/Include/Library/QemuFwCfgLib.h
new file mode 100644
index 00..f3c73adfe7
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Include/Library/QemuFwCfgLib.h
@@ -0,0 +1,179 @@
+/** @file
+ QEMU/KVM Firmware Configuration access
+
+ Copyright (c) 2021 Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Glossary:
+- FW or Fw- Firmware
+- Cfg - Configure
+**/
+
+#ifndef QEMU_FW_CFG_LIB_
+#define QEMU_FW_CFG_LIB_
+
+#include
+
+/**
+
[edk2-devel] [edk2-platforms][PATCH V1 12/15] Platform/Loongson: Add RealTime Clock lib.
This library provides interfaces such as
real-time clock initialization
to get time and setting time.
Signed-off-by: xianglai li
---
.../LsRealTimeClockLib/LsRealTimeClock.h | 41 +++
.../LsRealTimeClockLib/LsRealTimeClockLib.c | 343 ++
.../LsRealTimeClockLib/LsRealTimeClockLib.inf | 41 +++
3 files changed, 425 insertions(+)
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClock.h
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClockLib.c
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClockLib.inf
diff --git
a/Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClock.h
b/Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClock.h
new file mode 100644
index 00..74a5c629ab
--- /dev/null
+++
b/Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClock.h
@@ -0,0 +1,41 @@
+/** @file
+ Implement EFI RealTimeClock runtime services via RTC Lib.
+
+ Copyright (c) 2021, Loongson Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#ifndef LS_REAL_TIME_CLOCK_H_
+#define LS_REAL_TIME_CLOCK_H_
+
+#define TOY_WRITE0_REG0x24
+#define TOY_WRITE1_REG0x28
+#define TOY_READ0_REG 0x2c
+#define TOY_READ1_REG 0x30
+#define RTC_CTRL_REG 0x40
+
+/* TOY Enable bits */
+#define RTC_ENABLE_BIT (1UL << 13)
+#define TOY_ENABLE_BIT (1UL << 11)
+#define OSC_ENABLE_BIT (1UL << 8)
+
+/*
+ * shift bits and filed mask
+ */
+#define TOY_MON_MASK 0x3f
+#define TOY_DAY_MASK 0x1f
+#define TOY_HOUR_MASK 0x1f
+#define TOY_MIN_MASK 0x3f
+#define TOY_SEC_MASK 0x3f
+#define TOY_MSEC_MASK 0xf
+
+#define TOY_MON_SHIFT 26
+#define TOY_DAY_SHIFT 21
+#define TOY_HOUR_SHIFT 16
+#define TOY_MIN_SHIFT 10
+#define TOY_SEC_SHIFT 4
+
+#endif //__LS_REAL_TIME_CLOCK_H__
diff --git
a/Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClockLib.c
b/Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClockLib.c
new file mode 100644
index 00..cc5e426f03
--- /dev/null
+++
b/Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClockLib.c
@@ -0,0 +1,343 @@
+/** @file
+ Implement EFI RealTimeClock runtime services via RTC Lib.
+
+ Copyright (c) 2021, Loongson Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "LsRealTimeClock.h"
+
+STATIC BOOLEANmInitialized = FALSE;
+STATIC EFI_EVENT mRtcVirtualAddrChangeEvent;
+STATIC UINTN mRtcBase = 0X100d0100;
+/*
+ Enable Real-time clock.
+
+ @param VOID
+
+ @retval VOID
+ */
+VOID
+InitRtc (
+ VOID
+ )
+{
+ UINTN Val;
+
+ if (!mInitialized) {
+/* enable rtc */
+Val = MmioRead32 (mRtcBase + RTC_CTRL_REG);
+Val |= TOY_ENABLE_BIT | OSC_ENABLE_BIT;
+MmioWrite32 (mRtcBase + RTC_CTRL_REG, Val);
+mInitialized = TRUE;
+ }
+}
+
+/**
+ Returns the current time and date information, and the time-keeping
capabilities
+ of the hardware platform.
+
+ @param Time A pointer to storage to receive a snapshot of
the current time.
+ @param Capabilities An optional pointer to a buffer to receive
the real time clock
+ device's capabilities.
+
+ @retval EFI_SUCCESSThe operation completed successfully.
+ @retval EFI_INVALID_PARAMETER Time is NULL.
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to
hardware error.
+ @retval EFI_SECURITY_VIOLATION The time could not be retrieved due to an
authentication failure.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetTime (
+ OUT EFI_TIME*Time,
+ OUT EFI_TIME_CAPABILITIES *Capabilities
+ )
+{
+ UINT32 Val;
+
+ // Ensure Time is a valid pointer
+ if (Time == NULL) {
+return EFI_INVALID_PARAMETER;
+ }
+
+ InitRtc ();
+ Val = MmioRead32 (mRtcBase + TOY_READ1_REG);
+ Time->Year = Val + 1900;
+
+ Val = MmioRead32 (mRtcBase + TOY_READ0_REG);
+ Time->Month = ((Val >> TOY_MON_SHIFT) & TOY_MON_MASK) - 1;
+ Time->Day = (Val >> TOY_DAY_SHIFT) & TOY_DAY_MASK;
+ Time->Hour = (Val >> TOY_HOUR_SHIFT) & TOY_HOUR_MASK;
+ Time->Minute = (Val >> TOY_MIN_SHIFT) & TOY_MIN_MASK;
+ Time->Second = (Val >> TOY_SEC_SHIFT) & TOY_SEC_MASK;
+ Time->Nanosecond = 0;
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Sets the current local time and date information.
+
+ @param Time A pointer to the current time.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR
[edk2-devel] [edk2-platforms][PATCH V1 13/15] Platform/Loongson: Add Platform Boot Manager Lib.
The Library provides Boot Manager interfaces.
Signed-off-by: xianglai li
---
.../PlatformBootManagerLib/PlatformBm.c | 761 ++
.../PlatformBootManagerLib/PlatformBm.h | 126 +++
.../PlatformBootManagerLib.inf| 78 ++
.../PlatformBootManagerLib/QemuKernel.c | 449 +++
4 files changed, 1414 insertions(+)
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Library/PlatformBootManagerLib/PlatformBm.c
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Library/PlatformBootManagerLib/PlatformBm.h
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Library/PlatformBootManagerLib/QemuKernel.c
diff --git
a/Platform/Loongson/LoongArchQemuPkg/Library/PlatformBootManagerLib/PlatformBm.c
b/Platform/Loongson/LoongArchQemuPkg/Library/PlatformBootManagerLib/PlatformBm.c
new file mode 100644
index 00..1805a6a9b3
--- /dev/null
+++
b/Platform/Loongson/LoongArchQemuPkg/Library/PlatformBootManagerLib/PlatformBm.c
@@ -0,0 +1,761 @@
+/** @file
+ Implementation for PlatformBootManagerLib library class interfaces.
+
+ Copyright (c) 2021 Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "PlatformBm.h"
+
+STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole = {
+//
+// VENDOR_DEVICE_PATH SerialDxe
+//
+{
+{ HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DP_NODE_LEN (VENDOR_DEVICE_PATH)
},
+SERIAL_DXE_FILE_GUID
+},
+
+//
+// UART_DEVICE_PATH Uart
+//
+{
+{ MESSAGING_DEVICE_PATH, MSG_UART_DP, DP_NODE_LEN (UART_DEVICE_PATH) },
+0, // Reserved
+FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate
+FixedPcdGet8 (PcdUartDefaultDataBits), // DataBits
+FixedPcdGet8 (PcdUartDefaultParity),// Parity
+FixedPcdGet8 (PcdUartDefaultStopBits) // StopBits
+ },
+
+ //
+ // VENDOR_DEFINED_DEVICE_PATH TermType
+ //
+ {
+{
+ MESSAGING_DEVICE_PATH, MSG_VENDOR_DP,
+ DP_NODE_LEN (VENDOR_DEFINED_DEVICE_PATH)
+}
+//
+// Guid to be filled in dynamically
+//
+ },
+
+ //
+ // EFI_DEVICE_PATH_PROTOCOL End
+ //
+ {
+END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,
+DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL)
+ }
+};
+
+STATIC PLATFORM_USB_KEYBOARD mUsbKeyboard = {
+ //
+ // USB_CLASS_DEVICE_PATH Keyboard
+ //
+ {
+{
+ MESSAGING_DEVICE_PATH, MSG_USB_CLASS_DP,
+ DP_NODE_LEN (USB_CLASS_DEVICE_PATH)
+},
+0x, // VendorId: any
+0x, // ProductId: any
+3, // DeviceClass: HID
+1, // DeviceSubClass: boot
+1 // DeviceProtocol: keyboard
+ },
+
+ //
+ // EFI_DEVICE_PATH_PROTOCOL End
+ //
+ {
+END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,
+DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL)
+ }
+};
+
+/**
+ Locate all handles that carry the specified protocol, filter them with a
+ callback function, and pass each handle that passes the filter to another
+ callback.
+
+ @param[in] ProtocolGuid The protocol to look for.
+
+ @param[in] FilterThe filter function to pass each handle to. If this
+ parameter is NULL, then all handles are processed.
+
+ @param[in] Process The callback function to pass each handle to that
+ clears the filter.
+**/
+VOID
+FilterAndProcess (
+ IN EFI_GUID *ProtocolGuid,
+ IN FILTER_FUNCTION Filter OPTIONAL,
+ IN CALLBACK_FUNCTION Process
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *Handles;
+ UINTN NoHandles;
+ UINTN Idx;
+
+ Status = gBS->LocateHandleBuffer (ByProtocol, ProtocolGuid,
+ NULL /* SearchKey */, &NoHandles, &Handles);
+ if (EFI_ERROR (Status)) {
+//
+// This is not an error, just an informative condition.
+//
+DEBUG ((DEBUG_VERBOSE, "%a: %g: %r\n", __FUNCTION__, ProtocolGuid,
+ Status));
+return;
+ }
+
+ ASSERT (NoHandles > 0);
+ for (Idx = 0; Idx < NoHandles; ++Idx) {
+CHAR16*DevicePathText;
+STATIC CHAR16 Fallback[] = L"";
+
+//
+// The ConvertDevicePathToText () function handles NULL input
transparently.
+//
+DevicePathText = ConvertDevicePathToText (
+ DevicePathFromHandle (Handles[Idx]),
+ FALSE, // DisplayOnly
+ FALSE // AllowShortcuts
+ );
+if (DevicePathText == NULL) {
+ DevicePathText = Fallback;
+}
+
+if ((Filter == NULL)
+ || (Filter (Handles[Idx], DevicePathText)))
+{
+ Process (Handles[Idx], DevicePathText);
+}
+
+if (DevicePathText != Fallback) {
+ FreePool (DevicePat
[edk2-devel] [edk2-platforms][PATCH V1 15/15] Platform/Loongson: Support Dxe
Support Dxe for LoogArch.
Signed-off-by: xianglai li
---
.../Loongson/LoongArchQemuPkg/Loongson.dec| 14 +-
.../Loongson/LoongArchQemuPkg/Loongson.dsc| 385 +-
.../Loongson/LoongArchQemuPkg/Loongson.fdf| 241 +++
.../LoongArchQemuPkg/Loongson.fdf.inc | 41 ++
.../LoongArchQemuPkg/VarStore.fdf.inc | 64 +++
5 files changed, 742 insertions(+), 3 deletions(-)
create mode 100644 Platform/Loongson/LoongArchQemuPkg/VarStore.fdf.inc
diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
b/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
index aca53583f1..508a770a22 100644
--- a/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
+++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
@@ -18,7 +18,8 @@
# Comments are used for Keywords and Module Types.
#
# Supported Module Types:
-# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER
DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER
+# DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
#
[Includes.common]
@@ -26,12 +27,20 @@
[Guids]
gLoongArchQemuPkgTokenSpaceGuid = { 0x0e0383ce, 0x0151, 0x4d01, { 0x80,
0x0e, 0x3f, 0xef, 0x8b, 0x27, 0x6d, 0x52 } }
+ gEfiLoongsonBootparamsTableGuid = { 0x4660f721, 0x2ec5, 0x416a, { 0x89,
0x9a, 0x43, 0x18, 0x02, 0x50, 0xa0, 0xc9 } }
+
+[Protocols]
[PcdsFixedAtBuild, PcdsDynamic]
gLoongArchQemuPkgTokenSpaceGuid.PcdFlashPeiFvBase|0x0|UINT64|0x0003
gLoongArchQemuPkgTokenSpaceGuid.PcdFlashPeiFvSize|0x0|UINT32|0x0004
+ gLoongArchQemuPkgTokenSpaceGuid.PcdFlashDxeFvOffset|0x0|UINT64|0x0007
gLoongArchQemuPkgTokenSpaceGuid.PcdFlashDxeFvBase|0x0|UINT64|0x0008
gLoongArchQemuPkgTokenSpaceGuid.PcdFlashDxeFvSize|0x0|UINT32|0x0009
+ gLoongArchQemuPkgTokenSpaceGuid.PcdFlashSecModuleBase|0x0|UINT64|0x000a
+ gLoongArchQemuPkgTokenSpaceGuid.PcdFlashSecModuleSize|0x0|UINT32|0x000b
+ gLoongArchQemuPkgTokenSpaceGuid.PcdFlashEventLogBase|0x0|UINT64|0x000c
+ gLoongArchQemuPkgTokenSpaceGuid.PcdFlashEventLogSize|0x0|UINT32|0x000d
gLoongArchQemuPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize|0|UINT32|0x0016
gLoongArchQemuPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|0|UINT32|0x0017
gLoongArchQemuPkgTokenSpaceGuid.PcdDeviceTreeBase|0x0|UINT64|0x0018
@@ -47,6 +56,8 @@
[PcdsFixedAtBuild.LOONGARCH64]
gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|32|UINT8|0x0010
gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0|UINT8|0x0011
+
gLoongArchQemuPkgTokenSpaceGuid.PcdDeviceSpaceStartAddress|0x1000|UINT32|0x0012
+
gLoongArchQemuPkgTokenSpaceGuid.PcdDeviceSpaceLength|0x8000|UINT32|0x0013
[PcdsDynamic]
gLoongArchQemuPkgTokenSpaceGuid.PcdRamSize|0x4000|UINT64|0x0041
@@ -58,3 +69,4 @@
gLoongArchQemuPkgTokenSpaceGuid.PcdInvalidPmd|0x0|UINT64|0x0047
gLoongArchQemuPkgTokenSpaceGuid.PcdInvalidPte|0x0|UINT64|0x0048
+[PcdsFeatureFlag]
diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
b/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
index 09b324c3f7..7d69339674 100644
--- a/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
+++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
@@ -24,6 +24,25 @@
FLASH_DEFINITION =
Platform/Loongson/LoongArchQemuPkg/Loongson.fdf
TTY_TERMINAL = FALSE
+ #
+ # Defines for default states. These can be changed on the command line.
+ # -D FLAG=VALUE
+ DEFINE TTY_TERMINAL= FALSE
+ DEFINE SECURE_BOOT_ENABLE = FALSE
+ DEFINE TPM2_ENABLE = FALSE
+ DEFINE TPM2_CONFIG_ENABLE = FALSE
+
+ #
+ # Network definition
+ #
+ DEFINE NETWORK_IP6_ENABLE = FALSE
+ DEFINE NETWORK_HTTP_BOOT_ENABLE= FALSE
+ DEFINE NETWORK_SNP_ENABLE = FALSE
+ DEFINE NETWORK_TLS_ENABLE = FALSE
+ DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS = TRUE
+ DEFINE NETWORK_ISCSI_ENABLE= FALSE
+
+!include NetworkPkg/NetworkDefines.dsc.inc
#
# Defines for default states. These can be changed on the command line.
@@ -37,16 +56,25 @@
#
GCC:*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
+!include NetworkPkg/NetworkBuildOptions.dsc.inc
[BuildOptions.LOONGARCH64.EDKII.SEC]
*_*_*_CC_FLAGS =
-#[BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION]
-# GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
+[BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION]
+GCC:*_*_LOONGARCH64_DLINK_FLAGS = -z common-page-size=0x1000
[Buil
[edk2-devel] [edk2-platforms][PATCH V1 08/15] Platform/Loongson: Support PEI phase.
Platform PEI module for LoongArch platform initialization. Signed-off-by: xianglai li --- .../Loongson/LoongArchQemuPkg/Loongson.dec| 22 ++ .../Loongson/LoongArchQemuPkg/Loongson.dsc| 66 - .../Loongson/LoongArchQemuPkg/Loongson.fdf| 51 .../LoongArchQemuPkg/PlatformPei/Fv.c | 61 .../LoongArchQemuPkg/PlatformPei/MemDetect.c | 116 .../LoongArchQemuPkg/PlatformPei/Platform.c | 264 ++ .../LoongArchQemuPkg/PlatformPei/Platform.h | 87 ++ .../PlatformPei/PlatformPei.inf | 72 + 8 files changed, 738 insertions(+), 1 deletion(-) create mode 100644 Platform/Loongson/LoongArchQemuPkg/PlatformPei/Fv.c create mode 100644 Platform/Loongson/LoongArchQemuPkg/PlatformPei/MemDetect.c create mode 100644 Platform/Loongson/LoongArchQemuPkg/PlatformPei/Platform.c create mode 100644 Platform/Loongson/LoongArchQemuPkg/PlatformPei/Platform.h create mode 100644 Platform/Loongson/LoongArchQemuPkg/PlatformPei/PlatformPei.inf diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.dec b/Platform/Loongson/LoongArchQemuPkg/Loongson.dec index 248b668fd1..aca53583f1 100644 --- a/Platform/Loongson/LoongArchQemuPkg/Loongson.dec +++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.dec @@ -30,9 +30,31 @@ [PcdsFixedAtBuild, PcdsDynamic] gLoongArchQemuPkgTokenSpaceGuid.PcdFlashPeiFvBase|0x0|UINT64|0x0003 gLoongArchQemuPkgTokenSpaceGuid.PcdFlashPeiFvSize|0x0|UINT32|0x0004 + gLoongArchQemuPkgTokenSpaceGuid.PcdFlashDxeFvBase|0x0|UINT64|0x0008 + gLoongArchQemuPkgTokenSpaceGuid.PcdFlashDxeFvSize|0x0|UINT32|0x0009 gLoongArchQemuPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize|0|UINT32|0x0016 gLoongArchQemuPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|0|UINT32|0x0017 + gLoongArchQemuPkgTokenSpaceGuid.PcdDeviceTreeBase|0x0|UINT64|0x0018 + gLoongArchQemuPkgTokenSpaceGuid.PcdDeviceTreePadding|256|UINT32|0x0019 + gLoongArchQemuPkgTokenSpaceGuid.PcdSecPeiTempRamBase|0|UINT64|0x001c gLoongArchQemuPkgTokenSpaceGuid.PcdSecPeiTempRamSize|0|UINT32|0x001d + gLoongArchQemuPkgTokenSpaceGuid.PcdUefiRamTop|0x0|UINT64|0x001e + gLoongArchQemuPkgTokenSpaceGuid.PcdRamRegionsBottom|0x0|UINT64|0x0022 gLoongArchQemuPkgTokenSpaceGuid.PcdFlashSecFvBase|0x0|UINT64|0x0028 gLoongArchQemuPkgTokenSpaceGuid.PcdFlashSecFvSize|0x0|UINT32|0x0029 + +[PcdsFixedAtBuild.LOONGARCH64] + gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|32|UINT8|0x0010 + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0|UINT8|0x0011 + +[PcdsDynamic] + gLoongArchQemuPkgTokenSpaceGuid.PcdRamSize|0x4000|UINT64|0x0041 + gLoongArchQemuPkgTokenSpaceGuid.PcdFwCfgSelectorAddress|0x0|UINT64|0x0042 + gLoongArchQemuPkgTokenSpaceGuid.PcdFwCfgDataAddress|0x0|UINT64|0x0043 + gLoongArchQemuPkgTokenSpaceGuid.PcdSwapPageDir|0x0|UINT64|0x0044 + gLoongArchQemuPkgTokenSpaceGuid.PcdInvalidPgd|0x0|UINT64|0x0045 + gLoongArchQemuPkgTokenSpaceGuid.PcdInvalidPud|0x0|UINT64|0x0046 + gLoongArchQemuPkgTokenSpaceGuid.PcdInvalidPmd|0x0|UINT64|0x0047 + gLoongArchQemuPkgTokenSpaceGuid.PcdInvalidPte|0x0|UINT64|0x0048 + diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc b/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc index f23fed77e6..09b324c3f7 100644 --- a/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc +++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc @@ -57,22 +57,58 @@ [LibraryClasses.common] PcdLib | MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + TimerLib | Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/TimerLib.inf PrintLib | MdePkg/Library/BasePrintLib/BasePrintLib.inf BaseMemoryLib| MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf BaseLib | MdePkg/Library/BaseLib/BaseLib.inf + PerformanceLib | MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf PeCoffLib| MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + CacheMaintenanceLib | MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf + UefiDecompressLib| MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf PeCoffGetEntryPointLib | MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf IoLib| MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf SerialPortLib| Platform/Loongson/LoongArchQemuPkg/Library/SerialPortLib/SerialPortLib.inf DebugPrintErrorLevelLib | MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf + FdtLib | EmbeddedPkg/Library/FdtLib/FdtLib.inf PeCoffExtraActionLib | MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf DebugAgentLib
[edk2-devel] [edk2-platforms][PATCH V1 09/15] Platform/Loongson: Add CPU DXE driver.
The driver produces EFI_CPU_ARCH_PROTOCOL,
Initialize the exception entry address.
Signed-off-by: xianglai li
---
.../LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c | 382 ++
.../LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.h | 153 +++
.../Drivers/CpuDxe/CpuDxe.inf | 56 +++
.../Drivers/CpuDxe/LoongArch64/Exception.c| 337 +++
.../Drivers/CpuDxe/LoongArch64/Fpu.S | 67 +++
.../Drivers/CpuDxe/LoongArch64/LoongArch.S| 288 +
6 files changed, 1283 insertions(+)
create mode 100644 Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c
create mode 100644 Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.h
create mode 100644 Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.inf
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/LoongArch64/Exception.c
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/LoongArch64/Fpu.S
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/LoongArch64/LoongArch.S
diff --git a/Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c
b/Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c
new file mode 100644
index 00..bff2bd0c0a
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c
@@ -0,0 +1,382 @@
+/** @file
+ CPU DXE Module to produce CPU ARCH Protocol
+
+ Copyright (c) 2021 Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "CpuDxe.h"
+
+BOOLEAN mInterruptState = FALSE;
+
+/*
+ This function flushes the range of addresses from Start to Start+Length
+ from the processor's data cache. If Start is not aligned to a cache line
+ boundary, then the bytes before Start to the preceding cache line boundary
+ are also flushed. If Start+Length is not aligned to a cache line boundary,
+ then the bytes past Start+Length to the end of the next cache line boundary
+ are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be
+ supported. If the data cache is fully coherent with all DMA operations, then
+ this function can just return EFI_SUCCESS. If the processor does not support
+ flushing a range of the data cache, then the entire data cache can be
flushed.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+ @param StartThe beginning physical address to flush from the
processor's data
+ cache.
+ @param Length The number of bytes to flush from the processor's
data cache. This
+ function may flush more bytes than Length specifies
depending upon
+ the granularity of the flush operation that the
processor supports.
+ @param FlushTypeSpecifies the type of flush operation to perform.
+
+ @retval EFI_SUCCESS The address range from Start to Start+Length
was flushed from
+the processor's data cache.
+ @retval EFI_UNSUPPORTEDT The processor does not support the cache flush
type specified
+by FlushType.
+ @retval EFI_DEVICE_ERROR The address range from Start to Start+Length
could not be flushed
+from the processor's data cache.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuFlushCpuDataCache (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESSStart,
+ IN UINT64 Length,
+ IN EFI_CPU_FLUSH_TYPE FlushType
+ )
+{
+
+ switch (FlushType) {
+case EfiCpuFlushTypeWriteBack:
+ WriteBackDataCacheRange ((VOID *) (UINTN)Start, (UINTN)Length);
+ break;
+case EfiCpuFlushTypeInvalidate:
+ InvalidateDataCacheRange ((VOID *) (UINTN)Start, (UINTN)Length);
+ break;
+case EfiCpuFlushTypeWriteBackInvalidate:
+ WriteBackInvalidateDataCacheRange ((VOID *) (UINTN)Start, (UINTN)Length);
+ break;
+default:
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function enables interrupt processing by the processor.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+
+ @retval EFI_SUCCESS Interrupts are enabled on the processor.
+ @retval EFI_DEVICE_ERROR Interrupts could not be enabled on the
processor.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuEnableInterrupt (
+ IN EFI_CPU_ARCH_PROTOCOL *This
+ )
+{
+ EnableInterrupts ();
+
+ mInterruptState = TRUE;
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function disables interrupt processing by the processor.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+
+ @retval EFI_SUCCESS Interrupts are disabled on the processor.
+ @retval EFI_DEVICE_ERROR Interrupts could not be disabled on the
processor.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuDisableInterr
[edk2-devel] [edk2-platforms][PATCH V1 14/15] Platform/Loongson: Add Reset System Lib.
This library provides interfaces related to restart and shutdown.
Signed-off-by: xianglai li
---
.../Library/ResetSystemLib/ResetSystemLib.c | 155 ++
.../Library/ResetSystemLib/ResetSystemLib.inf | 40 +
2 files changed, 195 insertions(+)
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemLib/ResetSystemLib.c
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemLib/ResetSystemLib.inf
diff --git
a/Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemLib/ResetSystemLib.c
b/Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemLib/ResetSystemLib.c
new file mode 100644
index 00..3adcb5193a
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemLib/ResetSystemLib.c
@@ -0,0 +1,155 @@
+/** @file
+ Base Reset System Library Shutdown API implementation for LoongArch.
+
+ Copyright (c) 2021 Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+/**
+ To get acpi base address.
+
+ @param VOID
+
+ @retval acpi base address.
+**/
+UINTN
+LoongArchQemuAcpiBase (VOID)
+{
+ VOID *Address = (VOID*) LS7A_ACPI_REG_BASE;
+
+ if (EfiGoneVirtual ()) {
+/**The RTC controller address and the ResetSystem controller address are
in the same page.
+ The function KVMToolRTCMapMemory has placed the entire page address in
the memory mapping table,
+ do not add additional.
+ * */
+EfiConvertPointer (0, &Address);
+DEBUG ((DEBUG_INFO, "%a: virtual -> 0x%x\n", __FUNCTION__, Address));
+ } else {
+DEBUG ((DEBUG_INFO, "%a: physical -> 0x%x\n", __FUNCTION__, Address));
+ }
+
+ return (UINTN) Address;
+}
+/**
+ Restart device.
+
+ @param VOID
+
+ @retval VOID
+**/
+VOID
+LoongArchQemuReset (VOID)
+{
+
+ UINTN Address;
+
+ DEBUG ((DEBUG_INFO, "%a: LoongArchQemu reset via acpi\n", __FUNCTION__));
+
+ Address = LoongArchQemuAcpiBase ();
+ MmioWrite32 (Address + LS7A_GPE0_RESET_REG, 1);
+ CpuDeadLoop ();
+}
+/**
+ Shutdown device.
+
+ @param VOID
+
+ @retval VOID
+**/
+VOID
+LoongArchQemuShutdown (VOID)
+{
+ UINTN Address;
+
+ //
+ // sleep with S5
+ //
+ Address = LoongArchQemuAcpiBase ();
+ MmioWrite16 (Address + LS7A_PM_CNT_BLK, ACPI_BITMASK_SLEEP_ENABLE);
+ CpuDeadLoop ();
+}
+
+/**
+ This function causes a system-wide reset (cold reset), in which
+ all circuitry within the system returns to its initial state. This type of
reset
+ is asynchronous to system operation and operates without regard to
+ cycle boundaries.
+
+ If this function returns, it means that the system does not support cold
reset.
+**/
+VOID
+EFIAPI ResetCold (VOID)
+{
+ LoongArchQemuReset ();
+}
+
+/**
+ This function causes a system-wide initialization (warm reset), in which all
processors
+ are set to their initial state. Pending cycles are not corrupted.
+
+ If this function returns, it means that the system does not support warm
reset.
+**/
+VOID
+EFIAPI ResetWarm (VOID)
+{
+ LoongArchQemuReset ();
+}
+
+/**
+ This function causes a systemwide reset. The exact type of the reset is
+ defined by the EFI_GUID that follows the Null-terminated Unicode string passed
+ into ResetData. If the platform does not recognize the EFI_GUID in ResetData
+ the platform must pick a supported reset type to perform.The platform may
+ optionally log the parameters from any non-normal reset that occurs.
+
+ @param[in] DataSize The size, in bytes, of ResetData.
+ @param[in] ResetData The data buffer starts with a Null-terminated string,
+followed by the EFI_GUID.
+ **/
+VOID
+EFIAPI
+ResetPlatformSpecific (
+ IN UINTN DataSize,
+ IN VOID*ResetData
+ )
+{
+ LoongArchQemuReset ();
+}
+
+/**
+ This function causes the system to enter a power state equivalent
+ to the ACPI G2/S5 or G3 states.
+
+ If this function returns, it means that the system does not support shutdown
reset.
+**/
+VOID
+EFIAPI ResetShutdown (VOID)
+{
+ LoongArchQemuShutdown ();
+}
+
+
+/**
+ This function causes the system to enter S3 and then wake up immediately.
+
+ If this function returns, it means that the system does not support S3
feature.
+ **/
+VOID
+EFIAPI
+EnterS3WithImmediateWake (
+ VOID
+ )
+{
+ // not implemented
+}
diff --git
a/Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemLib/ResetSystemLib.inf
b/Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemLib/ResetSystemLib.inf
new file mode 100644
index 00..03bb479d73
--- /dev/null
+++
b/Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemLib/ResetSystemLib.inf
@@ -0,0 +1,40 @@
+## @file
+# Base Reset System Library Shutdown API implementation for LoongArch.
+#
+# Copyright (c) 2021 Loongson Technology Corporation Limited. All rights
reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION= 0x0001
[edk2-devel] [edk2-platforms][PATCH V1 10/15] Platform/Loongson: Add PciCpuIoDxe driver.
Add PCI CpuIo protocol.there is no fix translation
offset between I/O port accesses and MMIO accesses.
Add PciCpuIo2Dxe driver to implement EFI_CPU_IO2_PROTOCOL
to add the translation for IO access.
Signed-off-by: xianglai li
---
.../Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 548 ++
.../Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.h | 219 +++
.../Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 40 ++
3 files changed, 807 insertions(+)
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.h
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
diff --git
a/Platform/Loongson/LoongArchQemuPkg/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
b/Platform/Loongson/LoongArchQemuPkg/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
new file mode 100644
index 00..f5154eea7a
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
@@ -0,0 +1,548 @@
+/** @file
+ Produces the CPU I/O 2 Protocol.
+
+ Copyright (c) 2021 Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include "PciCpuIo2Dxe.h"
+
+//
+// Handle for the CPU I/O 2 Protocol
+//
+STATIC EFI_HANDLE mHandle = NULL;
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mInStride[] = {
+ 1, // EfiCpuIoWidthUint8
+ 2, // EfiCpuIoWidthUint16
+ 4, // EfiCpuIoWidthUint32
+ 8, // EfiCpuIoWidthUint64
+ 0, // EfiCpuIoWidthFifoUint8
+ 0, // EfiCpuIoWidthFifoUint16
+ 0, // EfiCpuIoWidthFifoUint32
+ 0, // EfiCpuIoWidthFifoUint64
+ 1, // EfiCpuIoWidthFillUint8
+ 2, // EfiCpuIoWidthFillUint16
+ 4, // EfiCpuIoWidthFillUint32
+ 8 // EfiCpuIoWidthFillUint64
+};
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mOutStride[] = {
+ 1, // EfiCpuIoWidthUint8
+ 2, // EfiCpuIoWidthUint16
+ 4, // EfiCpuIoWidthUint32
+ 8, // EfiCpuIoWidthUint64
+ 1, // EfiCpuIoWidthFifoUint8
+ 2, // EfiCpuIoWidthFifoUint16
+ 4, // EfiCpuIoWidthFifoUint32
+ 8, // EfiCpuIoWidthFifoUint64
+ 0, // EfiCpuIoWidthFillUint8
+ 0, // EfiCpuIoWidthFillUint16
+ 0, // EfiCpuIoWidthFillUint32
+ 0 // EfiCpuIoWidthFillUint64
+};
+
+/**
+ Check parameters to a CPU I/O 2 Protocol service request.
+
+ The I/O operations are carried out exactly as requested. The caller is
responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port
operation.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] AddressThe base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The
number of
+bytes moved is Width size * Count, starting at
Address.
+ @param[in] Buffer For read operations, the destination buffer to
store the results.
+For write operations, the source buffer from which
to write data.
+
+ @retval EFI_SUCCESSThe parameters for this request pass the
checks.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTEDThe Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTEDThe address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+EFI_STATUS
+CpuIoCheckParameter (
+ IN BOOLEANMmioOperation,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ UINT64 MaxCount;
+ UINT64 Limit;
+
+ //
+ // Check to see if Buffer is NULL
+ //
+ if (Buffer == NULL) {
+return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check to see if Width is in the valid range
+ //
+ if ((UINT32)Width >= EfiCpuIoWidthMaximum) {
+return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // For FIFO type, the target address won't increase during the access,
+ // so treat Count as 1
+ //
+ if ((Width >= EfiCpuIoWidthFifoUint8)
+&& (Width <= EfiCpuIoWidthFifoUint64))
+ {
+Count = 1;
+ }
+
+ //
+ // Check to see if Width is in the valid range for I/O Port operations
+ //
+ Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ if ((!MmioOperation)
+&& (Width == EfiCpuIoWidthUint64))
+ {
+return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check to see if Address is aligned
+ //
+ if ((
[edk2-devel] [edk2-platforms][PATCH V1 06/15] Platform/Loongson: Add MmuLib.
Read the memory map information through the QemuFwCfg interface, then build the page table through the memory map information, and finally enable Mmu. Signed-off-by: xianglai li --- .../LoongArchQemuPkg/Include/Library/MmuLib.h | 85 ++ .../LoongArchQemuPkg/Library/MmuLib/Mmu.S | 35 + .../Library/MmuLib/MmuBaseLib.inf | 35 + .../Library/MmuLib/MmuBaseLibPei.inf | 45 + .../Library/MmuLib/MmuLibCore.c | 790 ++ .../Library/MmuLib/MmuLibCore.h | 39 + .../Library/MmuLib/MmuLibCorePei.c| 237 ++ .../LoongArchQemuPkg/Library/MmuLib/mmu.h | 101 +++ .../LoongArchQemuPkg/Library/MmuLib/page.h| 267 ++ .../LoongArchQemuPkg/Library/MmuLib/pte.h | 57 ++ 10 files changed, 1691 insertions(+) create mode 100644 Platform/Loongson/LoongArchQemuPkg/Include/Library/MmuLib.h create mode 100644 Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/Mmu.S create mode 100644 Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/MmuBaseLib.inf create mode 100644 Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/MmuBaseLibPei.inf create mode 100644 Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/MmuLibCore.c create mode 100644 Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/MmuLibCore.h create mode 100644 Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/MmuLibCorePei.c create mode 100644 Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/mmu.h create mode 100644 Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/page.h create mode 100644 Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/pte.h diff --git a/Platform/Loongson/LoongArchQemuPkg/Include/Library/MmuLib.h b/Platform/Loongson/LoongArchQemuPkg/Include/Library/MmuLib.h new file mode 100644 index 00..6c501eca07 --- /dev/null +++ b/Platform/Loongson/LoongArchQemuPkg/Include/Library/MmuLib.h @@ -0,0 +1,85 @@ +/** @file + + Copyright (c) 2021 Loongson Technology Corporation Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Glossary: +- EXC - execute +**/ +#ifndef MMU_LIB_H_ +#define MMU_LIB_H_ +/** + write operation is performed Count times from the first element of Buffer. +Convert EFI Attributes to Loongarch Attributes. + @param[in] EfiAttributes Efi Attributes. + + @retval LoongArch Attributes. +**/ +UINTN +EfiAttributeToLoongArchAttribute ( + IN UINTN EfiAttributes + ); + +/** + Finds the length and memory properties of the memory region corresponding to the specified base address. + + @param[in] BaseAddressTo find the base address of the memory region. + @param[in] EndAddress To find the end address of the memory region. + @param[out] RegionLengthThe length of the memory region found. + @param[out] RegionAttributesProperties of the memory region found. + + @retval EFI_SUCCESSThe corresponding memory area was successfully found + EFI_NOT_FOUNDNo memory area found +**/ +EFI_STATUS +GetLoongArchMemoryRegion ( + IN UINTN BaseAddress, + IN UINTN EndAddress, + OUTUINTN *RegionLength, + OUTUINTN *RegionAttributes + ); + +/** + Sets the Attributes of the specified memory region + + @param[in] BaseAddress The base address of the memory region to set the Attributes. + @param[in] Length The length of the memory region to set the Attributes. + @param[in] Attributes The Attributes to be set. + + @retval EFI_SUCCESSThe Attributes was set successfully + +**/ +EFI_STATUS +LoongArchSetMemoryAttributes ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINTN Length, + IN UINTN Attributes + ); + +/** + Sets the non-executable Attributes for the specified memory region + + @param[in] BaseAddress The base address of the memory region to set the Attributes. + @param[in] Length The length of the memory region to set the Attributes. + + @retval EFI_SUCCESSThe Attributes was set successfully +**/ +EFI_STATUS +LoongArchSetMemoryRegionNoExec ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINTNLength + ); +/** + Create a page table and initialize the MMU. + + @param[] VOID + + @retval VOID +**/ +VOID +EFIAPI +ConfigureMmu ( + VOID + ); +#endif diff --git a/Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/Mmu.S b/Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/Mmu.S new file mode 100644 index 00..a697b54e65 --- /dev/null +++ b/Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/Mmu.S @@ -0,0 +1,35 @@ +#-- +# +# LoongArch for LoongArch +# +# Copyright (c) 2021 Loongson Technology Corporation Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#- + +#ifndef _KERNEL +#define _KERNEL +#endif + +#include "Library/Cpu.h" +#include "LoongArchAsmMacro.h
[edk2-devel] [edk2-platforms][PATCH V1 05/15] Platform/Loongson: Add BpiLib.
This library provides interfaces for creating kernel boot parameters.
Signed-off-by: xianglai li
---
.../LoongArchQemuPkg/Include/Library/Bpi.h| 77 +++
.../LoongArchQemuPkg/Library/BpiLib/Bpi.c | 492 ++
.../Library/BpiLib/BpiLib.inf | 38 ++
3 files changed, 607 insertions(+)
create mode 100644 Platform/Loongson/LoongArchQemuPkg/Include/Library/Bpi.h
create mode 100644 Platform/Loongson/LoongArchQemuPkg/Library/BpiLib/Bpi.c
create mode 100644 Platform/Loongson/LoongArchQemuPkg/Library/BpiLib/BpiLib.inf
diff --git a/Platform/Loongson/LoongArchQemuPkg/Include/Library/Bpi.h
b/Platform/Loongson/LoongArchQemuPkg/Include/Library/Bpi.h
new file mode 100644
index 00..cb2585ccb7
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Include/Library/Bpi.h
@@ -0,0 +1,77 @@
+/** @file
+
+ Copyright (c) 2021 Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Glossary:
+- BPI or Bpi- Boot Parameter Interface
+- MEM or Mem- Memory
+- info or INFO - Information
+- SINFO- Screen information
+**/
+#ifndef BPI_H_
+#define BPI_H_
+
+#include
+#define SYSTEM_RAM 1
+#define SYSTEM_RAM_RESERVED 2
+#define ACPI_TABLE 3
+#define ACPI_NVS4
+#define SYSTEM_PMEM 5
+
+#define MAX_MEM_MAP 128
+
+#define DEBUG_BPI
+
+#define MAP_ENTRY(Entry, Type, Start, Size) \
+ MemMap->Map[(Entry)].MemType = (Type), \
+ MemMap->Map[(Entry)].MemStart = (Start), \
+ MemMap->Map[(Entry)].MemSize = (Size), \
+ Entry++
+
+#pragma pack(1)
+typedef struct _extension_list_hdr{
+ UINT64 Signature;
+ UINT32 Length;
+ UINT8 Revision;
+ UINT8 CheckSum;
+ struct _extension_list_hdr *next;
+}EXT_LIST;
+
+typedef struct _BootParams_Interface {
+ UINT64 Signature; //{'B', 'P', 'I', '0', '1', '0', '0', '1'}
+ EFI_SYSTEM_TABLE *SystemTable;
+ EXT_LIST *ExtList;
+}BootParamsInterface;
+
+typedef struct _MEMMAP_ {
+ UINT32 MemType;
+ UINT64 MemStart;
+ UINT64 MemSize;
+}MEMMAP;
+
+typedef struct _MEM_MAP_ {
+ EXT_LIST Header; // {'M', 'E', 'M'}
+ UINT8MapCount;
+ MEMMAP Map[MAX_MEM_MAP];
+} MEM_MAP;
+
+typedef struct {
+ EXT_LIST Header; // {SI}
+ struct screen_info si;
+}SINFO;
+
+typedef struct {
+ UINT64 BaseAddr;
+ UINT64 Length;
+ UINT32 Type;
+ UINT32 Reserved;
+} LOONGARCH_MEMMAP_ENTRY;
+
+#pragma pack()
+
+typedef struct screen_info SCREEN_INFO;
+
+#endif
+
diff --git a/Platform/Loongson/LoongArchQemuPkg/Library/BpiLib/Bpi.c
b/Platform/Loongson/LoongArchQemuPkg/Library/BpiLib/Bpi.c
new file mode 100644
index 00..c36ade6be9
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Library/BpiLib/Bpi.c
@@ -0,0 +1,492 @@
+/** @file
+
+ Copyright (c) 2021 Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Glossary:
+- Bpi- Boot Parameter Interface
+- Calc - Calculation
+- Mem - memory
+- Ext - Exist
+- FwCfg - firmWare Configure
+- si - Screen Information
+- pos - Position
+**/
+#include "Uefi.h"
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*
+ Calculates the checksum and saves the result at the end of the data.
+
+ @param Buffer A pointer to the data to calculate the checksum.
+ @param Size The number of data involved in calculating the checksum.
+
+ @retval VOID
+ */
+VOID
+BpiChecksum (
+ IN UINT8 *Buffer,
+ IN UINTN Size
+ )
+{
+ UINTN ChecksumOffset;
+
+ //
+ // CheckSum's offset in EXT_LIST is the same as in EXT_LIST's container
(Buffer).
+ //
+ ChecksumOffset = OFFSET_OF (EXT_LIST, CheckSum);
+
+ //
+ // set checksum to 0 first
+ //
+ Buffer[ChecksumOffset] = 0;
+
+ //
+ // Update checksum value
+ //
+ Buffer[ChecksumOffset] = CalculateCheckSum8 (Buffer, Size);
+}
+
+/*
+ Add a linked list node to the linked list.
+
+ @param BpiA pointer to the structure that holds the header of the
linked list.
+ @param Header The address of the node to join the linked list.
+
+ @retval VOID
+ */
+VOID
+EFIAPI
+AddToList (
+ IN BootParamsInterface *Bpi,
+ OUT EXT_LIST *Header
+ )
+{
+ EXT_LIST *LastHeader;
+
+ if (Bpi->ExtList == NULL) {
+Bpi->ExtList = Header;
+ } else {
+for (LastHeader = Bpi->ExtList; LastHeader->next; LastHeader =
LastHeader->next) {
+}
+LastHeader->next = Header;
+BpiChecksum ((UINT8 *)LastHeader, LastHeader->Length);
+ }
+ Header->next = NULL;
+ BpiChecksum ((UINT8 *)Header, Header->Length);
+}
+
+#ifdef DEBUG_BPI
+/*
+ Iterates through the linked list and prints the data in all linked list
nodes.
+
+ @param BpiA pointer to the structure that holds the header of the
linked list.
+
+ @retval VOID
+ */
+VOID
+EFIAPI
+ShowList (
+ IN BootParamsInterface *Bpi
+
[edk2-devel] [edk2-platforms][PATCH V1 00/15] Platform: Add Loongson support
The uploaded code generates firmware to support Linux launching on the LoongArch platform under qemu, So it will run in a virtual machine. LoongArch is the general processor architecture of Loongson. You can get the latest LoongArch documents or LoongArch tools at https://github.com/loongson/. xianglai li (15): Platform/Loongson: Add Serial Port library Platform/Loongson: Support SEC And Add Readme.md Platform/Loongson: Add PeiServicesTablePointerLib. Platform/Loongson: Add QemuFwCfgLib. Platform/Loongson: Add BpiLib. Platform/Loongson: Add MmuLib. Platform/Loongson: Add StableTimerLib. Platform/Loongson: Support PEI phase. Platform/Loongson: Add CPU DXE driver. Platform/Loongson: Add PciCpuIoDxe driver. Platform/Loongson: Add timer Dxe driver. Platform/Loongson: Add RealTime Clock lib. Platform/Loongson: Add Platform Boot Manager Lib. Platform/Loongson: Add Reset System Lib. Platform/Loongson: Support Dxe .../LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c | 382 + .../LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.h | 153 .../Drivers/CpuDxe/CpuDxe.inf | 56 ++ .../Drivers/CpuDxe/LoongArch64/Exception.c| 337 .../Drivers/CpuDxe/LoongArch64/Fpu.S | 67 ++ .../Drivers/CpuDxe/LoongArch64/LoongArch.S| 288 +++ .../Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 548 .../Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.h | 219 + .../Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 40 + .../Drivers/StableTimerDxe/Timer.c| 405 + .../Drivers/StableTimerDxe/Timer.h| 166 .../Drivers/StableTimerDxe/TimerDxe.inf | 40 + .../Include/IndustryStandard/QemuFwCfg.h | 95 +++ .../LoongArchQemuPkg/Include/Library/Bpi.h| 77 ++ .../LoongArchQemuPkg/Include/Library/Cpu.h| 344 .../LoongArchQemuPkg/Include/Library/MmuLib.h | 85 ++ .../Include/Library/QemuFwCfgLib.h| 179 .../Include/Library/StableTimer.h | 42 + .../Include/LoongArchAsmMacro.h | 23 + .../Include/LoongArchQemuPlatform.h | 103 +++ .../LoongArchQemuPkg/Library/BpiLib/Bpi.c | 492 +++ .../Library/BpiLib/BpiLib.inf | 38 + .../LsRealTimeClockLib/LsRealTimeClock.h | 41 + .../LsRealTimeClockLib/LsRealTimeClockLib.c | 343 .../LsRealTimeClockLib/LsRealTimeClockLib.inf | 41 + .../LoongArchQemuPkg/Library/MmuLib/Mmu.S | 35 + .../Library/MmuLib/MmuBaseLib.inf | 35 + .../Library/MmuLib/MmuBaseLibPei.inf | 45 + .../Library/MmuLib/MmuLibCore.c | 790 ++ .../Library/MmuLib/MmuLibCore.h | 39 + .../Library/MmuLib/MmuLibCorePei.c| 237 ++ .../LoongArchQemuPkg/Library/MmuLib/mmu.h | 101 +++ .../LoongArchQemuPkg/Library/MmuLib/page.h| 267 ++ .../LoongArchQemuPkg/Library/MmuLib/pte.h | 57 ++ .../PeiServicesTablePointer.c | 78 ++ .../PeiServicesTablePointerLib.inf| 32 + .../PlatformBootManagerLib/PlatformBm.c | 761 + .../PlatformBootManagerLib/PlatformBm.h | 126 +++ .../PlatformBootManagerLib.inf| 78 ++ .../PlatformBootManagerLib/QemuKernel.c | 449 ++ .../Library/QemuFwCfgLib/QemuFwCfg.c | 119 +++ .../Library/QemuFwCfgLib/QemuFwCfgLib.c | 477 +++ .../Library/QemuFwCfgLib/QemuFwCfgLib.inf | 44 + .../QemuFwCfgLib/QemuFwCfgLibInternal.h | 64 ++ .../Library/ResetSystemLib/ResetSystemLib.c | 155 .../Library/ResetSystemLib/ResetSystemLib.inf | 40 + .../Library/SerialPortLib/SerialPortLib.c | 614 ++ .../Library/SerialPortLib/SerialPortLib.inf | 36 + .../Library/StableTimerLib/Count.S| 26 + .../Library/StableTimerLib/TimerLib.c | 262 ++ .../Library/StableTimerLib/TimerLib.inf | 28 + .../Loongson/LoongArchQemuPkg/Loongson.dec| 72 ++ .../Loongson/LoongArchQemuPkg/Loongson.dsc| 578 + .../Loongson/LoongArchQemuPkg/Loongson.fdf| 345 .../LoongArchQemuPkg/Loongson.fdf.inc | 62 ++ .../LoongArchQemuPkg/PlatformPei/Fv.c | 61 ++ .../LoongArchQemuPkg/PlatformPei/MemDetect.c | 116 +++ .../LoongArchQemuPkg/PlatformPei/Platform.c | 264 ++ .../LoongArchQemuPkg/PlatformPei/Platform.h | 87 ++ .../PlatformPei/PlatformPei.inf | 72 ++ Platform/Loongson/LoongArchQemuPkg/Readme.md | 53 ++ .../LoongArchQemuPkg/Sec/LoongArch64/Start.S | 76 ++ .../Loongson/LoongArchQemuPkg/Sec/SecMain.c | 510 +++ .../Loongson/LoongArchQemuPkg/Sec/SecMain.inf | 49 ++ .../LoongArchQemuPkg/VarStore.fdf.inc | 64 ++ Readme.md | 9 + 66 files changed, 12017 insertions(+) create mode 100644 Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c create mode 100644 Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/
[edk2-devel] [edk2-platforms][PATCH V1 02/15] Platform/Loongson: Support SEC And Add Readme.md
Add SEC Code And Readme.md for LoongArchQemu
Signed-off-by: xianglai li
Signed-off-by: xianglai li
---
.../Include/LoongArchAsmMacro.h | 23 +
.../Loongson/LoongArchQemuPkg/Loongson.dec| 38 ++
.../Loongson/LoongArchQemuPkg/Loongson.dsc| 133 +
.../Loongson/LoongArchQemuPkg/Loongson.fdf| 53 ++
.../LoongArchQemuPkg/Loongson.fdf.inc | 21 +
Platform/Loongson/LoongArchQemuPkg/Readme.md | 53 ++
.../LoongArchQemuPkg/Sec/LoongArch64/Start.S | 76 +++
.../Loongson/LoongArchQemuPkg/Sec/SecMain.c | 510 ++
.../Loongson/LoongArchQemuPkg/Sec/SecMain.inf | 49 ++
Readme.md | 9 +
10 files changed, 965 insertions(+)
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Include/LoongArchAsmMacro.h
create mode 100644 Platform/Loongson/LoongArchQemuPkg/Loongson.dec
create mode 100644 Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
create mode 100644 Platform/Loongson/LoongArchQemuPkg/Loongson.fdf
create mode 100644 Platform/Loongson/LoongArchQemuPkg/Loongson.fdf.inc
create mode 100644 Platform/Loongson/LoongArchQemuPkg/Readme.md
create mode 100644 Platform/Loongson/LoongArchQemuPkg/Sec/LoongArch64/Start.S
create mode 100644 Platform/Loongson/LoongArchQemuPkg/Sec/SecMain.c
create mode 100644 Platform/Loongson/LoongArchQemuPkg/Sec/SecMain.inf
diff --git a/Platform/Loongson/LoongArchQemuPkg/Include/LoongArchAsmMacro.h
b/Platform/Loongson/LoongArchQemuPkg/Include/LoongArchAsmMacro.h
new file mode 100644
index 00..366d4308e8
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Include/LoongArchAsmMacro.h
@@ -0,0 +1,23 @@
+/** @file
+ LoongArch ASM macro definition.
+
+ Copyright (c) 2021, Loongson Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ **/
+
+#ifndef LOONGARCH_ASM_MACRO_H_
+#define LOONGARCH_ASM_MACRO_H_
+
+#include
+
+#define _ASM_FUNC(Name, Section)\
+ .global Name ; \
+ .section #Section, "ax"; \
+ .type Name, %function ; \
+ Name:
+
+#define ASM_FUNC(Name)_ASM_FUNC(ASM_PFX(Name), .text. ## Name)
+
+#endif // __LOONGARCH_ASM_MACRO_H__
diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
b/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
new file mode 100644
index 00..248b668fd1
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
@@ -0,0 +1,38 @@
+## @file
+#
+# Copyright (c) 2021 Loongson Technology Corporation Limited. All rights
reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = LoongArchQemuPkg
+ PACKAGE_GUID = b51d765a-41da-45fc-a537-de3ee785c0f6
+ PACKAGE_VERSION= 0.1
+
+
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER
DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+
+[Includes.common]
+ Include# Root include for the package
+
+[Guids]
+ gLoongArchQemuPkgTokenSpaceGuid = { 0x0e0383ce, 0x0151, 0x4d01, { 0x80,
0x0e, 0x3f, 0xef, 0x8b, 0x27, 0x6d, 0x52 } }
+
+[PcdsFixedAtBuild, PcdsDynamic]
+ gLoongArchQemuPkgTokenSpaceGuid.PcdFlashPeiFvBase|0x0|UINT64|0x0003
+ gLoongArchQemuPkgTokenSpaceGuid.PcdFlashPeiFvSize|0x0|UINT32|0x0004
+
gLoongArchQemuPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize|0|UINT32|0x0016
+
gLoongArchQemuPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|0|UINT32|0x0017
+ gLoongArchQemuPkgTokenSpaceGuid.PcdSecPeiTempRamBase|0|UINT64|0x001c
+ gLoongArchQemuPkgTokenSpaceGuid.PcdSecPeiTempRamSize|0|UINT32|0x001d
+ gLoongArchQemuPkgTokenSpaceGuid.PcdFlashSecFvBase|0x0|UINT64|0x0028
+ gLoongArchQemuPkgTokenSpaceGuid.PcdFlashSecFvSize|0x0|UINT32|0x0029
diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
b/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
new file mode 100644
index 00..f23fed77e6
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
@@ -0,0 +1,133 @@
+## @file
+#
+# Copyright (c) 2021 Loongson Technology Corporation Limited. All rights
reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+###
+[Defines]
+ PLATFORM_NAME = LoongArchQemu
+ PLATFORMPKG_NAME = LoongArchQemu
+ PLATFORM_GUID = 7926ea52-b0dc-
[edk2-devel] [edk2-platforms][PATCH V1 11/15] Platform/Loongson: Add timer Dxe driver.
This driver produces Timer Architectural Protocol,
Registers a timer interrupt and initializes the timer.
Signed-off-by: xianglai li
---
.../Drivers/StableTimerDxe/Timer.c| 405 ++
.../Drivers/StableTimerDxe/Timer.h| 166 +++
.../Drivers/StableTimerDxe/TimerDxe.inf | 40 ++
3 files changed, 611 insertions(+)
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Drivers/StableTimerDxe/Timer.c
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Drivers/StableTimerDxe/Timer.h
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Drivers/StableTimerDxe/TimerDxe.inf
diff --git a/Platform/Loongson/LoongArchQemuPkg/Drivers/StableTimerDxe/Timer.c
b/Platform/Loongson/LoongArchQemuPkg/Drivers/StableTimerDxe/Timer.c
new file mode 100644
index 00..29e10566b5
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Drivers/StableTimerDxe/Timer.c
@@ -0,0 +1,405 @@
+/** @file
+ Timer Architectural Protocol as defined in the DXE CIS
+
+ Copyright (c) 2021 Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include "Library/Cpu.h"
+#include
+#include
+#include "Timer.h"
+#include
+#include
+
+//
+// The handle onto which the Timer Architectural Protocol will be installed
+//
+EFI_HANDLEmTimerHandle = NULL;
+EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
+
+//
+// The Timer Architectural Protocol that this driver produces
+//
+EFI_TIMER_ARCH_PROTOCOL mTimer = {
+ TimerDriverRegisterHandler,
+ TimerDriverSetTimerPeriod,
+ TimerDriverGetTimerPeriod,
+ TimerDriverGenerateSoftInterrupt
+};
+
+//
+// Pointer to the CPU Architectural Protocol instance
+//
+EFI_CPU_ARCH_PROTOCOL *mCpu;
+
+//
+// The notification function to call on every timer interrupt.
+// A bug in the compiler prevents us from initializing this here.
+//
+EFI_TIMER_NOTIFY mTimerNotifyFunction;
+
+//
+// The current period of the timer interrupt
+//
+volatile UINT64 mTimerPeriod = 0;
+volatile UINT64 mTimerTicks = 0;
+
+//
+// Const frequence in Hz
+//
+extern UINT32 StableTimerFreq;
+
+/**
+ Sets the counter value for timer.
+
+ @param CountThe 16-bit counter value to program into stable timer.
+
+ @retval VOID
+**/
+VOID
+SetPitCount (
+ IN UINT64 Count
+ )
+{
+ if (Count <= 4) {
+return;
+ }
+
+ Count &= LOONGARCH_CSR_TMCFG_TIMEVAL;
+ Count |= LOONGARCH_CSR_TMCFG_EN | LOONGARCH_CSR_TMCFG_PERIOD;
+ LOONGARCH_CSR_WRITEQ (Count, LOONGARCH_CSR_TMCFG);
+}
+
+/**
+ Timer Interrupt Handler.
+
+ @param InterruptTypeThe type of interrupt that occurred
+ @param SystemContextA pointer to the system context when the interrupt
occurred
+
+ @retval VOID
+**/
+VOID
+EFIAPI
+TimerInterruptHandler (
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ )
+{
+ EFI_TPL OriginalTPL;
+
+ OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+
+ //
+ // Clear interrupt.
+ //
+ LOONGARCH_CSR_WRITEQ (0x1, LOONGARCH_CSR_TINTCLR);
+
+ if (mTimerNotifyFunction != NULL) {
+//
+// @bug : This does not handle missed timer interrupts
+//
+mTimerNotifyFunction (mTimerPeriod);
+ }
+
+ gBS->RestoreTPL (OriginalTPL);
+}
+
+/**
+
+ This function registers the handler NotifyFunction so it is called every time
+ the timer interrupt fires. It also passes the amount of time since the last
+ handler call to the NotifyFunction. If NotifyFunction is NULL, then the
+ handler is unregistered. If the handler is registered, then EFI_SUCCESS is
+ returned. If the CPU does not support registering a timer interrupt handler,
+ then EFI_UNSUPPORTED is returned. If an attempt is made to register a
handler
+ when a handler is already registered, then EFI_ALREADY_STARTED is returned.
+ If an attempt is made to unregister a handler when a handler is not
registered,
+ then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to
+ register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
+ is returned.
+
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param NotifyFunction The function to call when a timer interrupt fires.
This
+ function executes at TPL_HIGH_LEVEL. The DXE Core
will
+ register a handler for the timer interrupt, so it
can know
+ how much time has passed. This information is used
to
+ signal timer based events. NULL will unregister the
handler.
+
+ @retvalEFI_SUCCESSThe timer handler was registered.
+ @retvalEFI_UNSUPPORTEDThe platform does not support timer
interrupts.
+ @retvalEFI_ALREADY_STARTEDNotifyFunction is not NULL, and a
handler is already
+registered.
+ @retvalEFI_INVALID_PARAMETER NotifyFunction is NULL, and a han
[edk2-devel] [edk2-platforms][PATCH V1 07/15] Platform/Loongson: Add StableTimerLib.
This library provides a delay interface and a timing interface.
Signed-off-by: xianglai li
---
.../Include/Library/StableTimer.h | 42 +++
.../Library/StableTimerLib/Count.S| 26 ++
.../Library/StableTimerLib/TimerLib.c | 262 ++
.../Library/StableTimerLib/TimerLib.inf | 28 ++
4 files changed, 358 insertions(+)
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Include/Library/StableTimer.h
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/Count.S
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/TimerLib.c
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/TimerLib.inf
diff --git a/Platform/Loongson/LoongArchQemuPkg/Include/Library/StableTimer.h
b/Platform/Loongson/LoongArchQemuPkg/Include/Library/StableTimer.h
new file mode 100644
index 00..bd6a1eb90f
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Include/Library/StableTimer.h
@@ -0,0 +1,42 @@
+/** @file
+
+ Copyright (c) 2021 Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Glossary:
+- Csr- Cpu Status Register
+- Calc - Calculation
+- Freq - frequency
+**/
+
+#ifndef STABLE_TIMER_H_
+#define STABLE_TIMER_H_
+#include "Library/Cpu.h"
+
+/**
+ Gets the timer count value.
+
+ @param[] VOID
+
+ @retval timer count value.
+**/
+UINTN
+EFIAPI
+CsrReadTime (
+ VOID
+ );
+
+/**
+ Calculate the timer frequency.
+
+ @param[] VOID
+
+ @retval Timer frequency.
+**/
+UINT32
+EFIAPI
+CalcConstFreq (
+ VOID
+ );
+#endif
diff --git a/Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/Count.S
b/Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/Count.S
new file mode 100644
index 00..42f878caf8
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/Count.S
@@ -0,0 +1,26 @@
+#--
+#
+# Count for LoongArch
+#
+# Copyright (c) 2021 Loongson Technology Corporation Limited. All rights
reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#--
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include "Library/Cpu.h"
+#include "LoongArchAsmMacro.h"
+#
+# Set cpu interrupts
+# @param A0 The interrupt number
+#
+ASM_FUNC(CpuSetIP)
+csrrd T0, LOONGARCH_CSR_ECFG
+or T0, T0, A0
+csrwr T0, LOONGARCH_CSR_ECFG
+jirlZERO, RA,0
+
diff --git
a/Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/TimerLib.c
b/Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/TimerLib.c
new file mode 100644
index 00..21e3749ee6
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/TimerLib.c
@@ -0,0 +1,262 @@
+/** @file
+ Generic LoongArch implementation of TimerLib.h
+
+ Copyright (c) 2021 Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Glossary:
+- Freq - Frequency
+- Csr - Cpu Status Register
+- calc - calculate
+**/
+
+#include
+#include
+#include
+#include
+#include "Library/StableTimer.h"
+#include "Library/Cpu.h"
+
+UINT32 StableTimerFreq = 0;
+
+/**
+ Gets the timer count value.
+
+ @param[] VOID
+
+ @retval timer count value.
+**/
+UINTN
+EFIAPI
+CsrReadTime (
+ VOID
+ )
+{
+ UINTN Value = 0;
+ __asm__ __volatile__(
+ " rdtime.d %0, $r0\n"
+ : "=r" (Value));
+ return Value;
+}
+
+/**
+ Calculate the timer frequency.
+
+ @param[] VOID
+
+ @retval Timer frequency.
+**/
+UINT32
+EFIAPI
+CalcConstFreq (
+ VOID
+ )
+{
+ UINT32 Result;
+ UINT32 BaseFreq;
+ UINT32 ClockMultiplier;
+ UINT32 ClockDivide;
+
+ LOONGARCH_GET_CPUCFG (BaseFreq, LOONGARCH_CPUCFG4);
+ LOONGARCH_GET_CPUCFG (Result, LOONGARCH_CPUCFG5);
+ ClockMultiplier = Result & 0x;
+ ClockDivide = (Result >> 16) & 0x;
+
+ if ((!BaseFreq)
+|| (!ClockMultiplier)
+|| (!ClockDivide))
+ {
+return 0;
+ }
+ else {
+return (BaseFreq * ClockMultiplier / ClockDivide);
+ }
+}
+/**
+ Get the timer frequency.
+
+ @param[] VOID
+
+ @retval Timer frequency.
+**/
+UINT32
+EFIAPI
+GetFreq (
+ VOID
+ )
+{
+ if (StableTimerFreq) {
+ } else {
+StableTimerFreq = CalcConstFreq ();
+ }
+
+ return StableTimerFreq;
+}
+
+/**
+ Stalls the CPU for at least the given number of microseconds.
+
+ Stalls the CPU for the number of microseconds specified by MicroSeconds.
+
+ @param MicroSeconds The minimum number of microseconds to delay.
+
+ @return MicroSeconds
+
+**/
+UINTN
+EFIAPI
+MicroSecondDelay (
+ IN UINTN MicroSeconds
+ )
+{
+
+ UINTN Count;
+ UINTN Ticks;
+ UINTN Start;
+ UINTN End;
+
+ Count = GetFreq ();
+ Count = (Count * MicroSeconds) / 100;
+ Start = CsrReadTime ();
+ End = Start + Count;
+
+ do {
+Ticks = Cs
[edk2-devel] [edk2-platforms][PATCH V1 03/15] Platform/Loongson: Add PeiServicesTablePointerLib.
Use a register to save PeiServicesTable pointer,
This lib Provides PeiServicesTable pointer saving
and retrieval services.
Signed-off-by: xianglai li
---
.../PeiServicesTablePointer.c | 78 +++
.../PeiServicesTablePointerLib.inf| 32
2 files changed, 110 insertions(+)
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
diff --git
a/Platform/Loongson/LoongArchQemuPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c
b/Platform/Loongson/LoongArchQemuPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c
new file mode 100644
index 00..068960d4ce
--- /dev/null
+++
b/Platform/Loongson/LoongArchQemuPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c
@@ -0,0 +1,78 @@
+/** @file
+ PEI Services Table Pointer Library.
+
+ Copyright (c) 2021 Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include
+#include
+#include
+#include "Library/Cpu.h"
+
+/**
+ Caches a pointer PEI Services Table.
+
+ Caches the pointer to the PEI Services Table specified by
PeiServicesTablePointer
+ in a platform specific manner.
+
+ If PeiServicesTablePointer is NULL, then ASSERT ().
+
+ @paramPeiServicesTablePointer The address of PeiServices pointer.
+**/
+VOID
+EFIAPI
+SetPeiServicesTablePointer (
+ IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer
+ )
+{
+ LOONGARCH_CSR_WRITEQ ((UINTN)PeiServicesTablePointer, LOONGARCH_CSR_KS0);
+}
+
+/**
+ Retrieves the cached value of the PEI Services Table pointer.
+
+ Returns the cached value of the PEI Services Table pointer in a CPU specific
manner
+ as specified in the CPU binding section of the Platform Initialization
Pre-EFI
+ Initialization Core Interface Specification.
+
+ If the cached PEI Services Table pointer is NULL, then ASSERT ().
+
+ @return The pointer to PeiServices.
+**/
+CONST EFI_PEI_SERVICES **
+EFIAPI
+GetPeiServicesTablePointer (
+ VOID
+ )
+{
+ UINTN val;
+
+ LOONGARCH_CSR_READQ (val, LOONGARCH_CSR_KS0);
+ return (CONST EFI_PEI_SERVICES **)val;
+}
+
+/**
+Perform CPU specific actions required to migrate the PEI Services Table
+pointer from temporary RAM to permanent RAM.
+
+For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes
+immediately preceding the Interrupt Descriptor Table (IDT) in memory.
+For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes
+immediately preceding the Interrupt Descriptor Table (IDT) in memory.
+For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in
+a dedicated CPU register. This means that there is no memory storage
+associated with storing the PEI Services Table pointer, so no additional
+migration actions are required for Itanium or ARM CPUs.
+
+**/
+VOID
+EFIAPI
+MigratePeiServicesTablePointer (
+VOID
+)
+{
+ return;
+}
diff --git
a/Platform/Loongson/LoongArchQemuPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
b/Platform/Loongson/LoongArchQemuPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
new file mode 100644
index 00..6fe76d1351
--- /dev/null
+++
b/Platform/Loongson/LoongArchQemuPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
@@ -0,0 +1,32 @@
+## @file
+# PEI Services Table Pointer Library.
+#
+# Copyright (c) 2021 Loongson Technology Corporation Limited. All rights
reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+[Defines]
+ INF_VERSION= 0x00010005
+ BASE_NAME = PeiServicesTablePointerLib
+ FILE_GUID = C3C9C4ED-EB8A-4548-BE1B-ABB0B6F35B1E
+ MODULE_TYPE= PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PeiServicesTablePointerLib|PEIM PEI_CORE SEC
+
+#
+# VALID_ARCHITECTURES = LOONGARCH64
+#
+
+[Sources]
+ PeiServicesTablePointer.c
+
+[Packages]
+ Platform/Loongson/LoongArchQemuPkg/Loongson.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ DebugLib
+
+[Pcd]
+
--
2.27.0
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[edk2-devel] [edk2-platforms][PATCH V1 01/15] Platform/Loongson: Add Serial Port library
Serial Port library for LoongarchQemuPkg Signed-off-by: xianglai li --- .../LoongArchQemuPkg/Include/Library/Cpu.h| 344 ++ .../Include/LoongArchQemuPlatform.h | 103 +++ .../Library/SerialPortLib/SerialPortLib.c | 614 ++ .../Library/SerialPortLib/SerialPortLib.inf | 36 + 4 files changed, 1097 insertions(+) create mode 100644 Platform/Loongson/LoongArchQemuPkg/Include/Library/Cpu.h create mode 100644 Platform/Loongson/LoongArchQemuPkg/Include/LoongArchQemuPlatform.h create mode 100644 Platform/Loongson/LoongArchQemuPkg/Library/SerialPortLib/SerialPortLib.c create mode 100644 Platform/Loongson/LoongArchQemuPkg/Library/SerialPortLib/SerialPortLib.inf diff --git a/Platform/Loongson/LoongArchQemuPkg/Include/Library/Cpu.h b/Platform/Loongson/LoongArchQemuPkg/Include/Library/Cpu.h new file mode 100644 index 00..de466b7c6f --- /dev/null +++ b/Platform/Loongson/LoongArchQemuPkg/Include/Library/Cpu.h @@ -0,0 +1,344 @@ +/** @file + + Copyright (c) 2021 Loongson Technology Corporation Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Glossary: +- EXC - Exception +- INT - Interrupt +- FPU - Floating Point Unit +- CSR - CPU Status Register +- READQ - Read Quad Word +**/ +#ifndef LOONGARCH_CPU_H_ +#define LOONGARCH_CPU_H_ + +/* Exception types decoded by machdep exception decoder */ +#define EXC_INT 0 /* HW interrupt */ +#define EXC_TLBL1 /* TLB miss on a load */ +#define EXC_TLBS2 /* TLB miss on a store */ +#define EXC_TLBI3 /* TLB miss on a ifetch */ +#define EXC_TLBM4 /* TLB modified fault */ +#define EXC_TLBRI 5 /* TLB Read-Inhibit exception */ +#define EXC_TLBXI 6 /* TLB Execution-Inhibit exception */ +#define EXC_TLBPE 7 /* TLB Privilege Error */ +#define EXC_ADE 8 /* Address Error */ +#define EXC_ALE 9 /* Unalign Access */ +#define EXC_OOB 10 /* Out of bounds */ +#define EXC_SYS 11 /* System call */ +#define EXC_BP 12 /* Breakpoint */ +#define EXC_INE 13 /* Inst. Not Exist */ +#define EXC_IPE 14 /* Inst. Privileged Error */ +#define EXC_FPDIS 15 /* FPU Disabled */ +#define EXC_LSXDIS 16 /* LSX Disabled */ +#define EXC_LASXDIS 17 /* LASX Disabled */ +#define EXC_FPE 18 /* Floating Point Exception */ +#define EXC_WATCH 19 /* Watch address reference */ +#define EXC_BAD 255 /* Undecodeable */ + +#define COPY_SIGCODE// copy sigcode above user stack in exec +#define ZERO $r0 /* wired zero */ +#define RA$r1 /* return address */ +#define GP$r2 /* global pointer - caller saved for PIC */ +#define SP$r3 /* stack pointer */ +#define V0$r4 /* return value - caller saved */ +#define V1$r5 +#define A0$r4 /* argument registers */ +#define A1$r5 +#define A2$r6 +#define A3$r7 +#define A4$r8 /* arg reg 64 bit; caller saved in 32 bit */ +#define A5$r9 +#define A6$r10 +#define A7$r11 +#define T0$r12 /* caller saved */ +#define T1$r13 +#define T2$r14 +#define T3$r15 +#define T4$r16 /* callee saved */ +#define T5$r17 +#define T6$r18 +#define T7$r19 +#define T8$r20 /* caller saved */ +#define TP$r21 /* TLS */ +#define FP$r22 /* frame pointer */ +#define S0$r23 /* callee saved */ +#define S1$r24 +#define S2$r25 +#define S3$r26 +#define S4$r27 +#define S5$r28 +#define S6$r29 +#define S7$r30 +#define S8$r31 /* callee saved */ + +#define FCSR0 $r0 + +// +// Location of the saved registers relative to ZERO. +// Usage is p->p_regs[XX]. +// +#define RA_NUM 1 +#define GP_NUM 2 +#define SP_NUM 3 +#define A0_NUM 4 +#define A1_NUM 5 +#define A2_NUM 6 +#define A3_NUM 7 +#define A4_NUM 8 +#define A5_NUM 9 +#define A6_NUM 10 +#define A7_NUM 11 +#define T0_NUM 12 +#define T1_NUM 13 +#define T2_NUM 14 +#define T3_NUM 15 +#define T4_NUM 16 +#define T5_NUM 17 +#define T6_NUM 18 +#define T7_NUM 19 +#define T8_NUM 20 +#define TP_NUM 21 +#define FP_NUM 22 +#define S0_NUM 23 +#define S1_NUM 24 +#define S2_NUM 25 +#define S3_NUM 26 +#define S4_NUM 27 +#define S5_NUM 28 +#define S6_NUM 29 +#define S7_NUM 30 +#define S8_NUM 31 + +#define FP0_NUM0 +#define FP1_NUM1 +#define FP2_NUM2 +#define FP3_NUM3 +#define FP4_NUM4 +#define FP5_NUM5 +#define FP6_NUM6 +#define FP7_NUM7 +#define FP8_NUM8 +#define FP9_NUM9 +#define FP10_NUM 10 +#define FP11_NUM 11 +#define FP12_NUM 12 +#define FP13_NUM 13 +#define FP14_NUM 14 +#define FP15_NUM 15 +#define FP16_NUM 16 +#define FP17_NUM 17 +#define FP18_NUM 18 +#define FP19_NUM 19 +#define FP20_NUM 20
[edk2-devel] [PATCH v3 1/1] CryptoPkg: Add new hash algorithm ParallelHash256HashAll in BaseCryptLib.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3596
Parallel hash function ParallelHash256HashAll, as defined in NIST's
Special Publication 800-185, published December 2016. It utilizes
multi-process to calculate the digest.
Some modifications to pass CI test.
Cc: Jiewen Yao
Cc: Jian J Wang
Cc: Xiaoyu Lu
Cc: Guomin Jiang
Cc: Siyuan Fu
Cc: Zhihao Li
Signed-off-by: Zhihao Li
---
CryptoPkg/Library/BaseCryptLib/Hash/CryptCShake256.c | 381
CryptoPkg/Library/BaseCryptLib/Hash/CryptParallelHash.c | 350
++
CryptoPkg/Library/BaseCryptLib/Hash/CryptSha3.c | 166
+
CryptoPkg/Library/BaseCryptLib/Hash/CryptXkcp.c | 107
++
CryptoPkg/Test/UnitTest/Library/BaseCryptLib/ParallelhashTests.c | 145
CryptoPkg/Include/Library/BaseCryptLib.h | 31 +-
CryptoPkg/Library/BaseCryptLib/InternalCryptLib.h | 2 +-
CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf| 8 +-
CryptoPkg/Library/Include/CrtLibSupport.h | 38 +-
CryptoPkg/Test/CryptoPkgHostUnitTest.dsc | 3 +
CryptoPkg/Test/UnitTest/Library/BaseCryptLib/TestBaseCryptLibHost.inf | 4 +
11 files changed, 1231 insertions(+), 4 deletions(-)
diff --git a/CryptoPkg/Library/BaseCryptLib/Hash/CryptCShake256.c
b/CryptoPkg/Library/BaseCryptLib/Hash/CryptCShake256.c
new file mode 100644
index ..6b26d74d5413
--- /dev/null
+++ b/CryptoPkg/Library/BaseCryptLib/Hash/CryptCShake256.c
@@ -0,0 +1,381 @@
+/** @file
+ cSHAKE-256 Digest Wrapper Implementations.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "InternalCryptLib.h"
+
+#define CSHAKE256_SECURITY_STRENGTH 256
+#define CSHAKE256_RATE_IN_BYTES 136
+
+const CHAR8 mZeroPadding[CSHAKE256_RATE_IN_BYTES] = { 0 };
+
+/**
+ Encode function from XKCP.
+
+ Encodes the input as a byte string in a way that can be unambiguously parsed
+ from the beginning of the string by inserting the length of the byte string
+ before the byte string representation of input.
+
+ @param[out] EncBuf Result of left encode.
+ @param[in] Value Input of left encode.
+
+ @retval EncLen Size of encode result in bytes.
+**/
+UINTN
+EFIAPI
+LeftEncode (
+ OUT UINT8 *EncBuf,
+ IN UINTN Value
+ );
+
+/**
+ Encode function from XKCP.
+
+ Encodes the input as a byte string in a way that can be unambiguously parsed
+ from the end of the string by inserting the length of the byte string after
+ the byte string representation of input.
+
+ @param[out] EncBuf Result of right encode.
+ @param[in] Value Input of right encode.
+
+ @retval EncLen Size of encode result in bytes.
+**/
+UINTN
+EFIAPI
+RightEncode (
+ OUT UINT8 *EncBuf,
+ IN UINTN Value
+ );
+
+/**
+ Keccak initial fuction.
+
+ Set up state with specified capacity.
+
+ @param[out] Context Pointer to the context being initialized.
+ @param[in] Pad Delimited Suffix.
+ @param[in] BlockSize Size of context block.
+ @param[in] MessageDigestLen Size of message digest in bytes.
+
+ @retval 1 Initialize successfully.
+ @retval 0 Fail to initialize.
+**/
+UINT8
+EFIAPI
+KeccakInit (
+ OUT Keccak1600_Ctx *Context,
+ IN UINT8 Pad,
+ IN UINTN BlockSize,
+ IN UINTN MessageDigstLen
+ );
+
+/**
+ Sha3 update fuction.
+
+ This function performs Sha3 digest on a data buffer of the specified size.
+ It can be called multiple times to compute the digest of long or
discontinuous data streams.
+
+ @param[in,out] Context Pointer to the Keccak context.
+ @param[in] Data Pointer to the buffer containing the data to be
hashed.
+ @param[in] DataSize Size of Data buffer in bytes.
+
+ @retval 1 Update successfully.
+**/
+UINT8
+EFIAPI
+Sha3Update (
+ IN OUT Keccak1600_Ctx *Context,
+ IN const VOID *Data,
+ IN UINTN DataSize
+ );
+
+/**
+ Completes computation of Sha3 message digest.
+
+ This function completes sha3 hash computation and retrieves the digest value
into
+ the specified memory. After this function has been called, the keccak
context cannot
+ be used again.
+
+ @param[in, out] ContextPointer to the keccak context.
+ @param[out] MessageDigest Pointer to a buffer that receives the
message digest.
+
+ @retval 1 Meaasge digest computation succeeded.
+**/
+UINT8
+EFIAPI
+Sha3Final (
+ IN OUT Keccak1600_Ctx *Context,
+ OUTUINT8 *MessageDigest
+ );
+
+/**
+ CShake256 initial function.
+
+ Initializes user-supplied memory pointed by CShake256Context as cSHAKE-256
hash context for
+ subsequent use.
+
+ @param[out] CShake256Context Pointer to cSHAKE-256 context being
initialized.
+ @param[in] OutputLen The desired
