[edk2-devel] [PATCH v7 1/1] CryptoPkg: Add new hash algorithm ParallelHash256HashAll in BaseCryptLib.

[Li, Zhihao]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3596

Parallel hash function ParallelHash256HashAll, as defined in NIST's
Special Publication 800-185, published December 2016. It utilizes
multi-process to calculate the digest.

Passed CI test.
Onprotocol version code passed test.

Cc: Jiewen Yao 
Cc: Jian J Wang 
Cc: Xiaoyu Lu 
Cc: Guomin Jiang 
Cc: Siyuan Fu 

Signed-off-by: Zhihao Li 
---
 CryptoPkg/Driver/Crypto.c | 121 
-
 CryptoPkg/Library/BaseCryptLib/Hash/CryptCShake256.c  | 282 

 CryptoPkg/Library/BaseCryptLib/Hash/CryptParallelHash.c   | 278 
+++
 CryptoPkg/Library/BaseCryptLib/Hash/CryptParallelHashNull.c   |  40 +++
 CryptoPkg/Library/BaseCryptLib/Hash/CryptSha3.c   | 166 

 CryptoPkg/Library/BaseCryptLib/Hash/CryptXkcp.c   | 107 

 CryptoPkg/Library/BaseCryptLibNull/Hash/CryptParallelHashNull.c   |  40 +++
 CryptoPkg/Library/BaseCryptLibOnProtocolPpi/CryptLib.c|  34 ++-
 CryptoPkg/Test/UnitTest/Library/BaseCryptLib/ParallelhashTests.c  | 145 
++
 CryptoPkg/CryptoPkg.ci.yaml   |   4 +-
 CryptoPkg/Include/Library/BaseCryptLib.h  |  31 ++-
 CryptoPkg/Include/Pcd/PcdCryptoServiceFamilyEnable.h  |  15 +-
 CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf   |   3 +-
 CryptoPkg/Library/BaseCryptLib/Hash/CryptParallelHash.h   | 201 
++
 CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf|   3 +-
 CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf|   3 +-
 CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf|   8 +-
 CryptoPkg/Library/BaseCryptLibNull/BaseCryptLibNull.inf   |   3 +-
 CryptoPkg/Library/Include/CrtLibSupport.h |   3 +-
 CryptoPkg/Private/Protocol/Crypto.h   |  35 ++-
 CryptoPkg/Test/CryptoPkgHostUnitTest.dsc  |   4 +
 CryptoPkg/Test/UnitTest/Library/BaseCryptLib/TestBaseCryptLibHost.inf |   4 +
 22 files changed, 1516 insertions(+), 14 deletions(-)

diff --git a/CryptoPkg/Driver/Crypto.c b/CryptoPkg/Driver/Crypto.c
index d5d6aa8e5820..76cb9f4da0a4 100644
--- a/CryptoPkg/Driver/Crypto.c
+++ b/CryptoPkg/Driver/Crypto.c
@@ -3,7 +3,7 @@
   from BaseCryptLib and TlsLib.
 
   Copyright (C) Microsoft Corporation. All rights reserved.
-  Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
+  Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -4470,6 +4470,118 @@ CryptoServiceTlsGetCertRevocationList (
   return CALL_BASECRYPTLIB (TlsGet.Services.CertRevocationList, 
TlsGetCertRevocationList, (Data, DataSize), EFI_UNSUPPORTED);
 }
 
+/**
+  Carries out the RSA-SSA signature generation with EMSA-PSS encoding scheme.
+
+  This function carries out the RSA-SSA signature generation with EMSA-PSS 
encoding scheme defined in
+  RFC 8017.
+  Mask generation function is the same as the message digest algorithm.
+  If the Signature buffer is too small to hold the contents of signature, FALSE
+  is returned and SigSize is set to the required buffer size to obtain the 
signature.
+
+  If RsaContext is NULL, then return FALSE.
+  If Message is NULL, then return FALSE.
+  If MsgSize is zero or > INT_MAX, then return FALSE.
+  If DigestLen is NOT 32, 48 or 64, return FALSE.
+  If SaltLen is not equal to DigestLen, then return FALSE.
+  If SigSize is large enough but Signature is NULL, then return FALSE.
+  If this interface is not supported, then return FALSE.
+
+  @param[in]  RsaContext   Pointer to RSA context for signature generation.
+  @param[in]  Message  Pointer to octet message to be signed.
+  @param[in]  MsgSize  Size of the message in bytes.
+  @param[in]  DigestLenLength of the digest in bytes to be used for 
RSA signature operation.
+  @param[in]  SaltLen  Length of the salt in bytes to be used for PSS 
encoding.
+  @param[out] SignaturePointer to buffer to receive RSA PSS signature.
+  @param[in, out] SigSize  On input, the size of Signature buffer in bytes.
+   On output, the size of data returned in 
Signature buffer in bytes.
+
+  @retval  TRUE   Signature successfully generated in RSASSA-PSS.
+  @retval  FALSE  Signature generation failed.
+  @retval  FALSE  SigSize is too small.
+  @retval  FALSE  This interface is not supported.
+
+**/
+BOOLEAN
+EFIAPI
+CryptoServiceRsaPssSign (
+  IN  VOID *RsaContext,
+  IN  CONST UINT8  *Message,
+  IN  UINTNMsgSize,
+  IN  UINT16   DigestLen,
+  IN  UINT16   SaltLen,
+  OUT UINT8*Signature,
+  IN OUT  UINTN*SigSize
+  )
+{
+  return 

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回复: [edk2-devel] 回复: [PATCH v3 1/1] MdePkg/Include: Smbios Specification 3.5.0 changes

[gaoliming]

Create PR https://github.com/tianocore/edk2/pull/2647 to merge it.

Thanks
Liming
> -邮件原件-
> 发件人: devel@edk2.groups.io  代表 gaoliming
> 发送时间: 2022年3月8日 9:42
> 收件人: 'Abdul Lateef Attar' ; devel@edk2.groups.io
> 抄送: 'Michael D Kinney' ; 'Zhiguang Liu'
> 
> 主题: [edk2-devel] 回复: [PATCH v3 1/1] MdePkg/Include: Smbios
> Specification 3.5.0 changes
> 
> Reviewed-by: Liming Gao 
> 
> > -邮件原件-
> > 发件人: abdullateef.at...@amd.com  代表
> > Abdul Lateef Attar
> > 发送时间: 2022年2月24日 23:50
> > 收件人: devel@edk2.groups.io
> > 抄送: Michael D Kinney ; Liming Gao
> > ; Zhiguang Liu 
> > 主题: [PATCH v3 1/1] MdePkg/Include: Smbios Specification 3.5.0 changes
> >
> > Adds following changes
> > 1) Added support for manufacturing mode in
> >BIOS Characteristics Extension Byte 2.
> > 2) Added support for slot height in
> >System Slot Table (type 9).
> > 3) Updated Built-in pointing device interface with
> >USB, I2C and SPI.
> > 4) Updates Onboard Devices Extended Information with
> >wireless LAN, bluetooth, WWAN, eMMC, NVMe and UFC.
> > 5) Added new table Firmware Inventory Information (Type 45)
> >and its corresponding enum values.
> > 6) Added new table String Property Table (Type 46)
> >and its corresponding enum values.
> >
> > Cc: Michael D Kinney 
> > Cc: Liming Gao 
> > Cc: Zhiguang Liu 
> > Signed-off-by: Abdul Lateef Attar 
> > ---
> >  MdePkg/Include/IndustryStandard/SmBios.h | 144
> +++-
> >  1 file changed, 140 insertions(+), 4 deletions(-)
> >
> > diff --git a/MdePkg/Include/IndustryStandard/SmBios.h
> > b/MdePkg/Include/IndustryStandard/SmBios.h
> > index 828ea6d753c2..2b1567b0528b 100644
> > --- a/MdePkg/Include/IndustryStandard/SmBios.h
> > +++ b/MdePkg/Include/IndustryStandard/SmBios.h
> > @@ -1,9 +1,10 @@
> >  /** @file
> >
> > -  Industry Standard Definitions of SMBIOS Table Specification v3.3.0.
> >
> > +  Industry Standard Definitions of SMBIOS Table Specification v3.5.0.
> >
> >
> >
> >  Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
> >
> >  (C) Copyright 2015-2017 Hewlett Packard Enterprise Development
> LP
> >
> >  (C) Copyright 2015 - 2019 Hewlett Packard Enterprise Development
> LP
> >
> > +Copyright (c) 2022, AMD Incorporated. All rights reserved.
> >
> >  SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> >
> >
> >  **/
> >
> > @@ -94,6 +95,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> >  #define SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE
> > 42
> >
> >  #define SMBIOS_TYPE_TPM_DEVICE
> 43
> >
> >  #define SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION
> 44
> >
> > +#define SMBIOS_TYPE_FIRMWARE_INVENTORY_INFORMATION
> > 45
> >
> > +#define SMBIOS_TYPE_STRING_PROPERTY_INFORMATION
> 46
> >
> >
> >
> >  ///
> >
> >  /// Inactive type is added from SMBIOS 2.2. Reference SMBIOS 2.6,
> chapter
> > 3.3.43.
> >
> > @@ -252,7 +255,9 @@ typedef struct {
> >UINT8TargetContentDistributionEnabled  : 1;
> >
> >UINT8UefiSpecificationSupported: 1;
> >
> >UINT8VirtualMachineSupported   : 1;
> >
> > -  UINT8ExtensionByte2Reserved: 3;
> >
> > +  UINT8ManufacturingModeSupported: 1;
> >
> > +  UINT8ManufacturingModeEnabled  : 1;
> >
> > +  UINT8ExtensionByte2Reserved: 1;
> >
> >  } MBCE_SYSTEM_RESERVED;
> >
> >
> >
> >  ///
> >
> > @@ -1401,6 +1406,17 @@ typedef struct {
> >UINT8Reserved: 1; ///< Set to 0.
> >
> >  } MISC_SLOT_CHARACTERISTICS2;
> >
> >
> >
> > +///
> >
> > +/// System Slots - Slot Height
> >
> > +///
> >
> > +typedef enum {
> >
> > +  SlotHeightNone   = 0x00,
> >
> > +  SlotHeightOther  = 0x01,
> >
> > +  SlotHeightUnknown= 0x02,
> >
> > +  SlotHeightFullHeight = 0x03,
> >
> > +  SlotHeightLowProfile = 0x04
> >
> > +} MISC_SLOT_HEIGHT;
> >
> > +
> >
> >  ///
> >
> >  /// System Slots - Peer Segment/Bus/Device/Function/Width Groups
> >
> >  ///
> >
> > @@ -1446,6 +1462,10 @@ typedef struct {
> >UINT8 SlotInformation;
> >
> >UINT8 SlotPhysicalWidth;
> >
> >UINT16SlotPitch;
> >
> > +  //
> >
> > +  // Add for smbios 3.5
> >
> > +  //
> >
> > +  UINT8 SlotHeight; ///<
> The
> > enumeration value from MISC_SLOT_HEIGHT.
> >
> >  } SMBIOS_TABLE_TYPE9;
> >
> >
> >
> >  ///
> >
> > @@ -2004,7 +2024,9 @@ typedef enum {
> >PointingDeviceInterfaceADB  = 0x08,
> >
> >PointingDeviceInterfaceBusMouseDB9  = 0xA0,
> >
> >PointingDeviceInterfaceBusMouseMicroDin = 0xA1,
> >
> > -  PointingDeviceInterfaceUsb  = 0xA2
> >
> > +  PointingDeviceInterfaceUsb  = 0xA2,
> >
> > +  PointingDeviceInterfaceI2c  = 0xA3,
> >
> > +  PointingDeviceInterfaceSpi  = 0xA4
> >
> >  } BUILTIN_POINTING_DEVICE_INTERFACE;
> >
> >
> >
> >  ///
> >
> > @@ -2508,7 +2530,13 @@ typedef enum {
> >OnBoardDeviceExtendedTypeSound  = 0x07,
> >
> >  

Re: [edk2-devel] [PATCH v5 0/2] ShellPkg/AcpiView: Adds ACPI_PARSER bitfield parser

[Gao, Zhichao]

Sorry. I forgot to update. I have create the PR twice but the open-CI failed. 
Can you check? https://github.com/tianocore/edk2/pull/2568

Thanks,
Zhichao

> -Original Message-
> From: Attar, AbdulLateef (Abdul Lateef) 
> Sent: Thursday, March 17, 2022 3:10 PM
> To: Gao, Zhichao ; devel@edk2.groups.io
> Cc: Ni, Ray ; Sami Mujawar 
> Subject: RE: [PATCH v5 0/2] ShellPkg/AcpiView: Adds ACPI_PARSER bitfield
> parser
> 
> Gentle reminder for PR.
> 
> -Original Message-
> From: Gao, Zhichao 
> Sent: Monday, February 21, 2022 1:10 PM
> To: Attar, AbdulLateef (Abdul Lateef) ;
> devel@edk2.groups.io
> Cc: Ni, Ray ; Sami Mujawar 
> Subject: RE: [PATCH v5 0/2] ShellPkg/AcpiView: Adds ACPI_PARSER bitfield
> parser
> 
> [CAUTION: External Email]
> 
> Patchset Reviewed-by: Zhichao Gao 
> 
> Thanks,
> Zhichao
> 
> > -Original Message-
> > From: Abdul Lateef Attar 
> > Sent: Wednesday, February 16, 2022 7:14 PM
> > To: devel@edk2.groups.io
> > Cc: Ni, Ray ; Gao, Zhichao ;
> > Sami Mujawar 
> > Subject: [PATCH v5 0/2] ShellPkg/AcpiView: Adds ACPI_PARSER bitfield
> > parser
> >
> > Hi,
> >   Sorry for the delayed reply.
> > I had updated the patch according to the review comments.
> > Please review the updated patch.
> >
> > REF:
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith
> >
> ub.com%2Fabdattar%2Fedk2%2Ftree%2FFadtFlagsParserV5data=04%7C0
> 1%7
> >
> CAbdulLateef.Attar%40amd.com%7Cdbcced5d461947c4c52908d9f50d60e9%7C
> 3dd8
> >
> 961fe4884e608e11a82d994e183d%7C0%7C0%7C637810260090713957%7CUnk
> nown%7C
> >
> TWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJX
> VC
> >
> I6Mn0%3D%7C3000sdata=lqrY9GyWZTJl%2BsRa%2F223ft8ei5rKBbm36av
> 4SQh4
> > l9g%3Dreserved=0
> >
> >
> > Cc: Ray Ni 
> > Cc: Zhichao Gao 
> > Cc: Sami Mujawar 
> >
> > Abdul Lateef Attar (2):
> >   ShellPkg/AcpiView: Adds ACPI_PARSER bitfield parser
> >   ShellPkg/AcpiView: PrintFormatter for FADT Flags field
> >
> >  ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.h  |  
> > 48
> > +
> >  ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c  | 
> > 188
> > 
> >
> > ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Fadt/FadtParser.c
> > | 167 +++--
> >  3 files changed, 348 insertions(+), 55 deletions(-)
> >
> > --
> > 2.25.1



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Re: [edk2-devel] [PATCH v6 1/1] CryptoPkg: Add new hash algorithm ParallelHash256HashAll in BaseCryptLib.

[Li, Zhihao]

OK

> -Original Message-
> From: Yao, Jiewen 
> Sent: Friday, March 18, 2022 9:59 AM
> To: Li, Zhihao ; devel@edk2.groups.io
> Cc: Wang, Jian J ; Lu, Xiaoyu1 ;
> Jiang, Guomin ; Fu, Siyuan ;
> Yao, Jiewen 
> Subject: RE: [PATCH v6 1/1] CryptoPkg: Add new hash algorithm
> ParallelHash256HashAll in BaseCryptLib.
> 
> Yes. It seems we missed RsaPssSign and RsaPssVerify in previous patch. Sigh...
> 
> Would you please help to add them?
> 
> 
> 
> > -Original Message-
> > From: Li, Zhihao 
> > Sent: Friday, March 18, 2022 9:53 AM
> > To: Yao, Jiewen ; devel@edk2.groups.io
> > Cc: Wang, Jian J ; Lu, Xiaoyu1
> ;
> > Jiang, Guomin ; Fu, Siyuan 
> > Subject: RE: [PATCH v6 1/1] CryptoPkg: Add new hash algorithm
> > ParallelHash256HashAll in BaseCryptLib.
> >
> > Build CryptoPei and CryptoSmm driver report this error.
> >
> > INFO - /home/vsts/work/1/s/CryptoPkg/Driver/Crypto.c:4707:3: error:
> > initialization of 'BOOLEAN (__attribute__((ms_abi)) *)(void *, const UINT8 
> > *,
> > UINTN,  UINT16,  UINT16,  UINT8 *, UINTN *)' from incompatible pointer type
> > 'BOOLEAN (__attribute__((ms_abi)) *)(const void *, UINTN,  UINTN,  void *,
> > UINTN,  const void *, UINTN)' [-Werror=incompatible-pointer-types]
> > INFO -  4707 |   CryptoServiceParallelHash256HashAll
> >
> > In Crypto.c:
> > const EDKII_CRYPTO_PROTOCOL  mEdkiiCrypto = {
> > ...
> >   CryptoServiceTlsGetHostPrivateKey,
> >   CryptoServiceTlsGetCertRevocationList,
> >   /// Parallel hash
> >   CryptoServiceParallelHash256HashAll
> > };
> > In Crypto.h
> > struct _EDKII_CRYPTO_PROTOCOL {
> > ...
> >   EDKII_CRYPTO_TLS_GET_CERT_REVOCATION_LIST
> > TlsGetCertRevocationList;
> >   /// RSA PSS
> >   EDKII_CRYPTO_RSA_PSS_SIGN  RsaPssSign;
> >   EDKII_CRYPTO_RSA_PSS_VERIFYRsaPssVerify;
> >   /// Parallel hash
> >   EDKII_CRYPTO_PARALLEL_HASH_ALL ParallelHash256HashAll;
> > };
> > And
> > typedef
> > BOOLEAN
> > (EFIAPI *EDKII_CRYPTO_RSA_PSS_SIGN)(
> >   IN  VOID *RsaContext,
> >   IN  CONST UINT8  *Message,
> >   IN  UINTNMsgSize,
> >   IN  UINT16   DigestLen,
> >   IN  UINT16   SaltLen,
> >   OUT UINT8*Signature,
> >   IN OUT  UINTN*SigSize
> >   );
> >
> > So I think solve this error need to put ParallelHash256HashAll before
> RsaPssSign.
> > And test result is successful.
> > Is there anything wrong with my judgment?
> >
> >
> > > -Original Message-
> > > From: Yao, Jiewen 
> > > Sent: Friday, March 18, 2022 8:56 AM
> > > To: Li, Zhihao ; devel@edk2.groups.io
> > > Cc: Wang, Jian J ; Lu, Xiaoyu1
> > ;
> > > Jiang, Guomin ; Fu, Siyuan 
> > > Subject: RE: [PATCH v6 1/1] CryptoPkg: Add new hash algorithm
> > > ParallelHash256HashAll in BaseCryptLib.
> > >
> > > What is root cause of failure?
> > >
> > > I don't understand.
> > >
> > > > -Original Message-
> > > > From: Li, Zhihao 
> > > > Sent: Friday, March 18, 2022 12:27 AM
> > > > To: Yao, Jiewen ; devel@edk2.groups.io
> > > > Cc: Wang, Jian J ; Lu, Xiaoyu1
> > > ;
> > > > Jiang, Guomin ; Fu, Siyuan
> 
> > > > Subject: RE: [PATCH v6 1/1] CryptoPkg: Add new hash algorithm
> > > > ParallelHash256HashAll in BaseCryptLib.
> > > >
> > > > Because it will cause patch to fail in CI test while to succeed if 
> > > > follow the
> > > setting.
> > > > Failed test: https://github.com/tianocore/edk2/pull/2535
> > > >
> > > > I guess it's because data structure
> EDKII_CRYPTO_PROTOCOL( mEdkiiCrypto)
> > > > doesn't have /// RSA PSS members in Crypto.c
> > > >
> > > > > -Original Message-
> > > > > From: Yao, Jiewen 
> > > > > Sent: Thursday, March 17, 2022 10:13 PM
> > > > > To: Li, Zhihao ; devel@edk2.groups.io
> > > > > Cc: Wang, Jian J ; Lu, Xiaoyu1
> > > > ;
> > > > > Jiang, Guomin ; Fu, Siyuan
> > 
> > > > > Subject: RE: [PATCH v6 1/1] CryptoPkg: Add new hash algorithm
> > > > > ParallelHash256HashAll in BaseCryptLib.
> > > > >
> > > > > Hey
> > > > > Are you following the guideline - don't put new field in the middle ?
> > > > >
> > > > > ParallelHash256HashAll API is still in the middle..
> > > > >
> > > > >
> > > > > > @@ -3641,6 +3670,8 @@ struct _EDKII_CRYPTO_PROTOCOL {
> > > > > >EDKII_CRYPTO_TLS_GET_HOST_PUBLIC_CERT
> > > TlsGetHostPublicCert;
> > > > > >
> > > > > >EDKII_CRYPTO_TLS_GET_HOST_PRIVATE_KEY
> > > TlsGetHostPrivateKey;
> > > > > >
> > > > > >EDKII_CRYPTO_TLS_GET_CERT_REVOCATION_LIST
> > > > > > TlsGetCertRevocationList;
> > > > > >
> > > > > > +  /// Parallel hash
> > > > > >
> > > > > > +  EDKII_CRYPTO_PARALLEL_HASH_ALL
> > ParallelHash256HashAll;
> > > > > >
> > > > > >/// RSA PSS
> > > > > >
> > > > > >EDKII_CRYPTO_RSA_PSS_SIGN  RsaPssSign;
> > > > > >
> > > > > >EDKII_CRYPTO_RSA_PSS_VERIFYRsaPssVerify;
> > > > > >
> > > > >
> > > > >
> > > > > > -Original Message-
> > > > > > From: Li, Zhihao 
> > > > > > Sent: Thursday, March 17, 2022 12:35 PM
> 

Re: [edk2-devel] [PATCH v6 1/1] CryptoPkg: Add new hash algorithm ParallelHash256HashAll in BaseCryptLib.

[Yao, Jiewen]

Yes. It seems we missed RsaPssSign and RsaPssVerify in previous patch. Sigh...

Would you please help to add them?



> -Original Message-
> From: Li, Zhihao 
> Sent: Friday, March 18, 2022 9:53 AM
> To: Yao, Jiewen ; devel@edk2.groups.io
> Cc: Wang, Jian J ; Lu, Xiaoyu1 ;
> Jiang, Guomin ; Fu, Siyuan 
> Subject: RE: [PATCH v6 1/1] CryptoPkg: Add new hash algorithm
> ParallelHash256HashAll in BaseCryptLib.
> 
> Build CryptoPei and CryptoSmm driver report this error.
> 
> INFO - /home/vsts/work/1/s/CryptoPkg/Driver/Crypto.c:4707:3: error:
> initialization of 'BOOLEAN (__attribute__((ms_abi)) *)(void *, const UINT8 *,
> UINTN,  UINT16,  UINT16,  UINT8 *, UINTN *)' from incompatible pointer type
> 'BOOLEAN (__attribute__((ms_abi)) *)(const void *, UINTN,  UINTN,  void *,
> UINTN,  const void *, UINTN)' [-Werror=incompatible-pointer-types]
> INFO -  4707 |   CryptoServiceParallelHash256HashAll
> 
> In Crypto.c:
> const EDKII_CRYPTO_PROTOCOL  mEdkiiCrypto = {
> ...
>   CryptoServiceTlsGetHostPrivateKey,
>   CryptoServiceTlsGetCertRevocationList,
>   /// Parallel hash
>   CryptoServiceParallelHash256HashAll
> };
> In Crypto.h
> struct _EDKII_CRYPTO_PROTOCOL {
> ...
>   EDKII_CRYPTO_TLS_GET_CERT_REVOCATION_LIST
> TlsGetCertRevocationList;
>   /// RSA PSS
>   EDKII_CRYPTO_RSA_PSS_SIGN  RsaPssSign;
>   EDKII_CRYPTO_RSA_PSS_VERIFYRsaPssVerify;
>   /// Parallel hash
>   EDKII_CRYPTO_PARALLEL_HASH_ALL ParallelHash256HashAll;
> };
> And
> typedef
> BOOLEAN
> (EFIAPI *EDKII_CRYPTO_RSA_PSS_SIGN)(
>   IN  VOID *RsaContext,
>   IN  CONST UINT8  *Message,
>   IN  UINTNMsgSize,
>   IN  UINT16   DigestLen,
>   IN  UINT16   SaltLen,
>   OUT UINT8*Signature,
>   IN OUT  UINTN*SigSize
>   );
> 
> So I think solve this error need to put ParallelHash256HashAll before 
> RsaPssSign.
> And test result is successful.
> Is there anything wrong with my judgment?
> 
> 
> > -Original Message-
> > From: Yao, Jiewen 
> > Sent: Friday, March 18, 2022 8:56 AM
> > To: Li, Zhihao ; devel@edk2.groups.io
> > Cc: Wang, Jian J ; Lu, Xiaoyu1
> ;
> > Jiang, Guomin ; Fu, Siyuan 
> > Subject: RE: [PATCH v6 1/1] CryptoPkg: Add new hash algorithm
> > ParallelHash256HashAll in BaseCryptLib.
> >
> > What is root cause of failure?
> >
> > I don't understand.
> >
> > > -Original Message-
> > > From: Li, Zhihao 
> > > Sent: Friday, March 18, 2022 12:27 AM
> > > To: Yao, Jiewen ; devel@edk2.groups.io
> > > Cc: Wang, Jian J ; Lu, Xiaoyu1
> > ;
> > > Jiang, Guomin ; Fu, Siyuan 
> > > Subject: RE: [PATCH v6 1/1] CryptoPkg: Add new hash algorithm
> > > ParallelHash256HashAll in BaseCryptLib.
> > >
> > > Because it will cause patch to fail in CI test while to succeed if follow 
> > > the
> > setting.
> > > Failed test: https://github.com/tianocore/edk2/pull/2535
> > >
> > > I guess it's because data structure EDKII_CRYPTO_PROTOCOL( mEdkiiCrypto)
> > > doesn't have /// RSA PSS members in Crypto.c
> > >
> > > > -Original Message-
> > > > From: Yao, Jiewen 
> > > > Sent: Thursday, March 17, 2022 10:13 PM
> > > > To: Li, Zhihao ; devel@edk2.groups.io
> > > > Cc: Wang, Jian J ; Lu, Xiaoyu1
> > > ;
> > > > Jiang, Guomin ; Fu, Siyuan
> 
> > > > Subject: RE: [PATCH v6 1/1] CryptoPkg: Add new hash algorithm
> > > > ParallelHash256HashAll in BaseCryptLib.
> > > >
> > > > Hey
> > > > Are you following the guideline - don't put new field in the middle ?
> > > >
> > > > ParallelHash256HashAll API is still in the middle..
> > > >
> > > >
> > > > > @@ -3641,6 +3670,8 @@ struct _EDKII_CRYPTO_PROTOCOL {
> > > > >EDKII_CRYPTO_TLS_GET_HOST_PUBLIC_CERT
> > TlsGetHostPublicCert;
> > > > >
> > > > >EDKII_CRYPTO_TLS_GET_HOST_PRIVATE_KEY
> > TlsGetHostPrivateKey;
> > > > >
> > > > >EDKII_CRYPTO_TLS_GET_CERT_REVOCATION_LIST
> > > > > TlsGetCertRevocationList;
> > > > >
> > > > > +  /// Parallel hash
> > > > >
> > > > > +  EDKII_CRYPTO_PARALLEL_HASH_ALL
> ParallelHash256HashAll;
> > > > >
> > > > >/// RSA PSS
> > > > >
> > > > >EDKII_CRYPTO_RSA_PSS_SIGN  RsaPssSign;
> > > > >
> > > > >EDKII_CRYPTO_RSA_PSS_VERIFYRsaPssVerify;
> > > > >
> > > >
> > > >
> > > > > -Original Message-
> > > > > From: Li, Zhihao 
> > > > > Sent: Thursday, March 17, 2022 12:35 PM
> > > > > To: devel@edk2.groups.io
> > > > > Cc: Yao, Jiewen ; Wang, Jian J
> > > > ;
> > > > > Lu, Xiaoyu1 ; Jiang, Guomin
> > > > ;
> > > > > Fu, Siyuan 
> > > > > Subject: [PATCH v6 1/1] CryptoPkg: Add new hash algorithm
> > > > > ParallelHash256HashAll in BaseCryptLib.
> > > > >
> > > > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3596
> > > > >
> > > > > Parallel hash function ParallelHash256HashAll, as defined in NIST's
> > > > > Special Publication 800-185, published December 2016. It utilizes
> > > > > multi-process to calculate the digest.
> > > > >
> > > > > Passed CI test.
> 

Re: [edk2-devel] [PATCH 0/3] [RFC] consolidate compiler intrinsics

[Pedro Falcato]

Hi,

Something I've just noticed: edk2-libc also ships its own intrinsics (
https://github.com/tianocore/edk2-libc/blob/master/StdLib/LibC/CRT/Gcc.c)

I know edk2-libc is not part of the core edk2 repo but I think we should
keep this in mind when this patch set gets merged.

On Fri, Mar 18, 2022 at 1:27 AM gaoliming  wrote:

> Gerd:
>   I suggest to submit the different BZs for those tasks. This patch set is
> the first stage. Future enhancement can be added later.
>
>   If no more comment for the first stage, this patch set can be merged
> first.
>
> Thanks
> Liming
> > -邮件原件-
> > 发件人: Gerd Hoffmann 
> > 发送时间: 2022年3月16日 17:46
> > 收件人: devel@edk2.groups.io; michael.d.kin...@intel.com
> > 抄送: Sean Brogan ; Lu, Xiaoyu1
> > ; Feng, Bob C ; Rebecca Cran
> > ; James Bottomley ; Sami
> > Mujawar ; Justen, Jordan L
> > ; Aktas, Erdem ; Yao,
> > Jiewen ; Supreeth Venkatesh
> > ; Boeuf, Sebastien
> > ; Gao, Zhichao ; Liu,
> > Zhiguang ; Maciej Rabeda
> > ; Ma, Maurice ;
> > Andrew Fish ; Ard Biesheuvel
> > ; Tom Lendacky ;
> > Peter Grehan ; Jiang, Guomin
> > ; Bret Barkelew ;
> > Chen, Christine ; You, Benjamin
> > ; Schaefer, Daniel ;
> > Gao, Liming ; Xu, Wei6 ;
> > Wang, Jian J ; Wu, Jiaxin ;
> Fu,
> > Siyuan ; Dong, Guo ;
> > kilian_ke...@hotmail.com; Chang, Abner ; Oliver
> > Steffen ; Leif Lindholm  >;
> > Brijesh Singh ; Xu, Min M ;
> > Ni, Ray ; Alexei Fedorov ;
> > Julien Grall ; Wang, Nickle ; Pawel
> > Polawski ; Anthony Perard
> > 
> > 主题: Re: [edk2-devel] [PATCH 0/3] [RFC] consolidate compiler intrinsics
> >
> > On Tue, Mar 15, 2022 at 03:27:58PM +, Michael D Kinney wrote:
> > > Hi Gerd,
> > >
> > > Thanks for working on this.  I raised this topic in the new TianoCore
> build
> > and CI
> > > meeting yesterday because the intrinsic libs are closely tied to the
> > toolchains
> > > supported by TianoCore.
> > >
> > > I agree with the concept of moving the compiler intrinsics to a library
> in the
> > MdePkg.
> > >
> > > + Sean Brogan
> > >
> > > Sean mentioned that he has some addition work on intrinsic libs for
> Visual
> > Studio
> > > toolchains.  It would be good to see if this set of changes is aligned
> with
> > those
> > > efforts.
> >
> > Having a single place where all compiler intrinsics are located should
> > simplify this kind of changes.
> >
> > > I see a few items that might be good to clean up at some point
> > > * fltused should go into its own file.  Not related to the strcmp() API
> > > * I see size_t defined in multiple places using different mappings.
> Would
> > be good to
> > >   define that in a single location.
> >
> > Yes, sure.  Both are valid points.
> >
> > I see this series as first step, consolidating the existing code in a
> > singe place with (almost) no actual code changes.  There surely will be
> > incremental improvements and cleanups later on.  I will need a few more
> > intrinsic functions when moving edk2 to openssl 3.0 for example.
> >
> > take care,
> >   Gerd
>
>
>
>
>
> 
>
>
>

-- 
Pedro Falcato


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Re: [edk2-devel] [PATCH v6 1/1] CryptoPkg: Add new hash algorithm ParallelHash256HashAll in BaseCryptLib.

[Li, Zhihao]

Build CryptoPei and CryptoSmm driver report this error.

INFO - /home/vsts/work/1/s/CryptoPkg/Driver/Crypto.c:4707:3: error: 
initialization of 'BOOLEAN (__attribute__((ms_abi)) *)(void *, const UINT8 *, 
UINTN,  UINT16,  UINT16,  UINT8 *, UINTN *)' from incompatible pointer type 
'BOOLEAN (__attribute__((ms_abi)) *)(const void *, UINTN,  UINTN,  void *, 
UINTN,  const void *, UINTN)' [-Werror=incompatible-pointer-types]
INFO -  4707 |   CryptoServiceParallelHash256HashAll

In Crypto.c:
const EDKII_CRYPTO_PROTOCOL  mEdkiiCrypto = {
...
  CryptoServiceTlsGetHostPrivateKey,
  CryptoServiceTlsGetCertRevocationList,
  /// Parallel hash
  CryptoServiceParallelHash256HashAll
};
In Crypto.h
struct _EDKII_CRYPTO_PROTOCOL {
...
  EDKII_CRYPTO_TLS_GET_CERT_REVOCATION_LIST  TlsGetCertRevocationList;
  /// RSA PSS
  EDKII_CRYPTO_RSA_PSS_SIGN  RsaPssSign;
  EDKII_CRYPTO_RSA_PSS_VERIFYRsaPssVerify;
  /// Parallel hash
  EDKII_CRYPTO_PARALLEL_HASH_ALL ParallelHash256HashAll;
};
And 
typedef
BOOLEAN
(EFIAPI *EDKII_CRYPTO_RSA_PSS_SIGN)(
  IN  VOID *RsaContext,
  IN  CONST UINT8  *Message,
  IN  UINTNMsgSize,
  IN  UINT16   DigestLen,
  IN  UINT16   SaltLen,
  OUT UINT8*Signature,
  IN OUT  UINTN*SigSize
  );

So I think solve this error need to put ParallelHash256HashAll before 
RsaPssSign.
And test result is successful.
Is there anything wrong with my judgment?


> -Original Message-
> From: Yao, Jiewen 
> Sent: Friday, March 18, 2022 8:56 AM
> To: Li, Zhihao ; devel@edk2.groups.io
> Cc: Wang, Jian J ; Lu, Xiaoyu1 ;
> Jiang, Guomin ; Fu, Siyuan 
> Subject: RE: [PATCH v6 1/1] CryptoPkg: Add new hash algorithm
> ParallelHash256HashAll in BaseCryptLib.
> 
> What is root cause of failure?
> 
> I don't understand.
> 
> > -Original Message-
> > From: Li, Zhihao 
> > Sent: Friday, March 18, 2022 12:27 AM
> > To: Yao, Jiewen ; devel@edk2.groups.io
> > Cc: Wang, Jian J ; Lu, Xiaoyu1
> ;
> > Jiang, Guomin ; Fu, Siyuan 
> > Subject: RE: [PATCH v6 1/1] CryptoPkg: Add new hash algorithm
> > ParallelHash256HashAll in BaseCryptLib.
> >
> > Because it will cause patch to fail in CI test while to succeed if follow 
> > the
> setting.
> > Failed test: https://github.com/tianocore/edk2/pull/2535
> >
> > I guess it's because data structure EDKII_CRYPTO_PROTOCOL( mEdkiiCrypto)
> > doesn't have /// RSA PSS members in Crypto.c
> >
> > > -Original Message-
> > > From: Yao, Jiewen 
> > > Sent: Thursday, March 17, 2022 10:13 PM
> > > To: Li, Zhihao ; devel@edk2.groups.io
> > > Cc: Wang, Jian J ; Lu, Xiaoyu1
> > ;
> > > Jiang, Guomin ; Fu, Siyuan 
> > > Subject: RE: [PATCH v6 1/1] CryptoPkg: Add new hash algorithm
> > > ParallelHash256HashAll in BaseCryptLib.
> > >
> > > Hey
> > > Are you following the guideline - don't put new field in the middle ?
> > >
> > > ParallelHash256HashAll API is still in the middle..
> > >
> > >
> > > > @@ -3641,6 +3670,8 @@ struct _EDKII_CRYPTO_PROTOCOL {
> > > >EDKII_CRYPTO_TLS_GET_HOST_PUBLIC_CERT
> TlsGetHostPublicCert;
> > > >
> > > >EDKII_CRYPTO_TLS_GET_HOST_PRIVATE_KEY
> TlsGetHostPrivateKey;
> > > >
> > > >EDKII_CRYPTO_TLS_GET_CERT_REVOCATION_LIST
> > > > TlsGetCertRevocationList;
> > > >
> > > > +  /// Parallel hash
> > > >
> > > > +  EDKII_CRYPTO_PARALLEL_HASH_ALL 
> > > > ParallelHash256HashAll;
> > > >
> > > >/// RSA PSS
> > > >
> > > >EDKII_CRYPTO_RSA_PSS_SIGN  RsaPssSign;
> > > >
> > > >EDKII_CRYPTO_RSA_PSS_VERIFYRsaPssVerify;
> > > >
> > >
> > >
> > > > -Original Message-
> > > > From: Li, Zhihao 
> > > > Sent: Thursday, March 17, 2022 12:35 PM
> > > > To: devel@edk2.groups.io
> > > > Cc: Yao, Jiewen ; Wang, Jian J
> > > ;
> > > > Lu, Xiaoyu1 ; Jiang, Guomin
> > > ;
> > > > Fu, Siyuan 
> > > > Subject: [PATCH v6 1/1] CryptoPkg: Add new hash algorithm
> > > > ParallelHash256HashAll in BaseCryptLib.
> > > >
> > > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3596
> > > >
> > > > Parallel hash function ParallelHash256HashAll, as defined in NIST's
> > > > Special Publication 800-185, published December 2016. It utilizes
> > > > multi-process to calculate the digest.
> > > >
> > > > Passed CI test.
> > > > Onprotocol version code passed test.
> > > >
> > > > Cc: Jiewen Yao 
> > > > Cc: Jian J Wang 
> > > > Cc: Xiaoyu Lu 
> > > > Cc: Guomin Jiang 
> > > > Cc: Siyuan Fu 
> > > > Cc: Zhihao Li 
> > > >
> > > > Signed-off-by: Zhihao Li 
> > > > ---
> > > >  CryptoPkg/Driver/Crypto.c 
> > > > |  38 ++-
> > > >  CryptoPkg/Library/BaseCryptLib/Hash/CryptCShake256.c  
> > > > | 282
> > > > 
> > > >  CryptoPkg/Library/BaseCryptLib/Hash/CryptParallelHash.c   
> > > > | 278
> > > > +++
> > > >  

回复: [edk2-devel] [PATCH 0/3] [RFC] consolidate compiler intrinsics

[gaoliming]

Gerd:
  I suggest to submit the different BZs for those tasks. This patch set is
the first stage. Future enhancement can be added later.

  If no more comment for the first stage, this patch set can be merged
first.

Thanks
Liming
> -邮件原件-
> 发件人: Gerd Hoffmann 
> 发送时间: 2022年3月16日 17:46
> 收件人: devel@edk2.groups.io; michael.d.kin...@intel.com
> 抄送: Sean Brogan ; Lu, Xiaoyu1
> ; Feng, Bob C ; Rebecca Cran
> ; James Bottomley ; Sami
> Mujawar ; Justen, Jordan L
> ; Aktas, Erdem ; Yao,
> Jiewen ; Supreeth Venkatesh
> ; Boeuf, Sebastien
> ; Gao, Zhichao ; Liu,
> Zhiguang ; Maciej Rabeda
> ; Ma, Maurice ;
> Andrew Fish ; Ard Biesheuvel
> ; Tom Lendacky ;
> Peter Grehan ; Jiang, Guomin
> ; Bret Barkelew ;
> Chen, Christine ; You, Benjamin
> ; Schaefer, Daniel ;
> Gao, Liming ; Xu, Wei6 ;
> Wang, Jian J ; Wu, Jiaxin ;
Fu,
> Siyuan ; Dong, Guo ;
> kilian_ke...@hotmail.com; Chang, Abner ; Oliver
> Steffen ; Leif Lindholm ;
> Brijesh Singh ; Xu, Min M ;
> Ni, Ray ; Alexei Fedorov ;
> Julien Grall ; Wang, Nickle ; Pawel
> Polawski ; Anthony Perard
> 
> 主题: Re: [edk2-devel] [PATCH 0/3] [RFC] consolidate compiler intrinsics
> 
> On Tue, Mar 15, 2022 at 03:27:58PM +, Michael D Kinney wrote:
> > Hi Gerd,
> >
> > Thanks for working on this.  I raised this topic in the new TianoCore
build
> and CI
> > meeting yesterday because the intrinsic libs are closely tied to the
> toolchains
> > supported by TianoCore.
> >
> > I agree with the concept of moving the compiler intrinsics to a library
in the
> MdePkg.
> >
> > + Sean Brogan
> >
> > Sean mentioned that he has some addition work on intrinsic libs for
Visual
> Studio
> > toolchains.  It would be good to see if this set of changes is aligned
with
> those
> > efforts.
> 
> Having a single place where all compiler intrinsics are located should
> simplify this kind of changes.
> 
> > I see a few items that might be good to clean up at some point
> > * fltused should go into its own file.  Not related to the strcmp() API
> > * I see size_t defined in multiple places using different mappings.
Would
> be good to
> >   define that in a single location.
> 
> Yes, sure.  Both are valid points.
> 
> I see this series as first step, consolidating the existing code in a
> singe place with (almost) no actual code changes.  There surely will be
> incremental improvements and cleanups later on.  I will need a few more
> intrinsic functions when moving edk2 to openssl 3.0 for example.
> 
> take care,
>   Gerd





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回复: [edk2-devel] [PATCH v1 1/1] MdeModulePkg: PiSmmCore: Inspect memory guarded with pool headers

[gaoliming]

Reviewed-by: Liming Gao 

> -邮件原件-
> 发件人: devel@edk2.groups.io  代表 Kun Qin
> 发送时间: 2022年3月16日 12:00
> 收件人: devel@edk2.groups.io
> 抄送: Jiewen Yao ; Eric Dong ;
> Ray Ni ; Jian J Wang ; Liming Gao
> 
> 主题: [edk2-devel] [PATCH v1 1/1] MdeModulePkg: PiSmmCore: Inspect
> memory guarded with pool headers
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3488
> 
> Current free pool routine from PiSmmCore will inspect memory guard status
> for target buffer without considering pool headers. This could lead to
> `IsMemoryGuarded` function to return incorrect results.
> 
> In that sense, allocating a 0 sized pool could cause an allocated buffer
> directly points into a guard page, which is legal. However, trying to
> free this pool will cause the routine changed in this commit to read XP
> pages, which leads to page fault.
> 
> This change will inspect memory guarded with pool headers. This can avoid
> errors when a pool content happens to be on a page boundary.
> 
> Cc: Jiewen Yao 
> Cc: Eric Dong 
> Cc: Ray Ni 
> Cc: Jian J Wang 
> Cc: Liming Gao 
> 
> Signed-off-by: Kun Qin 
> ---
>  MdeModulePkg/Core/PiSmmCore/Pool.c | 10 +-
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/MdeModulePkg/Core/PiSmmCore/Pool.c
> b/MdeModulePkg/Core/PiSmmCore/Pool.c
> index 96ebe811c669..e1ff40a8ea55 100644
> --- a/MdeModulePkg/Core/PiSmmCore/Pool.c
> +++ b/MdeModulePkg/Core/PiSmmCore/Pool.c
> @@ -382,11 +382,6 @@ SmmInternalFreePool (
>  return EFI_INVALID_PARAMETER;
>}
> 
> -  MemoryGuarded = IsHeapGuardEnabled () &&
> -  IsMemoryGuarded
> ((EFI_PHYSICAL_ADDRESS)(UINTN)Buffer);
> -  HasPoolTail = !(MemoryGuarded &&
> -  ((PcdGet8 (PcdHeapGuardPropertyMask) & BIT7) ==
> 0));
> -
>FreePoolHdr = (FREE_POOL_HEADER *)((POOL_HEADER *)Buffer - 1);
>ASSERT (FreePoolHdr->Header.Signature == POOL_HEAD_SIGNATURE);
>ASSERT (!FreePoolHdr->Header.Available);
> @@ -394,6 +389,11 @@ SmmInternalFreePool (
>  return EFI_INVALID_PARAMETER;
>}
> 
> +  MemoryGuarded = IsHeapGuardEnabled () &&
> +  IsMemoryGuarded
> ((EFI_PHYSICAL_ADDRESS)(UINTN)FreePoolHdr);
> +  HasPoolTail = !(MemoryGuarded &&
> +  ((PcdGet8 (PcdHeapGuardPropertyMask) & BIT7) ==
> 0));
> +
>if (HasPoolTail) {
>  PoolTail = HEAD_TO_TAIL (>Header);
>  ASSERT (PoolTail->Signature == POOL_TAIL_SIGNATURE);
> --
> 2.35.1.windows.2
> 
> 
> 
> 
> 





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[edk2-devel] 回复: [PATCH v2] MdePkg/AcpiXX.h: Update Error Severity type for Generic Error Status Block

[gaoliming]

Reviewed-by: Liming Gao 

> -邮件原件-
> 发件人: Wu, Hao A 
> 发送时间: 2022年3月15日 14:08
> 收件人: devel@edk2.groups.io; Kinney, Michael D
> ; Gao, Liming ;
> Liu, Zhiguang ; Ni, Ray 
> 主题: RE: [PATCH v2] MdePkg/AcpiXX.h: Update Error Severity type for
> Generic Error Status Block
> 
> Hello,
> 
> Any feedback for the patch? Thanks in advance.
> 
> Best Regards,
> Hao Wu
> 
> > -Original Message-
> > From: Wu, Hao A 
> > Sent: Tuesday, March 8, 2022 1:43 PM
> > To: devel@edk2.groups.io
> > Cc: Wu, Hao A ; Kinney, Michael D
> > ; Gao, Liming ;
> Liu,
> > Zhiguang ; Ni, Ray 
> > Subject: [PATCH v2] MdePkg/AcpiXX.h: Update Error Severity type for
> Generic
> > Error Status Block
> >
> > Starting from ACPI Specification Version 5.1 Errata B, the term
> > 'Correctable' is no longer being used as an error severity of the
> > reported error in Chapter 18 APEI.
> >
> > This commit will
> > a) For Acpi40.h & Acpi50.h
> > Add new macro EFI_ACPI_X_X_ERROR_SEVERITY_RECOVERABLE, since
> both the
> > terms 'Correctable' and 'Recoverable' are used to denote the same error
> > severity.
> >
> > b) Header files starting from Acpi51.h to Acpi64.h
> > Add new macro EFI_ACPI_X_X_ERROR_SEVERITY_RECOVERABLE.
> > Keeps the origin EFI_ACPI_X_X_ERROR_SEVERITY_CORRECTABLE for
> > compatibility
> > consideration, but add comments to mark it as deprecated and should no
> > longer be used.
> >
> > Cc: Michael D Kinney 
> > Cc: Liming Gao 
> > Cc: Zhiguang Liu 
> > Cc: Ray Ni 
> > Signed-off-by: Hao A Wu 
> > ---
> >  MdePkg/Include/IndustryStandard/Acpi40.h |  3 ++-
> >  MdePkg/Include/IndustryStandard/Acpi50.h |  3 ++-
> >  MdePkg/Include/IndustryStandard/Acpi51.h | 10 --
> >  MdePkg/Include/IndustryStandard/Acpi60.h | 10 --
> >  MdePkg/Include/IndustryStandard/Acpi61.h | 10 --
> >  MdePkg/Include/IndustryStandard/Acpi62.h | 10 --
> >  MdePkg/Include/IndustryStandard/Acpi63.h | 10 --
> >  MdePkg/Include/IndustryStandard/Acpi64.h | 10 --
> >  8 files changed, 52 insertions(+), 14 deletions(-)
> >
> > diff --git a/MdePkg/Include/IndustryStandard/Acpi40.h
> > b/MdePkg/Include/IndustryStandard/Acpi40.h
> > index 862113dff9..a2da09346f 100644
> > --- a/MdePkg/Include/IndustryStandard/Acpi40.h
> > +++ b/MdePkg/Include/IndustryStandard/Acpi40.h
> > @@ -1,7 +1,7 @@
> >  /** @file
> >
> >ACPI 4.0 definitions from the ACPI Specification Revision 4.0a April
5,
> 2010
> >
> >
> >
> > -  Copyright (c) 2010 - 2018, Intel Corporation. All rights
reserved.
> >
> > +  Copyright (c) 2010 - 2022, Intel Corporation. All rights
reserved.
> >
> >SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> >  **/
> >
> >
> >
> > @@ -690,6 +690,7 @@ typedef struct {
> >  // Boot Error Severity types
> >
> >  //
> >
> >  #define EFI_ACPI_4_0_ERROR_SEVERITY_CORRECTABLE  0x00
> >
> > +#define EFI_ACPI_4_0_ERROR_SEVERITY_RECOVERABLE  0x00
> >
> >  #define EFI_ACPI_4_0_ERROR_SEVERITY_FATAL0x01
> >
> >  #define EFI_ACPI_4_0_ERROR_SEVERITY_CORRECTED0x02
> >
> >  #define EFI_ACPI_4_0_ERROR_SEVERITY_NONE 0x03
> >
> > diff --git a/MdePkg/Include/IndustryStandard/Acpi50.h
> > b/MdePkg/Include/IndustryStandard/Acpi50.h
> > index be8f85f577..76706aa640 100644
> > --- a/MdePkg/Include/IndustryStandard/Acpi50.h
> > +++ b/MdePkg/Include/IndustryStandard/Acpi50.h
> > @@ -2,7 +2,7 @@
> >ACPI 5.0 definitions from the ACPI Specification Revision 5.0a
> November 13,
> > 2013.
> >
> >
> >
> >Copyright (c) 2014 Hewlett-Packard Development Company, L.P.
> >
> > -  Copyright (c) 2011 - 2018, Intel Corporation. All rights
reserved.
> >
> > +  Copyright (c) 2011 - 2022, Intel Corporation. All rights
reserved.
> >
> >Copyright (c) 2020, ARM Ltd. All rights reserved.
> >
> >SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> >  **/
> >
> > @@ -1361,6 +1361,7 @@ typedef struct {
> >  // Boot Error Severity types
> >
> >  //
> >
> >  #define EFI_ACPI_5_0_ERROR_SEVERITY_CORRECTABLE  0x00
> >
> > +#define EFI_ACPI_5_0_ERROR_SEVERITY_RECOVERABLE  0x00
> >
> >  #define EFI_ACPI_5_0_ERROR_SEVERITY_FATAL0x01
> >
> >  #define EFI_ACPI_5_0_ERROR_SEVERITY_CORRECTED0x02
> >
> >  #define EFI_ACPI_5_0_ERROR_SEVERITY_NONE 0x03
> >
> > diff --git a/MdePkg/Include/IndustryStandard/Acpi51.h
> > b/MdePkg/Include/IndustryStandard/Acpi51.h
> > index d8ee3ef8f2..01ef544c3a 100644
> > --- a/MdePkg/Include/IndustryStandard/Acpi51.h
> > +++ b/MdePkg/Include/IndustryStandard/Acpi51.h
> > @@ -2,7 +2,7 @@
> >ACPI 5.1 definitions from the ACPI Specification Revision 5.1 Errata
B
> January,
> > 2016.
> >
> >
> >
> >Copyright (c) 2014 Hewlett-Packard Development Company, L.P.
> >
> > -  Copyright (c) 2014 - 2018, Intel Corporation. All rights
reserved.
> >
> > +  Copyright (c) 2014 - 2022, Intel Corporation. All rights
reserved.
> >
> >(C) Copyright 2015 Hewlett Packard Enterprise Development LP
> >
> >Copyright (c) 2020, ARM Ltd. All rights reserved.
> >
> >SPDX-License-Identifier: 

回复: [edk2-devel] [PATCH V8 12/47] MdePkg: Add macro to check SEV / TDX guest

[gaoliming]

Min:
  This patch is good. I have no other comments in MdePkg. Reviewed-by:
Liming Gao 

Thanks
Liming
> -邮件原件-
> 发件人: devel@edk2.groups.io  代表 Min Xu
> 发送时间: 2022年3月17日 13:32
> 收件人: devel@edk2.groups.io; Xu, Min M 
> 抄送: Michael Roth ; Ni, Ray ;
> Kumar, Rahul1 ; Dong, Eric ;
> James Bottomley ; Yao, Jiewen
> ; Tom Lendacky ;
> Justen, Jordan L ; Ard Biesheuvel
> ; Aktas, Erdem ;
> Gerd Hoffmann ; Kinney, Michael D
> ; Gao, Liming ;
> Liu, Zhiguang 
> 主题: Re: [edk2-devel] [PATCH V8 12/47] MdePkg: Add macro to check SEV /
> TDX guest
> 
> Hi, Liming
> Can you help to review this patch?
> https://edk2.groups.io/g/devel/message/87480
> 
> Thanks
> Min
> > -Original Message-
> > From: devel@edk2.groups.io  On Behalf Of Min Xu
> > Sent: Saturday, March 12, 2022 9:54 AM
> > To: devel@edk2.groups.io
> > Cc: Xu, Min M ; Michael Roth
> ;
> > Ni, Ray ; Kumar, Rahul1 ;
> Dong,
> > Eric ; James Bottomley ; Yao,
> > Jiewen ; Tom Lendacky
> ;
> > Justen, Jordan L ; Ard Biesheuvel
> > ; Aktas, Erdem ;
> Gerd
> > Hoffmann ; Kinney, Michael D
> > ; Gao, Liming ;
> Liu,
> > Zhiguang 
> > Subject: [edk2-devel] [PATCH V8 12/47] MdePkg: Add macro to check SEV /
> > TDX guest
> >
> > RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
> >
> > Add macros CC_GUEST_IS_SEV / CC_GUEST_IS_TDX to check SEV / TDX
> guest.
> >
> > Cc: Michael Roth 
> > Cc: Ray Ni 
> > Cc: Rahul Kumar 
> > Cc: Eric Dong 
> > Cc: James Bottomley 
> > Cc: Min Xu 
> > Cc: Jiewen Yao 
> > Cc: Tom Lendacky 
> > Cc: Jordan Justen 
> > Cc: Ard Biesheuvel 
> > Cc: Erdem Aktas 
> > Cc: Gerd Hoffmann 
> > Cc: Michael D Kinney 
> > Cc: Liming Gao 
> > Cc: Zhiguang Liu 
> > Acked-by: Gerd Hoffmann 
> > Signed-off-by: Min Xu 
> > ---
> >  MdePkg/Include/ConfidentialComputingGuestAttr.h | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/MdePkg/Include/ConfidentialComputingGuestAttr.h
> > b/MdePkg/Include/ConfidentialComputingGuestAttr.h
> > index 6a1301801519..dd2541c6dcdf 100644
> > --- a/MdePkg/Include/ConfidentialComputingGuestAttr.h
> > +++ b/MdePkg/Include/ConfidentialComputingGuestAttr.h
> > @@ -22,4 +22,7 @@ typedef enum {
> >CCAttrIntelTdx = 0x200,
> >  } CONFIDENTIAL_COMPUTING_GUEST_ATTR;
> >
> > +#define CC_GUEST_IS_TDX(x)  ((x) == CCAttrIntelTdx) #define
> > +CC_GUEST_IS_SEV(x)  ((x) == CCAttrAmdSev || (x) == CCAttrAmdSevEs ||
> > +(x) == CCAttrAmdSevSnp)
> > +
> >  #endif
> > --
> > 2.29.2.windows.2
> >
> >
> >
> >
> >
> 
> 
> 
> 
> 





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Re: [edk2-devel] [PATCH v6 1/1] CryptoPkg: Add new hash algorithm ParallelHash256HashAll in BaseCryptLib.

[Yao, Jiewen]

What is root cause of failure?

I don't understand.

> -Original Message-
> From: Li, Zhihao 
> Sent: Friday, March 18, 2022 12:27 AM
> To: Yao, Jiewen ; devel@edk2.groups.io
> Cc: Wang, Jian J ; Lu, Xiaoyu1 ;
> Jiang, Guomin ; Fu, Siyuan 
> Subject: RE: [PATCH v6 1/1] CryptoPkg: Add new hash algorithm
> ParallelHash256HashAll in BaseCryptLib.
> 
> Because it will cause patch to fail in CI test while to succeed if follow the 
> setting.
> Failed test: https://github.com/tianocore/edk2/pull/2535
> 
> I guess it's because data structure EDKII_CRYPTO_PROTOCOL( mEdkiiCrypto)
> doesn't have /// RSA PSS members in Crypto.c
> 
> > -Original Message-
> > From: Yao, Jiewen 
> > Sent: Thursday, March 17, 2022 10:13 PM
> > To: Li, Zhihao ; devel@edk2.groups.io
> > Cc: Wang, Jian J ; Lu, Xiaoyu1
> ;
> > Jiang, Guomin ; Fu, Siyuan 
> > Subject: RE: [PATCH v6 1/1] CryptoPkg: Add new hash algorithm
> > ParallelHash256HashAll in BaseCryptLib.
> >
> > Hey
> > Are you following the guideline - don't put new field in the middle ?
> >
> > ParallelHash256HashAll API is still in the middle..
> >
> >
> > > @@ -3641,6 +3670,8 @@ struct _EDKII_CRYPTO_PROTOCOL {
> > >EDKII_CRYPTO_TLS_GET_HOST_PUBLIC_CERT  
> > > TlsGetHostPublicCert;
> > >
> > >EDKII_CRYPTO_TLS_GET_HOST_PRIVATE_KEY  
> > > TlsGetHostPrivateKey;
> > >
> > >EDKII_CRYPTO_TLS_GET_CERT_REVOCATION_LIST
> > > TlsGetCertRevocationList;
> > >
> > > +  /// Parallel hash
> > >
> > > +  EDKII_CRYPTO_PARALLEL_HASH_ALL 
> > > ParallelHash256HashAll;
> > >
> > >/// RSA PSS
> > >
> > >EDKII_CRYPTO_RSA_PSS_SIGN  RsaPssSign;
> > >
> > >EDKII_CRYPTO_RSA_PSS_VERIFYRsaPssVerify;
> > >
> >
> >
> > > -Original Message-
> > > From: Li, Zhihao 
> > > Sent: Thursday, March 17, 2022 12:35 PM
> > > To: devel@edk2.groups.io
> > > Cc: Yao, Jiewen ; Wang, Jian J
> > ;
> > > Lu, Xiaoyu1 ; Jiang, Guomin
> > ;
> > > Fu, Siyuan 
> > > Subject: [PATCH v6 1/1] CryptoPkg: Add new hash algorithm
> > > ParallelHash256HashAll in BaseCryptLib.
> > >
> > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3596
> > >
> > > Parallel hash function ParallelHash256HashAll, as defined in NIST's
> > > Special Publication 800-185, published December 2016. It utilizes
> > > multi-process to calculate the digest.
> > >
> > > Passed CI test.
> > > Onprotocol version code passed test.
> > >
> > > Cc: Jiewen Yao 
> > > Cc: Jian J Wang 
> > > Cc: Xiaoyu Lu 
> > > Cc: Guomin Jiang 
> > > Cc: Siyuan Fu 
> > > Cc: Zhihao Li 
> > >
> > > Signed-off-by: Zhihao Li 
> > > ---
> > >  CryptoPkg/Driver/Crypto.c |  
> > > 38 ++-
> > >  CryptoPkg/Library/BaseCryptLib/Hash/CryptCShake256.c  | 
> > > 282
> > > 
> > >  CryptoPkg/Library/BaseCryptLib/Hash/CryptParallelHash.c   | 
> > > 278
> > > +++
> > >  CryptoPkg/Library/BaseCryptLib/Hash/CryptParallelHashNull.c   |  
> > > 40
> +++
> > >  CryptoPkg/Library/BaseCryptLib/Hash/CryptSha3.c   | 
> > > 166
> > > 
> > >  CryptoPkg/Library/BaseCryptLib/Hash/CryptXkcp.c   | 
> > > 107
> > 
> > >  CryptoPkg/Library/BaseCryptLibNull/Hash/CryptParallelHashNull.c   |  
> > > 40
> > +++
> > >  CryptoPkg/Library/BaseCryptLibOnProtocolPpi/CryptLib.c|  
> > > 34 ++-
> > >  CryptoPkg/Test/UnitTest/Library/BaseCryptLib/ParallelhashTests.c  | 
> > > 145
> > > ++
> > >  CryptoPkg/CryptoPkg.ci.yaml   |  
> > >  4 +-
> > >  CryptoPkg/Include/Library/BaseCryptLib.h  |  
> > > 31 ++-
> > >  CryptoPkg/Include/Pcd/PcdCryptoServiceFamilyEnable.h  |  
> > >  8 +-
> > >  CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf   |  
> > >  3 +-
> > >  CryptoPkg/Library/BaseCryptLib/Hash/CryptParallelHash.h   | 
> > > 201
> > > ++
> > >  CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf|  
> > >  3 +-
> > >  CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf|  
> > >  3 +-
> > >  CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf|  
> > >  8 +-
> > >  CryptoPkg/Library/BaseCryptLibNull/BaseCryptLibNull.inf   |  
> > >  3 +-
> > >  CryptoPkg/Library/Include/CrtLibSupport.h |  
> > >  3 +-
> > >  CryptoPkg/Private/Protocol/Crypto.h   |  
> > > 35 ++-
> > >  CryptoPkg/Test/CryptoPkgHostUnitTest.dsc  |  
> > >  4 +
> > >  CryptoPkg/Test/UnitTest/Library/BaseCryptLib/TestBaseCryptLibHost.inf |
> 4
> > +
> > >  22 files changed, 1426 insertions(+), 14 deletions(-)
> > >
> > > diff --git a/CryptoPkg/Driver/Crypto.c b/CryptoPkg/Driver/Crypto.c
> > > index d5d6aa8e5820..5a9245c07cc5 100644
> > > --- 

[edk2-devel] [PATCH V9 40/47] OvmfPkg: Update AcpiPlatformDxe to alter MADT table

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429

In TDX the guest firmware is designed to publish a multiprocessor-wakeup
structure to let the guest-bootstrap processor wake up guest-application
processors with a mailbox. The mailbox is memory that the guest firmware
can reserve so each guest virtual processor can have the guest OS send
a message to them. The address of the mailbox is recorded in the MADT
table. See [ACPI].

To maintain the simplicity of the AcpiPlatformDxe, the MADT ACPI table
will be altered in another driver (TdxDxe) by installing a protocol
to notify that the ACPI table provided by Qemu is ready. Then in TdxDxe
a notification functioin will be called to alter the MADT table to recorded
the mailbox address.

The protocol is gQemuAcpiTableNotifyProtocolGuid.

Cc: Ard Biesheuvel 
Cc: Jordan Justen 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Acked-by: Gerd Hoffmann 
Signed-off-by: Min Xu 
---
 OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf   |  1 +
 OvmfPkg/AcpiPlatformDxe/QemuFwCfgAcpi.c   | 14 +-
 .../Include/Protocol/QemuAcpiTableNotify.h| 27 +++
 3 files changed, 41 insertions(+), 1 deletion(-)
 create mode 100644 OvmfPkg/Include/Protocol/QemuAcpiTableNotify.h

diff --git a/OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf 
b/OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf
index f22bd7cb6da1..09daf30bcd3d 100644
--- a/OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf
+++ b/OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf
@@ -49,6 +49,7 @@
 [Protocols]
   gEfiAcpiTableProtocolGuid # PROTOCOL ALWAYS_CONSUMED
   gEfiPciIoProtocolGuid # PROTOCOL SOMETIMES_CONSUMED
+  gQemuAcpiTableNotifyProtocolGuid  # PROTOCOL PRODUCES
 
 [Guids]
   gRootBridgesConnectedEventGroupGuid
diff --git a/OvmfPkg/AcpiPlatformDxe/QemuFwCfgAcpi.c 
b/OvmfPkg/AcpiPlatformDxe/QemuFwCfgAcpi.c
index b885965a601e..c8dee17c13e6 100644
--- a/OvmfPkg/AcpiPlatformDxe/QemuFwCfgAcpi.c
+++ b/OvmfPkg/AcpiPlatformDxe/QemuFwCfgAcpi.c
@@ -19,7 +19,10 @@
 #include// QemuFwCfgS3Enabled()
 #include  // gBS
 
+#include 
 #include "AcpiPlatform.h"
+EFI_HANDLE   mQemuAcpiHandle = NULL;
+QEMU_ACPI_TABLE_NOTIFY_PROTOCOL  mAcpiNotifyProtocol;
 
 //
 // The user structure for the ordered collection that will track the fw_cfg
@@ -1273,7 +1276,16 @@ UninstallAcpiTables:
   AcpiProtocol->UninstallAcpiTable (AcpiProtocol, InstalledKey[Installed]);
 }
   } else {
-DEBUG ((DEBUG_INFO, "%a: installed %d tables\n", __FUNCTION__, Installed));
+//
+// Install a protocol to notify that the ACPI table provided by Qemu is
+// ready.
+//
+gBS->InstallProtocolInterface (
+   ,
+   ,
+   EFI_NATIVE_INTERFACE,
+   
+   );
   }
 
   for (SeenPointerEntry = OrderedCollectionMin (SeenPointers);
diff --git a/OvmfPkg/Include/Protocol/QemuAcpiTableNotify.h 
b/OvmfPkg/Include/Protocol/QemuAcpiTableNotify.h
new file mode 100644
index ..a3dd2fc1dc91
--- /dev/null
+++ b/OvmfPkg/Include/Protocol/QemuAcpiTableNotify.h
@@ -0,0 +1,27 @@
+/** @file
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef QEMU_ACPI_TABLE_NOTIFY_H_
+#define QEMU_ACPI_TABLE_NOTIFY_H_
+
+#define QEMU_ACPI_TABLE_NOTIFY_GUID \
+  { 0x928939b2, 0x4235, 0x462f, { 0x95, 0x80, 0xf6, 0xa2, 0xb2, 0xc2, 0x1a, 
0x4f } };
+
+///
+/// Forward declaration
+///
+typedef struct _QEMU_ACPI_TABLE_NOTIFY_PROTOCOL 
QEMU_ACPI_TABLE_NOTIFY_PROTOCOL;
+
+///
+/// Protocol structure
+///
+struct _QEMU_ACPI_TABLE_NOTIFY_PROTOCOL {
+  UINT8Notify;
+};
+
+extern EFI_GUID  gQemuAcpiTableNotifyProtocolGuid;
+
+#endif
-- 
2.29.2.windows.2



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[edk2-devel] [PATCH V9 39/47] OvmfPkg: Update PlatformPei to support Tdx guest

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429

OvmfPkg/PlatformPei is updated to support Tdx guest. There are below
major changes.
 - Set Tdx related PCDs
 - Publish Tdx RamRegions

In this patch there is another new function BuildPlatformInfoHob ().
This function builds EFI_HOB_PLATFORM_INFO which contains the
HostBridgeDevId. The hob is built in both Td guest and Non-Td guest.

Cc: Ard Biesheuvel 
Cc: Jordan Justen 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Acked-by: Gerd Hoffmann 
Signed-off-by: Min Xu 
---
 OvmfPkg/OvmfPkg.dec  |  1 +
 OvmfPkg/PlatformPei/FeatureControl.c |  7 +++-
 OvmfPkg/PlatformPei/IntelTdx.c   | 51 
 OvmfPkg/PlatformPei/MemDetect.c  | 13 +--
 OvmfPkg/PlatformPei/Platform.c   | 13 +++
 OvmfPkg/PlatformPei/Platform.h   | 19 +++
 OvmfPkg/PlatformPei/PlatformPei.inf  |  3 ++
 7 files changed, 104 insertions(+), 3 deletions(-)
 create mode 100644 OvmfPkg/PlatformPei/IntelTdx.c

diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec
index f3d06411b51b..746050d64ba7 100644
--- a/OvmfPkg/OvmfPkg.dec
+++ b/OvmfPkg/OvmfPkg.dec
@@ -133,6 +133,7 @@
   gGrubFileGuid = {0xb5ae312c, 0xbc8a, 0x43b1, {0x9c, 
0x62, 0xeb, 0xb8, 0x26, 0xdd, 0x5d, 0x07}}
   gConfidentialComputingSecretGuid  = {0xadf956ad, 0xe98c, 0x484c, {0xae, 
0x11, 0xb5, 0x1c, 0x7d, 0x33, 0x64, 0x47}}
   gConfidentialComputingSevSnpBlobGuid  = {0x067b1f5f, 0xcf26, 0x44c5, {0x85, 
0x54, 0x93, 0xd7, 0x77, 0x91, 0x2d, 0x42}}
+  gUefiOvmfPkgPlatformInfoGuid  = {0xdec9b486, 0x1f16, 0x47c7, {0x8f, 
0x68, 0xdf, 0x1a, 0x41, 0x88, 0x8b, 0xa5}}
 
 [Ppis]
   # PPI whose presence in the PPI database signals that the TPM base address
diff --git a/OvmfPkg/PlatformPei/FeatureControl.c 
b/OvmfPkg/PlatformPei/FeatureControl.c
index 9af58c2655f8..5864ee0c214d 100644
--- a/OvmfPkg/PlatformPei/FeatureControl.c
+++ b/OvmfPkg/PlatformPei/FeatureControl.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "Platform.h"
 
@@ -37,7 +38,11 @@ WriteFeatureControl (
   IN OUT VOID  *WorkSpace
   )
 {
-  AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, mFeatureControlValue);
+  if (TdIsEnabled ()) {
+TdVmCall (TDVMCALL_WRMSR, (UINT64)MSR_IA32_FEATURE_CONTROL, 
mFeatureControlValue, 0, 0, 0);
+  } else {
+AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, mFeatureControlValue);
+  }
 }
 
 /**
diff --git a/OvmfPkg/PlatformPei/IntelTdx.c b/OvmfPkg/PlatformPei/IntelTdx.c
new file mode 100644
index ..3c1ddbfafd80
--- /dev/null
+++ b/OvmfPkg/PlatformPei/IntelTdx.c
@@ -0,0 +1,51 @@
+/** @file
+  Initialize Intel TDX support.
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "Platform.h"
+
+/**
+  This Function checks if TDX is available, if present then it sets
+  the dynamic PCDs for Tdx guest.
+  **/
+VOID
+IntelTdxInitialize (
+  VOID
+  )
+{
+ #ifdef MDE_CPU_X64
+  RETURN_STATUS  PcdStatus;
+
+  if (!TdIsEnabled ()) {
+return;
+  }
+
+  PcdStatus = PcdSet64S (PcdConfidentialComputingGuestAttr, CCAttrIntelTdx);
+  ASSERT_RETURN_ERROR (PcdStatus);
+
+  PcdStatus = PcdSet64S (PcdTdxSharedBitMask, TdSharedPageMask ());
+  ASSERT_RETURN_ERROR (PcdStatus);
+
+  PcdStatus = PcdSetBoolS (PcdSetNxForStack, TRUE);
+  ASSERT_RETURN_ERROR (PcdStatus);
+ #endif
+}
diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c
index 61d7d3059f7b..2e47b1322990 100644
--- a/OvmfPkg/PlatformPei/MemDetect.c
+++ b/OvmfPkg/PlatformPei/MemDetect.c
@@ -37,7 +37,6 @@ Module Name:
 
 #include 
 #include 
-
 #include "Platform.h"
 
 VOID
@@ -231,7 +230,12 @@ GetPeiMemoryCap (
 PdpEntries  = 1 << (mPlatformInfoHob.PhysMemAddressWidth - 30);
 ASSERT (PdpEntries <= 0x200);
   } else {
-Pml4Entries = 1 << (mPlatformInfoHob.PhysMemAddressWidth - 39);
+if (mPlatformInfoHob.PhysMemAddressWidth > 48) {
+  Pml4Entries = 0x200;
+} else {
+  Pml4Entries = 1 << (mPlatformInfoHob.PhysMemAddressWidth - 39);
+}
+
 ASSERT (Pml4Entries <= 0x200);
 PdpEntries = 512;
   }
@@ -354,6 +358,11 @@ InitializeRamRegions (
   IN EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
   )
 {
+  if (TdIsEnabled ()) {
+PlatformTdxPublishRamRegions ();
+return;
+  }
+
   PlatformQemuInitializeRam (PlatformInfoHob);
 
   SevInitializeRam ();
diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index f05aec599fcb..f006755d5fdb 100644
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -310,6 +310,17 @@ MaxCpuCountInitialization (
   ASSERT_RETURN_ERROR (PcdStatus);
 }
 
+/**
+ * @brief Builds PlatformInfo Hob
+ */
+VOID
+BuildPlatformInfoHob (
+  VOID
+  )
+{
+  

[edk2-devel] [PATCH V9 36/47] MdeModulePkg: Add PcdTdxSharedBitMask

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429

Guest Physical Address (GPA) space in Td guest is divided into private
and shared sub-spaces, determined by the SHARED bit of GPA. This PCD
holds the shared bit mask. Its default value is 0 and it will be set
in PlatformPei driver if it is of Td guest.

Cc: Jian J Wang 
Cc: Hao A Wu 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Acked-by: Gerd Hoffmann 
Reviewed-by: Jian J Wang 
Signed-off-by: Min Xu 
---
 MdeModulePkg/MdeModulePkg.dec  | 4 
 OvmfPkg/AmdSev/AmdSevX64.dsc   | 3 +++
 OvmfPkg/Bhyve/BhyveX64.dsc | 3 +++
 OvmfPkg/CloudHv/CloudHvX64.dsc | 3 +++
 OvmfPkg/Microvm/MicrovmX64.dsc | 3 +++
 OvmfPkg/OvmfPkgIa32.dsc| 3 +++
 OvmfPkg/OvmfPkgIa32X64.dsc | 1 +
 OvmfPkg/OvmfPkgX64.dsc | 3 +++
 OvmfPkg/OvmfXen.dsc| 3 +++
 9 files changed, 26 insertions(+)

diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec
index 463e889e9a68..1a2425974f44 100644
--- a/MdeModulePkg/MdeModulePkg.dec
+++ b/MdeModulePkg/MdeModulePkg.dec
@@ -2079,6 +2079,10 @@
   # @Prompt Enable PCIe Resizable BAR Capability support.
   
gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport|FALSE|BOOLEAN|0x1024
 
+  ## This PCD holds the shared bit mask for page table entries when Tdx is 
enabled.
+  # @Prompt The shared bit mask when Intel Tdx is enabled.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdTdxSharedBitMask|0x0|UINT64|0x1025
+
 [PcdsPatchableInModule]
   ## Specify memory size with page number for PEI code when
   #  Loading Module at Fixed Address feature is enabled.
diff --git a/OvmfPkg/AmdSev/AmdSevX64.dsc b/OvmfPkg/AmdSev/AmdSevX64.dsc
index c173a72134f4..dda98aa43bdb 100644
--- a/OvmfPkg/AmdSev/AmdSevX64.dsc
+++ b/OvmfPkg/AmdSev/AmdSevX64.dsc
@@ -558,6 +558,9 @@
   # Set memory encryption mask
   gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0
 
+  # Set Tdx shared bit mask
+  gEfiMdeModulePkgTokenSpaceGuid.PcdTdxSharedBitMask|0x0
+
   # Set SEV-ES defaults
   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0
   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0
diff --git a/OvmfPkg/Bhyve/BhyveX64.dsc b/OvmfPkg/Bhyve/BhyveX64.dsc
index 656e407473bb..0daae82d6705 100644
--- a/OvmfPkg/Bhyve/BhyveX64.dsc
+++ b/OvmfPkg/Bhyve/BhyveX64.dsc
@@ -550,6 +550,9 @@
   # Set memory encryption mask
   gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0
 
+  # Set Tdx shared bit mask
+  gEfiMdeModulePkgTokenSpaceGuid.PcdTdxSharedBitMask|0x0
+
   gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x00
 
   # MdeModulePkg resolution sets up the system display resolution
diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc
index c307f1cc7550..1732f281b435 100644
--- a/OvmfPkg/CloudHv/CloudHvX64.dsc
+++ b/OvmfPkg/CloudHv/CloudHvX64.dsc
@@ -603,6 +603,9 @@
   # Set memory encryption mask
   gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0
 
+  # Set Tdx shared bit mask
+  gEfiMdeModulePkgTokenSpaceGuid.PcdTdxSharedBitMask|0x0
+
   # Set SEV-ES defaults
   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0
   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0
diff --git a/OvmfPkg/Microvm/MicrovmX64.dsc b/OvmfPkg/Microvm/MicrovmX64.dsc
index 0eac0c02c630..cde90f523520 100644
--- a/OvmfPkg/Microvm/MicrovmX64.dsc
+++ b/OvmfPkg/Microvm/MicrovmX64.dsc
@@ -592,6 +592,9 @@
   # Set memory encryption mask
   gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0
 
+  # Set Tdx shared bit mask
+  gEfiMdeModulePkgTokenSpaceGuid.PcdTdxSharedBitMask|0x0
+
   # Set SEV-ES defaults
   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0
   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0
diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index 8f02dca63869..01a26c234a88 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -618,6 +618,9 @@
   # Set memory encryption mask
   gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0
 
+  # Set Tdx shared bit mask
+  gEfiMdeModulePkgTokenSpaceGuid.PcdTdxSharedBitMask|0x0
+
   # Set SEV-ES defaults
   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0
   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index 98a6748c62dd..bf08e893e053 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -631,6 +631,7 @@
 
   # Set memory encryption mask
   gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdTdxSharedBitMask|0x0
 
   # Set SEV-ES defaults
   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0
diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index 2df5b2999610..3092036bb7f6 100644
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -642,6 +642,9 @@
   # Set memory encryption mask
   gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0
 
+  # Set 

[edk2-devel] [PATCH V9 38/47] OvmfPkg: Update PlatformInitLib for Tdx guest

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429

There are below changes in PlatformInitLib for Tdx guest:

1. Publish ram regions
In Tdx guest, the system memory is passed in TdHob by host VMM. So
the major task of PlatformTdxPublishRamRegions is to walk thru the
TdHob list and transfer the ResourceDescriptorHob and MemoryAllocationHob
to the hobs in DXE phase.

2. Build MemoryAllocationHob for Tdx Mailbox and Ovmf work area.

3. Update of PlatformAddressWidthInitialization. The physical
address width that Tdx guest supports is either 48 or 52.

4. Update of PlatformMemMapInitialization.
0xA - 0xF is VGA bios region.  Platform initialization marks the
region as MMIO region. Dxe code maps MMIO region as IO region.
As TDX guest, MMIO region is maps as shared.  However VGA BIOS doesn't need
to be shared.  Guest TDX Linux maps VGA BIOS as private and accesses for
BIOS and stuck on repeating EPT violation.  VGA BIOS (more generally ROM
region) should be private.  Skip marking VGA BIOA region [0xa000, 0xf]
as MMIO in HOB.

Cc: Ard Biesheuvel 
Cc: Jordan Justen 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Acked-by: Gerd Hoffmann 
Signed-off-by: Min Xu 
---
 OvmfPkg/Include/Library/PlatformInitLib.h | 14 ++
 OvmfPkg/Library/PlatformInitLib/IntelTdx.c| 49 +++
 .../Library/PlatformInitLib/IntelTdxNull.c| 16 ++
 OvmfPkg/Library/PlatformInitLib/MemDetect.c   | 14 ++
 OvmfPkg/Library/PlatformInitLib/Platform.c|  4 +-
 5 files changed, 96 insertions(+), 1 deletion(-)

diff --git a/OvmfPkg/Include/Library/PlatformInitLib.h 
b/OvmfPkg/Include/Library/PlatformInitLib.h
index 6152a43d0da7..2987a367cc9c 100644
--- a/OvmfPkg/Include/Library/PlatformInitLib.h
+++ b/OvmfPkg/Include/Library/PlatformInitLib.h
@@ -220,4 +220,18 @@ ProcessTdxHobList (
   VOID
   );
 
+/**
+  In Tdx guest, the system memory is passed in TdHob by host VMM. So
+  the major task of PlatformTdxPublishRamRegions is to walk thru the
+  TdHob list and transfer the ResourceDescriptorHob and MemoryAllocationHob
+  to the hobs in DXE phase.
+
+  MemoryAllocationHob should also be created for Mailbox and Ovmf work area.
+**/
+VOID
+EFIAPI
+PlatformTdxPublishRamRegions (
+  VOID
+  );
+
 #endif // PLATFORM_INIT_LIB_H_
diff --git a/OvmfPkg/Library/PlatformInitLib/IntelTdx.c 
b/OvmfPkg/Library/PlatformInitLib/IntelTdx.c
index e9196b7ffaa7..c6d7c8bb6e0e 100644
--- a/OvmfPkg/Library/PlatformInitLib/IntelTdx.c
+++ b/OvmfPkg/Library/PlatformInitLib/IntelTdx.c
@@ -512,3 +512,52 @@ TransferTdxHobList (
 Hob.Raw = GET_NEXT_HOB (Hob);
   }
 }
+
+/**
+  In Tdx guest, the system memory is passed in TdHob by host VMM. So
+  the major task of PlatformTdxPublishRamRegions is to walk thru the
+  TdHob list and transfer the ResourceDescriptorHob and MemoryAllocationHob
+  to the hobs in DXE phase.
+
+  MemoryAllocationHob should also be created for Mailbox and Ovmf work area.
+**/
+VOID
+EFIAPI
+PlatformTdxPublishRamRegions (
+  VOID
+  )
+{
+  if (!TdIsEnabled ()) {
+return;
+  }
+
+  TransferTdxHobList ();
+
+  //
+  // The memory region defined by PcdOvmfSecGhcbBackupBase is pre-allocated by
+  // host VMM and used as the td mailbox at the beginning of system boot.
+  //
+  BuildMemoryAllocationHob (
+FixedPcdGet32 (PcdOvmfSecGhcbBackupBase),
+FixedPcdGet32 (PcdOvmfSecGhcbBackupSize),
+EfiACPIMemoryNVS
+);
+
+  if (FixedPcdGet32 (PcdOvmfWorkAreaSize) != 0) {
+//
+// Reserve the work area.
+//
+// Since this memory range will be used by the Reset Vector on S3
+// resume, it must be reserved as ACPI NVS.
+//
+// If S3 is unsupported, then various drivers might still write to the
+// work area. We ought to prevent DXE from serving allocation requests
+// such that they would overlap the work area.
+//
+BuildMemoryAllocationHob (
+  (EFI_PHYSICAL_ADDRESS)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaBase),
+  (UINT64)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaSize),
+  EfiBootServicesData
+  );
+  }
+}
diff --git a/OvmfPkg/Library/PlatformInitLib/IntelTdxNull.c 
b/OvmfPkg/Library/PlatformInitLib/IntelTdxNull.c
index af90e0866e89..3ebe582af8de 100644
--- a/OvmfPkg/Library/PlatformInitLib/IntelTdxNull.c
+++ b/OvmfPkg/Library/PlatformInitLib/IntelTdxNull.c
@@ -28,3 +28,19 @@ ProcessTdxHobList (
 {
   return EFI_UNSUPPORTED;
 }
+
+/**
+  In Tdx guest, the system memory is passed in TdHob by host VMM. So
+  the major task of PlatformTdxPublishRamRegions is to walk thru the
+  TdHob list and transfer the ResourceDescriptorHob and MemoryAllocationHob
+  to the hobs in DXE phase.
+
+  MemoryAllocationHob should also be created for Mailbox and Ovmf work area.
+**/
+VOID
+EFIAPI
+PlatformTdxPublishRamRegions (
+  VOID
+  )
+{
+}
diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c 
b/OvmfPkg/Library/PlatformInitLib/MemDetect.c
index 911c0906cb3d..4c1dedf863c3 100644
--- 

[edk2-devel] [PATCH V9 35/47] MdeModulePkg: Skip setting IA32_ERER.NXE if it has already been set

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429

If IA32_ERER.NXE has already been set, skip setting it again.

Cc: Jian J Wang 
Cc: Hao A Wu 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Acked-by: Gerd Hoffmann 
Reviewed-by: Jian J Wang 
Signed-off-by: Min Xu 
---
 MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c 
b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
index 1ebab2782010..a451ca160408 100644
--- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
+++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
@@ -179,9 +179,11 @@ EnableExecuteDisableBit (
 {
   UINT64  MsrRegisters;
 
-  MsrRegisters  = AsmReadMsr64 (0xC080);
-  MsrRegisters |= BIT11;
-  AsmWriteMsr64 (0xC080, MsrRegisters);
+  MsrRegisters = AsmReadMsr64 (0xC080);
+  if ((MsrRegisters & BIT11) == 0) {
+MsrRegisters |= BIT11;
+AsmWriteMsr64 (0xC080, MsrRegisters);
+  }
 }
 
 /**
-- 
2.29.2.windows.2



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[edk2-devel] [PATCH V9 37/47] UefiCpuPkg: Update AddressEncMask in CpuPageTable

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429

MMIO region in Tdx guest is set with PcdTdxSharedBitMask in TdxDxe's
entry point. In SEV guest the page table entries is set with
PcdPteMemoryEncryptionAddressOrMask when creating 1:1 identity table.

So the AddressEncMask in GetPageTableEntry (@CpuPageTable.c) is either
PcdPteMemoryEncryptionAddressOrMask (in SEV guest), or
PcdTdxSharedBitMask (in TDX guest), or all-0 (in Legacy guest).

Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Acked-by: Gerd Hoffmann 
Reviewed-by: Ray Ni 
Signed-off-by: Min Xu 
---
 UefiCpuPkg/CpuDxe/CpuDxe.inf | 1 +
 UefiCpuPkg/CpuDxe/CpuPageTable.c | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf
index d87fe503d152..235241899222 100644
--- a/UefiCpuPkg/CpuDxe/CpuDxe.inf
+++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf
@@ -80,6 +80,7 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask## 
CONSUMES
   gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList  ## 
CONSUMES
   gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize## 
CONSUMES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdTdxSharedBitMask## 
CONSUMES
 
 [Depex]
   TRUE
diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c b/UefiCpuPkg/CpuDxe/CpuPageTable.c
index d9e65ab4b22a..f7a4d92e921a 100644
--- a/UefiCpuPkg/CpuDxe/CpuPageTable.c
+++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c
@@ -307,6 +307,9 @@ GetPageTableEntry (
   // Make sure AddressEncMask is contained to smallest supported address field.
   //
   AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & 
PAGING_1G_ADDRESS_MASK_64;
+  if (AddressEncMask == 0) {
+AddressEncMask = PcdGet64 (PcdTdxSharedBitMask) & 
PAGING_1G_ADDRESS_MASK_64;
+  }
 
   if (PagingContext->MachineType == IMAGE_FILE_MACHINE_X64) {
 if ((PagingContext->ContextData.X64.Attributes & 
PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_5_LEVEL) != 0) {
-- 
2.29.2.windows.2



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[edk2-devel] [PATCH V9 32/47] OvmfPkg/Sec: Declare local variable as volatile in SecCoreStartupWithStack

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429

Declare the local variables in SecCoreStartupWithStack that actually
move the data elements as volatile to prevent the optimizer from
replacing this function with the intrinsic memcpy().

Cc: Ard Biesheuvel 
Cc: Jordan Justen 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Signed-off-by: Min Xu 
---
 OvmfPkg/Sec/SecMain.c | 15 ++-
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/OvmfPkg/Sec/SecMain.c b/OvmfPkg/Sec/SecMain.c
index 2c5561661ef3..02520e25ab9a 100644
--- a/OvmfPkg/Sec/SecMain.c
+++ b/OvmfPkg/Sec/SecMain.c
@@ -757,12 +757,17 @@ SecCoreStartupWithStack (
   //
   IdtTableInStack.PeiService = NULL;
   for (Index = 0; Index < SEC_IDT_ENTRY_COUNT; Index++) {
-UINT8  *Src;
-UINT8  *Dst;
-UINTN  Byte;
+//
+// Declare the local variables that actually move the data elements as
+// volatile to prevent the optimizer from replacing this function with
+// the intrinsic memcpy()
+//
+CONST UINT8 *Src;
+volatile UINT8  *Dst;
+UINTN   Byte;
 
-Src = (UINT8 *)
-Dst = (UINT8 *)[Index];
+Src = (CONST UINT8 *)
+Dst = (volatile UINT8 *)[Index];
 for (Byte = 0; Byte < sizeof (mIdtEntryTemplate); Byte++) {
   Dst[Byte] = Src[Byte];
 }
-- 
2.29.2.windows.2



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[edk2-devel] [PATCH V9 34/47] OvmfPkg: Check Tdx in QemuFwCfgPei to avoid DMA operation

[Min Xu]

RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429

If TDX is enabled then we do not support DMA operation in PEI phase.
This is mainly because DMA in TDX guest requires using bounce buffer
(which need to allocate dynamic memory and allocating a PAGE size'd
buffer can be challenge in PEI phase).

Cc: Ard Biesheuvel 
Cc: Jordan Justen 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Acked-by: Gerd Hoffmann 
Signed-off-by: Min Xu 
---
 .../QemuFwCfgLib/QemuFwCfgLibInternal.h   | 11 +++
 OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c   | 32 +++
 .../Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf  |  2 ++
 3 files changed, 45 insertions(+)

diff --git a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLibInternal.h 
b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLibInternal.h
index 0b77cad1c030..6f7beb6ac1c7 100644
--- a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLibInternal.h
+++ b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLibInternal.h
@@ -59,4 +59,15 @@ InternalQemuFwCfgDmaBytes (
   IN UINT32  Control
   );
 
+/**
+  Check if it is Tdx guest
+
+  @retvalTRUE   It is Tdx guest
+  @retvalFALSE  It is not Tdx guest
+**/
+BOOLEAN
+QemuFwCfgIsTdxGuest (
+  VOID
+  );
+
 #endif
diff --git a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c 
b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c
index f696fb7cacaa..b8230613dcea 100644
--- a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c
+++ b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c
@@ -14,12 +14,30 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "QemuFwCfgLibInternal.h"
 
 STATIC BOOLEAN  mQemuFwCfgSupported = FALSE;
 STATIC BOOLEAN  mQemuFwCfgDmaSupported;
 
+/**
+  Check if it is Tdx guest
+
+  @retvalTRUE   It is Tdx guest
+  @retvalFALSE  It is not Tdx guest
+**/
+BOOLEAN
+QemuFwCfgIsTdxGuest (
+  VOID
+  )
+{
+  CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER  *CcWorkAreaHeader;
+
+  CcWorkAreaHeader = (CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER *)FixedPcdGet32 
(PcdOvmfWorkAreaBase);
+  return (CcWorkAreaHeader != NULL && CcWorkAreaHeader->GuestType == 
GUEST_TYPE_INTEL_TDX);
+}
+
 /**
   Returns a boolean indicating if the firmware configuration interface
   is available or not.
@@ -81,6 +99,14 @@ QemuFwCfgInitialize (
 //
 if (MemEncryptSevIsEnabled ()) {
   DEBUG ((DEBUG_INFO, "SEV: QemuFwCfg fallback to IO Port interface.\n"));
+} else if (QemuFwCfgIsTdxGuest ()) {
+  //
+  // If TDX is enabled then we do not support DMA operations in PEI phase.
+  // This is mainly because DMA in TDX guest requires using bounce buffer
+  // (which need to allocate dynamic memory and allocating a PAGE size'd
+  // buffer can be challenge in PEI phase)
+  //
+  DEBUG ((DEBUG_INFO, "TDX: QemuFwCfg fallback to IO Port interface.\n"));
 } else {
   mQemuFwCfgDmaSupported = TRUE;
   DEBUG ((DEBUG_INFO, "QemuFwCfg interface (DMA) is supported.\n"));
@@ -163,6 +189,12 @@ InternalQemuFwCfgDmaBytes (
   //
   ASSERT (!MemEncryptSevIsEnabled ());
 
+  //
+  // TDX does not support DMA operations in PEI stage, we should
+  // not have reached here.
+  //
+  ASSERT (!QemuFwCfgIsTdxGuest ());
+
   Access.Control = SwapBytes32 (Control);
   Access.Length  = SwapBytes32 (Size);
   Access.Address = SwapBytes64 ((UINTN)Buffer);
diff --git a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf 
b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf
index 9f9af7d03201..3910511880c9 100644
--- a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf
+++ b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf
@@ -43,3 +43,5 @@
   MemoryAllocationLib
   MemEncryptSevLib
 
+[Pcd]
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase
-- 
2.29.2.windows.2



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[edk2-devel] [PATCH V9 31/47] OvmfPkg: Update PlatformInitLib to process Tdx hoblist

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429

When host VMM create the Td guest, the system memory informations are
stored in TdHob, which is a memory region described in Tdx metadata.
The system memory region in TdHob should be accepted before it can be
accessed. So the newly added function (ProcessTdxHobList) is to process
the TdHobList to accept the memory. Because TdHobList is provided by
host VMM which is not trusted, so its content should be checked before
it is consumed by TDVF.

Because ProcessTdxHobList is to be called in SEC phase, so
PlatformInitLib.inf is updated to support SEC.

Note: In this patch it is BSP which accepts the pages. So there maybe
boot performance issue. There are some mitigations to this issue, such
as lazy accept, 2M accept page size, etc. We will re-visit here in the
future.

EFI_RESOURCE_MEMORY_UNACCEPTED is a new ResourceType in
EFI_HOB_RESOURCE_DESCRIPTOR. It is defined for the unaccepted memory
passed from Host VMM. This is proposed in microsoft/mu_basecore#66
files#diff-b20a11152d1ce9249c691be5690b4baf52069efadf2e2546cdd2eb663d80c9
e4R237 according to UEFI-Code-First. The proposal was approved in 2021
in UEFI Mantis, and will be added to the new PI.next specification.

Per the MdePkg reviewer's comments, before this new ResourceType is
added in the PI spec, it should not be in MdePkg. So it is now
defined as an internal implementation and will be moved to
MdePkg/Include/Pi/PiHob.h after it is added in PI spec.
See https://edk2.groups.io/g/devel/message/87641

PcdTdxAcceptPageSize is added for page accepting. Currently TDX supports
4K and 2M accept page size. The default value is 2M.

Tdx guest is only supported in X64. So for IA32 ProcessTdxHobList
just returns EFI_UNSUPPORTED.

Cc: Ard Biesheuvel 
Cc: Jordan Justen 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Acked-by: Gerd Hoffmann 
Signed-off-by: Min Xu 
---
 OvmfPkg/Include/Library/PlatformInitLib.h |  17 +
 OvmfPkg/Library/PlatformInitLib/IntelTdx.c| 514 ++
 .../Library/PlatformInitLib/IntelTdxNull.c|  30 +
 .../PlatformInitLib/PlatformInitLib.inf   |  13 +-
 OvmfPkg/OvmfPkg.dec   |   3 +
 5 files changed, 576 insertions(+), 1 deletion(-)
 create mode 100644 OvmfPkg/Library/PlatformInitLib/IntelTdx.c
 create mode 100644 OvmfPkg/Library/PlatformInitLib/IntelTdxNull.c

diff --git a/OvmfPkg/Include/Library/PlatformInitLib.h 
b/OvmfPkg/Include/Library/PlatformInitLib.h
index b31f521578c2..6152a43d0da7 100644
--- a/OvmfPkg/Include/Library/PlatformInitLib.h
+++ b/OvmfPkg/Include/Library/PlatformInitLib.h
@@ -203,4 +203,21 @@ PlatformMaxCpuCountInitialization (
   IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
   );
 
+/**
+  In Tdx guest, some information need to be passed from host VMM to guest
+  firmware. For example, the memory resource, etc. These information are
+  prepared by host VMM and put in HobList which is described in TdxMetadata.
+
+  Information in HobList is treated as external input. From the security
+  perspective before it is consumed, it should be validated.
+
+  @retval   EFI_SUCCESS   Successfully process the hoblist
+  @retval   OthersOther error as indicated
+**/
+EFI_STATUS
+EFIAPI
+ProcessTdxHobList (
+  VOID
+  );
+
 #endif // PLATFORM_INIT_LIB_H_
diff --git a/OvmfPkg/Library/PlatformInitLib/IntelTdx.c 
b/OvmfPkg/Library/PlatformInitLib/IntelTdx.c
new file mode 100644
index ..e9196b7ffaa7
--- /dev/null
+++ b/OvmfPkg/Library/PlatformInitLib/IntelTdx.c
@@ -0,0 +1,514 @@
+/** @file
+  Initialize Intel TDX support.
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ALIGNED_2MB_MASK0x1f
+#define EFI_RESOURCE_MEMORY_UNACCEPTED  7
+
+/**
+  This function will be called to accept pages. Only BSP accepts pages.
+
+  TDCALL(ACCEPT_PAGE) supports the accept page size of 4k and 2M. To
+  simplify the implementation, the Memory to be accpeted is splitted
+  into 3 parts:
+  -  <-- StartAddress1 (not 2M aligned)
+  |  part 1   |  Length1 < 2M
+  |---|  <-- StartAddress2 (2M aligned)
+  |   |  Length2 = Integer multiples of 2M
+  |  part 2   |
+  |   |
+  |---|  <-- StartAddress3
+  |  part 3   |  Length3 < 2M
+  |---|
+
+  @param[in] PhysicalAddress   Start physical adress
+  @param[in] PhysicalEnd   End physical address
+
+  @retvalEFI_SUCCESS   Accept memory successfully
+  @retvalOthersOther errors as indicated
+**/
+EFI_STATUS
+EFIAPI
+BspAcceptMemoryResourceRange (
+  IN EFI_PHYSICAL_ADDRESS  PhysicalAddress,
+  IN EFI_PHYSICAL_ADDRESS  PhysicalEnd
+  )
+{
+  

[edk2-devel] [PATCH V9 33/47] OvmfPkg: Update Sec to support Tdx

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429

There are below major changes in this commit.

1. SecEntry.nasm
In TDX BSP and APs goes to the same entry point in SecEntry.nasm.

BSP initialize the temporary stack and then jumps to SecMain, just as
legacy Ovmf does.

APs spin in a modified mailbox loop using initial mailbox structure.
Its structure defition is in OvmfPkg/Include/IndustryStandard/IntelTdx.h.
APs wait for command to see if the command is for me. If so execute the
command.

2. Sec/SecMain.c
When host VMM create the Td guest, the system memory informations are
stored in TdHob, which is a memory region described in Tdx metadata.
The system memory region in TdHob should be accepted before it can be
accessed. So the major task of this patch is to process the TdHobList
to accept the memory. After that TDVF follow the standard OVMF flow
and jump to PEI phase.

PcdUse1GPageTable is set to FALSE by default in OvmfPkgX64.dsc. It gives
no chance for Intel TDX to support 1G page table. To support 1G page
table this PCD is set to TRUE in OvmfPkgX64.dsc.

TDX_GUEST_SUPPORTED is defined in OvmfPkgX64.dsc. This macro wraps the
Tdx specific code.

TDX only works on X64, so the code is only valid in X64 arch.

Cc: Ard Biesheuvel 
Cc: Jordan Justen 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Acked-by: Gerd Hoffmann 
Signed-off-by: Min Xu 
---
 OvmfPkg/AmdSev/AmdSevX64.dsc  |  1 +
 OvmfPkg/Bhyve/BhyveX64.dsc|  1 +
 OvmfPkg/CloudHv/CloudHvX64.dsc|  1 +
 OvmfPkg/Include/TdxCommondefs.inc | 51 +++
 OvmfPkg/Microvm/MicrovmX64.dsc|  1 +
 OvmfPkg/OvmfPkgIa32X64.dsc|  2 +
 OvmfPkg/OvmfPkgX64.dsc| 14 ++
 OvmfPkg/OvmfXen.dsc   |  1 +
 OvmfPkg/Sec/SecMain.c | 29 ++-
 OvmfPkg/Sec/SecMain.inf   |  3 ++
 OvmfPkg/Sec/X64/SecEntry.nasm | 82 +++
 11 files changed, 184 insertions(+), 2 deletions(-)
 create mode 100644 OvmfPkg/Include/TdxCommondefs.inc

diff --git a/OvmfPkg/AmdSev/AmdSevX64.dsc b/OvmfPkg/AmdSev/AmdSevX64.dsc
index 785049c88962..c173a72134f4 100644
--- a/OvmfPkg/AmdSev/AmdSevX64.dsc
+++ b/OvmfPkg/AmdSev/AmdSevX64.dsc
@@ -208,6 +208,7 @@
 [LibraryClasses.common]
   BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
   VmgExitLib|OvmfPkg/Library/VmgExitLib/VmgExitLib.inf
+  TdxLib|MdePkg/Library/TdxLib/TdxLib.inf
 
 [LibraryClasses.common.SEC]
   TimerLib|OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.inf
diff --git a/OvmfPkg/Bhyve/BhyveX64.dsc b/OvmfPkg/Bhyve/BhyveX64.dsc
index 5fa08bebd73c..656e407473bb 100644
--- a/OvmfPkg/Bhyve/BhyveX64.dsc
+++ b/OvmfPkg/Bhyve/BhyveX64.dsc
@@ -228,6 +228,7 @@
 [LibraryClasses.common]
   BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
   VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf
+  TdxLib|MdePkg/Library/TdxLib/TdxLib.inf
 
 [LibraryClasses.common.SEC]
 !ifdef $(DEBUG_ON_SERIAL_PORT)
diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc
index b8a82380202c..c307f1cc7550 100644
--- a/OvmfPkg/CloudHv/CloudHvX64.dsc
+++ b/OvmfPkg/CloudHv/CloudHvX64.dsc
@@ -237,6 +237,7 @@
 [LibraryClasses.common]
   BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
   VmgExitLib|OvmfPkg/Library/VmgExitLib/VmgExitLib.inf
+  TdxLib|MdePkg/Library/TdxLib/TdxLib.inf
 
 [LibraryClasses.common.SEC]
   TimerLib|OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.inf
diff --git a/OvmfPkg/Include/TdxCommondefs.inc 
b/OvmfPkg/Include/TdxCommondefs.inc
new file mode 100644
index ..970eac96592a
--- /dev/null
+++ b/OvmfPkg/Include/TdxCommondefs.inc
@@ -0,0 +1,51 @@
+;--
+; @file
+; TDX Common defitions used by the APs in mailbox
+;
+; Copyright (c) 2021, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;--
+
+CommandOffset equ   00h
+ApicidOffset  equ   04h
+WakeupVectorOffsetequ   08h
+OSArgsOffset  equ   10h
+FirmwareArgsOffsetequ   800h
+WakeupArgsRelocatedMailBoxequ   800h
+AcceptPageArgsPhysicalStart   equ   800h
+AcceptPageArgsPhysicalEnd equ   808h
+AcceptPageArgsChunkSize   equ   810h
+AcceptPageArgsPageSizeequ   818h
+CpuArrivalOffset  equ   900h
+CpusExitingOffset equ   0a00h
+TalliesOffset equ   0a08h
+ErrorsOffset  equ   0e08h
+
+SIZE_4KB  equ   1000h
+SIZE_2MB  equ   20h

[edk2-devel] [PATCH V9 30/47] OvmfPkg/PlatformInitLib: Move functions to Platform.c

[Min Xu]

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863

Move functions in PlatformPei/Platform.c to PlatformInitLib/Platform.c.

Cc: Ard Biesheuvel 
Cc: Jordan Justen 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Cc: Sebastien Boeuf 
Acked-by: Gerd Hoffmann 
Signed-off-by: Min Xu 
---
 OvmfPkg/Include/Library/PlatformInitLib.h  |  34 ++
 OvmfPkg/Library/PlatformInitLib/Platform.c | 465 +
 OvmfPkg/PlatformPei/Platform.c | 451 
 3 files changed, 499 insertions(+), 451 deletions(-)

diff --git a/OvmfPkg/Include/Library/PlatformInitLib.h 
b/OvmfPkg/Include/Library/PlatformInitLib.h
index 62020efadf37..b31f521578c2 100644
--- a/OvmfPkg/Include/Library/PlatformInitLib.h
+++ b/OvmfPkg/Include/Library/PlatformInitLib.h
@@ -169,4 +169,38 @@ PlatformQemuInitializeRamForS3 (
   IN EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
   );
 
+VOID
+EFIAPI
+PlatformMemMapInitialization (
+  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
+  );
+
+/**
+ * Fetch "opt/ovmf/PcdSetNxForStack" from QEMU
+ *
+ * @param Setting The pointer to the setting of 
"/opt/ovmf/PcdSetNxForStack".
+ * @return EFI_SUCCESS  Successfully fetch the settings.
+ */
+EFI_STATUS
+EFIAPI
+PlatformNoexecDxeInitialization (
+  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
+  );
+
+VOID
+EFIAPI
+PlatformMiscInitialization (
+  IN EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
+  );
+
+/**
+  Fetch the boot CPU count and the possible CPU count from QEMU, and expose
+  them to UefiCpuPkg modules.
+**/
+VOID
+EFIAPI
+PlatformMaxCpuCountInitialization (
+  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
+  );
+
 #endif // PLATFORM_INIT_LIB_H_
diff --git a/OvmfPkg/Library/PlatformInitLib/Platform.c 
b/OvmfPkg/Library/PlatformInitLib/Platform.c
index e41f230ff563..c4fa7d445394 100644
--- a/OvmfPkg/Library/PlatformInitLib/Platform.c
+++ b/OvmfPkg/Library/PlatformInitLib/Platform.c
@@ -19,6 +19,18 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
 #include 
 
 VOID
@@ -104,3 +116,456 @@ PlatformAddMemoryRangeHob (
 {
   PlatformAddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - 
MemoryBase));
 }
+
+VOID
+EFIAPI
+PlatformMemMapInitialization (
+  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
+  )
+{
+  UINT64  PciIoBase;
+  UINT64  PciIoSize;
+  UINT32  TopOfLowRam;
+  UINT64  PciExBarBase;
+  UINT32  PciBase;
+  UINT32  PciSize;
+
+  PciIoBase = 0xC000;
+  PciIoSize = 0x4000;
+
+  //
+  // Video memory + Legacy BIOS region
+  //
+  PlatformAddIoMemoryRangeHob (0x0A, BASE_1MB);
+
+  if (PlatformInfoHob->HostBridgeDevId == 0x /* microvm */) {
+PlatformAddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB);
+PlatformAddIoMemoryBaseSizeHob (0xFEC0, SIZE_4KB); /* ioapic #1 */
+PlatformAddIoMemoryBaseSizeHob (0xFEC1, SIZE_4KB); /* ioapic #2 */
+return;
+  }
+
+  TopOfLowRam  = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob);
+  PciExBarBase = 0;
+  if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
+//
+// The MMCONFIG area is expected to fall between the top of low RAM and
+// the base of the 32-bit PCI host aperture.
+//
+PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
+ASSERT (TopOfLowRam <= PciExBarBase);
+ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
+PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
+  } else {
+ASSERT (TopOfLowRam <= PlatformInfoHob->Uc32Base);
+PciBase = PlatformInfoHob->Uc32Base;
+  }
+
+  //
+  // address   purpose   size
+  //     -
+  // max(top, 2g)  PCI MMIO  0xFC00 - max(top, 2g)
+  // 0xFC00gap   44 MB
+  // 0xFEC0IO-APIC4 KB
+  // 0xFEC01000gap 1020 KB
+  // 0xFED0HPET   1 KB
+  // 0xFED00400gap  111 KB
+  // 0xFED1C000gap (PIIX4) / RCRB (ICH9) 16 KB
+  // 0xFED2gap  896 KB
+  // 0xFEE0LAPIC  1 MB
+  //
+  PciSize = 0xFC00 - PciBase;
+  PlatformAddIoMemoryBaseSizeHob (PciBase, PciSize);
+
+  PlatformInfoHob->PcdPciMmio32Base = PciBase;
+  PlatformInfoHob->PcdPciMmio32Size = PciSize;
+
+  PlatformAddIoMemoryBaseSizeHob (0xFEC0, SIZE_4KB);
+  PlatformAddIoMemoryBaseSizeHob (0xFED0, SIZE_1KB);
+  if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
+PlatformAddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
+//
+// Note: there should be an
+//
+//   PlatformAddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
+//
+// call below, just like the one above for RCBA. However, Linux insists
+// that the MMCONFIG area be marked in the E820 or UEFI memory map as
+// "reserved memory" 

[edk2-devel] [PATCH V9 29/47] OvmfPkg/PlatformInitLib: Create MemDetect.c

[Min Xu]

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863

Move functions in PlatformPei\MemDetect.c to PlatformInitLib\MemDetect.c.

Cc: Ard Biesheuvel 
Cc: Jordan Justen 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Cc: Sebastien Boeuf 
Acked-by: Gerd Hoffmann 
Signed-off-by: Min Xu 
---
 OvmfPkg/Include/Library/PlatformInitLib.h |  37 +
 OvmfPkg/Library/PlatformInitLib/MemDetect.c   | 842 ++
 .../PlatformInitLib/PlatformInitLib.inf   |  49 +
 OvmfPkg/PlatformPei/MemDetect.c   | 804 +
 OvmfPkg/PlatformPei/Platform.h|  12 -
 5 files changed, 929 insertions(+), 815 deletions(-)
 create mode 100644 OvmfPkg/Library/PlatformInitLib/MemDetect.c

diff --git a/OvmfPkg/Include/Library/PlatformInitLib.h 
b/OvmfPkg/Include/Library/PlatformInitLib.h
index 9b99d4c1f514..62020efadf37 100644
--- a/OvmfPkg/Include/Library/PlatformInitLib.h
+++ b/OvmfPkg/Include/Library/PlatformInitLib.h
@@ -132,4 +132,41 @@ PlatformAddReservedMemoryBaseSizeHob (
   IN BOOLEAN   Cacheable
   );
 
+VOID
+EFIAPI
+PlatformQemuUc32BaseInitialization (
+  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
+  );
+
+UINT32
+EFIAPI
+PlatformGetSystemMemorySizeBelow4gb (
+  IN EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
+  );
+
+/**
+  Initialize the PhysMemAddressWidth field in PlatformInfoHob based on guest 
RAM size.
+**/
+VOID
+EFIAPI
+PlatformAddressWidthInitialization (
+  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
+  );
+
+/**
+  Peform Memory Detection for QEMU / KVM
+
+**/
+VOID
+EFIAPI
+PlatformQemuInitializeRam (
+  IN EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
+  );
+
+VOID
+EFIAPI
+PlatformQemuInitializeRamForS3 (
+  IN EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
+  );
+
 #endif // PLATFORM_INIT_LIB_H_
diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c 
b/OvmfPkg/Library/PlatformInitLib/MemDetect.c
new file mode 100644
index ..911c0906cb3d
--- /dev/null
+++ b/OvmfPkg/Library/PlatformInitLib/MemDetect.c
@@ -0,0 +1,842 @@
+/**@file
+  Memory Detection for Virtual Machines.
+
+  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+Module Name:
+
+  MemDetect.c
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+//
+// The Library classes this module consumes
+//
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+VOID
+EFIAPI
+PlatformQemuUc32BaseInitialization (
+  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
+  )
+{
+  UINT32  LowerMemorySize;
+
+  if (PlatformInfoHob->HostBridgeDevId == 0x /* microvm */) {
+return;
+  }
+
+  if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
+//
+// On q35, the 32-bit area that we'll mark as UC, through variable MTRRs,
+// starts at PcdPciExpressBaseAddress. The platform DSC is responsible for
+// setting PcdPciExpressBaseAddress such that describing the
+// [PcdPciExpressBaseAddress, 4GB) range require a very small number of
+// variable MTRRs (preferably 1 or 2).
+//
+ASSERT (FixedPcdGet64 (PcdPciExpressBaseAddress) <= MAX_UINT32);
+PlatformInfoHob->Uc32Base = (UINT32)FixedPcdGet64 
(PcdPciExpressBaseAddress);
+return;
+  }
+
+  if (PlatformInfoHob->HostBridgeDevId == CLOUDHV_DEVICE_ID) {
+PlatformInfoHob->Uc32Size = CLOUDHV_MMIO_HOLE_SIZE;
+PlatformInfoHob->Uc32Base = CLOUDHV_MMIO_HOLE_ADDRESS;
+return;
+  }
+
+  ASSERT (PlatformInfoHob->HostBridgeDevId == INTEL_82441_DEVICE_ID);
+  //
+  // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one
+  // variable MTRR suffices by truncating the size to a whole power of two,
+  // while keeping the end affixed to 4GB. This will round the base up.
+  //
+  LowerMemorySize   = PlatformGetSystemMemorySizeBelow4gb 
(PlatformInfoHob);
+  PlatformInfoHob->Uc32Size = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - 
LowerMemorySize));
+  PlatformInfoHob->Uc32Base = (UINT32)(SIZE_4GB - PlatformInfoHob->Uc32Size);
+  //
+  // Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most 2GB.
+  // Therefore Uc32Base is at least 2GB.
+  //
+  ASSERT (PlatformInfoHob->Uc32Base >= BASE_2GB);
+
+  if (PlatformInfoHob->Uc32Base != LowerMemorySize) {
+DEBUG ((
+  DEBUG_VERBOSE,
+  "%a: rounded UC32 base from 0x%x up to 0x%x, for "
+  "an UC32 size of 0x%x\n",
+  __FUNCTION__,
+  LowerMemorySize,
+  PlatformInfoHob->Uc32Base,
+  PlatformInfoHob->Uc32Size
+  ));
+  }
+}
+
+/**
+  Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map that start outside
+  of the 32-bit address range.
+
+  Find the highest exclusive >=4GB RAM address, or produce memory resource
+  descriptor HOBs for RAM entries that start at or above 4GB.
+

[edk2-devel] [PATCH V9 28/47] OvmfPkg/PlatformPei: Refactor MiscInitialization

[Min Xu]

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863

MiscInitialization is split into 2 functions:
 - PlatformMiscInitialization is for PlatformInitLib.
 - MiscInitialization calls PlatformMiscInitialization and then sets
   PCD. It is for PlatformPei.

Cc: Ard Biesheuvel 
Cc: Jordan Justen 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Cc: Sebastien Boeuf 
Acked-by: Gerd Hoffmann 
Signed-off-by: Min Xu 
---
 OvmfPkg/PlatformPei/Platform.c | 43 --
 1 file changed, 26 insertions(+), 17 deletions(-)

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index e91acca9f769..02697c473d01 100644
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -57,12 +57,12 @@ PlatformMemMapInitialization (
   IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
   )
 {
-  UINT64 PciIoBase;
-  UINT64 PciIoSize;
-  UINT32 TopOfLowRam;
-  UINT64 PciExBarBase;
-  UINT32 PciBase;
-  UINT32 PciSize;
+  UINT64  PciIoBase;
+  UINT64  PciIoSize;
+  UINT32  TopOfLowRam;
+  UINT64  PciExBarBase;
+  UINT32  PciBase;
+  UINT32  PciSize;
 
   PciIoBase = 0xC000;
   PciIoSize = 0x4000;
@@ -360,17 +360,16 @@ MiscInitializationForMicrovm (
 }
 
 VOID
-MiscInitialization (
+PlatformMiscInitialization (
   IN EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
   )
 {
-  UINTN  PmCmd;
-  UINTN  Pmba;
-  UINT32 PmbaAndVal;
-  UINT32 PmbaOrVal;
-  UINTN  AcpiCtlReg;
-  UINT8  AcpiEnBit;
-  RETURN_STATUS  PcdStatus;
+  UINTN   PmCmd;
+  UINTN   Pmba;
+  UINT32  PmbaAndVal;
+  UINT32  PmbaOrVal;
+  UINTN   AcpiCtlReg;
+  UINT8   AcpiEnBit;
 
   //
   // Disable A20 Mask
@@ -417,9 +416,6 @@ MiscInitialization (
   return;
   }
 
-  PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, 
PlatformInfoHob->HostBridgeDevId);
-  ASSERT_RETURN_ERROR (PcdStatus);
-
   if (PlatformInfoHob->HostBridgeDevId == CLOUDHV_DEVICE_ID) {
 DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor is done.\n", __FUNCTION__));
 return;
@@ -464,6 +460,19 @@ MiscInitialization (
   }
 }
 
+VOID
+MiscInitialization (
+  IN EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
+  )
+{
+  RETURN_STATUS  PcdStatus;
+
+  PlatformMiscInitialization (PlatformInfoHob);
+
+  PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, 
PlatformInfoHob->HostBridgeDevId);
+  ASSERT_RETURN_ERROR (PcdStatus);
+}
+
 VOID
 BootModeInitialization (
   IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
-- 
2.29.2.windows.2



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[edk2-devel] [PATCH V9 27/47] OvmfPkg/PlatformPei: Refactor NoexecDxeInitialization

[Min Xu]

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863

NoexecDxeInitialization is split into 2 functions:
 - PlatformNoexecDxeInitialization is for PlatformInitLib
 - NoexecDxeInitialization calls PlatformNoexecDxeInitialization and
   then sets PCD.

Cc: Ard Biesheuvel 
Cc: Jordan Justen 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Cc: Sebastien Boeuf 
Acked-by: Gerd Hoffmann 
Signed-off-by: Min Xu 
---
 OvmfPkg/PlatformPei/Platform.c | 34 +-
 1 file changed, 21 insertions(+), 13 deletions(-)

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index b83bd7515809..e91acca9f769 100644
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -59,7 +59,6 @@ PlatformMemMapInitialization (
 {
   UINT64 PciIoBase;
   UINT64 PciIoSize;
-  RETURN_STATUS  PcdStatus;
   UINT32 TopOfLowRam;
   UINT64 PciExBarBase;
   UINT32 PciBase;
@@ -199,24 +198,33 @@ MemMapInitialization (
   ASSERT_RETURN_ERROR (PcdStatus);
 }
 
-#define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName)   \
-  do {  \
-BOOLEAN   Setting;  \
-RETURN_STATUS PcdStatus;\
-\
-if (!RETURN_ERROR (QemuFwCfgParseBool ( \
-  "opt/ovmf/" #TokenName, ))) { \
-  PcdStatus = PcdSetBoolS (TokenName, Setting); \
-  ASSERT_RETURN_ERROR (PcdStatus);  \
-}   \
-  } while (0)
+/**
+ * Fetch "opt/ovmf/PcdSetNxForStack" from QEMU
+ *
+ * @param Setting The pointer to the setting of 
"/opt/ovmf/PcdSetNxForStack".
+ * @return EFI_SUCCESS  Successfully fetch the settings.
+ */
+EFI_STATUS
+EFIAPI
+PlatformNoexecDxeInitialization (
+  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
+  )
+{
+  return QemuFwCfgParseBool ("opt/ovmf/PcdSetNxForStack", 
>PcdSetNxForStack);
+}
 
 VOID
 NoexecDxeInitialization (
   VOID
   )
 {
-  UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);
+  RETURN_STATUS  Status;
+
+  Status = PlatformNoexecDxeInitialization ();
+  if (!RETURN_ERROR (Status)) {
+Status = PcdSetBoolS (PcdSetNxForStack, mPlatformInfoHob.PcdSetNxForStack);
+ASSERT_RETURN_ERROR (Status);
+  }
 }
 
 VOID
-- 
2.29.2.windows.2



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[edk2-devel] [PATCH V9 25/47] OvmfPkg/PlatformPei: Refactor InitializeRamRegions

[Min Xu]

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863

InitializeRamRegions is refactored into 3 calls:
 - PlatformQemuInitializeRam
 - SevInitializeRam
 - PlatformQemuInitializeRamForS3

SevInitializeRam is not in PlatformInitLib. Because in the first stage
PlatformInitLib only support the basic platform featues.

PlatformQemuInitializeRamForS3 wraps the code which was previously in
InitializeRamRegions (many code in 2 if-checks).

Cc: Ard Biesheuvel 
Cc: Jordan Justen 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Cc: Sebastien Boeuf 
Acked-by: Gerd Hoffmann 
Signed-off-by: Min Xu 
---
 OvmfPkg/PlatformPei/MemDetect.c | 40 -
 OvmfPkg/PlatformPei/Platform.c  |  2 +-
 OvmfPkg/PlatformPei/Platform.h  |  3 ++-
 3 files changed, 28 insertions(+), 17 deletions(-)

diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c
index 45f7eba65d04..23a583ed3386 100644
--- a/OvmfPkg/PlatformPei/MemDetect.c
+++ b/OvmfPkg/PlatformPei/MemDetect.c
@@ -161,7 +161,7 @@ PlatformQemuUc32BaseInitialization (
   // variable MTRR suffices by truncating the size to a whole power of two,
   // while keeping the end affixed to 4GB. This will round the base up.
   //
-  LowerMemorySize   = GetSystemMemorySizeBelow4gb (PlatformInfoHob);
+  LowerMemorySize   = PlatformGetSystemMemorySizeBelow4gb 
(PlatformInfoHob);
   PlatformInfoHob->Uc32Size = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - 
LowerMemorySize));
   PlatformInfoHob->Uc32Base = (UINT32)(SIZE_4GB - PlatformInfoHob->Uc32Size);
   //
@@ -372,7 +372,8 @@ GetHighestSystemMemoryAddressFromPvhMemmap (
 }
 
 UINT32
-GetSystemMemorySizeBelow4gb (
+EFIAPI
+PlatformGetSystemMemorySizeBelow4gb (
   IN EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
   )
 {
@@ -761,7 +762,7 @@ PublishPeiMemory (
   UINT32S3AcpiReservedMemoryBase;
   UINT32S3AcpiReservedMemorySize;
 
-  LowerMemorySize = GetSystemMemorySizeBelow4gb ();
+  LowerMemorySize = PlatformGetSystemMemorySizeBelow4gb ();
   if (mPlatformInfoHob.SmmSmramRequire) {
 //
 // TSEG is chipped from the end of low RAM
@@ -871,7 +872,7 @@ QemuInitializeRamBelow1gb (
 **/
 STATIC
 VOID
-QemuInitializeRam (
+PlatformQemuInitializeRam (
   IN EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
   )
 {
@@ -885,7 +886,7 @@ QemuInitializeRam (
   //
   // Determine total memory size available
   //
-  LowerMemorySize = GetSystemMemorySizeBelow4gb (PlatformInfoHob);
+  LowerMemorySize = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob);
 
   if (PlatformInfoHob->BootMode == BOOT_ON_S3_RESUME) {
 //
@@ -995,19 +996,12 @@ QemuInitializeRam (
   }
 }
 
-/**
-  Publish system RAM and reserve memory regions
-
-**/
+STATIC
 VOID
-InitializeRamRegions (
+PlatformQemuInitializeRamForS3 (
   IN EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
   )
 {
-  QemuInitializeRam (PlatformInfoHob);
-
-  SevInitializeRam ();
-
   if (PlatformInfoHob->S3Supported && (PlatformInfoHob->BootMode != 
BOOT_ON_S3_RESUME)) {
 //
 // This is the memory range that will be used for PEI on S3 resume
@@ -1113,7 +1107,7 @@ InitializeRamRegions (
   //
   TsegSize = PlatformInfoHob->Q35TsegMbytes * SIZE_1MB;
   BuildMemoryAllocationHob (
-GetSystemMemorySizeBelow4gb (PlatformInfoHob) - TsegSize,
+PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob) - TsegSize,
 TsegSize,
 EfiReservedMemoryType
 );
@@ -1152,3 +1146,19 @@ InitializeRamRegions (
  #endif
   }
 }
+
+/**
+  Publish system RAM and reserve memory regions
+
+**/
+VOID
+InitializeRamRegions (
+  IN EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
+  )
+{
+  PlatformQemuInitializeRam (PlatformInfoHob);
+
+  SevInitializeRam ();
+
+  PlatformQemuInitializeRamForS3 (PlatformInfoHob);
+}
diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 1275c9187e86..f89d14493ecf 100644
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -79,7 +79,7 @@ MemMapInitialization (
 return;
   }
 
-  TopOfLowRam  = GetSystemMemorySizeBelow4gb (PlatformInfoHob);
+  TopOfLowRam  = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob);
   PciExBarBase = 0;
   if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 //
diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h
index 038a806a1e1b..635d58379a24 100644
--- a/OvmfPkg/PlatformPei/Platform.h
+++ b/OvmfPkg/PlatformPei/Platform.h
@@ -35,7 +35,8 @@ PublishPeiMemory (
   );
 
 UINT32
-GetSystemMemorySizeBelow4gb (
+EFIAPI
+PlatformGetSystemMemorySizeBelow4gb (
   IN EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
   );
 
-- 
2.29.2.windows.2



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[edk2-devel] [PATCH V9 24/47] OvmfPkg/PlatformPei: Refactor QemuUc32BaseInitialization

[Min Xu]

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863

Rename QemuUc32BaseInitialization to PlatformQemuUc32BaseInitialization.
This function is for PlatformInitLib.

Cc: Ard Biesheuvel 
Cc: Jordan Justen 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Cc: Sebastien Boeuf 
Acked-by: Gerd Hoffmann 
Signed-off-by: Min Xu 
---
 OvmfPkg/PlatformPei/MemDetect.c | 3 ++-
 OvmfPkg/PlatformPei/Platform.c  | 2 +-
 OvmfPkg/PlatformPei/Platform.h  | 3 ++-
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c
index 5507d9585bab..45f7eba65d04 100644
--- a/OvmfPkg/PlatformPei/MemDetect.c
+++ b/OvmfPkg/PlatformPei/MemDetect.c
@@ -125,7 +125,8 @@ Q35SmramAtDefaultSmbaseInitialization (
 }
 
 VOID
-QemuUc32BaseInitialization (
+EFIAPI
+PlatformQemuUc32BaseInitialization (
   IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
   )
 {
diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 20e38a098d52..1275c9187e86 100644
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -780,7 +780,7 @@ InitializePlatform (
 
   PublishPeiMemory ();
 
-  QemuUc32BaseInitialization ();
+  PlatformQemuUc32BaseInitialization ();
 
   InitializeRamRegions ();
 
diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h
index ff4459d79fe4..038a806a1e1b 100644
--- a/OvmfPkg/PlatformPei/Platform.h
+++ b/OvmfPkg/PlatformPei/Platform.h
@@ -40,7 +40,8 @@ GetSystemMemorySizeBelow4gb (
   );
 
 VOID
-QemuUc32BaseInitialization (
+EFIAPI
+PlatformQemuUc32BaseInitialization (
   IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
   );
 
-- 
2.29.2.windows.2



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[edk2-devel] [PATCH V9 23/47] OvmfPkg/PlatformPei: Refactor MaxCpuCountInitialization

[Min Xu]

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863

MaxCpuCountInitialization is splitted into two:
 - PlatformMaxCpuCountInitialization is for PlatformInitLib
 - MaxCpuCountInitialization is for PlatformPei. It calls
   PlatformMaxCpuCountInitialization then sets PCDs.

Cc: Ard Biesheuvel 
Cc: Jordan Justen 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Cc: Sebastien Boeuf 
Signed-off-by: Min Xu 
---
 OvmfPkg/PlatformPei/Platform.c | 33 +++--
 1 file changed, 23 insertions(+), 10 deletions(-)

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 7d370c9b8fa8..20e38a098d52 100644
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -539,16 +539,15 @@ Q35BoardVerification (
 
 /**
   Fetch the boot CPU count and the possible CPU count from QEMU, and expose
-  them to UefiCpuPkg modules. Set the mMaxCpuCount variable.
+  them to UefiCpuPkg modules. Set the MaxCpuCount field in PlatformInfoHob.
 **/
 VOID
-MaxCpuCountInitialization (
+PlatformMaxCpuCountInitialization (
   IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
   )
 {
-  UINT16 BootCpuCount;
-  UINT32 MaxCpuCount;
-  RETURN_STATUS  PcdStatus;
+  UINT16  BootCpuCount;
+  UINT32  MaxCpuCount;
 
   //
   // Try to fetch the boot CPU count.
@@ -705,15 +704,29 @@ MaxCpuCountInitialization (
 ));
   ASSERT (BootCpuCount <= MaxCpuCount);
 
-  PcdStatus = PcdSet32S (PcdCpuBootLogicalProcessorNumber, BootCpuCount);
-  ASSERT_RETURN_ERROR (PcdStatus);
-  PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, MaxCpuCount);
-  ASSERT_RETURN_ERROR (PcdStatus);
-
   PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber  = MaxCpuCount;
   PlatformInfoHob->PcdCpuBootLogicalProcessorNumber = BootCpuCount;
 }
 
+/**
+  Fetch the boot CPU count and the possible CPU count from QEMU, and expose
+  them to UefiCpuPkg modules. Set the MaxCpuCount field in PlatformInfoHob.
+**/
+VOID
+MaxCpuCountInitialization (
+  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
+  )
+{
+  RETURN_STATUS  PcdStatus;
+
+  PlatformMaxCpuCountInitialization (PlatformInfoHob);
+
+  PcdStatus = PcdSet32S (PcdCpuBootLogicalProcessorNumber, 
PlatformInfoHob->PcdCpuBootLogicalProcessorNumber);
+  ASSERT_RETURN_ERROR (PcdStatus);
+  PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, 
PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber);
+  ASSERT_RETURN_ERROR (PcdStatus);
+}
+
 /**
   Perform Platform PEI initialization.
 
-- 
2.29.2.windows.2



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[edk2-devel] [PATCH V9 22/47] OvmfPkg/PlatformPei: Refactor AddressWidthInitialization

[Min Xu]

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863

>From this patch we start to restruct the functions which set PCDs into
two, one for PlatformInitLib, one for PlatformPei.

AddressWidthInitialization is the first one. It is splitted into two:
 - PlatformAddressWidthInitialization is for PlatformInitLib
 - AddressWidthInitialization is for PlatformPei. It calls
   PlatformAddressWidthInitialization then set PCDs.

Below functions are also refined for PlatformInitLib:
 - PlatformScanOrAdd64BitE820Ram
 - PlatformGetSystemMemorySizeAbove4gb
 - PlatformGetFirstNonAddress

All the SetPcd codes are removed from above functions.

Cc: Ard Biesheuvel 
Cc: Jordan Justen 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Cc: Sebastien Boeuf 
Signed-off-by: Min Xu 
---
 OvmfPkg/PlatformPei/MemDetect.c | 117 
 OvmfPkg/PlatformPei/Platform.c  |   6 +-
 2 files changed, 78 insertions(+), 45 deletions(-)

diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c
index f3819b997b3b..5507d9585bab 100644
--- a/OvmfPkg/PlatformPei/MemDetect.c
+++ b/OvmfPkg/PlatformPei/MemDetect.c
@@ -189,7 +189,7 @@ QemuUc32BaseInitialization (
   Find the highest exclusive >=4GB RAM address, or produce memory resource
   descriptor HOBs for RAM entries that start at or above 4GB.
 
-  @param[out] MaxAddress  If MaxAddress is NULL, then ScanOrAdd64BitE820Ram()
+  @param[out] MaxAddress  If MaxAddress is NULL, then 
PlatformScanOrAdd64BitE820Ram()
   produces memory resource descriptor HOBs for RAM
   entries that start at or above 4GB.
 
@@ -210,7 +210,7 @@ QemuUc32BaseInitialization (
 **/
 STATIC
 EFI_STATUS
-ScanOrAdd64BitE820Ram (
+PlatformScanOrAdd64BitE820Ram (
   IN BOOLEAN  AddHighHob,
   OUT UINT64  *LowMemory OPTIONAL,
   OUT UINT64  *MaxAddress OPTIONAL
@@ -385,7 +385,7 @@ GetSystemMemorySizeBelow4gb (
 return (UINT32)GetHighestSystemMemoryAddressFromPvhMemmap (TRUE);
   }
 
-  Status = ScanOrAdd64BitE820Ram (FALSE, , NULL);
+  Status = PlatformScanOrAdd64BitE820Ram (FALSE, , NULL);
   if ((Status == EFI_SUCCESS) && (LowerMemorySize > 0)) {
 return (UINT32)LowerMemorySize;
   }
@@ -407,7 +407,7 @@ GetSystemMemorySizeBelow4gb (
 
 STATIC
 UINT64
-GetSystemMemorySizeAbove4gb (
+PlatformGetSystemMemorySizeAbove4gb (
   )
 {
   UINT32  Size;
@@ -434,7 +434,7 @@ GetSystemMemorySizeAbove4gb (
 **/
 STATIC
 UINT64
-GetFirstNonAddress (
+PlatformGetFirstNonAddress (
   IN OUT  EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
   )
 {
@@ -444,7 +444,6 @@ GetFirstNonAddress (
   FIRMWARE_CONFIG_ITEM  FwCfgItem;
   UINTN FwCfgSize;
   UINT64HotPlugMemoryEnd;
-  RETURN_STATUS PcdStatus;
 
   //
   // set FirstNonAddress to suppress incorrect compiler/analyzer warnings
@@ -458,9 +457,9 @@ GetFirstNonAddress (
   // Otherwise, get the flat size of the memory above 4GB from the CMOS (which
   // can only express a size smaller than 1TB), and add it to 4GB.
   //
-  Status = ScanOrAdd64BitE820Ram (FALSE, NULL, );
+  Status = PlatformScanOrAdd64BitE820Ram (FALSE, NULL, );
   if (EFI_ERROR (Status)) {
-FirstNonAddress = BASE_4GB + GetSystemMemorySizeAbove4gb ();
+FirstNonAddress = BASE_4GB + PlatformGetSystemMemorySizeAbove4gb ();
   }
 
   //
@@ -475,12 +474,6 @@ GetFirstNonAddress (
 
  #endif
 
-  //
-  // Otherwise, in order to calculate the highest address plus one, we must
-  // consider the 64-bit PCI host aperture too. Fetch the default size.
-  //
-  PlatformInfoHob->PcdPciMmio64Size = PcdGet64 (PcdPciMmio64Size);
-
   //
   // See if the user specified the number of megabytes for the 64-bit PCI host
   // aperture. Accept an aperture size up to 16TB.
@@ -522,8 +515,6 @@ GetFirstNonAddress (
 "%a: disabling 64-bit PCI host aperture\n",
 __FUNCTION__
 ));
-  PcdStatus = PcdSet64S (PcdPciMmio64Size, 0);
-  ASSERT_RETURN_ERROR (PcdStatus);
 }
 
 //
@@ -574,26 +565,6 @@ GetFirstNonAddress (
   //
   PlatformInfoHob->PcdPciMmio64Base = ALIGN_VALUE 
(PlatformInfoHob->PcdPciMmio64Base, GetPowerOfTwo64 
(PlatformInfoHob->PcdPciMmio64Size));
 
-  if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) {
-//
-// The core PciHostBridgeDxe driver will automatically add this range to
-// the GCD memory space map through our PciHostBridgeLib instance; here we
-// only need to set the PCDs.
-//
-PcdStatus = PcdSet64S (PcdPciMmio64Base, 
PlatformInfoHob->PcdPciMmio64Base);
-ASSERT_RETURN_ERROR (PcdStatus);
-PcdStatus = PcdSet64S (PcdPciMmio64Size, 
PlatformInfoHob->PcdPciMmio64Size);
-ASSERT_RETURN_ERROR (PcdStatus);
-
-DEBUG ((
-  DEBUG_INFO,
-  "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",
-  __FUNCTION__,
-  PlatformInfoHob->PcdPciMmio64Base,
-  PlatformInfoHob->PcdPciMmio64Size
-  ));
-  }
-
   //
   // The useful address space ends with the 64-bit 

[edk2-devel] [PATCH V9 21/47] OvmfPkg/PlatformPei: Refactor MiscInitialization for CloudHV

[Min Xu]

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863

Refactor MiscInitialization for CloudHV to set PCD as other platforms
do. Because in the following patch we will split the functions which
set PCDs into two, one for PlatformInitLib, one for PlatformPei.

Cc: Ard Biesheuvel 
Cc: Jordan Justen 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Cc: Sebastien Boeuf 
Acked-by: Gerd Hoffmann 
Signed-off-by: Min Xu 
---
 OvmfPkg/PlatformPei/Platform.c | 13 ++---
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index af9e72cd7a98..3e0c56db57ed 100644
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -380,13 +380,7 @@ MiscInitialization (
   AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
   break;
 case CLOUDHV_DEVICE_ID:
-  DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor host bridge\n", __FUNCTION__));
-  PcdStatus = PcdSet16S (
-PcdOvmfHostBridgePciDevId,
-CLOUDHV_DEVICE_ID
-);
-  ASSERT_RETURN_ERROR (PcdStatus);
-  return;
+  break;
 default:
   DEBUG ((
 DEBUG_ERROR,
@@ -401,6 +395,11 @@ MiscInitialization (
   PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, 
PlatformInfoHob->HostBridgeDevId);
   ASSERT_RETURN_ERROR (PcdStatus);
 
+  if (PlatformInfoHob->HostBridgeDevId == CLOUDHV_DEVICE_ID) {
+DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor is done.\n", __FUNCTION__));
+return;
+  }
+
   //
   // If the appropriate IOspace enable bit is set, assume the ACPI PMBA has
   // been configured and skip the setup here. This matches the logic in
-- 
2.29.2.windows.2



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[edk2-devel] [PATCH V9 20/47] OvmfPkg/PlatformPei: Refactor MiscInitialization

[Min Xu]

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863

In MiscInitialization Microvm looks a little weird. Other platforms
call PcdSet16S to set the PcdOvmfHostBridgePciDevId with the value same
as PlatformInfoHob->HostBridgeDevId. But Microvm doesn't follow this
way. In switch-case 0x is Microvm, but set with
MICROVM_PSEUDO_DEVICE_ID. So we have to add a new function
( MiscInitializationForMicrovm ) for Microvm and delete the code in
MiscInitialization.

Cc: Ard Biesheuvel 
Cc: Jordan Justen 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Cc: Sebastien Boeuf 
Acked-by: Gerd Hoffmann 
Signed-off-by: Min Xu 
---
 OvmfPkg/PlatformPei/Platform.c | 46 ++
 1 file changed, 36 insertions(+), 10 deletions(-)

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 80eb4cc9adcd..af9e72cd7a98 100644
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -304,6 +304,36 @@ MicrovmInitialization (
   *FdtHobData = (UINTN)NewBase;
 }
 
+VOID
+MiscInitializationForMicrovm (
+  IN EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
+  )
+{
+  RETURN_STATUS  PcdStatus;
+
+  ASSERT (PlatformInfoHob->HostBridgeDevId == 0x);
+
+  DEBUG ((DEBUG_INFO, "%a: microvm\n", __FUNCTION__));
+  //
+  // Disable A20 Mask
+  //
+  IoOr8 (0x92, BIT1);
+
+  //
+  // Build the CPU HOB with guest RAM size dependent address width and 16-bits
+  // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
+  // S3 resume as well, so we build it unconditionally.)
+  //
+  BuildCpuHob (PlatformInfoHob->PhysMemAddressWidth, 16);
+
+  MicrovmInitialization ();
+  PcdStatus = PcdSet16S (
+PcdOvmfHostBridgePciDevId,
+MICROVM_PSEUDO_DEVICE_ID
+);
+  ASSERT_RETURN_ERROR (PcdStatus);
+}
+
 VOID
 MiscInitialization (
   IN EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
@@ -349,15 +379,6 @@ MiscInitialization (
   AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
   AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
   break;
-case 0x: /* microvm */
-  DEBUG ((DEBUG_INFO, "%a: microvm\n", __FUNCTION__));
-  MicrovmInitialization ();
-  PcdStatus = PcdSet16S (
-PcdOvmfHostBridgePciDevId,
-MICROVM_PSEUDO_DEVICE_ID
-);
-  ASSERT_RETURN_ERROR (PcdStatus);
-  return;
 case CLOUDHV_DEVICE_ID:
   DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor host bridge\n", __FUNCTION__));
   PcdStatus = PcdSet16S (
@@ -762,7 +783,12 @@ InitializePlatform (
 
   InstallClearCacheCallback ();
   AmdSevInitialize ();
-  MiscInitialization ();
+  if (mPlatformInfoHob.HostBridgeDevId == 0x) {
+MiscInitializationForMicrovm ();
+  } else {
+MiscInitialization ();
+  }
+
   InstallFeatureControlCallback ();
 
   return EFI_SUCCESS;
-- 
2.29.2.windows.2



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[edk2-devel] [PATCH V9 19/47] OvmfPkg/PlatformPei: Move global variables to PlatformInfoHob

[Min Xu]

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863

The intention of PlatformInitLib is to extract the common function used
in OvmfPkg/PlatformPei. This lib will be used not only in PEI phase but
also in SEC phase. SEC phase cannot use global variables between
different functions. So PlatformInfoHob is created to hold the
informations shared between functions. For example, HostBridgeDevId
corespond to mHostBridgeDevId in PlatformPei.

In this patch we will first move below global variables to
PlatformInfoHob.
 - mBootMode
 - mS3Supported
 - mPhysMemAddressWidth
 - mMaxCpuCount
 - mHostBridgeDevId
 - mQ35SmramAtDefaultSmbase
 - mQemuUc32Base
 - mS3AcpiReservedMemorySize
 - mS3AcpiReservedMemoryBase

PlatformInfoHob also holds other information, for example,
PciIoBase / PciIoSize. This is because in SEC phase, PcdSetxxx
doesn't work. So we will restruct the functions which set PCDs
into two, one for PlatformInfoLib, one for PlatformPei.

So in this patch we first move global variables and PCDs to
PlatformInfoHob. All the changes are in OvmfPkg/PlatformPei.

Cc: Ard Biesheuvel 
Cc: Jordan Justen 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Cc: Sebastien Boeuf 
Signed-off-by: Min Xu 
---
 OvmfPkg/PlatformPei/AmdSev.c  |   8 +-
 OvmfPkg/PlatformPei/Fv.c  |   4 +-
 OvmfPkg/PlatformPei/MemDetect.c   | 210 +++---
 OvmfPkg/PlatformPei/MemTypeInfo.c |   2 +-
 OvmfPkg/PlatformPei/Platform.c| 109 
 OvmfPkg/PlatformPei/Platform.h|  45 ---
 6 files changed, 196 insertions(+), 182 deletions(-)

diff --git a/OvmfPkg/PlatformPei/AmdSev.c b/OvmfPkg/PlatformPei/AmdSev.c
index fb7e21ec140f..385562b44c4e 100644
--- a/OvmfPkg/PlatformPei/AmdSev.c
+++ b/OvmfPkg/PlatformPei/AmdSev.c
@@ -228,7 +228,7 @@ AmdSevEsInitialize (
   //   Since the pages must survive across the UEFI to OS transition
   //   make them reserved.
   //
-  GhcbPageCount = mMaxCpuCount * 2;
+  GhcbPageCount = mPlatformInfoHob.PcdCpuMaxLogicalProcessorNumber * 2;
   GhcbBase  = AllocateReservedPages (GhcbPageCount);
   ASSERT (GhcbBase != NULL);
 
@@ -266,7 +266,7 @@ AmdSevEsInitialize (
   // Allocate #VC recursion backup pages. The number of backup pages needed is
   // one less than the maximum VC count.
   //
-  GhcbBackupPageCount = mMaxCpuCount * (VMGEXIT_MAXIMUM_VC_COUNT - 1);
+  GhcbBackupPageCount = mPlatformInfoHob.PcdCpuMaxLogicalProcessorNumber * 
(VMGEXIT_MAXIMUM_VC_COUNT - 1);
   GhcbBackupBase  = AllocatePages (GhcbBackupPageCount);
   ASSERT (GhcbBackupBase != NULL);
 
@@ -367,7 +367,7 @@ AmdSevInitialize (
   // until after re-encryption, in order to prevent an information leak to the
   // hypervisor.
   //
-  if (FeaturePcdGet (PcdSmmSmramRequire) && (mBootMode != BOOT_ON_S3_RESUME)) {
+  if (mPlatformInfoHob.SmmSmramRequire && (mPlatformInfoHob.BootMode != 
BOOT_ON_S3_RESUME)) {
 RETURN_STATUS  LocateMapStatus;
 UINTN  MapPagesBase;
 UINTN  MapPagesCount;
@@ -378,7 +378,7 @@ AmdSevInitialize (
 );
 ASSERT_RETURN_ERROR (LocateMapStatus);
 
-if (mQ35SmramAtDefaultSmbase) {
+if (mPlatformInfoHob.Q35SmramAtDefaultSmbase) {
   //
   // The initial SMRAM Save State Map has been covered as part of a larger
   // reserved memory allocation in InitializeRamRegions().
diff --git a/OvmfPkg/PlatformPei/Fv.c b/OvmfPkg/PlatformPei/Fv.c
index 8cd8cacc5913..e40c5922206b 100644
--- a/OvmfPkg/PlatformPei/Fv.c
+++ b/OvmfPkg/PlatformPei/Fv.c
@@ -37,7 +37,7 @@ PeiFvInitialization (
   BuildMemoryAllocationHob (
 PcdGet32 (PcdOvmfPeiMemFvBase),
 PcdGet32 (PcdOvmfPeiMemFvSize),
-mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData
+mPlatformInfoHob.S3Supported ? EfiACPIMemoryNVS : EfiBootServicesData
 );
 
   //
@@ -45,7 +45,7 @@ PeiFvInitialization (
   //
   BuildFvHob (PcdGet32 (PcdOvmfDxeMemFvBase), PcdGet32 (PcdOvmfDxeMemFvSize));
 
-  SecureS3Needed = mS3Supported && FeaturePcdGet (PcdSmmSmramRequire);
+  SecureS3Needed = mPlatformInfoHob.S3Supported && 
mPlatformInfoHob.SmmSmramRequire;
 
   //
   // Create a memory allocation HOB for the DXE FV.
diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c
index e5e105f377dd..f3819b997b3b 100644
--- a/OvmfPkg/PlatformPei/MemDetect.c
+++ b/OvmfPkg/PlatformPei/MemDetect.c
@@ -37,21 +37,9 @@ Module Name:
 #include 
 #include 
 #include 
-#include 
 
 #include "Platform.h"
 
-UINT8  mPhysMemAddressWidth;
-
-STATIC UINT32  mS3AcpiReservedMemoryBase;
-STATIC UINT32  mS3AcpiReservedMemorySize;
-
-STATIC UINT16  mQ35TsegMbytes;
-
-BOOLEAN  mQ35SmramAtDefaultSmbase;
-
-UINT32  mQemuUc32Base;
-
 VOID
 Q35TsegMbytesInitialization (
   VOID
@@ -60,7 +48,7 @@ Q35TsegMbytesInitialization (
   UINT16 ExtendedTsegMbytes;
   RETURN_STATUS  PcdStatus;
 
-  ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);
+  ASSERT (mPlatformInfoHob.HostBridgeDevId == 

[edk2-devel] [PATCH V9 18/47] OvmfPkg/PlatformInitLib: Add hob functions

[Min Xu]

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863

In this patch of PlatformInitLib, below hob functions are introduced:
 - PlatformAddIoMemoryBaseSizeHob
 - PlatformAddIoMemoryRangeHob
 - PlatformAddMemoryBaseSizeHob
 - PlatformAddMemoryRangeHob
 - PlatformAddReservedMemoryBaseSizeHob

They correspond the below functions in OvmfPkg/PlatformPei:
 - AddIoMemoryBaseSizeHob
 - AddIoMemoryRangeHob
 - AddMemoryBaseSizeHob
 - AddMemoryRangeHob
 - AddReservedMemoryBaseSizeHob

After above hob functions are introduced in PlatformInitLib,
OvmfPkg/PlatformPei is refactored with this library.

Cc: Ard Biesheuvel 
Cc: Jordan Justen 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Acked-by: Gerd Hoffmann 
Signed-off-by: Min Xu 
---
 OvmfPkg/Include/Library/PlatformInitLib.h |  36 ++
 OvmfPkg/Library/PlatformInitLib/Platform.c| 106 ++
 .../PlatformInitLib/PlatformInitLib.inf   |   2 +
 OvmfPkg/PlatformPei/MemDetect.c   |  20 ++--
 OvmfPkg/PlatformPei/Platform.c| 101 ++---
 OvmfPkg/PlatformPei/Platform.h|  31 -
 6 files changed, 165 insertions(+), 131 deletions(-)
 create mode 100644 OvmfPkg/Library/PlatformInitLib/Platform.c

diff --git a/OvmfPkg/Include/Library/PlatformInitLib.h 
b/OvmfPkg/Include/Library/PlatformInitLib.h
index 2ebac5ccb013..9b99d4c1f514 100644
--- a/OvmfPkg/Include/Library/PlatformInitLib.h
+++ b/OvmfPkg/Include/Library/PlatformInitLib.h
@@ -96,4 +96,40 @@ PlatformDebugDumpCmos (
   VOID
   );
 
+VOID
+EFIAPI
+PlatformAddIoMemoryBaseSizeHob (
+  IN EFI_PHYSICAL_ADDRESS  MemoryBase,
+  IN UINT64MemorySize
+  );
+
+VOID
+EFIAPI
+PlatformAddIoMemoryRangeHob (
+  IN EFI_PHYSICAL_ADDRESS  MemoryBase,
+  IN EFI_PHYSICAL_ADDRESS  MemoryLimit
+  );
+
+VOID
+EFIAPI
+PlatformAddMemoryBaseSizeHob (
+  IN EFI_PHYSICAL_ADDRESS  MemoryBase,
+  IN UINT64MemorySize
+  );
+
+VOID
+EFIAPI
+PlatformAddMemoryRangeHob (
+  IN EFI_PHYSICAL_ADDRESS  MemoryBase,
+  IN EFI_PHYSICAL_ADDRESS  MemoryLimit
+  );
+
+VOID
+EFIAPI
+PlatformAddReservedMemoryBaseSizeHob (
+  IN EFI_PHYSICAL_ADDRESS  MemoryBase,
+  IN UINT64MemorySize,
+  IN BOOLEAN   Cacheable
+  );
+
 #endif // PLATFORM_INIT_LIB_H_
diff --git a/OvmfPkg/Library/PlatformInitLib/Platform.c 
b/OvmfPkg/Library/PlatformInitLib/Platform.c
new file mode 100644
index ..e41f230ff563
--- /dev/null
+++ b/OvmfPkg/Library/PlatformInitLib/Platform.c
@@ -0,0 +1,106 @@
+/**@file
+
+  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+  Copyright (c) 2011, Andrei Warkentin 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include 
+
+//
+// The Library classes this module consumes
+//
+#include 
+#include 
+#include 
+#include 
+#include 
+
+VOID
+EFIAPI
+PlatformAddIoMemoryBaseSizeHob (
+  IN EFI_PHYSICAL_ADDRESS  MemoryBase,
+  IN UINT64MemorySize
+  )
+{
+  BuildResourceDescriptorHob (
+EFI_RESOURCE_MEMORY_MAPPED_IO,
+EFI_RESOURCE_ATTRIBUTE_PRESENT |
+EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+EFI_RESOURCE_ATTRIBUTE_TESTED,
+MemoryBase,
+MemorySize
+);
+}
+
+VOID
+EFIAPI
+PlatformAddReservedMemoryBaseSizeHob (
+  IN EFI_PHYSICAL_ADDRESS  MemoryBase,
+  IN UINT64MemorySize,
+  IN BOOLEAN   Cacheable
+  )
+{
+  BuildResourceDescriptorHob (
+EFI_RESOURCE_MEMORY_RESERVED,
+EFI_RESOURCE_ATTRIBUTE_PRESENT |
+EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+(Cacheable ?
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
+ 0
+) |
+EFI_RESOURCE_ATTRIBUTE_TESTED,
+MemoryBase,
+MemorySize
+);
+}
+
+VOID
+EFIAPI
+PlatformAddIoMemoryRangeHob (
+  IN EFI_PHYSICAL_ADDRESS  MemoryBase,
+  IN EFI_PHYSICAL_ADDRESS  MemoryLimit
+  )
+{
+  PlatformAddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - 
MemoryBase));
+}
+
+VOID
+EFIAPI
+PlatformAddMemoryBaseSizeHob (
+  IN EFI_PHYSICAL_ADDRESS  MemoryBase,
+  IN UINT64MemorySize
+  )
+{
+  BuildResourceDescriptorHob (
+EFI_RESOURCE_SYSTEM_MEMORY,
+EFI_RESOURCE_ATTRIBUTE_PRESENT |
+EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+EFI_RESOURCE_ATTRIBUTE_TESTED,
+MemoryBase,
+MemorySize
+);
+}
+
+VOID
+EFIAPI
+PlatformAddMemoryRangeHob (
+  IN EFI_PHYSICAL_ADDRESS  MemoryBase,
+  IN EFI_PHYSICAL_ADDRESS  MemoryLimit
+  )
+{
+  PlatformAddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - 
MemoryBase));
+}
diff --git 

[edk2-devel] [PATCH V9 17/47] OvmfPkg: Create initial version of PlatformInitLib

[Min Xu]

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863

There are 3 variants of PlatformPei in OvmfPkg:
 - OvmfPkg/PlatformPei
 - OvmfPkg/XenPlatformPei
 - OvmfPkg/Bhyve/PlatformPei/PlatformPei.inf
These PlatformPeis can share many common codes, such as
Cmos / Hob / Memory / Platform related functions. This commit
(and its following several patches) are to create a PlatformInitLib
which wraps the common code called in above PlatformPeis.

In this initial version of PlatformInitLib, below Cmos related functions
are introduced:
 - PlatformCmosRead8
 - PlatformCmosWrite8
 - PlatformDebugDumpCmos

They correspond to the functions in OvmfPkg/PlatformPei:
 - CmosRead8
 - CmosWrite8
 - DebugDumpCmos

Considering this PlatformInitLib will be used in SEC phase, global
variables and dynamic PCDs are avoided. We use PlatformInfoHob
to exchange information between functions.

EFI_HOB_PLATFORM_INFO is the data struct which contains the platform
information, such as HostBridgeDevId, BootMode, S3Supported,
SmmSmramRequire, etc.

After PlatformInitLib is created, OvmfPkg/PlatformPei is refactored
with this library.

Cc: Ard Biesheuvel 
Cc: Jordan Justen 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Acked-by: Gerd Hoffmann 
Signed-off-by: Min Xu 
---
 OvmfPkg/AmdSev/AmdSevX64.dsc  |  1 +
 OvmfPkg/CloudHv/CloudHvX64.dsc|  1 +
 OvmfPkg/Include/Library/PlatformInitLib.h | 99 +++
 .../PlatformInitLib}/Cmos.c   | 32 +-
 .../PlatformInitLib/PlatformInitLib.inf   | 36 +++
 OvmfPkg/Microvm/MicrovmX64.dsc|  1 +
 OvmfPkg/OvmfPkg.dec   |  4 +
 OvmfPkg/OvmfPkgIa32.dsc   |  1 +
 OvmfPkg/OvmfPkgIa32X64.dsc|  1 +
 OvmfPkg/OvmfPkgX64.dsc|  1 +
 OvmfPkg/PlatformPei/Cmos.h| 48 -
 OvmfPkg/PlatformPei/MemDetect.c   |  8 +-
 OvmfPkg/PlatformPei/Platform.c| 29 +-
 OvmfPkg/PlatformPei/PlatformPei.inf   |  3 +-
 14 files changed, 183 insertions(+), 82 deletions(-)
 create mode 100644 OvmfPkg/Include/Library/PlatformInitLib.h
 rename OvmfPkg/{PlatformPei => Library/PlatformInitLib}/Cmos.c (61%)
 create mode 100644 OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf
 delete mode 100644 OvmfPkg/PlatformPei/Cmos.h

diff --git a/OvmfPkg/AmdSev/AmdSevX64.dsc b/OvmfPkg/AmdSev/AmdSevX64.dsc
index fd56176796d5..785049c88962 100644
--- a/OvmfPkg/AmdSev/AmdSevX64.dsc
+++ b/OvmfPkg/AmdSev/AmdSevX64.dsc
@@ -280,6 +280,7 @@
 !include OvmfPkg/OvmfTpmLibsPeim.dsc.inc
 
   MemEncryptSevLib|OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLib.inf
+  PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf
 
 [LibraryClasses.common.DXE_CORE]
   HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc
index b4d855d80f56..b8a82380202c 100644
--- a/OvmfPkg/CloudHv/CloudHvX64.dsc
+++ b/OvmfPkg/CloudHv/CloudHvX64.dsc
@@ -307,6 +307,7 @@
 !include OvmfPkg/OvmfTpmLibsPeim.dsc.inc
 
   MemEncryptSevLib|OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLib.inf
+  PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf
 
 [LibraryClasses.common.DXE_CORE]
   HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
diff --git a/OvmfPkg/Include/Library/PlatformInitLib.h 
b/OvmfPkg/Include/Library/PlatformInitLib.h
new file mode 100644
index ..2ebac5ccb013
--- /dev/null
+++ b/OvmfPkg/Include/Library/PlatformInitLib.h
@@ -0,0 +1,99 @@
+/** @file
+  PlatformInitLib header file.
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef PLATFORM_INIT_LIB_H_
+#define PLATFORM_INIT_LIB_H_
+
+#include 
+
+#pragma pack(1)
+typedef struct {
+  EFI_HOB_GUID_TYPEGuidHeader;
+  UINT16   HostBridgeDevId;
+
+  UINT64   PcdConfidentialComputingGuestAttr;
+  BOOLEAN  SevEsIsEnabled;
+
+  UINT32   BootMode;
+  BOOLEAN  S3Supported;
+
+  BOOLEAN  SmmSmramRequire;
+  BOOLEAN  Q35SmramAtDefaultSmbase;
+  UINT16   Q35TsegMbytes;
+
+  UINT64   FirstNonAddress;
+  UINT8PhysMemAddressWidth;
+  UINT32   Uc32Base;
+  UINT32   Uc32Size;
+
+  BOOLEAN  PcdSetNxForStack;
+  UINT64   PcdTdxSharedBitMask;
+
+  UINT64   PcdPciMmio64Base;
+  UINT64   PcdPciMmio64Size;
+  UINT32   PcdPciMmio32Base;
+  UINT32   PcdPciMmio32Size;
+  UINT64   PcdPciIoBase;
+  UINT64   PcdPciIoSize;
+
+  UINT64   PcdEmuVariableNvStoreReserved;
+  UINT32   PcdCpuBootLogicalProcessorNumber;
+  UINT32   PcdCpuMaxLogicalProcessorNumber;
+  UINT32   

[edk2-devel] [PATCH V9 16/47] OvmfPkg: Add TdxMailboxLib

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429

In Tdx BSP may issues commands to APs for some task, for example, to
accept pages paralelly. BSP also need to wait until all the APs have
done the task. TdxMailboxLib wraps these common funtions for BSP.

Cc: Ard Biesheuvel 
Cc: Jordan Justen 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Acked-by: Gerd Hoffmann 
Signed-off-by: Min Xu 
---
 OvmfPkg/Include/Library/TdxMailboxLib.h   |  76 ++
 OvmfPkg/Library/TdxMailboxLib/TdxMailbox.c| 141 ++
 .../Library/TdxMailboxLib/TdxMailboxLib.inf   |  52 +++
 .../Library/TdxMailboxLib/TdxMailboxNull.c|  85 +++
 OvmfPkg/OvmfPkg.dec   |   4 +
 5 files changed, 358 insertions(+)
 create mode 100644 OvmfPkg/Include/Library/TdxMailboxLib.h
 create mode 100644 OvmfPkg/Library/TdxMailboxLib/TdxMailbox.c
 create mode 100644 OvmfPkg/Library/TdxMailboxLib/TdxMailboxLib.inf
 create mode 100644 OvmfPkg/Library/TdxMailboxLib/TdxMailboxNull.c

diff --git a/OvmfPkg/Include/Library/TdxMailboxLib.h 
b/OvmfPkg/Include/Library/TdxMailboxLib.h
new file mode 100644
index ..166cab43bc02
--- /dev/null
+++ b/OvmfPkg/Include/Library/TdxMailboxLib.h
@@ -0,0 +1,76 @@
+/** @file
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef TDX_MAILBOX_LIB_H_
+#define TDX_MAILBOX_LIB_H_
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  This function will be called by BSP to get the CPU number.
+
+  @retval   CPU number
+**/
+UINT32
+EFIAPI
+GetCpusNum (
+  VOID
+  );
+
+/**
+  Get the address of Td mailbox.
+**/
+volatile VOID *
+EFIAPI
+GetTdxMailBox (
+  VOID
+  );
+
+/**
+  This function will be called by BSP to wakeup APs the are spinning on mailbox
+  in protected mode
+
+  @param[in] Command  Command to send APs
+  @param[in] WakeupVector If used, address for APs to start executing
+  @param[in] WakeArgsXArgs to pass to APs for excuting commands
+**/
+VOID
+EFIAPI
+MpSendWakeupCommand (
+  IN UINT16  Command,
+  IN UINT64  WakeupVector,
+  IN UINT64  WakeupArgs1,
+  IN UINT64  WakeupArgs2,
+  IN UINT64  WakeupArgs3,
+  IN UINT64  WakeupArgs4
+  );
+
+/**
+  BSP wait until all the APs arriving. It means the task triggered by BSP is 
started.
+**/
+VOID
+EFIAPI
+MpSerializeStart (
+  VOID
+  );
+
+/**
+  BSP wait until all the APs arriving. It means the task triggered by BSP is 
ended.
+**/
+VOID
+EFIAPI
+MpSerializeEnd (
+  VOID
+  );
+
+#endif
diff --git a/OvmfPkg/Library/TdxMailboxLib/TdxMailbox.c 
b/OvmfPkg/Library/TdxMailboxLib/TdxMailbox.c
new file mode 100644
index ..74cb55611fe3
--- /dev/null
+++ b/OvmfPkg/Library/TdxMailboxLib/TdxMailbox.c
@@ -0,0 +1,141 @@
+/** @file
+
+  Copyright (c) 2008, Intel Corporation. All rights reserved.
+  (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+volatile VOID  *mMailBox  = NULL;
+UINT32 mNumOfCpus = 0;
+
+/**
+  This function will be called by BSP to get the CPU number.
+
+  @retval   CPU number
+**/
+UINT32
+EFIAPI
+GetCpusNum (
+  VOID
+  )
+{
+  if (mNumOfCpus == 0) {
+mNumOfCpus = TdVCpuNum ();
+  }
+
+  return mNumOfCpus;
+}
+
+/**
+  Get the address of Td mailbox.
+**/
+volatile VOID *
+EFIAPI
+GetTdxMailBox (
+  VOID
+  )
+{
+  if (mMailBox == NULL) {
+mMailBox = (VOID *)(UINTN)PcdGet32 (PcdOvmfSecGhcbBackupBase);
+  }
+
+  return mMailBox;
+}
+
+/**
+  This function will be called by BSP to wakeup APs the are spinning on mailbox
+  in protected mode
+
+  @param[in] Command  Command to send APs
+  @param[in] WakeupVector If used, address for APs to start executing
+  @param[in] WakeArgsXArgs to pass to APs for excuting commands
+**/
+VOID
+EFIAPI
+MpSendWakeupCommand (
+  IN UINT16  Command,
+  IN UINT64  WakeupVector,
+  IN UINT64  WakeupArgs1,
+  IN UINT64  WakeupArgs2,
+  IN UINT64  WakeupArgs3,
+  IN UINT64  WakeupArgs4
+  )
+{
+  volatile MP_WAKEUP_MAILBOX  *MailBox;
+
+  MailBox   = (volatile MP_WAKEUP_MAILBOX *)GetTdxMailBox ();
+  MailBox->ApicId   = MP_CPU_PROTECTED_MODE_MAILBOX_APICID_INVALID;
+  MailBox->WakeUpVector = 0;
+  MailBox->Command  = MpProtectedModeWakeupCommandNoop;
+  MailBox->ApicId   = MP_CPU_PROTECTED_MODE_MAILBOX_APICID_BROADCAST;
+  MailBox->WakeUpVector = WakeupVector;
+  MailBox->WakeUpArgs1  = WakeupArgs1;
+  MailBox->WakeUpArgs2  = WakeupArgs2;
+  MailBox->WakeUpArgs3  = WakeupArgs3;
+  MailBox->WakeUpArgs4  = WakeupArgs4;
+  AsmCpuid (0x01, NULL, NULL, NULL, NULL);
+  MailBox->Command = Command;
+  AsmCpuid (0x01, NULL, NULL, NULL, NULL);
+  return;
+}
+
+/**
+  BSP wait until all the APs arriving. It means the task triggered by BSP 

[edk2-devel] [PATCH V9 15/47] OvmfPkg: Add IntelTdx.h in OvmfPkg/Include/IndustryStandard

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429

IntelTdx.h defines the defition used by TDX in OvmfPkg:
 - Mailbox related defitions,such as the data structure, command code,
   AP relocation defitions.

See Table 5.44 Multiprocessor Wakeup Mailbox Structure in below link.
https://uefi.org/specs/ACPI/6.4/05_ACPI_Software_Programming_Model/
ACPI_Software_Programming_Model.html#multiprocessor-wakeup-structure

Cc: Ard Biesheuvel 
Cc: Jordan Justen 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Acked-by: Gerd Hoffmann 
Signed-off-by: Min Xu 
---
 OvmfPkg/Include/IndustryStandard/IntelTdx.h | 67 +
 1 file changed, 67 insertions(+)
 create mode 100644 OvmfPkg/Include/IndustryStandard/IntelTdx.h

diff --git a/OvmfPkg/Include/IndustryStandard/IntelTdx.h 
b/OvmfPkg/Include/IndustryStandard/IntelTdx.h
new file mode 100644
index ..cc849be2fb59
--- /dev/null
+++ b/OvmfPkg/Include/IndustryStandard/IntelTdx.h
@@ -0,0 +1,67 @@
+/** @file
+  Defines the defitions used by TDX in OvmfPkg.
+
+  Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef OVMF_INTEL_TDX_H_
+#define OVMF_INTEL_TDX_H_
+
+#include 
+#include 
+#include 
+#include 
+
+#define MP_CPU_PROTECTED_MODE_MAILBOX_APICID_INVALID0x
+#define MP_CPU_PROTECTED_MODE_MAILBOX_APICID_BROADCAST  0xFFFE
+
+typedef enum {
+  MpProtectedModeWakeupCommandNoop= 0,
+  MpProtectedModeWakeupCommandWakeup  = 1,
+  MpProtectedModeWakeupCommandSleep   = 2,
+  MpProtectedModeWakeupCommandAcceptPages = 3,
+} MP_CPU_PROTECTED_MODE_WAKEUP_CMD;
+
+#pragma pack(1)
+
+//
+// Describes the CPU MAILBOX control structure use to
+// wakeup cpus spinning in long mode
+//
+typedef struct {
+  UINT16Command;
+  UINT16Resv;
+  UINT32ApicId;
+  UINT64WakeUpVector;
+  UINT8 ResvForOs[2032];
+  //
+  // Arguments available for wakeup code
+  //
+  UINT64WakeUpArgs1;
+  UINT64WakeUpArgs2;
+  UINT64WakeUpArgs3;
+  UINT64WakeUpArgs4;
+  UINT8 Pad1[0xe0];
+  UINT64NumCpusArriving;
+  UINT8 Pad2[0xf8];
+  UINT64NumCpusExiting;
+  UINT32Tallies[256];
+  UINT8 Errors[256];
+  UINT8 Pad3[0xf8];
+} MP_WAKEUP_MAILBOX;
+
+//
+// AP relocation code information including code address and size,
+// this structure will be shared be C code and assembly code.
+// It is natural aligned by design.
+//
+typedef struct {
+  UINT8*RelocateApLoopFuncAddress;
+  UINTNRelocateApLoopFuncSize;
+} MP_RELOCATION_MAP;
+
+#pragma pack()
+
+#endif
-- 
2.29.2.windows.2



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[edk2-devel] [PATCH V9 14/47] UefiCpuPkg: Enable Tdx support in MpInitLib

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429

In TDVF BSP and APs are simplified. BSP is the vCPU-0, while the others
are treated as APs.

So MP intialization is rather simple. The processor info is retrieved by
TDCALL, ApWorker is not supported, BSP is always the working processor,
while the APs are just in a wait-for-precedure state.

Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Acked-by: Gerd Hoffmann 
Signed-off-by: Min Xu 
---
 UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf |   3 +
 UefiCpuPkg/Library/MpInitLib/DxeMpLib.c   |  15 +-
 UefiCpuPkg/Library/MpInitLib/MpIntelTdx.h |  71 ++
 UefiCpuPkg/Library/MpInitLib/MpLib.c  |  27 
 UefiCpuPkg/Library/MpInitLib/MpLibTdx.c   | 128 ++
 UefiCpuPkg/Library/MpInitLib/MpLibTdxNull.c   |  73 ++
 UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf |   3 +
 7 files changed, 319 insertions(+), 1 deletion(-)
 create mode 100644 UefiCpuPkg/Library/MpInitLib/MpIntelTdx.h
 create mode 100644 UefiCpuPkg/Library/MpInitLib/MpLibTdx.c
 create mode 100644 UefiCpuPkg/Library/MpInitLib/MpLibTdxNull.c

diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf 
b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
index e1cd0b350008..159b4d16ed0e 100644
--- a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
+++ b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
@@ -24,10 +24,12 @@
 [Sources.IA32]
   Ia32/AmdSev.c
   Ia32/MpFuncs.nasm
+  MpLibTdxNull.c
 
 [Sources.X64]
   X64/AmdSev.c
   X64/MpFuncs.nasm
+  MpLibTdx.c
 
 [Sources.common]
   AmdSev.c
@@ -36,6 +38,7 @@
   MpLib.c
   MpLib.h
   Microcode.c
+  MpIntelTdx.h
 
 [Packages]
   MdePkg/MdePkg.dec
diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c 
b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
index 60d14a5a0e10..237cad8c5fd6 100644
--- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
@@ -7,6 +7,7 @@
 **/
 
 #include "MpLib.h"
+#include "MpIntelTdx.h"
 
 #include 
 #include 
@@ -15,8 +16,8 @@
 #include 
 #include 
 #include 
-
 #include 
+#include 
 
 #define  AP_SAFE_STACK_SIZE  128
 
@@ -824,6 +825,10 @@ MpInitLibStartupThisAP (
 {
   EFI_STATUS  Status;
 
+  if (CC_GUEST_IS_TDX (PcdGet64 (PcdConfidentialComputingGuestAttr))) {
+return EFI_UNSUPPORTED;
+  }
+
   //
   // temporarily stop checkAllApsStatus for avoid resource dead-lock.
   //
@@ -880,6 +885,10 @@ MpInitLibSwitchBSP (
   EFI_TIMER_ARCH_PROTOCOL  *Timer;
   UINT64   TimerPeriod;
 
+  if (CC_GUEST_IS_TDX (PcdGet64 (PcdConfidentialComputingGuestAttr))) {
+return EFI_UNSUPPORTED;
+  }
+
   TimerPeriod = 0;
   //
   // Locate Timer Arch Protocol
@@ -953,6 +962,10 @@ MpInitLibEnableDisableAP (
   EFI_STATUS  Status;
   BOOLEAN TempStopCheckState;
 
+  if (CC_GUEST_IS_TDX (PcdGet64 (PcdConfidentialComputingGuestAttr))) {
+return EFI_UNSUPPORTED;
+  }
+
   TempStopCheckState = FALSE;
   //
   // temporarily stop checkAllAPsStatus for initialize parameters.
diff --git a/UefiCpuPkg/Library/MpInitLib/MpIntelTdx.h 
b/UefiCpuPkg/Library/MpInitLib/MpIntelTdx.h
new file mode 100644
index ..b2136f466ce6
--- /dev/null
+++ b/UefiCpuPkg/Library/MpInitLib/MpIntelTdx.h
@@ -0,0 +1,71 @@
+/** @file
+  Intel Tdx header file.
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef MP_INTEL_TDX_H_
+#define MP_INTEL_TDX_H_
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Gets detailed MP-related information on the requested processor at the
+  instant this call is made. This service may only be called from the BSP.
+
+  @param[in]  ProcessorNumber   The handle number of processor.
+  @param[out] ProcessorInfoBuffer   A pointer to the buffer where information 
for
+the requested processor is deposited.
+  @param[out]  HealthDataReturn processor health data.
+
+  @retval EFI_SUCCESS Processor information was returned.
+  @retval EFI_DEVICE_ERRORThe calling processor is an AP.
+  @retval EFI_INVALID_PARAMETER   ProcessorInfoBuffer is NULL.
+  @retval EFI_NOT_FOUND   The processor with the handle specified by
+  ProcessorNumber does not exist in the 
platform.
+  @retval EFI_NOT_READY   MP Initialize Library is not initialized.
+
+**/
+EFI_STATUS
+EFIAPI
+TdxMpInitLibGetProcessorInfo (
+  IN  UINTN  ProcessorNumber,
+  OUT EFI_PROCESSOR_INFORMATION  *ProcessorInfoBuffer,
+  OUT EFI_HEALTH_FLAGS   *HealthData  OPTIONAL
+  );
+
+/**
+  Retrieves the number of logical processor in the platform and the number of
+  those logical processors that are enabled on this boot. This service may only
+  be called from the BSP.
+
+  @param[out] NumberOfProcessors  Pointer to the total number of 
logical
+  

[edk2-devel] [PATCH V9 13/47] MdePkg: Add macro to check SEV / TDX guest

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429

Add macros CC_GUEST_IS_SEV / CC_GUEST_IS_TDX to check SEV / TDX guest.

Cc: Michael Roth 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Eric Dong 
Cc: James Bottomley 
Cc: Min Xu 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Jordan Justen 
Cc: Ard Biesheuvel 
Cc: Erdem Aktas 
Cc: Gerd Hoffmann 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Acked-by: Gerd Hoffmann 
Signed-off-by: Min Xu 
---
 MdePkg/Include/ConfidentialComputingGuestAttr.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/MdePkg/Include/ConfidentialComputingGuestAttr.h 
b/MdePkg/Include/ConfidentialComputingGuestAttr.h
index 6a1301801519..dd2541c6dcdf 100644
--- a/MdePkg/Include/ConfidentialComputingGuestAttr.h
+++ b/MdePkg/Include/ConfidentialComputingGuestAttr.h
@@ -22,4 +22,7 @@ typedef enum {
   CCAttrIntelTdx = 0x200,
 } CONFIDENTIAL_COMPUTING_GUEST_ATTR;
 
+#define CC_GUEST_IS_TDX(x)  ((x) == CCAttrIntelTdx)
+#define CC_GUEST_IS_SEV(x)  ((x) == CCAttrAmdSev || (x) == CCAttrAmdSevEs || 
(x) == CCAttrAmdSevSnp)
+
 #endif
-- 
2.29.2.windows.2



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[edk2-devel] [PATCH V9 12/47] UefiCpuPkg: Support TDX in BaseXApicX2ApicLib

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429

MSR is accessed in BaseXApicX2ApicLib. In TDX some MSRs are accessed
directly from/to CPU. Some should be accessed via explicit requests
from the host VMM using TDCALL(TDG.VP.VMCALL). This is done by the
help of TdxLib.

Please refer to [TDX] Section 18.1
TDX: https://software.intel.com/content/dam/develop/external/us/en/
documents/tdx-module-1.0-public-spec-v0.931.pdf

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Acked-by: Gerd Hoffmann 
Reviewed-by: Ray Ni 
Signed-off-by: Min Xu 
---
 .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c   | 160 +-
 1 file changed, 152 insertions(+), 8 deletions(-)

diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c 
b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
index aaa42ff8450b..2d17177df12b 100644
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -23,11 +23,155 @@
 #include 
 #include 
 #include 
+#include 
 
 //
 // Library internal functions
 //
 
+/**
+  Some MSRs in TDX are accessed via TdCall.
+  Some are directly read/write from/to CPU.
+
+  @param  MsrIndex  Index of the MSR
+  @retval TRUE  MSR accessed via TdCall.
+  @retval FALSE MSR accessed not via TdCall.
+
+**/
+BOOLEAN
+AccessMsrTdxCall (
+  IN UINT32  MsrIndex
+  )
+{
+  if (!TdIsEnabled ()) {
+return FALSE;
+  }
+
+  switch (MsrIndex) {
+case MSR_IA32_X2APIC_TPR:
+case MSR_IA32_X2APIC_PPR:
+case MSR_IA32_X2APIC_EOI:
+case MSR_IA32_X2APIC_ISR0:
+case MSR_IA32_X2APIC_ISR1:
+case MSR_IA32_X2APIC_ISR2:
+case MSR_IA32_X2APIC_ISR3:
+case MSR_IA32_X2APIC_ISR4:
+case MSR_IA32_X2APIC_ISR5:
+case MSR_IA32_X2APIC_ISR6:
+case MSR_IA32_X2APIC_ISR7:
+case MSR_IA32_X2APIC_TMR0:
+case MSR_IA32_X2APIC_TMR1:
+case MSR_IA32_X2APIC_TMR2:
+case MSR_IA32_X2APIC_TMR3:
+case MSR_IA32_X2APIC_TMR4:
+case MSR_IA32_X2APIC_TMR5:
+case MSR_IA32_X2APIC_TMR6:
+case MSR_IA32_X2APIC_TMR7:
+case MSR_IA32_X2APIC_IRR0:
+case MSR_IA32_X2APIC_IRR1:
+case MSR_IA32_X2APIC_IRR2:
+case MSR_IA32_X2APIC_IRR3:
+case MSR_IA32_X2APIC_IRR4:
+case MSR_IA32_X2APIC_IRR5:
+case MSR_IA32_X2APIC_IRR6:
+case MSR_IA32_X2APIC_IRR7:
+  return FALSE;
+default:
+  break;
+  }
+
+  return TRUE;
+}
+
+/**
+  Read MSR value.
+
+  @param  MsrIndex  Index of the MSR to read
+  @retval 64-bitValue of MSR.
+
+**/
+UINT64
+LocalApicReadMsrReg64 (
+  IN UINT32  MsrIndex
+  )
+{
+  UINT64  Val;
+  UINT64  Status;
+
+  if (AccessMsrTdxCall (MsrIndex)) {
+Status = TdVmCall (TDVMCALL_RDMSR, (UINT64)MsrIndex, 0, 0, 0, );
+if (Status != 0) {
+  TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0);
+}
+  } else {
+Val = AsmReadMsr64 (MsrIndex);
+  }
+
+  return Val;
+}
+
+/**
+  Write to MSR.
+
+  @param  MsrIndex  Index of the MSR to write to
+  @param  Value Value to be written to the MSR
+
+  @return Value
+
+**/
+UINT64
+LocalApicWriteMsrReg64 (
+  IN UINT32  MsrIndex,
+  IN UINT64  Value
+  )
+{
+  UINT64  Status;
+
+  if (AccessMsrTdxCall (MsrIndex)) {
+Status = TdVmCall (TDVMCALL_WRMSR, (UINT64)MsrIndex, Value, 0, 0, 0);
+if (Status != 0) {
+  TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0);
+}
+  } else {
+AsmWriteMsr64 (MsrIndex, Value);
+  }
+
+  return Value;
+}
+
+/**
+  Read MSR value.
+
+  @param  MsrIndex  Index of the MSR to read
+  @retval 32-bitValue of MSR.
+
+**/
+UINT32
+LocalApicReadMsrReg32 (
+  IN UINT32  MsrIndex
+  )
+{
+  return (UINT32)LocalApicReadMsrReg64 (MsrIndex);
+}
+
+/**
+  Write to MSR.
+
+  @param  MsrIndex  Index of the MSR to write to
+  @param  Value Value to be written to the MSR
+
+  @return Value
+
+**/
+UINT32
+LocalApicWriteMsrReg32 (
+  IN UINT32  MsrIndex,
+  IN UINT32  Value
+  )
+{
+  return (UINT32)LocalApicWriteMsrReg64 (MsrIndex, Value);
+}
+
 /**
   Determine if the CPU supports the Local APIC Base Address MSR.
 
@@ -78,7 +222,7 @@ GetLocalApicBaseAddress (
 return PcdGet32 (PcdCpuLocalApicBaseAddress);
   }
 
-  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
+  ApicBaseMsr.Uint64 = LocalApicReadMsrReg64 (MSR_IA32_APIC_BASE);
 
   return (UINTN)(LShiftU64 ((UINT64)ApicBaseMsr.Bits.ApicBaseHi, 32)) +
  (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
@@ -109,12 +253,12 @@ SetLocalApicBaseAddress (
 return;
   }
 
-  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
+  ApicBaseMsr.Uint64 = LocalApicReadMsrReg64 (MSR_IA32_APIC_BASE);
 
   ApicBaseMsr.Bits.ApicBase   = (UINT32)(BaseAddress >> 12);
   ApicBaseMsr.Bits.ApicBaseHi = (UINT32)(RShiftU64 ((UINT64)BaseAddress, 32));
 
-  AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
+  LocalApicWriteMsrReg64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
 }
 
 /**
@@ -154,7 +298,7 @@ ReadLocalApicReg (

[edk2-devel] [PATCH V9 11/47] MdePkg: Support IoRead/IoWrite for Tdx guest in BaseIoLibIntrinsic

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429

This commit supports IoRead/IoWrite for SEV/TDX/Legacy guest in one
binary. It checks the guest type in runtime and then call corresponding
functions.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Acked-by: Gerd Hoffmann 
Reviewed-by: Liming Gao 
Signed-off-by: Min Xu 
---
 MdePkg/Library/BaseIoLibIntrinsic/IoLibGcc.c | 51 --
 MdePkg/Library/BaseIoLibIntrinsic/IoLibMsc.c | 73 +++-
 2 files changed, 99 insertions(+), 25 deletions(-)

diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibGcc.c 
b/MdePkg/Library/BaseIoLibIntrinsic/IoLibGcc.c
index 5c791289c469..05a739085967 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/IoLibGcc.c
+++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibGcc.c
@@ -16,6 +16,7 @@
 **/
 
 #include "BaseIoLibIntrinsicInternal.h"
+#include "IoLibTdx.h"
 
 /**
   Reads an 8-bit I/O port.
@@ -24,7 +25,9 @@
   This function must guarantee that all I/O read and write operations are
   serialized.
 
-  If 8-bit I/O port operations are not supported, then ASSERT().
+  If 8-bit I/O port operations are not supported, then ASSERT()
+
+  For Td guest TDVMCALL_IO is invoked to read I/O port.
 
   @param  Port  The I/O port to read.
 
@@ -42,7 +45,11 @@ IoRead8 (
 
   Flag = FilterBeforeIoRead (FilterWidth8, Port, );
   if (Flag) {
-__asm__ __volatile__ ("inb %w1,%b0" : "=a" (Data) : "d" ((UINT16)Port));
+if (IsTdxGuest ()) {
+  Data = TdIoRead8 (Port);
+} else {
+  __asm__ __volatile__ ("inb %w1,%b0" : "=a" (Data) : "d" ((UINT16)Port));
+}
   }
 
   FilterAfterIoRead (FilterWidth8, Port, );
@@ -59,6 +66,8 @@ IoRead8 (
 
   If 8-bit I/O port operations are not supported, then ASSERT().
 
+  For Td guest TDVMCALL_IO is invoked to write I/O port.
+
   @param  Port  The I/O port to write.
   @param  Value The value to write to the I/O port.
 
@@ -76,7 +85,11 @@ IoWrite8 (
 
   Flag = FilterBeforeIoWrite (FilterWidth8, Port, );
   if (Flag) {
-__asm__ __volatile__ ("outb %b0,%w1" : : "a" (Value), "d" ((UINT16)Port));
+if (IsTdxGuest ()) {
+  TdIoWrite8 (Port, Value);
+} else {
+  __asm__ __volatile__ ("outb %b0,%w1" : : "a" (Value), "d" 
((UINT16)Port));
+}
   }
 
   FilterAfterIoWrite (FilterWidth8, Port, );
@@ -94,6 +107,8 @@ IoWrite8 (
   If 16-bit I/O port operations are not supported, then ASSERT().
   If Port is not aligned on a 16-bit boundary, then ASSERT().
 
+  For Td guest TDVMCALL_IO is invoked to read I/O port.
+
   @param  Port  The I/O port to read.
 
   @return The value read.
@@ -112,7 +127,11 @@ IoRead16 (
 
   Flag = FilterBeforeIoRead (FilterWidth16, Port, );
   if (Flag) {
-__asm__ __volatile__ ("inw %w1,%w0" : "=a" (Data) : "d" ((UINT16)Port));
+if (IsTdxGuest ()) {
+  Data = TdIoRead16 (Port);
+} else {
+  __asm__ __volatile__ ("inw %w1,%w0" : "=a" (Data) : "d" ((UINT16)Port));
+}
   }
 
   FilterAfterIoRead (FilterWidth16, Port, );
@@ -130,6 +149,8 @@ IoRead16 (
   If 16-bit I/O port operations are not supported, then ASSERT().
   If Port is not aligned on a 16-bit boundary, then ASSERT().
 
+  For Td guest TDVMCALL_IO is invoked to write I/O port.
+
   @param  Port  The I/O port to write.
   @param  Value The value to write to the I/O port.
 
@@ -149,7 +170,11 @@ IoWrite16 (
 
   Flag = FilterBeforeIoWrite (FilterWidth16, Port, );
   if (Flag) {
-__asm__ __volatile__ ("outw %w0,%w1" : : "a" (Value), "d" ((UINT16)Port));
+if (IsTdxGuest ()) {
+  TdIoWrite16 (Port, Value);
+} else {
+  __asm__ __volatile__ ("outw %w0,%w1" : : "a" (Value), "d" 
((UINT16)Port));
+}
   }
 
   FilterAfterIoWrite (FilterWidth16, Port, );
@@ -167,6 +192,8 @@ IoWrite16 (
   If 32-bit I/O port operations are not supported, then ASSERT().
   If Port is not aligned on a 32-bit boundary, then ASSERT().
 
+  For Td guest TDVMCALL_IO is invoked to read I/O port.
+
   @param  Port  The I/O port to read.
 
   @return The value read.
@@ -185,7 +212,11 @@ IoRead32 (
 
   Flag = FilterBeforeIoRead (FilterWidth32, Port, );
   if (Flag) {
-__asm__ __volatile__ ("inl %w1,%0" : "=a" (Data) : "d" ((UINT16)Port));
+if (IsTdxGuest ()) {
+  Data = TdIoRead32 (Port);
+} else {
+  __asm__ __volatile__ ("inl %w1,%0" : "=a" (Data) : "d" ((UINT16)Port));
+}
   }
 
   FilterAfterIoRead (FilterWidth32, Port, );
@@ -203,6 +234,8 @@ IoRead32 (
   If 32-bit I/O port operations are not supported, then ASSERT().
   If Port is not aligned on a 32-bit boundary, then ASSERT().
 
+  For Td guest TDVMCALL_IO is invoked to write I/O port.
+
   @param  Port  The I/O port to write.
   @param  Value The value to write to the I/O port.
 
@@ -222,7 +255,11 @@ IoWrite32 (
 
   Flag = FilterBeforeIoWrite (FilterWidth32, Port, );
   if (Flag) {
-__asm__ __volatile__ ("outl %0,%w1" : : "a" (Value), "d" ((UINT16)Port));
+if 

[edk2-devel] [PATCH V9 10/47] MdePkg: Support IoFifo for Tdx guest in BaseIoLibIntrinsic

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429

Previously IoFifo functions are in X64/IoFifoSev.nasm which supports
both SEV guest and Legacy guest. IoLibFifo.c is introduced to support
SEV/TDX/Legacy guest in one binary. It checks the guest type in runtime
and call corresponding functions then.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Acked-by: Gerd Hoffmann 
Reviewed-by: Liming Gao 
Signed-off-by: Min Xu 
---
 .../BaseIoLibIntrinsicSev.inf |   2 +
 MdePkg/Library/BaseIoLibIntrinsic/IoLibFifo.c | 217 ++
 MdePkg/Library/BaseIoLibIntrinsic/IoLibSev.h  | 166 ++
 .../BaseIoLibIntrinsic/X64/IoFifoSev.nasm |  34 +--
 4 files changed, 402 insertions(+), 17 deletions(-)
 create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibFifo.c
 create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibSev.h

diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf 
b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf
index a74e54bee8b5..7fe1c60f046e 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf
+++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf
@@ -31,6 +31,7 @@
   BaseIoLibIntrinsicInternal.h
   IoHighLevel.c
   IoLibTdx.h
+  IoLibSev.h
 
 [Sources.IA32]
   IoLibGcc.c| GCC
@@ -44,6 +45,7 @@
   IoLibMsc.c| MSFT
   IoLib.c
   IoLibInternalTdx.c
+  IoLibFifo.c
   X64/IoFifoSev.nasm
 
 [Packages]
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibFifo.c 
b/MdePkg/Library/BaseIoLibIntrinsic/IoLibFifo.c
new file mode 100644
index ..9a94bc6a054c
--- /dev/null
+++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibFifo.c
@@ -0,0 +1,217 @@
+/** @file
+  IoFifo read/write routines.
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseIoLibIntrinsicInternal.h"
+#include "IoLibSev.h"
+#include "IoLibTdx.h"
+#include 
+#include 
+
+/**
+  Reads an 8-bit I/O port fifo into a block of memory.
+
+  Reads the 8-bit I/O fifo port specified by Port.
+  The port is read Count times, and the read data is
+  stored in the provided Buffer.
+
+  This function must guarantee that all I/O read and write operations are
+  serialized.
+
+  If 8-bit I/O port operations are not supported, then ASSERT().
+
+  In TDX a serial of TdIoRead8 is invoked to read the I/O port fifo.
+
+  @param  PortThe I/O port to read.
+  @param  Count   The number of times to read I/O port.
+  @param  Buffer  The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+IoReadFifo8 (
+  IN  UINTN  Port,
+  IN  UINTN  Count,
+  OUT VOID   *Buffer
+  )
+{
+  if (IsTdxGuest ()) {
+TdIoReadFifo8 (Port, Count, Buffer);
+  } else {
+SevIoReadFifo8 (Port, Count, Buffer);
+  }
+}
+
+/**
+  Writes a block of memory into an 8-bit I/O port fifo.
+
+  Writes the 8-bit I/O fifo port specified by Port.
+  The port is written Count times, and the write data is
+  retrieved from the provided Buffer.
+
+  This function must guarantee that all I/O write and write operations are
+  serialized.
+
+  If 8-bit I/O port operations are not supported, then ASSERT().
+
+  In TDX a serial of TdIoWrite8 is invoked to write data to the I/O port.
+
+  @param  PortThe I/O port to write.
+  @param  Count   The number of times to write I/O port.
+  @param  Buffer  The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+IoWriteFifo8 (
+  IN  UINTN  Port,
+  IN  UINTN  Count,
+  IN  VOID   *Buffer
+  )
+{
+  if (IsTdxGuest ()) {
+TdIoWriteFifo8 (Port, Count, Buffer);
+  } else {
+SevIoWriteFifo8 (Port, Count, Buffer);
+  }
+}
+
+/**
+  Reads a 16-bit I/O port fifo into a block of memory.
+
+  Reads the 16-bit I/O fifo port specified by Port.
+  The port is read Count times, and the read data is
+  stored in the provided Buffer.
+
+  This function must guarantee that all I/O read and write operations are
+  serialized.
+
+  If 16-bit I/O port operations are not supported, then ASSERT().
+
+  In TDX a serial of TdIoRead16 is invoked to read data from the I/O port.
+
+  @param  PortThe I/O port to read.
+  @param  Count   The number of times to read I/O port.
+  @param  Buffer  The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+IoReadFifo16 (
+  IN  UINTN  Port,
+  IN  UINTN  Count,
+  OUT VOID   *Buffer
+  )
+{
+  if (IsTdxGuest ()) {
+TdIoReadFifo16 (Port, Count, Buffer);
+  } else {
+SevIoReadFifo16 (Port, Count, Buffer);
+  }
+}
+
+/**
+  Writes a block of memory into a 16-bit I/O port fifo.
+
+  Writes the 16-bit I/O fifo port specified by Port.
+  The port is written Count times, and the write data is
+  retrieved from the provided Buffer.
+
+  This function must guarantee that all I/O write and write operations are
+  serialized.
+
+  If 16-bit I/O port operations are 

[edk2-devel] [PATCH V9 09/47] MdePkg: Support mmio for Tdx guest in BaseIoLibIntrinsic

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429

TDVF access MMIO with TDG.VP.VMCALL to invoke VMM provided emulation
functions. If the access to MMIO fails, it fall backs to the direct
access.

BaseIoLibIntrinsic.inf is the IoLib used by other packages. It will
not support I/O in Td guest. But some files are shared between
BaseIoLibIntrinsic and BaseIoLibIntrinsicSev (IoLib.c is the example). So
IoLibInternalTdxNull.c (which holds the null stub of the Td I/O routines)
is included in BaseIoLibIntrinsic.inf. BaseIoLibIntrinsic.inf doesn't
import TdxLib so that the Pkgs which include BaseIoLibIntrinsic.inf
need not include TdxLib.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Acked-by: Gerd Hoffmann 
Reviewed-by: Liming Gao 
Signed-off-by: Min Xu 
---
 .../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf |  2 +
 .../BaseIoLibIntrinsicSev.inf |  3 +
 MdePkg/Library/BaseIoLibIntrinsic/IoLib.c | 81 +--
 3 files changed, 78 insertions(+), 8 deletions(-)

diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf 
b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
index 97eeada0656e..27b15d9ae256 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
@@ -34,6 +34,8 @@
   IoLibMmioBuffer.c
   BaseIoLibIntrinsicInternal.h
   IoHighLevel.c
+  IoLibInternalTdxNull.c
+  IoLibTdx.h
 
 [Sources.IA32]
   IoLibGcc.c| GCC
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf 
b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf
index 336d79736d9a..a74e54bee8b5 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf
+++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf
@@ -30,17 +30,20 @@
   IoLibMmioBuffer.c
   BaseIoLibIntrinsicInternal.h
   IoHighLevel.c
+  IoLibTdx.h
 
 [Sources.IA32]
   IoLibGcc.c| GCC
   IoLibMsc.c| MSFT
   IoLib.c
+  IoLibInternalTdxNull.c
   Ia32/IoFifoSev.nasm
 
 [Sources.X64]
   IoLibGcc.c| GCC
   IoLibMsc.c| MSFT
   IoLib.c
+  IoLibInternalTdx.c
   X64/IoFifoSev.nasm
 
 [Packages]
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLib.c 
b/MdePkg/Library/BaseIoLibIntrinsic/IoLib.c
index 9d42e21a691c..5bd02b56a1fa 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/IoLib.c
+++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLib.c
@@ -7,6 +7,7 @@
 **/
 
 #include "BaseIoLibIntrinsicInternal.h"
+#include "IoLibTdx.h"
 
 /**
   Reads a 64-bit I/O port.
@@ -69,6 +70,8 @@ IoWrite64 (
 
   If 8-bit MMIO register operations are not supported, then ASSERT().
 
+  For Td guest TDVMCALL_MMIO is invoked to read MMIO registers.
+
   @param  Address The MMIO register to read.
 
   @return The value read.
@@ -86,7 +89,13 @@ MmioRead8 (
   Flag = FilterBeforeMmIoRead (FilterWidth8, Address, );
   if (Flag) {
 MemoryFence ();
-Value = *(volatile UINT8 *)Address;
+
+if (IsTdxGuest ()) {
+  Value = TdMmioRead8 (Address);
+} else {
+  Value = *(volatile UINT8 *)Address;
+}
+
 MemoryFence ();
   }
 
@@ -104,6 +113,8 @@ MmioRead8 (
 
   If 8-bit MMIO register operations are not supported, then ASSERT().
 
+  For Td guest TDVMCALL_MMIO is invoked to write MMIO registers.
+
   @param  Address The MMIO register to write.
   @param  Value   The value to write to the MMIO register.
 
@@ -122,7 +133,13 @@ MmioWrite8 (
   Flag = FilterBeforeMmIoWrite (FilterWidth8, Address, );
   if (Flag) {
 MemoryFence ();
-*(volatile UINT8 *)Address = Value;
+
+if (IsTdxGuest ()) {
+  TdMmioWrite8 (Address, Value);
+} else {
+  *(volatile UINT8 *)Address = Value;
+}
+
 MemoryFence ();
   }
 
@@ -141,6 +158,8 @@ MmioWrite8 (
   If 16-bit MMIO register operations are not supported, then ASSERT().
   If Address is not aligned on a 16-bit boundary, then ASSERT().
 
+  For Td guest TDVMCALL_MMIO is invoked to read MMIO registers.
+
   @param  Address The MMIO register to read.
 
   @return The value read.
@@ -159,7 +178,13 @@ MmioRead16 (
   Flag = FilterBeforeMmIoRead (FilterWidth16, Address, );
   if (Flag) {
 MemoryFence ();
-Value = *(volatile UINT16 *)Address;
+
+if (IsTdxGuest ()) {
+  Value = TdMmioRead16 (Address);
+} else {
+  Value = *(volatile UINT16 *)Address;
+}
+
 MemoryFence ();
   }
 
@@ -178,6 +203,8 @@ MmioRead16 (
   If 16-bit MMIO register operations are not supported, then ASSERT().
   If Address is not aligned on a 16-bit boundary, then ASSERT().
 
+  For Td guest TDVMCALL_MMIO is invoked to write MMIO registers.
+
   @param  Address The MMIO register to write.
   @param  Value   The value to write to the MMIO register.
 
@@ -198,7 +225,13 @@ MmioWrite16 (
   Flag = FilterBeforeMmIoWrite (FilterWidth16, Address, );
   if (Flag) {
 MemoryFence ();
-*(volatile UINT16 *)Address = Value;
+
+if (IsTdxGuest ()) 

[edk2-devel] [PATCH V9 07/47] UefiCpuPkg/CpuExceptionHandler: Add base support for the #VE exception

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429

Add base support to handle #VE exceptions. Update the common exception
handlers to invoke the VmTdExitHandleVe () function of the VmgExitLib
library when a #VE is encountered. A non-zero return code will propagate
to the targeted exception handler.

Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Acked-by: Gerd Hoffmann 
Reviewed-by: Ray Ni 
Signed-off-by: Min Xu 
---
 .../PeiDxeSmmCpuException.c   | 53 -
 .../SecPeiCpuException.c  | 57 +--
 2 files changed, 79 insertions(+), 31 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c
index 762ea2460f91..f47a80dcab8f 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c
@@ -24,25 +24,48 @@ CommonExceptionHandlerWorker (
   IN EXCEPTION_HANDLER_DATA  *ExceptionHandlerData
   )
 {
+  EFI_STATUS Status;
   EXCEPTION_HANDLER_CONTEXT  *ExceptionHandlerContext;
   RESERVED_VECTORS_DATA  *ReservedVectors;
   EFI_CPU_INTERRUPT_HANDLER  *ExternalInterruptHandler;
 
-  if (ExceptionType == VC_EXCEPTION) {
-EFI_STATUS  Status;
-//
-// #VC needs to be handled immediately upon enabling exception handling
-// and therefore can't use the RegisterCpuInterruptHandler() interface.
-//
-// Handle the #VC:
-//   On EFI_SUCCESS - Exception has been handled, return
-//   On other   - ExceptionType contains (possibly new) exception
-//value
-//
-Status = VmgExitHandleVc (, SystemContext);
-if (!EFI_ERROR (Status)) {
-  return;
-}
+  switch (ExceptionType) {
+case VC_EXCEPTION:
+  //
+  // #VC needs to be handled immediately upon enabling exception handling
+  // and therefore can't use the RegisterCpuInterruptHandler() interface.
+  //
+  // Handle the #VC:
+  //   On EFI_SUCCESS - Exception has been handled, return
+  //   On other   - ExceptionType contains (possibly new) exception
+  //value
+  //
+  Status = VmgExitHandleVc (, SystemContext);
+  if (!EFI_ERROR (Status)) {
+return;
+  }
+
+  break;
+
+case VE_EXCEPTION:
+  //
+  // #VE needs to be handled immediately upon enabling exception handling
+  // and therefore can't use the RegisterCpuInterruptHandler() interface.
+  //
+  // Handle the #VE:
+  //   On EFI_SUCCESS - Exception has been handled, return
+  //   On other   - ExceptionType contains (possibly new) exception
+  //value
+  //
+  Status = VmTdExitHandleVe (, SystemContext);
+  if (!EFI_ERROR (Status)) {
+return;
+  }
+
+  break;
+
+default:
+  break;
   }
 
   ExceptionHandlerContext  = (EXCEPTION_HANDLER_CONTEXT 
*)(UINTN)(SystemContext.SystemContextIa32);
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c
index c614d5b0b6f1..6e5216380da8 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c
@@ -25,22 +25,47 @@ CommonExceptionHandler (
   IN EFI_SYSTEM_CONTEXT  SystemContext
   )
 {
-  if (ExceptionType == VC_EXCEPTION) {
-EFI_STATUS  Status;
-//
-// #VC needs to be handled immediately upon enabling exception handling
-// and therefore can't use the RegisterCpuInterruptHandler() interface
-// (which isn't supported under Sec and Pei anyway).
-//
-// Handle the #VC:
-//   On EFI_SUCCESS - Exception has been handled, return
-//   On other   - ExceptionType contains (possibly new) exception
-//value
-//
-Status = VmgExitHandleVc (, SystemContext);
-if (!EFI_ERROR (Status)) {
-  return;
-}
+  EFI_STATUS  Status;
+
+  switch (ExceptionType) {
+case VC_EXCEPTION:
+  //
+  // #VC needs to be handled immediately upon enabling exception handling
+  // and therefore can't use the RegisterCpuInterruptHandler() interface
+  // (which isn't supported under Sec and Pei anyway).
+  //
+  // Handle the #VC:
+  //   On EFI_SUCCESS - Exception has been handled, return
+  //   On other   - ExceptionType contains (possibly new) exception
+  //value
+  //
+  Status = VmgExitHandleVc (, SystemContext);
+  if (!EFI_ERROR (Status)) {
+return;
+  }
+
+  break;
+
+case VE_EXCEPTION:
+  //
+  // #VE needs to be handled immediately upon enabling exception handling
+  // and therefore can't use the 

[edk2-devel] [PATCH V9 08/47] MdePkg: Add helper functions for Tdx guest in BaseIoLibIntrinsic

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429

Intel TDX architecture does not prescribe a specific software convention
to perform I/O from the guest TD. Guest TD providers have many choices to
provide I/O to the guest. The common I/O models are emulated devices,
para-virtualized devices, SRIOV devices and Direct Device assignments.

TDVF chooses para-virtualized I/O (Choice-A) which use the TDG.VP.VMCALL
function to invoke the funtions provided by the host VMM to perform I/O.
Another choice (Choice-B) is the emulation performed by the #VE handler.

There are 2 benefits of para-virtualized I/O:
1. Performance.
   VMEXIT/VMENTRY is skipped so that the performance is better than #VE
   handler.
2. De-couple with #VE handler.
   Choice-B depends on the #VE handler which means I/O is not available
   until #VE handler is installed. For example, in PEI phase #VE handler
   is installed in CpuMpPei, while communication with Qemu (via I/O port)
   happen earlier than it.

IoLibInternalTdx.c provides the helper functions for Tdx guest.
IoLibInternalTdxNull.c provides the null version of the helper functions.
It is included in the Non-X64 IoLib so that the build will not be broken.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Reviewed-by: Liming Gao 
Signed-off-by: Min Xu 
---
 .../BaseIoLibIntrinsicSev.inf |   2 +
 .../BaseIoLibIntrinsic/IoLibInternalTdx.c | 674 ++
 .../BaseIoLibIntrinsic/IoLibInternalTdxNull.c | 497 +
 MdePkg/Library/BaseIoLibIntrinsic/IoLibTdx.h  | 410 +++
 4 files changed, 1583 insertions(+)
 create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdx.c
 create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdxNull.c
 create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibTdx.h

diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf 
b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf
index 34f9d1d1062f..336d79736d9a 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf
+++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf
@@ -51,3 +51,5 @@
   BaseLib
   RegisterFilterLib
 
+[LibraryClasses.X64]
+  TdxLib
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdx.c 
b/MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdx.c
new file mode 100644
index ..1e539dbfbbad
--- /dev/null
+++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdx.c
@@ -0,0 +1,674 @@
+/** @file
+  TDX I/O Library routines.
+
+  Copyright (c) 2020-2021, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include "BaseIoLibIntrinsicInternal.h"
+#include 
+#include 
+#include 
+#include 
+#include "IoLibTdx.h"
+
+// Size of TDVMCALL Access, including IO and MMIO
+#define TDVMCALL_ACCESS_SIZE_1  1
+#define TDVMCALL_ACCESS_SIZE_2  2
+#define TDVMCALL_ACCESS_SIZE_4  4
+#define TDVMCALL_ACCESS_SIZE_8  8
+
+// Direction of TDVMCALL Access, including IO and MMIO
+#define TDVMCALL_ACCESS_READ   0
+#define TDVMCALL_ACCESS_WRITE  1
+
+BOOLEAN  mTdxEnabled = FALSE;
+BOOLEAN  mTdxProbed  = FALSE;
+
+/**
+  Check if it is Tdx guest.
+
+  @return TRUEIt is Tdx guest
+  @return FALSE   It is not Tdx guest
+
+**/
+BOOLEAN
+EFIAPI
+IsTdxGuest (
+  VOID
+  )
+{
+  if (mTdxProbed) {
+return mTdxEnabled;
+  }
+
+  mTdxEnabled = TdIsEnabled ();
+  mTdxProbed  = TRUE;
+
+  return mTdxEnabled;
+}
+
+/**
+  Reads an 8-bit I/O port.
+
+  TDVMCALL_IO is invoked to read I/O port.
+
+  @param  Port  The I/O port to read.
+
+  @return The value read.
+
+**/
+UINT8
+EFIAPI
+TdIoRead8 (
+  IN  UINTN  Port
+  )
+{
+  UINT64  Status;
+  UINT64  Val;
+
+  Status = TdVmCall (TDVMCALL_IO, TDVMCALL_ACCESS_SIZE_1, 
TDVMCALL_ACCESS_READ, Port, 0, );
+  if (Status != 0) {
+TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0);
+  }
+
+  return (UINT8)Val;
+}
+
+/**
+  Reads a 16-bit I/O port.
+
+  TDVMCALL_IO is invoked to write I/O port.
+
+  @param  Port  The I/O port to read.
+
+  @return The value read.
+
+**/
+UINT16
+EFIAPI
+TdIoRead16 (
+  IN  UINTN  Port
+  )
+{
+  UINT64  Status;
+  UINT64  Val;
+
+  ASSERT ((Port & 1) == 0);
+
+  Status = TdVmCall (TDVMCALL_IO, TDVMCALL_ACCESS_SIZE_2, 
TDVMCALL_ACCESS_READ, Port, 0, );
+  if (Status != 0) {
+TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0);
+  }
+
+  return (UINT16)Val;
+}
+
+/**
+  Reads a 32-bit I/O port.
+
+  TDVMCALL_IO is invoked to read I/O port.
+
+  @param  Port  The I/O port to read.
+
+  @return The value read.
+
+**/
+UINT32
+EFIAPI
+TdIoRead32 (
+  IN  UINTN  Port
+  )
+{
+  UINT64  Status;
+  UINT64  Val;
+
+  ASSERT ((Port & 3) == 0);
+
+  Status = TdVmCall (TDVMCALL_IO, TDVMCALL_ACCESS_SIZE_4, 
TDVMCALL_ACCESS_READ, Port, 0, );
+  if (Status != 0) {
+TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0);
+  }
+
+  return (UINT32)Val;
+}
+
+/**
+  Writes an 8-bit I/O port.
+
+  TDVMCALL_IO 

[edk2-devel] [PATCH V9 06/47] OvmfPkg: Extend VmgExitLib to handle #VE exception

[Min Xu]

RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429

The base VmgExitLib library provides a default limited interface to
handle #VE exception. To provide full support, the OVMF version of
VmgExitLib is extended to provide full support of #VE handler.

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Acked-by: Gerd Hoffmann 
Signed-off-by: Min Xu 
---
 OvmfPkg/Library/VmgExitLib/SecVmgExitLib.inf  |   3 +-
 OvmfPkg/Library/VmgExitLib/VmTdExitHandler.h  |  32 +
 .../Library/VmgExitLib/VmTdExitVeHandler.c| 559 ++
 OvmfPkg/Library/VmgExitLib/VmgExitLib.inf |   2 +
 .../Library/VmgExitLib/X64/TdVmcallCpuid.nasm | 146 +
 5 files changed, 741 insertions(+), 1 deletion(-)
 create mode 100644 OvmfPkg/Library/VmgExitLib/VmTdExitHandler.h
 create mode 100644 OvmfPkg/Library/VmgExitLib/VmTdExitVeHandler.c
 create mode 100644 OvmfPkg/Library/VmgExitLib/X64/TdVmcallCpuid.nasm

diff --git a/OvmfPkg/Library/VmgExitLib/SecVmgExitLib.inf 
b/OvmfPkg/Library/VmgExitLib/SecVmgExitLib.inf
index 78207fa0f9c9..f9bd4974f6dc 100644
--- a/OvmfPkg/Library/VmgExitLib/SecVmgExitLib.inf
+++ b/OvmfPkg/Library/VmgExitLib/SecVmgExitLib.inf
@@ -25,6 +25,8 @@
   VmgExitVcHandler.c
   VmgExitVcHandler.h
   SecVmgExitVcHandler.c
+  VmTdExitVeHandler.c
+  X64/TdVmcallCpuid.nasm
 
 [Packages]
   MdePkg/MdePkg.dec
@@ -44,4 +46,3 @@
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupSize
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidBase
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidSize
-
diff --git a/OvmfPkg/Library/VmgExitLib/VmTdExitHandler.h 
b/OvmfPkg/Library/VmgExitLib/VmTdExitHandler.h
new file mode 100644
index ..7eacd0872f46
--- /dev/null
+++ b/OvmfPkg/Library/VmgExitLib/VmTdExitHandler.h
@@ -0,0 +1,32 @@
+/** @file
+
+  Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef VMTD_EXIT_HANDLER_H_
+#define VMTD_EXIT_HANDLER_H_
+
+#include 
+#include 
+
+/**
+  This function enable the TD guest to request the VMM to emulate CPUID
+  operation, especially for non-architectural, CPUID leaves.
+
+  @param[in]  EaxMain leaf of the CPUID
+  @param[in]  EcxSub-leaf of the CPUID
+  @param[out] ResultsReturned result of CPUID operation
+
+  @return EFI_SUCCESS
+**/
+EFI_STATUS
+EFIAPI
+TdVmCallCpuid (
+  IN UINT64  Eax,
+  IN UINT64  Ecx,
+  OUT VOID   *Results
+  );
+
+#endif
diff --git a/OvmfPkg/Library/VmgExitLib/VmTdExitVeHandler.c 
b/OvmfPkg/Library/VmgExitLib/VmTdExitVeHandler.c
new file mode 100644
index ..b73e877c093b
--- /dev/null
+++ b/OvmfPkg/Library/VmgExitLib/VmTdExitVeHandler.c
@@ -0,0 +1,559 @@
+/** @file
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include "VmTdExitHandler.h"
+#include 
+#include 
+#include 
+#include 
+
+typedef union {
+  struct {
+UINT32Eax;
+UINT32Edx;
+  } Regs;
+  UINT64Val;
+} MSR_DATA;
+
+typedef union {
+  UINT8Val;
+  struct {
+UINT8B : 1;
+UINT8X : 1;
+UINT8R : 1;
+UINT8W : 1;
+  } Bits;
+} REX;
+
+typedef union {
+  UINT8Val;
+  struct {
+UINT8Rm  : 3;
+UINT8Reg : 3;
+UINT8Mod : 2;
+  } Bits;
+} MODRM;
+
+typedef struct {
+  UINT64Regs[4];
+} CPUID_DATA;
+
+/**
+  Handle an CPUID event.
+
+  Use the TDVMCALL instruction to handle cpuid #ve
+
+  @param[in, out] Regs x64 processor context
+  @param[in]  Veinfo   VE Info
+
+  @retval 0Event handled successfully
+  @return  New exception value to propagate
+**/
+STATIC
+UINT64
+EFIAPI
+CpuIdExit (
+  IN EFI_SYSTEM_CONTEXT_X64 *Regs,
+  IN TDCALL_VEINFO_RETURN_DATA  *Veinfo
+  )
+{
+  CPUID_DATA  CpuIdData;
+  UINT64  Status;
+
+  Status = TdVmCallCpuid (Regs->Rax, Regs->Rcx, );
+
+  if (Status == 0) {
+Regs->Rax = CpuIdData.Regs[0];
+Regs->Rbx = CpuIdData.Regs[1];
+Regs->Rcx = CpuIdData.Regs[2];
+Regs->Rdx = CpuIdData.Regs[3];
+  }
+
+  return Status;
+}
+
+/**
+  Handle an IO event.
+
+  Use the TDVMCALL instruction to handle either an IO read or an IO write.
+
+  @param[in, out] Regs x64 processor context
+  @param[in]  Veinfo   VE Info
+
+  @retval 0Event handled successfully
+  @return  New exception value to propagate
+**/
+STATIC
+UINT64
+EFIAPI
+IoExit (
+  IN OUT EFI_SYSTEM_CONTEXT_X64  *Regs,
+  IN TDCALL_VEINFO_RETURN_DATA   *Veinfo
+  )
+{
+  BOOLEAN  Write;
+  UINTNSize;
+  UINTNPort;
+  UINT64   Val;
+  UINT64   RepCnt;
+  UINT64   Status;
+
+  Val   = 0;
+  Write = Veinfo->ExitQualification.Io.Direction ? FALSE : TRUE;
+  Size  = Veinfo->ExitQualification.Io.Size + 1;
+  Port  = Veinfo->ExitQualification.Io.Port;
+
+  if 

[edk2-devel] [PATCH V9 05/47] UefiCpuPkg: Extend VmgExitLibNull to handle #VE exception

[Min Xu]

RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429

VmgExitLib performs the necessary processing to handle a #VC exception.
VmgExitLibNull is a NULL instance of VmgExitLib which provides a
default limited interface. In this commit VmgExitLibNull is extended to
handle a #VE exception with a default limited interface. A full feature
version of #VE handler will be created later.

Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Acked-by: Gerd Hoffmann 
Reviewed-by: Ray Ni 
Signed-off-by: Min Xu 
---
 UefiCpuPkg/Include/Library/VmgExitLib.h   | 28 ++
 .../Library/VmgExitLibNull/VmTdExitNull.c | 38 +++
 .../Library/VmgExitLibNull/VmgExitLibNull.inf |  1 +
 3 files changed, 67 insertions(+)
 create mode 100644 UefiCpuPkg/Library/VmgExitLibNull/VmTdExitNull.c

diff --git a/UefiCpuPkg/Include/Library/VmgExitLib.h 
b/UefiCpuPkg/Include/Library/VmgExitLib.h
index ebda1c3d907c..f9f911099a7b 100644
--- a/UefiCpuPkg/Include/Library/VmgExitLib.h
+++ b/UefiCpuPkg/Include/Library/VmgExitLib.h
@@ -15,6 +15,8 @@
 #include 
 #include 
 
+#define VE_EXCEPTION  20
+
 /**
   Perform VMGEXIT.
 
@@ -142,4 +144,30 @@ VmgExitHandleVc (
   IN OUT EFI_SYSTEM_CONTEXT  SystemContext
   );
 
+/**
+  Handle a #VE exception.
+
+  Performs the necessary processing to handle a #VE exception.
+
+  The base library function returns an error equal to VE_EXCEPTION,
+  to be propagated to the standard exception handling stack.
+
+  @param[in, out]  ExceptionType  Pointer to an EFI_EXCEPTION_TYPE to be set
+  as value to use on error.
+  @param[in, out]  SystemContext  Pointer to EFI_SYSTEM_CONTEXT
+
+  @retval  EFI_SUCCESSException handled
+  @retval  EFI_UNSUPPORTED#VE not supported, (new) exception value to
+  propagate provided
+  @retval  EFI_PROTOCOL_ERROR #VE handling failed, (new) exception value to
+  propagate provided
+
+**/
+EFI_STATUS
+EFIAPI
+VmTdExitHandleVe (
+  IN OUT EFI_EXCEPTION_TYPE  *ExceptionType,
+  IN OUT EFI_SYSTEM_CONTEXT  SystemContext
+  );
+
 #endif
diff --git a/UefiCpuPkg/Library/VmgExitLibNull/VmTdExitNull.c 
b/UefiCpuPkg/Library/VmgExitLibNull/VmTdExitNull.c
new file mode 100644
index ..6a4e8087cb89
--- /dev/null
+++ b/UefiCpuPkg/Library/VmgExitLibNull/VmTdExitNull.c
@@ -0,0 +1,38 @@
+/** @file
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include 
+#include 
+#include 
+
+/**
+  Handle a #VE exception.
+
+  Performs the necessary processing to handle a #VE exception.
+
+  @param[in, out]  ExceptionType  Pointer to an EFI_EXCEPTION_TYPE to be set
+  as value to use on error.
+  @param[in, out]  SystemContext  Pointer to EFI_SYSTEM_CONTEXT
+
+  @retval  EFI_SUCCESSException handled
+  @retval  EFI_UNSUPPORTED#VE not supported, (new) exception value to
+  propagate provided
+  @retval  EFI_PROTOCOL_ERROR #VE handling failed, (new) exception value to
+  propagate provided
+
+**/
+EFI_STATUS
+EFIAPI
+VmTdExitHandleVe (
+  IN OUT EFI_EXCEPTION_TYPE  *ExceptionType,
+  IN OUT EFI_SYSTEM_CONTEXT  SystemContext
+  )
+{
+  *ExceptionType = VE_EXCEPTION;
+
+  return EFI_UNSUPPORTED;
+}
diff --git a/UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf 
b/UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf
index d8770a21c355..4aab601939ff 100644
--- a/UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf
+++ b/UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf
@@ -17,6 +17,7 @@
 
 [Sources.common]
   VmgExitLibNull.c
+  VmTdExitNull.c
 
 [Packages]
   MdePkg/MdePkg.dec
-- 
2.29.2.windows.2



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[edk2-devel] [PATCH V9 04/47] MdePkg: Add TdxLib to wrap Tdx operations

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429

TdxLib is created with functions to perform the related Tdx operation.
This includes functions for:
 - TdAcceptPages   : Accept pending private pages and initialize the pages
 to all-0 using the TD ephemeral private key.
 - TdExtendRtmr: Extend measurement to one of the RTMR registers.
 - TdSharedPageMask: Get the Td guest shared page mask which indicates it
 is a Shared or Private page.
 - TdMaxVCpuNum: Get the maximum number of virtual CPUs.
 - TdVCpuNum   : Get the number of virtual CPUs.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Acked-by: Gerd Hoffmann 
Reviewed-by: Liming Gao 
Signed-off-by: Min Xu 
---
 MdePkg/Include/Library/TdxLib.h |  92 ++
 MdePkg/Library/TdxLib/AcceptPages.c | 181 
 MdePkg/Library/TdxLib/Rtmr.c|  84 +
 MdePkg/Library/TdxLib/TdInfo.c  | 115 ++
 MdePkg/Library/TdxLib/TdxLib.inf|  37 ++
 MdePkg/Library/TdxLib/TdxLibNull.c  | 106 
 MdePkg/MdePkg.dec   |   3 +
 MdePkg/MdePkg.dsc   |   1 +
 8 files changed, 619 insertions(+)
 create mode 100644 MdePkg/Include/Library/TdxLib.h
 create mode 100644 MdePkg/Library/TdxLib/AcceptPages.c
 create mode 100644 MdePkg/Library/TdxLib/Rtmr.c
 create mode 100644 MdePkg/Library/TdxLib/TdInfo.c
 create mode 100644 MdePkg/Library/TdxLib/TdxLib.inf
 create mode 100644 MdePkg/Library/TdxLib/TdxLibNull.c

diff --git a/MdePkg/Include/Library/TdxLib.h b/MdePkg/Include/Library/TdxLib.h
new file mode 100644
index ..55f0436cca1f
--- /dev/null
+++ b/MdePkg/Include/Library/TdxLib.h
@@ -0,0 +1,92 @@
+/** @file
+  TdxLib definitions
+
+  Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef TDX_LIB_H_
+#define TDX_LIB_H_
+
+/**
+  This function accepts a pending private page, and initialize the page to
+  all-0 using the TD ephemeral private key.
+
+  @param[in]  StartAddress Guest physical address of the private page
+   to accept. [63:52] and [11:0] must be 0.
+  @param[in]  NumberOfPagesNumber of the pages to be accepted.
+  @param[in]  PageSize GPA page size. Accept 2M/4K page size.
+
+  @return EFI_SUCCESS
+**/
+EFI_STATUS
+EFIAPI
+TdAcceptPages (
+  IN UINT64  StartAddress,
+  IN UINT64  NumberOfPages,
+  IN UINT32  PageSize
+  );
+
+/**
+  This function extends one of the RTMR measurement register
+  in TDCS with the provided extension data in memory.
+  RTMR extending supports SHA384 which length is 48 bytes.
+
+  @param[in]  Data  Point to the data to be extended
+  @param[in]  DataLen   Length of the data. Must be 48
+  @param[in]  Index RTMR index
+
+  @return EFI_SUCCESS
+  @return EFI_INVALID_PARAMETER
+  @return EFI_DEVICE_ERROR
+
+**/
+EFI_STATUS
+EFIAPI
+TdExtendRtmr (
+  IN  UINT32  *Data,
+  IN  UINT32  DataLen,
+  IN  UINT8   Index
+  );
+
+/**
+  This function gets the Td guest shared page mask.
+
+  The guest indicates if a page is shared using the Guest Physical Address
+  (GPA) Shared (S) bit. If the GPA Width(GPAW) is 48, the S-bit is bit-47.
+  If the GPAW is 52, the S-bit is bit-51.
+
+  @return Shared page bit mask
+**/
+UINT64
+EFIAPI
+TdSharedPageMask (
+  VOID
+  );
+
+/**
+  This function gets the maximum number of Virtual CPUs that are usable for
+  Td Guest.
+
+  @return maximum Virtual CPUs number
+**/
+UINT32
+EFIAPI
+TdMaxVCpuNum (
+  VOID
+  );
+
+/**
+  This function gets the number of Virtual CPUs that are usable for Td
+  Guest.
+
+  @return Virtual CPUs number
+**/
+UINT32
+EFIAPI
+TdVCpuNum (
+  VOID
+  );
+
+#endif
diff --git a/MdePkg/Library/TdxLib/AcceptPages.c 
b/MdePkg/Library/TdxLib/AcceptPages.c
new file mode 100644
index ..3a2182e95f47
--- /dev/null
+++ b/MdePkg/Library/TdxLib/AcceptPages.c
@@ -0,0 +1,181 @@
+/** @file
+
+  Unaccepted memory is a special type of private memory. In Td guest
+  TDCALL [TDG.MEM.PAGE.ACCEPT] is invoked to accept the unaccepted
+  memory before use it.
+
+  Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+UINT64  mNumberOfDuplicatedAcceptedPages;
+
+#define TDX_ACCEPTPAGE_MAX_RETRIED  3
+
+// PageSize is mapped to PageLevel like below:
+// 4KB - 0, 2MB - 1
+UINT32  mTdxAcceptPageLevelMap[2] = {
+  SIZE_4KB,
+  SIZE_2MB
+};
+
+#define INVALID_ACCEPT_PAGELEVEL  ARRAY_SIZE(mTdxAcceptPageLevelMap)
+
+/**
+  This function gets the PageLevel according to the input page size.
+
+  @param[in]  PageSizePage size
+
+  @return UINT32  The mapped page level
+**/
+UINT32
+GetGpaPageLevel (
+  UINT32  PageSize
+  )
+{
+  

[edk2-devel] [PATCH V9 03/47] MdePkg: Introduce basic Tdx functions in BaseLib

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429

Introduce basic Tdx functions in BaseLib:
 - TdCall ()
 - TdVmCall ()
 - TdIsEnabled ()

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Acked-by: Gerd Hoffmann 
Reviewed-by: Liming Gao 
Signed-off-by: Min Xu 
---
 MdePkg/Include/Library/BaseLib.h |  66 +++
 MdePkg/Library/BaseLib/BaseLib.inf   |   4 +
 MdePkg/Library/BaseLib/IntelTdxNull.c|  83 +
 MdePkg/Library/BaseLib/X64/TdCall.nasm   |  85 +
 MdePkg/Library/BaseLib/X64/TdProbe.c |  63 ++
 MdePkg/Library/BaseLib/X64/TdVmcall.nasm | 145 +++
 6 files changed, 446 insertions(+)
 create mode 100644 MdePkg/Library/BaseLib/IntelTdxNull.c
 create mode 100644 MdePkg/Library/BaseLib/X64/TdCall.nasm
 create mode 100644 MdePkg/Library/BaseLib/X64/TdProbe.c
 create mode 100644 MdePkg/Library/BaseLib/X64/TdVmcall.nasm

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 6aa0d972186e..9d58a7c4ad13 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -4759,6 +4759,72 @@ SpeculationBarrier (
   VOID
   );
 
+#if defined (MDE_CPU_X64) || defined (MDE_CPU_IA32)
+
+/**
+  The TDCALL instruction causes a VM exit to the Intel TDX module.  It is
+  used to call guest-side Intel TDX functions, either local or a TD exit
+  to the host VMM, as selected by Leaf.
+
+  @param[in]  LeafLeaf number of TDCALL instruction
+  @param[in]  Arg1Arg1
+  @param[in]  Arg2Arg2
+  @param[in]  Arg3Arg3
+  @param[in,out]  Results  Returned result of the Leaf function
+
+  @return 0   A successful call
+  @return Other   See individual leaf functions
+**/
+UINTN
+EFIAPI
+TdCall (
+  IN UINT64Leaf,
+  IN UINT64Arg1,
+  IN UINT64Arg2,
+  IN UINT64Arg3,
+  IN OUT VOID  *Results
+  );
+
+/**
+  TDVMALL is a leaf function 0 for TDCALL. It helps invoke services from the
+  host VMM to pass/receive information.
+
+  @param[in] LeafNumber of sub-functions
+  @param[in] Arg1Arg1
+  @param[in] Arg2Arg2
+  @param[in] Arg3Arg3
+  @param[in] Arg4Arg4
+  @param[in,out] Results Returned result of the sub-function
+
+  @return 0   A successful call
+  @return Other   See individual sub-functions
+
+**/
+UINTN
+EFIAPI
+TdVmCall (
+  IN UINT64Leaf,
+  IN UINT64Arg1,
+  IN UINT64Arg2,
+  IN UINT64Arg3,
+  IN UINT64Arg4,
+  IN OUT VOID  *Results
+  );
+
+/**
+  Probe if TD is enabled.
+
+  @return TRUETD is enabled.
+  @return FALSE   TD is not enabled.
+**/
+BOOLEAN
+EFIAPI
+TdIsEnabled (
+  VOID
+  );
+
+#endif
+
 #if defined (MDE_CPU_X64)
 //
 // The page size for the PVALIDATE instruction
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf 
b/MdePkg/Library/BaseLib/BaseLib.inf
index cebda3b210c1..16b7ac391705 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -210,6 +210,7 @@
   X86RdRand.c
   X86PatchInstruction.c
   X86SpeculationBarrier.c
+  IntelTdxNull.c
 
 [Sources.X64]
   X64/Thunk16.nasm
@@ -293,6 +294,9 @@
   X64/ReadCr0.nasm| MSFT
   X64/ReadEflags.nasm| MSFT
 
+  X64/TdCall.nasm
+  X64/TdVmcall.nasm
+  X64/TdProbe.c
 
   X64/Non-existing.c
   Math64.c
diff --git a/MdePkg/Library/BaseLib/IntelTdxNull.c 
b/MdePkg/Library/BaseLib/IntelTdxNull.c
new file mode 100644
index ..ec95470bd43e
--- /dev/null
+++ b/MdePkg/Library/BaseLib/IntelTdxNull.c
@@ -0,0 +1,83 @@
+/** @file
+
+  Null stub of TdxLib
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+
+/**
+  The TDCALL instruction causes a VM exit to the Intel TDX module.  It is
+  used to call guest-side Intel TDX functions, either local or a TD exit
+  to the host VMM, as selected by Leaf.
+  Leaf functions are described at 
+
+  @param[in]  LeafLeaf number of TDCALL instruction
+  @param[in]  Arg1Arg1
+  @param[in]  Arg2Arg2
+  @param[in]  Arg3Arg3
+  @param[in,out]  Results  Returned result of the Leaf function
+
+  @return EFI_SUCCESS
+  @return Other   See individual leaf functions
+**/
+UINTN
+EFIAPI
+TdCall (
+  IN UINT64Leaf,
+  IN UINT64Arg1,
+  IN UINT64Arg2,
+  IN UINT64Arg3,
+  IN OUT VOID  *Results
+  )
+{
+  return EFI_UNSUPPORTED;
+}
+
+/**
+  TDVMALL is a leaf function 0 for TDCALL. It helps invoke services from the
+  host VMM to pass/receive information.
+
+  @param[in] LeafNumber of sub-functions
+  @param[in] Arg1Arg1
+  @param[in] Arg2Arg2
+  @param[in] Arg3Arg3
+  

[edk2-devel] [PATCH V9 02/47] MdePkg: Update Cpuid.h for Tdx

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429

Guest software can be designed to run either as a TD, as a legacy virtual
machine, or directly on the CPU, based on enumeration of its run-time
environment. [TDX-Module] Chap 10.2 defines the flow and the new CPUID
leaf 0x21.

[TDX-Module] Architecture Specification: Intel(R) Trust Domain Extensions
Module, Chap 10.2, 344425-003US, August 2021
https://www.intel.com/content/dam/develop/external/us/en/documents/
tdx-module-1.0-public-spec-v0.931.pdf

Cc: Ray Ni 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Signed-off-by: Min Xu 
---
 MdePkg/Include/Register/Intel/Cpuid.h | 35 +--
 1 file changed, 33 insertions(+), 2 deletions(-)

diff --git a/MdePkg/Include/Register/Intel/Cpuid.h 
b/MdePkg/Include/Register/Intel/Cpuid.h
index bd6349d7940d..350bf60252e1 100644
--- a/MdePkg/Include/Register/Intel/Cpuid.h
+++ b/MdePkg/Include/Register/Intel/Cpuid.h
@@ -12,6 +12,8 @@
   @par Specification Reference:
   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,
   November 2018, CPUID instruction.
+  Architecture Specification: Intel(R) Trust Domain Extensions Module, Chap 
10.2
+  344425-003US, August 2021
 
 **/
 
@@ -321,9 +323,9 @@ typedef union {
 ///
 UINT32RDRAND  : 1;
 ///
-/// [Bit 31] Always returns 0.
+/// [Bit 31] A value of 1 indicates that processor is in Para-Virtualized.
 ///
-UINT32NotUsed : 1;
+UINT32ParaVirtualized : 1;
   } Bits;
   ///
   /// All bit fields as a 32-bit value
@@ -3689,6 +3691,35 @@ typedef union {
 /// @}
 ///
 
+/**
+  CPUID Guest TD Run Time Environment Enumeration Leaf
+
+  @note
+  Guest software can be designed to run either as a TD, as a legacy virtual 
machine,
+  or directly on the CPU, based on enumeration of its run-time environment.
+  CPUID leaf 21H emulation is done by the Intel TDX module. Sub-leaf 0 returns 
the values
+  shown below. Other sub-leaves return 0 in EAX/EBX/ECX/EDX.
+EAX: 0x
+EBX: 0x65746E49 "Inte"
+ECX: 0x20202020 ""
+EDX: 0x5844546C "lTDX"
+
+  @param   EAX  CPUID_GUESTTD_RUNTIME_ENVIRONMENT(0x21)
+  @param   ECX  Level number
+
+**/
+#define CPUID_GUESTTD_RUNTIME_ENVIRONMENT  0x21
+
+///
+/// @{ CPUID Guest TD signature values returned by Intel processors
+///
+#define CPUID_GUESTTD_SIGNATURE_GENUINE_INTEL_EBX  SIGNATURE_32 ('I', 'n', 
't', 'e')
+#define CPUID_GUESTTD_SIGNATURE_GENUINE_INTEL_ECX  SIGNATURE_32 (' ', ' ', ' 
', ' ')
+#define CPUID_GUESTTD_SIGNATURE_GENUINE_INTEL_EDX  SIGNATURE_32 ('l', 'T', 
'D', 'X')
+///
+/// @}
+///
+
 /**
   CPUID Extended Function
 
-- 
2.29.2.windows.2



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[edk2-devel] [PATCH V9 00/47] Enable Intel TDX in OvmfPkg (Config-A)

[Min Xu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3249

Intel's Trust Domain Extensions (Intel TDX) refers to an Intel technology
that extends Virtual Machines Extensions (VMX) and Multi-Key Total Memory
Encryption (MKTME) with a new kind of virutal machines guest called a 
Trust Domain (TD). A TD is desinged to run in a CPU mode that protects the
confidentiality of TD memory contents and the TD's CPU state from other
software, including the hosting Virtual-Machine Monitor (VMM), unless
explicitly shared by the TD itself.

There are 2 configurations for TDVF to upstream. See below link for
the definitions of the 2 configurations.
https://edk2.groups.io/g/devel/message/76367

This patch-set is to enable Config-A in OvmfPkg.
 - Merge the *basic* TDVF feature to existing OvmfX64Pkg.dsc. (Align
   with existing SEV)
 - Threat model: VMM is NOT out of TCB. (We don’t make things worse.)
 - The OvmfX64Pkg.dsc includes SEV/TDX/normal OVMF basic boot capability.
   The final binary can run on SEV/TDX/normal OVMF
 - No changes to existing OvmfPkgX64 image layout.
 - No need to add additional security features if they do not exist today
 - No need to remove features if they exist today.
 - RTMR is not supported
 - PEI phase is NOT skipped in either Td or Non-Td

Patch 01 - 33 are changes in SEC phase. Also some libraries in these
patches are workable in SEC/PEI/DXE.

Patch 16 - 29 extract the common codes from OvmfPkg/PlatformPei to a new
PlatformInitLib. After that OvmfPkg/PlatformPei is refactored with this
lib. These 14 patches are currently reviewed in another separate
patch-set. https://edk2.groups.io/g/devel/message/87327

Patch 34 - 39 are changes in PEI phase.

Patch 40 - 44 are changes in DXE phase.

Patch 45 - 47 are for local Apic timer DXE driver.

[TDX]: https://software.intel.com/content/dam/develop/external/us/en/
documents/tdx-whitepaper-final9-17.pdf

[TDX-Module]: https://software.intel.com/content/dam/develop/external/
us/en/documents/tdx-module-1.0-public-spec-v0.931.pdf

[TDVF]: https://software.intel.com/content/dam/develop/external/us/en/
documents/tdx-virtual-firmware-design-guide-rev-1.pdf

[GCHI]: https://software.intel.com/content/dam/develop/external/us/en/
documents/intel-tdx-guest-hypervisor-communication-interface-1.0-344426-002.pdf

Code is at https://github.com/mxu9/edk2/tree/tdvf_wave2.v9

v9 changes:
 - Move the definition of EFI_RESOURCE_MEMORY_UNACCEPTED from MdePkg
   to OvmfPkg as in internal implementation. Because it has not been
   added in PI spec. After the definition is added in PI spec, it can
   be moved to MdePkg.
 - Add definition of new CPUID leaf 0x21 in
   MdePkg/Include/Register/Intel/Cpuid.h.
 - Use switch-case to hanle VC/VE handling together in
   CpuExceptionHandlerLib.
 - Refactor changes for Tdx guest in MpInitLib.
 - Refine the comments in BaseLib and PlatformInitLib.
 - Other minor updates and changes.

v8 changes:
 - Based on the comments of PlatformInitLib and OvmfPkg/PlatformPei,
   a separte patch-set is created for the changes. It is now under review
   https://edk2.groups.io/g/devel/message/87327
 - Based on the comments, TdCall/TdVmCall/TdIsEnabled is wrapped with
   MDE_CPU_IA32 and MDE_CPU_X64.
 - EFI_RESOURCE_ATTRIBUTE_ENCRYPTED is removed based on the TDVF Spec
   update. Instead EFI_RESOURCE_MEMORY_UNACCEPTED is added to indicate
   the memory which to be accepted in TDVF. The corresponding logic
   of AcceptMemory is updated as well. Please see Patch 31.
 - PcdIa32EferChangeAllowed is deleted. Because for Td guest
   IA32_EFER.NXE is set by default. So we only need check whether it has
   been set before it is to be set again. See Patch 35.
 - Based on comments PcdTdxSharedBitMask is defined in
   [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
 - Delete un-necessary header files in TdxLib.h.
 - Other minor updates and changes.

v7 changes:
 - Based on the comments from last review, 8 PlatformInitLib patches
   are squashed into 4 patches (#17-#20). These 4 patches are not
   related to Tdx guest. Tdx related codes of PlatformInitLib is
   in #21.
 - gUefiOvmfPkgTdxPlatformGuid is renamed as gUefiOvmfPkgPlatformInfoGuid.
   Because this GUID is used not only by Tdx guest, but also by
   Legacy guest.
 - PlatformInitLibNull is deleted.
 - In PlatformPei Pml4Entries is cap at 512 entries when
   mPhysMemAddressWidth > 48.

v7 not-addressed comments
 - Comments in MpInitLib have not been addressed yet. It will be
   addressed in the following version.
 - Thanks much for your understanding.

v6 changes:
 - PlatformInitLib and OvmfPkg/PlatformPei refactoring are covered in
   patch from 17 - 24. These patches are not related to Tdx guest. Tdx
   related codes of PlatformInitLib is in patch 25.
 - In the previous patch-sets, TdHob is processed in
   OvmfPkg/Sec/IntelTdx.c. Per Gerd's suggestion they are now moved
   to PlatformInitLib/IntelTdx.c. So that they can be reused in Config-B.
 - The default Accept page size is 

[edk2-devel] [PATCH V9 01/47] MdePkg: Add Tdx.h

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429

Tdx.h includes the Intel Trust Domain Extension definitions.

Detailed information can be found in below document:
https://software.intel.com/content/dam/develop/external/us/en/
documents/tdx-module-1eas-v0.85.039.pdf

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Gerd Hoffmann 
Cc: Jiewen Yao 
Acked-by: Gerd Hoffmann 
Reviewed-by: Liming Gao 
Signed-off-by: Min Xu 
---
 MdePkg/Include/IndustryStandard/Tdx.h | 203 ++
 1 file changed, 203 insertions(+)
 create mode 100644 MdePkg/Include/IndustryStandard/Tdx.h

diff --git a/MdePkg/Include/IndustryStandard/Tdx.h 
b/MdePkg/Include/IndustryStandard/Tdx.h
new file mode 100644
index ..81df1361842b
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/Tdx.h
@@ -0,0 +1,203 @@
+/** @file
+  Intel Trust Domain Extension definitions
+  Detailed information is in below document:
+  https://software.intel.com/content/dam/develop/external/us/en/documents
+  /tdx-module-1eas-v0.85.039.pdf
+
+  Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef MDE_PKG_TDX_H_
+#define MDE_PKG_TDX_H_
+
+#define EXIT_REASON_EXTERNAL_INTERRUPT  1
+#define EXIT_REASON_TRIPLE_FAULT2
+
+#define EXIT_REASON_PENDING_INTERRUPT7
+#define EXIT_REASON_NMI_WINDOW   8
+#define EXIT_REASON_TASK_SWITCH  9
+#define EXIT_REASON_CPUID10
+#define EXIT_REASON_HLT  12
+#define EXIT_REASON_INVD 13
+#define EXIT_REASON_INVLPG   14
+#define EXIT_REASON_RDPMC15
+#define EXIT_REASON_RDTSC16
+#define EXIT_REASON_VMCALL   18
+#define EXIT_REASON_VMCLEAR  19
+#define EXIT_REASON_VMLAUNCH 20
+#define EXIT_REASON_VMPTRLD  21
+#define EXIT_REASON_VMPTRST  22
+#define EXIT_REASON_VMREAD   23
+#define EXIT_REASON_VMRESUME 24
+#define EXIT_REASON_VMWRITE  25
+#define EXIT_REASON_VMOFF26
+#define EXIT_REASON_VMON 27
+#define EXIT_REASON_CR_ACCESS28
+#define EXIT_REASON_DR_ACCESS29
+#define EXIT_REASON_IO_INSTRUCTION   30
+#define EXIT_REASON_MSR_READ 31
+#define EXIT_REASON_MSR_WRITE32
+#define EXIT_REASON_INVALID_STATE33
+#define EXIT_REASON_MSR_LOAD_FAIL34
+#define EXIT_REASON_MWAIT_INSTRUCTION36
+#define EXIT_REASON_MONITOR_TRAP_FLAG37
+#define EXIT_REASON_MONITOR_INSTRUCTION  39
+#define EXIT_REASON_PAUSE_INSTRUCTION40
+#define EXIT_REASON_MCE_DURING_VMENTRY   41
+#define EXIT_REASON_TPR_BELOW_THRESHOLD  43
+#define EXIT_REASON_APIC_ACCESS  44
+#define EXIT_REASON_EOI_INDUCED  45
+#define EXIT_REASON_GDTR_IDTR46
+#define EXIT_REASON_LDTR_TR  47
+#define EXIT_REASON_EPT_VIOLATION48
+#define EXIT_REASON_EPT_MISCONFIG49
+#define EXIT_REASON_INVEPT   50
+#define EXIT_REASON_RDTSCP   51
+#define EXIT_REASON_PREEMPTION_TIMER 52
+#define EXIT_REASON_INVVPID  53
+#define EXIT_REASON_WBINVD   54
+#define EXIT_REASON_XSETBV   55
+#define EXIT_REASON_APIC_WRITE   56
+#define EXIT_REASON_RDRAND   57
+#define EXIT_REASON_INVPCID  58
+#define EXIT_REASON_VMFUNC   59
+#define EXIT_REASON_ENCLS60
+#define EXIT_REASON_RDSEED   61
+#define EXIT_REASON_PML_FULL 62
+#define EXIT_REASON_XSAVES   63
+#define EXIT_REASON_XRSTORS  64
+
+// TDCALL API Function Completion Status Codes
+#define TDX_EXIT_REASON_SUCCESS0x
+#define TDX_EXIT_REASON_PAGE_ALREADY_ACCEPTED  0x0B0A
+#define TDX_EXIT_REASON_PAGE_SIZE_MISMATCH 0xCB0B
+#define TDX_EXIT_REASON_OPERAND_INVALID0xC100
+#define TDX_EXIT_REASON_OPERAND_BUSY   0x8200
+
+// TDCALL [TDG.MEM.PAGE.ACCEPT] page size
+#define TDCALL_ACCEPT_PAGE_SIZE_4K  0
+#define TDCALL_ACCEPT_PAGE_SIZE_2M  1
+#define TDCALL_ACCEPT_PAGE_SIZE_1G  2
+
+#define TDCALL_TDVMCALL  0
+#define TDCALL_TDINFO1
+#define TDCALL_TDEXTENDRTMR  2
+#define TDCALL_TDGETVEINFO   3
+#define TDCALL_TDREPORT  4
+#define TDCALL_TDSETCPUIDVE  5
+#define TDCALL_TDACCEPTPAGE  6
+
+#define TDVMCALL_CPUID0xa
+#define TDVMCALL_HALT 0xc
+#define TDVMCALL_IO   0x0001e
+#define TDVMCALL_RDMSR0x0001f
+#define TDVMCALL_WRMSR0x00020
+#define TDVMCALL_MMIO 0x00030
+#define TDVMCALL_PCONFIG  0x00041
+
+#define TDVMCALL_GET_TDVMCALL_INFO   0x1
+#define TDVMCALL_MAPGPA  0x10001
+#define TDVMCALL_GET_QUOTE   0x10002
+#define TDVMCALL_REPORT_FATAL_ERR0x10003
+#define TDVMCALL_SETUP_EVENT_NOTIFY  0x10004
+
+#pragma pack(1)
+typedef struct {
+  UINT64

Re: [edk2-devel] [Patch] Fix edkii-rust brach in edk2-staging

[ayushdevel1325]

Thanks Marvin. That guide is amazing.

As for rebasing, I will get to it once all the old stuff compiles successfully. 
Currently, I am working on getting acquainted with tianocore workflow and 
migrating everything from cargo-xbuild to build-std feature. Also, some of the 
nightly APIs have changed and some of the nightly APIs have also been 
stabilized, so just doing a bit of cleanup.

Ayush Singh


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Re: [edk2-devel] [Patch] Fix edkii-rust brach in edk2-staging

[Marvin Häuser]

CC Jiewen

(needs whitespace changes cleaned and the bench needs to be rebased beyond 2019 
too)

Also see: 
https://github.com/tianocore/tianocore.github.io/wiki/Laszlo's-unkempt-git-guide-for-edk2-contributors-and-maintainers

Best regards,
Marvin

> On 17. Mar 2022, at 15:54, ayushdevel1...@gmail.com wrote:
> 
> From: Ayush Singh 
> 
> Hello everyone,
> 
> I am Ayush Singh, an applicant for for GSoC 2022. My Introduction can be 
> found here.
> 
> To get myself acquainted with the project, I was trying to build the Rust 
> tests in edkii-rust branch in edk2-staging and found out that due to changes 
> in the Rust Allocator API, Test/TestRustLangLib and Test/RustLangApp fail to 
> build. Also, cargo now supports cross-compiling sysroot (build-std feature) 
> so there is no need for cargo-xbuild.
> 
> I have tried to fix Test/TestRustLangLib and would like someone to review if 
> it is correct. Here is the diff:
> 
> diff --git a/RustPkg/Library/UefiRustAllocationLib/src/lib.rs 
> b/RustPkg/Library/UefiRustAllocationLib/src/lib.rs
> index f369e1bb17..6a65f0a5f9 100644
> --- a/RustPkg/Library/UefiRustAllocationLib/src/lib.rs
> +++ b/RustPkg/Library/UefiRustAllocationLib/src/lib.rs
> @@ -15,44 +15,42 @@
>  #![feature(alloc_layout_extra)] 
>  #![feature(allocator_api)] 
>  #![feature(alloc_error_handler)] 
> - 
>  #![cfg_attr(not(test), no_std)] 
> - 
>  #![allow(unused)] 
>   
>  extern crate uefi_rust_panic_lib; 
>   
> -use core::alloc::{GlobalAlloc, Layout, Alloc}; 
> -use r_efi::efi; 
> -use r_efi::efi::{Status}; 
> +use core::alloc::{GlobalAlloc, Layout}; 
>  use core::ffi::c_void; 
> +use r_efi::efi; 
> +use r_efi::efi::Status; 
>   
>  pub struct MyAllocator; 
>   
> -static mut ST : *mut efi::SystemTable = core::ptr::null_mut(); 
> -static mut BS : *mut efi::BootServices = core::ptr::null_mut(); 
> +static mut ST: *mut efi::SystemTable = core::ptr::null_mut(); 
> +static mut BS: *mut efi::BootServices = core::ptr::null_mut(); 
>   
>  unsafe impl GlobalAlloc for MyAllocator { 
>  unsafe fn alloc(, layout: Layout) -> *mut u8 { 
> -  let size = layout.size(); 
> -  let align = layout.align(); 
> -  if align > 8 { 
> -return core::ptr::null_mut(); 
> -  } 
> +let size = layout.size(); 
> +let align = layout.align(); 
> +if align > 8 { 
> +return core::ptr::null_mut(); 
> +} 
>   
> -  let mut address : *mut c_void = core::ptr::null_mut(); 
> -  let status = ((*BS).allocate_pool) ( 
> - efi::MemoryType::BootServicesData, 
> - size, 
> -  address as *mut *mut c_void 
> - ); 
> -  if status != Status::SUCCESS { 
> -return core::ptr::null_mut(); 
> -  } 
> -  address as *mut u8 
> +let mut address: *mut c_void = core::ptr::null_mut(); 
> +let status = ((*BS).allocate_pool)( 
> +efi::MemoryType::BootServicesData, 
> +size, 
> + address as *mut *mut c_void, 
> +); 
> +if status != Status::SUCCESS { 
> +return core::ptr::null_mut(); 
> +} 
> +address as *mut u8 
>  } 
>  unsafe fn dealloc(, ptr: *mut u8, _layout: Layout) { 
> -  ((*BS).free_pool) (ptr as *mut c_void); 
> +((*BS).free_pool)(ptr as *mut c_void); 
>  } 
>  } 
>   
> @@ -60,14 +58,13 @@ unsafe impl GlobalAlloc for MyAllocator {
>  static ALLOCATOR: MyAllocator = MyAllocator; 
>   
>  #[alloc_error_handler] 
> -fn alloc_error_handler(layout: core::alloc::Layout) -> ! 
> -{ 
> +fn alloc_error_handler(layout: core::alloc::Layout) -> ! { 
>  loop {} 
>  } 
>   
> -pub extern fn init(system_table: *mut efi::SystemTable) { 
> +pub extern "C" fn init(system_table: *mut efi::SystemTable) { 
>  unsafe { 
> -  ST = system_table; 
> -  BS = (*ST).boot_services; 
> +ST = system_table; 
> +BS = (*ST).boot_services; 
>  } 
>  } 
> diff --git a/RustPkg/Test/HelloWorld/.cargo/config.toml 
> b/RustPkg/Test/HelloWorld/.cargo/config.toml
> new file mode 100644
> index 00..3d6a3ff35c
> --- /dev/null
> +++ b/RustPkg/Test/HelloWorld/.cargo/config.toml
> @@ -0,0 +1,3 @@
> +[unstable]
> +build-std = ["core", "compiler_builtins"]
> +build-std-features = ["compiler-builtins-mem"]
> diff --git a/RustPkg/Test/HelloWorld2/.cargo/config.toml 
> b/RustPkg/Test/HelloWorld2/.cargo/config.toml
> new file mode 100644
> index 00..3d6a3ff35c
> --- /dev/null
> +++ b/RustPkg/Test/HelloWorld2/.cargo/config.toml
> @@ -0,0 +1,3 @@
> +[unstable]
> +build-std = ["core", "compiler_builtins"]
> +build-std-features = ["compiler-builtins-mem"]
> diff --git a/RustPkg/Test/TestRustLangLib/.cargo/config.toml 
> b/RustPkg/Test/TestRustLangLib/.cargo/config.toml
> new file mode 100644
> index 00..422bf9d2ab
> --- /dev/null
> +++ b/RustPkg/Test/TestRustLangLib/.cargo/config.toml
> @@ -0,0 +1,3 @@
> +[unstable]
> +build-std = ["core", 

Re: [edk2-devel] [GSoC 2022] Introducing Myself

[Marvin Häuser]

Hey Ayush,

I heard Bret likes Rust. :) The Rust staging branch is owned by Jiewen. Nate 
handles GSoC. All CC’d (better get used to it fast :) ).

Best regards,
Marvin

> On 16. Mar 2022, at 23:16, ayushdevel1...@gmail.com wrote:
> Hello everyone,
> 
> I am Ayush Singh, a 2nd-year student from India. I am interested in the 
> proposal: Add Rust support to EDK II.
> 
> I am experienced in Rust, C, and Python. However, I have very little 
> experience with Assembly. I am currently participating in Season of KDE to 
> write Rust Bindings for KConfig. I am also a collaborator in qmetaobject 
> project which allows creating Qt applications with Rust.
> 
> While I have not done anything much that is so low-level, I am interested in 
> learning more about bare-metal programming. I have also used Rust without std 
> although it was when I was following along with the OS Philip Blog, so it was 
> not all that special.
> 
> Are there any tasks for this project that I can complete? Due to COVID, my 
> semester times are a bit off, so I don't have too much time to complete tasks 
> right now, but I will try my best.
> 


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Re: [edk2-devel] [PATCH v5 0/2] ShellPkg/AcpiView: Adds ACPI_PARSER bitfield parser

[Attar, AbdulLateef (Abdul Lateef) via groups.io]

Gentle reminder for PR.

-Original Message-
From: Gao, Zhichao  
Sent: Monday, February 21, 2022 1:10 PM
To: Attar, AbdulLateef (Abdul Lateef) ; 
devel@edk2.groups.io
Cc: Ni, Ray ; Sami Mujawar 
Subject: RE: [PATCH v5 0/2] ShellPkg/AcpiView: Adds ACPI_PARSER bitfield parser

[CAUTION: External Email]

Patchset Reviewed-by: Zhichao Gao 

Thanks,
Zhichao

> -Original Message-
> From: Abdul Lateef Attar 
> Sent: Wednesday, February 16, 2022 7:14 PM
> To: devel@edk2.groups.io
> Cc: Ni, Ray ; Gao, Zhichao ; 
> Sami Mujawar 
> Subject: [PATCH v5 0/2] ShellPkg/AcpiView: Adds ACPI_PARSER bitfield 
> parser
>
> Hi,
>   Sorry for the delayed reply.
> I had updated the patch according to the review comments.
> Please review the updated patch.
>
> REF: 
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith
> ub.com%2Fabdattar%2Fedk2%2Ftree%2FFadtFlagsParserV5data=04%7C01%7
> CAbdulLateef.Attar%40amd.com%7Cdbcced5d461947c4c52908d9f50d60e9%7C3dd8
> 961fe4884e608e11a82d994e183d%7C0%7C0%7C637810260090713957%7CUnknown%7C
> TWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVC
> I6Mn0%3D%7C3000sdata=lqrY9GyWZTJl%2BsRa%2F223ft8ei5rKBbm36av4SQh4
> l9g%3Dreserved=0
>
>
> Cc: Ray Ni 
> Cc: Zhichao Gao 
> Cc: Sami Mujawar 
>
> Abdul Lateef Attar (2):
>   ShellPkg/AcpiView: Adds ACPI_PARSER bitfield parser
>   ShellPkg/AcpiView: PrintFormatter for FADT Flags field
>
>  ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.h  |  48
> +
>  ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c  | 188
> 
>  
> ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Fadt/FadtParser.c
> | 167 +++--
>  3 files changed, 348 insertions(+), 55 deletions(-)
>
> --
> 2.25.1



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Re: [edk2-devel] [PATCH v6 1/1] CryptoPkg: Add new hash algorithm ParallelHash256HashAll in BaseCryptLib.

[Li, Zhihao]

Because it will cause patch to fail in CI test while to succeed if follow the 
setting.
Failed test: https://github.com/tianocore/edk2/pull/2535

I guess it's because data structure EDKII_CRYPTO_PROTOCOL( mEdkiiCrypto) 
doesn't have /// RSA PSS members in Crypto.c

> -Original Message-
> From: Yao, Jiewen 
> Sent: Thursday, March 17, 2022 10:13 PM
> To: Li, Zhihao ; devel@edk2.groups.io
> Cc: Wang, Jian J ; Lu, Xiaoyu1 ;
> Jiang, Guomin ; Fu, Siyuan 
> Subject: RE: [PATCH v6 1/1] CryptoPkg: Add new hash algorithm
> ParallelHash256HashAll in BaseCryptLib.
> 
> Hey
> Are you following the guideline - don't put new field in the middle ?
> 
> ParallelHash256HashAll API is still in the middle..
> 
> 
> > @@ -3641,6 +3670,8 @@ struct _EDKII_CRYPTO_PROTOCOL {
> >EDKII_CRYPTO_TLS_GET_HOST_PUBLIC_CERT  TlsGetHostPublicCert;
> >
> >EDKII_CRYPTO_TLS_GET_HOST_PRIVATE_KEY  TlsGetHostPrivateKey;
> >
> >EDKII_CRYPTO_TLS_GET_CERT_REVOCATION_LIST
> > TlsGetCertRevocationList;
> >
> > +  /// Parallel hash
> >
> > +  EDKII_CRYPTO_PARALLEL_HASH_ALL 
> > ParallelHash256HashAll;
> >
> >/// RSA PSS
> >
> >EDKII_CRYPTO_RSA_PSS_SIGN  RsaPssSign;
> >
> >EDKII_CRYPTO_RSA_PSS_VERIFYRsaPssVerify;
> >
> 
> 
> > -Original Message-
> > From: Li, Zhihao 
> > Sent: Thursday, March 17, 2022 12:35 PM
> > To: devel@edk2.groups.io
> > Cc: Yao, Jiewen ; Wang, Jian J
> ;
> > Lu, Xiaoyu1 ; Jiang, Guomin
> ;
> > Fu, Siyuan 
> > Subject: [PATCH v6 1/1] CryptoPkg: Add new hash algorithm
> > ParallelHash256HashAll in BaseCryptLib.
> >
> > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3596
> >
> > Parallel hash function ParallelHash256HashAll, as defined in NIST's
> > Special Publication 800-185, published December 2016. It utilizes
> > multi-process to calculate the digest.
> >
> > Passed CI test.
> > Onprotocol version code passed test.
> >
> > Cc: Jiewen Yao 
> > Cc: Jian J Wang 
> > Cc: Xiaoyu Lu 
> > Cc: Guomin Jiang 
> > Cc: Siyuan Fu 
> > Cc: Zhihao Li 
> >
> > Signed-off-by: Zhihao Li 
> > ---
> >  CryptoPkg/Driver/Crypto.c |  
> > 38 ++-
> >  CryptoPkg/Library/BaseCryptLib/Hash/CryptCShake256.c  | 282
> > 
> >  CryptoPkg/Library/BaseCryptLib/Hash/CryptParallelHash.c   | 278
> > +++
> >  CryptoPkg/Library/BaseCryptLib/Hash/CryptParallelHashNull.c   |  
> > 40 +++
> >  CryptoPkg/Library/BaseCryptLib/Hash/CryptSha3.c   | 166
> > 
> >  CryptoPkg/Library/BaseCryptLib/Hash/CryptXkcp.c   | 107
> 
> >  CryptoPkg/Library/BaseCryptLibNull/Hash/CryptParallelHashNull.c   |  40
> +++
> >  CryptoPkg/Library/BaseCryptLibOnProtocolPpi/CryptLib.c|  
> > 34 ++-
> >  CryptoPkg/Test/UnitTest/Library/BaseCryptLib/ParallelhashTests.c  | 145
> > ++
> >  CryptoPkg/CryptoPkg.ci.yaml   |   
> > 4 +-
> >  CryptoPkg/Include/Library/BaseCryptLib.h  |  
> > 31 ++-
> >  CryptoPkg/Include/Pcd/PcdCryptoServiceFamilyEnable.h  |   
> > 8 +-
> >  CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf   |   
> > 3 +-
> >  CryptoPkg/Library/BaseCryptLib/Hash/CryptParallelHash.h   | 201
> > ++
> >  CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf|   
> > 3 +-
> >  CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf|   
> > 3 +-
> >  CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf|   
> > 8 +-
> >  CryptoPkg/Library/BaseCryptLibNull/BaseCryptLibNull.inf   |   
> > 3 +-
> >  CryptoPkg/Library/Include/CrtLibSupport.h |   
> > 3 +-
> >  CryptoPkg/Private/Protocol/Crypto.h   |  
> > 35 ++-
> >  CryptoPkg/Test/CryptoPkgHostUnitTest.dsc  |   
> > 4 +
> >  CryptoPkg/Test/UnitTest/Library/BaseCryptLib/TestBaseCryptLibHost.inf |   4
> +
> >  22 files changed, 1426 insertions(+), 14 deletions(-)
> >
> > diff --git a/CryptoPkg/Driver/Crypto.c b/CryptoPkg/Driver/Crypto.c
> > index d5d6aa8e5820..5a9245c07cc5 100644
> > --- a/CryptoPkg/Driver/Crypto.c
> > +++ b/CryptoPkg/Driver/Crypto.c
> > @@ -3,7 +3,7 @@
> >from BaseCryptLib and TlsLib.
> >
> >
> >
> >Copyright (C) Microsoft Corporation. All rights reserved.
> >
> > -  Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
> >
> > +  Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.
> >
> >SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> >
> >
> >  **/
> >
> > @@ -4470,6 +4470,38 @@ CryptoServiceTlsGetCertRevocationList (
> >return CALL_BASECRYPTLIB (TlsGet.Services.CertRevocationList,
> > TlsGetCertRevocationList, (Data, DataSize), EFI_UNSUPPORTED);
> >
> >  }
> >
> >
> >

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Re: [edk2-devel] [PATCH 2/2] UefiPayloadPkg: Hookup SD/MMC timeout

[Guo Dong]

Reviewed-by: Guo Dong 

-Original Message-
From: Sean Rhodes  
Sent: Thursday, February 24, 2022 12:59 AM
To: devel@edk2.groups.io
Cc: Dong, Guo ; Rhodes, Sean ; Ni, 
Ray ; Ma, Maurice ; You, Benjamin 

Subject: [PATCH 2/2] UefiPayloadPkg: Hookup SD/MMC timeout

Hook SD_MMC_TIMEOUT build option to SdMmcGenericTimeoutValue PCD.

Cc: Guo Dong 
Cc: Ray Ni 
Cc: Maurice Ma 
Cc: Benjamin You 
Signed-off-by: Sean Rhodes 
---
 UefiPayloadPkg/UefiPayloadPkg.dsc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc 
b/UefiPayloadPkg/UefiPayloadPkg.dsc
index 1ce96a51c1..23c2787a94 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -33,6 +33,7 @@
   DEFINE UNIVERSAL_PAYLOAD= FALSE

   DEFINE SECURITY_STUB_ENABLE = TRUE

   DEFINE SMM_SUPPORT  = FALSE

+  DEFINE SD_MMC_TIMEOUT   = 100

   #

   # SBL:  UEFI payload for Slim Bootloader

   # COREBOOT: UEFI payload for coreboot

@@ -398,6 +399,7 @@
 !if $(PERFORMANCE_MEASUREMENT_ENABLE)

   gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask   | 0x1

 !endif

+  gEfiMdeModulePkgTokenSpaceGuid.PcdSdMmcGenericTimeoutValue|$(SD_MMC_TIMEOUT)

 

 [PcdsPatchableInModule.X64]

   gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|$(RTC_INDEX_REGISTER)

-- 
2.32.0



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[edk2-devel] [Patch] Fix edkii-rust brach in edk2-staging

[ayushdevel1325]

From: Ayush Singh 

Hello everyone,

I am Ayush Singh, an applicant for for GSoC 2022. My Introduction can be found 
here ( https://edk2.groups.io/g/devel/message/87637 ).

To get myself acquainted with the project, I was trying to build the Rust tests 
in edkii-rust branch in edk2-staging and found out that due to changes in the 
Rust Allocator API, *Test/TestRustLangLib* and *Test/RustLangApp* fail to 
build. Also, cargo now supports cross-compiling sysroot ( build-std feature ( 
https://doc.rust-lang.org/nightly/cargo/reference/unstable.html#build-std ) ) 
so there is no need for cargo-xbuild.

I have tried to fix *Test/TestRustLangLib* and would like someone to review if 
it is correct. Here is the diff:

diff --git a/RustPkg/Library/UefiRustAllocationLib/src/lib.rs 
b/RustPkg/Library/UefiRustAllocationLib/src/lib.rs
index f369e1bb17..6a65f0a5f9 100644
--- a/RustPkg/Library/UefiRustAllocationLib/src/lib.rs
+++ b/RustPkg/Library/UefiRustAllocationLib/src/lib.rs
@@ -15,44 +15,42 @@
#![feature(alloc_layout_extra)]
#![feature(allocator_api)]
#![feature(alloc_error_handler)]
-
#![cfg_attr(not(test), no_std)]
-
#![allow(unused)]

extern crate uefi_rust_panic_lib;

-use core::alloc::{GlobalAlloc, Layout, Alloc};
-use r_efi::efi;
-use r_efi::efi::{Status};
+use core::alloc::{GlobalAlloc, Layout};
use core::ffi::c_void;
+use r_efi::efi;
+use r_efi::efi::Status;

pub struct MyAllocator;

-static mut ST : *mut efi::SystemTable = core::ptr::null_mut();
-static mut BS : *mut efi::BootServices = core::ptr::null_mut();
+static mut ST: *mut efi::SystemTable = core::ptr::null_mut();
+static mut BS: *mut efi::BootServices = core::ptr::null_mut();

unsafe impl GlobalAlloc for MyAllocator {
unsafe fn alloc(, layout: Layout) -> *mut u8 {
-  let size = layout.size();
-  let align = layout.align();
-  if align > 8 {
-    return core::ptr::null_mut();
-  }
+    let size = layout.size();
+    let align = layout.align();
+    if align > 8 {
+    return core::ptr::null_mut();
+    }

-  let mut address : *mut c_void = core::ptr::null_mut();
-  let status = ((*BS).allocate_pool) (
- efi::MemoryType::BootServicesData,
- size,
-  address as *mut *mut c_void
- );
-  if status != Status::SUCCESS {
-    return core::ptr::null_mut();
-  }
-  address as *mut u8
+    let mut address: *mut c_void = core::ptr::null_mut();
+    let status = ((*BS).allocate_pool)(
+    efi::MemoryType::BootServicesData,
+    size,
+     address as *mut *mut c_void,
+    );
+    if status != Status::SUCCESS {
+    return core::ptr::null_mut();
+    }
+    address as *mut u8
}
unsafe fn dealloc(, ptr: *mut u8, _layout: Layout) {
-  ((*BS).free_pool) (ptr as *mut c_void);
+    ((*BS).free_pool)(ptr as *mut c_void);
}
}

@@ -60,14 +58,13 @@ unsafe impl GlobalAlloc for MyAllocator {
static ALLOCATOR: MyAllocator = MyAllocator;

#[alloc_error_handler]
-fn alloc_error_handler(layout: core::alloc::Layout) -> !
-{
+fn alloc_error_handler(layout: core::alloc::Layout) -> ! {
loop {}
}

-pub extern fn init(system_table: *mut efi::SystemTable) {
+pub extern "C" fn init(system_table: *mut efi::SystemTable) {
unsafe {
-  ST = system_table;
-  BS = (*ST).boot_services;
+    ST = system_table;
+    BS = (*ST).boot_services;
}
}
diff --git a/RustPkg/Test/HelloWorld/.cargo/config.toml 
b/RustPkg/Test/HelloWorld/.cargo/config.toml
new file mode 100644
index 00..3d6a3ff35c
--- /dev/null
+++ b/RustPkg/Test/HelloWorld/.cargo/config.toml
@@ -0,0 +1,3 @@
+[unstable]
+build-std = ["core", "compiler_builtins"]
+build-std-features = ["compiler-builtins-mem"]
diff --git a/RustPkg/Test/HelloWorld2/.cargo/config.toml 
b/RustPkg/Test/HelloWorld2/.cargo/config.toml
new file mode 100644
index 00..3d6a3ff35c
--- /dev/null
+++ b/RustPkg/Test/HelloWorld2/.cargo/config.toml
@@ -0,0 +1,3 @@
+[unstable]
+build-std = ["core", "compiler_builtins"]
+build-std-features = ["compiler-builtins-mem"]
diff --git a/RustPkg/Test/TestRustLangLib/.cargo/config.toml 
b/RustPkg/Test/TestRustLangLib/.cargo/config.toml
new file mode 100644
index 00..422bf9d2ab
--- /dev/null
+++ b/RustPkg/Test/TestRustLangLib/.cargo/config.toml
@@ -0,0 +1,3 @@
+[unstable]
+build-std = ["core", "compiler_builtins", "alloc"]
+build-std-features = ["compiler-builtins-mem"]
diff --git a/RustPkg/Test/TestRustLangLib/src/lib.rs 
b/RustPkg/Test/TestRustLangLib/src/lib.rs
index ee3a0d7cc8..888733232b 100644
--- a/RustPkg/Test/TestRustLangLib/src/lib.rs
+++ b/RustPkg/Test/TestRustLangLib/src/lib.rs
@@ -14,24 +14,22 @@

#![feature(alloc_layout_extra)]
#![feature(allocator_api)]
-#![feature(core_panic_info)]
-
+#![feature(slice_ptr_get)]
#![cfg_attr(not(test), no_std)]
-
#![allow(unused)]

mod mem;

use r_efi::efi;
-use r_efi::efi::{Status};
+use r_efi::efi::Status;

-extern {
-  fn 

Re: [edk2-devel] [PATCH v6 1/1] CryptoPkg: Add new hash algorithm ParallelHash256HashAll in BaseCryptLib.

[Yao, Jiewen]

Hey
Are you following the guideline - don't put new field in the middle ?

ParallelHash256HashAll API is still in the middle..


> @@ -3641,6 +3670,8 @@ struct _EDKII_CRYPTO_PROTOCOL {
>EDKII_CRYPTO_TLS_GET_HOST_PUBLIC_CERT  TlsGetHostPublicCert;
> 
>EDKII_CRYPTO_TLS_GET_HOST_PRIVATE_KEY  TlsGetHostPrivateKey;
> 
>EDKII_CRYPTO_TLS_GET_CERT_REVOCATION_LIST
> TlsGetCertRevocationList;
> 
> +  /// Parallel hash
> 
> +  EDKII_CRYPTO_PARALLEL_HASH_ALL ParallelHash256HashAll;
> 
>/// RSA PSS
> 
>EDKII_CRYPTO_RSA_PSS_SIGN  RsaPssSign;
> 
>EDKII_CRYPTO_RSA_PSS_VERIFYRsaPssVerify;
>


> -Original Message-
> From: Li, Zhihao 
> Sent: Thursday, March 17, 2022 12:35 PM
> To: devel@edk2.groups.io
> Cc: Yao, Jiewen ; Wang, Jian J ;
> Lu, Xiaoyu1 ; Jiang, Guomin ;
> Fu, Siyuan 
> Subject: [PATCH v6 1/1] CryptoPkg: Add new hash algorithm
> ParallelHash256HashAll in BaseCryptLib.
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3596
> 
> Parallel hash function ParallelHash256HashAll, as defined in NIST's
> Special Publication 800-185, published December 2016. It utilizes
> multi-process to calculate the digest.
> 
> Passed CI test.
> Onprotocol version code passed test.
> 
> Cc: Jiewen Yao 
> Cc: Jian J Wang 
> Cc: Xiaoyu Lu 
> Cc: Guomin Jiang 
> Cc: Siyuan Fu 
> Cc: Zhihao Li 
> 
> Signed-off-by: Zhihao Li 
> ---
>  CryptoPkg/Driver/Crypto.c |  38 
> ++-
>  CryptoPkg/Library/BaseCryptLib/Hash/CryptCShake256.c  | 282
> 
>  CryptoPkg/Library/BaseCryptLib/Hash/CryptParallelHash.c   | 278
> +++
>  CryptoPkg/Library/BaseCryptLib/Hash/CryptParallelHashNull.c   |  40 
> +++
>  CryptoPkg/Library/BaseCryptLib/Hash/CryptSha3.c   | 166
> 
>  CryptoPkg/Library/BaseCryptLib/Hash/CryptXkcp.c   | 107 
> 
>  CryptoPkg/Library/BaseCryptLibNull/Hash/CryptParallelHashNull.c   |  40 
> +++
>  CryptoPkg/Library/BaseCryptLibOnProtocolPpi/CryptLib.c|  34 
> ++-
>  CryptoPkg/Test/UnitTest/Library/BaseCryptLib/ParallelhashTests.c  | 145
> ++
>  CryptoPkg/CryptoPkg.ci.yaml   |   4 
> +-
>  CryptoPkg/Include/Library/BaseCryptLib.h  |  31 
> ++-
>  CryptoPkg/Include/Pcd/PcdCryptoServiceFamilyEnable.h  |   8 
> +-
>  CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf   |   3 
> +-
>  CryptoPkg/Library/BaseCryptLib/Hash/CryptParallelHash.h   | 201
> ++
>  CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf|   3 
> +-
>  CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf|   3 
> +-
>  CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf|   8 
> +-
>  CryptoPkg/Library/BaseCryptLibNull/BaseCryptLibNull.inf   |   3 
> +-
>  CryptoPkg/Library/Include/CrtLibSupport.h |   3 
> +-
>  CryptoPkg/Private/Protocol/Crypto.h   |  35 
> ++-
>  CryptoPkg/Test/CryptoPkgHostUnitTest.dsc  |   4 +
>  CryptoPkg/Test/UnitTest/Library/BaseCryptLib/TestBaseCryptLibHost.inf |   4 +
>  22 files changed, 1426 insertions(+), 14 deletions(-)
> 
> diff --git a/CryptoPkg/Driver/Crypto.c b/CryptoPkg/Driver/Crypto.c
> index d5d6aa8e5820..5a9245c07cc5 100644
> --- a/CryptoPkg/Driver/Crypto.c
> +++ b/CryptoPkg/Driver/Crypto.c
> @@ -3,7 +3,7 @@
>from BaseCryptLib and TlsLib.
> 
> 
> 
>Copyright (C) Microsoft Corporation. All rights reserved.
> 
> -  Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
> 
> +  Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.
> 
>SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> 
> 
>  **/
> 
> @@ -4470,6 +4470,38 @@ CryptoServiceTlsGetCertRevocationList (
>return CALL_BASECRYPTLIB (TlsGet.Services.CertRevocationList,
> TlsGetCertRevocationList, (Data, DataSize), EFI_UNSUPPORTED);
> 
>  }
> 
> 
> 
> +/**
> 
> +  Parallel hash function ParallelHash256, as defined in NIST's Special 
> Publication
> 800-185,
> 
> +  published December 2016.
> 
> +
> 
> +  @param[in]   InputPointer to the input message (X).
> 
> +  @param[in]   InputByteLen The number(>0) of input bytes provided for 
> the
> input data.
> 
> +  @param[in]   BlockSizeThe size of each block (B).
> 
> +  @param[out]  Output   Pointer to the output buffer.
> 
> +  @param[in]   OutputByteLenThe desired number of output bytes (L).
> 
> +  @param[in]   CustomizationPointer to the customization string (S).
> 
> +  @param[in]   CustomByteLenThe length of the customization string in 
> bytes.
> 
> +
> 
> +  @retval TRUE   ParallelHash256 digest computation succeeded.
> 
> +  @retval FALSE  

Re: [edk2-devel] [PATCH 5/8] MdePkg: Define CC Measure EventLog ACPI Table

[Yao, Jiewen]

Good, Thank you Samer.

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Samer El-
> Haj-Mahmoud
> Sent: Thursday, March 17, 2022 9:26 PM
> To: Yao, Jiewen ; Sami Mujawar
> ; Xu, Min M ;
> devel@edk2.groups.io
> Cc: Kinney, Michael D ; Gao, Liming
> ; Liu, Zhiguang ; Wang,
> Jian J ; Lu, Ken ; Gerd Hoffmann
> ; nd ; Thanu Rangarajan
> ; Samer El-Haj-Mahmoud  mahm...@arm.com>
> Subject: Re: [edk2-devel] [PATCH 5/8] MdePkg: Define CC Measure EventLog
> ACPI Table
> 
> Thanks Sami and Jiewen.
> 
> I will bring this to ASWG attention to confirm the change.
> 
> 
> 
> > -Original Message-
> > From: Yao, Jiewen 
> > Sent: Thursday, March 17, 2022 9:23 AM
> > To: Sami Mujawar ; Xu, Min M
> > ; devel@edk2.groups.io
> > Cc: Kinney, Michael D ; Gao, Liming
> > ; Liu, Zhiguang ; Wang,
> > Jian J ; Lu, Ken ; Gerd Hoffmann
> > ; nd ; Samer El-Haj-Mahmoud
> > ; Thanu Rangarajan
> > 
> > Subject: RE: [PATCH 5/8] MdePkg: Define CC Measure EventLog ACPI Table
> >
> > Thanks to remind me.
> >
> > I uploaded version 2 in the same mantis.
> >
> > Thank you
> > Yao Jiewen
> >
> > > -Original Message-
> > > From: Sami Mujawar 
> > > Sent: Thursday, March 17, 2022 9:10 PM
> > > To: Yao, Jiewen ; Xu, Min M
> > ;
> > > devel@edk2.groups.io
> > > Cc: Kinney, Michael D ; Gao, Liming
> > > ; Liu, Zhiguang ;
> > Wang,
> > > Jian J ; Lu, Ken ; Gerd Hoffmann
> > > ; nd ; Samer El-Haj-Mahmoud
> >  > > haj-mahm...@arm.com>; Thanu Rangarajan
> > 
> > > Subject: Re: [PATCH 5/8] MdePkg: Define CC Measure EventLog ACPI Table
> > >
> > > Hi Jiewen,
> > >
> > > I was informed there is an ASWG ECR
> > > https://mantis.uefi.org/mantis/view.php?id=2177 for TDEL. I can see the
> > > content has been approved for ACPI 6.5.
> > >
> > > Do you plan to update this ECR to reflect the changes for CCEL or this 
> > > would
> > be
> > > a separate request?
> > >
> > > Regards,
> > >
> > > Sami Mujawar
> > >
> > > On 10/03/2022, 10:27, "Sami Mujawar"  wrote:
> > >
> > > Hi Jiewen,
> > >
> > > Please find my response inline marked [SAMI].
> > >
> > > Regards,
> > >
> > > Sami Mujawar
> > >
> > > On 10/03/2022, 05:49, "Yao, Jiewen"  wrote:
> > >
> > > HI Sami
> > > I think it is OK to update signature to `CCEL`. That means it 
> > > will be
> > applicable
> > > for other CC, right?
> > > [SAMI] Yes, the same table can then be used by other CC.
> > >
> > > Then, I recommend we add CcType there.
> > >
> > > typedef struct {
> > >   EFI_ACPI_DESCRIPTION_HEADERHeader;
> > >   EFI_CC_TYPE   CcType; <== new field.
> > >   UINT16 Rsvd;
> > >   UINT64 Laml;
> > >   UINT64 Lasa;
> > > } EFI_CC_EVENTLOG_ACPI_TABLE;
> > >
> > > Do you agree?
> > > [SAMI] Agree, the above suggestion looks good to me.
> > >
> > > Thank you
> > > Yao Jiewen
> > >
> > > > -Original Message-
> > > > From: Sami Mujawar 
> > > > Sent: Wednesday, March 9, 2022 11:35 PM
> > > > To: Xu, Min M ; devel@edk2.groups.io
> > > > Cc: Kinney, Michael D ; Gao, Liming
> > > > ; Liu, Zhiguang
> > ;
> > > Yao,
> > > > Jiewen ; Wang, Jian J
> > ;
> > > Lu, Ken
> > > > ; Gerd Hoffmann ; nd
> > > ;
> > > > Samer El-Haj-Mahmoud ;
> > > > thanu.rangara...@arm.com
> > > > Subject: Re: [PATCH 5/8] MdePkg: Define CC Measure EventLog ACPI
> > > Table
> > > >
> > > > Hi Min,
> > > >
> > > > Thank you for this patch.
> > > >
> > > > Please find my response inline marked [SAMI].
> > > >
> > > > Regards,
> > > >
> > > > Sami Mujawar
> > > >
> > > >
> > > > On 02/03/2022 12:28 AM, Min Xu wrote:
> > > > > RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853
> > > > >
> > > > > TDVF set up an ACPI table (EFI_CC_EVENTLOG_ACPI_TABLE) to pass
> > the
> > > > > event-log information. The event log created by the TD owner
> > contains
> > > > > the hashes to reconstruct the MRTD and RTMR registers.
> > > > >
> > > > > Please refer to Sec 4.3.3 in blow link:
> > > > >
> > > https://www.intel.com/content/dam/develop/external/us/en/documents/
> > > > > intel-tdx-guest-hypervisor-communication-interface-1.0-344426-
> > > 002.pdf
> > > > >
> > > > > Cc: Michael D Kinney 
> > > > > Cc: Liming Gao 
> > > > > Cc: Zhiguang Liu 
> > > > > Cc: Jiewen Yao 
> > > > > Cc: Jian J Wang 
> > > > > Cc: Ken Lu 
> > > > > Cc: Sami Mujawar 
> > > > > Cc: Gerd Hoffmann 
> > > > > Signed-off-by: Min Xu 
> > > > > ---
> > > > >   MdePkg/Include/Protocol/CcMeasurement.h | 20
> > > 
> > > > >   1 file 

Re: [edk2-devel] [PATCH 5/8] MdePkg: Define CC Measure EventLog ACPI Table

[Samer El-Haj-Mahmoud]

Thanks Sami and Jiewen.

I will bring this to ASWG attention to confirm the change.



> -Original Message-
> From: Yao, Jiewen 
> Sent: Thursday, March 17, 2022 9:23 AM
> To: Sami Mujawar ; Xu, Min M
> ; devel@edk2.groups.io
> Cc: Kinney, Michael D ; Gao, Liming
> ; Liu, Zhiguang ; Wang,
> Jian J ; Lu, Ken ; Gerd Hoffmann
> ; nd ; Samer El-Haj-Mahmoud
> ; Thanu Rangarajan
> 
> Subject: RE: [PATCH 5/8] MdePkg: Define CC Measure EventLog ACPI Table
> 
> Thanks to remind me.
> 
> I uploaded version 2 in the same mantis.
> 
> Thank you
> Yao Jiewen
> 
> > -Original Message-
> > From: Sami Mujawar 
> > Sent: Thursday, March 17, 2022 9:10 PM
> > To: Yao, Jiewen ; Xu, Min M
> ;
> > devel@edk2.groups.io
> > Cc: Kinney, Michael D ; Gao, Liming
> > ; Liu, Zhiguang ;
> Wang,
> > Jian J ; Lu, Ken ; Gerd Hoffmann
> > ; nd ; Samer El-Haj-Mahmoud
>  > haj-mahm...@arm.com>; Thanu Rangarajan
> 
> > Subject: Re: [PATCH 5/8] MdePkg: Define CC Measure EventLog ACPI Table
> >
> > Hi Jiewen,
> >
> > I was informed there is an ASWG ECR
> > https://mantis.uefi.org/mantis/view.php?id=2177 for TDEL. I can see the
> > content has been approved for ACPI 6.5.
> >
> > Do you plan to update this ECR to reflect the changes for CCEL or this would
> be
> > a separate request?
> >
> > Regards,
> >
> > Sami Mujawar
> >
> > On 10/03/2022, 10:27, "Sami Mujawar"  wrote:
> >
> > Hi Jiewen,
> >
> > Please find my response inline marked [SAMI].
> >
> > Regards,
> >
> > Sami Mujawar
> >
> > On 10/03/2022, 05:49, "Yao, Jiewen"  wrote:
> >
> > HI Sami
> > I think it is OK to update signature to `CCEL`. That means it will 
> > be
> applicable
> > for other CC, right?
> > [SAMI] Yes, the same table can then be used by other CC.
> >
> > Then, I recommend we add CcType there.
> >
> > typedef struct {
> >   EFI_ACPI_DESCRIPTION_HEADERHeader;
> >   EFI_CC_TYPE   CcType; <== new field.
> >   UINT16 Rsvd;
> >   UINT64 Laml;
> >   UINT64 Lasa;
> > } EFI_CC_EVENTLOG_ACPI_TABLE;
> >
> > Do you agree?
> > [SAMI] Agree, the above suggestion looks good to me.
> >
> > Thank you
> > Yao Jiewen
> >
> > > -Original Message-
> > > From: Sami Mujawar 
> > > Sent: Wednesday, March 9, 2022 11:35 PM
> > > To: Xu, Min M ; devel@edk2.groups.io
> > > Cc: Kinney, Michael D ; Gao, Liming
> > > ; Liu, Zhiguang
> ;
> > Yao,
> > > Jiewen ; Wang, Jian J
> ;
> > Lu, Ken
> > > ; Gerd Hoffmann ; nd
> > ;
> > > Samer El-Haj-Mahmoud ;
> > > thanu.rangara...@arm.com
> > > Subject: Re: [PATCH 5/8] MdePkg: Define CC Measure EventLog ACPI
> > Table
> > >
> > > Hi Min,
> > >
> > > Thank you for this patch.
> > >
> > > Please find my response inline marked [SAMI].
> > >
> > > Regards,
> > >
> > > Sami Mujawar
> > >
> > >
> > > On 02/03/2022 12:28 AM, Min Xu wrote:
> > > > RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853
> > > >
> > > > TDVF set up an ACPI table (EFI_CC_EVENTLOG_ACPI_TABLE) to pass
> the
> > > > event-log information. The event log created by the TD owner
> contains
> > > > the hashes to reconstruct the MRTD and RTMR registers.
> > > >
> > > > Please refer to Sec 4.3.3 in blow link:
> > > >
> > https://www.intel.com/content/dam/develop/external/us/en/documents/
> > > > intel-tdx-guest-hypervisor-communication-interface-1.0-344426-
> > 002.pdf
> > > >
> > > > Cc: Michael D Kinney 
> > > > Cc: Liming Gao 
> > > > Cc: Zhiguang Liu 
> > > > Cc: Jiewen Yao 
> > > > Cc: Jian J Wang 
> > > > Cc: Ken Lu 
> > > > Cc: Sami Mujawar 
> > > > Cc: Gerd Hoffmann 
> > > > Signed-off-by: Min Xu 
> > > > ---
> > > >   MdePkg/Include/Protocol/CcMeasurement.h | 20
> > 
> > > >   1 file changed, 20 insertions(+)
> > > >
> > > > diff --git a/MdePkg/Include/Protocol/CcMeasurement.h
> > > b/MdePkg/Include/Protocol/CcMeasurement.h
> > > > index 83eaafaf10a6..86de226c1d82 100644
> > > > --- a/MdePkg/Include/Protocol/CcMeasurement.h
> > > > +++ b/MdePkg/Include/Protocol/CcMeasurement.h
> > > > @@ -307,4 +307,24 @@ extern EFI_GUID
> gEfiCcFinalEventsTableGuid;
> > > >
> > > >   extern EFI_GUID  gCcEventEntryHobGuid;
> > > >
> > > > +//
> > > > +// Define the CC Measure EventLog ACPI Table
> > > > +//
> > > > +#pragma pack(1)
> > > > +
> > > > +typedef struct {
> > > > +  EFI_ACPI_DESCRIPTION_HEADERHeader;
> > > > +  UINT32   

Re: [edk2-devel] [PATCH 5/8] MdePkg: Define CC Measure EventLog ACPI Table

[Yao, Jiewen]

Thanks to remind me. 

I uploaded version 2 in the same mantis.

Thank you
Yao Jiewen

> -Original Message-
> From: Sami Mujawar 
> Sent: Thursday, March 17, 2022 9:10 PM
> To: Yao, Jiewen ; Xu, Min M ;
> devel@edk2.groups.io
> Cc: Kinney, Michael D ; Gao, Liming
> ; Liu, Zhiguang ; Wang,
> Jian J ; Lu, Ken ; Gerd Hoffmann
> ; nd ; Samer El-Haj-Mahmoud  haj-mahm...@arm.com>; Thanu Rangarajan 
> Subject: Re: [PATCH 5/8] MdePkg: Define CC Measure EventLog ACPI Table
> 
> Hi Jiewen,
> 
> I was informed there is an ASWG ECR
> https://mantis.uefi.org/mantis/view.php?id=2177 for TDEL. I can see the
> content has been approved for ACPI 6.5.
> 
> Do you plan to update this ECR to reflect the changes for CCEL or this would 
> be
> a separate request?
> 
> Regards,
> 
> Sami Mujawar
> 
> On 10/03/2022, 10:27, "Sami Mujawar"  wrote:
> 
> Hi Jiewen,
> 
> Please find my response inline marked [SAMI].
> 
> Regards,
> 
> Sami Mujawar
> 
> On 10/03/2022, 05:49, "Yao, Jiewen"  wrote:
> 
> HI Sami
> I think it is OK to update signature to `CCEL`. That means it will be 
> applicable
> for other CC, right?
> [SAMI] Yes, the same table can then be used by other CC.
> 
> Then, I recommend we add CcType there.
> 
> typedef struct {
>   EFI_ACPI_DESCRIPTION_HEADERHeader;
>   EFI_CC_TYPE   CcType; <== new field.
>   UINT16 Rsvd;
>   UINT64 Laml;
>   UINT64 Lasa;
> } EFI_CC_EVENTLOG_ACPI_TABLE;
> 
> Do you agree?
> [SAMI] Agree, the above suggestion looks good to me.
> 
> Thank you
> Yao Jiewen
> 
> > -Original Message-
> > From: Sami Mujawar 
> > Sent: Wednesday, March 9, 2022 11:35 PM
> > To: Xu, Min M ; devel@edk2.groups.io
> > Cc: Kinney, Michael D ; Gao, Liming
> > ; Liu, Zhiguang ;
> Yao,
> > Jiewen ; Wang, Jian J ;
> Lu, Ken
> > ; Gerd Hoffmann ; nd
> ;
> > Samer El-Haj-Mahmoud ;
> > thanu.rangara...@arm.com
> > Subject: Re: [PATCH 5/8] MdePkg: Define CC Measure EventLog ACPI
> Table
> >
> > Hi Min,
> >
> > Thank you for this patch.
> >
> > Please find my response inline marked [SAMI].
> >
> > Regards,
> >
> > Sami Mujawar
> >
> >
> > On 02/03/2022 12:28 AM, Min Xu wrote:
> > > RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853
> > >
> > > TDVF set up an ACPI table (EFI_CC_EVENTLOG_ACPI_TABLE) to pass the
> > > event-log information. The event log created by the TD owner 
> contains
> > > the hashes to reconstruct the MRTD and RTMR registers.
> > >
> > > Please refer to Sec 4.3.3 in blow link:
> > >
> https://www.intel.com/content/dam/develop/external/us/en/documents/
> > > intel-tdx-guest-hypervisor-communication-interface-1.0-344426-
> 002.pdf
> > >
> > > Cc: Michael D Kinney 
> > > Cc: Liming Gao 
> > > Cc: Zhiguang Liu 
> > > Cc: Jiewen Yao 
> > > Cc: Jian J Wang 
> > > Cc: Ken Lu 
> > > Cc: Sami Mujawar 
> > > Cc: Gerd Hoffmann 
> > > Signed-off-by: Min Xu 
> > > ---
> > >   MdePkg/Include/Protocol/CcMeasurement.h | 20
> 
> > >   1 file changed, 20 insertions(+)
> > >
> > > diff --git a/MdePkg/Include/Protocol/CcMeasurement.h
> > b/MdePkg/Include/Protocol/CcMeasurement.h
> > > index 83eaafaf10a6..86de226c1d82 100644
> > > --- a/MdePkg/Include/Protocol/CcMeasurement.h
> > > +++ b/MdePkg/Include/Protocol/CcMeasurement.h
> > > @@ -307,4 +307,24 @@ extern EFI_GUID  gEfiCcFinalEventsTableGuid;
> > >
> > >   extern EFI_GUID  gCcEventEntryHobGuid;
> > >
> > > +//
> > > +// Define the CC Measure EventLog ACPI Table
> > > +//
> > > +#pragma pack(1)
> > > +
> > > +typedef struct {
> > > +  EFI_ACPI_DESCRIPTION_HEADERHeader;
> > > +  UINT32 Rsvd;
> > > +  UINT64 Laml;
> > > +  UINT64 Lasa;
> > > +} EFI_CC_EVENTLOG_ACPI_TABLE;
> > > +
> > > +#pragma pack()
> > > +
> > > +//
> > > +// Define the signature and revision of CC Measurement EventLog 
> ACPI
> Table
> > for Td guest
> > > +//
> > > +#define EFI_CC_EVENTLOG_ACPI_TABLE_TD_SIGNATURE
> SIGNATURE_32('T',
> > 'D', 'E', 'L')
> > > +#define EFI_CC_EVENTLOG_ACPI_TABLE_TD_REVISION   1
> > [SAMI] I can see that the above macros have the _TD_ infix. Is the
> > intention here that each architecture shall define its own 
> signature 

Re: [edk2-devel] [PATCH 5/8] MdePkg: Define CC Measure EventLog ACPI Table

[Sami Mujawar]

Hi Jiewen,

I was informed there is an ASWG ECR 
https://mantis.uefi.org/mantis/view.php?id=2177 for TDEL. I can see the content 
has been approved for ACPI 6.5.

Do you plan to update this ECR to reflect the changes for CCEL or this would be 
a separate request?

Regards,

Sami Mujawar

On 10/03/2022, 10:27, "Sami Mujawar"  wrote:

Hi Jiewen,

Please find my response inline marked [SAMI].

Regards,

Sami Mujawar

On 10/03/2022, 05:49, "Yao, Jiewen"  wrote:

HI Sami
I think it is OK to update signature to `CCEL`. That means it will be 
applicable for other CC, right?
[SAMI] Yes, the same table can then be used by other CC. 

Then, I recommend we add CcType there.

typedef struct {
  EFI_ACPI_DESCRIPTION_HEADERHeader;
  EFI_CC_TYPE   CcType; <== new field.
  UINT16 Rsvd;
  UINT64 Laml;
  UINT64 Lasa;
} EFI_CC_EVENTLOG_ACPI_TABLE;

Do you agree?
[SAMI] Agree, the above suggestion looks good to me. 

Thank you
Yao Jiewen

> -Original Message-
> From: Sami Mujawar 
> Sent: Wednesday, March 9, 2022 11:35 PM
> To: Xu, Min M ; devel@edk2.groups.io
> Cc: Kinney, Michael D ; Gao, Liming
> ; Liu, Zhiguang ; 
Yao,
> Jiewen ; Wang, Jian J ; 
Lu, Ken
> ; Gerd Hoffmann ; nd 
;
> Samer El-Haj-Mahmoud ;
> thanu.rangara...@arm.com
> Subject: Re: [PATCH 5/8] MdePkg: Define CC Measure EventLog ACPI Table
> 
> Hi Min,
> 
> Thank you for this patch.
> 
> Please find my response inline marked [SAMI].
> 
> Regards,
> 
> Sami Mujawar
> 
> 
> On 02/03/2022 12:28 AM, Min Xu wrote:
> > RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853
> >
> > TDVF set up an ACPI table (EFI_CC_EVENTLOG_ACPI_TABLE) to pass the
> > event-log information. The event log created by the TD owner 
contains
> > the hashes to reconstruct the MRTD and RTMR registers.
> >
> > Please refer to Sec 4.3.3 in blow link:
> > https://www.intel.com/content/dam/develop/external/us/en/documents/
> > 
intel-tdx-guest-hypervisor-communication-interface-1.0-344426-002.pdf
> >
> > Cc: Michael D Kinney 
> > Cc: Liming Gao 
> > Cc: Zhiguang Liu 
> > Cc: Jiewen Yao 
> > Cc: Jian J Wang 
> > Cc: Ken Lu 
> > Cc: Sami Mujawar 
> > Cc: Gerd Hoffmann 
> > Signed-off-by: Min Xu 
> > ---
> >   MdePkg/Include/Protocol/CcMeasurement.h | 20 
> >   1 file changed, 20 insertions(+)
> >
> > diff --git a/MdePkg/Include/Protocol/CcMeasurement.h
> b/MdePkg/Include/Protocol/CcMeasurement.h
> > index 83eaafaf10a6..86de226c1d82 100644
> > --- a/MdePkg/Include/Protocol/CcMeasurement.h
> > +++ b/MdePkg/Include/Protocol/CcMeasurement.h
> > @@ -307,4 +307,24 @@ extern EFI_GUID  gEfiCcFinalEventsTableGuid;
> >
> >   extern EFI_GUID  gCcEventEntryHobGuid;
> >
> > +//
> > +// Define the CC Measure EventLog ACPI Table
> > +//
> > +#pragma pack(1)
> > +
> > +typedef struct {
> > +  EFI_ACPI_DESCRIPTION_HEADERHeader;
> > +  UINT32 Rsvd;
> > +  UINT64 Laml;
> > +  UINT64 Lasa;
> > +} EFI_CC_EVENTLOG_ACPI_TABLE;
> > +
> > +#pragma pack()
> > +
> > +//
> > +// Define the signature and revision of CC Measurement EventLog 
ACPI Table
> for Td guest
> > +//
> > +#define EFI_CC_EVENTLOG_ACPI_TABLE_TD_SIGNATURE  SIGNATURE_32('T',
> 'D', 'E', 'L')
> > +#define EFI_CC_EVENTLOG_ACPI_TABLE_TD_REVISION   1
> [SAMI] I can see that the above macros have the _TD_ infix. Is the
> intention here that each architecture shall define its own signature 
and
> revision?
> Would it be possible to make the signature generic across 
architectures,
> e.g. "SIGNATURE_32('C', 'C', 'E', 'L')" ?
> [/SAMI]
> > +
> >   #endif





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invite.ics
Description: application/ics

Re: [edk2-devel][PATCH] MdeModulePkg: Make RSP 16-byte boundary aligned for PEI 64bit

[Marvin Häuser]

Good day,


On 17. Mar 2022, at 02:05, Kuo, Ted  wrote:

Hi Liming and Mike,

Can you please review the change?

Thanks,
Ted

-Original Message-
From: devel@edk2.groups.io  On Behalf Of Kuo, Ted
Sent: Thursday, March 10, 2022 2:21 PM
To: devel@edk2.groups.io
Cc: Bi, Dandan ; Gao, Liming 
; De, Debkumar ; Han, 
Harry ; West, Catharine 
; Wang, Jian J ; S, 
Ashraf Ali 
Subject: [edk2-devel][PATCH] MdeModulePkg: Make RSP 16-byte boundary 
aligned for PEI 64bit


REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3865
Use SwitchPeiCore instead of calling PeiCore directly when switching 
PeiCore from temporary memory to permanent memory. For PEI 32bit, 
SwitchPeiCore always calls PeiCore without any additional step. For 
PEI 64bit, SwitchPeiCore makes RSP 16-byte boundary aligned and then 
allocate 32 bytes as a shadow store on call stack before calling PeiCore.


Cc: Dandan Bi 
Cc: Liming Gao 
Cc: Debkumar De 
Cc: Harry Han 
Cc: Catharine West 
Cc: Jian J Wang 
Cc: Ashraf Ali S 
Signed-off-by: Ted Kuo 
---
MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c |  2 +- 
 MdeModulePkg/Core/Pei/Ia32/SwitchPeiCore.nasm | 33 
+++

MdeModulePkg/Core/Pei/PeiMain.h   | 25 ++
MdeModulePkg/Core/Pei/PeiMain.inf |  6 +
MdeModulePkg/Core/Pei/X64/SwitchPeiCore.nasm  | 38 
+++
5 files changed, 103 insertions(+), 1 deletion(-)  create mode 100644 
MdeModulePkg/Core/Pei/Ia32/SwitchPeiCore.nasm

create mode 100644 MdeModulePkg/Core/Pei/X64/SwitchPeiCore.nasm

diff --git a/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c 
b/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c

index 3552feda8f..5af6e6e86f 100644
--- a/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
+++ b/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
@@ -871,7 +871,7 @@ PeiCheckAndSwitchStack (
  //
  // Entry PEI Phase 2
  //
-  PeiCore (SecCoreData, NULL, Private);
+  SwitchPeiCore (SecCoreData, NULL, Private);
} else {
  //
  // Migrate memory pages allocated in pre-memory phase.
diff --git a/MdeModulePkg/Core/Pei/Ia32/SwitchPeiCore.nasm 
b/MdeModulePkg/Core/Pei/Ia32/SwitchPeiCore.nasm

new file mode 100644
index 00..23cfb5090b
--- /dev/null
+++ b/MdeModulePkg/Core/Pei/Ia32/SwitchPeiCore.nasm
@@ -0,0 +1,33 @@
+;--
+
+;
+; Copyright (c) 2022, Intel Corporation. All rights reserved. ;
+SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract:
+;
+;   Switch PeiCore from temporary memory to permanent memory.
+;
+;--
+
+
+    SECTION .text
+
+extern ASM_PFX(PeiCore)
+
+;--
+
+; VOID
+; EFIAPI
+; SwitchPeiCore (
+;   EFI_SEC_PEI_HAND_OFF    *SecCoreDataPtr,
+;   EFI_PEI_PPI_DESCRIPTOR  *PpiList,
+;   VOID    *Data
+;   );
+;--
+
+global ASM_PFX(SwitchPeiCore)
+ASM_PFX(SwitchPeiCore):
+  push   DWORD [esp + 12]
+  push   DWORD [esp + 12]
+  push   DWORD [esp + 12]
+  call   ASM_PFX(PeiCore)
+  jmp    $    ; Should never reach here
+  ret
+


I think there were efforts in the past to avoid ASM whenever possible. 
Can’t this just remain a C function (for IA32 only of course) and if 
not, wouldn't a simple jmp instruction be sufficient?


diff --git a/MdeModulePkg/Core/Pei/PeiMain.h 
b/MdeModulePkg/Core/Pei/PeiMain.h index 556beddad5..8e8ed3dadf 100644

--- a/MdeModulePkg/Core/Pei/PeiMain.h
+++ b/MdeModulePkg/Core/Pei/PeiMain.h
@@ -2038,4 +2038,29 @@ PeiReinitializeFv (
  IN  PEI_CORE_INSTANCE  *PrivateData
  );

+/**
+  This routine is invoked by main entry of PeiMain module during
+transition
+  from temporary memory to permanent memory.
+
+  @param SecCoreDataPtr  Points to a data structure containing 
information about the PEI core's operating
+ environment, such as the size and location 
of temporary RAM, the stack location and

+ the BFV location.
+  @param PpiList Points to a list of one or more PPI 
descriptors to be installed initially by the PEI core.
+ An empty PPI list consists of a single 
descriptor with the end-tag
+ EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST. As 
part of its initialization
+ phase, the PEI Foundation will add these 
SEC-hosted PPIs to its PPI database such
+ that both the PEI Foundation and any modules 
can leverage the associated service

+ calls and/or code in these early PPIs
+  @param Data    Pointer to old core data that is used to 
initialize the

+ core's data areas.
+ If NULL, it is first PeiCore entering.
+
+**/
+VOID
+EFIAPI
+SwitchPeiCore (
+  IN CONST 

Re: [edk2-devel] [PATCH edk2-platforms 3/3] Platform/ARM/JunoPkg: Reserve the ECAM area in ACPI with RES0 device

[Sami Mujawar]

Hi Rebecca,

Thank you for this patch. This change looks good to me.

I have a minor suggestion marked inline as [SAMI].

With that upated,

Tested-by: Sami Mujawar 
Reviewed-by: Sami Mujawar 

Regards,

Sami Mujawar
On 05/03/2022 04:19 AM, Rebecca Cran wrote:

Add a RES0 device to the SSDT to reserve the PCI ECAM area.

This fixes the warning that Linux prints:

acpi PNP0A08:00: [Firmware Bug]: ECAM area [mem 0x4000-0x4fff]
not reserved in ACPI namespace

[SAMI] I noticed that the "Firmware Bug" message is no longer seen, but
instead the following message is now printed
"system 00:00: [mem 0x4000-0x4fff window] could not be reserved"

It appears this is a harmless message and the relevant discussion can be
seen at: https://lore.kernel.org/all/20210603141641.GA17284@lpieralisi/#t

I think it may be better to update the commit message to reference this
discussion and clarify that this is an expected behavior.
[/SAMI]


Signed-off-by: Rebecca Cran 
---
  Platform/ARM/JunoPkg/AcpiTables/AcpiTables.inf  |  4 
  Platform/ARM/JunoPkg/AcpiTables/AcpiSsdtRootPci.asl | 13 +
  2 files changed, 17 insertions(+)

diff --git a/Platform/ARM/JunoPkg/AcpiTables/AcpiTables.inf 
b/Platform/ARM/JunoPkg/AcpiTables/AcpiTables.inf
index f140febc4ad4..9a76475765f0 100644
--- a/Platform/ARM/JunoPkg/AcpiTables/AcpiTables.inf
+++ b/Platform/ARM/JunoPkg/AcpiTables/AcpiTables.inf
@@ -45,6 +45,10 @@ [FixedPcd]
gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase

+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+  gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceSize
+  gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceLimit
+
#
# PL011 UART Settings for Serial Port Console Redirection
#
diff --git a/Platform/ARM/JunoPkg/AcpiTables/AcpiSsdtRootPci.asl 
b/Platform/ARM/JunoPkg/AcpiTables/AcpiSsdtRootPci.asl
index 317b621e013e..e60fc42a3340 100644
--- a/Platform/ARM/JunoPkg/AcpiTables/AcpiSsdtRootPci.asl
+++ b/Platform/ARM/JunoPkg/AcpiTables/AcpiSsdtRootPci.asl
@@ -140,6 +140,19 @@ DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", 
"ARM-JUNO", EFI_ACPI_ARM_OEM
  Return (RBUF)
} // Method(_CRS)

+  Device (RES0) {
+Name (_HID, "PNP0C02" /* PNP Motherboard Resources */)  // _HID: 
Hardware ID
+Name (_CRS, ResourceTemplate () {   // _CRS: 
Current Resource Settings
+   QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, 
NonCacheable, ReadWrite,
+   0x,  // Granularity
+   FixedPcdGet64 (PcdPciExpressBaseAddress),// Range 
Minimum
+   FixedPcdGet64 (PcdPciConfigurationSpaceLimit),   // Range 
Maximum
+   0x,  // Translation 
Offset
+   FixedPcdGet64 (PcdPciConfigurationSpaceSize),// Length
+   ,, , AddressRangeMemory, TypeStatic)
+})
+  }
+
//
// OS Control Handoff
//


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Re: [edk2-devel] [PATCH edk2-platforms 2/3] Platform/ARM/JunoPkg: Use MdePkg PcdPciExpressBaseAddress for ECAM addr

[Sami Mujawar]

Hi Rebecca,

I have one minor suggestion marked inline as [SAMI]. Otherwise these
changes look good to me.

With that changed,

Reviewed-by: Sami Mujawar 

Regards,

Sami Mujawar


On 05/03/2022 04:19 AM, Rebecca Cran wrote:

Instead of using a custom Pcd for the ECAM address
(gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress),
use the Pcd from MdePkg.

Signed-off-by: Rebecca Cran 
---
  Platform/ARM/JunoPkg/ArmJuno.dec  
| 4 ++--
  
Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
 | 2 +-
  Platform/ARM/JunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf
| 2 +-
  Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoLib.inf
| 2 +-
  Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.inf
| 2 +-
  Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/XPressRich3.h   
| 2 +-
  
Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
  | 2 +-
  Platform/ARM/JunoPkg/Drivers/ArmJunoDxe/AcpiTables.c  
| 2 +-
  Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c  
| 4 ++--
  9 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/Platform/ARM/JunoPkg/ArmJuno.dec b/Platform/ARM/JunoPkg/ArmJuno.dec
index 37ea6857366f..b6437d6fe98c 100644
--- a/Platform/ARM/JunoPkg/ArmJuno.dec
+++ b/Platform/ARM/JunoPkg/ArmJuno.dec
@@ -34,8 +34,8 @@ [PcdsFeatureFlag.common]
  [PcdsFixedAtBuild.common]

gArmJunoTokenSpaceGuid.PcdPcieControlBaseAddress|0x7FF2|UINT64|0x000B

gArmJunoTokenSpaceGuid.PcdPcieRootPortBaseAddress|0x7FF3|UINT64|0x000C
-  
gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress|0x4000|UINT64|0x0011
-  
gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceSize|0x1000|UINT64|0x0012
+  
gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceSize|0x1000|UINT64|0x0011
+  
gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceLimit|0x4FFF|UINT64|0x0012


gArmJunoTokenSpaceGuid.PcdSynopsysUsbOhciBaseAddress|0x7FFB|UINT32|0x0004

gArmJunoTokenSpaceGuid.PcdSynopsysUsbEhciBaseAddress|0x7FFC|UINT32|0x0005
diff --git 
a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
 
b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
index 00be2c435bd6..7ca134d6674b 100644
--- 
a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
+++ 
b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
@@ -46,7 +46,7 @@ [Protocols]

  [FixedPcd]
# PCI Root complex specific PCDs
-  gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceSize

## PL011 Serial Debug UART
diff --git a/Platform/ARM/JunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf 
b/Platform/ARM/JunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf
index d016967c3c37..c35984c172e1 100644
--- a/Platform/ARM/JunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf
+++ b/Platform/ARM/JunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf
@@ -67,7 +67,7 @@ [FixedPcd]
gArmJunoTokenSpaceGuid.PcdJunoFdtDevicePath

# PCI Root complex specific PCDs
-  gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gArmTokenSpaceGuid.PcdPciBusMin
gArmTokenSpaceGuid.PcdPciBusMax

diff --git a/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoLib.inf 
b/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoLib.inf
index 145663c2fa28..fb80f10a9409 100644
--- a/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoLib.inf
+++ b/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoLib.inf
@@ -45,7 +45,7 @@ [FixedPcd]
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask

gArmJunoTokenSpaceGuid.PcdPcieControlBaseAddress
-  gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceSize

# Framebuffer Memory
diff --git 
a/Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.inf 
b/Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.inf
index f448803fda7d..784618ffa013 100644
--- a/Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.inf
+++ b/Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.inf
@@ -62,7 +62,7 @@ [FixedPcd]

gArmJunoTokenSpaceGuid.PcdPcieControlBaseAddress
gArmJunoTokenSpaceGuid.PcdPcieRootPortBaseAddress
-  gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceSize

  [Protocols]
diff --git 

Re: [edk2-devel][PATCH] UefiCpuPkg: Update BFV searching algorithm in VTF0

[Min Xu]

On March 17, 2022 4:39 PM, Kuo Ted wrote:
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3870
> The new algorithm searches FFS3 GUID first and then FFS2 GUID at every 4KB
> address in the top 16MB just below 4GB.
> 
> Cc: Ray Ni 
> Cc: Debkumar De 
> Cc: Harry Han 
> Cc: Catharine West 
> Cc: Min Xu 
> Signed-off-by: Ted Kuo 
> ---
>  .../Vtf0/Bin/IA32/ResetVector.ia32.port80.raw   | Bin 548 -> 532 bytes
>  .../ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.raw  | Bin 516 -> 500 bytes
>  .../Vtf0/Bin/IA32/ResetVector.ia32.serial.raw   | Bin 932 -> 900 bytes
>  .../Bin/X64/PageTable1G/ResetVector.x64.port80.raw  | Bin 12292 -> 12292
> bytes
>  .../Vtf0/Bin/X64/PageTable1G/ResetVector.x64.raw| Bin 12292 -> 12292
> bytes
>  .../Bin/X64/PageTable1G/ResetVector.x64.serial.raw  | Bin 12292 -> 12292
> bytes  .../Bin/X64/PageTable2M/ResetVector.x64.port80.raw  | Bin 28676 ->
> 28676 bytes
>  .../Vtf0/Bin/X64/PageTable2M/ResetVector.x64.raw| Bin 28676 -> 28676
> bytes
>  .../Bin/X64/PageTable2M/ResetVector.x64.serial.raw  | Bin 28676 -> 28676
> bytes
>  .../ResetVector/Vtf0/Ia32/SearchForBfvBase.asm  |  19 +--
>  10 files changed, 5 insertions(+), 14 deletions(-)
> 
> diff --git
> a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw
> b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw
> index
> 23254e83bf1a17dee9f38c235fcc9948624a7536..a3601274c25dde665872ff3
> 75f1deadf1c838476 100644 GIT binary patch delta 190
> zcmZ3&}9%{V6bIiVEA7Y*;pY^b)Yz;RJO4~ %^pr3W>e>a??t=
> z8!KcwpPS4oWqPdwR8{e`r>FENP?c?$jDP7KpsJasor$HJfvQ>$>s~Hh)m)*%P`a
> e^
> zFmr@L>D<@68#X*^*s*-
> 2o*Lifq#%B#L8KWjnif8;k@l&;M&40Z#en#=M9m)(0
> p4*W_7(q6?+ZeUbk^qjnqQF!tuMib78|1Z`5{r~@R;pF#>rU2NrRB!+Q
> 
> delta 211
> zcmbQjvV^660uUG;*vZVmz@W<@z`$S)9RYyQbxs@7N`P<5a !Q@*8l
> z8!IIC=F3ehz0z1A)A`(FR_W>2DnL~gPkVYw4**r!cFFjcZU?HGY1)}sx(=wS^|0>c
> z(xuH6Dh#FbI}bBQD3s24Eoykcv-u}uY2Sto!p|CZ><5C*qp$yU9^J6 ze 1ofx&@a=|I}6#L0P#3LNee Ka`EK*jHUp(F<`s^
> 
> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.raw
> b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.raw
> index
> 18562d8f1f58601f66fcb0cbf2f994046ce48fde..6124f3f9a40e4e58cc672b54c
> bf5cc33360b3858 100644 GIT binary patch delta 192
> zcmZo+`NCX30SF8a=rRZ}FxWCMF#IoyY^)HdI#3)^D%)5ga@zKkZ>dOQg~Z-
> `xoM@`
> zjTJJT
> s;YR}(^GmBsLHlW#=mqAP}NM+`WbuX8$YOYXWC|%Nd
> zm^nhBbna`;9s7Zx^XTh;okw3fGBPk2-
> tN3Nabf`DyNQp=g rI*|4%dvXq=441u9|NoybVe$kLTf4OV)8Aly`5
> 
> delta 202
> zcmeyu+`>{n0SF8a>||zOV9;d{U|_HXGX59EHUDHTRcoves5(#_Qu?g1LgcjVDc{
> n&
> zjTI7m^W~3nW7tMv416`-n$r#(HT2Y{+ Jw*ytpH0?|*T?bUvdRX^z
> z>C)y36^7FJorjqt6iR2j7BoEI+5D5Sv~S0L?*04scOHHHuk+|j`-v6djBh4hC>L(~
> zub0NpD4w=MnSsH9U+F;FtK7*^j4~W{6XY2t{Qv)das#6oNB2vMfB*l#+%tI}qZt
> 4b
> C>RJ*2
> 
> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.serial.raw
> b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.serial.raw
> index
> e4aa4fc30a32bc3d4d8d0e1726c43fdafef4a374..48b46e3473e77a1179bf818a
> 1f1deafb7e46cf3e 100644 GIT binary patch delta 206
> zcmZ3&-
> oidXwqBLl@PICZ00V<90|UeVqR7SyfvN+=A*Hg76(Xl?Px+RLG*(FL&6k^2
> z%H3EY)A`(FRw>hK6`-n$r#(HTM}ewryJY-J_W)JRH0?|*-3(OKdRX^z>8j=m6^7C!
> zorjqt6iVm5_DtLLm-)>Kg_7@SyM8clNO}k1Ph3~VXf;`t@fKssB|pc_!-
> 61
> zb|^D2IPfbSNPA^C`4CeKhus8uh6(@w|DSBatS4~b
> (Cv;e|i4T|Nk!!PA+0L
> F0svn-S`YvL
> 
> delta 228
> zcmZo+U&1~?w%(Q5@W4)H1_lOQ1_1^JTOi|qQC#y+=2ErB3W2Hv#UZ878Y
> @Ij+n(|*
> zz1vtJu{U3CTIrR>3YpI5CbLRUzg7XNs(9MdQ+fcX%C<|!zjQlL)lAdQ#L{&@Rjr40
> zFPAQDu25kpo!@zwIYOay#_K@C1D?%48B6=pcKv0ZcvWh02cy!?K-
> ?lZ6>?F&0gJ
> z$GBd&=D%JVKcjfs4rK-g2Y#gkX|I$gZ(xcM^O+#eFya6I{}WKaWD#aPfdzkFGrj)y
> TlJ)<~^?&~Vf4O;b5VH{gPc~z_
> 
> diff --git
> a/UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.port80
> .raw
> b/UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.port80
> .raw
> index
> 51ad3ecde0e4e02e91ed299ec207e9f7460524b3..def0ec856d0d14b4ea11b0a
> 33db1512077eae00f 100644 GIT binary patch delta 296
> zcmZokXi3<>rckfTAi%(2%fP_!zbLY?LZIqEaY(6bV};0R+f%-!B8?Rid-LU{m2x*$
> z$aFq8nN`a4S_P=8;%QG$=~196+b$XZ(mg;`Gfg`aOE&{mwI0^JT)L{cLWQApN#
> |ka
> z2!+zQuX#6Yc-F9EKM-
> ^tef_WV=!T8Y8eUFfWMDA7J$br96r=g%PYP4a%Rc`9FTt=O
> z1t>QM=$;)67ykd}SGw`~=mxQ84Zn6XeCWHq`@~1RG=4_$v>nO}3=aHC2hv`x
> nY>p~
> zfzw5u;Q~ 6sc_<$BP(0$%`QZPv
> i2@^I7Zs1jTDfMXr2mozl2n%szm@wfbGeiU|JOKccERnVV
> 
> delta 270
> zcmZokXi3<>rcl3=nSp^pmqCDm!4}B)UliB;letu_u|lBgKygUvv)3&
> T
> zNbJp*n^t OHs*
> zn=4cpO6PYTW{yxOo$*@K@PKFYPsY-
> |4I7>{?AX75Kkxp|qp$yU9^J6 zj3$#GC`{q$`1t?71jB|DpzzGe4T=)Nw?68n@iU62?NDZ5aNt)ukoIcd T
> z4}fYXUs1H=d)@Hz!QcP?U*`M+5+;*nlq47@Y!qC;tMF3m(*zIzdXXV4#EoIXgqO
> k)
> I5wP$C0A)jcr~m)}
> 
> diff --git
> a/UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.raw
> b/UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.raw
> index
> eec88b1c9cbd2f87951762b6db2be79c8dd73656..cd6559018826fa74d39def
> 72a3d578628d2891f7 100644 GIT binary patch delta 290
> 

[edk2-devel][PATCH] UefiCpuPkg: Update BFV searching algorithm in VTF0

[Kuo, Ted]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3870
The new algorithm searches FFS3 GUID first and then FFS2 GUID at
every 4KB address in the top 16MB just below 4GB.

Cc: Ray Ni 
Cc: Debkumar De 
Cc: Harry Han 
Cc: Catharine West 
Cc: Min Xu 
Signed-off-by: Ted Kuo 
---
 .../Vtf0/Bin/IA32/ResetVector.ia32.port80.raw   | Bin 548 -> 532 bytes
 .../ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.raw  | Bin 516 -> 500 bytes
 .../Vtf0/Bin/IA32/ResetVector.ia32.serial.raw   | Bin 932 -> 900 bytes
 .../Bin/X64/PageTable1G/ResetVector.x64.port80.raw  | Bin 12292 -> 12292 bytes
 .../Vtf0/Bin/X64/PageTable1G/ResetVector.x64.raw| Bin 12292 -> 12292 bytes
 .../Bin/X64/PageTable1G/ResetVector.x64.serial.raw  | Bin 12292 -> 12292 bytes
 .../Bin/X64/PageTable2M/ResetVector.x64.port80.raw  | Bin 28676 -> 28676 bytes
 .../Vtf0/Bin/X64/PageTable2M/ResetVector.x64.raw| Bin 28676 -> 28676 bytes
 .../Bin/X64/PageTable2M/ResetVector.x64.serial.raw  | Bin 28676 -> 28676 bytes
 .../ResetVector/Vtf0/Ia32/SearchForBfvBase.asm  |  19 +--
 10 files changed, 5 insertions(+), 14 deletions(-)

diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw 
b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw
index 
23254e83bf1a17dee9f38c235fcc9948624a7536..a3601274c25dde665872ff375f1deadf1c838476
 100644
GIT binary patch
delta 190
zcmZ3&}9%{V6bIiVEA7Y*;pY^b)Yz;RJO4~e>a??t=
z8!KcwpPS4oWqPdwR8{e`r>FENP?c?$jDP7KpsJasor$HJfvQ>$>s~Hh)m)*%P`ae^
zFmr@L>D<@68#X*^*s*-2o*Lifq#%B#L8KWjnif8;k@l&;M&40Z#en#=M9m)(0
p4*W_7(q6?+ZeUbk^qjnqQF!tuMib78|1Z`5{r~@R;pF#>rU2NrRB!+Q

delta 211
zcmbQjvV^660uUG;*vZVmz@W<@z`$S)9RYyQbxs@7N`P<5a2DnL~gPkVYw4**r!cFFjcZU?HGY1)}sx(=wS^|0>c
z(xuH6Dh#FbI}bBQD3s24Eoykcv-u}uY2Sto!p|CZ><5C*qp$yU9^J6dOQg~Z-`xoM@`
zjTJJTYR}(^GmBsLHlW#=mqAP}NM+`WbuX8$YOYXWC|%Nd
zm^nhBbna`;9s7Zx^XTh;okw3fGBPk2-tN3Nabf`DyNQp=gu9|NoybVe$kLTf4OV)8Aly`5

delta 202
zcmeyu+`>{n0SF8a>||zOV9;d{U|_HXGX59EHUDHTRcoves5(#_Qu?g1LgcjVDc{n&
zjTI7m^W~3nW7tMv416`-n$r#(HT2Y{+C)y36^7FJorjqt6iR2j7BoEI+5D5Sv~S0L?*04scOHHHuk+|j`-v6djBh4hC>L(~
zub0NpD4w=MnSsH9U+F;FtK7*^j4~W{6XY2t{Qv)das#6oNB2vMfB*l#+%tI}qZt4b
C>RJ*2

diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.serial.raw 
b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.serial.raw
index 
e4aa4fc30a32bc3d4d8d0e1726c43fdafef4a374..48b46e3473e77a1179bf818a1f1deafb7e46cf3e
 100644
GIT binary patch
delta 206
zcmZ3&-oidXwqBLl@PICZ00V<90|UeVqR7SyfvN+=A*Hg76(Xl?Px+RLG*(FL&6k^2
z%H3EY)A`(FRw>hK6`-n$r#(HTM}ewryJY-J_W)JRH0?|*-3(OKdRX^z>8j=m6^7C!
zorjqt6iVm5_DtLLm-)>Kg_7@SyM8clNO}k1Ph3~VXf;`t@fKssB|pc_!-61
zb|^D2IPfbSNPA^C`4CeKhus8uh6(@w|DSBatS4~b(Cv;e|i4T|Nk!!PA+0L
F0svn-S`YvL

delta 228
zcmZo+U&1~?w%(Q5@W4)H1_lOQ1_1^JTOi|qQC#y+=2ErB3W2Hv#UZ878Y@Ij+n(|*
zz1vtJu{U3CTIrR>3YpI5CbLRUzg7XNs(9MdQ+fcX%C<|!zjQlL)lAdQ#L{&@Rjr40
zFPAQDu25kpo!@zwIYOay#_K@C1D?%48B6=pcKv0ZcvWh02cy!?K-?lZ6>?F&0gJ
z$GBd&=D%JVKcjfs4rK-g2Y#gkX|I$gZ(xcM^O+#eFya6I{}WKaWD#aPfdzkFGrj)y
TlJ)<~^?&~Vf4O;b5VH{gPc~z_

diff --git 
a/UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.port80.raw 
b/UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.port80.raw
index 
51ad3ecde0e4e02e91ed299ec207e9f7460524b3..def0ec856d0d14b4ea11b0a33db1512077eae00f
 100644
GIT binary patch
delta 296
zcmZokXi3<>rckfTAi%(2%fP_!zbLY?LZIqEaY(6bV};0R+f%-!B8?Rid-LU{m2x*$
z$aFq8nN`a4S_P=8;%QG$=~196+b$XZ(mg;`Gfg`aOE&{mwI0^JT)L{cLWQApN#|ka
z2!+zQuX#6Yc-F9EKM-^tef_WV=!T8Y8eUFfWMDA7J$br96r=g%PYP4a%Rc`9FTt=O
z1t>QM=$;)67ykd}SGw`~=mxQ84Zn6XeCWHq`@~1RG=4_$v>nO}3=aHC2hv`xnY>p~
zfzw5u;Q~rcl3=nSp^pmqCDm!4}B)UliB;letu_u|lBgKygUvv)3
zNbJp*n^t{?AX75Kkxp|qp$yU9^J6rckfTAi%(2%fP_!zbLY?LZIqEaY(6bV};0R+f%-!B8?Rid-LU{m2x*$
z$aFq8nN`a4S_P=8;%QG$=~196+b$XZ(mg;`Gfg`aOE&{mwI0^JT)L{cLWQApN#|ka
z2!+zQuQ_+@2ZGL{um5!(ec8pxz+ia0^IqqRwC-4g$rcl3=nSp^pmqCDm!4}B)UliB;letu_u|lBgKygUvv)3
zNbJp*n^tSd%lXob(@m2qS`Tp(
zR?6L2A=CNXWL7EDYZaiXil;q2rAL9PY`bLqOZNa(%{1*yEZq!L)p}U>a_Oq(3KfRZ
zC7p+vBNR=Mp^_Th03WbvIX}f+fZ%BFv;ZI(tP{w#@vZ~@O#y69crZBclo~q==
zC_4F$l8(lW(EcZT?PRL23sKGe^FfXPv%m!#tMO|1H~bw)R4PTQXH
zExp@VA+a}KZd#tNCv=O(jCPrp_Hs;YR}(^Gl?sLHlW#=mqsP}NM+`W
zbuX7LZLUyZD4pMVm^nhBbjIsI!vmhpKN(B=(suo2o_tk7YI297(?bK8yz@3oG7Y
zd^P!<;uOYdlbe;?7=ws9pHVz*hcW|$1HaONv{yEhHI-x7z10~OeE$D`
za-Xt|sK%eyOs~JaWc{LlaYFRlLqiMq}AmA`T;ynOX}0tf*8#t;_b#xP;R%gYcE
Huh!SMFv=?PJc=951qOffI}`2W8I
z!-f=~+#H~Lb}%|DRv!#_OXS#GW<$+RgBx@AmE!ANA7s8O76fC^IlP@GBiid$nfr
z-b4jX7j=dUKh!#EoIXgqO?^5wP$C0AK}^xBvhE

delta 272
zcmZp9z}WJDaRXaI{Z3{E1_oUQ0R{$JAme{gT=P%nQnkhkfvN+=A*Ih6D@0D)p7Jfd
z+gKs7H(zdA>6OL`na<}Xvr13DRspK2c-qrbdH|@(woAspbURShOw-Q9(se*pt%r3l
zmo9CtP+=+7ohLZNiVYf-}kp3OfQOZzr#c-F9E|Ni~F`#X=m{?~bQ!^UR~FZ(Aq
zB*ZhCOn#6sg{R}=|NjyU8(kTjsF%jiD4w=MnSsH9U+F;Ft9_GKCn~Tz
zsxv$Qs-1i#(UR|V!^;PM|NnoP^AAXvOqNNKV4Sc~Z~?EvORY~6Kmh1PhOiJfh6xj1
K3PVJ|!V>^C=zwYf

diff --git 
a/UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable2M/ResetVector.x64.raw 
b/UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable2M/ResetVector.x64.raw
index 

Re: [edk2-devel] [PATCH EDK2 v1 1/1] ArmPlatformPkg: Fix ECC issues

[wenyi,xie via groups.io]

Hi, Sami

Thank you for your reviewing, I have created a PR an here is the link.
https://github.com/tianocore/edk2/pull/2619

Regards
Wenyi

On 2022/3/14 18:13, Sami Mujawar wrote:
> Hi Wenyi,
> 
> Thank you for this patch. These changes look good to me.
> 
> Reviewed-by: Sami Mujawar 
> 
> Regards,
> 
> Sami Mujawar
> 
> On 14/03/2022, 09:26, "devel@edk2.groups.io on behalf of wenyi,xie via 
> groups.io"  
> wrote:
> 
> Fix header files on #ifdef.
> 
> Cc: Leif Lindholm 
> Cc: Ard Biesheuvel 
> 
> Signed-off-by: Wenyi Xie 
> ---
>  ArmPlatformPkg/Drivers/NorFlashDxe/NorFlash.h | 6 
> +++---
>  ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.h   | 6 
> +++---
>  ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.h   | 6 
> +++---
>  ArmPlatformPkg/Include/Library/ArmPlatformLib.h   | 4 
> ++--
>  ArmPlatformPkg/Include/Library/NorFlashPlatformLib.h  | 6 
> +++---
>  ArmPlatformPkg/Include/Library/PL011UartClockLib.h| 4 
> ++--
>  ArmPlatformPkg/Include/Library/PL011UartLib.h | 4 
> ++--
>  ArmPlatformPkg/Library/PL011UartLib/PL011Uart.h   | 4 
> ++--
>  ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClock.h | 4 
> ++--
>  ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.h| 6 
> +++---
>  ArmPlatformPkg/PrePeiCore/PrePeiCore.h| 4 
> ++--
>  ArmPlatformPkg/PrePi/PrePi.h  | 6 
> +++---
>  12 files changed, 30 insertions(+), 30 deletions(-)
> 
> diff --git a/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlash.h 
> b/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlash.h
> index c83032e87d9c..c8b567d0c413 100644
> --- a/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlash.h
> +++ b/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlash.h
> @@ -6,8 +6,8 @@
> 
>  **/
> 
> -#ifndef __NOR_FLASH_H__
> -#define __NOR_FLASH_H__
> +#ifndef NOR_FLASH_H_
> +#define NOR_FLASH_H_
> 
>  #include 
>  #include 
> @@ -419,4 +419,4 @@ NorFlashVirtualNotifyEvent (
>IN VOID   *Context
>);
> 
> -#endif /* __NOR_FLASH_H__ */
> +#endif // NOR_FLASH_H_
> diff --git a/ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.h 
> b/ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.h
> index 42d87a16a3dd..3117f0abe2b3 100644
> --- a/ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.h
> +++ b/ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.h
> @@ -6,8 +6,8 @@
> 
>  **/
> 
> -#ifndef __PL061_GPIO_H__
> -#define __PL061_GPIO_H__
> +#ifndef PL061_GPIO_H_
> +#define PL061_GPIO_H_
> 
>  #include 
> 
> @@ -39,4 +39,4 @@
>  // All bits low except one bit high, native bit length
>  #define GPIO_PIN_MASK(Pin)  (1UL << ((UINTN)(Pin)))
> 
> -#endif // __PL061_GPIO_H__
> +#endif // PL061_GPIO_H_
> diff --git a/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.h 
> b/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.h
> index 597d6911fa10..f6a332fda247 100644
> --- a/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.h
> +++ b/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.h
> @@ -6,8 +6,8 @@
> 
>  **/
> 
> -#ifndef __SP805_WATCHDOG_H__
> -#define __SP805_WATCHDOG_H__
> +#ifndef SP805_WATCHDOG_H_
> +#define SP805_WATCHDOG_H_
> 
>  // SP805 Watchdog Registers
>  #define SP805_WDOG_LOAD_REG ((UINT32)PcdGet32 
> (PcdSP805WatchdogBase) + 0x000)
> @@ -38,4 +38,4 @@
>  #define SP805_WDOG_LOCK_IS_LOCKED   0x0001
>  #define SP805_WDOG_SPECIAL_UNLOCK_CODE  0x1ACCE551
> 
> -#endif // __SP805_WATCHDOG_H__
> +#endif // SP805_WATCHDOG_H_
> diff --git a/ArmPlatformPkg/Include/Library/ArmPlatformLib.h 
> b/ArmPlatformPkg/Include/Library/ArmPlatformLib.h
> index cd87743eba52..cf056808fedf 100644
> --- a/ArmPlatformPkg/Include/Library/ArmPlatformLib.h
> +++ b/ArmPlatformPkg/Include/Library/ArmPlatformLib.h
> @@ -6,8 +6,8 @@
> 
>  **/
> 
> -#ifndef _ARMPLATFORMLIB_H_
> -#define _ARMPLATFORMLIB_H_
> +#ifndef ARMPLATFORMLIB_H_
> +#define ARMPLATFORMLIB_H_
> 
>  //
>  // The package level header files this module uses
> diff --git a/ArmPlatformPkg/Include/Library/NorFlashPlatformLib.h 
> b/ArmPlatformPkg/Include/Library/NorFlashPlatformLib.h
> index 6ef5b70e9948..37c0a69a6d07 100644
> --- a/ArmPlatformPkg/Include/Library/NorFlashPlatformLib.h
> +++ b/ArmPlatformPkg/Include/Library/NorFlashPlatformLib.h
> @@ -6,8 +6,8 @@
> 
>   **/
> 
> -#ifndef _NORFLASHPLATFORMLIB_H_
> -#define _NORFLASHPLATFORMLIB_H_
> +#ifndef NORFLASHPLATFORMLIB_H_
> +#define NORFLASHPLATFORMLIB_H_
> 
>  typedef struct {
>UINTNDeviceBaseAddress;   // Start address of the Device Base 
> Address (DBA)
> @@ -27,4 +27,4 @@ 

Re: [edk2-devel][PATCH v2] UefiCpuPkg: Support FFS3 GUID in SearchForBfvBase.asm

[Ni, Ray]

Ted, thank you for the fix in advance!

-Original Message-
From: Kuo, Ted  
Sent: Thursday, March 17, 2022 2:05 PM
To: Ni, Ray ; devel@edk2.groups.io
Cc: De, Debkumar ; Han, Harry ; 
West, Catharine ; Xu, Min M 
Subject: RE: [edk2-devel][PATCH v2] UefiCpuPkg: Support FFS3 GUID in 
SearchForBfvBase.asm

Hi Ray,

No, I'll send patch to update the searching algorithm.

Thanks,
Ted

-Original Message-
From: Ni, Ray 
Sent: Thursday, March 17, 2022 1:21 PM
To: devel@edk2.groups.io; Ni, Ray ; Kuo, Ted 

Cc: De, Debkumar ; Han, Harry ; 
West, Catharine ; Xu, Min M 
Subject: RE: [edk2-devel][PATCH v2] UefiCpuPkg: Support FFS3 GUID in 
SearchForBfvBase.asm

Ted,
Have you considered a case that BFV is a FFS2 FV and the logic may find a FFS3 
FV just below the BFV?

Thanks,
Ray

-Original Message-
From: devel@edk2.groups.io  On Behalf Of Ni, Ray
Sent: Friday, March 11, 2022 3:42 PM
To: Kuo, Ted ; devel@edk2.groups.io
Cc: De, Debkumar ; Han, Harry ; 
West, Catharine 
Subject: Re: [edk2-devel][PATCH v2] UefiCpuPkg: Support FFS3 GUID in 
SearchForBfvBase.asm

Reviewed-by: Ray Ni 

-Original Message-
From: Kuo, Ted 
Sent: Friday, March 11, 2022 3:29 PM
To: devel@edk2.groups.io
Cc: Ni, Ray ; De, Debkumar ; Han, 
Harry ; West, Catharine 
Subject: [edk2-devel][PATCH v2] UefiCpuPkg: Support FFS3 GUID in 
SearchForBfvBase.asm

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3862
The new algorithm searches BFV address with FFS3 GUID first.
If not found, it will search BFV address with FFS2 GUID.

Cc: Ray Ni 
Cc: Debkumar De 
Cc: Harry Han 
Cc: Catharine West 
Signed-off-by: Ted Kuo 
---
 .../Vtf0/Bin/IA32/ResetVector.ia32.port80.raw  | Bin 484 -> 548 bytes
 .../ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.raw | Bin 468 -> 516 bytes
 .../Vtf0/Bin/IA32/ResetVector.ia32.serial.raw  | Bin 868 -> 932 bytes
 .../Bin/X64/PageTable1G/ResetVector.x64.port80.raw | Bin 12292 -> 12292 bytes
 .../Vtf0/Bin/X64/PageTable1G/ResetVector.x64.raw   | Bin 12292 -> 12292 bytes
 .../Bin/X64/PageTable1G/ResetVector.x64.serial.raw | Bin 12292 -> 12292 bytes  
.../Bin/X64/PageTable2M/ResetVector.x64.port80.raw | Bin 28676 -> 28676 bytes
 .../Vtf0/Bin/X64/PageTable2M/ResetVector.x64.raw   | Bin 28676 -> 28676 bytes
 .../Bin/X64/PageTable2M/ResetVector.x64.serial.raw | Bin 28676 -> 28676 bytes
 .../ResetVector/Vtf0/Ia32/SearchForBfvBase.asm |  51 +
 10 files changed, 41 insertions(+), 10 deletions(-)

diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw 
b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw
index 
79b23c047bdc6e552d77d5c9e9aeae21ff04d91d..23254e83bf1a17dee9f38c235fcc9948624a7536
 100644 GIT binary patch delta 227 
zcmaFDyo9BG0uUG;*vZVmz@W<@z`$S)9RYyQbxs@7N`P<5a2DnL~gPkVYw4**r!cFFjcZU?HGY1)}sx(=wS^|0>c
z(xuH6Dh#FbI}bBQD3s24Eoykcv-u}uY2Sto!p|CZ><5C*qp$yU9^J6;8$wu(9TV=}(c8
zUjg)y@_Q48|1M?^0T*VtBLDzE4S>dJ0U!uIkRJe$|NsA!umLp*>x1c7{{R2!
Mtds8n6_W!3A^UepbpQYW

diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.raw 
b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.raw
index 
ce7faa502b858e99908bcdb397b776258205e1d5..18562d8f1f58601f66fcb0cbf2f994046ce48fde
 100644 GIT binary patch delta 225 
zcmcb@+`>{n0SF8a>||zOV9;d{U|_HXGX59EHUDHTRcoves5(#_Qu?g1LgcjVDc{n&
zjTI7m^W~3nW7tMv416`-n$r#(HT2Y{+C)y36^7FJorjqt6iR2j7BoEI+5D5Sv~S0L?*04scOHHHuk+|j`-wr}jBh5cDmQQY
zub0NpD4w=MnSsH9U+F;FtK9$p{|hkeaA0F#;8%K(wu6JA??`Yyb-n;_3H
Z0jOYd0;3s6_e+a^|Np<-GkG4P833r5W}5&2

delta 153
zcmZo+xxySY0SF8a=rRZ}FxWCMF#InvZmbZfc-qrb`ns_~#I{Suzw}XKg~UwL
zjTJJjhjlNPUTCgRVJJP-d6+puq4e-;>)Kp!4YKf1O8Px=-v1XZ$kpQMqv4f4ww*
zM)9;A$_xw+{7MJXUZqaXVU!VYn;_3H;s5{tAge)O@^>vc|Nj4fxn=S>Ml%58
CZbm==

diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.serial.raw 
b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.serial.raw
index 
6503a988abdac06f9aa88f0a65f2525e12233b0a..e4aa4fc30a32bc3d4d8d0e1726c43fdafef4a374
 100644 GIT binary patch delta 214 
zcmaFDwuF6xY`rV9;enmZ3=9mq3<3-cwm`=JqPXUt%%y6L6#`WUibG1DHCBk6wms!r
zdbhDcVsF0Ow9+e$6*8UAO=gvzeysvjRq?c^r}O|=df9ZChs+p#piKXj+s#*{0
zUM^kQT%p2HI=}NUbA&?ajMssN2Rxg9GM4tG?fT0+F{OjiW8`AFs>J_`LCD8
z@Lz#iWfnVuB+AHPBT}&|oJ`>~_Cj9^Ze*zRte#c}Yu;9;Yrq|zIvi^U${?Gsa
LFE>v%Vm1N**#ci0

delta 146
zcmV;D0B!%I2jm8j9YX~JF~BVV5C8x@00030ax;N=5P0Q`jCJdQcoaQ~98Y!Pfp{31
zHHl$$*@1W*g~Kh=brcl3=nSp^pmqCDm!4}B)UliB;letu_u|lBgKygUvv)3
zNbJp*n^t{?AX75Kkxp|qp$yU9^J6Bj4$8^oS9{Mya%q3`zYTOak(_!-61
zb|^D2IPfbSNPD$!a;u^OyQ4b81EBWFTNEw%UN^ja@b~}!mpT7{gvsPTiV}

delta 259
zcmZokXi3<>rVygbAi%(2%fP_!zsR_;LZISlPfzLV#tISJE*byQM~xK{Gfg`aOK
z$h02Tysxk81Z^i=0z<_Lw-!>@TaY`>8ANp?ZUi48fjh|6GZHF=g
zg9E?PfwWg`llLkr@O!Brcl3=nSp^pmqCDm!4}B)UliB;letu_u|lBgKygUvv)3
zNbJp*n^tq;e#OWC
z|0Nh+`|M`_}ygvDBH^Ya%+q?ID)Jx-M6i?fs%)sEluXG^o)w0RCiZc9u
z>I@fv+9p83MyJRzkL7q|Noc8|A2(?|NsAY0P%kh#bX|dM?DmecyvDa|7^m9
eje;9^6<$hx0&4}@$q*Le#xP;ROJ;}$oEHj+dD

delta 239
zcmZokXi3<>rr@K?Ai%(2%fP_!zsR_;LZISlPfzLV#tISJE*byQM~xK{Gfg`aOK

[edk2-devel] [PATCH 1/2] BaseTools: TEST ONLY1 FeatureFlagExpression

[yi1 li]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1446

FeatureFlagExpression Support in LibraryClasses/Guids/Ppi/Protocols
section of INF file. The Pcd value in the expression is from INF or DEC
When a FeatureFlagExpression is present,if the expression evaluates
to TRUE,then the entry is valid. If the expression evaluates to FALSE,
then the EDK II build tools must ignore the entry.

This patch is going to add this feature.

Signed-off-by: yi1 li 
---
 BaseTools/Source/Python/Common/Expression.py  |  2 +-
 BaseTools/Source/Python/Common/GlobalData.py  |  1 +
 .../Source/Python/Workspace/InfBuildData.py   | 67 +--
 .../Python/Workspace/WorkspaceCommon.py   | 10 ++-
 4 files changed, 72 insertions(+), 8 deletions(-)

diff --git a/BaseTools/Source/Python/Common/Expression.py 
b/BaseTools/Source/Python/Common/Expression.py
index 07ca039a9cf3..31bf0e4b6cf7 100644
--- a/BaseTools/Source/Python/Common/Expression.py
+++ b/BaseTools/Source/Python/Common/Expression.py
@@ -43,7 +43,7 @@ ERR_IN_OPERAND  = 'Macro after IN operator can only 
be: $(FAMILY), $(ARC
 __ValidString = re.compile(r'[_a-zA-Z][_0-9a-zA-Z]*$')
 _ReLabel = re.compile('LABEL\((\w+)\)')
 _ReOffset = re.compile('OFFSET_OF\((\w+)\)')
-PcdPattern = re.compile(r'[_a-zA-Z][0-9A-Za-z_]*\.[_a-zA-Z][0-9A-Za-z_]*$')
+PcdPattern = re.compile(r'^[_a-zA-Z][0-9A-Za-z_]*\.[_a-zA-Z][0-9A-Za-z_]*$')
 
 ## SplitString
 #  Split string to list according double quote
diff --git a/BaseTools/Source/Python/Common/GlobalData.py 
b/BaseTools/Source/Python/Common/GlobalData.py
index 61ab3f7e24cd..197bd8366682 100755
--- a/BaseTools/Source/Python/Common/GlobalData.py
+++ b/BaseTools/Source/Python/Common/GlobalData.py
@@ -18,6 +18,7 @@ gGlobalDefines = {}
 gPlatformDefines = {}
 # PCD name and value pair for fixed at build and feature flag
 gPlatformPcds = {}
+gPlatformFinalPcds = {}
 # PCDs with type that are not fixed at build and feature flag
 gPlatformOtherPcds = {}
 gActivePlatform = None
diff --git a/BaseTools/Source/Python/Workspace/InfBuildData.py 
b/BaseTools/Source/Python/Workspace/InfBuildData.py
index 45b8ef4716dd..91d986d8cb1b 100644
--- a/BaseTools/Source/Python/Workspace/InfBuildData.py
+++ b/BaseTools/Source/Python/Workspace/InfBuildData.py
@@ -14,6 +14,7 @@ from types import *
 from .MetaFileParser import *
 from collections import OrderedDict
 from Workspace.BuildClassObject import ModuleBuildClassObject, 
LibraryClassObject, PcdClassObject
+from Common.Expression import ValueExpressionEx, PcdPattern
 
 ## Get Protocol value from given packages
 #
@@ -554,6 +555,9 @@ class InfBuildData(ModuleBuildClassObject):
 Instance = Record[1]
 if Instance:
 Instance = NormPath(Instance, self._Macros)
+FeaturePcdExpression = self.CheckFeatureFlagPcd(Instance)
+if not FeaturePcdExpression:
+continue
 RetVal[Lib] = Instance
 else:
 RetVal[Lib] = None
@@ -584,6 +588,10 @@ class InfBuildData(ModuleBuildClassObject):
 self._ProtocolComments = OrderedDict()
 RecordList = self._RawData[MODEL_EFI_PROTOCOL, self._Arch, 
self._Platform]
 for Record in RecordList:
+if Record[1]:
+FeaturePcdExpression = self.CheckFeatureFlagPcd(Record[1])
+if not FeaturePcdExpression:
+continue
 CName = Record[0]
 Value = _ProtocolValue(CName, self.Packages, self.MetaFile.Path)
 if Value is None:
@@ -608,6 +616,10 @@ class InfBuildData(ModuleBuildClassObject):
 self._PpiComments = OrderedDict()
 RecordList = self._RawData[MODEL_EFI_PPI, self._Arch, self._Platform]
 for Record in RecordList:
+if Record[1]:
+FeaturePcdExpression = self.CheckFeatureFlagPcd(Record[1])
+if not FeaturePcdExpression:
+continue
 CName = Record[0]
 Value = _PpiValue(CName, self.Packages, self.MetaFile.Path)
 if Value is None:
@@ -631,7 +643,12 @@ class InfBuildData(ModuleBuildClassObject):
 RetVal = OrderedDict()
 self._GuidComments = OrderedDict()
 RecordList = self._RawData[MODEL_EFI_GUID, self._Arch, self._Platform]
+RetVal.update(self.GetGuidsUsedByPcd())
 for Record in RecordList:
+if Record[1]:
+FeaturePcdExpression = self.CheckFeatureFlagPcd(Record[1])
+if not FeaturePcdExpression:
+continue
 CName = Record[0]
 Value = GuidValue(CName, self.Packages, self.MetaFile.Path)
 if Value is None:
@@ -860,7 +877,12 @@ class InfBuildData(ModuleBuildClassObject):
 def GetGuidsUsedByPcd(self):
 self.Guid
 return self._GuidsUsedByPcd
-
+@cached_class_function
+def GetGuidDict(self):
+GuidDict = OrderedDict()
+for Package in self.Packages:
+

[edk2-devel] [PATCH 2/2] BaseTools: TEST ONLY2 FeatureFlagExpression

[yi1 li]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1446

FeatureFlagExpression Support in Source section of INF file. The Pcd
value in the expression is from INF or DEC.
When a FeatureFlagExpression is present,if the expression evaluates
to TRUE,then the entry is valid. If the expression evaluates to FALSE,
then the EDK II build tools must ignore the entry.

This patch is going to add this feature.

Signed-off-by: yi1 li 
---
 BaseTools/Source/Python/Workspace/InfBuildData.py  | 14 ++
 .../Source/Python/Workspace/MetaFileParser.py  |  4 
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/BaseTools/Source/Python/Workspace/InfBuildData.py 
b/BaseTools/Source/Python/Workspace/InfBuildData.py
index 91d986d8cb1b..cb58e612cbd0 100644
--- a/BaseTools/Source/Python/Workspace/InfBuildData.py
+++ b/BaseTools/Source/Python/Workspace/InfBuildData.py
@@ -529,11 +529,17 @@ class InfBuildData(ModuleBuildClassObject):
 for Record in RecordList:
 LineNo = Record[-1]
 ToolChainFamily = Record[1]
-TagName = Record[2]
-ToolCode = Record[3]
-
+# OptionsList := [TagName, ToolCode, FeatureFlag]
+OptionsList = ['','','']
+TokenList = GetSplitValueList(Record[2], TAB_VALUE_SPLIT)
+for Index in range(len(TokenList)):
+OptionsList[Index] = TokenList[Index]
+if OptionsList[2]:
+FeaturePcdExpression = self.CheckFeatureFlagPcd(OptionsList[2])
+if not FeaturePcdExpression:
+continue
 File = PathClass(NormPath(Record[0], Macros), self._ModuleDir, '',
- '', False, self._Arch, ToolChainFamily, '', 
TagName, ToolCode)
+ '', False, self._Arch, ToolChainFamily, '', 
OptionsList[0], OptionsList[1])
 # check the file validation
 ErrorCode, ErrorInfo = File.Validate()
 if ErrorCode != 0:
diff --git a/BaseTools/Source/Python/Workspace/MetaFileParser.py 
b/BaseTools/Source/Python/Workspace/MetaFileParser.py
index a3b6edbd15ee..3508591b281e 100644
--- a/BaseTools/Source/Python/Workspace/MetaFileParser.py
+++ b/BaseTools/Source/Python/Workspace/MetaFileParser.py
@@ -736,6 +736,10 @@ class InfParser(MetaFileParser):
 @ParseMacro
 def _SourceFileParser(self):
 TokenList = GetSplitValueList(self._CurrentLine, TAB_VALUE_SPLIT)
+# Let TokenList[2] be TagName|ToolCode|FeatureFlag
+if len(TokenList) > 3:
+for extraToken in range(3, len(TokenList)):
+TokenList[2] = TokenList[2] + '|' + TokenList[extraToken]
 self._ValueList[0:len(TokenList)] = TokenList
 Macros = self._Macros
 # For Acpi tables, remove macro like ' TABLE_NAME=Sata1'
-- 
2.33.0.windows.2



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[edk2-devel] [PATCH 0/2] BaseTools: TEST ONLY0 FeatureFlagExpression

[yi1 li]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1446

FeatureFlagExpression Support in LibraryClasses/Guids/Ppi/Protocols/
Source section of INF file. The Pcd value in the expression is from 
INF or DEC When a FeatureFlagExpression is present,if the expression
evaluates to TRUE,then the entry is valid. If the expression evaluates
to FALSE, then the EDK II build tools must ignore the entry.

This patch is going to add this feature.

Signed-off-by: yi1 li 

yi1 li (2):
  BaseTools:Add the FeatureFlagExpression usage to the InfBuildData
  BaseTools:Add the FeatureFlagExpression usage to the Source Section

 BaseTools/Source/Python/Common/Expression.py  |  2 +-
 BaseTools/Source/Python/Common/GlobalData.py  |  1 +
 .../Source/Python/Workspace/InfBuildData.py   | 81 ---
 .../Source/Python/Workspace/MetaFileParser.py |  4 +
 .../Python/Workspace/WorkspaceCommon.py   | 10 ++-
 5 files changed, 86 insertions(+), 12 deletions(-)

-- 
2.33.0.windows.2



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Re: [edk2-devel][PATCH v2] UefiCpuPkg: Support FFS3 GUID in SearchForBfvBase.asm

[Kuo, Ted]

Hi Ray,

No, I'll send patch to update the searching algorithm.

Thanks,
Ted

-Original Message-
From: Ni, Ray  
Sent: Thursday, March 17, 2022 1:21 PM
To: devel@edk2.groups.io; Ni, Ray ; Kuo, Ted 

Cc: De, Debkumar ; Han, Harry ; 
West, Catharine ; Xu, Min M 
Subject: RE: [edk2-devel][PATCH v2] UefiCpuPkg: Support FFS3 GUID in 
SearchForBfvBase.asm

Ted,
Have you considered a case that BFV is a FFS2 FV and the logic may find a FFS3 
FV just below the BFV?

Thanks,
Ray

-Original Message-
From: devel@edk2.groups.io  On Behalf Of Ni, Ray
Sent: Friday, March 11, 2022 3:42 PM
To: Kuo, Ted ; devel@edk2.groups.io
Cc: De, Debkumar ; Han, Harry ; 
West, Catharine 
Subject: Re: [edk2-devel][PATCH v2] UefiCpuPkg: Support FFS3 GUID in 
SearchForBfvBase.asm

Reviewed-by: Ray Ni 

-Original Message-
From: Kuo, Ted 
Sent: Friday, March 11, 2022 3:29 PM
To: devel@edk2.groups.io
Cc: Ni, Ray ; De, Debkumar ; Han, 
Harry ; West, Catharine 
Subject: [edk2-devel][PATCH v2] UefiCpuPkg: Support FFS3 GUID in 
SearchForBfvBase.asm

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3862
The new algorithm searches BFV address with FFS3 GUID first.
If not found, it will search BFV address with FFS2 GUID.

Cc: Ray Ni 
Cc: Debkumar De 
Cc: Harry Han 
Cc: Catharine West 
Signed-off-by: Ted Kuo 
---
 .../Vtf0/Bin/IA32/ResetVector.ia32.port80.raw  | Bin 484 -> 548 bytes
 .../ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.raw | Bin 468 -> 516 bytes
 .../Vtf0/Bin/IA32/ResetVector.ia32.serial.raw  | Bin 868 -> 932 bytes
 .../Bin/X64/PageTable1G/ResetVector.x64.port80.raw | Bin 12292 -> 12292 bytes
 .../Vtf0/Bin/X64/PageTable1G/ResetVector.x64.raw   | Bin 12292 -> 12292 bytes
 .../Bin/X64/PageTable1G/ResetVector.x64.serial.raw | Bin 12292 -> 12292 bytes  
.../Bin/X64/PageTable2M/ResetVector.x64.port80.raw | Bin 28676 -> 28676 bytes
 .../Vtf0/Bin/X64/PageTable2M/ResetVector.x64.raw   | Bin 28676 -> 28676 bytes
 .../Bin/X64/PageTable2M/ResetVector.x64.serial.raw | Bin 28676 -> 28676 bytes
 .../ResetVector/Vtf0/Ia32/SearchForBfvBase.asm |  51 +
 10 files changed, 41 insertions(+), 10 deletions(-)

diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw 
b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw
index 
79b23c047bdc6e552d77d5c9e9aeae21ff04d91d..23254e83bf1a17dee9f38c235fcc9948624a7536
 100644 GIT binary patch delta 227 
zcmaFDyo9BG0uUG;*vZVmz@W<@z`$S)9RYyQbxs@7N`P<5a2DnL~gPkVYw4**r!cFFjcZU?HGY1)}sx(=wS^|0>c
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Mtds8n6_W!3A^UepbpQYW

diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.raw 
b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.raw
index 
ce7faa502b858e99908bcdb397b776258205e1d5..18562d8f1f58601f66fcb0cbf2f994046ce48fde
 100644 GIT binary patch delta 225 
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Z0jOYd0;3s6_e+a^|Np<-GkG4P833r5W}5&2

delta 153
zcmZo+xxySY0SF8a=rRZ}FxWCMF#InvZmbZfc-qrb`ns_~#I{Suzw}XKg~UwL
zjTJJjhjlNPUTCgRVJJP-d6+puq4e-;>)Kp!4YKf1O8Px=-v1XZ$kpQMqv4f4ww*
zM)9;A$_xw+{7MJXUZqaXVU!VYn;_3H;s5{tAge)O@^>vc|Nj4fxn=S>Ml%58
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diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.serial.raw 
b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.serial.raw
index 
6503a988abdac06f9aa88f0a65f2525e12233b0a..e4aa4fc30a32bc3d4d8d0e1726c43fdafef4a374
 100644 GIT binary patch delta 214 
zcmaFDwuF6xY`rV9;enmZ3=9mq3<3-cwm`=JqPXUt%%y6L6#`WUibG1DHCBk6wms!r
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LFE>v%Vm1N**#ci0

delta 146
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zHHl$$*@1W*g~Kh=brcl3=nSp^pmqCDm!4}B)UliB;letu_u|lBgKygUvv)3
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delta 259
zcmZokXi3<>rVygbAi%(2%fP_!zsR_;LZISlPfzLV#tISJE*byQM~xK{Gfg`aOK
z$h02Tysxk81Z^i=0z<_Lw-!>@TaY`>8ANp?ZUi48fjh|6GZHF=g
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delta 239
zcmZokXi3<>rr@K?Ai%(2%fP_!zsR_;LZISlPfzLV#tISJE*byQM~xK{Gfg`aOK
z$h02Tysxk81Z^i=0z<_Lw-!>>7a><5C*qp$yU9(`Fqxl19OQD^cag(*P}AOHWC
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e54;L5Z+)Bq0zms1!b02_CQNvF7$O1|o$orgJI)

diff --git 
a/UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.serial.raw