Re: [edk2-devel] [PATCH v4 2/2] IntelFsp2WrapperPkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention

[Chiu, Chasel]

Thanks Chinni!
Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Duggapu, Chinni B 
> Sent: Tuesday, May 17, 2022 1:07 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Zeng, Star ; S,
> Ashraf Ali 
> Subject: [PATCH v4 2/2] IntelFsp2WrapperPkg: FSP_TEMP_RAM_INIT call
> must follow X64 Calling Convention
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
> Pass Input parameters using RCX.
> 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Star Zeng 
> Cc: Ashraf Ali S 
> Signed-off-by: cbduggap 
> ---
>  .../SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm   | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git
> a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64
> /SecEntry.nasm
> b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64
> /SecEntry.nasm
> index dbbf63336e..065d80d0e2 100644
> ---
> a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64
> /SecEntry.nasm
> +++
> b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64
> /SecEntry.nasm
> @@ -130,6 +130,9 @@ FspHeaderFound:
>mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]
> 
>add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
> 
> 
> 
> +  ; Pass Fsp T Udp pointer as Input parameter
> 
> +  mov rcx, ASM_PFX(FsptUpdDataPtr)
> 
> +
> 
>; Setup the hardcode stack
> 
>mov rsp, TempRamInitStack
> 
> 
> 
> @@ -167,5 +170,4 @@ FspApiFailed:
>  align 10h
> 
>  TempRamInitStack:
> 
>  DQ  TempRamInitDone
> 
> -DQ  ASM_PFX(FsptUpdDataPtr) ; TempRamInitParams
> 
> 
> 
> --
> 2.36.0.windows.1



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Re: [edk2-devel] [PATCH v4 1/2] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention

[Chiu, Chasel]

Thanks Chinni!
Reviewed-by: Chasel Chiu 


> -Original Message-
> From: Duggapu, Chinni B 
> Sent: Tuesday, May 17, 2022 1:07 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Zeng, Star ; S,
> Ashraf Ali 
> Subject: [PATCH v4 1/2] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must
> follow X64 Calling Convention
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
> This API accept one parameter using RCX and this is consumed in mutiple
> sub functions.
> 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Star Zeng 
> Cc: Ashraf Ali S 
> Signed-off-by: cbduggap 
> ---
>  IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 39 ++-
>  .../Include/SaveRestoreSseAvxNasm.inc | 28 +
>  2 files changed, 48 insertions(+), 19 deletions(-)
> 
> diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> index a9f5f28ed7..22dbea1fed 100644
> --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> @@ -114,7 +114,7 @@ endstruc
>  global ASM_PFX(LoadMicrocodeDefault)
> ASM_PFX(LoadMicrocodeDefault):; Inputs:-   ;   rsp ->
> LoadMicrocodeParams pointer+   ;   rcx -> LoadMicrocodeParams pointer;
> Register Usage:;   rsp  Preserved;   All others destroyed@@ -130,10
> +130,9 @@ ASM_PFX(LoadMicrocodeDefault):
>  cmprsp, 0jz ParamError-   moveax, dword [rsp + 8];
> Parameter pointer-   cmpeax, 0+   cmprcx, 0jz ParamError-   
> mov
> esp, eax+   movrsp, rcx ; skip loading Microcode if the
> MicrocodeCodeSize is zero; and report error if size is less than 2k@@ -
> 144,14 +143,14 @@ ASM_PFX(LoadMicrocodeDefault):
> jneParamError ; UPD structure is compliant with FSP spec 2.4-   
> mov
> eax, dword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]-   cmp
> eax, 0+   movrax, qword [rsp +
> LoadMicrocodeParamsFsp24.MicrocodeCodeSize]+   cmprax, 0jz
> Exit2-   cmpeax, 0800h+   cmprax, 0800hjl ParamError -   mov  
>   esi,
> dword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]-   cmpesi,
> 0+   movrsi, qword [rsp +
> LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]+   cmprsi, 0jnz
> CheckMainHeader  ParamError:@@ -256,7 +255,8 @@ CheckAddress:
> ; UPD structure is compliant with FSP spec 2.4; Is automatic size
> detection ?mov   rax, qword [rsp +
> LoadMicrocodeParamsFsp24.MicrocodeCodeSize]-   cmp   rax,
> 0h+   cmp   rcx, 0h+   cmp   rax, rcxjz
> LoadMicrocodeDefault4 ; Address >= microcode region address +
> microcode region size?@@ -321,8 +321,7 @@
> ASM_PFX(EstablishStackFsp):
>;   ; Save parameter pointer in rdx   ;-  mov   rdx, qword [rsp + 8]-+ 
>  mov
> rdx, rcx   ;   ; Enable FSP STACK   ;@@ -420,7 +419,10 @@
> ASM_PFX(TempRamInitApi):
>;   ENABLE_SSE   ENABLE_AVX-+  ;+  ; Save Input Parameter in YMM10+  ;+
> SAVE_RCX   ;   ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and
> YMM6   ;@@ -442,9 +444,8 @@ ASM_PFX(TempRamInitApi):
>;   ; Check Parameter   ;-  mov   rax, qword [rsp + 8]-  cmp   
> rax, 0-
> mov   rax, 08002h+  cmp   rcx, 0+  mov   rcx,
> 08002h   jzTempRamInitExit;@@ -455,18 +456,18
> @@ ASM_PFX(TempRamInitApi):
>jnz   TempRamInitExit; Load microcode-  LOAD_RSP+  LOAD_RCX
> CALL_YMM  ASM_PFX(LoadMicrocodeDefault)   SAVE_UCODE_STATUS
> rax ; Save microcode return status in SLOT 0 in YMM9 (upper
> 128bits).   ; @note If return value rax is not 0, microcode did not load, but
> continue and attempt to boot.; Call Sec CAR Init-  LOAD_RSP+  LOAD_RCX
> CALL_YMM  ASM_PFX(SecCarInit)   cmp   rax, 0   jnz   TempRamInitExit
> -  LOAD_RSP+  LOAD_RCX   CALL_YMM  ASM_PFX(EstablishStackFsp)   cmp
> rax, 0   jnz   TempRamInitExitdiff --git
> a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
> b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
> index e8bd91669d..38c807a311 100644
> --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
> +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
> @@ -177,6 +177,30 @@
>  LXMMN   xmm5, %1, 1 %endmacro +;+; Upper half of
> YMM10 to save/restore RCX+;+;+; Save RCX to YMM10[128:191]+;
> Modified: XMM5 and YMM10+;++%macro SAVE_RCX 0+LYMMN
> ymm10, xmm5, 1+SXMMN   xmm5, 0, rcx+SYMMN   ymm10,
> 1, xmm5+%endmacro++;+; Restore RCX from YMM10[128:191]+;
> Modified: XMM5 and RCX+;++%macro LOAD_RCX 0+LYMMN
> ymm10, xmm5, 1+movqrcx,  xmm5+%endmacro+ ; ;
> YMM7[128:191] for calling stack ; arg 1:Entry@@ -231,6 +255,7 @@
> NextAddress:
>  ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to
> test ; whether the processor supports SSE instruction.
>  ;+
> mov r10, rcx mov rax, 

回复: 回复: 回复: [edk2-devel] [PATCH v5 0/8] Add Variable Flash Info HOB

[gaoliming]

Michael:
  Yes. I can. Where is the change for Edk2?

Thanks
Liming
> -邮件原件-
> 发件人: Michael Kubacki 
> 发送时间: 2022年5月17日 12:14
> 收件人: devel@edk2.groups.io; a...@kernel.org
> 抄送: gaoliming ; Abner Chang
> ; Andrew Fish ; Anthony Perard
> ; Ard Biesheuvel ;
> Benjamin You ; Brijesh Singh
> ; Erdem Aktas ; Gerd
> Hoffmann ; Guo Dong ; Hao A
> Wu ; James Bottomley ; Jian J
> Wang ; Jiewen Yao ; Jordan
> Justen ; Julien Grall ; Leif
> Lindholm ; Maurice Ma
> ; Min Xu ; Nickle Wang
> ; Peter Grehan ; Ray Ni
> ; Rebecca Cran ; Sami Mujawar
> ; Sean Rhodes ;
> Sebastien Boeuf ; Tom Lendacky
> 
> 主题: Re: 回复: 回复: [edk2-devel] [PATCH v5 0/8] Add Variable Flash Info
> HOB
> 
> Liming, will you push both?
> 
> I put a rebased edk2-platforms with all the review tags for that series
> here:
> https://github.com/makubacki/edk2-platforms/commits/add_variableflashinf
> olib_to_platforms
> 
> Thanks,
> Michael
> 
> On 5/16/2022 1:36 PM, Ard Biesheuvel wrote:
> > On Mon, 16 May 2022 at 17:27, Michael Kubacki
> >  wrote:
> >>
> >> Yes, it has been reviewed by all maintainers. An announcement of the
> >> change was sent to edk2 on April 29th:
> >> https://edk2.groups.io/g/announce/message/291
> >>
> >> The series for edk2-platforms has also been out since April 25th:
> >> https://edk2.groups.io/g/devel/message/89308
> >>
> >> Thanks,
> >> Michael
> >>
> >
> > I am fine with merging this as is, but please merge the edk2-platforms
> > changes as soon as the edk2 changes are in, so platforms there are not
> > left in a broken state.
> >
> >
> > 
> >




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[edk2-devel] [PATCH v4 2/2] IntelFsp2WrapperPkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention

[cbduggap]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
Pass Input parameters using RCX.

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Ashraf Ali S 
Signed-off-by: cbduggap 
---
 .../SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm   | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git 
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm
 
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm
index dbbf63336e..065d80d0e2 100644
--- 
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm
+++ 
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm
@@ -130,6 +130,9 @@ FspHeaderFound:
   mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]
   add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
 
+  ; Pass Fsp T Udp pointer as Input parameter
+  mov rcx, ASM_PFX(FsptUpdDataPtr)
+
   ; Setup the hardcode stack
   mov rsp, TempRamInitStack
 
@@ -167,5 +170,4 @@ FspApiFailed:
 align 10h
 TempRamInitStack:
 DQ  TempRamInitDone
-DQ  ASM_PFX(FsptUpdDataPtr) ; TempRamInitParams
 
-- 
2.36.0.windows.1



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[edk2-devel] [PATCH v4 1/2] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention

[cbduggap]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
This API accept one parameter using RCX and this is consumed
in mutiple sub functions.

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Ashraf Ali S 
Signed-off-by: cbduggap 
---
 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 39 ++-
 .../Include/SaveRestoreSseAvxNasm.inc | 28 +
 2 files changed, 48 insertions(+), 19 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm 
b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
index a9f5f28ed7..22dbea1fed 100644
--- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
@@ -114,7 +114,7 @@ endstruc
 global ASM_PFX(LoadMicrocodeDefault)
 ASM_PFX(LoadMicrocodeDefault):
; Inputs:
-   ;   rsp -> LoadMicrocodeParams pointer
+   ;   rcx -> LoadMicrocodeParams pointer
; Register Usage:
;   rsp  Preserved
;   All others destroyed
@@ -130,10 +130,9 @@ ASM_PFX(LoadMicrocodeDefault):
 
cmprsp, 0
jz ParamError
-   moveax, dword [rsp + 8]; Parameter pointer
-   cmpeax, 0
+   cmprcx, 0
jz ParamError
-   movesp, eax
+   movrsp, rcx
 
; skip loading Microcode if the MicrocodeCodeSize is zero
; and report error if size is less than 2k
@@ -144,14 +143,14 @@ ASM_PFX(LoadMicrocodeDefault):
jneParamError
 
; UPD structure is compliant with FSP spec 2.4
-   moveax, dword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
-   cmpeax, 0
+   movrax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
+   cmprax, 0
jz Exit2
-   cmpeax, 0800h
+   cmprax, 0800h
jl ParamError
 
-   movesi, dword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]
-   cmpesi, 0
+   movrsi, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]
+   cmprsi, 0
jnzCheckMainHeader
 
 ParamError:
@@ -256,7 +255,8 @@ CheckAddress:
; UPD structure is compliant with FSP spec 2.4
; Is automatic size detection ?
mov   rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
-   cmp   rax, 0h
+   cmp   rcx, 0h
+   cmp   rax, rcx
jzLoadMicrocodeDefault4
 
; Address >= microcode region address + microcode region size?
@@ -321,8 +321,7 @@ ASM_PFX(EstablishStackFsp):
   ;
   ; Save parameter pointer in rdx
   ;
-  mov   rdx, qword [rsp + 8]
-
+  mov   rdx, rcx
   ;
   ; Enable FSP STACK
   ;
@@ -420,7 +419,10 @@ ASM_PFX(TempRamInitApi):
   ;
   ENABLE_SSE
   ENABLE_AVX
-
+  ;
+  ; Save Input Parameter in YMM10
+  ;
+  SAVE_RCX
   ;
   ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6
   ;
@@ -442,9 +444,8 @@ ASM_PFX(TempRamInitApi):
   ;
   ; Check Parameter
   ;
-  mov   rax, qword [rsp + 8]
-  cmp   rax, 0
-  mov   rax, 08002h
+  cmp   rcx, 0
+  mov   rcx, 08002h
   jzTempRamInitExit
 
   ;
@@ -455,18 +456,18 @@ ASM_PFX(TempRamInitApi):
   jnz   TempRamInitExit
 
   ; Load microcode
-  LOAD_RSP
+  LOAD_RCX
   CALL_YMM  ASM_PFX(LoadMicrocodeDefault)
   SAVE_UCODE_STATUS rax ; Save microcode return status in SLOT 0 
in YMM9 (upper 128bits).
   ; @note If return value rax is not 0, microcode did not load, but continue 
and attempt to boot.
 
   ; Call Sec CAR Init
-  LOAD_RSP
+  LOAD_RCX
   CALL_YMM  ASM_PFX(SecCarInit)
   cmp   rax, 0
   jnz   TempRamInitExit
 
-  LOAD_RSP
+  LOAD_RCX
   CALL_YMM  ASM_PFX(EstablishStackFsp)
   cmp   rax, 0
   jnz   TempRamInitExit
diff --git a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc 
b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
index e8bd91669d..38c807a311 100644
--- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
+++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
@@ -177,6 +177,30 @@
 LXMMN   xmm5, %1, 1
 %endmacro
 
+;
+; Upper half of YMM10 to save/restore RCX
+;
+;
+; Save RCX to YMM10[128:191]
+; Modified: XMM5 and YMM10
+;
+
+%macro SAVE_RCX 0
+LYMMN   ymm10, xmm5, 1
+SXMMN   xmm5, 0, rcx
+SYMMN   ymm10, 1, xmm5
+%endmacro
+
+;
+; Restore RCX from YMM10[128:191]
+; Modified: XMM5 and RCX
+;
+
+%macro LOAD_RCX 0
+LYMMN   ymm10, xmm5, 1
+movqrcx,  xmm5
+%endmacro
+
 ;
 ; YMM7[128:191] for calling stack
 ; arg 1:Entry
@@ -231,6 +255,7 @@ NextAddress:
 ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
 ; whether the processor supports SSE instruction.
 ;
+mov r10, rcx
 mov rax, 1
 cpuid
 bt  rdx, 25
@@ -241,6 +266,7 @@ NextAddress:
 ;
 bt  ecx, 19
 jnc SseError
+mov rcx,  r10
 
 ;
 ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
@@ -258,6 +284,7 @@ NextAddress:
 %endmacro
 
 %macro 

[edk2-devel] [PATCH v4 0/2] FSP_TEMP_RAM_INIT call must follow X64 Calling

[cbduggap]

*** BLURB HERE ***
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
FSP_TEMP_RAM_INIT consume input parameter using RCX.

cbduggap (2):
  IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling
Convention
  IntelFsp2WrapperPkg: FSP_TEMP_RAM_INIT call must follow X64 Calling
Convention

 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 39 ++-
 .../Include/SaveRestoreSseAvxNasm.inc | 28 +
 .../X64/SecEntry.nasm |  4 +-
 3 files changed, 51 insertions(+), 20 deletions(-)

-- 
2.36.0.windows.1



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Re: [edk2-devel] [edk2-platforms][PATCH v1 0/3] MinPlatformPkg: Add FADT duty offset and width PCDs

[Michael Kubacki]

Can someone seriously respond?

This was approved over 3 weeks ago and sent 5 weeks ago. I know Ankit 
now has a similar change out but I'd like to see if this can get in and 
that be rebased on it since this has been out for so long and has the 
primary change needed for our integration.


Thanks,
Michael

On 5/13/2022 1:42 PM, Michael Kubacki wrote:

Reminder

On 5/10/2022 1:34 PM, Michael Kubacki wrote:

Another reminder to look at this patch.

Thanks,
Michael


On 4/29/2022 4:07 PM, Michael Kubacki wrote:
Another reminder to merge this series. Chasel has added his review 
and that is in this branch:


https://github.com/makubacki/edk2-platforms/commits/active/add_duty_pcds_minplatformpkg_v1_rb1 



Thanks,
Michael

On 4/22/2022 10:04 AM, Michael Kubacki wrote:

Reminder to review this series.

Ankit Sinha has reviewed it but need a maintainer to review and merge.

On 4/11/2022 4:58 PM, Michael Kubacki wrote:

From: Michael Kubacki 

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3543

Adds PCDs to the MinPlatformPkg DEC file so MinPlatformPkg consumers
(board packages) can customize the DUTY_OFFSET and DUTY_CYCLE
values in their build files.

The copy of AcpiPlatform in SimicsOpenBoardPkg is also updated to
keep the change in sync with the source MinPlatformPkg module.

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Eric Dong 
Signed-off-by: Michael Kubacki 

Michael Kubacki (3):
   MinPlatformPkg: Add FADT duty offset and duty width PCDs
   MinPlatformPkg/AcpiPlatform: Use FADT duty offset and width PCDs
   SimicsOpenBoardPkg/AcpiPlatform: Use FADT duty offset and width 
PCDs


Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c |  3 +++
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.c |  4 ++--
Platform/Intel/SimicsOpenBoardPkg/AcpiTables/MinPlatformAcpiTables/AcpiPlatform.c 
|  3 +++
Platform/Intel/SimicsOpenBoardPkg/AcpiTables/MinPlatformAcpiTables/Fadt/Fadt.c 
|  4 ++--

Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf |  2 ++
Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec | 15 +++
Platform/Intel/SimicsOpenBoardPkg/AcpiTables/MinPlatformAcpiTables/AcpiPlatform.inf 
|  2 ++

  7 files changed, 29 insertions(+), 4 deletions(-)




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Re: 回复: 回复: [edk2-devel] [PATCH v5 0/8] Add Variable Flash Info HOB

[Michael Kubacki]

Liming, will you push both?

I put a rebased edk2-platforms with all the review tags for that series 
here: 
https://github.com/makubacki/edk2-platforms/commits/add_variableflashinfolib_to_platforms


Thanks,
Michael

On 5/16/2022 1:36 PM, Ard Biesheuvel wrote:

On Mon, 16 May 2022 at 17:27, Michael Kubacki
 wrote:


Yes, it has been reviewed by all maintainers. An announcement of the
change was sent to edk2 on April 29th:
https://edk2.groups.io/g/announce/message/291

The series for edk2-platforms has also been out since April 25th:
https://edk2.groups.io/g/devel/message/89308

Thanks,
Michael



I am fine with merging this as is, but please merge the edk2-platforms
changes as soon as the edk2 changes are in, so platforms there are not
left in a broken state.







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[edk2-devel] [edk2-staging][PATCH] edk2-staging/RedfishClientPkg: Introduce Redfish version library

[Nickle Wang]

Add RedfishVersionLib to Redfish client package. This library provides
interface for Redfish feature drivers to get Redfish version on BMC.

Signed-off-by: Nickle Wang 
Cc: Abner Chang 
---
 .../Include/Library/RedfishVersionLib.h   |  30 +++
 RedfishClientPkg/Include/RedfishBase.h|  16 ++
 .../RedfishVersionLib/RedfishVersionLib.c | 203 ++
 .../RedfishVersionLib/RedfishVersionLib.inf   |  44 
 RedfishClientPkg/RedfishClientLibs.dsc.inc|   2 +-
 RedfishClientPkg/RedfishClientPkg.dec |   6 +-
 6 files changed, 298 insertions(+), 3 deletions(-)
 create mode 100644 RedfishClientPkg/Include/Library/RedfishVersionLib.h
 create mode 100644 RedfishClientPkg/Include/RedfishBase.h
 create mode 100644 
RedfishClientPkg/Library/RedfishVersionLib/RedfishVersionLib.c
 create mode 100644 
RedfishClientPkg/Library/RedfishVersionLib/RedfishVersionLib.inf

diff --git a/RedfishClientPkg/Include/Library/RedfishVersionLib.h 
b/RedfishClientPkg/Include/Library/RedfishVersionLib.h
new file mode 100644
index 00..5076c2ce9f
--- /dev/null
+++ b/RedfishClientPkg/Include/Library/RedfishVersionLib.h
@@ -0,0 +1,30 @@
+/** @file
+  This file defines the Redfish version library interface.
+
+  (C) Copyright 2022 Hewlett Packard Enterprise Development LP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef REDFISH_VERSION_LIB_H_
+#define REDFISH_VERSION_LIB_H_
+
+/**
+  Query HTTP request to BMC with given redfish service and return redfish
+  version information. If there is troulbe to get Redfish version on BMC,
+  The value of PcdDefaultRedfishVersion is returned.
+
+  It's call responsibility to release returned buffer.
+
+  @param[in]   Service  Redfish service instance
+
+  @retval EFI_STRING  Redfish version string. NULL while error occurs.
+
+**/
+EFI_STRING
+RedfishGetVersion (
+  IN REDFISH_SERVICE  *Service
+  );
+
+#endif
diff --git a/RedfishClientPkg/Include/RedfishBase.h 
b/RedfishClientPkg/Include/RedfishBase.h
new file mode 100644
index 00..60d585c54a
--- /dev/null
+++ b/RedfishClientPkg/Include/RedfishBase.h
@@ -0,0 +1,16 @@
+/** @file
+  Redfish base header file.
+
+  (C) Copyright 2022 Hewlett Packard Enterprise Development LP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef EFI_REDFISH_BASE_H_
+#define EFI_REDFISH_BASE_H_
+
+#define IS_EMPTY_STRING(a)((a) == NULL || (a)[0] == '\0')
+#define REDFISH_DEBUG_TRACE   DEBUG_VERBOSE
+
+#endif
diff --git a/RedfishClientPkg/Library/RedfishVersionLib/RedfishVersionLib.c 
b/RedfishClientPkg/Library/RedfishVersionLib/RedfishVersionLib.c
new file mode 100644
index 00..0a2ace7726
--- /dev/null
+++ b/RedfishClientPkg/Library/RedfishVersionLib/RedfishVersionLib.c
@@ -0,0 +1,203 @@
+/** @file
+  Redfish version library implementation
+
+  (C) Copyright 2022 Hewlett Packard Enterprise Development LP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define REDFISH_VERSION_DEFAULT_STRING L"v1"
+#define REDFISH_ROOT_URI   "/redfish"
+
+REDFISH_SERVICE *mCacheService;
+EFI_STRING  mVersionCache;
+UINTN   mVersionStringSize;
+
+/**
+  Cache the redfish service version for later use so we don't have to query
+  HTTP request everytime.
+
+  @param[in]   Service  Redfish service instance
+  @param[in]   Version  Version string to cache
+
+  @retval EFI_SUCCESS   Version is saved in cache successfully.
+  @retval Others
+
+**/
+EFI_STATUS
+CacheVersion (
+  IN REDFISH_SERVICE  *Service,
+  IN EFI_STRING   Version
+  )
+{
+  if (Service == NULL || IS_EMPTY_STRING (Version)) {
+return EFI_INVALID_PARAMETER;
+  }
+
+  if (mCacheService == Service) {
+return EFI_ALREADY_STARTED;
+  }
+
+  mCacheService = Service;
+  if (mVersionCache != NULL) {
+FreePool (mVersionCache);
+  }
+
+  mVersionStringSize = StrSize (Version);
+  mVersionCache = AllocateCopyPool (mVersionStringSize, Version);
+  if (mVersionCache == NULL) {
+mCacheService = NULL;
+return EFI_OUT_OF_RESOURCES;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Query HTTP request to BMC with given redfish service and return redfish
+  version information. If there is troulbe to get Redfish version on BMC,
+  The value of PcdDefaultRedfishVersion is returned.
+
+  It's call responsibility to release returned buffer.
+
+  @param[in]   Service  Redfish service instance
+
+  @retval EFI_STRING  Redfish version string. NULL while error occurs.
+
+**/
+EFI_STRING
+RedfishGetVersion (
+  IN REDFISH_SERVICE  *Service
+  )
+{
+  EFI_STATUSStatus;
+  EFI_STRINGVersionString;
+  REDFISH_RESPONSE  Response;
+  EDKII_JSON_VALUE  JsonValue;
+  EDKII_JSON_VALUE  N;
+  CHAR8 *Key;
+  EDKII_JSON_VALUE  Value;
+
+  VersionString = NULL;
+
+  if (Service == NULL) {
+goto ON_ERROR;
+  }
+
+  //
+  // Use cache to prevent HTTP connection.
+  //
+  if (Service == 

[edk2-devel] [PATCH V1 1/1] MinPlatformPkg: Add PCDs to update FADT entries from board package

[Chiu, Chasel]

From: Ankit Sinha 

Adds new PCDs to allow entries in FADT to be customized during platform
integration. Board packages will can update these PCDs during boot.

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Eric Dong 

Signed-off-by: Ankit Sinha 
---
 Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c   | 85 

 Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf | 24 ++
 Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec   | 36 +++--
 3 files changed, 105 insertions(+), 40 deletions(-)

diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c 
b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
index 05fc7799fb13..b3d067def3fa 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
@@ -1165,6 +1165,11 @@ PlatformUpdateTables (
   // Update the creator revision
   //
   TableHeader->CreatorRevision = PcdGet32(PcdAcpiDefaultCreatorRevision);
+
+  //
+  // Update the oem revision
+  //
+  TableHeader->OemRevision = PcdGet32(PcdAcpiDefaultOemRevision);
 }
   }
 
@@ -1187,44 +1192,54 @@ PlatformUpdateTables (
   case EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE:
 FadtHeader = (EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *) Table;
 
-FadtHeader->PreferredPmProfile = PcdGet8 (PcdFadtPreferredPmProfile);
-FadtHeader->IaPcBootArch   = PcdGet16 (PcdFadtIaPcBootArch);
-FadtHeader->Flags  = PcdGet32 (PcdFadtFlags);
+FadtHeader->PreferredPmProfile= PcdGet8 
(PcdFadtPreferredPmProfile);
+FadtHeader->IaPcBootArch  = PcdGet16 
(PcdFadtIaPcBootArch);
+FadtHeader->Flags = PcdGet32 (PcdFadtFlags);
+FadtHeader->AcpiEnable= PcdGet8 
(PcdAcpiEnableSwSmi);
+FadtHeader->AcpiDisable   = PcdGet8 
(PcdAcpiDisableSwSmi);
+FadtHeader->Pm1aEvtBlk= PcdGet16 
(PcdAcpiPm1AEventBlockAddress);
+FadtHeader->Pm1bEvtBlk= PcdGet16 
(PcdAcpiPm1BEventBlockAddress);
+FadtHeader->Pm1aCntBlk= PcdGet16 
(PcdAcpiPm1AControlBlockAddress);
+FadtHeader->Pm1bCntBlk= PcdGet16 
(PcdAcpiPm1BControlBlockAddress);
+FadtHeader->Pm2CntBlk = PcdGet16 
(PcdAcpiPm2ControlBlockAddress);
+FadtHeader->PmTmrBlk  = PcdGet16 
(PcdAcpiPmTimerBlockAddress);
+FadtHeader->Gpe0Blk   = PcdGet16 
(PcdAcpiGpe0BlockAddress);
+FadtHeader->Gpe0BlkLen= PcdGet8 
(PcdAcpiGpe0BlockLength);
+FadtHeader->Gpe1Blk   = PcdGet16 
(PcdAcpiGpe1BlockAddress);
+FadtHeader->Gpe1Base  = PcdGet8 (PcdAcpiGpe1Base);
+FadtHeader->DutyWidth = PcdGet8 (PcdAcpiDutyWidth);
 
-FadtHeader->AcpiEnable  = PcdGet8 (PcdAcpiEnableSwSmi);
-FadtHeader->AcpiDisable = PcdGet8 (PcdAcpiDisableSwSmi);
+FadtHeader->XPm1aEvtBlk.Address   = PcdGet16 
(PcdAcpiPm1AEventBlockAddress);
+FadtHeader->XPm1aCntBlk.Address   = PcdGet16 
(PcdAcpiPm1AControlBlockAddress);
+FadtHeader->XPm1bCntBlk.Address   = PcdGet16 
(PcdAcpiPm1BControlBlockAddress);
+FadtHeader->XPm2CntBlk.Address= PcdGet16 
(PcdAcpiPm2ControlBlockAddress);
+FadtHeader->XPmTmrBlk.Address = PcdGet16 
(PcdAcpiPmTimerBlockAddress);
+FadtHeader->XGpe0Blk.Address  = PcdGet16 
(PcdAcpiGpe0BlockAddress);
+FadtHeader->XGpe1Blk.Address  = PcdGet16 
(PcdAcpiGpe1BlockAddress);
 
-FadtHeader->Pm1aEvtBlk = PcdGet16 (PcdAcpiPm1AEventBlockAddress);
-FadtHeader->Pm1bEvtBlk = PcdGet16 (PcdAcpiPm1BEventBlockAddress);
-FadtHeader->Pm1aCntBlk = PcdGet16 (PcdAcpiPm1AControlBlockAddress);
-FadtHeader->Pm1bCntBlk = PcdGet16 (PcdAcpiPm1BControlBlockAddress);
-FadtHeader->Pm2CntBlk  = PcdGet16 (PcdAcpiPm2ControlBlockAddress);
-FadtHeader->PmTmrBlk   = PcdGet16 (PcdAcpiPmTimerBlockAddress);
-FadtHeader->Gpe0Blk= PcdGet16 (PcdAcpiGpe0BlockAddress);
-FadtHeader->Gpe0BlkLen = 0x20;
-FadtHeader->Gpe1Blk= PcdGet16 (PcdAcpiGpe1BlockAddress);
+FadtHeader->ResetReg.AccessSize   = PcdGet8 
(PcdAcpiResetRegAccessSize);
+FadtHeader->XPm1aEvtBlk.AccessSize= PcdGet8 
(PcdAcpiXPm1aEvtBlkAccessSize);
+FadtHeader->XPm1bEvtBlk.AccessSize= PcdGet8 
(PcdAcpiXPm1bEvtBlkAccessSize);
+FadtHeader->XPm1aCntBlk.AccessSize= PcdGet8 
(PcdAcpiXPm1aCntBlkAccessSize);
+FadtHeader->XPm1bCntBlk.AccessSize= PcdGet8 
(PcdAcpiXPm1bCntBlkAccessSize);
+FadtHeader->XPm2CntBlk.AccessSize = PcdGet8 
(PcdAcpiXPm2CntBlkAccessSize);
+FadtHeader->XPmTmrBlk.AccessSize  = 

Re: [edk2-devel] [Patch v2 00/28] UEFI variable protection

[Michael Kubacki]

Hi Judah,

Do you have reference information for the following?

1. Overall boot time impact for a sample variable store?

-  In particular:
  - Initial HMAC calculation/verification time.
  - Non-volatile write impact time to caluclate new store HMAC value 
and update MetaDataHmacVar.

  - Variable reclaim before and after time.

2. Overall non-volatile store size overhead impact with AES-CBC 
encrypted variables?


I understand these will vary based on system properties like SPI flash 
parameters, cryptographic processor details, etc. I'm trying to get an 
idea of the impact from sample data or averages on a particular system 
configuration. Also to learn whether the native encryption instruction 
(AES-NI) was used and if that could provide any benefit given the 
potential number of encryption/decryption operations introduced.


For the code design, I feel the ProtectedVariableLib interface is a bit 
too coupled against internal implementation details of the variable 
driver. I generally understand why the code is split out to wrap 
operations around the new functionality and it follows the AuthVarLib 
pattern but changing the library or driver will continue to require 
large changes across both like this due to the coupling.


Small things I noticed:
1. VariableKeyLib.inf should not be "BASE", it directly depends on PEI 
services

2. Typo "varabile" in some files
3. Does ProtectedVariableLibNull actually need to depend on BaseMemoryLib?

Thanks,
Michael

On 4/29/2022 2:04 PM, Judah Vang wrote:

For a more detail description of the UEFI variable protected feature you can
view the Readme.md located at the following location:
https://github.com/judahvang/edk2/tree/rpmc-update


Judah Vang (28):
   MdeModulePkg: Add new GUID for Variable Store Info
   SecurityPkg: Add new GUIDs for
   MdeModulePkg: Update AUTH_VARIABLE_INFO struct
   MdeModulePkg: Add reference to new Ppi Guid
   MdeModulePkg: Add new ProtectedVariable GUIDs
   MdeModulePkg: Add new include files
   MdeModulePkg: Add Null ProtectedVariable Library
   MdeModulePkg: Add new Variable functionality
   MdeModulePkg: Add support for Protected Variables
   SecurityPkg: Add new KeyService types and defines
   SecurityPkg: Update RPMC APIs with index
   SecurityPkg: Add new variable types and functions
   SecurityPkg: Fix GetVariableKey API
   SecurityPkg: Add null encryption variable libs
   SecurityPkg: Add VariableKey library function
   SecurityPkg: Add EncryptionVariable lib with AES
   SecurityPkg: Add Protected Variable Services
   MdeModulePkg: Reference Null ProtectedVariableLib
   SecurityPkg: Add references to new *.inf files
   ArmVirtPkg: Add reference to ProtectedVariableNull
   UefiPayloadPkg: Add ProtectedVariable reference
   EmulatorPkg: Add ProtectedVariable reference
   OvmfPkg: Add ProtectedVariable reference
   OvmfPkg: Add ProtectedVariableLib reference
   OvmfPkg: Add ProtectedVariableLib reference
   OvmfPkg: Add ProtectedVariableLib reference
   OvmfPkg: Add ProtectedVariable reference
   CryptoPkg: Enable cypto HMAC KDF library

  MdeModulePkg/MdeModulePkg.dec   | 
  13 +-
  SecurityPkg/SecurityPkg.dec | 
  43 +-
  ArmVirtPkg/ArmVirtQemu.dsc  | 
   3 +-
  EmulatorPkg/EmulatorPkg.dsc | 
   3 +-
  MdeModulePkg/MdeModulePkg.dsc   | 
   4 +-
  OvmfPkg/AmdSev/AmdSevX64.dsc| 
   3 +-
  OvmfPkg/Bhyve/BhyveX64.dsc  | 
   3 +-
  OvmfPkg/CloudHv/CloudHvX64.dsc  | 
   1 +
  OvmfPkg/Microvm/MicrovmX64.dsc  | 
   3 +-
  OvmfPkg/OvmfPkgIa32.dsc | 
   1 +
  OvmfPkg/OvmfPkgIa32X64.dsc  | 
   1 +
  OvmfPkg/OvmfPkgX64.dsc  | 
   1 +
  OvmfPkg/OvmfXen.dsc | 
   3 +-
  SecurityPkg/SecurityPkg.dsc | 
  13 +-
  UefiPayloadPkg/UefiPayloadPkg.dsc   | 
   2 +
  CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf  | 
   2 +-
  MdeModulePkg/Library/ProtectedVariableLibNull/ProtectedVariableLibNull.inf  | 
  34 +
  MdeModulePkg/Universal/Variable/Pei/VariablePei.inf | 
  10 +-
  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf   | 
   3 +-
  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf  | 
   3 +-
  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf| 
   4 +-
  

[edk2-devel] [edk2-staging][PATCH] edk2-staging/RedfishClientPkg: Introduce Redfish event library

[Nickle Wang]

Add RedfishEventLib to Redfish client package. This library provides
interface for Redfish feature drivers to listen to Redfish event
such as the event before provisioning and the event after
provisioning. Feature driver can perform additional operation before
and after Redfish provisioning.

Signed-off-by: Nickle Wang 
Cc: Abner Chang 
---
 .../Include/Guid/RedfishClientEventGroup.h|  27 
 .../Include/Library/RedfishEventLib.h |  77 ++
 .../Library/RedfishEventLib/RedfishEventLib.c | 139 ++
 .../RedfishEventLib/RedfishEventLib.inf   |  38 +
 RedfishClientPkg/RedfishClientLibs.dsc.inc|   2 +-
 RedfishClientPkg/RedfishClientPkg.dec |   7 +-
 6 files changed, 288 insertions(+), 2 deletions(-)
 create mode 100644 RedfishClientPkg/Include/Guid/RedfishClientEventGroup.h
 create mode 100644 RedfishClientPkg/Include/Library/RedfishEventLib.h
 create mode 100644 RedfishClientPkg/Library/RedfishEventLib/RedfishEventLib.c
 create mode 100644 RedfishClientPkg/Library/RedfishEventLib/RedfishEventLib.inf

diff --git a/RedfishClientPkg/Include/Guid/RedfishClientEventGroup.h 
b/RedfishClientPkg/Include/Guid/RedfishClientEventGroup.h
new file mode 100644
index 00..0d88dd4726
--- /dev/null
+++ b/RedfishClientPkg/Include/Guid/RedfishClientEventGroup.h
@@ -0,0 +1,27 @@
+/** @file
+  GUID for Redfish Client Event Group GUID
+
+  (C) Copyright 2022 Hewlett Packard Enterprise Development LP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef REDFISH_CLIENT_EVENT_GROUP_GUID_H_
+#define REDFISH_CLIENT_EVENT_GROUP_GUID_H_
+
+#define REDFISH_CLIENT_FEATURE_READY_TO_PROVISIONING_GUID \
+  { \
+0x77E4FC1C, 0x2428, 0x47EE, { 0x9E, 0xEC, 0x8B, 0x77, 0xEF, 0x9D, 0x4E, 
0xF0 } \
+  }
+
+extern EFI_GUID gEfiRedfishClientFeatureReadyToProvisioningGuid;
+
+#define REDFISH_CLIENT_FEATURE_AFTER_PROVISIONING_GUID \
+  { \
+0xE547CB6F, 0x306F, 0x4226, { 0xAB, 0x70, 0xA0, 0x6E, 0x26, 0xF1, 0x2E, 
0xD0 } \
+  }
+
+extern EFI_GUID gEfiRedfishClientFeatureAfterProvisioningGuid;
+
+#endif
diff --git a/RedfishClientPkg/Include/Library/RedfishEventLib.h 
b/RedfishClientPkg/Include/Library/RedfishEventLib.h
new file mode 100644
index 00..1f3d0acf19
--- /dev/null
+++ b/RedfishClientPkg/Include/Library/RedfishEventLib.h
@@ -0,0 +1,77 @@
+/** @file
+  This file defines the Redfish event library interface.
+
+  (C) Copyright 2022 Hewlett Packard Enterprise Development LP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef REDFISH_EVENT_LIB_H_
+#define REDFISH_EVENT_LIB_H_
+
+#include 
+
+/**
+  Create an EFI event before Redfish provisioning start.
+
+  @param  NotifyFunctionThe notification function to call when the 
event is signaled.
+  @param  NotifyContext The content to pass to NotifyFunction when 
the event is signaled.
+  @param  ReadyToProvisioningEvent  Returns the EFI event returned from 
gBS->CreateEvent(Ex).
+
+  @retval EFI_SUCCESS   Event was created.
+  @retval Other Event was not created.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateReadyToProvisioningEvent (
+  IN  EFI_EVENT_NOTIFY  NotifyFunction,  OPTIONAL
+  IN  VOID  *NotifyContext,  OPTIONAL
+  OUT EFI_EVENT *ReadyToProvisioningEvent
+  );
+
+/**
+  Create an EFI event after Redfish provisioning finished.
+
+  @param  NotifyFunctionThe notification function to call when the 
event is signaled.
+  @param  NotifyContext The content to pass to NotifyFunction when 
the event is signaled.
+  @param  ReadyToProvisioningEvent  Returns the EFI event returned from 
gBS->CreateEvent(Ex).
+
+  @retval EFI_SUCCESS   Event was created.
+  @retval Other Event was not created.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateAfterProvisioningEvent (
+  IN  EFI_EVENT_NOTIFY  NotifyFunction,  OPTIONAL
+  IN  VOID  *NotifyContext,  OPTIONAL
+  OUT EFI_EVENT *ReadyToProvisioningEvent
+  );
+
+/**
+  Signal ready to provisioning event.
+
+  @retval EFI_SUCCESS   Event was created.
+  @retval Other Event was not created.
+
+**/
+EFI_STATUS
+SignalReadyToProvisioningEvent (
+  IN VOID
+  );
+
+/**
+  Signal after provisioning event.
+
+  @retval EFI_SUCCESS   Event was created.
+  @retval Other Event was not created.
+
+**/
+EFI_STATUS
+SignalAfterProvisioningEvent (
+  IN VOID
+  );
+
+#endif
diff --git a/RedfishClientPkg/Library/RedfishEventLib/RedfishEventLib.c 
b/RedfishClientPkg/Library/RedfishEventLib/RedfishEventLib.c
new file mode 100644
index 00..1c8cfe53c7
--- /dev/null
+++ b/RedfishClientPkg/Library/RedfishEventLib/RedfishEventLib.c
@@ -0,0 +1,139 @@
+/** @file
+  Redfish event library implementation.
+
+  (C) Copyright 2022 Hewlett Packard Enterprise Development LP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Create an EFI event before Redfish 

[edk2-devel] Cancelled Event: TianoCore Bug Triage - APAC / NAMO - Tuesday, May 17, 2022 #cal-cancelled

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[edk2-devel] Event: TianoCore Bug Triage - APAC / NAMO - 05/17/2022 #cal-reminder

[Group Notification]

*Reminder: TianoCore Bug Triage - APAC / NAMO*

*When:*
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Re: [edk2-devel] [PATCH V2 5/6] MdePkg: Probe Cc guest in BaseIoLibIntrinsicSev

[Min Xu]

On May 17, 2022 6:22 AM, dann frazier wrote:
> I ran through our tests on stable-202205-rc1, and I'm finding that all of the
> tests using 2M FD_SIZE & SMM_REQUIRE=TRUE are failing with QEMU
> hanging w/o output. Equivalent tests w/ 4M FD_SIZE are working fine. I
> bisected it down to this commit, and also confirmed that reverting this
> commit on top of 202205-rc1 also avoids the problem.
> 
> I might have a chance to debug more tomorrow, but for now I just wanted to
> flag it.
This patch calls CcProbe () to get the Confidential Computing guest type. There 
are 2 versions of CcProbeLib, one is to get the Cc guest type from 
PcdOvmfWorkArea, the other is a null instance and it always return 
CcGuestTypeNonEncrypted (which means it is a legacy vm guest).  Only 
OvmfPkgX64.dsc and IntelTdxX64.dsc include the first one (which probe the 
PcdOvmfWorkArea). 

If this patch is reverted, it means it is to check the guest type by calling 
CPUID, not reading the PcdOvmfWorkArea.

Can you share your build command and qemu command so that I can try it in my 
side?

Thanks
Min


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Re: [edk2-devel] [PATCH v3] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention

[Chiu, Chasel]

Thanks for clarification!
In this case, please use "mov rsp, rcx" to support 64bit addressing.

Thanks,
Chasel


> -Original Message-
> From: Duggapu, Chinni B 
> Sent: Tuesday, May 17, 2022 12:33 AM
> To: Chiu, Chasel ; devel@edk2.groups.io
> Cc: Desimone, Nathaniel L ; Zeng, Star
> ; S, Ashraf Ali 
> Subject: RE: [PATCH v3] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must
> follow X64 Calling Convention
> 
> HI Chasel,
> Yes, we don't need to modify esp for LoadMicrocodeDefault. However, this
> function does couple of MSR Accesses in b/w that would lead to modify RCX
> anyway.
> So, if not RSP, we need to use different register to save RCX and consume in
> the whole function.
> 
> That's why I have not changed the usage of RSP to hold the input parameter.
> 
> 
> 
> Thanks,
> Chinni.
> 
> -Original Message-
> From: Chiu, Chasel 
> Sent: Monday, May 16, 2022 5:38 PM
> To: Duggapu, Chinni B ;
> devel@edk2.groups.io
> Cc: Desimone, Nathaniel L ; Zeng, Star
> ; S, Ashraf Ali 
> Subject: RE: [PATCH v3] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must
> follow X64 Calling Convention
> 
> 
> Thanks for correcting format and updating patch per feedbacks!
> Just one more comment below inline and please also help to include patch
> of
> IntelFsp2WrapperPkg\Library\SecFspWrapperPlatformSecLibSample\X64\S
> ecEntry.nasm for passing API parameter by RCX.
> You might want to create a patch series:
>   [1/2] IntelFsp2Pkg patch
>   [2/2] IntelFsp2WrapperPkg patch
> 
> Thanks,
> Chasel
> 
> > -Original Message-
> > From: Duggapu, Chinni B 
> > Sent: Monday, May 16, 2022 6:54 PM
> > To: devel@edk2.groups.io
> > Cc: Chiu, Chasel ; Desimone, Nathaniel L
> > ; Zeng, Star ; S,
> > Ashraf Ali 
> > Subject: [PATCH v3] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow
> > X64 Calling Convention
> >
> > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
> > This API accept one parameter using RCX and this is consumed in
> > mutiple sub functions.
> >
> > Cc: Chasel Chiu 
> > Cc: Nate DeSimone 
> > Cc: Star Zeng 
> > Cc: Ashraf Ali S 
> > Signed-off-by: cbduggap 
> > ---
> >  IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 26 -
> >  .../Include/SaveRestoreSseAvxNasm.inc | 28
> +++
> >  2 files changed, 41 insertions(+), 13 deletions(-)
> >
> > diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> > b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> > index a9f5f28ed7..9504c96b81 100644
> > --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> > +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> > @@ -114,7 +114,7 @@ endstruc
> >  global ASM_PFX(LoadMicrocodeDefault)
> > ASM_PFX(LoadMicrocodeDefault):; Inputs:-   ;   rsp ->
> > LoadMicrocodeParams pointer+   ;   rcx -> LoadMicrocodeParams
> pointer;
> > Register Usage:;   rsp  Preserved;   All others destroyed@@ -130,10
> > +130,9 @@ ASM_PFX(LoadMicrocodeDefault):
> >  cmprsp, 0jz ParamError-   moveax, dword [rsp + 8];
> > Parameter pointer-   cmpeax, 0+   cmpecx, 0jz ParamError-   
> > mov
> > esp, eax+   movesp, ecx
> 
> 
> 
> I think we do not need to modify esp because now esp/rsp only containing
> return address initialized by caller.
> 
> 
> 
>  ; skip loading Microcode if the
> > MicrocodeCodeSize is zero; and report error if size is less than 2k@@ -
> > 321,8 +320,7 @@ ASM_PFX(EstablishStackFsp):
> >;   ; Save parameter pointer in rdx   ;-  mov   rdx, qword [rsp + 
> > 8]-+
> mov
> > rdx, rcx   ;   ; Enable FSP STACK   ;@@ -420,7 +418,10 @@
> > ASM_PFX(TempRamInitApi):
> >;   ENABLE_SSE   ENABLE_AVX-+  ;+  ; Save Input Parameter in
> YMM10+  ;+
> > SAVE_RCX   ;   ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and
> > YMM6   ;@@ -442,9 +443,8 @@ ASM_PFX(TempRamInitApi):
> >;   ; Check Parameter   ;-  mov   rax, qword [rsp + 8]-  cmp   
> > rax, 0-
> > mov   rax, 08002h+  cmp   rcx, 0+  mov   rcx,
> > 08002h   jzTempRamInitExit;@@ -455,18 +455,18
> > @@ ASM_PFX(TempRamInitApi):
> >jnz   TempRamInitExit; Load microcode-  LOAD_RSP+  LOAD_RCX
> > CALL_YMM  ASM_PFX(LoadMicrocodeDefault)   SAVE_UCODE_STATUS
> > rax ; Save microcode return status in SLOT 0 in YMM9 (upper
> > 128bits).   ; @note If return value rax is not 0, microcode did not load, 
> > but
> > continue and attempt to boot.; Call Sec CAR Init-  LOAD_RSP+
> LOAD_RCX
> > CALL_YMM  ASM_PFX(SecCarInit)   cmp   rax, 0   jnz
> TempRamInitExit
> > -  LOAD_RSP+  LOAD_RCX   CALL_YMM  ASM_PFX(EstablishStackFsp)
> cmp
> > rax, 0   jnz   TempRamInitExitdiff --git
> > a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
> > b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
> > index e8bd91669d..38c807a311 100644
> > --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
> > +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
> > @@ -177,6 +177,30 @@
> >  LXMMN   xmm5, %1, 1

Re: [edk2-devel] System S3 via UEFI shell

[Steven Shi]

As far as I know, there is no general(safe) way to do S3 in Uefi shell. There 
is no AML interpreter driver in UEFI shell to run the platform ASL code.

The warm reset is different from the S3 resume.


Thanks

Steven Shi


From: devel@edk2.groups.io  On Behalf Of Rafael Machado
Sent: Tuesday, May 17, 2022 3:11 AM
To: devel@edk2.groups.io
Subject: [edk2-devel] System S3 via UEFI shell

Hi everyone

I have a question.
Is there a way to put a system to sleep (S3) via UEFI shell?

Checking the UEFIshell spec, there is the reset command, that can be triggered 
with parameter -w, that would cause a warm boot. But I am not sure if warm boot 
and a S3 resume are the same.

Any comments?

Thanks
Rafael




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[edk2-devel] Now: Tools, CI, Code base construction meeting series - 05/16/2022 #cal-notice

[Group Notification]

*Tools, CI, Code base construction meeting series*

*When:*
05/16/2022
4:30pm to 5:30pm
(UTC-07:00) America/Los Angeles

*Where:*
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View Event ( https://edk2.groups.io/g/devel/viewevent?eventid=1496535 )

*Description:*

TianoCore community,

Microsoft and Intel will be hosting a series of open meetings to discuss build, 
CI, tools, and other related topics. If you are interested, have ideas/opinions 
please join us. These meetings will be Monday 4:30pm Pacific Time on Microsoft 
Teams.

MS Teams Link in following discussion: * 
https://github.com/tianocore/edk2/discussions/2614

Anyone is welcome to join.

* tianocore/edk2: EDK II (github.com)
* tianocore/edk2-basetools: EDK II BaseTools Python tools as a PIP module 
(github.com) https://github.com/tianocore/edk2-basetools
* tianocore/edk2-pytool-extensions: Extensions to the edk2 build system 
allowing for a more robust and plugin based build system and tool execution 
environment (github.com) https://github.com/tianocore/edk2-pytool-extensions
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[edk2-devel] [PATCH] MdeModulePkg/UefiBootManagerLib: Configurable New Boot Options

[Ashish Singhal via groups.io]

Add a new PCD to be able to configure whether newly detected boot options
are to be added at the beginning of the current boot options list or at
the end.

Signed-off-by: Ashish Singhal 
---
 MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c| 6 +-
 .../Library/UefiBootManagerLib/UefiBootManagerLib.inf   | 1 +
 MdeModulePkg/MdeModulePkg.dec   | 5 +
 MdeModulePkg/MdeModulePkg.uni   | 4 
 4 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c 
b/MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c
index 962892d38f..8a46100c2a 100644
--- a/MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c
+++ b/MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c
@@ -2435,7 +2435,11 @@ EfiBootManagerRefreshAllBootOption (
   //
   for (Index = 0; Index < BootOptionCount; Index++) {
 if (EfiBootManagerFindLoadOption ([Index], NvBootOptions, 
NvBootOptionCount) == -1) {
-  EfiBootManagerAddLoadOptionVariable ([Index], (UINTN)-1);
+  if (PcdGetBool (PcdNewBootOptionAtStart)) {
+EfiBootManagerAddLoadOptionVariable ([Index], 0);
+  } else {
+EfiBootManagerAddLoadOptionVariable ([Index], (UINTN)-1);
+  }
   //
   // Try best to add the boot options so continue upon failure.
   //
diff --git a/MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf 
b/MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
index fe05d5f1cc..46f41a7c63 100644
--- a/MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+++ b/MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
@@ -119,3 +119,4 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile ## 
CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdDriverHealthConfigureForm   ## 
SOMETIMES_CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdMaxRepairCount  ## 
CONSUMES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdNewBootOptionAtStart## 
CONSUMES
diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec
index cf79292ec8..9d696f117b 100644
--- a/MdeModulePkg/MdeModulePkg.dec
+++ b/MdeModulePkg/MdeModulePkg.dec
@@ -2146,6 +2146,11 @@
   # @Prompt GHCB Pool Size
   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0|UINT64|0x00030008
 
+  ## This dynamic PCD holds the flag to tell UEFI boot manager whether to add 
newly detected devices at
+  #  the end, or at the start of the boot option.
+  # @Prompt Add new devices in boot options at start
+  
gEfiMdeModulePkgTokenSpaceGuid.PcdNewBootOptionAtStart|FALSE|BOOLEAN|0x00030009
+
 [PcdsDynamicEx]
   ## This dynamic PCD enables the default variable setting.
   #  Its value is the default store ID value. The default value is zero as 
Standard default.
diff --git a/MdeModulePkg/MdeModulePkg.uni b/MdeModulePkg/MdeModulePkg.uni
index b070f15ff2..8e68db1c25 100644
--- a/MdeModulePkg/MdeModulePkg.uni
+++ b/MdeModulePkg/MdeModulePkg.uni
@@ -1325,6 +1325,10 @@
 
 #string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdGhcbBase_HELP #language en-US 
"Used with SEV-ES support to identify an address range that is not to be 
encrypted."
 
+#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdNewBootOptionAtStart_PROMPT 
#language en-US "Add new devices in boot options at start"
+
+#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdNewBootOptionAtStart_HELP 
#language en-US "Used by UEFI boot manager to decide whether to place newly 
detcted devices at start of the list or end."
+
 #string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdGhcbSize_PROMPT #language en-US 
"Guest-Hypervisor Communication Block (GHCB) Pool Base Size"
 
 #string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdGhcbSize_HELP #language en-US 
"Used with SEV-ES support to identify the size of the address range that is not 
to be encrypted."
-- 
2.17.1



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Re: [edk2-devel] [PATCH V2 5/6] MdePkg: Probe Cc guest in BaseIoLibIntrinsicSev

[dann frazier]

On Fri, Apr 15, 2022 at 08:07:08AM +0800, Min Xu wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3902
> 
> Bad IO performance in SEC phase is observed after TDX features was
> introduced. (after commit b6b2de884864 - "MdePkg: Support mmio for
> Tdx guest in BaseIoLibIntrinsic").
> 
> This is because IsTdxGuest() will be called in each MMIO operation.
> It is trying to cache the result of the probe in the efi data segment.
> However, that doesn't work in SEC, because the data segment is read only
> (so the write seems to succeed but a read will always return the
> original value), leading to us calling TdIsEnabled() check for every
> mmio we do, which is causing the slowdown because it's very expensive.
> 
> This patch is to call CcProbe instead of TdIsEnabled in IsTdxGuest.
> Null instance of CcProbe always returns CCGuestTypeNonEncrypted. Its
> OvmfPkg version returns the guest type in Ovmf work area.

Hi!

I ran through our tests on stable-202205-rc1, and I'm finding that all
of the tests using 2M FD_SIZE & SMM_REQUIRE=TRUE are failing with
QEMU hanging w/o output. Equivalent tests w/ 4M FD_SIZE are working
fine. I bisected it down to this commit, and also confirmed that
reverting this commit on top of 202205-rc1 also avoids the problem.

I might have a chance to debug more tomorrow, but for now I just
wanted to flag it.

  -dann

> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Cc: James Bottomley 
> Cc: James Bottomley 
> Cc: Jiewen Yao 
> Cc: Gerd Hoffmann 
> Signed-off-by: Min Xu 
> ---
>  .../BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf|  1 +
>  .../Library/BaseIoLibIntrinsic/IoLibInternalTdx.c   | 13 ++---
>  2 files changed, 3 insertions(+), 11 deletions(-)
> 
> diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf 
> b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf
> index 7fe1c60f046e..e1b8298ac451 100644
> --- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf
> +++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf
> @@ -55,6 +55,7 @@
>DebugLib
>BaseLib
>RegisterFilterLib
> +  CcProbeLib
>  
>  [LibraryClasses.X64]
>TdxLib
> diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdx.c 
> b/MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdx.c
> index 1e539dbfbbad..8af6fc35c591 100644
> --- a/MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdx.c
> +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdx.c
> @@ -10,6 +10,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include "IoLibTdx.h"
>  
>  // Size of TDVMCALL Access, including IO and MMIO
> @@ -22,9 +23,6 @@
>  #define TDVMCALL_ACCESS_READ   0
>  #define TDVMCALL_ACCESS_WRITE  1
>  
> -BOOLEAN  mTdxEnabled = FALSE;
> -BOOLEAN  mTdxProbed  = FALSE;
> -
>  /**
>Check if it is Tdx guest.
>  
> @@ -38,14 +36,7 @@ IsTdxGuest (
>VOID
>)
>  {
> -  if (mTdxProbed) {
> -return mTdxEnabled;
> -  }
> -
> -  mTdxEnabled = TdIsEnabled ();
> -  mTdxProbed  = TRUE;
> -
> -  return mTdxEnabled;
> +  return CcProbe () == CCGuestTypeIntelTdx;
>  }
>  
>  /**


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[edk2-devel] How to prevent a DXE driver from loading automatically

[King Sumo]

Hi All,

I'm including EFI drivers for an Intel Network card, but this adds a huge
delay in the system startup when the ports are being initialized (the
server has several slots). The network cards will be used only for PXE boot
during the staging/setup process, so I'm thinking of adding a configurable
option to enable/disable the PXE boot. So only if enabled the drivers will
be loaded, and after the staging the PXE can be disabled via BMC or
something else.

Do we have any way to prevent a driver from being loaded automatically?
Such as using some conditions or dependencies? For instance, if some driver
is not loaded or some protocol isn't available?

One option will be setting the EFI files as RAW or FREEFORM so they will
not be recognized as a DRIVER during the DXE phase. But it will be required
to implement the driver loading, I'm not sure how difficult it will be
(maybe using GetSectionFromAnyFv to load the contents to a buffer, but how
to load it?).

Kind Regards,
Sumo


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[edk2-devel] [PATCH] OvmfPkg: Make an Ia32/X64 hybrid build work with SEV

[Lendacky, Thomas via groups.io]

The BaseMemEncryptSevLib functionality was updated to rely on the use of
the OVMF/SEV workarea to check for SEV guests. However, this area is only
updated when running the X64 OVMF build, not the hybrid Ia32/X64 build.
Base SEV support is allowed under the Ia32/X64 build, but it now fails
to boot as a result of the change.

Update the ResetVector code to check for SEV features when built for
32-bit mode, not just 64-bit mode (requiring updates to both the Ia32
and Ia32X64 fdf files).

Fixes: f1d1c337e7c0575da7fd248b2dd9cffc755940df
Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Michael Roth 
Cc: Min Xu 
Signed-off-by: Tom Lendacky 
---
 OvmfPkg/OvmfPkgIa32.fdf   | 11 +++
 OvmfPkg/OvmfPkgIa32X64.fdf|  8 +++
 OvmfPkg/OvmfPkgX64.fdf|  3 +-
 OvmfPkg/ResetVector/Ia32/AmdSev.asm   |  4 ++
 OvmfPkg/ResetVector/Main.asm  |  6 ++
 OvmfPkg/ResetVector/ResetVector.nasmb | 72 ++--
 6 files changed, 67 insertions(+), 37 deletions(-)

diff --git a/OvmfPkg/OvmfPkgIa32.fdf b/OvmfPkg/OvmfPkgIa32.fdf
index 3ab1755749d4..57d13b7130bc 100644
--- a/OvmfPkg/OvmfPkgIa32.fdf
+++ b/OvmfPkg/OvmfPkgIa32.fdf
@@ -76,6 +76,9 @@ [FD.MEMFD]
 0x007000|0x001000
 
gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize
 
+0x008000|0x001000
+gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaSize
+
 0x01|0x01
 
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize
 
@@ -87,6 +90,14 @@ [FD.MEMFD]
 
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize
 FV = DXEFV
 
+##
+# Set the SEV-ES specific work area PCDs (used for all forms of SEV since the
+# the SEV STATUS MSR is now saved in the work area)
+#
+SET gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase = $(MEMFD_BASE_ADDRESS) +  
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase + 
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeader
+SET gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize = 
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaSize - 
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeader
+##
+
 

 
 [FV.SECFV]
diff --git a/OvmfPkg/OvmfPkgIa32X64.fdf b/OvmfPkg/OvmfPkgIa32X64.fdf
index e1638fa6ea38..ccde366887a9 100644
--- a/OvmfPkg/OvmfPkgIa32X64.fdf
+++ b/OvmfPkg/OvmfPkgIa32X64.fdf
@@ -90,6 +90,14 @@ [FD.MEMFD]
 
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize
 FV = DXEFV
 
+##
+# Set the SEV-ES specific work area PCDs (used for all forms of SEV since the
+# the SEV STATUS MSR is now saved in the work area)
+#
+SET gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase = $(MEMFD_BASE_ADDRESS) +  
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase + 
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeader
+SET gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize = 
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaSize - 
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeader
+##
+
 

 
 [FV.SECFV]
diff --git a/OvmfPkg/OvmfPkgX64.fdf b/OvmfPkg/OvmfPkgX64.fdf
index aa9a83032d9b..438806fba8f1 100644
--- a/OvmfPkg/OvmfPkgX64.fdf
+++ b/OvmfPkg/OvmfPkgX64.fdf
@@ -106,7 +106,8 @@ [FD.MEMFD]
 FV = DXEFV
 
 
##
-# Set the SEV-ES specific work area PCDs
+# Set the SEV-ES specific work area PCDs (used for all forms of SEV since the
+# the SEV STATUS MSR is now saved in the work area)
 #
 SET gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase = $(MEMFD_BASE_ADDRESS) +  
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase + 
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeader
 SET gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize = 
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaSize - 
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeader
diff --git a/OvmfPkg/ResetVector/Ia32/AmdSev.asm 
b/OvmfPkg/ResetVector/Ia32/AmdSev.asm
index 864d68385342..9350b0406833 100644
--- a/OvmfPkg/ResetVector/Ia32/AmdSev.asm
+++ b/OvmfPkg/ResetVector/Ia32/AmdSev.asm
@@ -150,6 +150,8 @@ BITS32
 SevEsUnexpectedRespTerminate:
 TerminateVmgExitTERM_UNEXPECTED_RESP_CODE
 
+%ifdef ARCH_X64
+
 ; If SEV-ES is enabled then initialize and make the GHCB page shared
 SevClearPageEncMaskForGhcbPage:
 ; Check 

[edk2-devel] System S3 via UEFI shell

[Rafael Machado]

Hi everyone

I have a question.
Is there a way to put a system to sleep (S3) via UEFI shell?

Checking the UEFIshell spec, there is the reset command, that can be
triggered with parameter -w, that would cause a warm boot. But I am not
sure if warm boot and a S3 resume are the same.

Any comments?

Thanks
Rafael


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Re: 回复: 回复: [edk2-devel] [PATCH v5 0/8] Add Variable Flash Info HOB

[Ard Biesheuvel]

On Mon, 16 May 2022 at 17:27, Michael Kubacki
 wrote:
>
> Yes, it has been reviewed by all maintainers. An announcement of the
> change was sent to edk2 on April 29th:
> https://edk2.groups.io/g/announce/message/291
>
> The series for edk2-platforms has also been out since April 25th:
> https://edk2.groups.io/g/devel/message/89308
>
> Thanks,
> Michael
>

I am fine with merging this as is, but please merge the edk2-platforms
changes as soon as the edk2 changes are in, so platforms there are not
left in a broken state.


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Re: [edk2-devel] [PATCH v3] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention

[cbduggap]

HI Chasel,
Yes, we don't need to modify esp for LoadMicrocodeDefault. However, this 
function does couple of MSR Accesses in b/w that would lead to modify RCX 
anyway.
So, if not RSP, we need to use different register to save RCX and consume in 
the whole function. 

That's why I have not changed the usage of RSP to hold the input parameter.  
 


Thanks,
Chinni.

-Original Message-
From: Chiu, Chasel  
Sent: Monday, May 16, 2022 5:38 PM
To: Duggapu, Chinni B ; devel@edk2.groups.io
Cc: Desimone, Nathaniel L ; Zeng, Star 
; S, Ashraf Ali 
Subject: RE: [PATCH v3] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 
Calling Convention


Thanks for correcting format and updating patch per feedbacks!
Just one more comment below inline and please also help to include patch of 
IntelFsp2WrapperPkg\Library\SecFspWrapperPlatformSecLibSample\X64\SecEntry.nasm 
for passing API parameter by RCX.
You might want to create a patch series:
[1/2] IntelFsp2Pkg patch
[2/2] IntelFsp2WrapperPkg patch

Thanks,
Chasel

> -Original Message-
> From: Duggapu, Chinni B 
> Sent: Monday, May 16, 2022 6:54 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L 
> ; Zeng, Star ; S, 
> Ashraf Ali 
> Subject: [PATCH v3] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow
> X64 Calling Convention
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
> This API accept one parameter using RCX and this is consumed in 
> mutiple sub functions.
> 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Star Zeng 
> Cc: Ashraf Ali S 
> Signed-off-by: cbduggap 
> ---
>  IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 26 -
>  .../Include/SaveRestoreSseAvxNasm.inc | 28 +++
>  2 files changed, 41 insertions(+), 13 deletions(-)
> 
> diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> index a9f5f28ed7..9504c96b81 100644
> --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> @@ -114,7 +114,7 @@ endstruc
>  global ASM_PFX(LoadMicrocodeDefault)
> ASM_PFX(LoadMicrocodeDefault):; Inputs:-   ;   rsp ->
> LoadMicrocodeParams pointer+   ;   rcx -> LoadMicrocodeParams pointer;
> Register Usage:;   rsp  Preserved;   All others destroyed@@ -130,10
> +130,9 @@ ASM_PFX(LoadMicrocodeDefault):
>  cmprsp, 0jz ParamError-   moveax, dword [rsp + 8];
> Parameter pointer-   cmpeax, 0+   cmpecx, 0jz ParamError-   
> mov
> esp, eax+   movesp, ecx



I think we do not need to modify esp because now esp/rsp only containing return 
address initialized by caller.



 ; skip loading Microcode if the
> MicrocodeCodeSize is zero; and report error if size is less than 2k@@ -
> 321,8 +320,7 @@ ASM_PFX(EstablishStackFsp):
>;   ; Save parameter pointer in rdx   ;-  mov   rdx, qword [rsp + 8]-+ 
>  mov
> rdx, rcx   ;   ; Enable FSP STACK   ;@@ -420,7 +418,10 @@
> ASM_PFX(TempRamInitApi):
>;   ENABLE_SSE   ENABLE_AVX-+  ;+  ; Save Input Parameter in YMM10+  ;+
> SAVE_RCX   ;   ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and
> YMM6   ;@@ -442,9 +443,8 @@ ASM_PFX(TempRamInitApi):
>;   ; Check Parameter   ;-  mov   rax, qword [rsp + 8]-  cmp   
> rax, 0-
> mov   rax, 08002h+  cmp   rcx, 0+  mov   rcx,
> 08002h   jzTempRamInitExit;@@ -455,18 +455,18
> @@ ASM_PFX(TempRamInitApi):
>jnz   TempRamInitExit; Load microcode-  LOAD_RSP+  LOAD_RCX
> CALL_YMM  ASM_PFX(LoadMicrocodeDefault)   SAVE_UCODE_STATUS
> rax ; Save microcode return status in SLOT 0 in YMM9 (upper
> 128bits).   ; @note If return value rax is not 0, microcode did not load, but
> continue and attempt to boot.; Call Sec CAR Init-  LOAD_RSP+  LOAD_RCX
> CALL_YMM  ASM_PFX(SecCarInit)   cmp   rax, 0   jnz   TempRamInitExit
> -  LOAD_RSP+  LOAD_RCX   CALL_YMM  ASM_PFX(EstablishStackFsp)   cmp
> rax, 0   jnz   TempRamInitExitdiff --git
> a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
> b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
> index e8bd91669d..38c807a311 100644
> --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
> +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
> @@ -177,6 +177,30 @@
>  LXMMN   xmm5, %1, 1 %endmacro +;+; Upper half of
> YMM10 to save/restore RCX+;+;+; Save RCX to YMM10[128:191]+;
> Modified: XMM5 and YMM10+;++%macro SAVE_RCX 0+LYMMN
> ymm10, xmm5, 1+SXMMN   xmm5, 0, rcx+SYMMN   ymm10,
> 1, xmm5+%endmacro++;+; Restore RCX from YMM10[128:191]+;
> Modified: XMM5 and RCX+;++%macro LOAD_RCX 0+LYMMN
> ymm10, xmm5, 1+movqrcx,  xmm5+%endmacro+ ; ;
> YMM7[128:191] for calling stack ; arg 1:Entry@@ -231,6 +255,7 @@
> NextAddress:
>  ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to
> test  

Re: [edk2-devel] [PATCH V4 7/9] MdePkg: Define CC Measure EventLog ACPI Table

[Sami Mujawar]

Hi Min,

This patch looks good to me.

Reviewed-by: Sami Mujawar 

Regards,

Sami Mujawar


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Re: [edk2-devel] [PATCH V4 3/9] SecurityPkg: Add definition of EFI_CC_EVENT_HOB_GUID

[Sami Mujawar]

Hi Min,

Thank you for this patch.

Reviewed-by: Sami Mujawar 

Regards,

Sami Mujawar


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Re: [edk2-devel] [PATCH v2 1/1] ArmPlatformPkg: Remove overly verbose DEBUG lines in LcdGraphicsBlt

[Sami Mujawar]

Hi Rebecca,

Thank you for this patch.
These changes look good to me.

Reviewed-by: Sami Mujawar 

Regards,

Sami Mujawar


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Re: [edk2-devel] [PATCH v2 1/1] ArmPlatformPkg: Remove overly verbose DEBUG lines in LcdGraphicsBlt

[Rebecca Cran]

Could I have some reviews of this v2 patch please?


Thanks.

Rebecca Cran


On 5/3/22 14:07, Rebecca Cran wrote:

The DEBUG output in LcdGraphicsBlt is overly verbose, and makes using
the console difficult, for example when using the UiApp.

Since the extra output should no longer be needed, delete the DEBUG
lines.

Signed-off-by: Rebecca Cran 
---
  ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputBlt.c | 12 

  1 file changed, 12 deletions(-)

diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputBlt.c 
b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputBlt.c
index 01ec6f68bd93..013506976f91 100644
--- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputBlt.c
+++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputBlt.c
@@ -815,18 +815,6 @@ LcdGraphicsBlt (
HorizontalResolution = This->Mode->Info->HorizontalResolution;
VerticalResolution   = This->Mode->Info->VerticalResolution;
  
-  DEBUG ((

-DEBUG_INFO,
-"LcdGraphicsBlt (BltOperation:%d,DestX:%d,DestY:%d,Width:%d,Height:%d) 
res(%d,%d)\n",
-BltOperation,
-DestinationX,
-DestinationY,
-Width,
-Height,
-HorizontalResolution,
-VerticalResolution
-));
-
// Check we have reasonable parameters
if ((Width == 0) || (Height == 0)) {
  DEBUG ((DEBUG_ERROR, "LcdGraphicsBlt: ERROR - Invalid dimension: Zero size 
area.\n"));



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Re: [edk2-devel] Some questions about Azure CI

[Michael Kubacki]

I added some contacts that might know more about what ECC requires in 
this case. I didn't see any obvious issues in a few of the snippets 
reported.


Regards,
Michael

On 5/16/2022 1:15 AM, Chao Li wrote:

Hi All,

There have one last error about EFI coding style error when buiding the 
package for MdePkg, all errors are register defined. Refer 
URL: https://dev.azure.com/kilaterlee/LoongArch_edk2/_build/results?buildId=42=logs=39eb2cd7-22b4-5bd2-0a69-7cfb110ec9ce=05ebc774-447e-5082-7d78-51b7641489fd=511 




Such errors come from adding new ARCH support, and Liming has suggested 
that we update the field ExceptionList in MdePkg.ci.yaml to skip this 
issue. I tried it and it passed, but I don't think it is best way.



Question:

Do you or other maintainer know why other ARCH don't need to do this? If 
there is another way, we will try it. Please help me!



Thanks,

Chao



-原始邮件-
*发件人:*"Chao Li" 
*发送时间:*2022-04-21 09:34:51 (星期四)
*收件人:* "devel@edk2.groups.io" ,
"mikub...@linux.microsoft.com" 
*抄送:* "\"devel@edk2.groups.io\"" ,
"\"michael.d.kin...@intel.com\"" ,
"\"quic_rc...@quicinc.com\"" ,
"\"spbro...@outlook.com\"" 
*主题:* Re: [edk2-devel] Some questions about Azure CI

Hi Micheal,

Sorry for my so carelessness, I actually fixed our code yesterday, I
think this bug was brought on by when I modified the code
formatting, I will check carefully next time. Sorry again.

--
Thanks,
Chao



On 4月 20 2022, at 10:45 晚上, "Michael Kubacki"
 wrote:

My understanding is that you were referring to the document on
my fork
being difficult to access and you shared a link to your CI
results that
does not have the message pointing to the wiki page yet.

This is all correct. The wiki content has moved from my fork to the
official wiki page and the patch that adds the message to the CI
results
has not been merged yet. It is posted on the mailing list here and
waiting for reviews:

https://edk2.groups.io/g/devel/message/89098

---

As for your build failing between yesterday and today, note that
the
builds are based on different commits.

Yesterday:

https://github.com/loongson/edk2/commit/8d100910a2ad98b71acaabc0dcdd70be7e0eba63


Today:

https://github.com/loongson/edk2/commit/6ca5d9d6c55ca773a652fe52508e980c7aa372d3


The commits have different content. In particular, I took a
quick look
at a build that is failing now (Build_GCC5
TARGET_MDEMODULE_DEBUG) but
previously succeeded.

The compilation step is failing for reasons such as the following:

INFO -
/home/vsts/work/1/s/MdePkg/Include/LoongArch64/ProcessorBind.h:35:24:

error: expected ‘=’, ‘,’, ‘;’, ‘asm’ or ‘__attribute__’ before
‘UINT16’
INFO - 35 | typedef unsigned shor UINT16;

Notice, that there is a typo introduced in the new commit.
"shor" versus
"short", this is what is causing compilation failure.

Here is a comparison of those two commits showing the line in
ProcessorBind.h that is causing the problem:


https://github.com/loongson/edk2/compare/8d10091..6ca5d9d#diff-50b24eb92c5785d5c70097a70104040fcacfb70225dd8196c1a97ef3bbb305c8R35-R36


Regards,
Michael

On 4/20/2022 7:08 AM, Chao Li wrote:
 > Hi Micheal,
 >
 > Do you know if anyone has modified the Azure CI today? I did
a CI test
 > today, and many modules reported errors, but yesterday, only
two modules
 > reported errors, I don't know what happened. Please refer
following two
 > links:
 >
 > Today:
 >

https://dev.azure.com/kilaterlee/LoongArch_edk2/_build/results?buildId=32=results

 >



 > Yesterday:
 >

https://dev.azure.com/kilaterlee/LoongArch_edk2/_build/results?buildId=31=results

 >



 >
 > --
 > Thanks,
 > Chao
 > 
 >
 >
 > On 4月 20 2022, at 6:10 晚上, Chao Li 
wrote:
 >
 > Hi Micheal,
 >
 > Sorry for late reply, I'm busy with other things, focusing on
 > modifying our code, refer 

Re: 回复: 回复: [edk2-devel] [PATCH v5 0/8] Add Variable Flash Info HOB

[Michael Kubacki]

Yes, it has been reviewed by all maintainers. An announcement of the 
change was sent to edk2 on April 29th:

https://edk2.groups.io/g/announce/message/291

The series for edk2-platforms has also been out since April 25th:
https://edk2.groups.io/g/devel/message/89308

Thanks,
Michael

On 5/13/2022 9:16 PM, gaoliming wrote:

Michael:
   This is my suggestion to resolve such compatible issue. As you say, it needs 
more review and discussion. So, it may not be applied immediately.

   If this patch set needs to catch this table tag, it has to take current way 
to update each DSC file. Have the patch set got reviewed-by from Package 
maintainers? If yes, I think this patch set can still be merged for this stable 
tag.

Thanks
Liming

-邮件原件-
发件人: Michael Kubacki 
发送时间: 2022年5月14日 2:24
收件人: gaoliming ; devel@edk2.groups.io; 'Ard
Biesheuvel' 
抄送: 'Abner Chang' ; 'Andrew Fish'
; 'Anthony Perard' ; 'Ard
Biesheuvel' ; 'Benjamin You'
; 'Brijesh Singh' ; 'Erdem
Aktas' ; 'Gerd Hoffmann' ;
'Guo Dong' ; 'Hao A Wu' ;
'James Bottomley' ; 'Jian J Wang'
; 'Jiewen Yao' ; 'Jordan
Justen' ; 'Julien Grall' ; 'Leif
Lindholm' ; 'Maurice Ma'
; 'Min Xu' ; 'Nickle Wang'
; 'Peter Grehan' ; 'Ray Ni'
; 'Rebecca Cran' ; 'Sami Mujawar'
; 'Sean Rhodes' ;
'Sebastien Boeuf' ; 'Tom Lendacky'

主题: Re: 回复: [edk2-devel] [PATCH v5 0/8] Add Variable Flash Info HOB

Can you please respond with your preference?

I am ready to do this but if it is required now, it should be documented
so it becomes a consistent pattern for future changes.

Thanks,
Michael

On 5/10/2022 11:01 AM, Michael Kubacki wrote:

What's the plan for next steps? The v5 PR has been up for two weeks with
no changes.

Are we going to try to define a long-term pattern for how to include new
library classes in core packages or merge the patch series?

Thanks,
Michael

On 5/5/2022 9:52 PM, Michael Kubacki wrote:

I still believe a long term design pattern deserves more focus and
documentation than a quick modification to this series.

Can you confirm that you envision MdePkg/MdeLibs.dsc.inc serving as a
monolithic host of various other default library class instances?

That somewhat inverts the package relationships, the code reviewer
policy would need to clarify when the original package owners are
included on the MdePkg patch (to confirm they agree with the default
instance choice), and "core" packages would have to be clearly defined
in this context for developers to know what packages are allowed.

In addition, this does not mean there still won't be some level of
platform integration thrash. For example, if a new library class
instance added to MdePkg/MdeLibs.dsc.inc requires another library
class (or multiple others), those might not be added to the DSC
include file. They could have been satisfied in the original package
DSC (or a test platform DSC) but that doesn't mean they will be in all
platform DSC files. So when the MdeLibs.dsc.inc file update occurs,
those platforms break and need to add the library class that was
already specified in other DSC files.

So I request that if this is the preferred approach, that it be agreed
upon (e.g. dedicated RFC), documented, and consistently followed by
other contributions as well.

Regards,
Michael

On 5/4/2022 9:27 PM, gaoliming wrote:

Michael:
I would suggest to reuse MdePkg/MdeLibs.dsc.inc to list the
library and PCD from the edk2 core packages, such as MdePkg,
MdeModulePkg, CryptoPkg, SecurirtyPkg and so on. Those packages are
required by every platforms. They can't be separated. So, I think
MdePkg/MdeLibs.dsc.inc is for edk2 core packages, not only for MdePkg.

Thanks
Liming

-邮件原件-
发件人: devel@edk2.groups.io  代表

Michael

Kubacki
发送时间: 2022年4月29日 23:48
收件人: Ard Biesheuvel 
抄送: edk2-devel-groups-io ; Abner Chang
; Andrew Fish ; Anthony

Perard

; Ard Biesheuvel
;
Benjamin You ; Brijesh Singh
; Erdem Aktas ;

Gerd

Hoffmann ; Guo Dong ; Hao

A

Wu ; James Bottomley ;

Jian J

Wang ; Jiewen Yao ;

Jordan

Justen ; Julien Grall ; Leif
Lindholm ; Liming Gao
; Maurice Ma ;

Min Xu

; Nickle Wang ; Peter

Grehan

; Ray Ni ; Rebecca Cran
; Sami Mujawar ;

Sean

Rhodes ; Sebastien Boeuf
; Tom Lendacky



主题: Re: [edk2-devel] [PATCH v5 0/8] Add Variable Flash Info HOB

I agree that would be a useful tool and in the case of changes such as
this that provide backward compatibility with existing functionality,
particularly helpful.

Some packages such as MdePkg


(https://github.com/tianocore/edk2/blob/master/MdePkg/MdeLibs.dsc.inc)

and NetworkPkg


(https://github.com/tianocore/edk2/blob/master/NetworkPkg/NetworkCom

ponents.dsc.inc)
provide DSC files that a platform can override if necessary.

However, this does not exist for all edk2 packages. I did not introduce
such a file in MdeModulePkg because I believe that is an independent
package design decision outside the scope of this series and, if that
change was made, it should include libraries other than just this
instance. That would lead to additional churn and a 

Re: [edk2-devel] [PATCH edk2-platforms 1/1] Silicon/SynQuacer/Fip006Dxe: Support 4-bytes address for erase and write

[Ard Biesheuvel]

On Tue, 10 May 2022 at 10:25, Masahisa Kojima
 wrote:
>
> From: Kazuhiko Sakamoto 
>
> Support 4-bytes address for erase and write, so that we can
> access whole region of SPI-NOR Flash(64MiB) implemented on the
> Developerbox.
>
> This commit also fixes the wrong macro name. SPINOR_OP_SE and
> SPINOR_OP_SE_4B is the commoand for 64KB block erase,
> it must be SPINOR_OP_BE and SPINOR_OP_BE_4B.
>
> Signed-off-by: Masahisa Kojima 

Reviewed-by: Ard Biesheuvel 

Pushed as df5e094ef347..03d1c51272c0

Thanks,

> ---
>  Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.h |  4 ++--
>  Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.c | 13 +
>  2 files changed, 7 insertions(+), 10 deletions(-)
>
> diff --git a/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.h 
> b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.h
> index bade5706e6ae..3cb86ab588e0 100644
> --- a/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.h
> +++ b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.h
> @@ -313,7 +313,7 @@ NorFlashReadID (
>  #define SPINOR_OP_BE_4K_PMC   0xd7  // Erase 4KiB block on PMC chips
>  #define SPINOR_OP_BE_32K  0x52  // Erase 32KiB block
>  #define SPINOR_OP_CHIP_ERASE  0xc7  // Erase whole flash chip
> -#define SPINOR_OP_SE  0xd8  // Sector erase (usually 64KiB)
> +#define SPINOR_OP_BE  0xd8  // Block erase (usually 64KiB)
>  #define SPINOR_OP_RDID0x9f  // Read JEDEC ID
>  #define SPINOR_OP_RDSFDP  0x5a  // Read SFDP
>  #define SPINOR_OP_RDCR0x35  // Read configuration register
> @@ -329,7 +329,7 @@ NorFlashReadID (
>  #define SPINOR_OP_PP_1_4_4_4B 0x3e  // Quad page program
>  #define SPINOR_OP_BE_4K_4B0x21  // Erase 4KiB block
>  #define SPINOR_OP_BE_32K_4B   0x5c  // Erase 32KiB block
> -#define SPINOR_OP_SE_4B   0xdc  // Sector erase (usually 64KiB)
> +#define SPINOR_OP_BE_4B   0xdc  // Block erase (usually 64KiB)
>  #define SPINOR_OP_RD_ARRAY0xe8  // Read array
>  #define SPINOR_OP_RD_NVCFG0xb5  // Read non-volatile config 
> register
>  #define SPINOR_OP_RD_VCR  0x85  // Read VCR register
> diff --git a/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.c 
> b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.c
> index 8cdaa0eeb83f..b2ca0033ac13 100644
> --- a/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.c
> +++ b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.c
> @@ -51,12 +51,10 @@ STATIC CONST CSDC_DEFINITION mN25qCSDCDefTable[] = {
>{ SPINOR_OP_READ_4B,  TRUE,  TRUE,  FALSE, FALSE, CS_CFG_MBM_SINGLE,
>  CSDC_TRP_SINGLE },
>// Write Operations
> -  { SPINOR_OP_PP,   TRUE,  FALSE, FALSE, TRUE,  CS_CFG_MBM_SINGLE,
> -CSDC_TRP_SINGLE },
> -  { SPINOR_OP_PP_1_1_4, TRUE,  FALSE, FALSE, TRUE,  CS_CFG_MBM_QUAD,
> +  { SPINOR_OP_PP_4B,TRUE,  TRUE,  FALSE, TRUE,  CS_CFG_MBM_SINGLE,
>  CSDC_TRP_SINGLE },
>// Erase Operations
> -  { SPINOR_OP_SE,   FALSE, FALSE, FALSE, TRUE,  CS_CFG_MBM_SINGLE,
> +  { SPINOR_OP_BE_4B,FALSE, FALSE, FALSE, TRUE,  CS_CFG_MBM_SINGLE,
>  CSDC_TRP_SINGLE },
>  };
>
> @@ -446,9 +444,8 @@ NorFlashEraseSingleBlock (
>BlockAddress -= Instance->RegionBaseAddress;
>BlockAddress += Instance->OffsetLba * Instance->BlockSize;
>
> -  NorFlashSetHostCSDC (Instance, TRUE, mFip006NullCmdSeq);
> -  MmioWrite32 (Instance->DeviceBaseAddress,
> -   SwapBytes32 (BlockAddress & 0x00FF) | SPINOR_OP_SE);
> +  NorFlashSetHostCommand (Instance, SPINOR_OP_BE_4B);
> +  MmioWrite32 (Instance->DeviceBaseAddress, SwapBytes32 (BlockAddress));
>NorFlashWaitProgramErase (Instance);
>NorFlashSetHostCSDC (Instance, TRUE, mFip006NullCmdSeq);
>
> @@ -515,7 +512,7 @@ NorFlashWriteSingleWord (
>if (EFI_ERROR (NorFlashEnableWrite (Instance))) {
>  return EFI_DEVICE_ERROR;
>}
> -  NorFlashSetHostCommand (Instance, SPINOR_OP_PP);
> +  NorFlashSetHostCommand (Instance, SPINOR_OP_PP_4B);
>MmioWrite32 (WordAddress, WriteData);
>NorFlashWaitProgramErase (Instance);
>
> --
> 2.17.1
>


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Re: [edk2-devel] [PATCH v3 3/5] MpInitLib: Put SEV logic in separate file

[Lendacky, Thomas via groups.io]

On 5/16/22 02:14, Ray Ni wrote:

The patch does several simplifications:
1. Treat SwitchToRealProc as part of RendezvousFunnelProc.
So the common logic in MpLib.c doesn't need to be aware of
SwitchToRealProc.
As a result, SwitchToRealSize/Offset are removed from
MP_ASSEMBLY_ADDRESS_MAP.

2. Move SwitchToRealProc to AmdSev.nasm.
All other assembly code in AmdSev.nasm is called through
OneTimeCall.


I hadn't realized that Brijesh made all of the functions in AmdSev.nasm 
OneTimeCall functions, so moving the include now actually gets those 
"functions" out of the RendezvousFunnelProc function. Looks much cleaner 
this way.


Thanks Ray!

Reviewed-by: Tom Lendacky 
Tested-by: Tom Lendacky 



Signed-off-by: Ray Ni 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Michael Roth 
Cc: James Bottomley 
Cc: Min Xu 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Jordan Justen 
Cc: Ard Biesheuvel 
Cc: Erdem Aktas 
Cc: Gerd Hoffmann 
---
  .../Library/MpInitLib/Ia32/MpFuncs.nasm   |   5 +-
  UefiCpuPkg/Library/MpInitLib/MpEqu.inc|   4 +-
  UefiCpuPkg/Library/MpInitLib/MpLib.c  |  13 +-
  UefiCpuPkg/Library/MpInitLib/MpLib.h  |   4 +-
  UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm  | 148 
  UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 159 +-
  6 files changed, 161 insertions(+), 172 deletions(-)

diff --git a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm 
b/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm
index 8981c32722..28301bb8f0 100644
--- a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm
+++ b/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm
@@ -199,7 +199,6 @@ CProcedureInvoke:
  call   eax   ; Invoke C function
  
  jmp$ ; Never reach here

-RendezvousFunnelProcEnd:
  
  ;-

  ;SwitchToRealProc procedure follows.
@@ -209,6 +208,8 @@ SwitchToRealProcStart:
  jmp$ ; Never reach here
  SwitchToRealProcEnd:
  
+RendezvousFunnelProcEnd:

+
  
;-
  ;  AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, 
TopOfApStack, CountTofinish, Pm16CodeSegment, SevEsAPJumpTable, WakeupBuffer);
  ;
@@ -258,8 +259,6 @@ ASM_PFX(AsmGetAddressMap):
  movdword [ebx + 
MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncAddress], AsmRelocateApLoopStart
  movdword [ebx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncSize], 
AsmRelocateApLoopEnd - AsmRelocateApLoopStart
  movdword [ebx + MP_ASSEMBLY_ADDRESS_MAP.ModeTransitionOffset], 
Flat32Start - RendezvousFunnelProcStart
-movdword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealSize], 
SwitchToRealProcEnd - SwitchToRealProcStart
-movdword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealOffset], 
SwitchToRealProcStart - RendezvousFunnelProcStart
  movdword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealNoNxOffset], 
SwitchToRealProcStart - Flat32Start
  movdword [ebx + 
MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeOffset], 0
  movdword [ebx + 
MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeSize], 0
diff --git a/UefiCpuPkg/Library/MpInitLib/MpEqu.inc 
b/UefiCpuPkg/Library/MpInitLib/MpEqu.inc
index aba53f5720..1cc071cf7b 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpEqu.inc
+++ b/UefiCpuPkg/Library/MpInitLib/MpEqu.inc
@@ -1,5 +1,5 @@
  
;-- 
;
-; Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
+; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
  ; SPDX-License-Identifier: BSD-2-Clause-Patent
  ;
  ; Module Name:
@@ -27,8 +27,6 @@ struc MP_ASSEMBLY_ADDRESS_MAP
.RelocateApLoopFuncAddress CTYPE_UINTN 1
.RelocateApLoopFuncSizeCTYPE_UINTN 1
.ModeTransitionOffset  CTYPE_UINTN 1
-  .SwitchToRealSize  CTYPE_UINTN 1
-  .SwitchToRealOffsetCTYPE_UINTN 1
.SwitchToRealNoNxOffsetCTYPE_UINTN 1
.SwitchToRealPM16ModeOffsetCTYPE_UINTN 1
.SwitchToRealPM16ModeSize  CTYPE_UINTN 1
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c 
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index d761bdc487..aa0eb9a70b 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -936,8 +936,7 @@ FillExchangeInfoData (
// EfiBootServicesCode to avoid page fault if NX memory protection is 
enabled.
//
if (CpuMpData->WakeupBufferHigh != 0) {
-Size = CpuMpData->AddressMap.RendezvousFunnelSize +
-   CpuMpData->AddressMap.SwitchToRealSize -
+Size = CpuMpData->AddressMap.RendezvousFunnelSize -
 CpuMpData->AddressMap.ModeTransitionOffset;
  CopyMem (
(VOID *)CpuMpData->WakeupBufferHigh,
@@ -991,8 +990,7 @@ BackupAndPrepareWakeupBuffer (
CopyMem (
  (VOID 

Re: [edk2-devel] OVMF_CODE/VARS unable to reboot a mac os vm during installation (only first stage)

[nafi]

Hi all,

I have. similar symptom in a completely different environment:
- Arch Linux Host
- Arch Linux Guest
- Guest with systems-boot and efi-stub
- Guest with auto-detected efi partition

Symptom is, that after downgrading and re-upgrading the kernel, the reboot will 
hang, similar to what Daniele Credo reported.

Everything is fine, if mounting efi partition statically, i.e. via fstab.
Downgrading to 2020.11 resolved the issue.

I have a setup available that can reproduce the issue, since I narrowed it down 
already.

Let me know if I can help in any way to identify, and hopefully fix, the issue.


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[edk2-devel] [PATCH v2] UefiCpuPkg: Store SEV-SNP AP jump table in the secrets page

[Michael Roth via groups.io]

A full-featured SEV-SNP guest will not rely on the AP jump table, and
will instead use the AP Creation interface defined by the GHCB. However,
a guest is still allowed to use the AP jump table if desired.

However, unlike with SEV-ES guests, SEV-SNP guests should not
store/retrieve the jump table address via GHCB requests to the
hypervisor, they should instead store/retrieve it via the SEV-SNP
secrets page. Implement the store side of this for OVMF.

Suggested-by: Tom Lendacky 
Signed-off-by: Michael Roth 
---
v2:
 - Update Secrets OS area to match latest GHCB 2.01 spec
 - Move Secrets header file into ./Register/AMD subdirectory
 - Fix CI EccCheck due to assignment in variable declaration

 MdePkg/Include/Register/Amd/SnpSecretsPage.h  | 56 +++
 MdePkg/MdePkg.dec |  4 ++
 OvmfPkg/AmdSev/AmdSevX64.dsc  |  3 +
 OvmfPkg/CloudHv/CloudHvX64.dsc|  3 +
 OvmfPkg/IntelTdx/IntelTdxX64.dsc  |  3 +
 OvmfPkg/Microvm/MicrovmX64.dsc|  3 +
 OvmfPkg/OvmfPkgIa32.dsc   |  3 +
 OvmfPkg/OvmfPkgIa32X64.dsc|  3 +
 OvmfPkg/OvmfPkgX64.dsc|  3 +
 OvmfPkg/PlatformPei/AmdSev.c  |  5 ++
 OvmfPkg/PlatformPei/PlatformPei.inf   |  1 +
 UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf |  1 +
 UefiCpuPkg/Library/MpInitLib/DxeMpLib.c   | 10 
 13 files changed, 98 insertions(+)
 create mode 100644 MdePkg/Include/Register/Amd/SnpSecretsPage.h

diff --git a/MdePkg/Include/Register/Amd/SnpSecretsPage.h 
b/MdePkg/Include/Register/Amd/SnpSecretsPage.h
new file mode 100644
index 00..3188459150
--- /dev/null
+++ b/MdePkg/Include/Register/Amd/SnpSecretsPage.h
@@ -0,0 +1,56 @@
+/** @file

+Definitions for AMD SEV-SNP Secrets Page

+

+Copyright (c) 2022 AMD Inc. All rights reserved.

+SPDX-License-Identifier: BSD-2-Clause-Patent

+

+**/

+

+#ifndef SNP_SECRETS_PAGE_H_

+#define SNP_SECRETS_PAGE_H_

+

+//

+// OS-defined area of secrets page

+//

+// As defined by "SEV-ES Guest-Hypervisor Communication Block Standardization",

+// revision 2.01, section 2.7, "SEV-SNP Secrets Page".

+//

+typedef PACKED struct _SNP_SECRETS_OS_AREA {

+  UINT32Vmpl0MsgSeqNumLo;

+  UINT32Vmpl1MsgSeqNumLo;

+  UINT32Vmpl2MsgSeqNumLo;

+  UINT32Vmpl3MsgSeqNumLo;

+  UINT64ApJumpTablePa;

+  UINT32Vmpl0MsgSeqNumHi;

+  UINT32Vmpl1MsgSeqNumHi;

+  UINT32Vmpl2MsgSeqNumHi;

+  UINT32Vmpl3MsgSeqNumHi;

+  UINT8 Reserved2[22];

+  UINT16Version;

+  UINT8 GuestUsage[32];

+} SNP_SECRETS_OS_AREA;

+

+#define VMPCK_KEY_LEN  32

+

+//

+// SEV-SNP Secrets page

+//

+// As defined by "SEV-SNP Firmware ABI", revision 1.51, section 8.17.2.5,

+// "PAGE_TYPE_SECRETS".

+//

+typedef PACKED struct _SNP_SECRETS_PAGE {

+  UINT32 Version;

+  UINT32 ImiEn: 1,

+ Reserved : 31;

+  UINT32 Fms;

+  UINT32 Reserved2;

+  UINT8  Gosvw[16];

+  UINT8  Vmpck0[VMPCK_KEY_LEN];

+  UINT8  Vmpck1[VMPCK_KEY_LEN];

+  UINT8  Vmpck2[VMPCK_KEY_LEN];

+  UINT8  Vmpck3[VMPCK_KEY_LEN];

+  SNP_SECRETS_OS_AREAOsArea;

+  UINT8  Reserved3[3840];

+} SNP_SECRETS_PAGE;

+

+#endif

diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index f1ebf9e251..a365bfcfe8 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -2417,5 +2417,9 @@
   # @Prompt Memory encryption attribute

   
gEfiMdePkgTokenSpaceGuid.PcdConfidentialComputingGuestAttr|0|UINT64|0x002e

 

+  ## This dynamic PCD indicates the location of the SEV-SNP secrets page.

+  # @Prompt SEV-SNP secrets page address

+  gEfiMdePkgTokenSpaceGuid.PcdSevSnpSecretsAddress|0|UINT64|0x002f

+

 [UserExtensions.TianoCore."ExtraFiles"]

   MdePkgExtra.uni

diff --git a/OvmfPkg/AmdSev/AmdSevX64.dsc b/OvmfPkg/AmdSev/AmdSevX64.dsc
index f0700035c1..02306945fd 100644
--- a/OvmfPkg/AmdSev/AmdSevX64.dsc
+++ b/OvmfPkg/AmdSev/AmdSevX64.dsc
@@ -575,6 +575,9 @@
   # Set ConfidentialComputing defaults

   gEfiMdePkgTokenSpaceGuid.PcdConfidentialComputingGuestAttr|0

 

+  # Set SEV-SNP Secrets page address default

+  gEfiMdePkgTokenSpaceGuid.PcdSevSnpSecretsAddress|0

+

 !include OvmfPkg/OvmfTpmPcds.dsc.inc

 

   gEfiMdePkgTokenSpaceGuid.PcdFSBClock|1

diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc
index d1c85f60c7..7143698253 100644
--- a/OvmfPkg/CloudHv/CloudHvX64.dsc
+++ b/OvmfPkg/CloudHv/CloudHvX64.dsc
@@ -630,6 +630,9 @@
   # Set ConfidentialComputing defaults

   gEfiMdePkgTokenSpaceGuid.PcdConfidentialComputingGuestAttr|0

 

+  # Set SEV-SNP Secrets page address default

+  gEfiMdePkgTokenSpaceGuid.PcdSevSnpSecretsAddress|0

+

 [PcdsDynamicHii]

 !include OvmfPkg/OvmfTpmPcdsHii.dsc.inc

 

diff --git a/OvmfPkg/IntelTdx/IntelTdxX64.dsc 

[edk2-devel] [PATCH v2] OvmfPkg/AmdSevDxe: Update ConfidentialComputing blob struct definition

[Michael Roth via groups.io]

The Confidential Computing blob defined here is intended to match the
definition defined by linux guest kernel. Previously, both definitions
relied on natural alignment, but that relies on both OVMF and kernel
being compiled as 64-bit. While there aren't currently any plans to
enable SNP support for 32-bit compilations, the kernel definition has
since been updated to use explicit padding/reserved fields to avoid
this dependency. Update OVMF to match that definition.

While at it, also fix up the Reserved fields to match the numbering
used in the kernel.

No functional changes (for currently-supported environments, at least).

Reviewed-by: Tom Lendacky 
Signed-off-by: Michael Roth 
---
v2:
 - Update commit message to clarify why Reserved fields are renamed

 OvmfPkg/AmdSevDxe/AmdSevDxe.c  | 2 ++
 OvmfPkg/Include/Guid/ConfidentialComputingSevSnpBlob.h | 6 --
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/OvmfPkg/AmdSevDxe/AmdSevDxe.c b/OvmfPkg/AmdSevDxe/AmdSevDxe.c
index 662d3c4ccb..ee6d2528d9 100644
--- a/OvmfPkg/AmdSevDxe/AmdSevDxe.c
+++ b/OvmfPkg/AmdSevDxe/AmdSevDxe.c
@@ -27,8 +27,10 @@ STATIC CONFIDENTIAL_COMPUTING_SNP_BLOB_LOCATION  
mSnpBootDxeTable = {
   0,

   (UINT64)(UINTN)FixedPcdGet32 (PcdOvmfSnpSecretsBase),

   FixedPcdGet32 (PcdOvmfSnpSecretsSize),

+  0,

   (UINT64)(UINTN)FixedPcdGet32 (PcdOvmfCpuidBase),

   FixedPcdGet32 (PcdOvmfCpuidSize),

+  0,

 };

 

 EFI_STATUS

diff --git a/OvmfPkg/Include/Guid/ConfidentialComputingSevSnpBlob.h 
b/OvmfPkg/Include/Guid/ConfidentialComputingSevSnpBlob.h
index b328310fd0..83620e31b8 100644
--- a/OvmfPkg/Include/Guid/ConfidentialComputingSevSnpBlob.h
+++ b/OvmfPkg/Include/Guid/ConfidentialComputingSevSnpBlob.h
@@ -18,14 +18,16 @@
 { 0x85, 0x54, 0x93, 0xd7, 0x77, 0x91, 0x2d, 0x42 }, \

   }

 

-typedef struct {

+typedef PACKED struct {

   UINT32Header;

   UINT16Version;

-  UINT16Reserved1;

+  UINT16Reserved;

   UINT64SecretsPhysicalAddress;

   UINT32SecretsSize;

+  UINT32Reserved1;

   UINT64CpuidPhysicalAddress;

   UINT32CpuidLSize;

+  UINT32Reserved2;

 } CONFIDENTIAL_COMPUTING_SNP_BLOB_LOCATION;

 

 extern EFI_GUID  gConfidentialComputingSevSnpBlobGuid;

-- 
2.25.1



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Re: [edk2-devel] [PATCH v3] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention

[Chiu, Chasel]

Thanks for correcting format and updating patch per feedbacks!
Just one more comment below inline and please also help to include patch of 
IntelFsp2WrapperPkg\Library\SecFspWrapperPlatformSecLibSample\X64\SecEntry.nasm 
for passing API parameter by RCX.
You might want to create a patch series:
[1/2] IntelFsp2Pkg patch
[2/2] IntelFsp2WrapperPkg patch

Thanks,
Chasel

> -Original Message-
> From: Duggapu, Chinni B 
> Sent: Monday, May 16, 2022 6:54 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Zeng, Star ; S,
> Ashraf Ali 
> Subject: [PATCH v3] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow
> X64 Calling Convention
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
> This API accept one parameter using RCX and this is consumed in mutiple
> sub functions.
> 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Star Zeng 
> Cc: Ashraf Ali S 
> Signed-off-by: cbduggap 
> ---
>  IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 26 -
>  .../Include/SaveRestoreSseAvxNasm.inc | 28 +++
>  2 files changed, 41 insertions(+), 13 deletions(-)
> 
> diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> index a9f5f28ed7..9504c96b81 100644
> --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> @@ -114,7 +114,7 @@ endstruc
>  global ASM_PFX(LoadMicrocodeDefault)
> ASM_PFX(LoadMicrocodeDefault):; Inputs:-   ;   rsp ->
> LoadMicrocodeParams pointer+   ;   rcx -> LoadMicrocodeParams pointer;
> Register Usage:;   rsp  Preserved;   All others destroyed@@ -130,10
> +130,9 @@ ASM_PFX(LoadMicrocodeDefault):
>  cmprsp, 0jz ParamError-   moveax, dword [rsp + 8];
> Parameter pointer-   cmpeax, 0+   cmpecx, 0jz ParamError-   
> mov
> esp, eax+   movesp, ecx



I think we do not need to modify esp because now esp/rsp only containing return 
address initialized by caller.



 ; skip loading Microcode if the
> MicrocodeCodeSize is zero; and report error if size is less than 2k@@ -
> 321,8 +320,7 @@ ASM_PFX(EstablishStackFsp):
>;   ; Save parameter pointer in rdx   ;-  mov   rdx, qword [rsp + 8]-+ 
>  mov
> rdx, rcx   ;   ; Enable FSP STACK   ;@@ -420,7 +418,10 @@
> ASM_PFX(TempRamInitApi):
>;   ENABLE_SSE   ENABLE_AVX-+  ;+  ; Save Input Parameter in YMM10+  ;+
> SAVE_RCX   ;   ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and
> YMM6   ;@@ -442,9 +443,8 @@ ASM_PFX(TempRamInitApi):
>;   ; Check Parameter   ;-  mov   rax, qword [rsp + 8]-  cmp   
> rax, 0-
> mov   rax, 08002h+  cmp   rcx, 0+  mov   rcx,
> 08002h   jzTempRamInitExit;@@ -455,18 +455,18
> @@ ASM_PFX(TempRamInitApi):
>jnz   TempRamInitExit; Load microcode-  LOAD_RSP+  LOAD_RCX
> CALL_YMM  ASM_PFX(LoadMicrocodeDefault)   SAVE_UCODE_STATUS
> rax ; Save microcode return status in SLOT 0 in YMM9 (upper
> 128bits).   ; @note If return value rax is not 0, microcode did not load, but
> continue and attempt to boot.; Call Sec CAR Init-  LOAD_RSP+  LOAD_RCX
> CALL_YMM  ASM_PFX(SecCarInit)   cmp   rax, 0   jnz   TempRamInitExit
> -  LOAD_RSP+  LOAD_RCX   CALL_YMM  ASM_PFX(EstablishStackFsp)   cmp
> rax, 0   jnz   TempRamInitExitdiff --git
> a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
> b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
> index e8bd91669d..38c807a311 100644
> --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
> +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
> @@ -177,6 +177,30 @@
>  LXMMN   xmm5, %1, 1 %endmacro +;+; Upper half of
> YMM10 to save/restore RCX+;+;+; Save RCX to YMM10[128:191]+;
> Modified: XMM5 and YMM10+;++%macro SAVE_RCX 0+LYMMN
> ymm10, xmm5, 1+SXMMN   xmm5, 0, rcx+SYMMN   ymm10,
> 1, xmm5+%endmacro++;+; Restore RCX from YMM10[128:191]+;
> Modified: XMM5 and RCX+;++%macro LOAD_RCX 0+LYMMN
> ymm10, xmm5, 1+movqrcx,  xmm5+%endmacro+ ; ;
> YMM7[128:191] for calling stack ; arg 1:Entry@@ -231,6 +255,7 @@
> NextAddress:
>  ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to
> test ; whether the processor supports SSE instruction.
>  ;+
> mov r10, rcx mov rax, 1 cpuid bt  
> rdx, 25@@ -
> 241,6 +266,7 @@ NextAddress:
>  ; bt  ecx, 19 jnc SseError+  
>   mov rcx,
> r10  ; ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit
> #10)@@ -258,6 +284,7 @@ NextAddress:
>  %endmacro  %macro ENABLE_AVX   0+mov r10, rcx
> mov eax, 1 cpuid and ecx, 1000h@@ -280,5 
> +307,6
> @@ EnableAvx:
>  xgetbv ; 

Re: [edk2-devel] [PATCH edk2-platforms 1/1] Silicon/SynQuacer/Fip006Dxe: Support 4-bytes address for erase and write

[Masahisa Kojima]

Hi Ard, Leif,

On Tue, 10 May 2022 at 17:25, Masahisa Kojima via groups.io
 wrote:
>
> From: Kazuhiko Sakamoto 
>
> Support 4-bytes address for erase and write, so that we can
> access whole region of SPI-NOR Flash(64MiB) implemented on the
> Developerbox.
>
> This commit also fixes the wrong macro name. SPINOR_OP_SE and
> SPINOR_OP_SE_4B is the commoand for 64KB block erase,
> it must be SPINOR_OP_BE and SPINOR_OP_BE_4B.
>
> Signed-off-by: Masahisa Kojima 
> ---
>  Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.h |  4 ++--
>  Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.c | 13 +
>  2 files changed, 7 insertions(+), 10 deletions(-)
>
> diff --git a/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.h 
> b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.h
> index bade5706e6ae..3cb86ab588e0 100644
> --- a/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.h
> +++ b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.h
> @@ -313,7 +313,7 @@ NorFlashReadID (
>  #define SPINOR_OP_BE_4K_PMC   0xd7  // Erase 4KiB block on PMC chips
>  #define SPINOR_OP_BE_32K  0x52  // Erase 32KiB block
>  #define SPINOR_OP_CHIP_ERASE  0xc7  // Erase whole flash chip
> -#define SPINOR_OP_SE  0xd8  // Sector erase (usually 64KiB)
> +#define SPINOR_OP_BE  0xd8  // Block erase (usually 64KiB)
>  #define SPINOR_OP_RDID0x9f  // Read JEDEC ID
>  #define SPINOR_OP_RDSFDP  0x5a  // Read SFDP
>  #define SPINOR_OP_RDCR0x35  // Read configuration register
> @@ -329,7 +329,7 @@ NorFlashReadID (
>  #define SPINOR_OP_PP_1_4_4_4B 0x3e  // Quad page program
>  #define SPINOR_OP_BE_4K_4B0x21  // Erase 4KiB block
>  #define SPINOR_OP_BE_32K_4B   0x5c  // Erase 32KiB block
> -#define SPINOR_OP_SE_4B   0xdc  // Sector erase (usually 64KiB)
> +#define SPINOR_OP_BE_4B   0xdc  // Block erase (usually 64KiB)
>  #define SPINOR_OP_RD_ARRAY0xe8  // Read array
>  #define SPINOR_OP_RD_NVCFG0xb5  // Read non-volatile config 
> register
>  #define SPINOR_OP_RD_VCR  0x85  // Read VCR register
> diff --git a/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.c 
> b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.c
> index 8cdaa0eeb83f..b2ca0033ac13 100644
> --- a/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.c
> +++ b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.c
> @@ -51,12 +51,10 @@ STATIC CONST CSDC_DEFINITION mN25qCSDCDefTable[] = {
>{ SPINOR_OP_READ_4B,  TRUE,  TRUE,  FALSE, FALSE, CS_CFG_MBM_SINGLE,
>  CSDC_TRP_SINGLE },
>// Write Operations
> -  { SPINOR_OP_PP,   TRUE,  FALSE, FALSE, TRUE,  CS_CFG_MBM_SINGLE,
> -CSDC_TRP_SINGLE },
> -  { SPINOR_OP_PP_1_1_4, TRUE,  FALSE, FALSE, TRUE,  CS_CFG_MBM_QUAD,
> +  { SPINOR_OP_PP_4B,TRUE,  TRUE,  FALSE, TRUE,  CS_CFG_MBM_SINGLE,
>  CSDC_TRP_SINGLE },
>// Erase Operations
> -  { SPINOR_OP_SE,   FALSE, FALSE, FALSE, TRUE,  CS_CFG_MBM_SINGLE,
> +  { SPINOR_OP_BE_4B,FALSE, FALSE, FALSE, TRUE,  CS_CFG_MBM_SINGLE,
>  CSDC_TRP_SINGLE },
>  };
>
> @@ -446,9 +444,8 @@ NorFlashEraseSingleBlock (
>BlockAddress -= Instance->RegionBaseAddress;
>BlockAddress += Instance->OffsetLba * Instance->BlockSize;
>
> -  NorFlashSetHostCSDC (Instance, TRUE, mFip006NullCmdSeq);
> -  MmioWrite32 (Instance->DeviceBaseAddress,
> -   SwapBytes32 (BlockAddress & 0x00FF) | SPINOR_OP_SE);
> +  NorFlashSetHostCommand (Instance, SPINOR_OP_BE_4B);
> +  MmioWrite32 (Instance->DeviceBaseAddress, SwapBytes32 (BlockAddress));
>NorFlashWaitProgramErase (Instance);
>NorFlashSetHostCSDC (Instance, TRUE, mFip006NullCmdSeq);
>
> @@ -515,7 +512,7 @@ NorFlashWriteSingleWord (
>if (EFI_ERROR (NorFlashEnableWrite (Instance))) {
>  return EFI_DEVICE_ERROR;
>}
> -  NorFlashSetHostCommand (Instance, SPINOR_OP_PP);
> +  NorFlashSetHostCommand (Instance, SPINOR_OP_PP_4B);
>MmioWrite32 (WordAddress, WriteData);
>NorFlashWaitProgramErase (Instance);

Ping. If you could take a look, it would be much appreciated.

Thanks,
Masahisa Kojima


>
> --
> 2.17.1
>
>
>
> 
>
>


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[edk2-devel] [PATCH v3] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention

[cbduggap]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
This API accept one parameter using RCX and this is consumed
in mutiple sub functions.

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Ashraf Ali S 
Signed-off-by: cbduggap 
---
 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 26 -
 .../Include/SaveRestoreSseAvxNasm.inc | 28 +++
 2 files changed, 41 insertions(+), 13 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm 
b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
index a9f5f28ed7..9504c96b81 100644
--- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
@@ -114,7 +114,7 @@ endstruc
 global ASM_PFX(LoadMicrocodeDefault)
 ASM_PFX(LoadMicrocodeDefault):
; Inputs:
-   ;   rsp -> LoadMicrocodeParams pointer
+   ;   rcx -> LoadMicrocodeParams pointer
; Register Usage:
;   rsp  Preserved
;   All others destroyed
@@ -130,10 +130,9 @@ ASM_PFX(LoadMicrocodeDefault):
 
cmprsp, 0
jz ParamError
-   moveax, dword [rsp + 8]; Parameter pointer
-   cmpeax, 0
+   cmpecx, 0
jz ParamError
-   movesp, eax
+   movesp, ecx
 
; skip loading Microcode if the MicrocodeCodeSize is zero
; and report error if size is less than 2k
@@ -321,8 +320,7 @@ ASM_PFX(EstablishStackFsp):
   ;
   ; Save parameter pointer in rdx
   ;
-  mov   rdx, qword [rsp + 8]
-
+  mov   rdx, rcx
   ;
   ; Enable FSP STACK
   ;
@@ -420,7 +418,10 @@ ASM_PFX(TempRamInitApi):
   ;
   ENABLE_SSE
   ENABLE_AVX
-
+  ;
+  ; Save Input Parameter in YMM10
+  ;
+  SAVE_RCX
   ;
   ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6
   ;
@@ -442,9 +443,8 @@ ASM_PFX(TempRamInitApi):
   ;
   ; Check Parameter
   ;
-  mov   rax, qword [rsp + 8]
-  cmp   rax, 0
-  mov   rax, 08002h
+  cmp   rcx, 0
+  mov   rcx, 08002h
   jzTempRamInitExit
 
   ;
@@ -455,18 +455,18 @@ ASM_PFX(TempRamInitApi):
   jnz   TempRamInitExit
 
   ; Load microcode
-  LOAD_RSP
+  LOAD_RCX
   CALL_YMM  ASM_PFX(LoadMicrocodeDefault)
   SAVE_UCODE_STATUS rax ; Save microcode return status in SLOT 0 
in YMM9 (upper 128bits).
   ; @note If return value rax is not 0, microcode did not load, but continue 
and attempt to boot.
 
   ; Call Sec CAR Init
-  LOAD_RSP
+  LOAD_RCX
   CALL_YMM  ASM_PFX(SecCarInit)
   cmp   rax, 0
   jnz   TempRamInitExit
 
-  LOAD_RSP
+  LOAD_RCX
   CALL_YMM  ASM_PFX(EstablishStackFsp)
   cmp   rax, 0
   jnz   TempRamInitExit
diff --git a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc 
b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
index e8bd91669d..38c807a311 100644
--- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
+++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
@@ -177,6 +177,30 @@
 LXMMN   xmm5, %1, 1
 %endmacro
 
+;
+; Upper half of YMM10 to save/restore RCX
+;
+;
+; Save RCX to YMM10[128:191]
+; Modified: XMM5 and YMM10
+;
+
+%macro SAVE_RCX 0
+LYMMN   ymm10, xmm5, 1
+SXMMN   xmm5, 0, rcx
+SYMMN   ymm10, 1, xmm5
+%endmacro
+
+;
+; Restore RCX from YMM10[128:191]
+; Modified: XMM5 and RCX
+;
+
+%macro LOAD_RCX 0
+LYMMN   ymm10, xmm5, 1
+movqrcx,  xmm5
+%endmacro
+
 ;
 ; YMM7[128:191] for calling stack
 ; arg 1:Entry
@@ -231,6 +255,7 @@ NextAddress:
 ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
 ; whether the processor supports SSE instruction.
 ;
+mov r10, rcx
 mov rax, 1
 cpuid
 bt  rdx, 25
@@ -241,6 +266,7 @@ NextAddress:
 ;
 bt  ecx, 19
 jnc SseError
+mov rcx,  r10
 
 ;
 ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
@@ -258,6 +284,7 @@ NextAddress:
 %endmacro
 
 %macro ENABLE_AVX   0
+mov r10, rcx
 mov eax, 1
 cpuid
 and ecx, 1000h
@@ -280,5 +307,6 @@ EnableAvx:
 xgetbv ; result in edx:eax
 or  eax, 0006h ; Set XCR0 bit #1 and bit #2 to enable SSE 
state and AVX state
 xsetbv
+mov rcx, r10
 %endmacro
 
-- 
2.36.0.windows.1



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Re: [edk2-devel] [PATCH] BaseTools: Fix dependency issue in PcdValueInit

[Bob Feng]

Reviewed-by: Bob Feng 

-Original Message-
From: devel@edk2.groups.io  On Behalf Of Jake Garver via 
groups.io
Sent: Friday, April 8, 2022 12:59 AM
To: devel@edk2.groups.io; jbra...@nvidia.com; ashishsin...@nvidia.com
Cc: Jake Garver 
Subject: [edk2-devel] [PATCH] BaseTools: Fix dependency issue in PcdValueInit

The generated Makefile was missing a dependency.  This resulted in a build-time 
race condition if the recursive make is multi-threaded and shares job control.

Signed-off-by: Jake Garver 
---
 BaseTools/Source/Python/Workspace/DscBuildData.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/BaseTools/Source/Python/Workspace/DscBuildData.py 
b/BaseTools/Source/Python/Workspace/DscBuildData.py
index fc1e773417..d55ea1bbe2 100644
--- a/BaseTools/Source/Python/Workspace/DscBuildData.py
+++ b/BaseTools/Source/Python/Workspace/DscBuildData.py
@@ -97,7 +97,8 @@ PcdMakefileEnd = '''
 
 AppTarget = '''
 all: $(APPFILE)
-$(APPFILE): $(OBJECTS)
+$(APPLICATION): $(OBJECTS)
+$(APPFILE): $(APPLICATION)
 %s
 '''
 
--
2.17.1








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Re: [edk2-devel] [PATCH] MdeModulePkg/FaultTolerantWriteDxe: Don't check for address alignment

[Wu, Hao A]

Sorry Star and Liming,

For the below patch (removing the alignment check for WorkSpace & SpareArea):
https://edk2.groups.io/g/devel/message/89742

Do you think it will impact the FTW service on flash device? Thanks in advance.

Best Regards,
Hao Wu

From: devel@edk2.groups.io  On Behalf Of Sean Rhodes
Sent: Monday, May 16, 2022 3:54 PM
To: Wu, Hao A 
Cc: devel@edk2.groups.io
Subject: Re: [edk2-devel] [PATCH] MdeModulePkg/FaultTolerantWriteDxe: Don't 
check for address alignment

The bug discovered was with coreboot, and the PCD values are derived from the 
block size of its SMMStore (NvStorage) region. The discussion on the patch can 
be found here: https://review.coreboot.org/c/coreboot/+/62990

Hacking the PCDs could work,, but why would we want to keep an incorrect check?

Thanks!


On Mon, 16 May 2022 at 08:36, Wu, Hao A 
mailto:hao.a...@intel.com>> wrote:
Sorry for not being clear on what I mean.
Is it possible to change the platform PCD values and keep these block size 
alignment requirements.

Best Regards,
Hao Wu

From: devel@edk2.groups.io 
mailto:devel@edk2.groups.io>> On Behalf Of Sean Rhodes
Sent: Monday, May 16, 2022 3:00 PM
To: Wu; Wu, Hao A mailto:hao.a...@intel.com>>; 
devel@edk2.groups.io
Subject: Re: [edk2-devel] [PATCH] MdeModulePkg/FaultTolerantWriteDxe: Don't 
check for address alignment

Hi Hao

Yes, it does conflict - I will update the patch to fix these comments :)

Thank you



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Re: [edk2-devel] [PATCH] MdeModulePkg/FaultTolerantWriteDxe: Don't check for address alignment

[Sean Rhodes]

The bug discovered was with coreboot, and the PCD values are derived from
the block size of its SMMStore (NvStorage) region. The discussion on the
patch can be found here: https://review.coreboot.org/c/coreboot/+/62990

Hacking the PCDs could work,, but why would we want to keep an incorrect
check?

Thanks!


On Mon, 16 May 2022 at 08:36, Wu, Hao A  wrote:

> Sorry for not being clear on what I mean.
>
> Is it possible to change the platform PCD values and keep these block size
> alignment requirements.
>
>
>
> Best Regards,
>
> Hao Wu
>
>
>
> *From:* devel@edk2.groups.io  * On Behalf Of *Sean
> Rhodes
> *Sent:* Monday, May 16, 2022 3:00 PM
> *To:* Wu; Wu, Hao A ; devel@edk2.groups.io
> *Subject:* Re: [edk2-devel] [PATCH] MdeModulePkg/FaultTolerantWriteDxe:
> Don't check for address alignment
>
>
>
> Hi Hao
>
> Yes, it does conflict - I will update the patch to fix these comments :)
>
> Thank you
>
> 
>


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[edk2-devel] [PATCH V4 9/9] OvmfPkg/IntelTdx: Enable RTMR based measurement and measure boot

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853

Enable RTMR based measurement and measure boot for Td guest.

Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Ken Lu 
Cc: Sami Mujawar 
Cc: Gerd Hoffmann 
Reviewed-by: Jiewen Yao 
Signed-off-by: Min Xu 
---
 OvmfPkg/IntelTdx/IntelTdxX64.dsc | 12 +++-
 OvmfPkg/IntelTdx/IntelTdxX64.fdf |  5 +
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/OvmfPkg/IntelTdx/IntelTdxX64.dsc b/OvmfPkg/IntelTdx/IntelTdxX64.dsc
index b101e9e74f09..a87e759c9a50 100644
--- a/OvmfPkg/IntelTdx/IntelTdxX64.dsc
+++ b/OvmfPkg/IntelTdx/IntelTdxX64.dsc
@@ -198,7 +198,7 @@
   
OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
 
   
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibNull/DxeTcg2PhysicalPresenceLib.inf
-  
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+  
TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf
 
 [LibraryClasses.common]
   BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
@@ -555,6 +555,7 @@
 !if $(SECURE_BOOT_ENABLE) == TRUE
   
NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf
 !endif
+  NULL|SecurityPkg/Library/DxeTpm2MeasureBootLib/DxeTpm2MeasureBootLib.inf
   }
 
   MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
@@ -752,3 +753,12 @@
 
   NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
   }
+
+  #
+  # Cc Measurement Protocol for Td guest
+  #
+  OvmfPkg/IntelTdx/TdTcg2Dxe/TdTcg2Dxe.inf {
+
+  HashLib|SecurityPkg/Library/HashLibTdx/HashLibTdx.inf
+  NULL|SecurityPkg/Library/HashInstanceLibSha384/HashInstanceLibSha384.inf
+  }
diff --git a/OvmfPkg/IntelTdx/IntelTdxX64.fdf b/OvmfPkg/IntelTdx/IntelTdxX64.fdf
index 1029916c3484..6923eb883113 100644
--- a/OvmfPkg/IntelTdx/IntelTdxX64.fdf
+++ b/OvmfPkg/IntelTdx/IntelTdxX64.fdf
@@ -295,6 +295,11 @@ INF  OvmfPkg/EmuVariableFvbRuntimeDxe/Fvb.inf
 INF  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
 INF  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
 
+#
+# EFI_CC_MEASUREMENT_PROTOCOL
+#
+INF OvmfPkg/IntelTdx/TdTcg2Dxe/TdTcg2Dxe.inf
+
 

 
 [FV.FVMAIN_COMPACT]
-- 
2.29.2.windows.2



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[edk2-devel] [PATCH V4 8/9] OvmfPkg/IntelTdx: Add TdTcg2Dxe

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853

TdTcg2Dxe mimics the Security/Tcg/Tcg2Dxe. It does below tasks:
 - Set up and install CC_EVENTLOG ACPI table
 - Parse the GUIDed HOB (gCcEventEntryHobGuid) and create CC event log
 - Measure handoff tables, Boot# variables etc
 - Measure Exit Boot Service failed
 - Install CcMeasurement Protocol

Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Ken Lu 
Cc: Sami Mujawar 
Cc: Gerd Hoffmann 
Reviewed-by: Jiewen Yao 
Signed-off-by: Min Xu 
---
 .../IntelTdx/TdTcg2Dxe/MeasureBootPeCoff.c|  407 +++
 OvmfPkg/IntelTdx/TdTcg2Dxe/TdTcg2Dxe.c| 2489 +
 OvmfPkg/IntelTdx/TdTcg2Dxe/TdTcg2Dxe.inf  |  101 +
 3 files changed, 2997 insertions(+)
 create mode 100644 OvmfPkg/IntelTdx/TdTcg2Dxe/MeasureBootPeCoff.c
 create mode 100644 OvmfPkg/IntelTdx/TdTcg2Dxe/TdTcg2Dxe.c
 create mode 100644 OvmfPkg/IntelTdx/TdTcg2Dxe/TdTcg2Dxe.inf

diff --git a/OvmfPkg/IntelTdx/TdTcg2Dxe/MeasureBootPeCoff.c 
b/OvmfPkg/IntelTdx/TdTcg2Dxe/MeasureBootPeCoff.c
new file mode 100644
index ..4d542156badd
--- /dev/null
+++ b/OvmfPkg/IntelTdx/TdTcg2Dxe/MeasureBootPeCoff.c
@@ -0,0 +1,407 @@
+/** @file
+  This module implements measuring PeCoff image for Tcg2 Protocol.
+
+  Caution: This file requires additional review when modified.
+  This driver will have external input - PE/COFF image.
+  This external input must be validated carefully to avoid security issue like
+  buffer overflow, integer overflow.
+
+Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+UINTN  mTcg2DxeImageSize = 0;
+
+/**
+  Reads contents of a PE/COFF image in memory buffer.
+
+  Caution: This function may receive untrusted input.
+  PE/COFF image is external input, so this function will make sure the PE/COFF 
image content
+  read is within the image buffer.
+
+  @param  FileHandle  Pointer to the file handle to read the PE/COFF image.
+  @param  FileOffset  Offset into the PE/COFF image to begin the read 
operation.
+  @param  ReadSizeOn input, the size in bytes of the requested read 
operation.
+  On output, the number of bytes actually read.
+  @param  Buffer  Output buffer that contains the data read from the 
PE/COFF image.
+
+  @retval EFI_SUCCESS The specified portion of the PE/COFF image was read 
and the size
+**/
+EFI_STATUS
+EFIAPI
+Tcg2DxeImageRead (
+  IN VOID   *FileHandle,
+  IN UINTN  FileOffset,
+  IN OUT UINTN  *ReadSize,
+  OUTVOID   *Buffer
+  )
+{
+  UINTN  EndPosition;
+
+  if ((FileHandle == NULL) || (ReadSize == NULL) || (Buffer == NULL)) {
+return EFI_INVALID_PARAMETER;
+  }
+
+  if (MAX_ADDRESS - FileOffset < *ReadSize) {
+return EFI_INVALID_PARAMETER;
+  }
+
+  EndPosition = FileOffset + *ReadSize;
+  if (EndPosition > mTcg2DxeImageSize) {
+*ReadSize = (UINT32)(mTcg2DxeImageSize - FileOffset);
+  }
+
+  if (FileOffset >= mTcg2DxeImageSize) {
+*ReadSize = 0;
+  }
+
+  CopyMem (Buffer, (UINT8 *)((UINTN)FileHandle + FileOffset), *ReadSize);
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Measure PE image into TPM log based on the authenticode image hashing in
+  PE/COFF Specification 8.0 Appendix A.
+
+  Caution: This function may receive untrusted input.
+  PE/COFF image is external input, so this function will validate its data 
structure
+  within this image buffer before use.
+
+  Notes: PE/COFF image is checked by BasePeCoffLib PeCoffLoaderGetImageInfo().
+
+  @param[in]  RtmrIndex  Rtmr index
+  @param[in]  ImageAddress   Start address of image buffer.
+  @param[in]  ImageSize  Image size
+  @param[out] DigestList Digest list of this image.
+
+  @retval EFI_SUCCESSSuccessfully measure image.
+  @retval EFI_OUT_OF_RESOURCES   No enough resource to measure image.
+  @retval other error value
+**/
+EFI_STATUS
+MeasurePeImageAndExtend (
+  IN  UINT32RtmrIndex,
+  IN  EFI_PHYSICAL_ADDRESS  ImageAddress,
+  IN  UINTN ImageSize,
+  OUT TPML_DIGEST_VALUES*DigestList
+  )
+{
+  EFI_STATUS   Status;
+  EFI_IMAGE_DOS_HEADER *DosHdr;
+  UINT32   PeCoffHeaderOffset;
+  EFI_IMAGE_SECTION_HEADER *Section;
+  UINT8*HashBase;
+  UINTNHashSize;
+  UINTNSumOfBytesHashed;
+  EFI_IMAGE_SECTION_HEADER *SectionHeader;
+  UINTNIndex;
+  UINTNPos;
+  EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION  Hdr;
+  UINT32   NumberOfRvaAndSizes;
+  UINT32   CertSize;
+  HASH_HANDLE  HashHandle;
+  

[edk2-devel] [PATCH V4 7/9] MdePkg: Define CC Measure EventLog ACPI Table

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853

TDVF set up an ACPI table (EFI_CC_EVENTLOG_ACPI_TABLE) to pass the
event-log information. The event log created by the TD owner contains
the hashes to reconstruct the MRTD and RTMR registers.

Please refer to Sec 4.3.3 in blow link:
https://www.intel.com/content/dam/develop/external/us/en/documents/
intel-tdx-guest-hypervisor-communication-interface-1.0-344426-002.pdf

Please be noted, the definition of EFI_CC_EVENTLOG_ACPI_TABLE is a
little different from the above document. This difference is based on
below discussion:
- https://edk2.groups.io/g/devel/message/87396
- https://edk2.groups.io/g/devel/message/87402

This change will be reflected in the next version of the above document.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Jiewen Yao 
Cc: Jian J Wang 
Cc: Ken Lu 
Cc: Sami Mujawar 
Cc: Gerd Hoffmann 
Reviewed-by: Liming Gao 
Reviewed-by: Jiewen Yao 
Signed-off-by: Min Xu 
---
 MdePkg/Include/Protocol/CcMeasurement.h | 21 +
 1 file changed, 21 insertions(+)

diff --git a/MdePkg/Include/Protocol/CcMeasurement.h 
b/MdePkg/Include/Protocol/CcMeasurement.h
index 68029e977fac..4bf21fc42fa0 100644
--- a/MdePkg/Include/Protocol/CcMeasurement.h
+++ b/MdePkg/Include/Protocol/CcMeasurement.h
@@ -299,4 +299,25 @@ typedef struct {
 
 extern EFI_GUID  gEfiCcFinalEventsTableGuid;
 
+//
+// Define the CC Measure EventLog ACPI Table
+//
+#pragma pack(1)
+
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADERHeader;
+  EFI_CC_TYPECcType;
+  UINT16 Rsvd;
+  UINT64 Laml;
+  UINT64 Lasa;
+} EFI_CC_EVENTLOG_ACPI_TABLE;
+
+#pragma pack()
+
+//
+// Define the signature and revision of CC Measurement EventLog ACPI Table
+//
+#define EFI_CC_EVENTLOG_ACPI_TABLE_SIGNATURE  SIGNATURE_32('C', 'C', 'E', 'L')
+#define EFI_CC_EVENTLOG_ACPI_TABLE_REVISION   1
+
 #endif
-- 
2.29.2.windows.2



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[edk2-devel] [PATCH V4 6/9] OvmfPkg: Add PCDs for LAML/LASA field in CC EVENTLOG ACPI table

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853

Add PCDs to records LAML/LASA field in CC EVENTLOG ACPI table.

Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Ken Lu 
Cc: Sami Mujawar 
Cc: Gerd Hoffmann 
Reviewed-by: Jiewen Yao 
Signed-off-by: Min Xu 
---
 OvmfPkg/OvmfPkg.dec | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec
index 1dd86af55b91..5fe487f82d1a 100644
--- a/OvmfPkg/OvmfPkg.dec
+++ b/OvmfPkg/OvmfPkg.dec
@@ -445,6 +445,12 @@
   #2 - set by GOP Driver.
   gUefiOvmfPkgTokenSpaceGuid.PcdVideoResolutionSource|0|UINT8|0x64
 
+  ## This PCD records LAML field in CC EVENTLOG ACPI table.
+  gUefiOvmfPkgTokenSpaceGuid.PcdCcEventlogAcpiTableLaml|0|UINT32|0x66
+
+  ## This PCD records LASA field in CC EVENTLOG ACPI table.
+  gUefiOvmfPkgTokenSpaceGuid.PcdCcEventlogAcpiTableLasa|0|UINT64|0x67
+
 [PcdsFeatureFlag]
   gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE|BOOLEAN|0x1c
   gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|FALSE|BOOLEAN|0x1d
-- 
2.29.2.windows.2



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[edk2-devel] [PATCH V4 5/9] OvmfPkg/IntelTdx: Measure Td HobList and Configuration FV

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853

TdHobList and Configuration FV are external data provided by Host VMM.
These are not trusted in Td guest. So they should be validated , measured
and extended to Td RTMR registers. In the meantime 2 EFI_CC_EVENT_HOB are
created. These 2 GUIDed HOBs carry the hash value of TdHobList and
Configuration FV. In DXE phase EFI_CC_EVENT can be created based on these
2 GUIDed HOBs.

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Gerd Hoffmann 
Reviewed-by: Jiewen Yao 
Signed-off-by: Min Xu 
---
 OvmfPkg/IntelTdx/IntelTdxX64.dsc  |   4 +
 OvmfPkg/Library/PeilessStartupLib/IntelTdx.c  | 163 ++
 .../PeilessStartupLib/PeilessStartup.c|  31 
 .../PeilessStartupInternal.h  |  17 ++
 .../PeilessStartupLib/PeilessStartupLib.inf   |   8 +-
 5 files changed, 221 insertions(+), 2 deletions(-)
 create mode 100644 OvmfPkg/Library/PeilessStartupLib/IntelTdx.c

diff --git a/OvmfPkg/IntelTdx/IntelTdxX64.dsc b/OvmfPkg/IntelTdx/IntelTdxX64.dsc
index 80c331ea233a..b101e9e74f09 100644
--- a/OvmfPkg/IntelTdx/IntelTdxX64.dsc
+++ b/OvmfPkg/IntelTdx/IntelTdxX64.dsc
@@ -526,6 +526,10 @@
   OvmfPkg/IntelTdx/Sec/SecMain.inf {
 
   
NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+  
SecMeasurementLib|OvmfPkg/Library/SecMeasurementLib/SecMeasurementLibTdx.inf
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SecCryptLib.inf
+  HashLib|SecurityPkg/Library/HashLibTdx/HashLibTdx.inf
+  NULL|SecurityPkg/Library/HashInstanceLibSha384/HashInstanceLibSha384.inf
   }
 
   #
diff --git a/OvmfPkg/Library/PeilessStartupLib/IntelTdx.c 
b/OvmfPkg/Library/PeilessStartupLib/IntelTdx.c
new file mode 100644
index ..d240d3b7719f
--- /dev/null
+++ b/OvmfPkg/Library/PeilessStartupLib/IntelTdx.c
@@ -0,0 +1,163 @@
+/** @file
+  Copyright (c) 2022, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "PeilessStartupInternal.h"
+
+/**
+  Check padding data all bit should be 1.
+
+  @param[in] Buffer - A pointer to buffer header
+  @param[in] BufferSize - Buffer size
+
+  @retval  TRUE   - The padding data is valid.
+  @retval  TRUE  - The padding data is invalid.
+
+**/
+BOOLEAN
+CheckPaddingData (
+  IN UINT8   *Buffer,
+  IN UINT32  BufferSize
+  )
+{
+  UINT32  index;
+
+  for (index = 0; index < BufferSize; index++) {
+if (Buffer[index] != 0xFF) {
+  return FALSE;
+}
+  }
+
+  return TRUE;
+}
+
+/**
+  Check the integrity of CFV data.
+
+  @param[in] TdxCfvBase - A pointer to CFV header
+  @param[in] TdxCfvSize - CFV data size
+
+  @retval  TRUE   - The CFV data is valid.
+  @retval  FALSE  - The CFV data is invalid.
+
+**/
+BOOLEAN
+EFIAPI
+TdxValidateCfv (
+  IN UINT8   *TdxCfvBase,
+  IN UINT32  TdxCfvSize
+  )
+{
+  UINT16 Checksum;
+  UINTN  VariableBase;
+  UINT32 VariableOffset;
+  UINT32 VariableOffsetBeforeAlign;
+  EFI_FIRMWARE_VOLUME_HEADER *CfvFvHeader;
+  VARIABLE_STORE_HEADER  *CfvVariableStoreHeader;
+  AUTHENTICATED_VARIABLE_HEADER  *VariableHeader;
+
+  static EFI_GUID  FvHdrGUID   = EFI_SYSTEM_NV_DATA_FV_GUID;
+  static EFI_GUID  VarStoreHdrGUID = EFI_AUTHENTICATED_VARIABLE_GUID;
+
+  VariableOffset = 0;
+
+  if (TdxCfvBase == NULL) {
+DEBUG ((DEBUG_ERROR, "TDX CFV: CFV pointer is NULL\n"));
+return FALSE;
+  }
+
+  //
+  // Verify the header zerovetor, filesystemguid,
+  // revision, signature, attributes, fvlength, checksum
+  // HeaderLength cannot be an odd number
+  //
+  CfvFvHeader = (EFI_FIRMWARE_VOLUME_HEADER *)TdxCfvBase;
+
+  if ((!IsZeroBuffer (CfvFvHeader->ZeroVector, 16)) ||
+  (!CompareGuid (, >FileSystemGuid)) ||
+  (CfvFvHeader->Signature != EFI_FVH_SIGNATURE) ||
+  (CfvFvHeader->Attributes != 0x4feff) ||
+  (CfvFvHeader->Revision != EFI_FVH_REVISION) ||
+  (CfvFvHeader->FvLength != TdxCfvSize)
+  )
+  {
+DEBUG ((DEBUG_ERROR, "TDX CFV: Basic FV headers were invalid\n"));
+return FALSE;
+  }
+
+  //
+  // Verify the header checksum
+  //
+  Checksum = CalculateSum16 ((VOID *)CfvFvHeader, CfvFvHeader->HeaderLength);
+
+  if (Checksum != 0) {
+DEBUG ((DEBUG_ERROR, "TDX CFV: FV checksum was invalid\n"));
+return FALSE;
+  }
+
+  //
+  // Verify the header signature, size, format, state
+  //
+  CfvVariableStoreHeader = (VARIABLE_STORE_HEADER *)(TdxCfvBase + 
CfvFvHeader->HeaderLength);
+  if ((!CompareGuid (, >Signature)) ||
+  (CfvVariableStoreHeader->Format != VARIABLE_STORE_FORMATTED) ||
+  (CfvVariableStoreHeader->State != VARIABLE_STORE_HEALTHY) ||
+  (CfvVariableStoreHeader->Size > (CfvFvHeader->FvLength - 
CfvFvHeader->HeaderLength)) ||
+  

[edk2-devel] [PATCH V4 4/9] OvmfPkg: Introduce SecMeasurementLib

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853

SecMeasurementLib is designed to do the measurement in SEC phase. In
current stage there are 2 functions introduced:
 - MeasureHobList: Measure the Hoblist passed from the VMM.
 - MeasureFvImage: Measure the FV image.

SecMeasurementLibTdx is the TDX version of the library.

Cc: Brijesh Singh 
Cc: Erdem Aktas 
Cc: James Bottomley 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Ken Lu 
Cc: Sami Mujawar 
Cc: Gerd Hoffmann 
Reviewed-by: Jiewen Yao 
Signed-off-by: Min Xu 
---
 OvmfPkg/Include/Library/SecMeasurementLib.h   |  46 +++
 .../SecMeasurementLib/SecMeasurementLibTdx.c  | 340 ++
 .../SecMeasurementLibTdx.inf  |  30 ++
 OvmfPkg/OvmfPkg.dec   |   4 +
 4 files changed, 420 insertions(+)
 create mode 100644 OvmfPkg/Include/Library/SecMeasurementLib.h
 create mode 100644 OvmfPkg/Library/SecMeasurementLib/SecMeasurementLibTdx.c
 create mode 100644 OvmfPkg/Library/SecMeasurementLib/SecMeasurementLibTdx.inf

diff --git a/OvmfPkg/Include/Library/SecMeasurementLib.h 
b/OvmfPkg/Include/Library/SecMeasurementLib.h
new file mode 100644
index ..ca7a7dc3a9b2
--- /dev/null
+++ b/OvmfPkg/Include/Library/SecMeasurementLib.h
@@ -0,0 +1,46 @@
+/** @file
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SEC_MEASUREMENT_LIB_H_
+#define SEC_MEASUREMENT_LIB_H_
+
+/**
+  Measure the Hoblist passed from the VMM.
+
+  @param[in] VmmHobListThe Hoblist pass the firmware
+
+  @retval EFI_SUCCESS   Fv image is measured successfully
+or it has been already measured.
+  @retval OthersOther errors as indicated
+**/
+EFI_STATUS
+EFIAPI
+MeasureHobList (
+  IN CONST VOID  *VmmHobList
+  );
+
+/**
+  Measure FV image.
+
+  @param[in]  FvBaseBase address of FV image.
+  @param[in]  FvLength  Length of FV image.
+  @param[in]  PcrIndex  Index of PCR
+
+  @retval EFI_SUCCESS   Fv image is measured successfully
+or it has been already measured.
+  @retval OthersOther errors as indicated
+**/
+EFI_STATUS
+EFIAPI
+MeasureFvImage (
+  IN EFI_PHYSICAL_ADDRESS  FvBase,
+  IN UINT64FvLength,
+  IN UINT8 PcrIndex
+  );
+
+#endif
diff --git a/OvmfPkg/Library/SecMeasurementLib/SecMeasurementLibTdx.c 
b/OvmfPkg/Library/SecMeasurementLib/SecMeasurementLibTdx.c
new file mode 100644
index ..274fda1e563e
--- /dev/null
+++ b/OvmfPkg/Library/SecMeasurementLib/SecMeasurementLibTdx.c
@@ -0,0 +1,340 @@
+/** @file
+*
+*  Copyright (c) 2021, Intel Corporation. All rights reserved.
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#pragma pack(1)
+
+typedef struct {
+  UINT32   count;
+  TPMI_ALG_HASHhashAlg;
+  BYTE sha384[SHA384_DIGEST_SIZE];
+} TDX_DIGEST_VALUE;
+
+#define HANDOFF_TABLE_DESC  "TdxTable"
+typedef struct {
+  UINT8  TableDescriptionSize;
+  UINT8  TableDescription[sizeof (HANDOFF_TABLE_DESC)];
+  UINT64 NumberOfTables;
+  EFI_CONFIGURATION_TABLETableEntry[1];
+} TDX_HANDOFF_TABLE_POINTERS2;
+
+#define FV_HANDOFF_TABLE_DESC  "Fv(----)"
+typedef struct {
+  UINT8   BlobDescriptionSize;
+  UINT8   BlobDescription[sizeof (FV_HANDOFF_TABLE_DESC)];
+  EFI_PHYSICAL_ADDRESSBlobBase;
+  UINT64  BlobLength;
+} FV_HANDOFF_TABLE_POINTERS2;
+
+#pragma pack()
+
+#define INVALID_PCR2MR_INDEX  0xFF
+
+/**
+RTMR[0]  => PCR[1,7]
+RTMR[1]  => PCR[2,3,4,5]
+RTMR[2]  => PCR[8~15]
+RTMR[3]  => NA
+  Note:
+PCR[0] is mapped to MRTD and should not appear here.
+PCR[6] is reserved for OEM. It is not used.
+**/
+UINT8
+GetMappedRtmrIndex (
+  UINT32  PCRIndex
+  )
+{
+  UINT8  RtmrIndex;
+
+  if ((PCRIndex == 6) || (PCRIndex == 0) || (PCRIndex > 15)) {
+DEBUG ((DEBUG_ERROR, "Invalid PCRIndex(%d) map to MR Index.\n", PCRIndex));
+ASSERT (FALSE);
+return INVALID_PCR2MR_INDEX;
+  }
+
+  RtmrIndex = 0;
+  if ((PCRIndex == 1) || (PCRIndex == 7)) {
+RtmrIndex = 0;
+  } else if ((PCRIndex >= 2) && (PCRIndex < 6)) {
+RtmrIndex = 1;
+  } else if ((PCRIndex >= 8) && (PCRIndex <= 15)) {
+RtmrIndex = 2;
+  }
+
+  return RtmrIndex;
+}
+
+/**
+  Tpm measure and log data, and extend the measurement result into a specific 
PCR.
+
+  @param[in]  PcrIndex PCR Index.
+  @param[in]  EventTypeEvent type.
+  @param[in]  EventLog Measurement event log.
+  @param[in]  LogLen   Event log length in bytes.
+  @param[in]  HashData The start of the data buffer to be hashed, 
extended.
+  @param[in]  HashDataLen  The length, in bytes, of the 

[edk2-devel] [PATCH V4 3/9] SecurityPkg: Add definition of EFI_CC_EVENT_HOB_GUID

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853

EFI_CC_EVENT_HOB_GUID is the global ID of a GUIDed HOB used to pass
TDX_DIGEST_VALUE from SEC to a DXE Driver ( This DXE driver will
be introduced in the following commit in this patch-sets ). In that
DXE driver this GUIDed HOB will be parsed and the TDX_DIGEST_VALUE
then will be extracted. After that a EFI_CC_EVENT will be created
based on it.

Cc: Gerd Hoffmann 
Cc: Jiewen Yao 
Cc: Sami Mujawar 
Cc: Jian J Wang 
Reviewed-by: Jiewen Yao 
Signed-off-by: Min Xu 
---
 SecurityPkg/Include/Guid/CcEventHob.h | 22 ++
 SecurityPkg/SecurityPkg.dec   |  4 
 2 files changed, 26 insertions(+)
 create mode 100644 SecurityPkg/Include/Guid/CcEventHob.h

diff --git a/SecurityPkg/Include/Guid/CcEventHob.h 
b/SecurityPkg/Include/Guid/CcEventHob.h
new file mode 100644
index ..072999ce92de
--- /dev/null
+++ b/SecurityPkg/Include/Guid/CcEventHob.h
@@ -0,0 +1,22 @@
+/** @file
+  Defines the HOB GUID used to pass a CC_EVENT from SEC to
+  a CC DXE Driver. A GUIDed HOB is generated for each measurement
+  made in the SEC Phase.
+
+Copyright (c) 2021 - 2022, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef CC_EVENT_HOB_H_
+#define CC_EVENT_HOB_H_
+
+//
+// The Global ID of a GUIDed HOB used to pass a CC_EVENT from SEC to a CC DXE 
Driver.
+//
+#define EFI_CC_EVENT_HOB_GUID \
+  { 0x20f8fd36, 0x6d00, 0x40fb, { 0xb7, 0x04, 0xd1, 0x2c, 0x15, 0x3c, 0x62, 
0xeb } }
+
+extern EFI_GUID  gCcEventEntryHobGuid;
+
+#endif
diff --git a/SecurityPkg/SecurityPkg.dec b/SecurityPkg/SecurityPkg.dec
index 9f7a032d60d5..0ee75efc1a97 100644
--- a/SecurityPkg/SecurityPkg.dec
+++ b/SecurityPkg/SecurityPkg.dec
@@ -136,6 +136,10 @@
   ## Include/Guid/TcgEventHob.h
   gTcgEvent2EntryHobGuid = { 0xd26c221e, 0x2430, 0x4c8a, { 0x91, 
0x70, 0x3f, 0xcb, 0x45, 0x0, 0x41, 0x3f }}
 
+  ## Hob GUID used to pass a CC_EVENT from SEC to a CC DXE Driver.
+  ## Include/Guid/CcEventHob.h
+  gCcEventEntryHobGuid   = { 0x20f8fd36, 0x6d00, 0x40fb, { 0xb7, 
0x04, 0xd1, 0x2c, 0x15, 0x3c, 0x62, 0xeb }}
+
   ## HOB GUID used to record TPM device error.
   #  Include/Guid/TcgEventHob.h
   gTpmErrorHobGuid   = { 0xef598499, 0xb25e, 0x473a, { 0xbf, 
0xaf, 0xe7, 0xe5, 0x7d, 0xce, 0x82, 0xc4 }}
-- 
2.29.2.windows.2



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[edk2-devel] [PATCH V4 2/9] CryptoPkg: Add SecCryptLib

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853

This is the Cryptographic library instance for SEC. The motivation of
this library is to support SHA384 in SEC phase for Td guest. So only
Hash/CryptSha512.c is included which supports SHA384 and SHA512. Other
cryptographics are added with the null version, such as CryptMd5Null.c.

Cc: Jiewen Yao 
Cc: Jian J Wang 
Cc: Xiaoyu Lu 
Cc: Guomin Jiang 
Cc: Gerd Hoffmann 
Reviewed-by: Jiewen Yao 
Signed-off-by: Min Xu 
---
 CryptoPkg/CryptoPkg.dsc   |   4 +
 .../Library/BaseCryptLib/Hash/CryptMd5Null.c  | 163 +
 .../Library/BaseCryptLib/Hash/CryptSha1Null.c | 166 ++
 .../BaseCryptLib/Hash/CryptSha256Null.c   | 162 +
 .../Library/BaseCryptLib/Hash/CryptSm3Null.c  | 164 +
 .../BaseCryptLib/Pk/CryptPkcs7VerifyEkuNull.c | 152 
 .../BaseCryptLib/Pk/CryptRsaBasicNull.c   | 121 +
 .../Library/BaseCryptLib/SecCryptLib.inf  |  91 ++
 8 files changed, 1023 insertions(+)
 create mode 100644 CryptoPkg/Library/BaseCryptLib/Hash/CryptMd5Null.c
 create mode 100644 CryptoPkg/Library/BaseCryptLib/Hash/CryptSha1Null.c
 create mode 100644 CryptoPkg/Library/BaseCryptLib/Hash/CryptSha256Null.c
 create mode 100644 CryptoPkg/Library/BaseCryptLib/Hash/CryptSm3Null.c
 create mode 100644 CryptoPkg/Library/BaseCryptLib/Pk/CryptPkcs7VerifyEkuNull.c
 create mode 100644 CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaBasicNull.c
 create mode 100644 CryptoPkg/Library/BaseCryptLib/SecCryptLib.inf

diff --git a/CryptoPkg/CryptoPkg.dsc b/CryptoPkg/CryptoPkg.dsc
index 06990cb6fc79..50e7721f25b8 100644
--- a/CryptoPkg/CryptoPkg.dsc
+++ b/CryptoPkg/CryptoPkg.dsc
@@ -109,6 +109,9 @@
 [LibraryClasses.ARM]
   ArmSoftFloatLib|ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.inf
 
+[LibraryClasses.common.SEC]
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SecCryptLib.inf
+
 [LibraryClasses.common.PEIM]
   PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
   
ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
@@ -236,6 +239,7 @@
 !if $(CRYPTO_SERVICES) == PACKAGE
 [Components]
   CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
+  CryptoPkg/Library/BaseCryptLib/SecCryptLib.inf
   CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf
   CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf
   CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
diff --git a/CryptoPkg/Library/BaseCryptLib/Hash/CryptMd5Null.c 
b/CryptoPkg/Library/BaseCryptLib/Hash/CryptMd5Null.c
new file mode 100644
index ..893a2302a6de
--- /dev/null
+++ b/CryptoPkg/Library/BaseCryptLib/Hash/CryptMd5Null.c
@@ -0,0 +1,163 @@
+/** @file
+
+MD5 Digest Wrapper Null Implementation.
+
+Copyright (c) Microsoft Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "InternalCryptLib.h"
+
+/**
+  Retrieves the size, in bytes, of the context buffer required for MD5 hash 
operations.
+
+  @return  The size, in bytes, of the context buffer required for MD5 hash 
operations.
+
+**/
+UINTN
+EFIAPI
+Md5GetContextSize (
+  VOID
+  )
+{
+  ASSERT (FALSE);
+  return 0;
+}
+
+/**
+  Initializes user-supplied memory pointed by Md5Context as MD5 hash context 
for
+  subsequent use.
+
+  If Md5Context is NULL, then return FALSE.
+
+  @param[out]  Md5Context  Pointer to MD5 context being initialized.
+
+  @retval TRUE   MD5 context initialization succeeded.
+  @retval FALSE  MD5 context initialization failed.
+
+**/
+BOOLEAN
+EFIAPI
+Md5Init (
+  OUT  VOID  *Md5Context
+  )
+{
+  ASSERT (FALSE);
+  return FALSE;
+}
+
+/**
+  Makes a copy of an existing MD5 context.
+
+  If Md5Context is NULL, then return FALSE.
+  If NewMd5Context is NULL, then return FALSE.
+
+  @param[in]  Md5Context Pointer to MD5 context being copied.
+  @param[out] NewMd5Context  Pointer to new MD5 context.
+
+  @retval TRUE   MD5 context copy succeeded.
+  @retval FALSE  MD5 context copy failed.
+
+**/
+BOOLEAN
+EFIAPI
+Md5Duplicate (
+  IN   CONST VOID  *Md5Context,
+  OUT  VOID*NewMd5Context
+  )
+{
+  ASSERT (FALSE);
+  return FALSE;
+}
+
+/**
+  Digests the input data and updates MD5 context.
+
+  This function performs MD5 digest on a data buffer of the specified size.
+  It can be called multiple times to compute the digest of long or 
discontinuous data streams.
+  MD5 context should be already correctly intialized by Md5Init(), and should 
not be finalized
+  by Md5Final(). Behavior with invalid context is undefined.
+
+  If Md5Context is NULL, then return FALSE.
+
+  @param[in, out]  Md5Context  Pointer to the MD5 context.
+  @param[in]   DataPointer to the buffer containing the data to be 
hashed.
+  @param[in]   DataSizeSize of Data buffer in bytes.
+
+  @retval TRUE   MD5 data digest succeeded.
+  @retval FALSE  MD5 data digest failed.
+
+**/
+BOOLEAN
+EFIAPI
+Md5Update (
+  IN OUT  VOID*Md5Context,
+  IN  CONST VOID  *Data,
+  IN

[edk2-devel] [PATCH V4 1/9] Security: Add HashLibTdx

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853

This library provides hash service by registered hash handler in Td
guest. Currently only SHA384 is supported. After that the hash value is
extended to Td RTMR registers which is similar to TPM PCRs.

Cc: Jiewen Yao 
Cc: Jian J Wang 
Cc: Gerd Hoffmann 
Reviewed-by: Jiewen Yao 
Signed-off-by: Min Xu 
---
 SecurityPkg/Library/HashLibTdx/HashLibTdx.c   | 207 ++
 SecurityPkg/Library/HashLibTdx/HashLibTdx.inf |  37 
 SecurityPkg/SecurityPkg.dsc   |  10 +
 3 files changed, 254 insertions(+)
 create mode 100644 SecurityPkg/Library/HashLibTdx/HashLibTdx.c
 create mode 100644 SecurityPkg/Library/HashLibTdx/HashLibTdx.inf

diff --git a/SecurityPkg/Library/HashLibTdx/HashLibTdx.c 
b/SecurityPkg/Library/HashLibTdx/HashLibTdx.c
new file mode 100644
index ..75d96ee64b44
--- /dev/null
+++ b/SecurityPkg/Library/HashLibTdx/HashLibTdx.c
@@ -0,0 +1,207 @@
+/** @file
+  This library is HashLib for Tdx.
+
+Copyright (c) 2021 - 2022, Intel Corporation. All rights reserved. 
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+EFI_GUID  mSha384Guid = HASH_ALGORITHM_SHA384_GUID;
+
+//
+// Currently TDX supports SHA384.
+//
+HASH_INTERFACE  mHashInterface =  {
+  { 0 }, NULL, NULL, NULL
+};
+
+UINTN  mHashInterfaceCount = 0;
+
+/**
+  Start hash sequence.
+
+  @param HashHandle Hash handle.
+
+  @retval EFI_SUCCESS  Hash sequence start and HandleHandle returned.
+  @retval EFI_OUT_OF_RESOURCES No enough resource to start hash.
+**/
+EFI_STATUS
+EFIAPI
+HashStart (
+  OUT HASH_HANDLE  *HashHandle
+  )
+{
+  HASH_HANDLE  HashCtx;
+
+  if (mHashInterfaceCount == 0) {
+ASSERT (FALSE);
+return EFI_UNSUPPORTED;
+  }
+
+  HashCtx = 0;
+  mHashInterface.HashInit ();
+
+  *HashHandle = HashCtx;
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Update hash sequence data.
+
+  @param HashHandleHash handle.
+  @param DataToHashData to be hashed.
+  @param DataToHashLen Data size.
+
+  @retval EFI_SUCCESS Hash sequence updated.
+**/
+EFI_STATUS
+EFIAPI
+HashUpdate (
+  IN HASH_HANDLE  HashHandle,
+  IN VOID *DataToHash,
+  IN UINTNDataToHashLen
+  )
+{
+  if (mHashInterfaceCount == 0) {
+ASSERT (FALSE);
+return EFI_UNSUPPORTED;
+  }
+
+  mHashInterface.HashUpdate (HashHandle, DataToHash, DataToHashLen);
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Hash sequence complete and extend to PCR.
+
+  @param HashHandleHash handle.
+  @param PcrIndex  PCR to be extended.
+  @param DataToHashData to be hashed.
+  @param DataToHashLen Data size.
+  @param DigestListDigest list.
+
+  @retval EFI_SUCCESS Hash sequence complete and DigestList is returned.
+**/
+EFI_STATUS
+EFIAPI
+HashCompleteAndExtend (
+  IN HASH_HANDLE  HashHandle,
+  IN TPMI_DH_PCR  PcrIndex,
+  IN VOID *DataToHash,
+  IN UINTNDataToHashLen,
+  OUT TPML_DIGEST_VALUES  *DigestList
+  )
+{
+  TPML_DIGEST_VALUES  Digest;
+  EFI_STATUS  Status;
+
+  if (mHashInterfaceCount == 0) {
+ASSERT (FALSE);
+return EFI_UNSUPPORTED;
+  }
+
+  ZeroMem (DigestList, sizeof (*DigestList));
+
+  mHashInterface.HashUpdate (HashHandle, DataToHash, DataToHashLen);
+  mHashInterface.HashFinal (HashHandle, );
+
+  CopyMem (
+>digests[0],
+[0],
+sizeof (Digest.digests[0])
+);
+  DigestList->count++;
+
+  ASSERT (DigestList->count == 1 && DigestList->digests[0].hashAlg == 
TPM_ALG_SHA384);
+
+  Status = TdExtendRtmr (
+ (UINT32 *)DigestList->digests[0].digest.sha384,
+ SHA384_DIGEST_SIZE,
+ (UINT8)PcrIndex
+ );
+
+  ASSERT (!EFI_ERROR (Status));
+  return Status;
+}
+
+/**
+  Hash data and extend to RTMR.
+
+  @param PcrIndex  PCR to be extended.
+  @param DataToHashData to be hashed.
+  @param DataToHashLen Data size.
+  @param DigestListDigest list.
+
+  @retval EFI_SUCCESS Hash data and DigestList is returned.
+**/
+EFI_STATUS
+EFIAPI
+HashAndExtend (
+  IN TPMI_DH_PCR  PcrIndex,
+  IN VOID *DataToHash,
+  IN UINTNDataToHashLen,
+  OUT TPML_DIGEST_VALUES  *DigestList
+  )
+{
+  HASH_HANDLE  HashHandle;
+  EFI_STATUS   Status;
+
+  if (mHashInterfaceCount == 0) {
+ASSERT (FALSE);
+return EFI_UNSUPPORTED;
+  }
+
+  ASSERT (TdIsEnabled ());
+
+  HashStart ();
+  HashUpdate (HashHandle, DataToHash, DataToHashLen);
+  Status = HashCompleteAndExtend (HashHandle, PcrIndex, NULL, 0, DigestList);
+
+  return Status;
+}
+
+/**
+  This service register Hash.
+
+  @param HashInterface  Hash interface
+
+  @retval EFI_SUCCESS  This hash interface is registered successfully.
+  @retval EFI_UNSUPPORTED  System does not support register this interface.
+  @retval EFI_ALREADY_STARTED  System already register this interface.
+**/
+EFI_STATUS
+EFIAPI
+RegisterHashInterfaceLib (
+  

[edk2-devel] [PATCH V4 0/9] Enable RTMR based measurement and measure boot for Td guest

[Min Xu]

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853

Intel's Trust Domain Extensions (Intel TDX) refers to an Intel technology
that extends Virtual Machines Extensions (VMX) and Multi-Key Total Memory
Encryption (MKTME) with a new kind of virutal machines guest called a
Trust Domain (TD). A TD is desinged to run in a CPU mode that protects the
confidentiality of TD memory contents and the TD's CPU state from other
software, including the hosting Virtual-Machine Monitor (VMM), unless
explicitly shared by the TD itself.

There are 2 configurations for TDVF to upstream. See below link for
the definitions of the 2 configurations.
https://edk2.groups.io/g/devel/message/76367

This patch-set is to enable below features of Config-B in OvmfPkg.
 - Enable RTMR based measurement and measured boot
 - Install CC_MEASUREMENT_PROTOCOL instance in Td guest

The measurement for the other components, such as kernel image, initrd,
will be introduced in the following patch-sets.

Patch 1:
HashLibTdx provides SHA384 service and extend to RTMR registers.

Patch 2:
SecCryptLib is the cryptographic library instance for SEC.

Patch 3 - 8:
These 6 patches are related to RTMR based measurement and
CC Eventlog ACPI table.

Patch 9:
Update IntelTdxX64.dsc/IntelTdxX64.fdf to support RTMR based
measurement and measured boot.

Code at: https://github.com/mxu9/edk2/tree/tdvf_wave4.v4

v4 changes:
 - Update Rsvd field in EFI_CC_EVENTLOG_ACPI_TABLE to UINT16.
 - Rebase EDK2 code base. (commit: 708620d29db8)

v3 changes:
 - Refine HashLibBaseCryptoRouterTdx to HashLibTdx
 - Add NULL version algorithms in SecCryptLib.
 - Add SecMeasurementLib which does the measurement in SEC phase.
 - Rebase EDK2 code base. (commit: 91a03f78ba)

v2 changes:
 - Move the definition of EFI_CC_EVENT_HOB_GUID from MdePkg to
   SecurityPkg.
 - Update the definition of EFI_CC_EVENTLOG_ACPI_TABLE based
   on below discussion:
   https://edk2.groups.io/g/devel/message/87396
   https://edk2.groups.io/g/devel/message/87402
 - Update the code base to 94f905b3bf.


Min Xu (9):
  Security: Add HashLibTdx
  CryptoPkg: Add SecCryptLib
  SecurityPkg: Add definition of EFI_CC_EVENT_HOB_GUID
  OvmfPkg: Introduce SecMeasurementLib
  OvmfPkg/IntelTdx: Measure Td HobList and Configuration FV
  OvmfPkg: Add PCDs for LAML/LASA field in CC EVENTLOG ACPI table
  MdePkg: Define CC Measure EventLog ACPI Table
  OvmfPkg/IntelTdx: Add TdTcg2Dxe
  OvmfPkg/IntelTdx: Enable RTMR based measurement and measure boot

 CryptoPkg/CryptoPkg.dsc   |4 +
 .../Library/BaseCryptLib/Hash/CryptMd5Null.c  |  163 ++
 .../Library/BaseCryptLib/Hash/CryptSha1Null.c |  166 ++
 .../BaseCryptLib/Hash/CryptSha256Null.c   |  162 ++
 .../Library/BaseCryptLib/Hash/CryptSm3Null.c  |  164 ++
 .../BaseCryptLib/Pk/CryptPkcs7VerifyEkuNull.c |  152 +
 .../BaseCryptLib/Pk/CryptRsaBasicNull.c   |  121 +
 .../Library/BaseCryptLib/SecCryptLib.inf  |   91 +
 MdePkg/Include/Protocol/CcMeasurement.h   |   21 +
 OvmfPkg/Include/Library/SecMeasurementLib.h   |   46 +
 OvmfPkg/IntelTdx/IntelTdxX64.dsc  |   16 +-
 OvmfPkg/IntelTdx/IntelTdxX64.fdf  |5 +
 .../IntelTdx/TdTcg2Dxe/MeasureBootPeCoff.c|  407 +++
 OvmfPkg/IntelTdx/TdTcg2Dxe/TdTcg2Dxe.c| 2489 +
 OvmfPkg/IntelTdx/TdTcg2Dxe/TdTcg2Dxe.inf  |  101 +
 OvmfPkg/Library/PeilessStartupLib/IntelTdx.c  |  163 ++
 .../PeilessStartupLib/PeilessStartup.c|   31 +
 .../PeilessStartupInternal.h  |   17 +
 .../PeilessStartupLib/PeilessStartupLib.inf   |8 +-
 .../SecMeasurementLib/SecMeasurementLibTdx.c  |  340 +++
 .../SecMeasurementLibTdx.inf  |   30 +
 OvmfPkg/OvmfPkg.dec   |   10 +
 SecurityPkg/Include/Guid/CcEventHob.h |   22 +
 SecurityPkg/Library/HashLibTdx/HashLibTdx.c   |  207 ++
 SecurityPkg/Library/HashLibTdx/HashLibTdx.inf |   37 +
 SecurityPkg/SecurityPkg.dec   |4 +
 SecurityPkg/SecurityPkg.dsc   |   10 +
 27 files changed, 4984 insertions(+), 3 deletions(-)
 create mode 100644 CryptoPkg/Library/BaseCryptLib/Hash/CryptMd5Null.c
 create mode 100644 CryptoPkg/Library/BaseCryptLib/Hash/CryptSha1Null.c
 create mode 100644 CryptoPkg/Library/BaseCryptLib/Hash/CryptSha256Null.c
 create mode 100644 CryptoPkg/Library/BaseCryptLib/Hash/CryptSm3Null.c
 create mode 100644 CryptoPkg/Library/BaseCryptLib/Pk/CryptPkcs7VerifyEkuNull.c
 create mode 100644 CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaBasicNull.c
 create mode 100644 CryptoPkg/Library/BaseCryptLib/SecCryptLib.inf
 create mode 100644 OvmfPkg/Include/Library/SecMeasurementLib.h
 create mode 100644 OvmfPkg/IntelTdx/TdTcg2Dxe/MeasureBootPeCoff.c
 create mode 100644 OvmfPkg/IntelTdx/TdTcg2Dxe/TdTcg2Dxe.c
 create mode 100644 OvmfPkg/IntelTdx/TdTcg2Dxe/TdTcg2Dxe.inf
 create mode 100644 OvmfPkg/Library/PeilessStartupLib/IntelTdx.c
 create mode 100644 OvmfPkg/Library/SecMeasurementLib/SecMeasurementLibTdx.c
 create mode 100644 

Re: [edk2-devel] [PATCH] MdeModulePkg/FaultTolerantWriteDxe: Don't check for address alignment

[Wu, Hao A]

Sorry for not being clear on what I mean.
Is it possible to change the platform PCD values and keep these block size 
alignment requirements.

Best Regards,
Hao Wu

From: devel@edk2.groups.io  On Behalf Of Sean Rhodes
Sent: Monday, May 16, 2022 3:00 PM
To: Wu; Wu, Hao A ; devel@edk2.groups.io
Subject: Re: [edk2-devel] [PATCH] MdeModulePkg/FaultTolerantWriteDxe: Don't 
check for address alignment

Hi Hao

Yes, it does conflict - I will update the patch to fix these comments :)

Thank you



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[edk2-devel] [PATCH v3 1/5] MpInitLib: Allocate code buffer for PEI phase

[Ni, Ray]

Today's implementation assumes PEI phase runs at 32bit so
the execution-disable feature is not applicable.
It's not always TRUE.
The patch allocates 32bit&64bit code buffer for PEI phase as well.

Signed-off-by: Ray Ni 
Cc: Eric Dong 
---
 UefiCpuPkg/Library/MpInitLib/DxeMpLib.c |  2 +-
 UefiCpuPkg/Library/MpInitLib/MpLib.c|  2 +-
 UefiCpuPkg/Library/MpInitLib/MpLib.h|  2 +-
 UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 15 ++-
 4 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c 
b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
index 60d14a5a0e..78cc3e2b93 100644
--- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
@@ -162,7 +162,7 @@ GetWakeupBuffer (
   @retval 0   Cannot find free memory below 4GB.
 **/
 UINTN
-GetModeTransitionBuffer (
+AllocateCodeBuffer (
   IN UINTN  BufferSize
   )
 {
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c 
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index 4a73787ee4..d761bdc487 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -1056,7 +1056,7 @@ AllocateResetVector (
(CpuMpData->WakeupBuffer +
 CpuMpData->AddressMap.RendezvousFunnelSize 
+
 CpuMpData->AddressMap.SwitchToRealSize);
-CpuMpData->WakeupBufferHigh = GetModeTransitionBuffer (
+CpuMpData->WakeupBufferHigh = AllocateCodeBuffer (
 CpuMpData->AddressMap.RendezvousFunnelSize 
+
 CpuMpData->AddressMap.SwitchToRealSize -
 CpuMpData->AddressMap.ModeTransitionOffset
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h 
b/UefiCpuPkg/Library/MpInitLib/MpLib.h
index f8c52426dd..59ab960897 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.h
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h
@@ -442,7 +442,7 @@ GetWakeupBuffer (
   @retval 0   Cannot find free memory below 4GB.
 **/
 UINTN
-GetModeTransitionBuffer (
+AllocateCodeBuffer (
   IN UINTN  BufferSize
   );
 
diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c 
b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
index efce574727..65400b95a2 100644
--- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
@@ -299,14 +299,19 @@ GetWakeupBuffer (
   @retval 0   Cannot find free memory below 4GB.
 **/
 UINTN
-GetModeTransitionBuffer (
+AllocateCodeBuffer (
   IN UINTN  BufferSize
   )
 {
-  //
-  // PEI phase doesn't need to do such transition. So simply return 0.
-  //
-  return 0;
+  EFI_STATUSStatus;
+  EFI_PHYSICAL_ADDRESS  Address;
+
+  Status = PeiServicesAllocatePages (EfiBootServicesCode, EFI_SIZE_TO_PAGES 
(BufferSize), );
+  if (EFI_ERROR (Status)) {
+Address = 0;
+  }
+
+  return (UINTN)Address;
 }
 
 /**
-- 
2.35.1.windows.2



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[edk2-devel] [PATCH v3 5/5] MpInitLib: Move the Above1Mb vector allocation to MpInitLibInitialize

[Ni, Ray]

The AP vector consists of 2 parts:
1. the initial 16-bit code that should be under 1MB and page aligned.
2. the 32-bit/64-bit code that can be anywhere in the memory with any
   alignment.

The need of part #2 is because the memory under 1MB is temporary
"stolen" for use and will "give" back after all AP wake up. The range
of memory is not marked as code page in page table. CPU may trigger
exception as soon as NX is enabled.

The part #2 memory allocation can be done in the MpInitLibInitialize.

Signed-off-by: Ray Ni 
Cc: Eric Dong 
---
 UefiCpuPkg/Library/MpInitLib/MpLib.c | 53 +++-
 1 file changed, 29 insertions(+), 24 deletions(-)

diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c 
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index e4edbb618d..66e0f94f03 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -955,18 +955,6 @@ FillExchangeInfoData (
 Size -= sizeof (IA32_SEGMENT_DESCRIPTOR);
   }
 
-  //
-  // Copy all 32-bit code and 64-bit code into memory with type of
-  // EfiBootServicesCode to avoid page fault if NX memory protection is 
enabled.
-  //
-  GetApResetVectorSize (>AddressMap, NULL, );
-  CopyMem (
-(VOID *)CpuMpData->WakeupBufferHigh,
-CpuMpData->AddressMap.RendezvousFunnelAddress +
-CpuMpData->AddressMap.ModeTransitionOffset,
-Size
-);
-
   ExchangeInfo->ModeTransitionMemory = (UINT32)CpuMpData->WakeupBufferHigh;
 
   ExchangeInfo->ModeHighMemory = ExchangeInfo->ModeTransitionMemory +
@@ -1035,21 +1023,24 @@ RestoreWakeupBuffer (
   @param[in, out]  CpuMpData  The pointer to CPU MP Data structure.
 **/
 VOID
-AllocateResetVector (
+AllocateResetVectorBelow1Mb (
   IN OUT CPU_MP_DATA  *CpuMpData
   )
 {
-  UINTN  ApResetVectorSizeBelow1Mb;
-  UINTN  ApResetVectorSizeAbove1Mb;
   UINTN  ApResetStackSize;
 
   if (CpuMpData->WakeupBuffer == (UINTN)-1) {
-GetApResetVectorSize (>AddressMap, , 
);
-
-CpuMpData->WakeupBuffer  = GetWakeupBuffer (ApResetVectorSizeBelow1Mb);
+CpuMpData->WakeupBuffer  = GetWakeupBuffer 
(CpuMpData->BackupBufferSize);
 CpuMpData->MpCpuExchangeInfo = (MP_CPU_EXCHANGE_INFO *)(UINTN)
-   (CpuMpData->WakeupBuffer + 
ApResetVectorSizeBelow1Mb - sizeof (MP_CPU_EXCHANGE_INFO));
-CpuMpData->WakeupBufferHigh = AllocateCodeBuffer 
(ApResetVectorSizeAbove1Mb);
+   (CpuMpData->WakeupBuffer + 
CpuMpData->BackupBufferSize - sizeof (MP_CPU_EXCHANGE_INFO));
+DEBUG ((
+  DEBUG_INFO,
+  "AP Vector: 16-bit = %p/%x, ExchangeInfo = %p/%x\n",
+  CpuMpData->WakeupBuffer,
+  CpuMpData->BackupBufferSize - sizeof (MP_CPU_EXCHANGE_INFO),
+  CpuMpData->MpCpuExchangeInfo,
+  sizeof (MP_CPU_EXCHANGE_INFO)
+  ));
 //
 // The AP reset stack is only used by SEV-ES guests. Do not allocate it
 // if SEV-ES is not enabled. An SEV-SNP guest is also considered
@@ -1148,7 +1139,7 @@ WakeUpAP (
   (CpuMpData->InitFlag   != ApInitDone))
   {
 ResetVectorRequired = TRUE;
-AllocateResetVector (CpuMpData);
+AllocateResetVectorBelow1Mb (CpuMpData);
 AllocateSevEsAPMemory (CpuMpData);
 FillExchangeInfoData (CpuMpData);
 SaveLocalApicTimerSetting (CpuMpData);
@@ -1789,6 +1780,7 @@ MpInitLibInitialize (
   UINT8*MonitorBuffer;
   UINTNIndex;
   UINTNApResetVectorSizeBelow1Mb;
+  UINTNApResetVectorSizeAbove1Mb;
   UINTNBackupBufferAddr;
   UINTNApIdtBase;
 
@@ -1802,9 +1794,9 @@ MpInitLibInitialize (
   ASSERT (MaxLogicalProcessorNumber != 0);
 
   AsmGetAddressMap ();
-  GetApResetVectorSize (, , NULL);
-  ApStackSize   = PcdGet32 (PcdCpuApStackSize);
-  ApLoopMode= GetApLoopMode ();
+  GetApResetVectorSize (, , 
);
+  ApStackSize = PcdGet32 (PcdCpuApStackSize);
+  ApLoopMode  = GetApLoopMode ();
 
   //
   // Save BSP's Control registers for APs.
@@ -1913,6 +1905,19 @@ MpInitLibInitialize (
   (UINT32 *)(MonitorBuffer + MonitorFilterSize * Index);
   }
 
+  //
+  // Copy all 32-bit code and 64-bit code into memory with type of
+  // EfiBootServicesCode to avoid page fault if NX memory protection is 
enabled.
+  //
+  CpuMpData->WakeupBufferHigh = AllocateCodeBuffer (ApResetVectorSizeAbove1Mb);
+  CopyMem (
+(VOID *)CpuMpData->WakeupBufferHigh,
+CpuMpData->AddressMap.RendezvousFunnelAddress +
+CpuMpData->AddressMap.ModeTransitionOffset,
+ApResetVectorSizeAbove1Mb
+);
+  DEBUG ((DEBUG_INFO, "AP Vector: non-16-bit = %p/%x\n", 
CpuMpData->WakeupBufferHigh, ApResetVectorSizeAbove1Mb));
+
   //
   // Enable the local APIC for Virtual Wire Mode.
   //
-- 
2.35.1.windows.2



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[edk2-devel] [PATCH v3 2/5] MpInitLib: remove unneeded global ASM_PFX

[Ni, Ray]

global in NASM file is used for symbols that are
referenced in C files.
Remove unneeded global keyword in NASM file.

Signed-off-by: Ray Ni 
---
 UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm |  8 +---
 UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm  | 10 ++
 2 files changed, 3 insertions(+), 15 deletions(-)

diff --git a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm 
b/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm
index 7bd2415670..8981c32722 100644
--- a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm
+++ b/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm
@@ -1,5 +1,5 @@
 
;-- 
;
-; Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
+; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
 ; SPDX-License-Identifier: BSD-2-Clause-Patent
 ;
 ; Module Name:
@@ -24,8 +24,6 @@ SECTION .text
 ;ALSO THIS PROCEDURE IS EXECUTED BY APs ONLY ON 16 BIT MODE. HENCE THIS PROC
 ;IS IN MACHINE CODE.
 
;-
-global ASM_PFX(RendezvousFunnelProc)
-ASM_PFX(RendezvousFunnelProc):
 RendezvousFunnelProcStart:
 ; At this point CS = 0x(vv00) and ip= 0x0.
 BITS 16
@@ -207,8 +205,6 @@ RendezvousFunnelProcEnd:
 ;SwitchToRealProc procedure follows.
 ;NOT USED IN 32 BIT MODE.
 
;-
-global ASM_PFX(SwitchToRealProc)
-ASM_PFX(SwitchToRealProc):
 SwitchToRealProcStart:
 jmp$ ; Never reach here
 SwitchToRealProcEnd:
@@ -219,8 +215,6 @@ SwitchToRealProcEnd:
 ;  The last three parameters (Pm16CodeSegment, SevEsAPJumpTable and 
WakeupBuffer) are
 ;  specific to SEV-ES support and are not applicable on IA32.
 
;-
-global ASM_PFX(AsmRelocateApLoop)
-ASM_PFX(AsmRelocateApLoop):
 AsmRelocateApLoopStart:
 moveax, esp
 movesp, [eax + 16] ; TopOfApStack
diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm 
b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm
index f1422fd30a..d7e0e1fabd 100644
--- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm
+++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm
@@ -35,8 +35,6 @@ SECTION .text
 ;ALSO THIS PROCEDURE IS EXECUTED BY APs ONLY ON 16 BIT MODE. HENCE THIS PROC
 ;IS IN MACHINE CODE.
 
;-
-global ASM_PFX(RendezvousFunnelProc)
-ASM_PFX(RendezvousFunnelProc):
 RendezvousFunnelProcStart:
 ; At this point CS = 0x(vv00) and ip= 0x0.
 ; Save BIST information to ebp firstly
@@ -279,8 +277,6 @@ RendezvousFunnelProcEnd:
 ;  r8  - Code32 Selector Offset
 ;  r9  - Stack Start
 
;-
-global ASM_PFX(SwitchToRealProc)
-ASM_PFX(SwitchToRealProc):
 SwitchToRealProcStart:
 BITS 64
 cli
@@ -421,8 +417,6 @@ SwitchToRealProcEnd:
 
;-
 ;  AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, 
TopOfApStack, CountTofinish, Pm16CodeSegment, SevEsAPJumpTable, WakeupBuffer);
 
;-
-global ASM_PFX(AsmRelocateApLoop)
-ASM_PFX(AsmRelocateApLoop):
 AsmRelocateApLoopStart:
 BITS 64
 cmpqword [rsp + 56], 0  ; SevEsAPJumpTable
@@ -594,11 +588,11 @@ AsmRelocateApLoopEnd:
 
;-
 global ASM_PFX(AsmGetAddressMap)
 ASM_PFX(AsmGetAddressMap):
-learax, [ASM_PFX(RendezvousFunnelProc)]
+learax, [RendezvousFunnelProcStart]
 movqword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RendezvousFunnelAddress], 
rax
 movqword [rcx + MP_ASSEMBLY_ADDRESS_MAP.ModeEntryOffset], 
LongModeStart - RendezvousFunnelProcStart
 movqword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RendezvousFunnelSize], 
RendezvousFunnelProcEnd - RendezvousFunnelProcStart
-learax, [ASM_PFX(AsmRelocateApLoop)]
+learax, [AsmRelocateApLoopStart]
 movqword [rcx + 
MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncAddress], rax
 movqword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncSize], 
AsmRelocateApLoopEnd - AsmRelocateApLoopStart
 movqword [rcx + MP_ASSEMBLY_ADDRESS_MAP.ModeTransitionOffset], 
Flat32Start - RendezvousFunnelProcStart
-- 
2.35.1.windows.2



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[edk2-devel] [PATCH v3 4/5] MpInitLib: Only allocate below 1MB memory for 16bit code

[Ni, Ray]

Today's implementation allocates below 1MB memory for the 16bit, 32bit
and 64bit code.

But it's not necessary since now the 32bit and 64bit code run at high
memory no matter in PEI and DXE phase.

The patch simplifies the logic to remove the code that handles the
case when WakeupBufferHigh is 0.
It also reduce the memory foot print under 1MB by allocating
memory for 16bit code only.

MP_CPU_EXCHANGE_INFO is still under 1MB which is immediate
after the 16bit code.

Signed-off-by: Ray Ni 
Cc: Eric Dong 
---
 UefiCpuPkg/Library/MpInitLib/AmdSev.c  |  6 +-
 UefiCpuPkg/Library/MpInitLib/MpEqu.inc |  2 +-
 UefiCpuPkg/Library/MpInitLib/MpLib.c   | 94 --
 3 files changed, 46 insertions(+), 56 deletions(-)

diff --git a/UefiCpuPkg/Library/MpInitLib/AmdSev.c 
b/UefiCpuPkg/Library/MpInitLib/AmdSev.c
index b4a344ee6b..4e4c63a52d 100644
--- a/UefiCpuPkg/Library/MpInitLib/AmdSev.c
+++ b/UefiCpuPkg/Library/MpInitLib/AmdSev.c
@@ -110,11 +110,7 @@ MpInitLibSevEsAPReset (
   Code16 = GetProtectedMode16CS ();
   Code32 = GetProtectedMode32CS ();
 
-  if (CpuMpData->WakeupBufferHigh != 0) {
-APResetFn = (AP_RESET *)(CpuMpData->WakeupBufferHigh + 
CpuMpData->AddressMap.SwitchToRealNoNxOffset);
-  } else {
-APResetFn = (AP_RESET *)(CpuMpData->MpCpuExchangeInfo->BufferStart + 
CpuMpData->AddressMap.SwitchToRealOffset);
-  }
+  APResetFn = (AP_RESET *)(CpuMpData->WakeupBufferHigh + 
CpuMpData->AddressMap.SwitchToRealNoNxOffset);
 
   BufferStart = CpuMpData->MpCpuExchangeInfo->BufferStart;
   StackStart  = CpuMpData->SevEsAPResetStackStart -
diff --git a/UefiCpuPkg/Library/MpInitLib/MpEqu.inc 
b/UefiCpuPkg/Library/MpInitLib/MpEqu.inc
index 1cc071cf7b..ebadcc6fb3 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpEqu.inc
+++ b/UefiCpuPkg/Library/MpInitLib/MpEqu.inc
@@ -95,5 +95,5 @@ struc MP_CPU_EXCHANGE_INFO
   .ExtTopoAvail: CTYPE_BOOLEAN 1
 endstruc
 
-MP_CPU_EXCHANGE_INFO_OFFSET equ (SwitchToRealProcEnd - 
RendezvousFunnelProcStart)
+MP_CPU_EXCHANGE_INFO_OFFSET equ (Flat32Start - RendezvousFunnelProcStart)
 %define MP_CPU_EXCHANGE_INFO_FIELD(Field) (MP_CPU_EXCHANGE_INFO_OFFSET + 
MP_CPU_EXCHANGE_INFO. %+ Field)
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c 
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index aa0eb9a70b..e4edbb618d 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -848,6 +848,30 @@ WaitApWakeup (
   }
 }
 
+/**
+  Calculate the size of the reset vector.
+
+  @param[in]  AddressMap  The pointer to Address Map structure.
+
+  @return Total amount of memory required for the AP reset area
+**/
+STATIC
+VOID
+GetApResetVectorSize (
+  IN  MP_ASSEMBLY_ADDRESS_MAP  *AddressMap,
+  OUT UINTN*SizeBelow1Mb OPTIONAL,
+  OUT UINTN*SizeAbove1Mb OPTIONAL
+  )
+{
+  if (SizeBelow1Mb != NULL) {
+*SizeBelow1Mb = AddressMap->ModeTransitionOffset + sizeof 
(MP_CPU_EXCHANGE_INFO);
+  }
+
+  if (SizeAbove1Mb != NULL) {
+*SizeAbove1Mb = AddressMap->RendezvousFunnelSize - 
AddressMap->ModeTransitionOffset;
+  }
+}
+
 /**
   This function will fill the exchange info structure.
 
@@ -935,21 +959,15 @@ FillExchangeInfoData (
   // Copy all 32-bit code and 64-bit code into memory with type of
   // EfiBootServicesCode to avoid page fault if NX memory protection is 
enabled.
   //
-  if (CpuMpData->WakeupBufferHigh != 0) {
-Size = CpuMpData->AddressMap.RendezvousFunnelSize -
-   CpuMpData->AddressMap.ModeTransitionOffset;
-CopyMem (
-  (VOID *)CpuMpData->WakeupBufferHigh,
-  CpuMpData->AddressMap.RendezvousFunnelAddress +
-  CpuMpData->AddressMap.ModeTransitionOffset,
-  Size
-  );
+  GetApResetVectorSize (>AddressMap, NULL, );
+  CopyMem (
+(VOID *)CpuMpData->WakeupBufferHigh,
+CpuMpData->AddressMap.RendezvousFunnelAddress +
+CpuMpData->AddressMap.ModeTransitionOffset,
+Size
+);
 
-ExchangeInfo->ModeTransitionMemory = (UINT32)CpuMpData->WakeupBufferHigh;
-  } else {
-ExchangeInfo->ModeTransitionMemory = (UINT32)
- (ExchangeInfo->BufferStart + 
CpuMpData->AddressMap.ModeTransitionOffset);
-  }
+  ExchangeInfo->ModeTransitionMemory = (UINT32)CpuMpData->WakeupBufferHigh;
 
   ExchangeInfo->ModeHighMemory = ExchangeInfo->ModeTransitionMemory +
  (UINT32)ExchangeInfo->ModeOffset -
@@ -990,7 +1008,7 @@ BackupAndPrepareWakeupBuffer (
   CopyMem (
 (VOID *)CpuMpData->WakeupBuffer,
 (VOID *)CpuMpData->AddressMap.RendezvousFunnelAddress,
-CpuMpData->AddressMap.RendezvousFunnelSize
+CpuMpData->BackupBufferSize - sizeof (MP_CPU_EXCHANGE_INFO)
 );
 }
 
@@ -1011,27 +1029,6 @@ RestoreWakeupBuffer (
 );
 }
 
-/**
-  Calculate the size of the reset vector.
-
-  @param[in]  AddressMap  The pointer to Address Map structure.
-
-  @return Total amount of memory required for the AP reset area
-**/
-STATIC
-UINTN
-GetApResetVectorSize (
-  

[edk2-devel] [PATCH v3 3/5] MpInitLib: Put SEV logic in separate file

[Ni, Ray]

The patch does several simplifications:
1. Treat SwitchToRealProc as part of RendezvousFunnelProc.
   So the common logic in MpLib.c doesn't need to be aware of
   SwitchToRealProc.
   As a result, SwitchToRealSize/Offset are removed from
   MP_ASSEMBLY_ADDRESS_MAP.

2. Move SwitchToRealProc to AmdSev.nasm.
   All other assembly code in AmdSev.nasm is called through
   OneTimeCall.

Signed-off-by: Ray Ni 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Michael Roth 
Cc: James Bottomley 
Cc: Min Xu 
Cc: Jiewen Yao 
Cc: Tom Lendacky 
Cc: Jordan Justen 
Cc: Ard Biesheuvel 
Cc: Erdem Aktas 
Cc: Gerd Hoffmann 
---
 .../Library/MpInitLib/Ia32/MpFuncs.nasm   |   5 +-
 UefiCpuPkg/Library/MpInitLib/MpEqu.inc|   4 +-
 UefiCpuPkg/Library/MpInitLib/MpLib.c  |  13 +-
 UefiCpuPkg/Library/MpInitLib/MpLib.h  |   4 +-
 UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm  | 148 
 UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 159 +-
 6 files changed, 161 insertions(+), 172 deletions(-)

diff --git a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm 
b/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm
index 8981c32722..28301bb8f0 100644
--- a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm
+++ b/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm
@@ -199,7 +199,6 @@ CProcedureInvoke:
 call   eax   ; Invoke C function
 
 jmp$ ; Never reach here
-RendezvousFunnelProcEnd:
 
 
;-
 ;SwitchToRealProc procedure follows.
@@ -209,6 +208,8 @@ SwitchToRealProcStart:
 jmp$ ; Never reach here
 SwitchToRealProcEnd:
 
+RendezvousFunnelProcEnd:
+
 
;-
 ;  AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, 
TopOfApStack, CountTofinish, Pm16CodeSegment, SevEsAPJumpTable, WakeupBuffer);
 ;
@@ -258,8 +259,6 @@ ASM_PFX(AsmGetAddressMap):
 movdword [ebx + 
MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncAddress], AsmRelocateApLoopStart
 movdword [ebx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncSize], 
AsmRelocateApLoopEnd - AsmRelocateApLoopStart
 movdword [ebx + MP_ASSEMBLY_ADDRESS_MAP.ModeTransitionOffset], 
Flat32Start - RendezvousFunnelProcStart
-movdword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealSize], 
SwitchToRealProcEnd - SwitchToRealProcStart
-movdword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealOffset], 
SwitchToRealProcStart - RendezvousFunnelProcStart
 movdword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealNoNxOffset], 
SwitchToRealProcStart - Flat32Start
 movdword [ebx + 
MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeOffset], 0
 movdword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeSize], 0
diff --git a/UefiCpuPkg/Library/MpInitLib/MpEqu.inc 
b/UefiCpuPkg/Library/MpInitLib/MpEqu.inc
index aba53f5720..1cc071cf7b 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpEqu.inc
+++ b/UefiCpuPkg/Library/MpInitLib/MpEqu.inc
@@ -1,5 +1,5 @@
 
;-- 
;
-; Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
+; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
 ; SPDX-License-Identifier: BSD-2-Clause-Patent
 ;
 ; Module Name:
@@ -27,8 +27,6 @@ struc MP_ASSEMBLY_ADDRESS_MAP
   .RelocateApLoopFuncAddress CTYPE_UINTN 1
   .RelocateApLoopFuncSizeCTYPE_UINTN 1
   .ModeTransitionOffset  CTYPE_UINTN 1
-  .SwitchToRealSize  CTYPE_UINTN 1
-  .SwitchToRealOffsetCTYPE_UINTN 1
   .SwitchToRealNoNxOffsetCTYPE_UINTN 1
   .SwitchToRealPM16ModeOffsetCTYPE_UINTN 1
   .SwitchToRealPM16ModeSize  CTYPE_UINTN 1
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c 
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index d761bdc487..aa0eb9a70b 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -936,8 +936,7 @@ FillExchangeInfoData (
   // EfiBootServicesCode to avoid page fault if NX memory protection is 
enabled.
   //
   if (CpuMpData->WakeupBufferHigh != 0) {
-Size = CpuMpData->AddressMap.RendezvousFunnelSize +
-   CpuMpData->AddressMap.SwitchToRealSize -
+Size = CpuMpData->AddressMap.RendezvousFunnelSize -
CpuMpData->AddressMap.ModeTransitionOffset;
 CopyMem (
   (VOID *)CpuMpData->WakeupBufferHigh,
@@ -991,8 +990,7 @@ BackupAndPrepareWakeupBuffer (
   CopyMem (
 (VOID *)CpuMpData->WakeupBuffer,
 (VOID *)CpuMpData->AddressMap.RendezvousFunnelAddress,
-CpuMpData->AddressMap.RendezvousFunnelSize +
-CpuMpData->AddressMap.SwitchToRealSize
+CpuMpData->AddressMap.RendezvousFunnelSize
 );
 }
 
@@ -1029,7 +1027,6 @@ GetApResetVectorSize (
   UINTN  Size;
 
   Size = AddressMap->RendezvousFunnelSize +
- AddressMap->SwitchToRealSize +
  

[edk2-devel] [PATCH v3 0/5] MpInitLib code refactoring

[Ni, Ray]

v2:
  Updated 3/5: "Put SEV logic in separate file" patch.
  Added 5/5: "Move the Above1Mb vector allocation to MpInitLibInitialize" patch.

v3:
  v2 was sent to wrong mailing list "edk2-de...@lists.01.org".
  v3 is created to send to correct mailing list.
  All code changes are in https://github.com/niruiyu/edk2/tree/refactormp3.

Ray Ni (5):
  MpInitLib: Allocate code buffer for PEI phase
  MpInitLib: remove unneeded global ASM_PFX
  MpInitLib: Put SEV logic in separate file
  MpInitLib: Only allocate below 1MB memory for 16bit code
  MpInitLib: Move the Above1Mb vector allocation to MpInitLibInitialize

 UefiCpuPkg/Library/MpInitLib/AmdSev.c |   6 +-
 UefiCpuPkg/Library/MpInitLib/DxeMpLib.c   |   2 +-
 .../Library/MpInitLib/Ia32/MpFuncs.nasm   |  13 +-
 UefiCpuPkg/Library/MpInitLib/MpEqu.inc|   6 +-
 UefiCpuPkg/Library/MpInitLib/MpLib.c  | 124 ++---
 UefiCpuPkg/Library/MpInitLib/MpLib.h  |   6 +-
 UefiCpuPkg/Library/MpInitLib/PeiMpLib.c   |  15 +-
 UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm  | 148 +++
 UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 169 +-
 9 files changed, 233 insertions(+), 256 deletions(-)

-- 
2.35.1.windows.2



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[edk2-devel] [PATCH] MdeModulePkg/FaultTolerantWriteDxe: Don't check for address alignment

[Sean Rhodes]

WorkSpaceAddress and SpareAreaAddress point into MMIO, which isn't
always aligned. Remove the check for block alignment to avoid
false assertions.

Signed-off-by: Sean Rhodes 
Change-Id: Ia1c1f44b6a0e7f32cac0d7806e74d729e5d83a6d
---
 MdeModulePkg/MdeModulePkg.dec |  2 --
 MdeModulePkg/MdeModulePkg.uni |  4 ++--
 .../Universal/FaultTolerantWriteDxe/FtwMisc.c | 20 ---
 3 files changed, 10 insertions(+), 16 deletions(-)

diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec
index cf79292ec8..b7e2f48028 100644
--- a/MdeModulePkg/MdeModulePkg.dec
+++ b/MdeModulePkg/MdeModulePkg.dec
@@ -1649,7 +1649,6 @@
   
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x0|UINT32|0x3014
 
   ## Base address of the FTW working block range in flash device.
-  # If PcdFlashNvStorageFtwWorkingSize is larger than one block size, this 
value should be block size aligned.
   # @Prompt Base address of flash FTW working block range.
   
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0|UINT32|0x3010
 
@@ -1668,7 +1667,6 @@
   
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x0|UINT64|0x8013
 
   ## 64-bit Base address of the FTW working block range in flash device.
-  # If PcdFlashNvStorageFtwWorkingSize is larger than one block size, this 
value should be block size aligned.
   # @Prompt 64-bit Base address of flash FTW working block range.
   
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x0|UINT64|0x8010
 
diff --git a/MdeModulePkg/MdeModulePkg.uni b/MdeModulePkg/MdeModulePkg.uni
index b070f15ff2..9f916506f7 100644
--- a/MdeModulePkg/MdeModulePkg.uni
+++ b/MdeModulePkg/MdeModulePkg.uni
@@ -374,7 +374,7 @@
 
 #string 
STR_gEfiMdeModulePkgTokenSpaceGuid_PcdFlashNvStorageFtwWorkingBase_PROMPT  
#language en-US "Base address of flash FTW working block range"
 
-#string 
STR_gEfiMdeModulePkgTokenSpaceGuid_PcdFlashNvStorageFtwWorkingBase_HELP  
#language en-US "Base address of the FTW working block range in flash device. 
If PcdFlashNvStorageFtwWorkingSize is larger than one block size, this value 
should be block size aligned."
+#string 
STR_gEfiMdeModulePkgTokenSpaceGuid_PcdFlashNvStorageFtwWorkingBase_HELP  
#language en-US "Base address of the FTW working block range in flash device."
 
 #string 
STR_gEfiMdeModulePkgTokenSpaceGuid_PcdFlashNvStorageFtwWorkingSize_PROMPT  
#language en-US "Size of flash FTW working block range"
 
@@ -390,7 +390,7 @@
 
 #string 
STR_gEfiMdeModulePkgTokenSpaceGuid_PcdFlashNvStorageFtwWorkingBase64_PROMPT  
#language en-US "64-bit Base address of flash FTW working block range"
 
-#string 
STR_gEfiMdeModulePkgTokenSpaceGuid_PcdFlashNvStorageFtwWorkingBase64_HELP  
#language en-US "64-bit Base address of the FTW working block range in flash 
device. If PcdFlashNvStorageFtwWorkingSize is larger than one block size, this 
value should be block size aligned."
+#string 
STR_gEfiMdeModulePkgTokenSpaceGuid_PcdFlashNvStorageFtwWorkingBase64_HELP  
#language en-US "64-bit Base address of the FTW working block range in flash 
device."
 
 #string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdEmuVariableNvModeEnable_PROMPT  
#language en-US "EMU variable NV mode enable"
 
diff --git a/MdeModulePkg/Universal/FaultTolerantWriteDxe/FtwMisc.c 
b/MdeModulePkg/Universal/FaultTolerantWriteDxe/FtwMisc.c
index 661e148767..2fce694f22 100644
--- a/MdeModulePkg/Universal/FaultTolerantWriteDxe/FtwMisc.c
+++ b/MdeModulePkg/Universal/FaultTolerantWriteDxe/FtwMisc.c
@@ -1108,8 +1108,8 @@ FindFvbForFtw (
   // To get the LBA of work space
   //
   for (LbaIndex = 1; LbaIndex <= NumberOfBlocks; LbaIndex += 1) {
-if (  (FtwDevice->WorkSpaceAddress >= (FvbBaseAddress + BlockSize * 
(LbaIndex - 1)))
-   && (FtwDevice->WorkSpaceAddress < (FvbBaseAddress + BlockSize * 
LbaIndex)))
+if ((FtwDevice->WorkSpaceAddress - FvbBaseAddress >= BlockSize * 
(LbaIndex - 1)) &&
+((FtwDevice->WorkSpaceAddress - FvbBaseAddress) / BlockSize >= 
LbaIndex - 1))
 {
   FtwDevice->FtwWorkSpaceLba = LbaIndex - 1;
   //
@@ -1121,12 +1121,10 @@ FindFvbForFtw (
   FtwDevice->NumberOfWorkSpaceBlock = FTW_BLOCKS 
(FtwDevice->FtwWorkSpaceBase + FtwDevice->FtwWorkSpaceSize, 
FtwDevice->WorkBlockSize);
   if (FtwDevice->FtwWorkSpaceSize >= FtwDevice->WorkBlockSize) {
 //
-// Check the alignment of work space address and length, they 
should be block size aligned when work space size is larger than one block size.
+// Check the alignment of work space length, it should be block 
size aligned when work space size is larger than one block size.
 //
-if (((FtwDevice->WorkSpaceAddress & (FtwDevice->WorkBlockSize - 
1)) != 0) ||
-((FtwDevice->WorkSpaceLength & (FtwDevice->WorkBlockSize - 1)) 
!= 0))
-{
-  DEBUG ((DEBUG_ERROR, "Ftw: Work space address 

Re: [edk2-devel] [PATCH] MdeModulePkg/FaultTolerantWriteDxe: Don't check for address alignment

[Sean Rhodes]

Hi Hao

Yes, it does conflict - I will update the patch to fix these comments :)

Thank you


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Re: [edk2-devel] [PATCH] MdeModulePkg/FaultTolerantWriteDxe: Don't check for address alignment

[Wu, Hao A]

Sorry for a question.

I referred the code in InitFtwDevice():
  FtwDevice->WorkSpaceAddress = (EFI_PHYSICAL_ADDRESS)PcdGet64 
(PcdFlashNvStorageFtwWorkingBase64);
  if (FtwDevice->WorkSpaceAddress == 0) {
FtwDevice->WorkSpaceAddress = (EFI_PHYSICAL_ADDRESS)PcdGet32 
(PcdFlashNvStorageFtwWorkingBase);
  }

and the PCD definition in MdeModulePkg.dec:
  ## Base address of the FTW working block range in flash device.
  # If PcdFlashNvStorageFtwWorkingSize is larger than one block size, this 
value should be block size aligned.
  # @Prompt Base address of flash FTW working block range.
  
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0|UINT32|0x3010

  ## 64-bit Base address of the FTW working block range in flash device.
  # If PcdFlashNvStorageFtwWorkingSize is larger than one block size, this 
value should be block size aligned.
  # @Prompt 64-bit Base address of flash FTW working block range.
  
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x0|UINT64|0x8010

The description of both PCDs mentioned a block size alignment requirement.
Does the change in this patch conflict with the above PCD description?

(SpareAreaAddress is having a similar case.)

Best Regards,
Hao Wu

From: Sean Rhodes 
Sent: Monday, May 16, 2022 1:41 PM
To: devel@edk2.groups.io; Rhodes, Sean 
Cc: Wang, Jian J ; Wu, Hao A ; Gao, 
Liming 
Subject: Re: [edk2-devel] [PATCH] MdeModulePkg/FaultTolerantWriteDxe: Don't 
check for address alignment

Hi

Would any one be able to review please?

Thank you

On Fri, 1 Apr 2022, 09:03 Sean Rhodes via groups.io, 
mailto:starlabs.syst...@groups.io>> wrote:
WorkSpaceAddress and SpareAreaAddress point into MMIO, which isn't
always aligned. Remove the check for block alignment to avoid
false assertions.

Cc: Jian J Wang mailto:jian.j.w...@intel.com>>
Cc: Hao A Wu mailto:hao.a...@intel.com>>
Cc: Liming Gao mailto:gaolim...@byosoft.com.cn>>
Signed-off-by: Sean Rhodes mailto:sean@starlabs.systems>>
Change-Id: Ia1c1f44b6a0e7f32cac0d7806e74d729e5d83a6d
---
 .../Universal/FaultTolerantWriteDxe/FtwMisc.c| 16 ++--
 1 file changed, 6 insertions(+), 10 deletions(-)

diff --git a/MdeModulePkg/Universal/FaultTolerantWriteDxe/FtwMisc.c 
b/MdeModulePkg/Universal/FaultTolerantWriteDxe/FtwMisc.c
index 661e148767..3b9ff1c828 100644
--- a/MdeModulePkg/Universal/FaultTolerantWriteDxe/FtwMisc.c
+++ b/MdeModulePkg/Universal/FaultTolerantWriteDxe/FtwMisc.c
@@ -1121,12 +1121,10 @@ FindFvbForFtw (
   FtwDevice->NumberOfWorkSpaceBlock = FTW_BLOCKS 
(FtwDevice->FtwWorkSpaceBase + FtwDevice->FtwWorkSpaceSize, 
FtwDevice->WorkBlockSize);
   if (FtwDevice->FtwWorkSpaceSize >= FtwDevice->WorkBlockSize) {
 //
-// Check the alignment of work space address and length, they 
should be block size aligned when work space size is larger than one block size.
+// Check the alignment of work space length, it should be block 
size aligned when work space size is larger than one block size.
 //
-if (((FtwDevice->WorkSpaceAddress & (FtwDevice->WorkBlockSize - 
1)) != 0) ||
-((FtwDevice->WorkSpaceLength & (FtwDevice->WorkBlockSize - 1)) 
!= 0))
-{
-  DEBUG ((DEBUG_ERROR, "Ftw: Work space address or length is not 
block size aligned when work space size is larger than one block size\n"));
+if ((FtwDevice->WorkSpaceLength & (FtwDevice->WorkBlockSize - 1)) 
!= 0) {
+  DEBUG ((EFI_D_ERROR, "Ftw: Work space length is not block size 
aligned when work space size is larger than one block size\n"));
   FreePool (HandleBuffer);
   ASSERT (FALSE);
   return EFI_ABORTED;
@@ -1171,12 +1169,10 @@ FindFvbForFtw (
   }

   //
-  // Check the alignment of spare area address and length, they should 
be block size aligned
+  // Check the alignment of spare area length, it should be block size 
aligned
   //
-  if (((FtwDevice->SpareAreaAddress & (FtwDevice->SpareBlockSize - 1)) 
!= 0) ||
-  ((FtwDevice->SpareAreaLength & (FtwDevice->SpareBlockSize - 1)) 
!= 0))
-  {
-DEBUG ((DEBUG_ERROR, "Ftw: Spare area address or length is not 
block size aligned\n"));
+  if ((FtwDevice->SpareAreaLength & (FtwDevice->SpareBlockSize - 1)) 
!= 0) {
+DEBUG ((EFI_D_ERROR, "Ftw: Spare area address or length is not 
block size aligned\n"));
 FreePool (HandleBuffer);
 //
 // Report Status Code EFI_SW_EC_ABORTED.
--
2.32.0




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