回复: [edk2-devel] [PATCH 0/3] BaseTools: allow users to override CC and CXX on the make command line

[gaoliming via groups.io]

Rebecca:
  I create PR https://github.com/tianocore/edk2/pull/4162 . But PR shows some 
failure. Can you help fix them?

Thanks
Liming
> -邮件原件-
> 发件人: devel@edk2.groups.io  代表 gaoliming via
> groups.io
> 发送时间: 2023年3月23日 9:10
> 收件人: devel@edk2.groups.io; rebe...@bsdio.com; 'Andrew Fish'
> ; 'Leif Lindholm' ; 'Michael D
> Kinney' ; 'Bob Feng' ;
> 'Yuwei Chen' 
> 主题: 回复: [edk2-devel] [PATCH 0/3] BaseTools: allow users to override CC
> and CXX on the make command line
> 
> Rebecca:
>   This patch looks good to me. Reviewed-by: Liming Gao
> 
> 
>   I will help to merge this patch set.
> 
> Thanks
> Liming
> > -邮件原件-
> > 发件人: Rebecca Cran 
> > 发送时间: 2023年3月15日 0:17
> > 收件人: devel@edk2.groups.io; Andrew Fish ; Leif
> > Lindholm ; Michael D Kinney
> > ; Bob Feng ; Liming
> > Gao ; Yuwei Chen 
> > 主题: Re: [edk2-devel] [PATCH 0/3] BaseTools: allow users to override CC
> and
> > CXX on the make command line
> >
> > This is a patch series that I'd really like to get committed.
> >
> > It'll allow us to drop the dependency on gcc for building edk2 on FreeBSD.
> >
> >
> > The Github branch is https://github.com/bcran/edk2/tree/mdepkg-c11 and
> > there's a PR at https://github.com/tianocore/edk2/pull/4142.
> >
> >
> > --
> >
> > Rebecca Cran
> >
> >
> > On 3/9/23 8:47 AM, Rebecca Cran wrote:
> > > Could I get some reviews on this please?
> > >
> > >
> > > Thanks.
> > >
> > > Rebecca Cran
> > >
> > >
> > > On 2/16/23 8:50 PM, Rebecca Cran wrote:
> > >> Currently, the BaseTools Makefiles use BUILD_CC and BUILD_CXX, which
> > >> doesn't allow users to override the compiler to use in the expected way
> > >> by running e.g. "make CC=clang-17 CXX=clang++-17". clang/llvm support
> > >> was added in https://bugzilla.tianocore.org/show_bug.cgi?id=2842 in a
> > >> way that required users to run "make CXX=llvm" and have clang and
> > >> clang++
> > >> executables under $(CLANG_BIN). As far as I know this isn't a standard
> > >> way of telling a build system to use clang, and so is likely difficult
> > >> to discover by users.
> > >>
> > >> This patch series fixes that, and as a side effect allows the clang
> > >> analyzer to run via "scan-build make".
> > >>
> > >> Since clang 17 defaults to C++17 or newer where the 'register' keyword
> > >> is deprecated and the warning turned into an error, override the
> > >> version used when building C++ code via "-std=c++14".
> > >>
> > >> Rebecca Cran (3):
> > >>BaseTools: Allow users to specify compiler to use with make CC=
> > CXX=
> > >>BaseTools: Improve detection of users wanting to build using clang
> > >>BaseTools: Build against C++14 when building with clang
> > >>
> > >>   BaseTools/Source/C/DevicePath/GNUmakefile  |  7 ++-
> > >>   BaseTools/Source/C/LzmaCompress/GNUmakefile|  2 +-
> > >>   BaseTools/Source/C/Makefiles/app.makefile  |  2 +-
> > >>   BaseTools/Source/C/Makefiles/footer.makefile   |  6 +-
> > >>   BaseTools/Source/C/Makefiles/header.makefile   | 59
> > >> ++--
> > >>   BaseTools/Source/C/VfrCompile/GNUmakefile  | 19
> > ---
> > >>   BaseTools/Source/C/VfrCompile/Pccts/antlr/makefile | 20 +++
> > >>   BaseTools/Source/C/VfrCompile/Pccts/dlg/makefile   | 31
> +-
> > >>   BaseTools/Source/Python/Workspace/DscBuildData.py  |  2 +-
> > >>   9 files changed, 76 insertions(+), 72 deletions(-)
> > >>
> 
> 
> 
> 
> 
> 





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[edk2-devel] 回复: [PATCH 2/3] BaseTools: Replace duplicate __PcdSet prototype with __PcdGet

[gaoliming via groups.io]

Reviewed-by: Liming Gao 

> -邮件原件-
> 发件人: Rebecca Cran 
> 发送时间: 2023年2月25日 8:55
> 收件人: devel@edk2.groups.io; Bob Feng ; Liming
> Gao ; Yuwei Chen 
> 抄送: Rebecca Cran 
> 主题: [PATCH 2/3] BaseTools: Replace duplicate __PcdSet prototype with
> __PcdGet
> 
> Replace the duplicate __PcdSet prototype in PcdValueCommon.h
> with the prototype for __PcdGet.
> 
> Signed-off-by: Rebecca Cran 
> ---
>  BaseTools/Source/C/Common/PcdValueCommon.h | 13 ++---
>  1 file changed, 6 insertions(+), 7 deletions(-)
> 
> diff --git a/BaseTools/Source/C/Common/PcdValueCommon.h
> b/BaseTools/Source/C/Common/PcdValueCommon.h
> index 02ef803be479..7dac5bd92dbc 100644
> --- a/BaseTools/Source/C/Common/PcdValueCommon.h
> +++ b/BaseTools/Source/C/Common/PcdValueCommon.h
> @@ -78,13 +78,12 @@ __PcdSet (
> 
>@return PCD value
>  **/
> -VOID
> -__PcdSet (
> -  CHAR8   *SkuName OPTIONAL,
> -  CHAR8   *DefaultValueNameOPTIONAL,
> -  CHAR8   *TokenSpaceGuidName,
> -  CHAR8   *TokenName,
> -  UINT64  Value
> +UINT64
> +__PcdGet (
> +  CHAR8  *SkuName OPTIONAL,
> +  CHAR8  *DefaultValueNameOPTIONAL,
> +  CHAR8  *TokenSpaceGuidName,
> +  CHAR8  *TokenName
>)
>  ;
> 
> --
> 2.37.1 (Apple Git-137.1)





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[edk2-devel] reg: MAC address could not change on pre-boot environment and failed to PXE boot.

[Sivaraman Nainar via groups.io]

Hello :

We are writing a application to program the MAC from UEFI shell and with the 
updated MAC address trying to do the PXE Boot which failed.

The application uses the Simple Network Protocols StationAddress() to update 
the MAC. After update the Current Address in the Mode of SimpleNetwork 
Interface updated to new MAC address. If we performed IfConfigl -l command the 
updated MAC not showing. Also in this environment PXE boot also got failed.

To bind the updated MAC, tried giving "reconnect -r" from UEFI shell after 
running test application and performed PXE boot. With On board Network 
controller (Intel I219), the MAC address updated in Snp->Mode->CurrentAddress 
is reverted back to older MAC address.  If reconnect not performed, the MAC 
Address changing but PXE Failed to boot.

Can someone comment if the method to update the MAC is correct or we missing 
something.

Thanks
Siva
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Re: [edk2-devel] [PATCH v4] MdePkg/Include: Add IPMI KCS definitions

[Tinh Nguyen via groups.io]

On 24/03/2023 10:15, Chang, Abner via groups.io wrote:

From: Abner Chang 

BZ #4354
This change adds definitions for IPMI KCS.

Spec ref:
https://www.intel.com/content/www/us/en/products/docs/servers/ipmi/ipmi-second-gen-interface-spec-v2-rev1-1.html

Signed-off-by: Abner Chang 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Nickle Wang 
Cc: Igor Kulchytskyy 
Cc: Isaac Oram 
Cc: Abdul Lateef Attar 
Acked-by: Isaac Oram 
---
  MdePkg/MdePkg.dec |  6 ++
  MdePkg/Include/IndustryStandard/IpmiKcs.h | 76 +++
  2 files changed, 82 insertions(+)
  create mode 100644 MdePkg/Include/IndustryStandard/IpmiKcs.h

diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index 2d643bede1d..5cf04bc0cb6 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -9,6 +9,7 @@
  # (C) Copyright 2016 - 2021 Hewlett Packard Enterprise Development LP
  # Copyright (c) 2022, Loongson Technology Corporation Limited. All rights 
reserved.
  # Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
  #
  # SPDX-License-Identifier: BSD-2-Clause-Patent
  #
@@ -2342,6 +2343,11 @@
# @Prompt Memory Address of GuidedExtractHandler Table.

gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|0x100|UINT64|0x30001015
  
+  ## This value is the IPMI KCS Interface I/O base address used to transmit IPMI commands.

+  #  The value of 0xca2 is the default I/O base address defined in IPMI 
specification.
+  # @Prompt IPMI KCS Interface I/O Base Address
+  gEfiMdePkgTokenSpaceGuid.PcdIpmiKcsIoBaseAddress|0xca2|UINT16|0x0031
+
  [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
## This value is used to set the base address of PCI express hierarchy.
# @Prompt PCI Express Base Address.
diff --git a/MdePkg/Include/IndustryStandard/IpmiKcs.h 
b/MdePkg/Include/IndustryStandard/IpmiKcs.h
new file mode 100644
index 000..1e1be787617
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/IpmiKcs.h
@@ -0,0 +1,76 @@
+/** @file
+  IPMI KCS Register Definitions
+
+  Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  IPMI Specification
+  Version 2.0, Rev. 1.1
+  
https://www.intel.com/content/www/us/en/products/docs/servers/ipmi/ipmi-second-gen-interface-spec-v2-rev1-1.html
+**/
+
+#ifndef IPMI_KCS_H_
+#define IPMI_KCS_H_
+
+#define IPMI_KCS_STATUS_REGISTER_OFFSET1
+#define IPMI_KCS_COMMAND_REGISTER_OFFSET   1
+#define IPMI_KCS_DATA_OUT_REGISTER_OFFSET  0
+#define IPMI_KCS_DATA_IN_REGISTER_OFFSET   0
+
+///
+/// IPMI KCS Interface Status Bits
+///
+#define IPMI_KCS_OBF   BIT0
+#define IPMI_KCS_IBF   BIT1
+#define IPMI_KCS_SMS_ATN   BIT2
+#define IPMI_KCS_COMMAND_DATA  BIT3
+#define IPMI_KCS_OEM1  BIT4
+#define IPMI_KCS_OEM2  BIT5
+#define IPMI_KCS_S0BIT6
+#define IPMI_KCS_S1BIT7
+
+///
+/// IPMI KCS Interface Control Codes
+///
+#define IPMI_KCS_CONTROL_CODE_GET_STATUS_ABORT  0x60
+#define IPMI_KCS_CONTROL_CODE_WRITE_START   0x61
+#define IPMI_KCS_CONTROL_CODE_WRITE_END 0x62
+#define IPMI_KCS_CONTROL_CODE_READ  0x68
+
+///
+/// Status Codes
+///
+#define IPMI_KCS_STATUS_NO_ERROR  0x00
+#define IPMI_KCS_STATUS_ABORT 0x01
+#define IPMI_KCS_STATUS_ILLEGAL   0x02
+#define IPMI_KCS_STATUS_LENGTH_ERROR  0x06
+#define IPMI_KCS_STATUS_UNSPECIFIED   0xFF
+
+///
+/// KCS Interface State Bit
+///
+typedef enum {
+  IPMI_KCS_IDLE_STATE = 0,
+  IPMI_KCS_READ_STATE,
+  IPMI_KCS_WRITE_STATE,
+  IPMI_KCS_ERROR_STATE
+} IPMI_KCS_STATE;
+
+///
+/// IPMI KCS Interface Request Format
+///
+typedef struct {
+  UINT8NetFunc;
+  UINT8Command;
+  UINT8Data[];
+} IPMI_KCS_RESQUEST_HEADER;

I mean, there's a typo here, IPMI_KCS_REQUEST_HEADER

+
+///
+/// IPMI KCS Interface Response Format
+///
+typedef struct {
+  UINT8NetFunc;
+  UINT8Command;
+} IPMI_KCS_RESPONSE_HEADER;
+#endif



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[edk2-devel] [PATCH v4] MdePkg/Include: Add IPMI KCS definitions

[Chang, Abner via groups.io]

From: Abner Chang 

BZ #4354
This change adds definitions for IPMI KCS.

Spec ref:
https://www.intel.com/content/www/us/en/products/docs/servers/ipmi/ipmi-second-gen-interface-spec-v2-rev1-1.html

Signed-off-by: Abner Chang 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Nickle Wang 
Cc: Igor Kulchytskyy 
Cc: Isaac Oram 
Cc: Abdul Lateef Attar 
Acked-by: Isaac Oram 
---
 MdePkg/MdePkg.dec |  6 ++
 MdePkg/Include/IndustryStandard/IpmiKcs.h | 76 +++
 2 files changed, 82 insertions(+)
 create mode 100644 MdePkg/Include/IndustryStandard/IpmiKcs.h

diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index 2d643bede1d..5cf04bc0cb6 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -9,6 +9,7 @@
 # (C) Copyright 2016 - 2021 Hewlett Packard Enterprise Development LP
 # Copyright (c) 2022, Loongson Technology Corporation Limited. All rights 
reserved.
 # Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -2342,6 +2343,11 @@
   # @Prompt Memory Address of GuidedExtractHandler Table.
   
gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|0x100|UINT64|0x30001015
 
+  ## This value is the IPMI KCS Interface I/O base address used to transmit 
IPMI commands.
+  #  The value of 0xca2 is the default I/O base address defined in IPMI 
specification.
+  # @Prompt IPMI KCS Interface I/O Base Address
+  gEfiMdePkgTokenSpaceGuid.PcdIpmiKcsIoBaseAddress|0xca2|UINT16|0x0031
+
 [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
   ## This value is used to set the base address of PCI express hierarchy.
   # @Prompt PCI Express Base Address.
diff --git a/MdePkg/Include/IndustryStandard/IpmiKcs.h 
b/MdePkg/Include/IndustryStandard/IpmiKcs.h
new file mode 100644
index 000..1e1be787617
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/IpmiKcs.h
@@ -0,0 +1,76 @@
+/** @file
+  IPMI KCS Register Definitions
+
+  Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  IPMI Specification
+  Version 2.0, Rev. 1.1
+  
https://www.intel.com/content/www/us/en/products/docs/servers/ipmi/ipmi-second-gen-interface-spec-v2-rev1-1.html
+**/
+
+#ifndef IPMI_KCS_H_
+#define IPMI_KCS_H_
+
+#define IPMI_KCS_STATUS_REGISTER_OFFSET1
+#define IPMI_KCS_COMMAND_REGISTER_OFFSET   1
+#define IPMI_KCS_DATA_OUT_REGISTER_OFFSET  0
+#define IPMI_KCS_DATA_IN_REGISTER_OFFSET   0
+
+///
+/// IPMI KCS Interface Status Bits
+///
+#define IPMI_KCS_OBF   BIT0
+#define IPMI_KCS_IBF   BIT1
+#define IPMI_KCS_SMS_ATN   BIT2
+#define IPMI_KCS_COMMAND_DATA  BIT3
+#define IPMI_KCS_OEM1  BIT4
+#define IPMI_KCS_OEM2  BIT5
+#define IPMI_KCS_S0BIT6
+#define IPMI_KCS_S1BIT7
+
+///
+/// IPMI KCS Interface Control Codes
+///
+#define IPMI_KCS_CONTROL_CODE_GET_STATUS_ABORT  0x60
+#define IPMI_KCS_CONTROL_CODE_WRITE_START   0x61
+#define IPMI_KCS_CONTROL_CODE_WRITE_END 0x62
+#define IPMI_KCS_CONTROL_CODE_READ  0x68
+
+///
+/// Status Codes
+///
+#define IPMI_KCS_STATUS_NO_ERROR  0x00
+#define IPMI_KCS_STATUS_ABORT 0x01
+#define IPMI_KCS_STATUS_ILLEGAL   0x02
+#define IPMI_KCS_STATUS_LENGTH_ERROR  0x06
+#define IPMI_KCS_STATUS_UNSPECIFIED   0xFF
+
+///
+/// KCS Interface State Bit
+///
+typedef enum {
+  IPMI_KCS_IDLE_STATE = 0,
+  IPMI_KCS_READ_STATE,
+  IPMI_KCS_WRITE_STATE,
+  IPMI_KCS_ERROR_STATE
+} IPMI_KCS_STATE;
+
+///
+/// IPMI KCS Interface Request Format
+///
+typedef struct {
+  UINT8NetFunc;
+  UINT8Command;
+  UINT8Data[];
+} IPMI_KCS_RESQUEST_HEADER;
+
+///
+/// IPMI KCS Interface Response Format
+///
+typedef struct {
+  UINT8NetFunc;
+  UINT8Command;
+} IPMI_KCS_RESPONSE_HEADER;
+#endif
-- 
2.37.1.windows.1



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Re: [edk2-devel] [PATCH v3] MdePkg/Include: Add DMTF MCTP definitions

[Chang, Abner via groups.io]

[AMD Official Use Only - General]

Hi Mike,
MCTP v4 was just sent.
Thanks
Abner

> -Original Message-
> From: Kinney, Michael D 
> Sent: Friday, March 24, 2023 6:24 AM
> To: Chang, Abner ; devel@edk2.groups.io
> Cc: Gao, Liming ; Liu, Zhiguang
> ; Nickle Wang ; Igor
> Kulchytskyy ; Oram, Isaac W ;
> Attar, AbdulLateef (Abdul Lateef) ; Kinney,
> Michael D 
> Subject: RE: [PATCH v3] MdePkg/Include: Add DMTF MCTP definitions
> 
> Caution: This message originated from an External Source. Use proper
> caution when opening attachments, clicking links, or responding.
> 
> 
> > -Original Message-
> > From: abner.ch...@amd.com 
> > Sent: Thursday, March 23, 2023 8:05 AM
> > To: devel@edk2.groups.io
> > Cc: Kinney, Michael D ; Gao, Liming
> > ; Liu, Zhiguang ;
> > Nickle Wang ; Igor Kulchytskyy ;
> > Oram, Isaac W ; Abdul Lateef Attar
> > 
> > Subject: [PATCH v3] MdePkg/Include: Add DMTF MCTP definitions
> >
> > From: Abner Chang 
> >
> > BZ #4355
> > This change adds definitions for DMTF MCTP base specification.
> >
> > Spec ref:
> >
> https://www.dmtf.org/sites/default/files/standards/documents/DSP0236_1
> > .3.1.pdf
> >
> > Signed-off-by: Abner Chang 
> > Cc: Michael D Kinney 
> > Cc: Liming Gao 
> > Cc: Zhiguang Liu 
> > Cc: Nickle Wang 
> > Cc: Igor Kulchytskyy 
> > Cc: Isaac Oram 
> > Cc: Abdul Lateef Attar 
> > Acked-by: Isaac Oram 
> > ---
> >  MdePkg/Include/IndustryStandard/Mctp.h | 138
> > +
> >  1 file changed, 138 insertions(+)
> >  create mode 100644 MdePkg/Include/IndustryStandard/Mctp.h
> >
> > diff --git a/MdePkg/Include/IndustryStandard/Mctp.h
> > b/MdePkg/Include/IndustryStandard/Mctp.h
> > new file mode 100644
> > index 000..bfbc843c7f1
> > --- /dev/null
> > +++ b/MdePkg/Include/IndustryStandard/Mctp.h
> > @@ -0,0 +1,138 @@
> > +/** @file
> > +
> > +  The definitions of DMTF Management Component Transport Protocol
> > + (MCTP)  Base Specification.
> > +
> > +  Copyright (C) 2023 Advanced Micro Devices, Inc. All rights
> > + reserved.
> > +  SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +  @par Revision Reference:
> > +  DMTF Management Component Transport Protocol (MCTP) Base
> > +Specification
> > +  Version 1.3.1
> > +
> >
> +https://www.dmtf.org/sites/default/files/standards/documents/DSP0236_
> > +1.3.1.pdf
> > +**/
> > +
> > +#ifndef MCTP_H_
> > +#define MCTP_H_
> > +
> > +///
> > +/// Definitions of endpoint ID
> > +///
> > +#define MCTP_NULL_DESTINATION_ENDPOINT_ID  0
> > +#define MCTP_NULL_SOURCE_ENDPOINT_ID   0
> > +#define MCTP_RESERVED_ENDPOINT_START_ID1
> > +#define MCTP_RESERVED_ENDPOINT_END_ID  7
> > +#define MCTP_BROADCAST_ENDPOINT_ID 0xFF
> > +
> > +/// Minimum transmission size is 64 bytes.
> > +/// The value of 64 is defined in MCTP Base Specification.
> > +#define MCTP_BASELINE_MINIMUM_UNIT_TRANSMISSION_SIZE  0x40
> > +
> > +///
> > +/// The 32-bit Header of MCTP packet.
> > +///
> > +typedef union {
> > +  struct {
> > +UINT8HeaderVersion : 4; ///< The version of header.
> > +UINT8Reserved  : 4; ///< Reserved for future 
> > definitions.
> > +UINT8DestinationEndpointId : 8; ///< Destination endpoint Id (EID).
> > +UINT8SourceEndpointIdId: 8; ///< Source endpoint Id (EID)
> > +UINT8MessageTag: 3; ///< Check the MCTP Base 
> > specification
> for the
> > +///< usages.
> > +UINT8TagOwner  : 1; ///< Tag owner identifies the 
> > message was
> > +///< originated by the source EID 
> > or
> > +///< destination EID.
> > +UINT8PacketSequence: 2; ///< Sequence number increments
> Modulo 4 on
> > +///< each packet.
> > +UINT8EndOfMessage  : 1; ///< Indicates the last packet of
> message.
> > +UINT8StartOfMessage: 1; ///< Indicates the first packet of
> message.
> 
> These bitfields should be type UINT32
> 
> > +  } Bits;
> > +  UINT32Header;
> > +} MCTP_TRANSPORT_HEADER;
> > +
> > +///
> > +/// The 8-bit Message Header of MCTP packet.
> > +///
> > +typedef union {
> > +  struct {
> > +UINT8MessageType   : 7;
> > +UINT8ItegrityCheck : 1;
> > +  } Bits;
> > +  UINT8MessageHeader;
> > +} MCTP_MESSAGE_HEADER;
> > +
> > +///
> > +/// MCTP Control Commands
> > +///
> > +#define   MCTP_CONTROL_RESERVED0x00
> > +#define   MCTP_CONTROL_SET_ENDPOINT_ID 0x01
> > +#define   MCTP_CONTROL_GET_ENDPOINT_ID 0x02
> > +#define   MCTP_CONTROL_GET_ENDPOINT_UUID   0x03
> > +#define   MCTP_CONTROL_GET_MCTP_VERSION_SUPPORT0x04
> > +#define   MCTP_CONTROL_GET_MESSAGE_TYPE_SUPPORT0x05
> > +#define   MCTP_CONTROL_GET_VENDOR_DEFINED_MESSAGE_SUPPORT
> 0x06
> > +#define   MCTP_CONTROL_RESOLVE_ENDPOINT_ID 

[edk2-devel] [PATCH v4] MdePkg/Include: Add DMTF MCTP definitions

[Chang, Abner via groups.io]

From: Abner Chang 

BZ #4355
This change adds definitions for DMTF MCTP
base specification.

Spec ref:
https://www.dmtf.org/sites/default/files/standards/documents/DSP0236_1.3.1.pdf

Signed-off-by: Abner Chang 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Nickle Wang 
Cc: Igor Kulchytskyy 
Cc: Isaac Oram 
Cc: Abdul Lateef Attar 
Acked-by: Isaac Oram 
---
 MdePkg/Include/IndustryStandard/Mctp.h | 139 +
 1 file changed, 139 insertions(+)
 create mode 100644 MdePkg/Include/IndustryStandard/Mctp.h

diff --git a/MdePkg/Include/IndustryStandard/Mctp.h 
b/MdePkg/Include/IndustryStandard/Mctp.h
new file mode 100644
index 000..81f99a38347
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/Mctp.h
@@ -0,0 +1,139 @@
+/** @file
+
+  The definitions of DMTF Management Component Transport Protocol (MCTP)
+  Base Specification.
+
+  Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  DMTF Management Component Transport Protocol (MCTP) Base Specification
+  Version 1.3.1
+  
https://www.dmtf.org/sites/default/files/standards/documents/DSP0236_1.3.1.pdf
+**/
+
+#ifndef MCTP_H_
+#define MCTP_H_
+
+///
+/// Definitions of endpoint ID
+///
+#define MCTP_NULL_DESTINATION_ENDPOINT_ID  0
+#define MCTP_NULL_SOURCE_ENDPOINT_ID   0
+#define MCTP_RESERVED_ENDPOINT_START_ID1
+#define MCTP_RESERVED_ENDPOINT_END_ID  7
+#define MCTP_BROADCAST_ENDPOINT_ID 0xFF
+
+///
+/// MCTP Control Commands
+///
+#define   MCTP_CONTROL_RESERVED0x00
+#define   MCTP_CONTROL_SET_ENDPOINT_ID 0x01
+#define   MCTP_CONTROL_GET_ENDPOINT_ID 0x02
+#define   MCTP_CONTROL_GET_ENDPOINT_UUID   0x03
+#define   MCTP_CONTROL_GET_MCTP_VERSION_SUPPORT0x04
+#define   MCTP_CONTROL_GET_MESSAGE_TYPE_SUPPORT0x05
+#define   MCTP_CONTROL_GET_VENDOR_DEFINED_MESSAGE_SUPPORT  0x06
+#define   MCTP_CONTROL_RESOLVE_ENDPOINT_ID 0x07
+#define   MCTP_CONTROL_ALLOCATE_ENDPOINT_IDS   0x08
+#define   MCTP_CONTROL_ROUTING_INFORMATION_UPDATE  0x09
+#define   MCTP_CONTROL_GET_ROUTINE_TABLE_ENTRIES   0x0A
+#define   MCTP_CONTROL_PREPARE_FOR_ENDPOINT_DISCOVERY  0x0B
+#define   MCTP_CONTROL_ENDPOINT_DISCOVERY  0x0C
+#define   MCTP_CONTROL_DISCOVERY_NOTIFY0x0D
+#define   MCTP_CONTROL_GET_NETWORK_ID  0x0E
+#define   MCTP_CONTROL_QUERY_HOP   0x0F
+#define   MCTP_CONTROL_RESOLVE_UUID0x10
+#define   MCTP_CONTROL_QUERY_RATE_LIMIT0x11
+#define   MCTP_CONTROL_REQUEST_TX_RATE_LIMIT   0x12
+#define   MCTP_CONTROL_UPDATE_RATE_LIMIT   0x13
+#define   MCTP_CONTROL_QUERY_SUPPORTED_INTERFACES  0x14
+#define   MCTP_CONTROL_TRANSPORT_SPECIFIC_START0xF0
+#define   MCTP_CONTROL_TRANSPORT_SPECIFIC_END  0xFF
+
+///
+/// MCTP Control Message Completion Codes
+///
+#define   MCTP_CONTROL_COMPLETION_CODES_SUCCESS 0x00
+#define   MCTP_CONTROL_COMPLETION_CODES_ERROR   0x01
+#define   MCTP_CONTROL_COMPLETION_CODES_ERROR_INVALID_DATA  0x02
+#define   MCTP_CONTROL_COMPLETION_CODES_ERROR_INVALID_LENGTH0x03
+#define   MCTP_CONTROL_COMPLETION_CODES_ERROR_NOT_READY 0x04
+#define   MCTP_CONTROL_COMPLETION_CODES_ERROR_UNSUPPORTED_CMD   0x05
+#define   MCTP_CONTROL_COMPLETION_CODES_COMMAND_SPECIFIC_START  0x80
+#define   MCTP_CONTROL_COMPLETION_CODES_COMMAND_SPECIFIC_END0xFF
+
+///
+/// MCTP Control Message Types
+///
+#define   MCTP_MESSAGE_TYPE_CONTROL  0x00
+#define   MCTP_MESSAGE_TYPE_PLDM 0x01
+#define   MCTP_MESSAGE_TYPE_NCSI 0x02
+#define   MCTP_MESSAGE_TYPE_ETHERNET 0x03
+#define   MCTP_MESSAGE_TYPE_NVME 0x04
+#define   MCTP_MESSAGE_TYPE_SPDM 0x05
+#define   MCTP_MESSAGE_TYPE_SECURE_MESSAGE   0x06
+#define   MCTP_MESSAGE_TYPE_CXL_FM_API   0x07
+#define   MCTP_MESSAGE_TYPE_CXL_CCI  0x08
+#define   MCTP_MESSAGE_TYPE_VENDOR_DEFINED_PCI   0x7E
+#define   MCTP_MESSAGE_TYPE_VENDOR_DEFINED_IANA  0x7F
+
+#define   MCTP_ENDPOINT_ID_NULL0
+#define   MCTP_ENDPOINT_ID_RESERVED_START  1
+#define   MCTP_ENDPOINT_ID_RESERVED_END7
+#define   MCTP_ENDPOINT_ID_BROADCAST   0xff
+///
+/// MCTP Control Message Format
+///
+typedef struct {
+  struct {
+UINT32MessageType: 7; ///< Message type.
+UINT32IntegrityCheck : 1; ///< Message integrity check.
+UINT32InstanceId : 5; ///< Instance ID.
+UINT32Reserved   : 1; ///< Reserved bit.
+UINT32DatagramBit: 1; ///< Datagram bit.
+UINT32RequestBit : 1; ///< Request bit.
+UINT32CommandCode: 8; ///< Command code of request message.
+UINT32

Re: [edk2-devel] [Patch V4 06/21] UefiCpuPkg/CpuPageTableLib: Fix issue when splitting leaf entry

[Ni, Ray]

Non-leaf entry doesn't have PAT bit.
So "& (~IA32_PE_BASE_ADDRESS_MASK_40)" is to make sure PAT bit in the original 
big-leaf entry
is not assigned to the corresponding bit (bit 12) in non-leaf entry.

Can you please add comments to explain why?

With that, Reviewed-by: Ray Ni 

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Ni, Ray
> Sent: Thursday, March 23, 2023 8:35 PM
> To: Tan, Dun ; devel@edk2.groups.io
> Cc: Dong, Eric ; Kumar, Rahul R
> ; Gerd Hoffmann 
> Subject: Re: [edk2-devel] [Patch V4 06/21] UefiCpuPkg/CpuPageTableLib: Fix
> issue when splitting leaf entry
> 
> > +  ParentPagingEntry->Uint64 = ((UINTN)(VOID *)PagingEntry) |
> > (ParentPagingEntry->Uint64 & (~IA32_PE_BASE_ADDRESS_MASK_40));
> 
> In this branch, ParentPagingEntry is a leaf entry covering 2M or 1G physical
> address range.
> Then, why not use IA32_PE_BASE_ADDRESS_MASK_39? Because for the two
> types leaf entry, address
> only occupies 39 bits, not 40bits.
> 
> 
> 
> 
> 



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Re: [edk2-devel] [Patch V4 08/21] UefiCpuPkg/CpuPageTableLib:Add check for Mask and Attr

[duntan]

Thanks for the comments Ray. I will update the patches in next version patch 
set.

-Why break out of the loop when meeting a non-present entry?
Because I think the parameter check is only needed once.

Thanks,
Dun

-Original Message-
From: Ni, Ray  
Sent: Thursday, March 23, 2023 8:53 PM
To: Tan, Dun ; devel@edk2.groups.io
Cc: Dong, Eric ; Kumar, Rahul R ; 
Gerd Hoffmann 
Subject: RE: [Patch V4 08/21] UefiCpuPkg/CpuPageTableLib:Add check for Mask and 
Attr

The commit message is very detailed.

But the function header comments are not.
Can you please update the function header comments to add 4 lines of @retval 
RETURN_INVALID_PARAMETER, each line describes one invalid case.

It's ok to have multiple lines starting with @retval RETURN_INVALID_PARAMETER>

> +// If (LinearAddress + Length - 1) is not in the same 
> + ParentPagingEntry
> with (LinearAddress + Offset), then the remaining child PagingEntry
> +// starting from PagingEntryIndex of ParentPagingEntry is all 
> + covered by
> [LinearAddress + Offset, LinearAddress + Length - 1].
> +//
> +PagingEntryIndexEnd = (BitFieldRead64 (LinearAddress + Length - 
> + 1,
> BitStart + 9, 63) != BitFieldRead64 (LinearAddress + Offset, BitStart + 9, 
> 63)) ?
> 511 :
> +  (UINTN)BitFieldRead64 (LinearAddress + 
> + Length - 1, BitStart,
> BitStart + 9 - 1);
> +PagingEntry = (IA32_PAGING_ENTRY
> *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (
> >Pnle);
> +for (Index = PagingEntryIndex; Index <= PagingEntryIndexEnd; Index++) {
> +  if (PagingEntry[Index].Pce.Present == 0) {
> +//
> +// [LinearAddress, LinearAddress + Length] contains non-present 
> range.
> +//
> +Status = IsAttributesAndMaskValidForNonPresentEntry 
> + (Attribute,
> Mask);
> +if (RETURN_ERROR (Status)) {
> +  return Status;
> +}
> +
> +break;

Why break out of the loop when meeting a non-present entry?



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Re: [edk2-devel] [edk2-staging/OpenSSL11_EOL][PATCH 4/4] Readme: 0322 update

[Li, Yi]

Hi Gerd,

Thanks for review,

>> +### Level 2: A bit like workaround, with possibility of upstream to 
>> +openssl 1. Enable the legacy path for X509 pubkey decode and pmeth 
>> +initialization, The purpose is to avoid the use of EN/DECODE and Signature 
>> provider, will reduce size about 90KB.
>> +(commit: x509: enable legacy path in pub decode)
>> +https://github.com/liyi77/openssl/commit/8780956da77c949ca42f6c4c3fd6
>> +ef7045646ef0
>> +(commit: evp: enable legacy pmeth)
>> +https://github.com/liyi77/openssl/commit/a2232b35aa308198b61c5734c1bf
>> +e1d0263f074b

>I suspect that is not going to work well long-term, probably openssl will 
>remove the code paths they consider being "legacy" at some point in the 
>future.  Probably not 3.0.x but maybe in 3.1 branch.

Yes, I think in long-term the better way is to remove all legacy code paths, 
this will also help reduce the size.
The problem is that a large number of legacy APIs are currently used in the 
EDK2 code.
In the future, it may be a big update to throw all the legacy code.

>> +### Level 3: Totally workaround and hard to upstream to openssl, may 
>> +need scripts to apply them inside EDK2 1. Provider cut.
>> +(commit: CryptoPkg: add own openssl provider) 
>> +https://github.com/liyi77/edk2-staging/commit/c3a5b69d8a3465259cfdca8
>> +f38b0dc7683b3690e

>Allow people implement their own providers looks like an openssl feature to 
>me.  So I don't think this will be a big problem to maintain, I expect they 
>try to keep the interfaces stable to not break apps doing so.

>The only little detail we do differently here is to remove the default 
>providers so LTO can actually remove the unused code.

>> +(commit: x509: remove print function 7KB)
>> +https://github.com/liyi77/openssl/commit/faa5d6781c3af601bcbc11ff199e
>> +2955d7ff4306

>Did you double-check this doesn't break something?

>It did for me, due to some code in openssl depending on a working 
>bio_sprintf() implementation.

I don't do any more test than unit test.
I am sick of this part, but I currently have no other way to reduce the size. I 
would like to drop those changes first if i find another way.

Regards,
Yi



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[edk2-devel] [PATCH] OvmfPkg/VirtioMmioDeviceLib: virtio 1.0: Fix SetQueueAlignment.

[Jeff Brasen via groups.io]

Nothing to do here for virtio 1.0 devices

Signed-off-by: Jeff Brasen 
---
 .../Library/VirtioMmioDeviceLib/VirtioMmioDeviceFunctions.c   | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDeviceFunctions.c 
b/OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDeviceFunctions.c
index 8bdf1e1fc3..de2c5fa2a6 100644
--- a/OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDeviceFunctions.c
+++ b/OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDeviceFunctions.c
@@ -144,7 +144,9 @@ VirtioMmioSetQueueAlignment (
 
   Device = VIRTIO_MMIO_DEVICE_FROM_VIRTIO_DEVICE (This);
 
-  VIRTIO_CFG_WRITE (Device, VIRTIO_MMIO_OFFSET_QUEUE_ALIGN, Alignment);
+  if (Device->Version == VIRTIO_MMIO_DEVICE_VERSION_0_95) {
+VIRTIO_CFG_WRITE (Device, VIRTIO_MMIO_OFFSET_QUEUE_ALIGN, Alignment);
+  }
 
   return EFI_SUCCESS;
 }
-- 
2.25.1



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Re: [edk2-devel] [PATCH 0/1] MdeModulePkg/Ahci: Skip retry for non-transient errors

[Wu, Hao A]

Thanks Baranee. We will proceed to merge the this patch after reviewing process.

For the PCD (PcdAhciCommandRetryCount) previously introduced to address the 
password retry issue, what is your opinion on it?
Do you think we can remove it or keep it for other reason? Thanks.

Best Regards,
Hao Wu

From: devel@edk2.groups.io  On Behalf Of Anbazhagan, 
Baraneedharan via groups.io
Sent: Friday, March 24, 2023 12:55 AM
To: devel@edk2.groups.io; Wu, Hao A ; Albecki, Mateusz 

Cc: Ni, Ray ; Chang, Hunter 
Subject: Re: [edk2-devel] [PATCH 0/1] MdeModulePkg/Ahci: Skip retry for 
non-transient errors

Hi,
This patch seems to resolve the issue reported in 4011 - MdeModulePkg: Need 
configurable AHCI command retries 
(tianocore.org) and 
verified with 'AHCI_COMMAND_RETRIES' as 5. Able to unlock the drive with 
correct password on 2nd attempt after providing an incorrect password.

Thanks,
Baranee

From: devel@edk2.groups.io 
mailto:devel@edk2.groups.io>> On Behalf Of Wu, Hao A via 
groups.io
Sent: Wednesday, March 22, 2023 1:59 AM
To: Albecki, Mateusz 
mailto:mateusz.albe...@intel.com>>; Anbazhagan, 
Baraneedharan mailto:anbazha...@hp.com>>; 
devel@edk2.groups.io
Cc: Ni, Ray mailto:ray...@intel.com>>; Chang, Hunter 
mailto:hunter.ch...@intel.com>>
Subject: Re: [edk2-devel] [PATCH 0/1] MdeModulePkg/Ahci: Skip retry for 
non-transient errors

CAUTION: External Email
Thanks Mateusz, the patch looks good to me.
I noticed that there are some check failures in 
https://github.com/tianocore/edk2/pull/4157, could you help to address them?


Hello Baraneedharan Anbazhagan,
Could you help to check if this patch can resolve the issue 
https://bugzilla.tianocore.org/show_bug.cgi?id=4011 when switching back to: 
"#define AHCI_COMMAND_RETRIES 5"?
This change can be accessed for integration at: 
https://patch-diff.githubusercontent.com/raw/tianocore/edk2/pull/4157.patch
Thanks in advance.

Best Regards,
Hao Wu

> -Original Message-
> From: Albecki, Mateusz 
> mailto:mateusz.albe...@intel.com>>
> Sent: Wednesday, March 22, 2023 4:20 AM
> To: devel@edk2.groups.io
> Cc: Albecki, Mateusz 
> mailto:mateusz.albe...@intel.com>>; Wu, Hao A
> mailto:hao.a...@intel.com>>; Ni, Ray 
> mailto:ray...@intel.com>>; Chang, Hunter
> mailto:hunter.ch...@intel.com>>
> Subject: [PATCH 0/1] MdeModulePkg/Ahci: Skip retry for non-transient errors
>
> Fix for the recovery logic which causes hdd unlock to fail if user supplies
> incorrect password. Every failed packet used to be recovered which is causing
> the incorrect password to be tried multiple times. This patch series fixes the
> logic to only retry commands that failed due to CRC error.
>
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4011
>
> Github pull: https://github.com/tianocore/edk2/pull/4157
>
> Tests:
> - tested basic linux boot from AHCI on qemu
> - tested basic linux boot from AHCI on custom qemu which will fail 50% of the
> DMA commands with CRC error.
> Observed that all of the packets that failed were successfully retried. Custom
> Qemu: https://github.com/matalbec/qemu/tree/sata_dma_50p_fail
> - additionally Hunter Chang tested and confirmed that the password issue is no
> longer observed.
>
> Cc: Hao A Wu mailto:hao.a...@intel.com>>
> Cc: Ray Ni mailto:ray...@intel.com>>
> Cc: Hunter Chang mailto:hunter.ch...@intel.com>>
>
> Mateusz Albecki (1):
> MdeModulePkg/Ahci: Skip retry for non-transient errors
>
> .../Bus/Ata/AtaAtapiPassThru/AhciMode.c | 69 +--
> .../Bus/Ata/AtaAtapiPassThru/AhciMode.h | 3 +-
> 2 files changed, 67 insertions(+), 5 deletions(-)
>
> --
> 2.39.1.windows.1





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Re: [edk2-devel] [PATCH V5 4/8] OvmfPkg/PlatformPei: Update ReserveEmuVariableNvStore

[Min Xu]

Hi, joeyli
Please see my comments in https://bugzilla.tianocore.org/show_bug.cgi?id=4379
I need your help to catch some logs in AMD SEV environment for this problem.

Thanks
Min

> -Original Message-
> From: joeyli 
> Sent: Tuesday, March 21, 2023 5:32 PM
> To: devel@edk2.groups.io; Xu, Min M 
> Cc: Aktas, Erdem ; James Bottomley
> ; Yao, Jiewen ; Tom Lendacky
> ; Gerd Hoffmann 
> Subject: Re: [edk2-devel] [PATCH V5 4/8] OvmfPkg/PlatformPei: Update
> ReserveEmuVariableNvStore
> 
> Hi Min M Xu,
> 
> I have filed a EDK2 bug relates to this patch:
> 
> Bug 4379 - Got NvVarStore FV headers were invalid when using OVMF with
> AMD SEV
> https://bugzilla.tianocore.org/show_bug.cgi?id=4379
> 
> I got a "NvVarStore FV headers were invalid." assert when using OVMF with
> AMD SEV. After reverted this patch, the assert is gone.
> 
> Thanks!
> Joey Lee
> 
> On Tue, Sep 06, 2022 at 12:35:56PM +0800, Min Xu via groups.io wrote:
> > From: Min M Xu 
> >
> > ReserveEmuVariableNvStore is updated with below 2 functions defined in
> > PlatformInitLib:
> >  - PlatformReserveEmuVariableNvStore
> >  - PlatformInitEmuVariableNvStore
> >
> > PlatformInitEmuVariableNvStore works when secure boot feature is enabled.
> > This is because secure boot needs the EFI variables (PK/KEK/DB/DBX,
> > etc) and EmuVariableNvStore is cleared when OVMF is launched with
> > -bios parameter.
> >
> > Cc: Erdem Aktas 
> > Cc: James Bottomley 
> > Cc: Jiewen Yao 
> > Cc: Tom Lendacky 
> > Cc: Gerd Hoffmann 
> > Acked-by: Gerd Hoffmann 
> > Signed-off-by: Min Xu 
> > ---
> >  OvmfPkg/PlatformPei/Platform.c | 25 +++--
> >  1 file changed, 7 insertions(+), 18 deletions(-)
> >
> > diff --git a/OvmfPkg/PlatformPei/Platform.c
> > b/OvmfPkg/PlatformPei/Platform.c index 009db67ee60a..b1f8140d6041
> > 100644
> > --- a/OvmfPkg/PlatformPei/Platform.c
> > +++ b/OvmfPkg/PlatformPei/Platform.c
> > @@ -220,24 +220,13 @@ ReserveEmuVariableNvStore (
> >EFI_PHYSICAL_ADDRESS  VariableStore;
> >RETURN_STATUS PcdStatus;
> >
> > -  //
> > -  // Allocate storage for NV variables early on so it will be
> > -  // at a consistent address.  Since VM memory is preserved
> > -  // across reboots, this allows the NV variable storage to survive
> > -  // a VM reboot.
> > -  //
> > -  VariableStore =
> > -(EFI_PHYSICAL_ADDRESS)(UINTN)
> > -AllocateRuntimePages (
> > -  EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))
> > -  );
> > -  DEBUG ((
> > -DEBUG_INFO,
> > -"Reserved variable store memory: 0x%lX; size: %dkb\n",
> > -VariableStore,
> > -(2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
> > -));
> > -  PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved,
> > VariableStore);
> > +  VariableStore =
> (EFI_PHYSICAL_ADDRESS)(UINTN)PlatformReserveEmuVariableNvStore ();
> > +  PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);
> > +
> > + #ifdef SECURE_BOOT_FEATURE_ENABLED
> > +  PlatformInitEmuVariableNvStore ((VOID *)(UINTN)VariableStore);
> > + #endif
> > +
> >ASSERT_RETURN_ERROR (PcdStatus);
> >  }
> >
> > --
> > 2.29.2.windows.2
> >
> >
> >
> > 
> >


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Re: [edk2-devel] [PATCH v3] MdePkg/Include: Add DMTF MCTP definitions

[Michael D Kinney]

> -Original Message-
> From: abner.ch...@amd.com 
> Sent: Thursday, March 23, 2023 8:05 AM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D ; Gao, Liming 
> ; Liu, Zhiguang ;
> Nickle Wang ; Igor Kulchytskyy ; Oram, 
> Isaac W ; Abdul Lateef Attar
> 
> Subject: [PATCH v3] MdePkg/Include: Add DMTF MCTP definitions
> 
> From: Abner Chang 
> 
> BZ #4355
> This change adds definitions for DMTF MCTP
> base specification.
> 
> Spec ref:
> https://www.dmtf.org/sites/default/files/standards/documents/DSP0236_1.3.1.pdf
> 
> Signed-off-by: Abner Chang 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Cc: Nickle Wang 
> Cc: Igor Kulchytskyy 
> Cc: Isaac Oram 
> Cc: Abdul Lateef Attar 
> Acked-by: Isaac Oram 
> ---
>  MdePkg/Include/IndustryStandard/Mctp.h | 138 +
>  1 file changed, 138 insertions(+)
>  create mode 100644 MdePkg/Include/IndustryStandard/Mctp.h
> 
> diff --git a/MdePkg/Include/IndustryStandard/Mctp.h 
> b/MdePkg/Include/IndustryStandard/Mctp.h
> new file mode 100644
> index 000..bfbc843c7f1
> --- /dev/null
> +++ b/MdePkg/Include/IndustryStandard/Mctp.h
> @@ -0,0 +1,138 @@
> +/** @file
> +
> +  The definitions of DMTF Management Component Transport Protocol (MCTP)
> +  Base Specification.
> +
> +  Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +  @par Revision Reference:
> +  DMTF Management Component Transport Protocol (MCTP) Base Specification
> +  Version 1.3.1
> +  
> https://www.dmtf.org/sites/default/files/standards/documents/DSP0236_1.3.1.pdf
> +**/
> +
> +#ifndef MCTP_H_
> +#define MCTP_H_
> +
> +///
> +/// Definitions of endpoint ID
> +///
> +#define MCTP_NULL_DESTINATION_ENDPOINT_ID  0
> +#define MCTP_NULL_SOURCE_ENDPOINT_ID   0
> +#define MCTP_RESERVED_ENDPOINT_START_ID1
> +#define MCTP_RESERVED_ENDPOINT_END_ID  7
> +#define MCTP_BROADCAST_ENDPOINT_ID 0xFF
> +
> +/// Minimum transmission size is 64 bytes.
> +/// The value of 64 is defined in MCTP Base Specification.
> +#define MCTP_BASELINE_MINIMUM_UNIT_TRANSMISSION_SIZE  0x40
> +
> +///
> +/// The 32-bit Header of MCTP packet.
> +///
> +typedef union {
> +  struct {
> +UINT8HeaderVersion : 4; ///< The version of header.
> +UINT8Reserved  : 4; ///< Reserved for future definitions.
> +UINT8DestinationEndpointId : 8; ///< Destination endpoint Id (EID).
> +UINT8SourceEndpointIdId: 8; ///< Source endpoint Id (EID)
> +UINT8MessageTag: 3; ///< Check the MCTP Base 
> specification for the
> +///< usages.
> +UINT8TagOwner  : 1; ///< Tag owner identifies the 
> message was
> +///< originated by the source EID or
> +///< destination EID.
> +UINT8PacketSequence: 2; ///< Sequence number increments 
> Modulo 4 on
> +///< each packet.
> +UINT8EndOfMessage  : 1; ///< Indicates the last packet of 
> message.
> +UINT8StartOfMessage: 1; ///< Indicates the first packet of 
> message.

These bitfields should be type UINT32

> +  } Bits;
> +  UINT32Header;
> +} MCTP_TRANSPORT_HEADER;
> +
> +///
> +/// The 8-bit Message Header of MCTP packet.
> +///
> +typedef union {
> +  struct {
> +UINT8MessageType   : 7;
> +UINT8ItegrityCheck : 1;
> +  } Bits;
> +  UINT8MessageHeader;
> +} MCTP_MESSAGE_HEADER;
> +
> +///
> +/// MCTP Control Commands
> +///
> +#define   MCTP_CONTROL_RESERVED0x00
> +#define   MCTP_CONTROL_SET_ENDPOINT_ID 0x01
> +#define   MCTP_CONTROL_GET_ENDPOINT_ID 0x02
> +#define   MCTP_CONTROL_GET_ENDPOINT_UUID   0x03
> +#define   MCTP_CONTROL_GET_MCTP_VERSION_SUPPORT0x04
> +#define   MCTP_CONTROL_GET_MESSAGE_TYPE_SUPPORT0x05
> +#define   MCTP_CONTROL_GET_VENDOR_DEFINED_MESSAGE_SUPPORT  0x06
> +#define   MCTP_CONTROL_RESOLVE_ENDPOINT_ID 0x07
> +#define   MCTP_CONTROL_ALLOCATE_ENDPOINT_IDS   0x08
> +#define   MCTP_CONTROL_ROUTING_INFORMATION_UPDATE  0x09
> +#define   MCTP_CONTROL_GET_ROUTINE_TABLE_ENTRIES   0x0A
> +#define   MCTP_CONTROL_PREPARE_FOR_ENDPOINT_DISCOVERY  0x0B
> +#define   MCTP_CONTROL_ENDPOINT_DISCOVERY  0x0C
> +#define   MCTP_CONTROL_DISCOVERY_NOTIFY0x0D
> +#define   MCTP_CONTROL_GET_NETWORK_ID  0x0E
> +#define   MCTP_CONTROL_QUERY_HOP   0x0F
> +#define   MCTP_CONTROL_RESOLVE_UUID0x10
> +#define   MCTP_CONTROL_QUERY_RATE_LIMIT0x11
> +#define   MCTP_CONTROL_REQUEST_TX_RATE_LIMIT   0x12
> +#define   MCTP_CONTROL_UPDATE_RATE_LIMIT   0x13
> +#define   

Re: [edk2-devel] [PATCH v3] MdePkg/Include: Add IPMI KCS definitions

[Michael D Kinney]

> -Original Message-
> From: abner.ch...@amd.com 
> Sent: Thursday, March 23, 2023 6:58 AM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D ; Gao, Liming 
> ; Liu, Zhiguang ;
> Nickle Wang ; Igor Kulchytskyy ; Oram, 
> Isaac W ; Abdul Lateef Attar
> 
> Subject: [PATCH v3] MdePkg/Include: Add IPMI KCS definitions
> 
> From: Abner Chang 
> 
> BZ #4354
> This change adds definitions for IPMI KCS.
> 
> Spec ref:
> https://www.intel.com/content/www/us/en/products/docs/servers/ipmi/ipmi-second-gen-interface-spec-v2-rev1-1.html
> 
> Signed-off-by: Abner Chang 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Cc: Nickle Wang 
> Cc: Igor Kulchytskyy 
> Cc: Isaac Oram 
> Cc: Abdul Lateef Attar 
> Acked-by: Isaac Oram 
> ---
>  MdePkg/MdePkg.dec |  6 ++
>  MdePkg/Include/IndustryStandard/IpmiKcs.h | 76 +++
>  2 files changed, 82 insertions(+)
>  create mode 100644 MdePkg/Include/IndustryStandard/IpmiKcs.h
> 
> diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
> index 2d643bede1d..5cf04bc0cb6 100644
> --- a/MdePkg/MdePkg.dec
> +++ b/MdePkg/MdePkg.dec
> @@ -9,6 +9,7 @@
>  # (C) Copyright 2016 - 2021 Hewlett Packard Enterprise Development LP
>  # Copyright (c) 2022, Loongson Technology Corporation Limited. All rights 
> reserved.
>  # Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
> +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent
>  #
> @@ -2342,6 +2343,11 @@
># @Prompt Memory Address of GuidedExtractHandler Table.
>
> gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|0x100|UINT64|0x30001015
> 
> +  ## This value is the IPMI KCS Interface I/O base address used to transmit 
> IPMI commands.
> +  #  The value of 0xca2 is the default I/O base address defined in IPMI 
> specification.
> +  # @Prompt IPMI KCS Interface I/O Base Address
> +  gEfiMdePkgTokenSpaceGuid.PcdIpmiKcsIoBaseAddress|0xca2|UINT16|0x0031
> +
>  [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
>## This value is used to set the base address of PCI express hierarchy.
># @Prompt PCI Express Base Address.
> diff --git a/MdePkg/Include/IndustryStandard/IpmiKcs.h 
> b/MdePkg/Include/IndustryStandard/IpmiKcs.h
> new file mode 100644
> index 000..c3baf80bd76
> --- /dev/null
> +++ b/MdePkg/Include/IndustryStandard/IpmiKcs.h
> @@ -0,0 +1,76 @@
> +/** @file
> +  IPMI KCS Register Definitions
> +
> +  Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +  @par Revision Reference:
> +  IPMI Specification
> +  Version 2.0, Rev. 1.1
> +  
> https://www.intel.com/content/www/us/en/products/docs/servers/ipmi/ipmi-second-gen-interface-spec-v2-rev1-1.html
> +**/
> +
> +#ifndef IPMI_KCS_H_
> +#define IPMI_KCS_H_
> +
> +#define IPMI_KCS_STATUS_REGISTER_OFFSET1
> +#define IPMI_KCS_COMMAND_REGISTER_OFFSET   1
> +#define IPMI_KCS_DATA_OUT_REGISTER_OFFSET  0
> +#define IPMI_KCS_DATA_IN_REGISTER_OFFSET   0
> +
> +///
> +/// IPMI KCS Interface Status Bits
> +///
> +#define IPMI_KCS_OBF   BIT0
> +#define IPMI_KCS_IBF   BIT1
> +#define IPMI_KCS_SMS_ATN   BIT2
> +#define IPMI_KCS_COMMAND_DATA  BIT3
> +#define IPMI_KCS_OEM1  BIT4
> +#define IPMI_KCS_OEM2  BIT5
> +#define IPMI_KCS_S0BIT6
> +#define IPMI_KCS_S1BIT7
> +
> +///
> +/// IPMI KCS Interface Control Codes
> +///
> +#define IPMI_KCS_CONTROL_CODE_GET_STATUS_ABORT  0x60
> +#define IPMI_KCS_CONTROL_CODE_WRITE_START   0x61
> +#define IPMI_KCS_CONTROL_CODE_WRITE_END 0x62
> +#define IPMI_KCS_CONTROL_CODE_READ  0x68
> +
> +///
> +/// Status Codes
> +///
> +#define IPMI_KCS_STATUS_NO_ERROR  0x00
> +#define IPMI_KCS_STATUS_ABORT 0x01
> +#define IPMI_KCS_STATUS_ILLEGAL   0x02
> +#define IPMI_KCS_STATUS_LENGTH_ERROR  0x06
> +#define IPMI_KCS_STATUS_UNSPECIFIED   0xFF
> +
> +///
> +/// KCS Interface State Bit
> +///
> +typedef enum {
> +  IPMI_KCS_IDLE_STATE = 0,
> +  IPMI_KCS_READ_STATE,
> +  IPMI_KCS_WRITE_STATE,
> +  IPMI_KCS_ERROR_STATE
> +} IPMI_KCS_STATE;
> +
> +///
> +/// IPMI KCS Interface Request Format
> +///
> +typedef struct {
> +  UINT8NetFunc;
> +  UINT8Command;
> +  UINT8Data[0];

I think flexible array members are supposed to use [] and not [0].

> +} IPMI_KCS_RESQUEST_HEADER;
> +
> +///
> +/// IPMI KCS Interface Response Format
> +///
> +typedef struct {
> +  UINT8NetFunc;
> +  UINT8Command;
> +} IPMI_KCS_RESPONSE_HEADER;
> +#endif
> --
> 2.37.1.windows.1



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Re: [edk2-devel] PATCH v1 1/1 MdePkg: Remove Itanium leftover data structure

[Michael D Kinney]

Hi Pawel,

Any updates on this task?

I would like to see this go in soon so it can get some flight time before next 
stable tag.

Mike

> -Original Message-
> From: Kinney, Michael D 
> Sent: Tuesday, March 7, 2023 2:25 PM
> To: Paweł Poławski ; devel@edk2.groups.io
> Cc: Gao, Liming ; Liu, Zhiguang 
> ; Zimmer, Vincent ;
> Kinney, Michael D 
> Subject: RE: [edk2-devel] PATCH v1 1/1 MdePkg: Remove Itanium leftover data 
> structure
> 
> Hi Pawel,
> 
> Can you please also reference the following BZ and commit in the commit 
> message
> 
> https://bugzilla.tianocore.org/show_bug.cgi?id=1560
> https://github.com/tianocore/edk2/commit/4e1daa60f5372c22a11503961061ffa569eaf873
> 
> If you post a branch with these small updates and my Rb and send it
> through EDK II CI, I can do the push from there.
> 
> Thanks,
> 
> Mike
> 
> > -Original Message-
> > From: Kinney, Michael D 
> > Sent: Tuesday, March 7, 2023 1:59 PM
> > To: Paweł Poławski ; devel@edk2.groups.io
> > Cc: Gao, Liming ; Liu, Zhiguang 
> > ; Zimmer, Vincent
> > ; Kinney, Michael D 
> > Subject: RE: [edk2-devel] PATCH v1 1/1 MdePkg: Remove Itanium leftover data 
> > structure
> >
> > Hi Pawel,
> >
> > With suggestion from Vincent, let's remove ItaniumHealthFlags.
> >
> > https://edk2.groups.io/g/devel/message/100812
> >
> > I recommend adding a note in the comment block for the
> > EFI_SEC_PLATFORM_INFORMATION_RECORD that with the removal of the
> > ItaniumHealthFlags, this union has diverged from the PI
> > Specification definition.
> >
> > With that one comment addition:
> >
> > Reviewed-by: Michael D Kinney 
> >
> > Mike
> >
> >
> > > -Original Message-
> > > From: Paweł Poławski 
> > > Sent: Thursday, December 1, 2022 7:36 AM
> > > To: devel@edk2.groups.io
> > > Cc: Kinney, Michael D ; Gao, Liming 
> > > ; Liu, Zhiguang
> > > 
> > > Subject: [edk2-devel] PATCH v1 1/1 MdePkg: Remove Itanium leftover data 
> > > structure
> > >
> > > Itanium support has been removed from EDK2 aroun 2019.
> > > ITANIUM_HANDOFF_STATUS data structure looks to be
> > > some leftover from that process.
> > >
> > > There is also positive sidefect of this data structure removal.
> > > Due to HOB allocation type used in PEI stage there is a limit
> > > how much data about virtual CPU can be hold. This limit result
> > > in only 1024 vCPU can be used by VM.
> > > With Itanium related data structure removed more allocated space
> > > can be used for vCPU data and with current allocation limit
> > > will change from 1024 to around 8k vCPUs.
> > >
> > > Cc: Michael D Kinney 
> > > Cc: Liming Gao 
> > > Cc: Zhiguang Liu 
> > >
> > > Signed-off-by: Paweł Poławski 
> > > ---
> > >  MdePkg/Include/Ppi/SecPlatformInformation.h | 44 
> > >  1 file changed, 44 deletions(-)
> > >
> > > diff --git a/MdePkg/Include/Ppi/SecPlatformInformation.h 
> > > b/MdePkg/Include/Ppi/SecPlatformInformation.h
> > > index 02b0711f189e..fbcd205acd96 100644
> > > --- a/MdePkg/Include/Ppi/SecPlatformInformation.h
> > > +++ b/MdePkg/Include/Ppi/SecPlatformInformation.h
> > > @@ -84,49 +84,6 @@ typedef union {
> > >
> > >  typedef EFI_HEALTH_FLAGS X64_HANDOFF_STATUS;
> > >  typedef EFI_HEALTH_FLAGS IA32_HANDOFF_STATUS;
> > > -///
> > > -/// The hand-off status structure for Itanium architecture.
> > > -///
> > > -typedef struct {
> > > -  ///
> > > -  /// SALE_ENTRY state : 3 = Recovery_Check
> > > -  /// and 0 = RESET or Normal_Boot phase.
> > > -  ///
> > > -  UINT8 BootPhase;
> > > -  ///
> > > -  /// Firmware status on entry to SALE.
> > > -  ///
> > > -  UINT8 FWStatus;
> > > -  UINT16Reserved1;
> > > -  UINT32Reserved2;
> > > -  ///
> > > -  /// Geographically significant unique processor ID assigned by PAL.
> > > -  ///
> > > -  UINT16ProcId;
> > > -  UINT16Reserved3;
> > > -  UINT8 IdMask;
> > > -  UINT8 EidMask;
> > > -  UINT16Reserved4;
> > > -  ///
> > > -  /// Address to make PAL calls.
> > > -  ///
> > > -  UINT64PalCallAddress;
> > > -  ///
> > > -  /// If the entry state is RECOVERY_CHECK, this contains the PAL_RESET
> > > -  /// return address, and if entry state is RESET, this contains
> > > -  /// address for PAL_authentication call.
> > > -  ///
> > > -  UINT64PalSpecialAddress;
> > > -  ///
> > > -  /// GR35 from PALE_EXIT state.
> > > -  ///
> > > -  UINT64SelfTestStatus;
> > > -  ///
> > > -  /// GR37 from PALE_EXIT state.
> > > -  ///
> > > -  UINT64SelfTestControl;
> > > -  UINT64MemoryBufferRequired;
> > > -} ITANIUM_HANDOFF_STATUS;
> > >
> > >  ///
> > >  /// EFI_SEC_PLATFORM_INFORMATION_RECORD.
> > > @@ -134,7 +91,6 @@ typedef struct {
> > >  typedef union {
> > >IA32_HANDOFF_STATUS   IA32HealthFlags;
> > >X64_HANDOFF_STATUSx64HealthFlags;
> > > -  ITANIUM_HANDOFF_STATUSItaniumHealthFlags;
> > >  } EFI_SEC_PLATFORM_INFORMATION_RECORD;
> > >
> > >  /**
> > > --
> > > 2.38.1



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Re: [edk2-devel] [PATCH v4 7/9] ManageabilityPkg: Implement Ipmi Protocol/Ppi

[Tinh Nguyen via groups.io]

Hi Abner,


On 3/22/2023 9:48 AM, Chang, Abner via groups.io wrote:

From: Abner Chang 

Add Ipmi Protocol/Ppi/SMM implementations.
The underlying implementation of transport
interface depends on the binded
ManageabilityTransportLib.

Signed-off-by: Abner Chang 
Cc: Liming Gao 
Cc: Isaac Oram 
Cc: Nate DeSimone 
Cc: Abdul Lateef Attar 
Cc: Nickle Wang 
Cc: Igor Kulchytskyy 
---
  .../IpmiProtocol/Dxe/IpmiProtocolDxe.inf  |  50 
  .../Universal/IpmiProtocol/Pei/IpmiPpiPei.inf |  53 
  .../IpmiProtocol/Smm/IpmiProtocolSmm.inf  |  52 
  .../IpmiProtocol/Common/IpmiProtocolCommon.h  | 108 
  .../IpmiProtocol/Pei/IpmiPpiInternal.h|  25 ++
  .../IpmiProtocol/Common/IpmiProtocolCommon.c  | 252 ++
  .../Universal/IpmiProtocol/Dxe/IpmiProtocol.c | 177 
  .../Universal/IpmiProtocol/Pei/IpmiPpi.c  | 159 +++
  .../Universal/IpmiProtocol/Smm/IpmiProtocol.c | 147 ++
  9 files changed, 1023 insertions(+)
  create mode 100644 
Features/ManageabilityPkg/Universal/IpmiProtocol/Dxe/IpmiProtocolDxe.inf
  create mode 100644 
Features/ManageabilityPkg/Universal/IpmiProtocol/Pei/IpmiPpiPei.inf
  create mode 100644 
Features/ManageabilityPkg/Universal/IpmiProtocol/Smm/IpmiProtocolSmm.inf
  create mode 100644 
Features/ManageabilityPkg/Universal/IpmiProtocol/Common/IpmiProtocolCommon.h
  create mode 100644 
Features/ManageabilityPkg/Universal/IpmiProtocol/Pei/IpmiPpiInternal.h
  create mode 100644 
Features/ManageabilityPkg/Universal/IpmiProtocol/Common/IpmiProtocolCommon.c
  create mode 100644 
Features/ManageabilityPkg/Universal/IpmiProtocol/Dxe/IpmiProtocol.c
  create mode 100644 
Features/ManageabilityPkg/Universal/IpmiProtocol/Pei/IpmiPpi.c
  create mode 100644 
Features/ManageabilityPkg/Universal/IpmiProtocol/Smm/IpmiProtocol.c

diff --git 
a/Features/ManageabilityPkg/Universal/IpmiProtocol/Dxe/IpmiProtocolDxe.inf 
b/Features/ManageabilityPkg/Universal/IpmiProtocol/Dxe/IpmiProtocolDxe.inf
new file mode 100644
index 00..ff5ec56c73
--- /dev/null
+++ b/Features/ManageabilityPkg/Universal/IpmiProtocol/Dxe/IpmiProtocolDxe.inf
@@ -0,0 +1,50 @@
+## @file
+# IPMI Protocol DXE Driver.
+#
+# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+  INF_VERSION= 0x0001001d
+  BASE_NAME  = IpmiDxe
+  FILE_GUID  = BC41B0C2-9D8A-42B5-A28F-02CE0D4A6C28
+  MODULE_TYPE= DXE_DRIVER
+  VERSION_STRING = 1.0
+  ENTRY_POINT= DxeIpmiEntry
+  UNLOAD_IMAGE   = IpmiUnloadImage
+
+#
+#  VALID_ARCHITECTURES   = IA32 X64 ARM AARCH64
+#
+
+[Sources]
+  IpmiProtocol.c
+  ../Common/IpmiProtocolCommon.c
+  ../Common/IpmiProtocolCommon.h
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ManageabilityPkg/ManageabilityPkg.dec
+
+[LibraryClasses]
+  BaseMemoryLib
+  DebugLib
+  ManageabilityTransportHelperLib
+  ManageabilityTransportLib
+  UefiDriverEntryPoint
+  UefiBootServicesTableLib
+
+[Protocols]
+  gIpmiProtocolGuid   # PROTOCOL ALWAYS_PRODUCED
+
+[Guids]
+  gManageabilityProtocolIpmiGuid
+  gManageabilityTransportKcsGuid
+
+[FixedPcd]
+  gEfiMdePkgTokenSpaceGuid.PcdIpmiKcsBaseAddress
+
+[Depex]
+  TRUE
diff --git 
a/Features/ManageabilityPkg/Universal/IpmiProtocol/Pei/IpmiPpiPei.inf 
b/Features/ManageabilityPkg/Universal/IpmiProtocol/Pei/IpmiPpiPei.inf
new file mode 100644
index 00..4e00693f64
--- /dev/null
+++ b/Features/ManageabilityPkg/Universal/IpmiProtocol/Pei/IpmiPpiPei.inf
@@ -0,0 +1,53 @@
+## @file
+# IPMI Protocol PEI Driver.
+#
+# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+  INF_VERSION= 0x0001001d
+  BASE_NAME  = IpmiPei
+  FILE_GUID  = 7832F989-CB72-4715-ADCA-35C0B031856C
+  MODULE_TYPE= PEIM
+  VERSION_STRING = 1.0
+  ENTRY_POINT= PeiIpmiEntry
+
+#
+# The following information is for reference only and not required by the 
build tools.
+#
+#  VALID_ARCHITECTURES   = IA32 X64 ARM AARCH64
+#
+
+[Sources]
+  IpmiPpi.c
+  IpmiPpiInternal.h
+  ../Common/IpmiProtocolCommon.c
+  ../Common/IpmiProtocolCommon.h
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ManageabilityPkg/ManageabilityPkg.dec
+
+[LibraryClasses]
+  BaseMemoryLib
+  DebugLib
+  MemoryAllocationLib
+  ManageabilityTransportHelperLib
+  ManageabilityTransportLib
+  PeimEntryPoint
+  ManageabilityTransportLib

Duplicate ManageabilityTransportLib

+
+[Ppis]
+  gPeiIpmiPpiGuid   # PPI ALWAYS PRODUCED
+
+[Guids]
+  gManageabilityProtocolIpmiGuid
+  gManageabilityTransportKcsGuid
+
+[FixedPcd]
+  gEfiMdePkgTokenSpaceGuid.PcdIpmiKcsBaseAddress
+
+[Depex]
+  TRUE
diff --git 

Re: [edk2-devel] [Patch 0/2] Add and use FirmwareVolumeShadowPpi

[Michael D Kinney]

Series Reviewed-by: Michael D Kinney 

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Michael D 
> Kinney
> Sent: Tuesday, March 21, 2023 7:06 PM
> To: devel@edk2.groups.io
> Cc: Yao, Jiewen ; Wang, Jian J ; 
> Gao, Liming ; Patel, Umang
> 
> Subject: [edk2-devel] [Patch 0/2] Add and use FirmwareVolumeShadowPpi
> 
> Add FirmwareVolumeShadow PPI to shadow an FV to memory.
> and use it to shadow FVs to memory.
> 
> Cc: Jiewen Yao 
> Cc: Jian J Wang 
> Cc: Liming Gao 
> Signed-off-by: Patel Umang 
> 
> Umang Patel (2):
>   MdeModulePkg/Include/Ppi: Add FirmwareVolumeShadowPpi
>   SecurityPkg/FvReportPei: Use FirmwareVolumeShadowPpi
> 
>  .../Include/Ppi/FirmwareVolumeShadowPpi.h | 61 +++
>  MdeModulePkg/MdeModulePkg.dec |  3 +
>  SecurityPkg/FvReportPei/FvReportPei.c | 37 ---
>  SecurityPkg/FvReportPei/FvReportPei.h |  1 +
>  SecurityPkg/FvReportPei/FvReportPei.inf   |  1 +
>  5 files changed, 96 insertions(+), 7 deletions(-)
>  create mode 100644 MdeModulePkg/Include/Ppi/FirmwareVolumeShadowPpi.h
> 
> --
> 2.39.1.windows.1
> 
> 
> 
> 
> 



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Re: [edk2-devel] [PATCH v4 5/9] ManageabilityPkg: Add ManageabilityTransportHelperLib

[Tinh Nguyen via groups.io]

Hi Abner,

On 3/22/2023 9:48 AM, Chang, Abner via groups.io wrote:

From: Abner Chang 

The helper functions library facilitates reducing
duplicated code in the manageability transport
library instances.

Signed-off-by: Abner Chang 
Cc: Liming Gao 
Cc: Isaac Oram 
Cc: Nate DeSimone 
Cc: Nickle Wang 
Cc: Igor Kulchytskyy 
Cc: Abdul Lateef Attar 
---
  .../ManageabilityPkg/ManageabilityPkg.dec |  24 +-
  .../Include/Dsc/Manageability.dsc |   2 +
  .../BaseManageabilityTransportHelper.inf  |  41 +++
  .../Library/ManageabilityTransportHelperLib.h |  93 +++
  .../BaseManageabilityTransportHelper.c| 261 ++
  .../BaseManageabilityTransportHelper.uni  |  13 +
  6 files changed, 433 insertions(+), 1 deletion(-)
  create mode 100644 
Features/ManageabilityPkg/Library/BaseManageabilityTransportHelperLib/BaseManageabilityTransportHelper.inf
  create mode 100644 
Features/ManageabilityPkg/Include/Library/ManageabilityTransportHelperLib.h
  create mode 100644 
Features/ManageabilityPkg/Library/BaseManageabilityTransportHelperLib/BaseManageabilityTransportHelper.c
  create mode 100644 
Features/ManageabilityPkg/Library/BaseManageabilityTransportHelperLib/BaseManageabilityTransportHelper.uni

diff --git a/Features/ManageabilityPkg/ManageabilityPkg.dec 
b/Features/ManageabilityPkg/ManageabilityPkg.dec
index 92ba4538c0..ebbb04dc0e 100644
--- a/Features/ManageabilityPkg/ManageabilityPkg.dec
+++ b/Features/ManageabilityPkg/ManageabilityPkg.dec
@@ -22,5 +22,27 @@
#   Manageability Transport Library definitions
ManageabilityTransportLib|Include/Library/ManageabilityTransportLib.h
  
+  ##  @libraryclass Manageability Transport Helper Library

+  #   Provide the help functions to use ManageabilityTransportLib
+  
ManageabilityTransportHelperLib|Include/Library/ManageabilityTransportHelperLib.h
+
  [Guids]
-  gManageabilityPkgTokenSpaceGuid = { 0xBDEFFF48, 0x1C31, 0x49CD, { 0xA7, 
0x6D, 0x92, 0x9E, 0x60, 0xDB, 0xB9, 0xF8 } }
+  gManageabilityPkgTokenSpaceGuid   = { 0xBDEFFF48, 0x1C31, 0x49CD, { 0xA7, 
0x6D, 0x92, 0x9E, 0x60, 0xDB, 0xB9, 0xF8 } }
+
+  # Manageability Transport Interface type
+  #
+  # Manageability Transport KCS
+  gManageabilityTransportKcsGuid= { 0x5A6E64E9, 0xFD47, 0x4086, { 0xAA, 
0xB0, 0x7A, 0x5F, 0xD7, 0x6B, 0x02, 0x2E } }
+  # Manageability Transport I2C
+  gManageabilityTransportI2CGuid= { 0x5B174658, 0x8263, 0x4CB8, { 0xA0, 
0x0F, 0xD6, 0x82, 0xE6, 0xBC, 0x74, 0x93 } }
+  # Manageability Transport PCI VDM
+  gManageabilityTransportPciVdmGuid = { 0x388021A7, 0xFB59, 0x4811, { 0x9D, 
0xA7, 0xD5, 0x63, 0x7D, 0x04, 0xA7, 0x2F } }
+
+  # Manageability Protocol Specification
+  #
+  # Manageability Protocol IPMI
+  gManageabilityProtocolIpmiGuid= { 0x36ACA47C, 0xCC80, 0x473B, { 0xAB, 
0xEC, 0xF3, 0x98, 0xFF, 0x87, 0x74, 0x5B } }
+  # Manageability Protocol MCTP
+  gManageabilityProtocolMctpGuid= { 0x76FED8F1, 0x0BE5, 0x4269, { 0xA3, 
0x1A, 0x38, 0x0F, 0x54, 0xF1, 0xA1, 0x8A } }
+  # Manageability Protocol PLDM
+  gManageabilityProtocolPldmGuid= { 0x3958090D, 0x69DD, 0x4868, { 0x9C, 
0x41, 0xC9, 0xAC, 0x31, 0xB5, 0x25, 0xC5 } }
diff --git a/Features/ManageabilityPkg/Include/Dsc/Manageability.dsc 
b/Features/ManageabilityPkg/Include/Dsc/Manageability.dsc
index 2cb63c1ca6..994c93f17c 100644
--- a/Features/ManageabilityPkg/Include/Dsc/Manageability.dsc
+++ b/Features/ManageabilityPkg/Include/Dsc/Manageability.dsc
@@ -5,6 +5,8 @@
  # SPDX-License-Identifier: BSD-2-Clause-Patent
  #
  ##
+[LibraryClasses]
+  
ManageabilityTransportHelperLib|ManageabilityPkg/Library/BaseManageabilityTransportHelperLib/BaseManageabilityTransportHelper.inf
  
  [LibraryClasses.ARM, LibraryClasses.AARCH64]

#
diff --git 
a/Features/ManageabilityPkg/Library/BaseManageabilityTransportHelperLib/BaseManageabilityTransportHelper.inf
 
b/Features/ManageabilityPkg/Library/BaseManageabilityTransportHelperLib/BaseManageabilityTransportHelper.inf
new file mode 100644
index 00..95c3362ddb
--- /dev/null
+++ 
b/Features/ManageabilityPkg/Library/BaseManageabilityTransportHelperLib/BaseManageabilityTransportHelper.inf
@@ -0,0 +1,41 @@
+## @file
+# Null instance of Manageability Transport Helper Library
+#
+# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 0x0001001B
+  BASE_NAME  = BaseManageabilityTransportHelper
+  MODULE_UNI_FILE= BaseManageabilityTransportHelper.uni
+  FILE_GUID  = 52F2DE11-A8FC-4A06-B8C6-10DCF4A7397C
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = ManageabilityTransportHelperLib
+
+#
+#  VALID_ARCHITECTURES   = IA32 X64 ARM AARCH64
+#
+
+[Sources]
+  BaseManageabilityTransportHelper.c
+
+[LibraryClasses]
+  BaseMemoryLib
+  DebugLib
+
+[Packages]
+  

Re: [edk2-devel] [PATCH v4 2/9] ManageabilityPkg: Initial package

[Isaac Oram]

Reviewed-by: Isaac Oram 

edk2 convention has changed to naming DSC include files *.dsc.inc.  I plan to 
update all the features sometime in the future.

Manageability.dsc:
I think that the "[LibraryClasses.ARM, LibraryClasses.AARCH64]" section 
contents should be moved to the ManageabilityPkg.dsc for package specific build 
settings.  These seem like ARM libraries not directly related to manageability 
features and we don't really want Manageability.dsc to override any board 
porting choices already made by the board.  And I think that we want these 
includable feature DSC to be scoped to the feature only as much as we can.

Regards,
Isaac

-Original Message-
From: devel@edk2.groups.io  On Behalf Of Chang, Abner via 
groups.io
Sent: Tuesday, March 21, 2023 7:49 PM
To: devel@edk2.groups.io
Cc: Gao, Liming ; Oram, Isaac W 
; Desimone, Nathaniel L 
; Abdul Lateef Attar ; Nickle 
Wang ; Igor Kulchytskyy ; Abdul Lateef Attar 

Subject: [edk2-devel] [PATCH v4 2/9] ManageabilityPkg: Initial package

From: Abner Chang 

Initial commit of ManageabilityPkg

Signed-off-by: Abner Chang 
Cc: Liming Gao 
Cc: Isaac Oram 
Cc: Nate DeSimone 
Cc: Abdul Lateef Attar 
Cc: Nickle Wang 
Cc: Igor Kulchytskyy 
Reviewed-by: Abdul Lateef Attar 
Reviewed-by: Nickle Wang 
---
 .../ManageabilityPkg/ManageabilityPkg.dec | 21 ++
 .../Include/Dsc/Manageability.dsc | 16 
 .../ManageabilityPkg/ManageabilityPkg.dsc | 39 +++
 3 files changed, 76 insertions(+)
 create mode 100644 Features/ManageabilityPkg/ManageabilityPkg.dec
 create mode 100644 Features/ManageabilityPkg/Include/Dsc/Manageability.dsc
 create mode 100644 Features/ManageabilityPkg/ManageabilityPkg.dsc

diff --git a/Features/ManageabilityPkg/ManageabilityPkg.dec 
b/Features/ManageabilityPkg/ManageabilityPkg.dec
new file mode 100644
index 00..71bd8a0c80
--- /dev/null
+++ b/Features/ManageabilityPkg/ManageabilityPkg.dec
@@ -0,0 +1,21 @@
+## @file
+# Manageabilty Package
+# This is the package provides the edk2 drivers and libraries # those 
+are related to the platform management.
+#
+# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights 
+reserved. # SPDX-License-Identifier: BSD-2-Clause-Patent # ##
+
+[Defines]
+  DEC_SPECIFICATION = 0x0001001d
+  PACKAGE_NAME  = ManageabilityPkg
+  PACKAGE_GUID  = 36310119-4FB2-4BA3-959D-74C16B849F9E
+  PACKAGE_VERSION   = 1.0
+
+[Includes]
+  Include
+
+[Guids]
+  gManageabilityPkgTokenSpaceGuid = { 0xBDEFFF48, 0x1C31, 0x49CD, { 
+0xA7, 0x6D, 0x92, 0x9E, 0x60, 0xDB, 0xB9, 0xF8 } }
diff --git a/Features/ManageabilityPkg/Include/Dsc/Manageability.dsc 
b/Features/ManageabilityPkg/Include/Dsc/Manageability.dsc
new file mode 100644
index 00..2cb63c1ca6
--- /dev/null
+++ b/Features/ManageabilityPkg/Include/Dsc/Manageability.dsc
@@ -0,0 +1,16 @@
+## @file
+# Common libraries for Manageabilty Package # # Copyright (C) 2023 
+Advanced Micro Devices, Inc. All rights reserved. # 
+SPDX-License-Identifier: BSD-2-Clause-Patent # ##
+
+[LibraryClasses.ARM, LibraryClasses.AARCH64]
+  #
+  # This library provides the instrinsic functions generated by a given 
compiler.
+  #
+  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+  NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+  ArmSoftFloatLib|ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.inf
+
diff --git a/Features/ManageabilityPkg/ManageabilityPkg.dsc 
b/Features/ManageabilityPkg/ManageabilityPkg.dsc
new file mode 100644
index 00..b3586afa07
--- /dev/null
+++ b/Features/ManageabilityPkg/ManageabilityPkg.dsc
@@ -0,0 +1,39 @@
+## @file
+# Manageabilty Package
+# This is the package provides edk2 drivers and libraries # those are 
+related to the platform management.
+#
+# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights 
+reserved. # SPDX-License-Identifier: BSD-2-Clause-Patent # ##
+
+[Defines]
+  PLATFORM_NAME  = ManageabilityPkg
+  PLATFORM_GUID  = 7A98123A-B194-40B6-A863-A52192F6D65D
+  PLATFORM_VERSION   = 1.0
+  DSC_SPECIFICATION  = 0x0001001e
+  OUTPUT_DIRECTORY   = Build/ManageabilityPkg
+  SUPPORTED_ARCHITECTURES= IA32|X64|ARM|AARCH64|RISCV64
+  BUILD_TARGETS  = DEBUG|RELEASE|NOOPT
+  SKUID_IDENTIFIER   = DEFAULT
+
+[Packages]
+  MinPlatformPkg/MinPlatformPkg.dec
+
+[PcdsFeatureFlag]
+  #
+  # MinPlatform common include currently required PCD
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable   
|FALSE
+  gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable  
|FALSE
+
+#
+# Include common libraries
+#
+!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc
+!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc
+!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc
+
+!include Include/Dsc/Manageability.dsc
+
--
2.37.1.windows.1








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Re: [edk2-devel] [PATCH v3] MdePkg/Include: Add IPMI KCS definitions

[Tinh Nguyen via groups.io]

Hi Abner,

On 3/23/2023 8:57 PM, Chang, Abner via groups.io wrote:

From: Abner Chang 

BZ #4354
This change adds definitions for IPMI KCS.

Spec ref:
https://www.intel.com/content/www/us/en/products/docs/servers/ipmi/ipmi-second-gen-interface-spec-v2-rev1-1.html

Signed-off-by: Abner Chang 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Nickle Wang 
Cc: Igor Kulchytskyy 
Cc: Isaac Oram 
Cc: Abdul Lateef Attar 
Acked-by: Isaac Oram 
---
  MdePkg/MdePkg.dec |  6 ++
  MdePkg/Include/IndustryStandard/IpmiKcs.h | 76 +++
  2 files changed, 82 insertions(+)
  create mode 100644 MdePkg/Include/IndustryStandard/IpmiKcs.h

diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index 2d643bede1d..5cf04bc0cb6 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -9,6 +9,7 @@
  # (C) Copyright 2016 - 2021 Hewlett Packard Enterprise Development LP
  # Copyright (c) 2022, Loongson Technology Corporation Limited. All rights 
reserved.
  # Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
  #
  # SPDX-License-Identifier: BSD-2-Clause-Patent
  #
@@ -2342,6 +2343,11 @@
# @Prompt Memory Address of GuidedExtractHandler Table.

gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|0x100|UINT64|0x30001015
  
+  ## This value is the IPMI KCS Interface I/O base address used to transmit IPMI commands.

+  #  The value of 0xca2 is the default I/O base address defined in IPMI 
specification.
+  # @Prompt IPMI KCS Interface I/O Base Address
+  gEfiMdePkgTokenSpaceGuid.PcdIpmiKcsIoBaseAddress|0xca2|UINT16|0x0031
+
  [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
## This value is used to set the base address of PCI express hierarchy.
# @Prompt PCI Express Base Address.
diff --git a/MdePkg/Include/IndustryStandard/IpmiKcs.h 
b/MdePkg/Include/IndustryStandard/IpmiKcs.h
new file mode 100644
index 000..c3baf80bd76
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/IpmiKcs.h
@@ -0,0 +1,76 @@
+/** @file
+  IPMI KCS Register Definitions
+
+  Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  IPMI Specification
+  Version 2.0, Rev. 1.1
+  
https://www.intel.com/content/www/us/en/products/docs/servers/ipmi/ipmi-second-gen-interface-spec-v2-rev1-1.html
+**/
+
+#ifndef IPMI_KCS_H_
+#define IPMI_KCS_H_
+
+#define IPMI_KCS_STATUS_REGISTER_OFFSET1
+#define IPMI_KCS_COMMAND_REGISTER_OFFSET   1
+#define IPMI_KCS_DATA_OUT_REGISTER_OFFSET  0
+#define IPMI_KCS_DATA_IN_REGISTER_OFFSET   0
+
+///
+/// IPMI KCS Interface Status Bits
+///
+#define IPMI_KCS_OBF   BIT0
+#define IPMI_KCS_IBF   BIT1
+#define IPMI_KCS_SMS_ATN   BIT2
+#define IPMI_KCS_COMMAND_DATA  BIT3
+#define IPMI_KCS_OEM1  BIT4
+#define IPMI_KCS_OEM2  BIT5
+#define IPMI_KCS_S0BIT6
+#define IPMI_KCS_S1BIT7
+
+///
+/// IPMI KCS Interface Control Codes
+///
+#define IPMI_KCS_CONTROL_CODE_GET_STATUS_ABORT  0x60
+#define IPMI_KCS_CONTROL_CODE_WRITE_START   0x61
+#define IPMI_KCS_CONTROL_CODE_WRITE_END 0x62
+#define IPMI_KCS_CONTROL_CODE_READ  0x68
+
+///
+/// Status Codes
+///
+#define IPMI_KCS_STATUS_NO_ERROR  0x00
+#define IPMI_KCS_STATUS_ABORT 0x01
+#define IPMI_KCS_STATUS_ILLEGAL   0x02
+#define IPMI_KCS_STATUS_LENGTH_ERROR  0x06
+#define IPMI_KCS_STATUS_UNSPECIFIED   0xFF
+
+///
+/// KCS Interface State Bit
+///
+typedef enum {
+  IPMI_KCS_IDLE_STATE = 0,
+  IPMI_KCS_READ_STATE,
+  IPMI_KCS_WRITE_STATE,
+  IPMI_KCS_ERROR_STATE
+} IPMI_KCS_STATE;
+
+///
+/// IPMI KCS Interface Request Format
+///
+typedef struct {
+  UINT8NetFunc;
That definition is fine, but I'm curious why you don't use bit field to 
separate NetFun and Lun

+  UINT8Command;
+  UINT8Data[0];
+} IPMI_KCS_RESQUEST_HEADER;

It should be REQUEST?

+
+///
+/// IPMI KCS Interface Response Format
+///
+typedef struct {
+  UINT8NetFunc;
+  UINT8Command;
+} IPMI_KCS_RESPONSE_HEADER;
+#endif



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Re: [edk2-devel] [PATCH v4 9/9] edk2-platforms: Maintainers.txt

[Isaac Oram]

Reviewed-by: Isaac Oram 

-Original Message-
From: Leif Lindholm  
Sent: Thursday, March 23, 2023 7:46 AM
To: abner.ch...@amd.com
Cc: devel@edk2.groups.io; Abdul Lateef Attar ; Kinney, 
Michael D ; Gao, Liming ; 
Oram, Isaac W ; Nickle Wang 
Subject: Re: [PATCH v4 9/9] edk2-platforms: Maintainers.txt

On Wed, Mar 22, 2023 at 10:48:40 +0800, abner.ch...@amd.com wrote:
> From: Abner Chang 
> 
> Add maintainer and reviewer of ManageabilityPkg.
> 
> Signed-off-by: Abner Chang 
> Cc: Abdul Lateef Attar 
> Cc: Leif Lindholm 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Isaac Oram 
> Cc: Nickle Wang 
> Reviewed-by: Michael D Kinney 
> Reviewed-by: Nickle Wang 
> ---
>  Maintainers.txt | 7 +++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/Maintainers.txt b/Maintainers.txt index 
> 7471913660..1871ffaa26 100644
> --- a/Maintainers.txt
> +++ b/Maintainers.txt
> @@ -164,6 +164,13 @@ F: Features/Intel/UserInterface/
>  M: Dandan Bi 
>  R: Liming Gao 
>  
> +Features/ManageabilityPkg
> +F: Features/ManageabilityPkg/
> +M: Abner Chang 
> +M: Isaac Oram 
> +R: Abdul Lateef Attar 
> +R: Nickle Wang 

Need R-b from Isaac and Abdul.
With that:
Reviewed-by: Leif Lindholm 

> +
>  Platform/Intel
>  F: Platform/Intel/
>  M: Sai Chaganty 
> --
> 2.37.1.windows.1
> 


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Re: [edk2-devel] [PATCH v3] MdePkg/Include: Add IPMI KCS definitions

[Isaac Oram]

Acked-by: Isaac Oram 

-Original Message-
From: abner.ch...@amd.com  
Sent: Thursday, March 23, 2023 6:58 AM
To: devel@edk2.groups.io
Cc: Kinney, Michael D ; Gao, Liming 
; Liu, Zhiguang ; Nickle Wang 
; Igor Kulchytskyy ; Oram, Isaac W 
; Abdul Lateef Attar 
Subject: [PATCH v3] MdePkg/Include: Add IPMI KCS definitions

From: Abner Chang 

BZ #4354
This change adds definitions for IPMI KCS.

Spec ref:
https://www.intel.com/content/www/us/en/products/docs/servers/ipmi/ipmi-second-gen-interface-spec-v2-rev1-1.html

Signed-off-by: Abner Chang 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Nickle Wang 
Cc: Igor Kulchytskyy 
Cc: Isaac Oram 
Cc: Abdul Lateef Attar 
Acked-by: Isaac Oram 
---
 MdePkg/MdePkg.dec |  6 ++
 MdePkg/Include/IndustryStandard/IpmiKcs.h | 76 +++
 2 files changed, 82 insertions(+)
 create mode 100644 MdePkg/Include/IndustryStandard/IpmiKcs.h

diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 
2d643bede1d..5cf04bc0cb6 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -9,6 +9,7 @@
 # (C) Copyright 2016 - 2021 Hewlett Packard Enterprise Development LP  # 
Copyright (c) 2022, Loongson Technology Corporation Limited. All rights 
reserved.  # Copyright (c) 2021 - 2022, Arm Limited. All rights 
reserved.
+# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights 
+reserved.
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent  # @@ -2342,6 +2343,11 @@
   # @Prompt Memory Address of GuidedExtractHandler Table.
   
gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|0x100|UINT64|0x30001015
 
+  ## This value is the IPMI KCS Interface I/O base address used to transmit 
IPMI commands.
+  #  The value of 0xca2 is the default I/O base address defined in IPMI 
specification.
+  # @Prompt IPMI KCS Interface I/O Base Address
+  
+ gEfiMdePkgTokenSpaceGuid.PcdIpmiKcsIoBaseAddress|0xca2|UINT16|0x00
+ 31
+
 [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
   ## This value is used to set the base address of PCI express hierarchy.
   # @Prompt PCI Express Base Address.
diff --git a/MdePkg/Include/IndustryStandard/IpmiKcs.h 
b/MdePkg/Include/IndustryStandard/IpmiKcs.h
new file mode 100644
index 000..c3baf80bd76
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/IpmiKcs.h
@@ -0,0 +1,76 @@
+/** @file
+  IPMI KCS Register Definitions
+
+  Copyright (C) 2023 Advanced Micro Devices, Inc. All rights 
+ reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  IPMI Specification
+  Version 2.0, Rev. 1.1
+  
+https://www.intel.com/content/www/us/en/products/docs/servers/ipmi/ipmi
+-second-gen-interface-spec-v2-rev1-1.html
+**/
+
+#ifndef IPMI_KCS_H_
+#define IPMI_KCS_H_
+
+#define IPMI_KCS_STATUS_REGISTER_OFFSET1
+#define IPMI_KCS_COMMAND_REGISTER_OFFSET   1
+#define IPMI_KCS_DATA_OUT_REGISTER_OFFSET  0
+#define IPMI_KCS_DATA_IN_REGISTER_OFFSET   0
+
+///
+/// IPMI KCS Interface Status Bits
+///
+#define IPMI_KCS_OBF   BIT0
+#define IPMI_KCS_IBF   BIT1
+#define IPMI_KCS_SMS_ATN   BIT2
+#define IPMI_KCS_COMMAND_DATA  BIT3
+#define IPMI_KCS_OEM1  BIT4
+#define IPMI_KCS_OEM2  BIT5
+#define IPMI_KCS_S0BIT6
+#define IPMI_KCS_S1BIT7
+
+///
+/// IPMI KCS Interface Control Codes
+///
+#define IPMI_KCS_CONTROL_CODE_GET_STATUS_ABORT  0x60
+#define IPMI_KCS_CONTROL_CODE_WRITE_START   0x61
+#define IPMI_KCS_CONTROL_CODE_WRITE_END 0x62
+#define IPMI_KCS_CONTROL_CODE_READ  0x68
+
+///
+/// Status Codes
+///
+#define IPMI_KCS_STATUS_NO_ERROR  0x00
+#define IPMI_KCS_STATUS_ABORT 0x01
+#define IPMI_KCS_STATUS_ILLEGAL   0x02
+#define IPMI_KCS_STATUS_LENGTH_ERROR  0x06
+#define IPMI_KCS_STATUS_UNSPECIFIED   0xFF
+
+///
+/// KCS Interface State Bit
+///
+typedef enum {
+  IPMI_KCS_IDLE_STATE = 0,
+  IPMI_KCS_READ_STATE,
+  IPMI_KCS_WRITE_STATE,
+  IPMI_KCS_ERROR_STATE
+} IPMI_KCS_STATE;
+
+///
+/// IPMI KCS Interface Request Format
+///
+typedef struct {
+  UINT8NetFunc;
+  UINT8Command;
+  UINT8Data[0];
+} IPMI_KCS_RESQUEST_HEADER;
+
+///
+/// IPMI KCS Interface Response Format
+///
+typedef struct {
+  UINT8NetFunc;
+  UINT8Command;
+} IPMI_KCS_RESPONSE_HEADER;
+#endif
--
2.37.1.windows.1



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Re: [edk2-devel] [PATCH 2/3] BaseTools: Replace duplicate __PcdSet prototype with __PcdGet

[Rebecca Cran]

Hi Liming,


Could you review this patch please?

I've dropped the 3rd patch which was running Uncrustify over the code, 
so this is the only one left before I can merge the series.



Thanks.

Rebecca Cran


On 2/24/23 5:54 PM, Rebecca Cran wrote:

Replace the duplicate __PcdSet prototype in PcdValueCommon.h
with the prototype for __PcdGet.

Signed-off-by: Rebecca Cran 
---
  BaseTools/Source/C/Common/PcdValueCommon.h | 13 ++---
  1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/BaseTools/Source/C/Common/PcdValueCommon.h 
b/BaseTools/Source/C/Common/PcdValueCommon.h
index 02ef803be479..7dac5bd92dbc 100644
--- a/BaseTools/Source/C/Common/PcdValueCommon.h
+++ b/BaseTools/Source/C/Common/PcdValueCommon.h
@@ -78,13 +78,12 @@ __PcdSet (
  
@return PCD value

  **/
-VOID
-__PcdSet (
-  CHAR8   *SkuName OPTIONAL,
-  CHAR8   *DefaultValueNameOPTIONAL,
-  CHAR8   *TokenSpaceGuidName,
-  CHAR8   *TokenName,
-  UINT64  Value
+UINT64
+__PcdGet (
+  CHAR8  *SkuName OPTIONAL,
+  CHAR8  *DefaultValueNameOPTIONAL,
+  CHAR8  *TokenSpaceGuidName,
+  CHAR8  *TokenName
)
  ;
  



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Re: [edk2-devel] [PATCH 0/1] MdeModulePkg/Ahci: Skip retry for non-transient errors

[Anbazhagan, Baraneedharan via groups.io]

Hi,
This patch seems to resolve the issue reported in 4011 - MdeModulePkg: Need 
configurable AHCI command retries 
(tianocore.org) and 
verified with 'AHCI_COMMAND_RETRIES' as 5. Able to unlock the drive with 
correct password on 2nd attempt after providing an incorrect password.

Thanks,
Baranee

From: devel@edk2.groups.io  On Behalf Of Wu, Hao A via 
groups.io
Sent: Wednesday, March 22, 2023 1:59 AM
To: Albecki, Mateusz ; Anbazhagan, Baraneedharan 
; devel@edk2.groups.io
Cc: Ni, Ray ; Chang, Hunter 
Subject: Re: [edk2-devel] [PATCH 0/1] MdeModulePkg/Ahci: Skip retry for 
non-transient errors

CAUTION: External Email
Thanks Mateusz, the patch looks good to me.
I noticed that there are some check failures in 
https://github.com/tianocore/edk2/pull/4157,
 could you help to address them?


Hello Baraneedharan Anbazhagan,
Could you help to check if this patch can resolve the issue 
https://bugzilla.tianocore.org/show_bug.cgi?id=4011
 when switching back to: "#define AHCI_COMMAND_RETRIES 5"?
This change can be accessed for integration at: 
https://patch-diff.githubusercontent.com/raw/tianocore/edk2/pull/4157.patch
Thanks in advance.

Best Regards,
Hao Wu

> -Original Message-
> From: Albecki, Mateusz 
> mailto:mateusz.albe...@intel.com>>
> Sent: Wednesday, March 22, 2023 4:20 AM
> To: devel@edk2.groups.io
> Cc: Albecki, Mateusz 
> mailto:mateusz.albe...@intel.com>>; Wu, Hao A
> mailto:hao.a...@intel.com>>; Ni, Ray 
> mailto:ray...@intel.com>>; Chang, Hunter
> mailto:hunter.ch...@intel.com>>
> Subject: [PATCH 0/1] MdeModulePkg/Ahci: Skip retry for non-transient errors
>
> Fix for the recovery logic which causes hdd unlock to fail if user supplies
> incorrect password. Every failed packet used to be recovered which is causing
> the incorrect password to be tried multiple times. This patch series fixes the
> logic to only retry commands that failed due to CRC error.
>
> BZ: 
> https://bugzilla.tianocore.org/show_bug.cgi?id=4011
>
> Github pull: 
> https://github.com/tianocore/edk2/pull/4157
>
> Tests:
> - tested basic linux boot from AHCI on qemu
> - tested basic linux boot from AHCI on custom qemu which will fail 50% of the
> DMA commands with CRC error.
> Observed that all of the packets that failed were successfully retried. Custom
> Qemu: 
> https://github.com/matalbec/qemu/tree/sata_dma_50p_fail
> - additionally Hunter Chang tested and confirmed that the password issue is no
> longer observed.
>
> Cc: Hao A Wu mailto:hao.a...@intel.com>>
> Cc: Ray Ni mailto:ray...@intel.com>>
> Cc: Hunter Chang mailto:hunter.ch...@intel.com>>
>
> Mateusz Albecki (1):
> MdeModulePkg/Ahci: Skip retry for non-transient errors
>
> .../Bus/Ata/AtaAtapiPassThru/AhciMode.c | 69 +--
> .../Bus/Ata/AtaAtapiPassThru/AhciMode.h | 3 +-
> 2 files changed, 67 insertions(+), 5 deletions(-)
>
> --
> 2.39.1.windows.1






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Re: [edk2-devel] [PATCH 0/1] MdeModulePkg/Ahci: Skip retry for non-transient errors

[Albecki, Mateusz]

Seems like a code formatting issue. I will address it tomorrow.

Regards,
Mateusz


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Re: [edk2-devel] [edk2-staging/OpenSSL11_EOL][PATCH 0/4] Openssl 3.0 POC update Mar 22

[Michael D Kinney]

Hi Jiewen,

What is your assessment of the progress on Openssl 3.0 from a size perspective.

What is the goal and how close are we now?

Thanks,

Mike

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Li, Yi
> Sent: Wednesday, March 22, 2023 7:45 PM
> To: devel@edk2.groups.io
> Cc: Li, Yi1 ; Yao, Jiewen ; Hou, 
> Wenxing ; Gerd Hoffmann
> 
> Subject: [edk2-devel] [edk2-staging/OpenSSL11_EOL][PATCH 0/4] Openssl 3.0 POC 
> update Mar 22
> 
> Please check the patch series if interested.
> PR: https://github.com/tianocore/edk2-staging/pull/363
> 
> Latest size data:
> Binaries:
>   CryptoDxeFull   1.70%   ->  -1.6%   -17KB
>   CryptoDxe   10.1%   ->  8.3%68KB
>   CryptoSmm   8.20%   ->  4.1%23KB
> After LZMA:
>   CryptoDxe   12.2%   ->  11.20%  35KB
>   CryptoSmm   12.8%   ->  10.40%  22KB
>   FV (Dxe+Smm)15.4%   ->  13.70%  49KB
> 
> Cc: Jiewen Yao 
> Cc: Wenxing Hou 
> Cc: Gerd Hoffmann 
> Signed-off-by: Yi Li 
> 
> Yi Li (4):
>   bugfix: use null md5 onlyif no-md5 defined
>   CryptoPkg: remove unnecessary sig, ec and rsa prov
>   CryptoPkg: update openssl submodule
>   Readme: 0322 update
> 
>  CryptoPkg/Library/OpensslLib/HashNull.c   |  3 +
>  .../Library/OpensslLib/OpensslStub/uefiprov.c | 23 ---
>  CryptoPkg/Library/OpensslLib/openssl  |  2 +-
>  CryptoPkg/Readme-OpenSSL3.0.md| 65 ---
>  4 files changed, 61 insertions(+), 32 deletions(-)
> 
> --
> 2.31.1.windows.1
> 
> 
> 
> 
> 



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[edk2-devel] [PATCH v3] MdePkg/Include: Add DMTF MCTP definitions

[Chang, Abner via groups.io]

From: Abner Chang 

BZ #4355
This change adds definitions for DMTF MCTP
base specification.

Spec ref:
https://www.dmtf.org/sites/default/files/standards/documents/DSP0236_1.3.1.pdf

Signed-off-by: Abner Chang 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Nickle Wang 
Cc: Igor Kulchytskyy 
Cc: Isaac Oram 
Cc: Abdul Lateef Attar 
Acked-by: Isaac Oram 
---
 MdePkg/Include/IndustryStandard/Mctp.h | 138 +
 1 file changed, 138 insertions(+)
 create mode 100644 MdePkg/Include/IndustryStandard/Mctp.h

diff --git a/MdePkg/Include/IndustryStandard/Mctp.h 
b/MdePkg/Include/IndustryStandard/Mctp.h
new file mode 100644
index 000..bfbc843c7f1
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/Mctp.h
@@ -0,0 +1,138 @@
+/** @file
+
+  The definitions of DMTF Management Component Transport Protocol (MCTP)
+  Base Specification.
+
+  Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  DMTF Management Component Transport Protocol (MCTP) Base Specification
+  Version 1.3.1
+  
https://www.dmtf.org/sites/default/files/standards/documents/DSP0236_1.3.1.pdf
+**/
+
+#ifndef MCTP_H_
+#define MCTP_H_
+
+///
+/// Definitions of endpoint ID
+///
+#define MCTP_NULL_DESTINATION_ENDPOINT_ID  0
+#define MCTP_NULL_SOURCE_ENDPOINT_ID   0
+#define MCTP_RESERVED_ENDPOINT_START_ID1
+#define MCTP_RESERVED_ENDPOINT_END_ID  7
+#define MCTP_BROADCAST_ENDPOINT_ID 0xFF
+
+/// Minimum transmission size is 64 bytes.
+/// The value of 64 is defined in MCTP Base Specification.
+#define MCTP_BASELINE_MINIMUM_UNIT_TRANSMISSION_SIZE  0x40
+
+///
+/// The 32-bit Header of MCTP packet.
+///
+typedef union {
+  struct {
+UINT8HeaderVersion : 4; ///< The version of header.
+UINT8Reserved  : 4; ///< Reserved for future definitions.
+UINT8DestinationEndpointId : 8; ///< Destination endpoint Id (EID).
+UINT8SourceEndpointIdId: 8; ///< Source endpoint Id (EID)
+UINT8MessageTag: 3; ///< Check the MCTP Base specification 
for the
+///< usages.
+UINT8TagOwner  : 1; ///< Tag owner identifies the message 
was
+///< originated by the source EID or
+///< destination EID.
+UINT8PacketSequence: 2; ///< Sequence number increments Modulo 
4 on
+///< each packet.
+UINT8EndOfMessage  : 1; ///< Indicates the last packet of 
message.
+UINT8StartOfMessage: 1; ///< Indicates the first packet of 
message.
+  } Bits;
+  UINT32Header;
+} MCTP_TRANSPORT_HEADER;
+
+///
+/// The 8-bit Message Header of MCTP packet.
+///
+typedef union {
+  struct {
+UINT8MessageType   : 7;
+UINT8ItegrityCheck : 1;
+  } Bits;
+  UINT8MessageHeader;
+} MCTP_MESSAGE_HEADER;
+
+///
+/// MCTP Control Commands
+///
+#define   MCTP_CONTROL_RESERVED0x00
+#define   MCTP_CONTROL_SET_ENDPOINT_ID 0x01
+#define   MCTP_CONTROL_GET_ENDPOINT_ID 0x02
+#define   MCTP_CONTROL_GET_ENDPOINT_UUID   0x03
+#define   MCTP_CONTROL_GET_MCTP_VERSION_SUPPORT0x04
+#define   MCTP_CONTROL_GET_MESSAGE_TYPE_SUPPORT0x05
+#define   MCTP_CONTROL_GET_VENDOR_DEFINED_MESSAGE_SUPPORT  0x06
+#define   MCTP_CONTROL_RESOLVE_ENDPOINT_ID 0x07
+#define   MCTP_CONTROL_ALLOCATE_ENDPOINT_IDS   0x08
+#define   MCTP_CONTROL_ROUTING_INFORMATION_UPDATE  0x09
+#define   MCTP_CONTROL_GET_ROUTINE_TABLE_ENTRIES   0x0A
+#define   MCTP_CONTROL_PREPARE_FOR_ENDPOINT_DISCOVERY  0x0B
+#define   MCTP_CONTROL_ENDPOINT_DISCOVERY  0x0C
+#define   MCTP_CONTROL_DISCOVERY_NOTIFY0x0D
+#define   MCTP_CONTROL_GET_NETWORK_ID  0x0E
+#define   MCTP_CONTROL_QUERY_HOP   0x0F
+#define   MCTP_CONTROL_RESOLVE_UUID0x10
+#define   MCTP_CONTROL_QUERY_RATE_LIMIT0x11
+#define   MCTP_CONTROL_REQUEST_TX_RATE_LIMIT   0x12
+#define   MCTP_CONTROL_UPDATE_RATE_LIMIT   0x13
+#define   MCTP_CONTROL_QUERY_SUPPORTED_INTERFACES  0x14
+#define   MCTP_CONTROL_TRANSPORT_SPECIFIC_START0xF0
+#define   MCTP_CONTROL_TRANSPORT_SPECIFIC_END  0xFF
+
+///
+/// MCTP Control Message Completion Codes
+///
+#define   MCTP_CONTROL_COMPLETION_CODES_SUCCESS 0x00
+#define   MCTP_CONTROL_COMPLETION_CODES_ERROR   0x01
+#define   MCTP_CONTROL_COMPLETION_CODES_ERROR_INVALID_DATA  0x02
+#define   MCTP_CONTROL_COMPLETION_CODES_ERROR_INVALID_LENGTH0x03
+#define   MCTP_CONTROL_COMPLETION_CODES_ERROR_NOT_READY 0x04
+#define   

Re: [edk2-devel] [PATCH 1/3] BaseTools/Conf/tools_def: Fix linking using CLANGDWARF_IA32

[Sheng Lean Tan]

Added the right reviewers @Gao, Liming   @Feng,
Bob C  @yuwei.c...@intel.com 


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Re: [edk2-devel] [PATCH v4 9/9] edk2-platforms: Maintainers.txt

[Leif Lindholm]

On Wed, Mar 22, 2023 at 10:48:40 +0800, abner.ch...@amd.com wrote:
> From: Abner Chang 
> 
> Add maintainer and reviewer of ManageabilityPkg.
> 
> Signed-off-by: Abner Chang 
> Cc: Abdul Lateef Attar 
> Cc: Leif Lindholm 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Isaac Oram 
> Cc: Nickle Wang 
> Reviewed-by: Michael D Kinney 
> Reviewed-by: Nickle Wang 
> ---
>  Maintainers.txt | 7 +++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/Maintainers.txt b/Maintainers.txt
> index 7471913660..1871ffaa26 100644
> --- a/Maintainers.txt
> +++ b/Maintainers.txt
> @@ -164,6 +164,13 @@ F: Features/Intel/UserInterface/
>  M: Dandan Bi 
>  R: Liming Gao 
>  
> +Features/ManageabilityPkg
> +F: Features/ManageabilityPkg/
> +M: Abner Chang 
> +M: Isaac Oram 
> +R: Abdul Lateef Attar 
> +R: Nickle Wang 

Need R-b from Isaac and Abdul.
With that:
Reviewed-by: Leif Lindholm 

> +
>  Platform/Intel
>  F: Platform/Intel/
>  M: Sai Chaganty 
> -- 
> 2.37.1.windows.1
> 


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Re: [edk2-devel] [PATCH 1/3] BaseTools/Conf/tools_def: Fix linking using CLANGDWARF_IA32

[Rebecca Cran]

The linker problems I was seeing were unrelated to those Patrick's patch 
fixed.


I just applied Patrick's changes on top of my CLANGDWARF patches and 
OvmfPkgIa32.dsc builds fine.



--

Rebecca Cran


On 3/17/23 2:35 PM, Rebecca Cran wrote:
Building with "build -p OvmfPkg/OvmfPkgX64.dsc -a X64 -t CLANGDWARF -b 
RELEASE" on FreeBSD causes the following errors:



ld.lld: error: relocation R_X86_64_64 cannot be used against local 
symbol; recompile with -fPIC
>>> defined in 
/home/bcran/src/uefi/edk2/Build/OvmfX64/RELEASE_CLANGDWARF/X64/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib/OUTPUT/SecPeiCpuExceptionHandlerLib.lib(ExceptionHandlerAsm.obj)
>>> referenced by 
/home/bcran/src/uefi/edk2/Build/OvmfX64/RELEASE_CLANGDWARF/X64/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib/OUTPUT/X64/ExceptionHandlerAsm.iii
>>>   ExceptionHandlerAsm.obj:(.text+0x5) in archive 
/home/bcran/src/uefi/edk2/Build/OvmfX64/RELEASE_CLANGDWARF/X64/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib/OUTPUT/SecPeiCpuExceptionHandlerLib.lib


ld.lld: error: relocation R_X86_64_64 cannot be used against local 
symbol; recompile with -fPIC
>>> defined in 
/home/bcran/src/uefi/edk2/Build/OvmfX64/RELEASE_CLANGDWARF/X64/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib/OUTPUT/SecPeiCpuExceptionHandlerLib.lib(ExceptionHandlerAsm.obj)
>>> referenced by 
/home/bcran/src/uefi/edk2/Build/OvmfX64/RELEASE_CLANGDWARF/X64/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib/OUTPUT/X64/ExceptionHandlerAsm.iii
>>>   ExceptionHandlerAsm.obj:(.text+0x14) in archive 
/home/bcran/src/uefi/edk2/Build/OvmfX64/RELEASE_CLANGDWARF/X64/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib/OUTPUT/SecPeiCpuExceptionHandlerLib.lib


ld.lld: error: relocation R_X86_64_64 cannot be used against local 
symbol; recompile with -fPIC
>>> defined in 
/home/bcran/src/uefi/edk2/Build/OvmfX64/RELEASE_CLANGDWARF/X64/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib/OUTPUT/SecPeiCpuExceptionHandlerLib.lib(ExceptionHandlerAsm.obj)
>>> referenced by 
/home/bcran/src/uefi/edk2/Build/OvmfX64/RELEASE_CLANGDWARF/X64/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib/OUTPUT/X64/ExceptionHandlerAsm.iii
>>>   ExceptionHandlerAsm.obj:(.text+0x23) in archive 
/home/bcran/src/uefi/edk2/Build/OvmfX64/RELEASE_CLANGDWARF/X64/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib/OUTPUT/SecPeiCpuExceptionHandlerLib.lib



Thinking about it, it might actually be a problem with the FreeBSD 
system toolchain. On Linux, I get a different set of errors about 
redefining uint64_t etc.






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[edk2-devel] [PATCH v3] MdePkg/Include: Add IPMI KCS definitions

[Chang, Abner via groups.io]

From: Abner Chang 

BZ #4354
This change adds definitions for IPMI KCS.

Spec ref:
https://www.intel.com/content/www/us/en/products/docs/servers/ipmi/ipmi-second-gen-interface-spec-v2-rev1-1.html

Signed-off-by: Abner Chang 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Nickle Wang 
Cc: Igor Kulchytskyy 
Cc: Isaac Oram 
Cc: Abdul Lateef Attar 
Acked-by: Isaac Oram 
---
 MdePkg/MdePkg.dec |  6 ++
 MdePkg/Include/IndustryStandard/IpmiKcs.h | 76 +++
 2 files changed, 82 insertions(+)
 create mode 100644 MdePkg/Include/IndustryStandard/IpmiKcs.h

diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index 2d643bede1d..5cf04bc0cb6 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -9,6 +9,7 @@
 # (C) Copyright 2016 - 2021 Hewlett Packard Enterprise Development LP
 # Copyright (c) 2022, Loongson Technology Corporation Limited. All rights 
reserved.
 # Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -2342,6 +2343,11 @@
   # @Prompt Memory Address of GuidedExtractHandler Table.
   
gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|0x100|UINT64|0x30001015
 
+  ## This value is the IPMI KCS Interface I/O base address used to transmit 
IPMI commands.
+  #  The value of 0xca2 is the default I/O base address defined in IPMI 
specification.
+  # @Prompt IPMI KCS Interface I/O Base Address
+  gEfiMdePkgTokenSpaceGuid.PcdIpmiKcsIoBaseAddress|0xca2|UINT16|0x0031
+
 [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
   ## This value is used to set the base address of PCI express hierarchy.
   # @Prompt PCI Express Base Address.
diff --git a/MdePkg/Include/IndustryStandard/IpmiKcs.h 
b/MdePkg/Include/IndustryStandard/IpmiKcs.h
new file mode 100644
index 000..c3baf80bd76
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/IpmiKcs.h
@@ -0,0 +1,76 @@
+/** @file
+  IPMI KCS Register Definitions
+
+  Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  IPMI Specification
+  Version 2.0, Rev. 1.1
+  
https://www.intel.com/content/www/us/en/products/docs/servers/ipmi/ipmi-second-gen-interface-spec-v2-rev1-1.html
+**/
+
+#ifndef IPMI_KCS_H_
+#define IPMI_KCS_H_
+
+#define IPMI_KCS_STATUS_REGISTER_OFFSET1
+#define IPMI_KCS_COMMAND_REGISTER_OFFSET   1
+#define IPMI_KCS_DATA_OUT_REGISTER_OFFSET  0
+#define IPMI_KCS_DATA_IN_REGISTER_OFFSET   0
+
+///
+/// IPMI KCS Interface Status Bits
+///
+#define IPMI_KCS_OBF   BIT0
+#define IPMI_KCS_IBF   BIT1
+#define IPMI_KCS_SMS_ATN   BIT2
+#define IPMI_KCS_COMMAND_DATA  BIT3
+#define IPMI_KCS_OEM1  BIT4
+#define IPMI_KCS_OEM2  BIT5
+#define IPMI_KCS_S0BIT6
+#define IPMI_KCS_S1BIT7
+
+///
+/// IPMI KCS Interface Control Codes
+///
+#define IPMI_KCS_CONTROL_CODE_GET_STATUS_ABORT  0x60
+#define IPMI_KCS_CONTROL_CODE_WRITE_START   0x61
+#define IPMI_KCS_CONTROL_CODE_WRITE_END 0x62
+#define IPMI_KCS_CONTROL_CODE_READ  0x68
+
+///
+/// Status Codes
+///
+#define IPMI_KCS_STATUS_NO_ERROR  0x00
+#define IPMI_KCS_STATUS_ABORT 0x01
+#define IPMI_KCS_STATUS_ILLEGAL   0x02
+#define IPMI_KCS_STATUS_LENGTH_ERROR  0x06
+#define IPMI_KCS_STATUS_UNSPECIFIED   0xFF
+
+///
+/// KCS Interface State Bit
+///
+typedef enum {
+  IPMI_KCS_IDLE_STATE = 0,
+  IPMI_KCS_READ_STATE,
+  IPMI_KCS_WRITE_STATE,
+  IPMI_KCS_ERROR_STATE
+} IPMI_KCS_STATE;
+
+///
+/// IPMI KCS Interface Request Format
+///
+typedef struct {
+  UINT8NetFunc;
+  UINT8Command;
+  UINT8Data[0];
+} IPMI_KCS_RESQUEST_HEADER;
+
+///
+/// IPMI KCS Interface Response Format
+///
+typedef struct {
+  UINT8NetFunc;
+  UINT8Command;
+} IPMI_KCS_RESPONSE_HEADER;
+#endif
-- 
2.37.1.windows.1



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Re: [edk2-devel] [Patch V4 21/21] UefiCpuPkg/CpuPageTableLib: Reduce the number of random tests

[Ni, Ray]

Reviewed-by: Ray Ni 

> -Original Message-
> From: Tan, Dun 
> Sent: Thursday, March 23, 2023 3:41 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; Kumar,
> Rahul R ; Gerd Hoffmann 
> Subject: [Patch V4 21/21] UefiCpuPkg/CpuPageTableLib: Reduce the number
> of random tests
> 
> Reduce the number of random tests. In previous patch, non-1:1
> mapping is enbaled and it may need more than an hour and a half
> for the CI test, which may lead to CI timeout. Reduce the number
> of random test count to pass the CI.
> 
> Signed-off-by: Dun Tan 
> Cc: Eric Dong 
> Cc: Ray Ni 
> Cc: Rahul Kumar 
> Cc: Gerd Hoffmann 
> ---
> 
> UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo
> st.c | 10 +-
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git
> a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest
> Host.c
> b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest
> Host.c
> index 8554eefa39..c60302eeac 100644
> ---
> a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest
> Host.c
> +++
> b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest
> Host.c
> @@ -9,11 +9,11 @@
>  #include "CpuPageTableLibUnitTest.h"
> 
>  // --- 
> PageMode--
> TestCount-TestRangeCount---RandomOptions
> -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT
> mTestContextPagingPae   = { PagingPae, 100, 20, USE_RANDOM_ARRAY };
> -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT
> mTestContextPaging4Level= { Paging4Level, 100, 20,
> USE_RANDOM_ARRAY };
> -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT
> mTestContextPaging4Level1GB = { Paging4Level1GB, 100, 20,
> USE_RANDOM_ARRAY };
> -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT
> mTestContextPaging5Level= { Paging5Level, 100, 20,
> USE_RANDOM_ARRAY };
> -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT
> mTestContextPaging5Level1GB = { Paging5Level1GB, 100, 20,
> USE_RANDOM_ARRAY };
> +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT
> mTestContextPagingPae   = { PagingPae, 30, 20, USE_RANDOM_ARRAY };
> +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT
> mTestContextPaging4Level= { Paging4Level, 30, 20,
> USE_RANDOM_ARRAY };
> +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT
> mTestContextPaging4Level1GB = { Paging4Level1GB, 30, 20,
> USE_RANDOM_ARRAY };
> +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT
> mTestContextPaging5Level= { Paging5Level, 30, 20,
> USE_RANDOM_ARRAY };
> +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT
> mTestContextPaging5Level1GB = { Paging5Level1GB, 30, 20,
> USE_RANDOM_ARRAY };
> 
>  /**
>Check if the input parameters are not supported.
> --
> 2.31.1.windows.1



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Re: [edk2-devel] [Patch V4 19/21] UefiCpuPkg/CpuPageTableLib: Enable PAE paging

[Ni, Ray]

Overall logics look good to me.
2 minor comments.

> -#define IA32_PE_BASE_ADDRESS_MASK_40  0xFF000ull
> -#define IA32_PE_BASE_ADDRESS_MASK_39  0xFE000ull
> +#define IA32_PE_BASE_ADDRESS_MASK_40 0xFF000ull
> +#define IA32_PE_BASE_ADDRESS_MASK_39 0xFE000ull
> +#define IA32_PE_BASE_ADDRESS_MASK_PAE_PDPTE  0xFFFE0ull

1. This macro is not used.

> 
>  #define REGION_LENGTH(l)  LShiftU64 (1, (l) * 9 + 3)
> 
> +#define MAX_PAE_PDPTE_NUM  4
> +
>  typedef enum {
>Pte   = 1,
>Pde   = 2,
> @@ -60,7 +63,8 @@ typedef union {
>UINT64Uint64;
>  } IA32_PAGE_NON_LEAF_ENTRY;
> 
> -#define IA32_PNLE_PAGE_TABLE_BASE_ADDRESS(pa)  ((pa)->Uint64 &
> IA32_PE_BASE_ADDRESS_MASK_40)
> +#define IA32_PNLE_PAGE_TABLE_BASE_ADDRESS(pa)   ((pa)->Uint64 &
> IA32_PE_BASE_ADDRESS_MASK_40)
> +#define IA32_PAE_PDPTE_PAGE_TABLE_BASE_ADDRESS(pa)  ((pa)->Uint64
> & IA32_PE_BASE_ADDRESS_MASK_PAE_PDPTE)

2. this macro is not used.



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Re: [edk2-devel] [Patch V4 18/21] UefiCpuPkg: Combine branch for non-present and leaf ParentEntry

[Ni, Ray]

> -//
> -// The parent entry is CR3 or PML5E/PML4E/PDPTE/PDE.
> +// When ParentPagingEntry is non-present, parent entry is CR3 or
> PML5E/PML4E/PDPTE/PDE.
>  // It does NOT point to an existing page directory.
> +// When ParentPagingEntry is present, parent entry is leaf PDPTE_1G or
> PDE_2M. Split to 2M or 4K pages.
> +// Note: it's impossible the parent entry is a PTE_4K.
>  //
> -ASSERT (Buffer == NULL || *BufferSize >= SIZE_4KB);
> -CreateNew= TRUE;
> -*BufferSize -= SIZE_4KB;
> +OneOfPagingEntry.Pnle.Uint64 = 0;
> +PleBAttribute.Uint64 = PageTableLibGetPleBMapAttribute
> (>PleB, ParentAttribute);
> 
> -if (Modify) {
> -  ParentPagingEntry->Uintn = (UINTN)Buffer + *BufferSize;
> -  ZeroMem ((VOID *)ParentPagingEntry->Uintn, SIZE_4KB);
> +if (ParentPagingEntry->Pce.Present == 0) {
>//
> -  // Set default attribute bits for PML5E/PML4E/PDPTE/PDE.
> +  // [LinearAddress, LinearAddress + Length] contains non-present range.
>//
> -  PageTableLibSetPnle (>Pnle, ,
> );
> +  Status = IsAttributesAndMaskValidForNonPresentEntry (Attribute,
> Mask);
> +  if (RETURN_ERROR (Status)) {
> +return Status;
> +  }

1. do you think put " OneOfPagingEntry.Pnle.Uint64 = 0;" in the if-body is 
better?
So both if and else initializes OneOfPagingEntry.
Other logic looks good to me.



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Re: [edk2-devel] [Patch V4 17/21] UefiCpuPkg/CpuPageTableLib: Add check for page table creation

[Ni, Ray]

Reviewed-by: Ray Ni 

> -Original Message-
> From: Tan, Dun 
> Sent: Thursday, March 23, 2023 3:41 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; Kumar,
> Rahul R ; Gerd Hoffmann 
> Subject: [Patch V4 17/21] UefiCpuPkg/CpuPageTableLib: Add check for page
> table creation
> 
> Add code to compare ParentPagingEntry Attribute and input
> Attribute to decide if new next level page table is needed
> in non-present ParentPagingEntry condition. This can help avoid
> unneccessary page table creation.
> 
> For example, there is a page table in which [0, 1G] is mapped(Lv4[0]
> ,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry).And we
> only want to map [1G, 1G+2M] linear address still as non-present.
> The expected behaviour should be nothing happens in the process.
> However, previous code logic doesn't check if ParentPagingEntry
> Attribute and input Attribute are the same in non-present
> ParentPagingEntry condition. Then a new 4K memory is allocated for
> Lv2 since 1G+2M is not 1G-aligned.
> So when ParentPagingEntry is non-present, before allocate 4K memory
> for next level paging, we also check if ParentPagingEntry Attribute&
> Mask and input Attribute are the same.
> 
> Signed-off-by: Dun Tan 
> Cc: Eric Dong 
> Cc: Ray Ni 
> Cc: Rahul Kumar 
> Cc: Gerd Hoffmann 
> ---
>  UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 10
> ++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
> b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
> index 982652b58b..55a756ad90 100644
> --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
> +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
> @@ -358,6 +358,16 @@ PageTableLibMapInLevel (
>return Status;
>  }
> 
> +//
> +// Check the attribute in ParentPagingEntry is equal to attribute 
> calculated
> by input Attribue and Mask.
> +//
> +PleBAttribute.Uint64 = PageTableLibGetPleBMapAttribute
> (>PleB, ParentAttribute);
> +if ((IA32_MAP_ATTRIBUTE_ATTRIBUTES () &
> IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask))
> +== (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) &
> IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)))
> +{
> +  return RETURN_SUCCESS;
> +}
> +
>  //
>  // The parent entry is CR3 or PML5E/PML4E/PDPTE/PDE.
>  // It does NOT point to an existing page directory.
> --
> 2.31.1.windows.1



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Re: [edk2-devel] [Patch V4 20/21] UefiCpuPkg/CpuPageTableLib: Add RandomTest for PAE paging

[Ni, Ray]

Reviewed-by: Ray Ni 

> -Original Message-
> From: Tan, Dun 
> Sent: Thursday, March 23, 2023 3:41 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; Kumar,
> Rahul R ; Gerd Hoffmann 
> Subject: [Patch V4 20/21] UefiCpuPkg/CpuPageTableLib: Add RandomTest
> for PAE paging
> 
> Add RandomTest for PAE paging.
> 
> Signed-off-by: Dun Tan 
> Cc: Eric Dong 
> Cc: Ray Ni 
> Cc: Rahul Kumar 
> Cc: Gerd Hoffmann 
> ---
> 
> UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo
> st.c |  2 ++
>  UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c  |  
> 3
> +--
>  UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c  | 
> 12
> 
>  3 files changed, 11 insertions(+), 6 deletions(-)
> 
> diff --git
> a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest
> Host.c
> b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest
> Host.c
> index e1efc84c82..8554eefa39 100644
> ---
> a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest
> Host.c
> +++
> b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest
> Host.c
> @@ -9,6 +9,7 @@
>  #include "CpuPageTableLibUnitTest.h"
> 
>  // --- 
> PageMode--
> TestCount-TestRangeCount---RandomOptions
> +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT
> mTestContextPagingPae   = { PagingPae, 100, 20, USE_RANDOM_ARRAY };
>  static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT
> mTestContextPaging4Level= { Paging4Level, 100, 20,
> USE_RANDOM_ARRAY };
>  static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT
> mTestContextPaging4Level1GB = { Paging4Level1GB, 100, 20,
> USE_RANDOM_ARRAY };
>  static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT
> mTestContextPaging5Level= { Paging5Level, 100, 20,
> USE_RANDOM_ARRAY };
> @@ -880,6 +881,7 @@ UefiTestMain (
>  goto EXIT;
>}
> 
> +  AddTestCase (RandomTestCase, "Random Test for PagingPae", "Random
> Test Case1", TestCaseforRandomTest, NULL, NULL,
> );
>AddTestCase (RandomTestCase, "Random Test for Paging4Level", "Random
> Test Case1", TestCaseforRandomTest, NULL, NULL,
> );
>AddTestCase (RandomTestCase, "Random Test for Paging4Level1G",
> "Random Test Case2", TestCaseforRandomTest, NULL, NULL,
> );
>AddTestCase (RandomTestCase, "Random Test for Paging5Level", "Random
> Test Case3", TestCaseforRandomTest, NULL, NULL,
> );
> diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
> b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
> index 18a5010c30..7e79b01823 100644
> --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
> +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
> @@ -258,10 +258,9 @@ ValidateAndRandomeModifyPageTable (
>UNIT_TEST_STATUS   Status;
>IA32_PAGING_ENTRY  *PagingEntry;
> 
> -  if ((PagingMode == Paging32bit) || (PagingMode == PagingPae) ||
> (PagingMode >= PagingModeMax)) {
> +  if ((PagingMode == Paging32bit) || (PagingMode >= PagingModeMax)) {
>  //
>  // 32bit paging is never supported.
> -// PAE paging will be supported later.
>  //
>  return UNIT_TEST_ERROR_TEST_FAILED;
>}
> diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c
> b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c
> index 22f179c21f..67776255c2 100644
> --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c
> +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c
> @@ -175,10 +175,9 @@ IsPageTableValid (
>  return UNIT_TEST_PASSED;
>}
> 
> -  if ((PagingMode == Paging32bit) || (PagingMode == PagingPae) ||
> (PagingMode >= PagingModeMax)) {
> +  if ((PagingMode == Paging32bit) || (PagingMode >= PagingModeMax)) {
>  //
>  // 32bit paging is never supported.
> -// PAE paging will be supported later.
>  //
>  return UNIT_TEST_ERROR_TEST_FAILED;
>}
> @@ -187,7 +186,12 @@ IsPageTableValid (
>MaxLevel = (UINT8)(PagingMode >> 8);
> 
>PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)PageTable;
> -  for (Index = 0; Index < 512; Index++) {
> +  for (Index = 0; Index < ((PagingMode == PagingPae) ? 4 : 512); Index++) {
> +if (PagingMode == PagingPae) {
> +  UT_ASSERT_EQUAL (PagingEntry[Index].PdptePae.Bits.MustBeZero, 0);
> +  UT_ASSERT_EQUAL (PagingEntry[Index].PdptePae.Bits.MustBeZero2, 0);
> +}
> +
>  Status = IsPageTableEntryValid ([Index], MaxLevel,
> MaxLeafLevel, Index << (9 * MaxLevel + 3));
>  if (Status != UNIT_TEST_PASSED) {
>return Status;
> @@ -264,7 +268,7 @@ GetEntryFromPageTable (
>UINT64 Index;
>IA32_PAGING_ENTRY  *PagingEntry;
> 
> -  if ((PagingMode == Paging32bit) || (PagingMode == PagingPae) ||
> (PagingMode >= PagingModeMax)) {
> +  if ((PagingMode == Paging32bit) || (PagingMode >= PagingModeMax)) {
>  //
>  // 32bit paging is never supported.
>  // PAE paging will be supported later.
> --
> 2.31.1.windows.1

[edk2-devel] [PATCH 1/1] OvmfPkg: replace SECURE_BOOT_FEATURE_ENABLED with PcdSecureBootSupported

[Gerd Hoffmann]

Drop the '-D SECURE_BOOT_FEATURE_ENABLED' compile time option,
use a new FeaturePcd instead.

Signed-off-by: Gerd Hoffmann 
---
 OvmfPkg/OvmfPkg.dec |  3 +++
 OvmfPkg/CloudHv/CloudHvX64.dsc  | 10 +-
 OvmfPkg/IntelTdx/IntelTdxX64.dsc| 10 +-
 OvmfPkg/Microvm/MicrovmX64.dsc  | 10 +-
 OvmfPkg/OvmfPkgIa32.dsc | 10 +-
 OvmfPkg/OvmfPkgIa32X64.dsc  | 10 +-
 OvmfPkg/OvmfPkgX64.dsc  | 10 +-
 OvmfPkg/Library/NvVarsFileLib/NvVarsFileLib.inf |  2 ++
 OvmfPkg/PlatformPei/PlatformPei.inf |  1 +
 OvmfPkg/Library/NvVarsFileLib/NvVarsFileLib.c   | 11 ---
 OvmfPkg/PlatformPei/Platform.c  |  7 ---
 11 files changed, 20 insertions(+), 64 deletions(-)

diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec
index 749fbd3b6bf4..03ae29e7b034 100644
--- a/OvmfPkg/OvmfPkg.dec
+++ b/OvmfPkg/OvmfPkg.dec
@@ -488,6 +488,9 @@ [PcdsFeatureFlag]
   #  used by OVMF, the varstore pflash chip, LockBox etc).
   gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire|FALSE|BOOLEAN|0x1e
 
+  ## This feature flag indicates the firmware build supports secure boot.
+  gUefiOvmfPkgTokenSpaceGuid.PcdSecureBootSupported|FALSE|BOOLEAN|0x6d
+
   ## Informs modules (including pre-DXE-phase modules) whether the platform
   #  firmware contains a CSM (Compatibility Support Module).
   #
diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc
index b9820cc14bee..5475d04271af 100644
--- a/OvmfPkg/CloudHv/CloudHvX64.dsc
+++ b/OvmfPkg/CloudHv/CloudHvX64.dsc
@@ -93,15 +93,6 @@ [BuildOptions]
   INTEL:*_*_*_CC_FLAGS = /D DISABLE_NEW_DEPRECATED_INTERFACES
   GCC:*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
 
-  #
-  # SECURE_BOOT_FEATURE_ENABLED
-  #
-!if $(SECURE_BOOT_ENABLE) == TRUE
-  MSFT:*_*_*_CC_FLAGS = /D SECURE_BOOT_FEATURE_ENABLED
-  INTEL:*_*_*_CC_FLAGS = /D SECURE_BOOT_FEATURE_ENABLED
-  GCC:*_*_*_CC_FLAGS = -D SECURE_BOOT_FEATURE_ENABLED
-!endif
-
 !include NetworkPkg/NetworkBuildOptions.dsc.inc
 
 [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
@@ -481,6 +472,7 @@ [PcdsFeatureFlag]
   gEfiMdeModulePkgTokenSpaceGuid.PcdEnableVariableRuntimeCache|FALSE
 !endif
 !if $(SECURE_BOOT_ENABLE) == TRUE
+  gUefiOvmfPkgTokenSpaceGuid.PcdSecureBootSupported|TRUE
   gEfiMdeModulePkgTokenSpaceGuid.PcdRequireSelfSignedPk|TRUE
 !endif
 
diff --git a/OvmfPkg/IntelTdx/IntelTdxX64.dsc b/OvmfPkg/IntelTdx/IntelTdxX64.dsc
index e6d85286e002..b6df7195166c 100644
--- a/OvmfPkg/IntelTdx/IntelTdxX64.dsc
+++ b/OvmfPkg/IntelTdx/IntelTdxX64.dsc
@@ -90,15 +90,6 @@ [BuildOptions]
   INTEL:*_*_*_CC_FLAGS = /D TDX_PEI_LESS_BOOT
   GCC:*_*_*_CC_FLAGS = -D TDX_PEI_LESS_BOOT
 
-  #
-  # SECURE_BOOT_FEATURE_ENABLED
-  #
-!if $(SECURE_BOOT_ENABLE) == TRUE
-  MSFT:*_*_*_CC_FLAGS = /D SECURE_BOOT_FEATURE_ENABLED
-  INTEL:*_*_*_CC_FLAGS = /D SECURE_BOOT_FEATURE_ENABLED
-  GCC:*_*_*_CC_FLAGS = -D SECURE_BOOT_FEATURE_ENABLED
-!endif
-
 [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
   GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
   XCODE:*_*_*_DLINK_FLAGS = -seg1addr 0x1000 -segalign 0x1000
@@ -391,6 +382,7 @@ [PcdsFeatureFlag]
   gUefiOvmfPkgTokenSpaceGuid.PcdCsmEnable|TRUE
 !endif
 !if $(SECURE_BOOT_ENABLE) == TRUE
+  gUefiOvmfPkgTokenSpaceGuid.PcdSecureBootSupported|TRUE
   gEfiMdeModulePkgTokenSpaceGuid.PcdRequireSelfSignedPk|TRUE
 !endif
 
diff --git a/OvmfPkg/Microvm/MicrovmX64.dsc b/OvmfPkg/Microvm/MicrovmX64.dsc
index 384b0b7afc74..3cba88006228 100644
--- a/OvmfPkg/Microvm/MicrovmX64.dsc
+++ b/OvmfPkg/Microvm/MicrovmX64.dsc
@@ -91,15 +91,6 @@ [BuildOptions]
   INTEL:*_*_*_CC_FLAGS = /D DISABLE_NEW_DEPRECATED_INTERFACES
   GCC:*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
 
-  #
-  # SECURE_BOOT_FEATURE_ENABLED
-  #
-!if $(SECURE_BOOT_ENABLE) == TRUE
-  MSFT:*_*_*_CC_FLAGS = /D SECURE_BOOT_FEATURE_ENABLED
-  INTEL:*_*_*_CC_FLAGS = /D SECURE_BOOT_FEATURE_ENABLED
-  GCC:*_*_*_CC_FLAGS = -D SECURE_BOOT_FEATURE_ENABLED
-!endif
-
 !include NetworkPkg/NetworkBuildOptions.dsc.inc
 
 [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
@@ -477,6 +468,7 @@ [PcdsFeatureFlag]
   gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
   gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
 !if $(SECURE_BOOT_ENABLE) == TRUE
+  gUefiOvmfPkgTokenSpaceGuid.PcdSecureBootSupported|TRUE
   gEfiMdeModulePkgTokenSpaceGuid.PcdRequireSelfSignedPk|TRUE
 !endif
 
diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index 9e4705f29b46..88d2c0d56bc3 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -94,15 +94,6 @@ [BuildOptions]
   INTEL:*_*_*_CC_FLAGS = /D DISABLE_NEW_DEPRECATED_INTERFACES
   GCC:*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
 
-  #
-  # SECURE_BOOT_FEATURE_ENABLED
-  #
-!if $(SECURE_BOOT_ENABLE) == TRUE
-  MSFT:*_*_*_CC_FLAGS = /D SECURE_BOOT_FEATURE_ENABLED
-  INTEL:*_*_*_CC_FLAGS = /D 

Re: [edk2-devel] [PATCH 7/8] BaseTools: remove duplicate includes: IndustryStandard/PeImage.h

[Chao Li]

Reviewed-by: Chao Li 


Thanks,
Chao
在 2023/3/23 19:17, Gerd Hoffmann 写道:

Use the MdePkg version instead of maintaining a copy in BaseTools.

Signed-off-by: Gerd Hoffmann
---
  .../C/Include/IndustryStandard/PeImage.h  | 779 --
  1 file changed, 779 deletions(-)
  delete mode 100644 BaseTools/Source/C/Include/IndustryStandard/PeImage.h

diff --git a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h 
b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
deleted file mode 100644
index 6e044938f5c6..
--- a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
+++ /dev/null
@@ -1,779 +0,0 @@
-/** @file
-  EFI image format for PE32+. Please note some data structures are different
-  for IA-32 and Itanium-based images, look for UINTN and the #ifdef EFI_IA64
-
-  @bug Fix text - doc as defined in MSFT EFI specification.
-
-  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
-  Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
-  Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights 
reserved.
-  Copyright (c) 2022, Loongson Technology Corporation Limited. All rights 
reserved.
-
-  SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef __PE_IMAGE_H__
-#define __PE_IMAGE_H__
-
-//
-// PE32+ Subsystem type for EFI images
-//
-#define EFI_IMAGE_SUBSYSTEM_EFI_APPLICATION 10
-#define EFI_IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER 11
-#define EFI_IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER  12
-#define EFI_IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER  13
-
-//
-// BugBug: Need to get a real answer for this problem. This is not in the
-// PE specification.
-//
-// A SAL runtime driver does not get fixed up when a transition to
-// virtual mode is made. In all other cases it should be treated
-// like a EFI_IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER image
-//
-#define EFI_IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER  13
-
-//
-// PE32+ Machine type for EFI images
-//
-#define IMAGE_FILE_MACHINE_I3860x014c
-#define IMAGE_FILE_MACHINE_EBC 0x0EBC
-#define IMAGE_FILE_MACHINE_X64 0x8664
-#define IMAGE_FILE_MACHINE_ARM 0x01c0  // Thumb only
-#define IMAGE_FILE_MACHINE_ARMT0x01c2  // 32bit Mixed ARM and 
Thumb/Thumb 2  Little Endian
-#define IMAGE_FILE_MACHINE_ARMTHUMB_MIXED IMAGE_FILE_MACHINE_ARMT
-#define IMAGE_FILE_MACHINE_ARM64   0xAA64  // 64bit ARM Architecture, 
Little Endian
-#define IMAGE_FILE_MACHINE_RISCV64 0x5064  // 64bit RISC-V ISA
-#define IMAGE_FILE_MACHINE_LOONGARCH64 0x6264  // 64bit LoongArch Architecture
-
-//
-// Support old names for backward compatible
-//
-#define EFI_IMAGE_MACHINE_IA32IMAGE_FILE_MACHINE_I386
-#define EFI_IMAGE_MACHINE_EBC IMAGE_FILE_MACHINE_EBC
-#define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64
-#define EFI_IMAGE_MACHINE_ARMTIMAGE_FILE_MACHINE_ARMT
-#define EFI_IMAGE_MACHINE_AARCH64 IMAGE_FILE_MACHINE_ARM64
-#define EFI_IMAGE_MACHINE_RISCV64 IMAGE_FILE_MACHINE_RISCV64
-#define EFI_IMAGE_MACHINE_LOONGARCH64 IMAGE_FILE_MACHINE_LOONGARCH64
-
-#define EFI_IMAGE_DOS_SIGNATURE 0x5A4D  // MZ
-#define EFI_IMAGE_OS2_SIGNATURE 0x454E  // NE
-#define EFI_IMAGE_OS2_SIGNATURE_LE  0x454C  // LE
-#define EFI_IMAGE_NT_SIGNATURE  0x4550  // PE00
-#define EFI_IMAGE_EDOS_SIGNATURE0x44454550  // PEED
-
-///
-/// PE images can start with an optional DOS header, so if an image is run
-///  under DOS it can print an error message.
-///
-typedef struct {
-  UINT16  e_magic;// Magic number
-  UINT16  e_cblp; // Bytes on last page of file
-  UINT16  e_cp;   // Pages in file
-  UINT16  e_crlc; // Relocations
-  UINT16  e_cparhdr;  // Size of header in paragraphs
-  UINT16  e_minalloc; // Minimum extra paragraphs needed
-  UINT16  e_maxalloc; // Maximum extra paragraphs needed
-  UINT16  e_ss;   // Initial (relative) SS value
-  UINT16  e_sp;   // Initial SP value
-  UINT16  e_csum; // Checksum
-  UINT16  e_ip;   // Initial IP value
-  UINT16  e_cs;   // Initial (relative) CS value
-  UINT16  e_lfarlc;   // File address of relocation table
-  UINT16  e_ovno; // Overlay number
-  UINT16  e_res[4];   // Reserved words
-  UINT16  e_oemid;// OEM identifier (for e_oeminfo)
-  UINT16  e_oeminfo;  // OEM information; e_oemid specific
-  UINT16  e_res2[10]; // Reserved words
-  UINT32  e_lfanew;   // File address of new exe header
-} EFI_IMAGE_DOS_HEADER;
-
-///
-/// File header format.
-///
-typedef struct {
-  UINT16  Machine;
-  UINT16  NumberOfSections;
-  UINT32  TimeDateStamp;
-  UINT32  PointerToSymbolTable;
-  UINT32  NumberOfSymbols;
-  UINT16  SizeOfOptionalHeader;
-  UINT16  Characteristics;
-} EFI_IMAGE_FILE_HEADER;
-
-#define EFI_IMAGE_SIZEOF_FILE_HEADER20
-
-#define EFI_IMAGE_FILE_RELOCS_STRIPPED  0x0001  // Relocation info 
stripped from file.
-#define EFI_IMAGE_FILE_EXECUTABLE_IMAGE 0x0002  // File is executable  

Re: [edk2-devel] [Patch V4 15/21] UefiCpuPkg: Fix IA32 build failure in CpuPageTableLib.inf

[Ni, Ray]

Reviewed-by: Ray Ni 

> -Original Message-
> From: Tan, Dun 
> Sent: Thursday, March 23, 2023 3:41 PM
> To: devel@edk2.groups.io
> Cc: Liu, Zhiguang ; Dong, Eric
> ; Ni, Ray ; Kumar, Rahul R
> 
> Subject: [Patch V4 15/21] UefiCpuPkg: Fix IA32 build failure in
> CpuPageTableLib.inf
> 
> From: Zhiguang Liu 
> 
> The definition of IA32_MAP_ATTRIBUTE has 64 bits, and one of the bit
> field PageTableBaseAddress is from bit 12 to bit 52. This means if the
> compiler treats the 64bits value as two UINT32 value, the field
> PageTableBaseAddress spans two UINT32 value. That's why when building in
> NOOPT mode in IA32, the below issue is noticed:
>   unresolved external symbol __allshl
> This patch fix the build failure by seperate field PageTableBaseAddress
> into two fields, make sure no field spans two UINT32 value.
> 
> Cc: Eric Dong 
> Cc: Ray Ni 
> Cc: Rahul Kumar 
> Signed-off-by: Zhiguang Liu 
> Signed-off-by: Ray Ni 
> ---
>  UefiCpuPkg/Include/Library/CpuPageTableLib.h |  32
> 
>  UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h| 125
> ++
> +--
>  UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c |  22
> +++---
>  3 files changed, 90 insertions(+), 89 deletions(-)
> 
> diff --git a/UefiCpuPkg/Include/Library/CpuPageTableLib.h
> b/UefiCpuPkg/Include/Library/CpuPageTableLib.h
> index c94d82ea65..5e545a35f6 100644
> --- a/UefiCpuPkg/Include/Library/CpuPageTableLib.h
> +++ b/UefiCpuPkg/Include/Library/CpuPageTableLib.h
> @@ -11,22 +11,22 @@
> 
>  typedef union {
>struct {
> -UINT64Present  : 1; // 0 = Not present in memory, 1 = 
> Present in
> memory
> -UINT64ReadWrite: 1; // 0 = Read-Only, 1= Read/Write
> -UINT64UserSupervisor   : 1; // 0 = Supervisor, 1=User
> -UINT64WriteThrough : 1; // 0 = Write-Back caching, 
> 1=Write-Through
> caching
> -UINT64CacheDisabled: 1; // 0 = Cached, 1=Non-Cached
> -UINT64Accessed : 1; // 0 = Not accessed, 1 = Accessed 
> (set by CPU)
> -UINT64Dirty: 1; // 0 = Not dirty, 1 = Dirty (set by 
> CPU)
> -UINT64Pat  : 1; // PAT
> -
> -UINT64Global   : 1; // 0 = Not global, 1 = Global (if 
> CR4.PGE = 1)
> -UINT64Reserved1: 3; // Ignored
> -
> -UINT64PageTableBaseAddress : 40; // Page Table Base Address
> -UINT64Reserved2: 7;  // Ignored
> -UINT64ProtectionKey: 4;  // Protection key
> -UINT64Nx   : 1;  // No Execute bit
> +UINT32Present  : 1;  // 0 = Not present in memory, 1 
> = Present
> in memory
> +UINT32ReadWrite: 1;  // 0 = Read-Only, 1= Read/Write
> +UINT32UserSupervisor   : 1;  // 0 = Supervisor, 1=User
> +UINT32WriteThrough : 1;  // 0 = Write-Back caching, 
> 1=Write-
> Through caching
> +UINT32CacheDisabled: 1;  // 0 = Cached, 1=Non-Cached
> +UINT32Accessed : 1;  // 0 = Not accessed, 1 = 
> Accessed (set by
> CPU)
> +UINT32Dirty: 1;  // 0 = Not dirty, 1 = Dirty 
> (set by CPU)
> +UINT32Pat  : 1;  // PAT
> +UINT32Global   : 1;  // 0 = Not global, 1 = Global 
> (if CR4.PGE = 1)
> +UINT32Reserved1: 3;  // Ignored
> +UINT32PageTableBaseAddressLow  : 20; // Page Table Base Address
> Low
> +
> +UINT32PageTableBaseAddressHigh : 20; // Page Table Base Address
> High
> +UINT32Reserved2: 7;  // Ignored
> +UINT32ProtectionKey: 4;  // Protection key
> +UINT32Nx   : 1;  // No Execute bit
>} Bits;
>UINT64Uint64;
>  } IA32_MAP_ATTRIBUTE;
> diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h
> b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h
> index 8d856d7c7e..2c67ecb469 100644
> --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h
> +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h
> @@ -29,11 +29,12 @@ typedef enum {
>  } IA32_PAGE_LEVEL;
> 
>  typedef struct {
> -  UINT64Present: 1;   // 0 = Not present in memory, 1 = 
> Present in
> memory
> -  UINT64ReadWrite  : 1;   // 0 = Read-Only, 1= Read/Write
> -  UINT64UserSupervisor : 1;   // 0 = Supervisor, 1=User
> -  UINT64Reserved   : 58;
> -  UINT64Nx : 1;// No Execute bit
> +  UINT32Present: 1;   // 0 = Not present in memory, 1 = 
> Present in
> memory
> +  UINT32ReadWrite  : 1;   // 0 = Read-Only, 1= Read/Write
> +  UINT32UserSupervisor : 1;   // 0 = Supervisor, 1=User
> +  UINT32Reserved0  : 29;
> +  UINT32Reserved1  

Re: [edk2-devel] [Patch V4 14/21] UefiCpuPkg/CpuPageTableLib: Modify RandomTest to check IsModified

[Ni, Ray]

Reviewed-by: Ray Ni 

> -Original Message-
> From: Tan, Dun 
> Sent: Thursday, March 23, 2023 3:41 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; Kumar,
> Rahul R ; Gerd Hoffmann ;
> Liu, Zhiguang 
> Subject: [Patch V4 14/21] UefiCpuPkg/CpuPageTableLib: Modify RandomTest
> to check IsModified
> 
> Modify RandomTest to check if parameter IsModified of
> PageTableMap() correctlly indicates whether input page table
> is modified or not.
> 
> Signed-off-by: Dun Tan 
> Cc: Eric Dong 
> Cc: Ray Ni 
> Cc: Rahul Kumar 
> Cc: Gerd Hoffmann 
> Cc: Zhiguang Liu 
> ---
>  UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c | 45
> +
>  1 file changed, 33 insertions(+), 12 deletions(-)
> 
> diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
> b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
> index 816fd7b446..6f1485976a 100644
> --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
> +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
> @@ -636,6 +636,8 @@ SingleMapEntryTest (
>VOID*Buffer;
>IA32_MAP_ENTRY  *Map;
>UINTN   MapCount;
> +  IA32_MAP_ENTRY  *Map2;
> +  UINTN   MapCount2;
>UINTN   Index;
>UINTN   KeyPointCount;
>UINTN   NewKeyPointCount;
> @@ -648,11 +650,13 @@ SingleMapEntryTest (
>UINT64  PreviousAddress;
>UINT64  RangeLimit;
>BOOLEAN IsNotPresent;
> +  BOOLEAN IsModified;
> 
>MapsIndex   = MapEntrys->Count;
>MapCount= 0;
>PreviousAddress = 0;
>IsNotPresent= FALSE;
> +  IsModified  = FALSE;
> 
>GenerateSingleRandomMapEntry (MaxAddress, MapEntrys);
>RangeLimit = MapEntrys->Maps[MapsIndex].LinearAddress + MapEntrys-
> >Maps[MapsIndex].Length;
> @@ -697,7 +701,7 @@ SingleMapEntryTest (
>MapEntrys->Maps[MapsIndex].Length,
>>Maps[MapsIndex].Attribute,
>>Maps[MapsIndex].Mask,
> -  NULL
> +  
>);
> 
>Attribute = >Maps[MapsIndex].Attribute;
> @@ -758,7 +762,7 @@ SingleMapEntryTest (
> MapEntrys->Maps[MapsIndex].Length,
> >Maps[MapsIndex].Attribute,
> >Maps[MapsIndex].Mask,
> -   NULL
> +   
> );
>}
> 
> @@ -772,18 +776,31 @@ SingleMapEntryTest (
>  return TestStatus;
>}
> 
> -  MapCount = 0;
> -  Status   = PageTableParse (*PageTable, PagingMode, NULL, );
> -  if (MapCount != 0) {
> +  MapCount2 = 0;
> +  Status= PageTableParse (*PageTable, PagingMode, NULL, );
> +  if (MapCount2 != 0) {
>  UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL);
> 
>  //
> -// Allocate memory for Maps
> +// Allocate memory for Map2
>  // Note the memory is only used in this one Single MapEntry Test
>  //
> -Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount * sizeof
> (IA32_MAP_ENTRY)));
> -ASSERT (Map != NULL);
> -Status = PageTableParse (*PageTable, PagingMode, Map, );
> +Map2 = AllocatePages (EFI_SIZE_TO_PAGES (MapCount2 * sizeof
> (IA32_MAP_ENTRY)));
> +ASSERT (Map2 != NULL);
> +Status = PageTableParse (*PageTable, PagingMode, Map2, );
> +  }
> +
> +  //
> +  // Check if PageTable has been modified.
> +  //
> +  if (MapCount2 != MapCount) {
> +UT_ASSERT_EQUAL (IsModified, TRUE);
> +  } else {
> +if (CompareMem (Map, Map2, MapCount2 * sizeof
> (IA32_MAP_ENTRY)) != 0) {
> +  UT_ASSERT_EQUAL (IsModified, TRUE);
> +} else {
> +  UT_ASSERT_EQUAL (IsModified, FALSE);
> +}
>}
> 
>UT_ASSERT_EQUAL (Status, RETURN_SUCCESS);
> @@ -793,17 +810,17 @@ SingleMapEntryTest (
>// Note the memory is only used in this one Single MapEntry Test
>//
>KeyPointCount = 0;
> -  GetKeyPointList (MapEntrys, Map, MapCount, NULL, );
> +  GetKeyPointList (MapEntrys, Map2, MapCount2, NULL, );
>KeyPointBuffer = AllocatePages (EFI_SIZE_TO_PAGES (KeyPointCount *
> sizeof (UINT64)));
>ASSERT (KeyPointBuffer != NULL);
>NewKeyPointCount = 0;
> -  GetKeyPointList (MapEntrys, Map, MapCount, KeyPointBuffer,
> );
> +  GetKeyPointList (MapEntrys, Map2, MapCount2, KeyPointBuffer,
> );
> 
>//
>// Compare all key point's attribute
>//
>for (Index = 0; Index < NewKeyPointCount; Index++) {
> -if (!CompareEntrysforOnePoint (KeyPointBuffer[Index], MapEntrys, Map,
> MapCount, InitMap, InitMapCount)) {
> +if (!CompareEntrysforOnePoint (KeyPointBuffer[Index], MapEntrys,
> Map2, MapCount2, InitMap, InitMapCount)) {
>DEBUG ((DEBUG_INFO, "Error happens at below key point\n"));
>DEBUG ((DEBUG_INFO, "Index = %d KeyPointBuffer[Index] = 0x%lx\n",
> Index, KeyPointBuffer[Index]));
>Value = GetEntryFromPageTable (*PageTable, PagingMode,
> 

Re: [edk2-devel] [Patch V4 13/21] UefiCpuPkg/CpuPageTableLib: Add OUTPUT IsModified parameter.

[Ni, Ray]

> @@ -290,7 +291,8 @@ PageTableLibMapInLevel (
>IN UINT64  Length,
>IN UINT64  Offset,
>IN IA32_MAP_ATTRIBUTE  *Attribute,
> -  IN IA32_MAP_ATTRIBUTE  *Mask
> +  IN IA32_MAP_ATTRIBUTE  *Mask,
> +  OUTBOOLEAN *IsModified
>)
>  {
>RETURN_STATUS   Status;
> @@ -316,6 +318,8 @@ PageTableLibMapInLevel (
>IA32_MAP_ATTRIBUTE  LocalParentAttribute;
>UINT64  PhysicalAddrInEntry;
>UINT64  PhysicalAddrInAttr;
> +  IA32_PAGING_ENTRY   OriginalParentPagingEntry;
> +  IA32_PAGING_ENTRY   OriginalCurrentPagingEntry;
> 
>ASSERT (Level != 0);
>ASSERT ((Attribute != NULL) && (Mask != NULL));
> @@ -328,8 +332,9 @@ PageTableLibMapInLevel (
>NopAttribute.Bits.ReadWrite  = 1;
>NopAttribute.Bits.UserSupervisor = 1;
> 
> -  LocalParentAttribute.Uint64 = ParentAttribute->Uint64;
> -  ParentAttribute = 
> +  LocalParentAttribute.Uint64  = ParentAttribute->Uint64;
> +  ParentAttribute  = 
> +  OriginalParentPagingEntry.Uint64 = ParentPagingEntry->Uint64;

1. can you add a blank line before "OriginalParentPagingEntry" assignment?
This helps to tell that the new added line has nothing to do with the original 
two lines code
that changes "ParentAttribute".

> 
> +  if (IsModified != NULL) {
> +*IsModified = FALSE;
> +  }

2. can you use code as below?
If (IsModified == NULL) {
  IsModified = LocalIsModified;
}

Then all code can just change "*IsModified" without checking if it's NULL.




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Re: [edk2-devel] [PATCH 6/8] BaseTools: switch from EFI_IMAGE_MACHINE_* to IMAGE_FILE_MACHINE_*

[Chao Li]

Reviewed-by: Chao Li 


Thanks,
Chao
在 2023/3/23 19:17, Gerd Hoffmann 写道:

Use the newer versions of the machine #defines.

Signed-off-by: Gerd Hoffmann
---
  BaseTools/Source/C/EfiRom/EfiRom.h| 10 ++---
  .../C/Include/IndustryStandard/PeImage.h  |  1 +
  BaseTools/Source/C/Common/BasePeCoff.c| 28 ++---
  BaseTools/Source/C/GenFv/GenFvInternalLib.c   | 42 +--
  BaseTools/Source/C/GenFw/Elf32Convert.c   |  6 +--
  BaseTools/Source/C/GenFw/Elf64Convert.c   | 10 ++---
  BaseTools/Source/C/GenFw/GenFw.c  |  8 +---
  7 files changed, 50 insertions(+), 55 deletions(-)

diff --git a/BaseTools/Source/C/EfiRom/EfiRom.h 
b/BaseTools/Source/C/EfiRom/EfiRom.h
index 0b39e2af2e0c..887a6a51e25b 100644
--- a/BaseTools/Source/C/EfiRom/EfiRom.h
+++ b/BaseTools/Source/C/EfiRom/EfiRom.h
@@ -108,11 +108,11 @@ typedef struct {
  // Machine Types
  //
  static STRING_LOOKUP  mMachineTypes[] = {
-  { EFI_IMAGE_MACHINE_IA32, "IA32" },
-  { EFI_IMAGE_MACHINE_X64, "X64" },
-  { EFI_IMAGE_MACHINE_EBC, "EBC" },
-  { EFI_IMAGE_MACHINE_ARMT, "ARM" },
-  { EFI_IMAGE_MACHINE_AARCH64, "AA64" },
+  { IMAGE_FILE_MACHINE_I386, "IA32" },
+  { IMAGE_FILE_MACHINE_X64, "X64" },
+  { IMAGE_FILE_MACHINE_EBC, "EBC" },
+  { IMAGE_FILE_MACHINE_ARMTHUMB_MIXED, "ARM" },
+  { IMAGE_FILE_MACHINE_ARM64, "AA64" },
{ 0, NULL }
  };
  
diff --git a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h

index 77ded3f61139..6e044938f5c6 100644
--- a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
+++ b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
@@ -42,6 +42,7 @@
  #define IMAGE_FILE_MACHINE_X64 0x8664
  #define IMAGE_FILE_MACHINE_ARM 0x01c0  // Thumb only
  #define IMAGE_FILE_MACHINE_ARMT0x01c2  // 32bit Mixed ARM and 
Thumb/Thumb 2  Little Endian
+#define IMAGE_FILE_MACHINE_ARMTHUMB_MIXED IMAGE_FILE_MACHINE_ARMT
  #define IMAGE_FILE_MACHINE_ARM64   0xAA64  // 64bit ARM Architecture, 
Little Endian
  #define IMAGE_FILE_MACHINE_RISCV64 0x5064  // 64bit RISC-V ISA
  #define IMAGE_FILE_MACHINE_LOONGARCH64 0x6264  // 64bit LoongArch Architecture
diff --git a/BaseTools/Source/C/Common/BasePeCoff.c 
b/BaseTools/Source/C/Common/BasePeCoff.c
index 78ef072bc354..bd410fb97d3d 100644
--- a/BaseTools/Source/C/Common/BasePeCoff.c
+++ b/BaseTools/Source/C/Common/BasePeCoff.c
@@ -188,13 +188,13 @@ Routine Description:
  ImageContext->Machine = TeHdr->Machine;
}
  
-  if (ImageContext->Machine != EFI_IMAGE_MACHINE_IA32 && \

-  ImageContext->Machine != EFI_IMAGE_MACHINE_X64  && \
-  ImageContext->Machine != EFI_IMAGE_MACHINE_ARMT && \
-  ImageContext->Machine != EFI_IMAGE_MACHINE_EBC  && \
-  ImageContext->Machine != EFI_IMAGE_MACHINE_AARCH64 && \
-  ImageContext->Machine != EFI_IMAGE_MACHINE_RISCV64 && \
-  ImageContext->Machine != EFI_IMAGE_MACHINE_LOONGARCH64) {
+  if (ImageContext->Machine != IMAGE_FILE_MACHINE_I386 && \
+  ImageContext->Machine != IMAGE_FILE_MACHINE_X64  && \
+  ImageContext->Machine != IMAGE_FILE_MACHINE_ARMTHUMB_MIXED && \
+  ImageContext->Machine != IMAGE_FILE_MACHINE_EBC  && \
+  ImageContext->Machine != IMAGE_FILE_MACHINE_ARM64 && \
+  ImageContext->Machine != IMAGE_FILE_MACHINE_RISCV64 && \
+  ImageContext->Machine != IMAGE_FILE_MACHINE_LOONGARCH64) {
  //
  // unsupported PeImage machine type
  //
@@ -801,16 +801,16 @@ Routine Description:
  
default:

  switch (MachineType) {
-case EFI_IMAGE_MACHINE_IA32:
+case IMAGE_FILE_MACHINE_I386:
Status = PeCoffLoaderRelocateIa32Image (Reloc, Fixup, , 
Adjust);
break;
-case EFI_IMAGE_MACHINE_ARMT:
+case IMAGE_FILE_MACHINE_ARMTHUMB_MIXED:
Status = PeCoffLoaderRelocateArmImage (, Fixup, , 
Adjust);
break;
-case EFI_IMAGE_MACHINE_RISCV64:
+case IMAGE_FILE_MACHINE_RISCV64:
Status = PeCoffLoaderRelocateRiscVImage (Reloc, Fixup, , 
Adjust);
break;
-case EFI_IMAGE_MACHINE_LOONGARCH64:
+case IMAGE_FILE_MACHINE_LOONGARCH64:
Status = PeCoffLoaderRelocateLoongArch64Image (Reloc, Fixup, 
, Adjust);
break;
  default:
@@ -1305,14 +1305,14 @@ PeCoffLoaderGetPdbPointer (
  //   generate PE32+ image with PE32 Magic.
  //
  switch (Hdr.Pe32->FileHeader.Machine) {
-case EFI_IMAGE_MACHINE_IA32:
-case EFI_IMAGE_MACHINE_ARMT:
+case IMAGE_FILE_MACHINE_I386:
+case IMAGE_FILE_MACHINE_ARMTHUMB_MIXED:
//
// Assume PE32 image with IA32 Machine field.
//
Magic = EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC;
break;
-case EFI_IMAGE_MACHINE_X64:
+case IMAGE_FILE_MACHINE_X64:
//
// Assume PE32+ image with X64 Machine field
//
diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c 

Re: [edk2-devel] [PATCH 2/8] BaseTools: remove duplicate includes: /ProcessorBind.h

[Chao Li]

Reviewed-by: Chao Li 


Thanks,
Chao
在 2023/3/23 19:17, Gerd Hoffmann 写道:

Use the MdePkg version instead of maintaining a copy in BaseTools.

Signed-off-by: Gerd Hoffmann
---
  .../Source/C/Include/AArch64/ProcessorBind.h  | 148 --
  .../Source/C/Include/Arm/ProcessorBind.h  | 147 --
  .../Source/C/Include/Ia32/ProcessorBind.h | 155 ---
  .../C/Include/LoongArch64/ProcessorBind.h |  80 
  .../Source/C/Include/RiscV64/ProcessorBind.h  |  85 
  .../Source/C/Include/X64/ProcessorBind.h  | 183 --
  BaseTools/Source/C/Common/Decompress.c|   1 +
  BaseTools/Source/C/Makefiles/header.makefile  |  14 +-
  BaseTools/Source/C/Makefiles/ms.common|  12 +-
  9 files changed, 19 insertions(+), 806 deletions(-)
  delete mode 100644 BaseTools/Source/C/Include/AArch64/ProcessorBind.h
  delete mode 100644 BaseTools/Source/C/Include/Arm/ProcessorBind.h
  delete mode 100644 BaseTools/Source/C/Include/Ia32/ProcessorBind.h
  delete mode 100644 BaseTools/Source/C/Include/LoongArch64/ProcessorBind.h
  delete mode 100644 BaseTools/Source/C/Include/RiscV64/ProcessorBind.h
  delete mode 100644 BaseTools/Source/C/Include/X64/ProcessorBind.h

diff --git a/BaseTools/Source/C/Include/AArch64/ProcessorBind.h 
b/BaseTools/Source/C/Include/AArch64/ProcessorBind.h
deleted file mode 100644
index dfa725b2e363..
--- a/BaseTools/Source/C/Include/AArch64/ProcessorBind.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/** @file
-  Processor or Compiler specific defines and types for AArch64.
-
-  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
-  Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
-  Portions copyright (c) 2013, ARM Ltd. All rights reserved.
-
-  SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef __PROCESSOR_BIND_H__
-#define __PROCESSOR_BIND_H__
-
-///
-/// Define the processor type so other code can make processor based choices
-///
-#define MDE_CPU_AARCH64
-
-//
-// Make sure we are using the correct packing rules per EFI specification
-//
-#ifndef __GNUC__
-#pragma pack()
-#endif
-
-#if _MSC_EXTENSIONS
-  //
-  // use Microsoft* C compiler dependent integer width types
-  //
-  typedef unsigned __int64UINT64;
-  typedef __int64 INT64;
-  typedef unsigned __int32UINT32;
-  typedef __int32 INT32;
-  typedef unsigned short  UINT16;
-  typedef unsigned short  CHAR16;
-  typedef short   INT16;
-  typedef unsigned char   BOOLEAN;
-  typedef unsigned char   UINT8;
-  typedef charCHAR8;
-  typedef signed char INT8;
-#else
-  //
-  // Use ANSI C 2000 stdint.h integer width declarations
-  //
-  #include 
-  typedef uint8_t   BOOLEAN;
-  typedef int8_tINT8;
-  typedef uint8_t   UINT8;
-  typedef int16_t   INT16;
-  typedef uint16_t  UINT16;
-  typedef int32_t   INT32;
-  typedef uint32_t  UINT32;
-  typedef int64_t   INT64;
-  typedef uint64_t  UINT64;
-  typedef char  CHAR8;
-  typedef uint16_t  CHAR16;
-
-#endif
-
-///
-/// Unsigned value of native width.  (4 bytes on supported 32-bit processor 
instructions,
-/// 8 bytes on supported 64-bit processor instructions)
-///
-typedef UINT64  UINTN;
-
-///
-/// Signed value of native width.  (4 bytes on supported 32-bit processor 
instructions,
-/// 8 bytes on supported 64-bit processor instructions)
-///
-typedef INT64   INTN;
-
-//
-// Processor specific defines
-//
-
-///
-/// A value of native width with the highest bit set.
-///
-#define MAX_BIT  0x8000
-
-///
-/// A value of native width with the two highest bits set.
-///
-#define MAX_2_BITS   0xC000
-
-///
-/// The stack alignment required for AARCH64
-///
-#define CPU_STACK_ALIGNMENT  16
-
-//
-// Modifier to ensure that all protocol member functions and EFI intrinsics
-// use the correct C calling convention. All protocol member functions and
-// EFI intrinsics are required to modify their member functions with EFIAPI.
-//
-#define EFIAPI
-
-#if defined(__GNUC__)
-  ///
-  /// For GNU assembly code, .global or .globl can declare global symbols.
-  /// Define this macro to unify the usage.
-  ///
-  #define ASM_GLOBAL .globl
-
-  #if !defined(__APPLE__)
-///
-/// ARM EABI defines that the linker should not manipulate call relocations
-/// (do bl/blx conversion) unless the target symbol has function type.
-/// CodeSourcery 2010.09 started requiring the .type to function properly
-///
-#define INTERWORK_FUNC(func__)   .type ASM_PFX(func__), %function
-
-#define GCC_ASM_EXPORT(func__)  \
- .global  _CONCATENATE (__USER_LABEL_PREFIX__, func__);\
- .type ASM_PFX(func__), %function
-
-#define GCC_ASM_IMPORT(func__)  \
- .extern  _CONCATENATE (__USER_LABEL_PREFIX__, func__)
-
-  #else
-//
-// .type not supported by Apple Xcode tools
-//
-#define INTERWORK_FUNC(func__)
-
-#define 

Re: [edk2-devel] [Patch V4 11/21] UefiCpuPkg/CpuPageTableLib:Modify RandomTest to check Mask/Attr

[Ni, Ray]

> -Original Message-
> From: Tan, Dun 
> Sent: Thursday, March 23, 2023 3:41 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; Kumar,
> Rahul R ; Gerd Hoffmann ;
> Liu, Zhiguang 
> Subject: [Patch V4 11/21] UefiCpuPkg/CpuPageTableLib:Modify RandomTest
> to check Mask/Attr
> 
> Modify RandomTest to check invalid input. When creating new page
> table or updating exsiting page table:
> 1.If set [LinearAddress, LinearAddress+Length] to non-preset, all
1. "non-present"

> +  //
> +  if (MapEntrys->Maps[MapsIndex].Length > 0) {
> +for (Index = 0; Index < MapCount; Index++) {
> +  if ((PreviousAddress < Map[Index].LinearAddress) &&
> +  (MapEntrys->Maps[MapsIndex].LinearAddress <
> Map[Index].LinearAddress) && (RangeLimit > PreviousAddress))
> +  {
> +//
> +// MapEntrys->Maps[MapsIndex] contains not-present range in
> exsiting page table.
> +//
> +break;
> +  }
> +
> +  PreviousAddress = Map[Index].LinearAddress + Map[Index].Length;
> +}
> +
> +if (PreviousAddress < RangeLimit) {
2. can you use "if (Index < MapCount)"?



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Re: [edk2-devel] [PATCH 3/9] BaseTools: Update CLANGDWARF toolchain and remove CLANG35 and CLANG38

[Ard Biesheuvel]

On Thu, 23 Mar 2023 at 10:04, Ard Biesheuvel  wrote:
>
> On Thu, 23 Mar 2023 at 02:30, Rebecca Cran  wrote:
> >
> > On 3/22/23 5:49 AM, Ard Biesheuvel wrote:
> >
> > >
> > > The reason I added CLANG3x support for ARM in the past is to ensure
> > > compatibility with the ARM proprietary, Clang based toolchain. At the
> > > time, we went with GNU ld, but I would actually prefer if we could
> > > make this work with LLD as well.
> >
> > Just to confirm, I'll keep lld for X64 and IA32, but I won't add
> > -fuse-ld=lld for ARM or AARCH64 since none of the toolchain definitions
> > currently do so.
> >
> >
> > The problem with trying to use lld for aarch64 is the following error:
> >
> >
> > GenFw: ERROR 3000: Invalid
> >WriteSections64():
> > /home/bcran/uefi/edk2/Build/ArmVirtQemu-AARCH64/RELEASE_CLANGDWARF/AARCH64/ArmVirtPkg/MemoryInitPei/MemoryInitPeim/DEBUG/MemoryInit.dll
> > due to its size (> 1 MB), this module requires 4 KB section alignment.
> >
>
> That seems to be a false positive error in GenFw.
>
> It looks like LLD turns
>
> ADRP
> ADD
>
> into
>
> NOP
> ADR
>
> if the target is within -/+ 1 MiB but it doesn't update the
> relocations, so GenFw goes off into the weeds. I.e..
>
>  304:   d503201fnop
> 304: R_AARCH64_ADR_PREL_PG_HI21 .data
>  308:   100015c1adr x1, 5c0 
> 308: R_AARCH64_ADD_ABS_LO12_NC  .data
>
> This is just another indication that using --emit-relocs is a bad
> idea, and we should really be building PIE executables and converting
> those based on the dynamic relocation instead.
>
> Adding -Wl,--no-relax to the DLINK flags should help with this,
> although I notice that there are other LLD related issues, in the ID
> map code I added to ArmVirtQemu a while ago, so ArmVirtQemu.dsc still
> does not build.

So I played around with this a bit more, also on ARM, and it seems to
me that simply disabling PIE linking is the best approach here - the
PE/COFF conversion essentially turns it into a relocatable binary
already, and so PIE linking does not actually add anything useful
here, and on ARM, the resulting ELF binary triggers an assert in GenFw

So adding

 -fuse-ld=lld -Wl,--no-relax,--no-pie

to both CLANG38_AARCH64_DLINK_FLAGS and CLANG38_ARM_DLINK_FLAGS works
for me locally, i.e., builds complete without errors and can boot
successfully.

We will also be able to drop the GccLto plugin pass through libraries,
which is rather nice as well.


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Re: [edk2-devel] [Patch V4 10/21] UefiCpuPkg/CpuPageTableLib:Modify RandomBoolean() in RandomTest

[Ni, Ray]

Reviewed-by: Ray Ni 

> -Original Message-
> From: Tan, Dun 
> Sent: Thursday, March 23, 2023 3:41 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; Kumar,
> Rahul R ; Gerd Hoffmann 
> Subject: [Patch V4 10/21] UefiCpuPkg/CpuPageTableLib:Modify
> RandomBoolean() in RandomTest
> 
> Add an input parameter to control the probability of returning
> true. Change RandomBoolean() in RandomTest from 50% chance
> returning true to returning true with the percentage of input
> Probability.
> 
> Signed-off-by: Dun Tan 
> Cc: Eric Dong 
> Cc: Ray Ni 
> Cc: Rahul Kumar 
> Cc: Gerd Hoffmann 
> ---
>  UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c | 43
> +--
>  1 file changed, 21 insertions(+), 22 deletions(-)
> 
> diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
> b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
> index 97a388ca1c..52eb9daa10 100644
> --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
> +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
> @@ -1,7 +1,7 @@
>  /** @file
>Random test case for Unit tests of the CpuPageTableLib instance of the
> CpuPageTableLib class
> 
> -  Copyright (c) 2022, Intel Corporation. All rights reserved.
> +  Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.
>SPDX-License-Identifier: BSD-2-Clause-Patent
> 
>  **/
> @@ -81,22 +81,6 @@ LocalRandomBytes (
>}
>  }
> 
> -/**
> -  Return a random boolean.
> -
> -  @return boolean
> -**/
> -BOOLEAN
> -RandomBoolean (
> -  VOID
> -  )
> -{
> -  BOOLEAN  Value;
> -
> -  LocalRandomBytes ((UINT8 *), sizeof (BOOLEAN));
> -  return Value%2;
> -}
> -
>  /**
>Return a 32bit random number.
> 
> @@ -139,6 +123,21 @@ Random64 (
>return (UINT64)(Value % (Limit - Start  + 1)) + Start;
>  }
> 
> +/**
> +  Returns true with the percentage of input Probability.
> +
> +  @param[in]   ProbabilityThe percentage to return true.
> +
> +  @return boolean
> +**/
> +BOOLEAN
> +RandomBoolean (
> +  UINT8  Probability
> +  )
> +{
> +  return ((Probability > ((UINT8)Random64 (0, 100))) ? TRUE : FALSE);
> +}
> +
>  /**
>Check if the Page table entry is valid
> 
> @@ -178,7 +177,7 @@
> ValidateAndRandomeModifyPageTablePageTableEntry (
>UT_ASSERT_EQUAL ((PagingEntry->Uint64 &
> mValidMaskLeaf[Level].Uint64), PagingEntry->Uint64);
>  }
> 
> -if ((RandomNumber < 100) && RandomBoolean ()) {
> +if ((RandomNumber < 100) && RandomBoolean (50)) {
>RandomNumber++;
>if (Level == 1) {
>  TempPhysicalBase = PagingEntry->Pte4K.Bits.PageTableBaseAddress;
> @@ -211,7 +210,7 @@
> ValidateAndRandomeModifyPageTablePageTableEntry (
>  UT_ASSERT_EQUAL ((PagingEntry->Uint64 &
> mValidMaskNoLeaf[Level].Uint64), PagingEntry->Uint64);
>}
> 
> -  if ((RandomNumber < 100) && RandomBoolean ()) {
> +  if ((RandomNumber < 100) && RandomBoolean (50)) {
>  RandomNumber++;
>  TempPhysicalBase = PagingEntry->Pnle.Bits.PageTableBaseAddress;
> 
> @@ -299,7 +298,7 @@ GenerateSingleRandomMapEntry (
>//
>// use AlignedTable to avoid that a random number can be very hard to be
> 1G or 2M aligned
>//
> -  if ((MapsIndex != 0) &&  (RandomBoolean ())) {
> +  if ((MapsIndex != 0) &&  (RandomBoolean (50))) {
>  FormerLinearAddress = MapEntrys->Maps[Random32 (0,
> (UINT32)MapsIndex-1)].LinearAddress;
>  if (FormerLinearAddress < 2 * (UINT64)SIZE_1GB) {
>FormerLinearAddressBottom = 0;
> @@ -323,7 +322,7 @@ GenerateSingleRandomMapEntry (
>//
>MapEntrys->Maps[MapsIndex].Length = Random64 (0, MIN (MaxAddress -
> MapEntrys->Maps[MapsIndex].LinearAddress, 10 * (UINT64)SIZE_1GB)) &
> AlignedTable[Random32 (0, ARRAY_SIZE (AlignedTable) -1)];
> 
> -  if ((MapsIndex != 0)  && (RandomBoolean ())) {
> +  if ((MapsIndex != 0)  && (RandomBoolean (50))) {
>  MapEntrys->Maps[MapsIndex].Attribute.Uint64 = MapEntrys-
> >Maps[Random32 (0, (UINT32)MapsIndex-1)].Attribute.Uint64;
>  MapEntrys->Maps[MapsIndex].Mask.Uint64  = MapEntrys-
> >Maps[Random32 (0, (UINT32)MapsIndex-1)].Mask.Uint64;
>} else {
> @@ -344,7 +343,7 @@ GenerateSingleRandomMapEntry (
>  //   Need to avoid such case when remove the Random option
> ONLY_ONE_ONE_MAPPING
>  //
>  MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress =
> (Random64 (0, (((UINT64)1)<<52) - 1) & AlignedTable[Random32 (0,
> ARRAY_SIZE (AlignedTable) -1)])>> 12;
> -if (RandomBoolean ()) {
> +if (RandomBoolean (50)) {
>MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress = 0;
>  }
>}
> --
> 2.31.1.windows.1



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Re: [edk2-devel] [Patch V4 09/21] UefiCpuPkg/CpuPageTableLib: Add manual test to check Mask and Attr

[Ni, Ray]

> +  PageTableBufferSize   = 0;
> +  PageTable = 0;
> +  Buffer= NULL;
> +  MapAttribute.Uint64   = 0;
> +  MapAttribute.Bits.Present = 1;
> +  MapMask.Uint64= 0;
> +  MapMask.Bits.Present  = 1;
> +  //
> +  // Create Page table to cover [0, 2G]. All fields of MapMask should be set.
> +  //
> +  Status = PageTableMap (, PagingMode, Buffer,
> , 0, SIZE_2GB, , );
> +  UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER);
> +  MapMask.Uint64 = MAX_UINT64;
> +  Status = PageTableMap (, PagingMode, Buffer,
> , 0, SIZE_2GB, , );
> +  UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL);
> +  Buffer = AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize));
> +  Status = PageTableMap (, PagingMode, Buffer,
> , 0, SIZE_2GB, , );
> +  UT_ASSERT_EQUAL (Status, RETURN_SUCCESS);
> +
> +  //
> +  // Update Page table to set [2G - 8K, 2G] from present to non-present. All
> fields of MapMask except present should be set.

"should not be set"?


> +
> +  //
> +  // Update Page table to set [2G - 8K, 2G] as present and RW. All fields of
> MapMask should not be set.

"should be set"?


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Re: [edk2-devel] [Patch V4 08/21] UefiCpuPkg/CpuPageTableLib:Add check for Mask and Attr

[Ni, Ray]

The commit message is very detailed.

But the function header comments are not.
Can you please update the function header comments to add 4 lines of
@retval RETURN_INVALID_PARAMETER, each line describes one invalid case.

It's ok to have multiple lines starting with @retval RETURN_INVALID_PARAMETER>

> +// If (LinearAddress + Length - 1) is not in the same ParentPagingEntry
> with (LinearAddress + Offset), then the remaining child PagingEntry
> +// starting from PagingEntryIndex of ParentPagingEntry is all covered by
> [LinearAddress + Offset, LinearAddress + Length - 1].
> +//
> +PagingEntryIndexEnd = (BitFieldRead64 (LinearAddress + Length - 1,
> BitStart + 9, 63) != BitFieldRead64 (LinearAddress + Offset, BitStart + 9, 
> 63)) ?
> 511 :
> +  (UINTN)BitFieldRead64 (LinearAddress + Length - 1, 
> BitStart,
> BitStart + 9 - 1);
> +PagingEntry = (IA32_PAGING_ENTRY
> *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (
> >Pnle);
> +for (Index = PagingEntryIndex; Index <= PagingEntryIndexEnd; Index++) {
> +  if (PagingEntry[Index].Pce.Present == 0) {
> +//
> +// [LinearAddress, LinearAddress + Length] contains non-present 
> range.
> +//
> +Status = IsAttributesAndMaskValidForNonPresentEntry (Attribute,
> Mask);
> +if (RETURN_ERROR (Status)) {
> +  return Status;
> +}
> +
> +break;

Why break out of the loop when meeting a non-present entry?



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Re: [edk2-devel] [Patch V4 07/21] UefiCpuPkg/MpInitLib: Add code to initialize MapMask

[Ni, Ray]

Reviewed-by: Ray Ni 

> -Original Message-
> From: Tan, Dun 
> Sent: Thursday, March 23, 2023 3:41 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; Kumar,
> Rahul R ; Gerd Hoffmann 
> Subject: [Patch V4 07/21] UefiCpuPkg/MpInitLib: Add code to initialize
> MapMask
> 
> In function CreatePageTable(), add code to initialize MapMask to
> MAX_UINT64. When creating new page table or map non-present range
> to present, all attributes should be provided.
> 
> Signed-off-by: Dun Tan 
> Cc: Eric Dong 
> Cc: Ray Ni 
> Cc: Rahul Kumar 
> Cc: Gerd Hoffmann 
> ---
>  UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c | 5 +
>  1 file changed, 1 insertion(+), 4 deletions(-)
> 
> diff --git a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c
> b/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c
> index 7cf91ed9c4..f20068152b 100644
> --- a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c
> +++ b/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c
> @@ -36,10 +36,7 @@ CreatePageTable (
>MapAttribute.Uint64 = Address;
>MapAttribute.Bits.Present   = 1;
>MapAttribute.Bits.ReadWrite = 1;
> -
> -  MapMask.Bits.PageTableBaseAddress = 1;
> -  MapMask.Bits.Present  = 1;
> -  MapMask.Bits.ReadWrite= 1;
> +  MapMask.Uint64  = MAX_UINT64;
> 
>PageTable   = 0;
>PageTableBufferSize = 0;
> --
> 2.31.1.windows.1



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Re: [edk2-devel] [Patch V4 06/21] UefiCpuPkg/CpuPageTableLib: Fix issue when splitting leaf entry

[Ni, Ray]

> +  ParentPagingEntry->Uint64 = ((UINTN)(VOID *)PagingEntry) |
> (ParentPagingEntry->Uint64 & (~IA32_PE_BASE_ADDRESS_MASK_40));

In this branch, ParentPagingEntry is a leaf entry covering 2M or 1G physical 
address range.
Then, why not use IA32_PE_BASE_ADDRESS_MASK_39? Because for the two types leaf 
entry, address
only occupies 39 bits, not 40bits.



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Re: [edk2-devel] [Patch V4 05/21] UefiCpuPkg/CpuPageTableLib:Clear PageSize bit(Bit7) for non-leaf

[Ni, Ray]

Reviewed-by: Ray Ni 

> -Original Message-
> From: Tan, Dun 
> Sent: Thursday, March 23, 2023 3:41 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; Kumar,
> Rahul R ; Gerd Hoffmann 
> Subject: [Patch V4 05/21] UefiCpuPkg/CpuPageTableLib:Clear PageSize
> bit(Bit7) for non-leaf
> 
> Clear PageSize bit(Bit7) for non-leaf entry in PageTableLibSetPnle.
> This function is used to set non-leaf entry attributes so it should
> make sure that the PageSize bit of the entry should be 0.
> 
> Signed-off-by: Dun Tan 
> Cc: Eric Dong 
> Cc: Ray Ni 
> Cc: Rahul Kumar 
> Cc: Gerd Hoffmann 
> ---
>  UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
> b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
> index ad68792ca8..cf0cfeca77 100644
> --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
> +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
> @@ -202,7 +202,8 @@ PageTableLibSetPnle (
>  Pnle->Bits.Nx = Attribute->Bits.Nx;
>}
> 
> -  Pnle->Bits.Accessed = 0;
> +  Pnle->Bits.Accessed   = 0;
> +  Pnle->Bits.MustBeZero = 0;
> 
>//
>// Set the attributes (WT, CD, A) to 0.
> --
> 2.31.1.windows.1



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Re: [edk2-devel] [Patch V4 04/21] UefiCpuPkg/CpuPageTableLib: Fix the non-1:1 mapping issue

[Ni, Ray]

> +  PhysicalAddrInEntry =
> IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS () +
> PagingEntryIndex * RegionLength;

Overall logic looks good to me.
But above code might fail to build in IA32 build due to UINT32 * UINT64.

> +  PhysicalAddrInAttr  =
> (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset)
> & (~RegionMask);
> +  if (PhysicalAddrInEntry == PhysicalAddrInAttr) {
> +return RETURN_SUCCESS;
> +  }
>  }
> 
>  ASSERT (Buffer == NULL || *BufferSize >= SIZE_4KB);
> --
> 2.31.1.windows.1



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Re: [edk2-devel] [Patch V4 03/21] UefiCpuPkg/CpuPageTableLib:Initialize some LocalVariable at beginning

[Ni, Ray]

Reviewed-by: Ray Ni 

> -Original Message-
> From: Tan, Dun 
> Sent: Thursday, March 23, 2023 3:41 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; Kumar,
> Rahul R ; Gerd Hoffmann 
> Subject: [Patch V4 03/21] UefiCpuPkg/CpuPageTableLib:Initialize some
> LocalVariable at beginning
> 
> Move some local variable initialization to the beginning of the
> function. Also delete duplicated calculation for RegionLength.
> 
> Signed-off-by: Dun Tan 
> Cc: Eric Dong 
> Cc: Ray Ni 
> Cc: Rahul Kumar 
> Cc: Gerd Hoffmann 
> ---
>  UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 21
> -
>  1 file changed, 12 insertions(+), 9 deletions(-)
> 
> diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
> b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
> index 218068a3e1..127b65183f 100644
> --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
> +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
> @@ -258,6 +258,7 @@ PageTableLibMapInLevel (
>UINTN   BitStart;
>UINTN   Index;
>IA32_PAGING_ENTRY   *PagingEntry;
> +  UINTN   PagingEntryIndex;
>IA32_PAGING_ENTRY   *CurrentPagingEntry;
>UINT64  RegionLength;
>UINT64  SubLength;
> @@ -288,6 +289,14 @@ PageTableLibMapInLevel (
>LocalParentAttribute.Uint64 = ParentAttribute->Uint64;
>ParentAttribute = 
> 
> +  //
> +  // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 21)
> or 4K (1 << 12).
> +  //
> +  BitStart = 12 + (Level - 1) * 9;
> +  PagingEntryIndex = (UINTN)BitFieldRead64 (LinearAddress + Offset,
> BitStart, BitStart + 9 - 1);
> +  RegionLength = REGION_LENGTH (Level);
> +  RegionMask   = RegionLength - 1;
> +
>//
>// ParentPagingEntry ONLY is deferenced for checking Present and
> MustBeOne bits
>// when Modify is FALSE.
> @@ -353,8 +362,7 @@ PageTableLibMapInLevel (
>//
>PageTableLibSetPnle (>Pnle, ,
> );
> 
> -  RegionLength = REGION_LENGTH (Level);
> -  PagingEntry  = (IA32_PAGING_ENTRY
> *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (
> >Pnle);
> +  PagingEntry = (IA32_PAGING_ENTRY
> *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (
> >Pnle);
>for (SubOffset = 0, Index = 0; Index < 512; Index++) {
>  PagingEntry[Index].Uint64 = OneOfPagingEntry.Uint64 + SubOffset;
>  SubOffset+= RegionLength;
> @@ -425,15 +433,10 @@ PageTableLibMapInLevel (
>}
> 
>//
> -  // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 21) 
> or
> 4K (1 << 12).
>// RegionStart:  points to the linear address that's aligned on 
> RegionLength
> and lower than (LinearAddress + Offset).
>//
> -  BitStart = 12 + (Level - 1) * 9;
> -  Index= (UINTN)BitFieldRead64 (LinearAddress + Offset, BitStart,
> BitStart + 9 - 1);
> -  RegionLength = LShiftU64 (1, BitStart);
> -  RegionMask   = RegionLength - 1;
> -  RegionStart  = (LinearAddress + Offset) & ~RegionMask;
> -
> +  Index   = PagingEntryIndex;
> +  RegionStart = (LinearAddress + Offset) & ~RegionMask;
>ParentAttribute->Uint64 = PageTableLibGetPnleMapAttribute
> (>Pnle, ParentAttribute);
> 
>//
> --
> 2.31.1.windows.1



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Re: [edk2-devel] [PATCH v3 2/3] Platform/AMD/MinBoardPkg: Adds SetCacheMtrrLib library

[Chang, Abner via groups.io]

[AMD Official Use Only - General]

Hi Abdul, one comment below,

> -Original Message-
> From: Abdul Lateef Attar 
> Sent: Thursday, March 23, 2023 2:14 PM
> To: devel@edk2.groups.io
> Cc: Attar, AbdulLateef (Abdul Lateef) ; Ard
> Biesheuvel ; Leif Lindholm
> ; Chang, Abner ;
> Michael D Kinney 
> Subject: [PATCH v3 2/3] Platform/AMD/MinBoardPkg: Adds SetCacheMtrrLib
> library
> 
> Adds SetCacheMtrrLib library for MinBoardPkg, which sets MTRR values for
> PEI phase and also modifies the MTRR value at the end of PEI phase.
> 
> Signed-off-by: Abdul Lateef Attar 
> Cc: Ard Biesheuvel 
> Cc: Leif Lindholm 
> Cc: Abner Chang 
> Cc: Michael D Kinney 
> ---
>  Platform/AMD/MinBoardPkg/MinBoardPkg.dsc  |   9 ++
>  .../SetCacheMtrrLib/SetCacheMtrrLib.inf   |  37 +
>  .../Library/SetCacheMtrrLib/SetCacheMtrrLib.c | 133 ++
>  3 files changed, 179 insertions(+)
>  create mode 100644
> Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
>  create mode 100644
> Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c
> 
> diff --git a/Platform/AMD/MinBoardPkg/MinBoardPkg.dsc
> b/Platform/AMD/MinBoardPkg/MinBoardPkg.dsc
> index 8c120c0649e7..810fac7aa9de 100644
> --- a/Platform/AMD/MinBoardPkg/MinBoardPkg.dsc
> +++ b/Platform/AMD/MinBoardPkg/MinBoardPkg.dsc
> @@ -17,5 +17,14 @@ [Defines]
>SUPPORTED_ARCHITECTURES = IA32 | X64
> 
>  [Packages]
> +  MdePkg/MdePkg.dec
>MinBoardPkg/MinBoardPkg.dec
> +  MinPlatformPkg/MinPlatformPkg.dec
> +  UefiCpuPkg/UefiCpuPkg.dec
> +
> +[LibraryClasses.common.PEIM]
> +
> +SetCacheMtrrLib|MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.i
> nf
> +
> +[Components.IA32]
> +  MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
> 
> diff --git
> a/Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.in
> f
> b/Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.in
> f
> new file mode 100644
> index ..add2e71651f9
> --- /dev/null
> +++
> b/Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.i
> +++ nf
> @@ -0,0 +1,37 @@
> +## @file
> +# Component information file for Platform SetCacheMtrr Library.
> +# This library implementation is for AMD processor based platforms.
> +#
> +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights
> +reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # ##
> +
> +[Defines]
> +  INF_VERSION= 1.29
> +  BASE_NAME  = PeiSetCacheMtrrLib
> +  FILE_GUID  = 1E8468E0-5EB4-4088-9B52-BFDC6E4DAE87
> +  MODULE_TYPE= PEIM
> +  VERSION_STRING = 1.0
> +  LIBRARY_CLASS  = SetCacheMtrrLib
> +
> +[LibraryClasses]
> +  BaseLib
> +  DebugLib
> +  MtrrLib
> +
> +[Packages]
> +  MdePkg/MdePkg.dec
> +  MinPlatformPkg/MinPlatformPkg.dec
> +  UefiCpuPkg/UefiCpuPkg.dec
> +
> +[Sources]
> +  SetCacheMtrrLib.c
> +
> +[Guids]
We can remove this section if no reference to any GUIDs.
You don't have to send another version of patch to address this comment, just 
update this file before you pushing it to edk2-platforms.

Reviewed-by: Abner Chang 
Thanks
Abner
> +
> +[Pcd]
> +  gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
> +  gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize
> +
> diff --git
> a/Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c
> b/Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c
> new file mode 100644
> index ..33b774fedbd3
> --- /dev/null
> +++
> b/Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c
> @@ -0,0 +1,133 @@
> +/** @file
> +
> +SetCacheMtrr library functions.
> +This library implementation is for AMD processor based platforms.
> +
> +Copyright (C) 2023 Advanced Micro Devices, Inc. All rights
> +reserved.
> +
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/**
> +  This function sets the cache MTRR values for PEI phase.
> +**/
> +VOID
> +EFIAPI
> +SetCacheMtrr (
> +  VOID
> +  )
> +{
> +  EFI_STATUS  Status;
> +
> +  Status = MtrrSetMemoryAttribute (
> + 0,
> + 0xA,
> + CacheWriteBack
> + );
> +  if (EFI_ERROR (Status)) {
> +DEBUG ((
> +  DEBUG_ERROR,
> +  "Error(%r) in setting CacheWriteBack for 0-0x9\n",
> +  Status
> +  ));
> +  }
> +
> +  Status = MtrrSetMemoryAttribute (
> + 0xA,
> + 0x2,
> + CacheUncacheable
> + );
> +  if (EFI_ERROR (Status)) {
> +DEBUG ((
> +  DEBUG_ERROR,
> +  "Error(%r) in setting CacheUncacheable for 0xA-0xB\n",
> +  Status
> +  ));
> +  }
> +
> +  Status = MtrrSetMemoryAttribute (
> + 0xC,
> + 0x4,
> + CacheWriteProtected
> + );
> +  if (EFI_ERROR (Status)) {
> +DEBUG ((
> +  DEBUG_ERROR,
> +  "Error(%r) in setting 

Re: [edk2-devel] [Patch V4 02/21] UefiCpuPkg/CpuPageTableLib: Add check for input Length

[Ni, Ray]

Reviewed-by: Ray Ni 

> -Original Message-
> From: Tan, Dun 
> Sent: Thursday, March 23, 2023 3:41 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; Kumar,
> Rahul R ; Gerd Hoffmann 
> Subject: [Patch V4 02/21] UefiCpuPkg/CpuPageTableLib: Add check for input
> Length
> 
> Add check for input Length in PageTableMap (). Return
> RETURN_SUCCESS when input Length is 0.
> 
> Signed-off-by: Dun Tan 
> Cc: Eric Dong 
> Cc: Ray Ni 
> Cc: Rahul Kumar 
> Cc: Gerd Hoffmann 
> ---
>  UefiCpuPkg/Include/Library/CpuPageTableLib.h | 4 ++--
>  UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 6 +-
>  2 files changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/UefiCpuPkg/Include/Library/CpuPageTableLib.h
> b/UefiCpuPkg/Include/Library/CpuPageTableLib.h
> index 2dc9b7d18e..5f44ece548 100644
> --- a/UefiCpuPkg/Include/Library/CpuPageTableLib.h
> +++ b/UefiCpuPkg/Include/Library/CpuPageTableLib.h
> @@ -1,7 +1,7 @@
>  /** @file
>Public include file for PageTableLib library.
> 
> -  Copyright (c) 2022, Intel Corporation. All rights reserved.
> +  Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.
>SPDX-License-Identifier: BSD-2-Clause-Patent
> 
>  **/
> @@ -81,7 +81,7 @@ typedef enum {
>@retval RETURN_BUFFER_TOO_SMALL   The buffer is too small for page
> table creation/updating.
>  BufferSize is updated to indicate the 
> expected buffer size.
>  Caller may still get 
> RETURN_BUFFER_TOO_SMALL with the
> new BufferSize.
> -  @retval RETURN_SUCCESSPageTable is created/updated 
> successfully.
> +  @retval RETURN_SUCCESSPageTable is created/updated
> successfully or the input Length is 0.
>  **/
>  RETURN_STATUS
>  EFIAPI
> diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
> b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
> index 52535e5a8d..218068a3e1 100644
> --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
> +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
> @@ -544,7 +544,7 @@ PageTableLibMapInLevel (
>@retval RETURN_BUFFER_TOO_SMALL   The buffer is too small for page
> table creation/updating.
>  BufferSize is updated to indicate the 
> expected buffer size.
>  Caller may still get 
> RETURN_BUFFER_TOO_SMALL with the
> new BufferSize.
> -  @retval RETURN_SUCCESSPageTable is created/updated 
> successfully.
> +  @retval RETURN_SUCCESSPageTable is created/updated
> successfully or the input Length is 0.
>  **/
>  RETURN_STATUS
>  EFIAPI
> @@ -567,6 +567,10 @@ PageTableMap (
>IA32_PAGE_LEVEL MaxLeafLevel;
>IA32_MAP_ATTRIBUTE  ParentAttribute;
> 
> +  if (Length == 0) {
> +return RETURN_SUCCESS;
> +  }
> +
>if ((PagingMode == Paging32bit) || (PagingMode == PagingPae) ||
> (PagingMode >= PagingModeMax)) {
>  //
>  // 32bit paging is never supported.
> --
> 2.31.1.windows.1



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Re: [edk2-devel] [PATCH v3 3/3] Maintainers.txt: Adds AMD/MinBoardPkg maintainers

[Chang, Abner via groups.io]

[AMD Official Use Only - General]

Reviewed-by: Abner Chang 

> -Original Message-
> From: Abdul Lateef Attar 
> Sent: Thursday, March 23, 2023 2:14 PM
> To: devel@edk2.groups.io
> Cc: Attar, AbdulLateef (Abdul Lateef) ; Attar,
> AbdulLateef (Abdul Lateef) ; Ard Biesheuvel
> ; Leif Lindholm ;
> Chang, Abner ; Michael D Kinney
> 
> Subject: [PATCH v3 3/3] Maintainers.txt: Adds AMD/MinBoardPkg
> maintainers
> 
> From: Abdul Lateef Attar 
> 
> Adds maintainers for AMD/MinBoardPkg
> 
> Signed-off-by: Abdul Lateef Attar 
> Cc: Ard Biesheuvel 
> Cc: Leif Lindholm 
> Cc: Abner Chang 
> Cc: Michael D Kinney 
> ---
>  Maintainers.txt | 5 +
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Maintainers.txt b/Maintainers.txt index
> 747191366070..3ce578abcf7e 100644
> --- a/Maintainers.txt
> +++ b/Maintainers.txt
> @@ -91,6 +91,11 @@ F: Silicon/AMD/Styx/
>  M: Ard Biesheuvel 
>  M: Leif Lindholm 
> 
> +AMD MinBoard package for MinPlatformPkg
> +F: Platform/AMD/MinBoardPkg
> +M: Abner Chang 
> +M: Abdul Lateef Attar 
> +
>  Ampere Computing
>  F: Platform/Ampere
>  F: Silicon/Ampere
> --
> 2.25.1


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Re: [edk2-devel] [PATCH v3 1/3] Platform/AMD: Adds MinBoardPkg to support MinPlatformPkg

[Chang, Abner via groups.io]

[AMD Official Use Only - General]

Reviewed-by: Abner Chang 

> -Original Message-
> From: Abdul Lateef Attar 
> Sent: Thursday, March 23, 2023 2:14 PM
> To: devel@edk2.groups.io
> Cc: Attar, AbdulLateef (Abdul Lateef) ; Ard
> Biesheuvel ; Leif Lindholm
> ; Chang, Abner ;
> Michael D Kinney 
> Subject: [PATCH v3 1/3] Platform/AMD: Adds MinBoardPkg to support
> MinPlatformPkg
> 
> Adds initial DEC and DSC file for MinBoardPkg.
> This package provides supporting modules for AMD boards to
> leverage MinPlatformPkg framework.
> 
> Signed-off-by: Abdul Lateef Attar 
> Cc: Ard Biesheuvel 
> Cc: Leif Lindholm 
> Cc: Abner Chang 
> Cc: Michael D Kinney 
> ---
>  Platform/AMD/MinBoardPkg/MinBoardPkg.dec | 19
> +++
>  Platform/AMD/MinBoardPkg/MinBoardPkg.dsc | 21
> +
>  2 files changed, 40 insertions(+)
>  create mode 100644 Platform/AMD/MinBoardPkg/MinBoardPkg.dec
>  create mode 100644 Platform/AMD/MinBoardPkg/MinBoardPkg.dsc
> 
> diff --git a/Platform/AMD/MinBoardPkg/MinBoardPkg.dec
> b/Platform/AMD/MinBoardPkg/MinBoardPkg.dec
> new file mode 100644
> index ..23d737d196a2
> --- /dev/null
> +++ b/Platform/AMD/MinBoardPkg/MinBoardPkg.dec
> @@ -0,0 +1,19 @@
> +## @file MinBoardPkg.dec
> +#  Declaration file for AMD's MinBoardPkg.
> +#
> +#  This package supports AMD processor family based board as per the
> MinPlatform
> +#  Arch specification.
> +#
> +#  Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#  @par Specification Reference:
> +#   -https://tianocore-docs.github.io/edk2-
> MinimumPlatformSpecification/draft/ 0.7
> +##
> +
> +[Defines]
> +  DEC_SPECIFICATION  = 1.27
> +  PACKAGE_NAME   = MinBoardPkg
> +  PACKAGE_GUID   = 44F9D761-9ECB-43DD-A5AC-177E5048701B
> +  PACKAGE_VERSION= 0.1
> +
> diff --git a/Platform/AMD/MinBoardPkg/MinBoardPkg.dsc
> b/Platform/AMD/MinBoardPkg/MinBoardPkg.dsc
> new file mode 100644
> index ..8c120c0649e7
> --- /dev/null
> +++ b/Platform/AMD/MinBoardPkg/MinBoardPkg.dsc
> @@ -0,0 +1,21 @@
> +## @file
> +#  MinBoardPkg.dsc
> +#
> +#  Description file for AMD MinBoardPkg
> +#
> +#  Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +##
> +
> +[Defines]
> +  DSC_SPECIFICATION   = 1.30
> +  PLATFORM_GUID   = 88F8A9AE-2FA0-4D58-A6F9-05F635C05F4E
> +  PLATFORM_NAME   = MinBoardPkg
> +  PLATFORM_VERSION= 0.1
> +  OUTPUT_DIRECTORY= Build/$(PLATFORM_NAME)
> +  BUILD_TARGETS   = DEBUG | RELEASE | NOOPT
> +  SUPPORTED_ARCHITECTURES = IA32 | X64
> +
> +[Packages]
> +  MinBoardPkg/MinBoardPkg.dec
> +
> --
> 2.25.1


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[edk2-devel] [PATCH 7/8] BaseTools: remove duplicate includes: IndustryStandard/PeImage.h

[Gerd Hoffmann]

Use the MdePkg version instead of maintaining a copy in BaseTools.

Signed-off-by: Gerd Hoffmann 
---
 .../C/Include/IndustryStandard/PeImage.h  | 779 --
 1 file changed, 779 deletions(-)
 delete mode 100644 BaseTools/Source/C/Include/IndustryStandard/PeImage.h

diff --git a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h 
b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
deleted file mode 100644
index 6e044938f5c6..
--- a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
+++ /dev/null
@@ -1,779 +0,0 @@
-/** @file
-  EFI image format for PE32+. Please note some data structures are different
-  for IA-32 and Itanium-based images, look for UINTN and the #ifdef EFI_IA64
-
-  @bug Fix text - doc as defined in MSFT EFI specification.
-
-  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
-  Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
-  Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights 
reserved.
-  Copyright (c) 2022, Loongson Technology Corporation Limited. All rights 
reserved.
-
-  SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef __PE_IMAGE_H__
-#define __PE_IMAGE_H__
-
-//
-// PE32+ Subsystem type for EFI images
-//
-#define EFI_IMAGE_SUBSYSTEM_EFI_APPLICATION 10
-#define EFI_IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER 11
-#define EFI_IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER  12
-#define EFI_IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER  13
-
-//
-// BugBug: Need to get a real answer for this problem. This is not in the
-// PE specification.
-//
-// A SAL runtime driver does not get fixed up when a transition to
-// virtual mode is made. In all other cases it should be treated
-// like a EFI_IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER image
-//
-#define EFI_IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER  13
-
-//
-// PE32+ Machine type for EFI images
-//
-#define IMAGE_FILE_MACHINE_I3860x014c
-#define IMAGE_FILE_MACHINE_EBC 0x0EBC
-#define IMAGE_FILE_MACHINE_X64 0x8664
-#define IMAGE_FILE_MACHINE_ARM 0x01c0  // Thumb only
-#define IMAGE_FILE_MACHINE_ARMT0x01c2  // 32bit Mixed ARM and 
Thumb/Thumb 2  Little Endian
-#define IMAGE_FILE_MACHINE_ARMTHUMB_MIXED IMAGE_FILE_MACHINE_ARMT
-#define IMAGE_FILE_MACHINE_ARM64   0xAA64  // 64bit ARM Architecture, 
Little Endian
-#define IMAGE_FILE_MACHINE_RISCV64 0x5064  // 64bit RISC-V ISA
-#define IMAGE_FILE_MACHINE_LOONGARCH64 0x6264  // 64bit LoongArch Architecture
-
-//
-// Support old names for backward compatible
-//
-#define EFI_IMAGE_MACHINE_IA32IMAGE_FILE_MACHINE_I386
-#define EFI_IMAGE_MACHINE_EBC IMAGE_FILE_MACHINE_EBC
-#define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64
-#define EFI_IMAGE_MACHINE_ARMTIMAGE_FILE_MACHINE_ARMT
-#define EFI_IMAGE_MACHINE_AARCH64 IMAGE_FILE_MACHINE_ARM64
-#define EFI_IMAGE_MACHINE_RISCV64 IMAGE_FILE_MACHINE_RISCV64
-#define EFI_IMAGE_MACHINE_LOONGARCH64 IMAGE_FILE_MACHINE_LOONGARCH64
-
-#define EFI_IMAGE_DOS_SIGNATURE 0x5A4D  // MZ
-#define EFI_IMAGE_OS2_SIGNATURE 0x454E  // NE
-#define EFI_IMAGE_OS2_SIGNATURE_LE  0x454C  // LE
-#define EFI_IMAGE_NT_SIGNATURE  0x4550  // PE00
-#define EFI_IMAGE_EDOS_SIGNATURE0x44454550  // PEED
-
-///
-/// PE images can start with an optional DOS header, so if an image is run
-///  under DOS it can print an error message.
-///
-typedef struct {
-  UINT16  e_magic;// Magic number
-  UINT16  e_cblp; // Bytes on last page of file
-  UINT16  e_cp;   // Pages in file
-  UINT16  e_crlc; // Relocations
-  UINT16  e_cparhdr;  // Size of header in paragraphs
-  UINT16  e_minalloc; // Minimum extra paragraphs needed
-  UINT16  e_maxalloc; // Maximum extra paragraphs needed
-  UINT16  e_ss;   // Initial (relative) SS value
-  UINT16  e_sp;   // Initial SP value
-  UINT16  e_csum; // Checksum
-  UINT16  e_ip;   // Initial IP value
-  UINT16  e_cs;   // Initial (relative) CS value
-  UINT16  e_lfarlc;   // File address of relocation table
-  UINT16  e_ovno; // Overlay number
-  UINT16  e_res[4];   // Reserved words
-  UINT16  e_oemid;// OEM identifier (for e_oeminfo)
-  UINT16  e_oeminfo;  // OEM information; e_oemid specific
-  UINT16  e_res2[10]; // Reserved words
-  UINT32  e_lfanew;   // File address of new exe header
-} EFI_IMAGE_DOS_HEADER;
-
-///
-/// File header format.
-///
-typedef struct {
-  UINT16  Machine;
-  UINT16  NumberOfSections;
-  UINT32  TimeDateStamp;
-  UINT32  PointerToSymbolTable;
-  UINT32  NumberOfSymbols;
-  UINT16  SizeOfOptionalHeader;
-  UINT16  Characteristics;
-} EFI_IMAGE_FILE_HEADER;
-
-#define EFI_IMAGE_SIZEOF_FILE_HEADER20
-
-#define EFI_IMAGE_FILE_RELOCS_STRIPPED  0x0001  // Relocation info 
stripped from file.
-#define EFI_IMAGE_FILE_EXECUTABLE_IMAGE 0x0002  // File is executable  
(i.e. no unresolved externel references).
-#define 

[edk2-devel] [PATCH 8/8] BaseTools: remove duplicate includes: IndustryStandard/*.h

[Gerd Hoffmann]

Use the MdePkg versions instead of maintaining a copy in BaseTools.

Signed-off-by: Gerd Hoffmann 
---
 BaseTools/Source/C/EfiRom/EfiRom.h|   4 +-
 .../C/Include/IndustryStandard/Bluetooth.h|  56 --
 .../C/Include/IndustryStandard/EfiPci.h   |  51 --
 ...emoryMappedConfigurationSpaceAccessTable.h |  39 --
 .../Source/C/Include/IndustryStandard/pci22.h | 536 --
 .../Source/C/Include/IndustryStandard/pci23.h |  18 -
 .../Source/C/Include/IndustryStandard/pci30.h |  38 --
 7 files changed, 2 insertions(+), 740 deletions(-)
 delete mode 100644 BaseTools/Source/C/Include/IndustryStandard/Bluetooth.h
 delete mode 100644 BaseTools/Source/C/Include/IndustryStandard/EfiPci.h
 delete mode 100644 
BaseTools/Source/C/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h
 delete mode 100644 BaseTools/Source/C/Include/IndustryStandard/pci22.h
 delete mode 100644 BaseTools/Source/C/Include/IndustryStandard/pci23.h
 delete mode 100644 BaseTools/Source/C/Include/IndustryStandard/pci30.h

diff --git a/BaseTools/Source/C/EfiRom/EfiRom.h 
b/BaseTools/Source/C/EfiRom/EfiRom.h
index 887a6a51e25b..dfb4c3207794 100644
--- a/BaseTools/Source/C/EfiRom/EfiRom.h
+++ b/BaseTools/Source/C/EfiRom/EfiRom.h
@@ -16,8 +16,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include 
 #include  // for PE32 structure definitions
 
-#include   // for option ROM header structures
-#include 
+#include   // for option ROM header structures
+#include 
 
 #include "Compress.h"
 #include "CommonLib.h"
diff --git a/BaseTools/Source/C/Include/IndustryStandard/Bluetooth.h 
b/BaseTools/Source/C/Include/IndustryStandard/Bluetooth.h
deleted file mode 100644
index 82f5e6299e78..
--- a/BaseTools/Source/C/Include/IndustryStandard/Bluetooth.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/** @file
-  This file contains the Bluetooth definitions that are consumed by drivers.
-  These definitions are from Bluetooth Core Specification Version 4.0 June, 
2010
-
-  Copyright (c) 2017, Intel Corporation. All rights reserved.
-  SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef _BLUETOOTH_H_
-#define _BLUETOOTH_H_
-
-#pragma pack(1)
-
-///
-/// BLUETOOTH_ADDRESS
-///
-typedef struct {
-  ///
-  /// 48bit Bluetooth device address.
-  ///
-  UINT8  Address[6];
-} BLUETOOTH_ADDRESS;
-
-///
-/// BLUETOOTH_CLASS_OF_DEVICE. See Bluetooth specification for detail.
-///
-typedef struct {
-  UINT8  FormatType:2;
-  UINT8  MinorDeviceClass: 6;
-  UINT16 MajorDeviceClass: 5;
-  UINT16 MajorServiceClass:11;
-} BLUETOOTH_CLASS_OF_DEVICE;
-
-///
-/// BLUETOOTH_LE_ADDRESS
-///
-typedef struct {
-  ///
-  /// 48-bit Bluetooth device address
-  ///
-  UINT8  Address[6];
-  ///
-  /// 0x00 - Public Device Address
-  /// 0x01 - Random Device Address
-  ///
-  UINT8  Type;
-} BLUETOOTH_LE_ADDRESS;
-
-#pragma pack()
-
-#define BLUETOOTH_HCI_COMMAND_LOCAL_READABLE_NAME_MAX_SIZE248
-
-#define BLUETOOTH_HCI_LINK_KEY_SIZE   16
-
-#endif
diff --git a/BaseTools/Source/C/Include/IndustryStandard/EfiPci.h 
b/BaseTools/Source/C/Include/IndustryStandard/EfiPci.h
deleted file mode 100644
index aab27f9bf914..
--- a/BaseTools/Source/C/Include/IndustryStandard/EfiPci.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/** @file
-  Support for EFI PCI specification.
-
-  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
-
-  SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef _EFI_PCI_H_
-#define _EFI_PCI_H_
-
-//#include "pci22.h"
-//#include "pci23.h"
-//#include "pci30.h"
-
-#pragma pack(push, 1)
-
-typedef struct {
-  UINT8 Register;
-  UINT8 Function;
-  UINT8 Device;
-  UINT8 Bus;
-  UINT8 Reserved[4];
-} DEFIO_PCI_ADDR;
-
-#define EFI_ROOT_BRIDGE_LIST'eprb'
-#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE   0x0EF1
-
-typedef struct {
-  UINT16  Signature;// 0xaa55
-  UINT16  InitializationSize;
-  UINT32  EfiSignature; // 0x0EF1
-  UINT16  EfiSubsystem;
-  UINT16  EfiMachineType;
-  UINT16  CompressionType;
-  UINT8   Reserved[8];
-  UINT16  EfiImageHeaderOffset;
-  UINT16  PcirOffset;
-} EFI_PCI_EXPANSION_ROM_HEADER;
-
-typedef union {
-  UINT8   *Raw;
-  PCI_EXPANSION_ROM_HEADER*Generic;
-  EFI_PCI_EXPANSION_ROM_HEADER*Efi;
-  EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;
-} EFI_PCI_ROM_HEADER;
-
-#pragma pack(pop)
-
-#endif
diff --git 
a/BaseTools/Source/C/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h
 
b/BaseTools/Source/C/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h
deleted file mode 100644
index 3d435001fc4d..
--- 
a/BaseTools/Source/C/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/** @file
-  ACPI memory mapped configuration space access table definition, defined at
-  in the PCI Firmware Specification, version 3.0 draft version 0.5.
-  Specification is available at 

[edk2-devel] [PATCH 6/8] BaseTools: switch from EFI_IMAGE_MACHINE_* to IMAGE_FILE_MACHINE_*

[Gerd Hoffmann]

Use the newer versions of the machine #defines.

Signed-off-by: Gerd Hoffmann 
---
 BaseTools/Source/C/EfiRom/EfiRom.h| 10 ++---
 .../C/Include/IndustryStandard/PeImage.h  |  1 +
 BaseTools/Source/C/Common/BasePeCoff.c| 28 ++---
 BaseTools/Source/C/GenFv/GenFvInternalLib.c   | 42 +--
 BaseTools/Source/C/GenFw/Elf32Convert.c   |  6 +--
 BaseTools/Source/C/GenFw/Elf64Convert.c   | 10 ++---
 BaseTools/Source/C/GenFw/GenFw.c  |  8 +---
 7 files changed, 50 insertions(+), 55 deletions(-)

diff --git a/BaseTools/Source/C/EfiRom/EfiRom.h 
b/BaseTools/Source/C/EfiRom/EfiRom.h
index 0b39e2af2e0c..887a6a51e25b 100644
--- a/BaseTools/Source/C/EfiRom/EfiRom.h
+++ b/BaseTools/Source/C/EfiRom/EfiRom.h
@@ -108,11 +108,11 @@ typedef struct {
 // Machine Types
 //
 static STRING_LOOKUP  mMachineTypes[] = {
-  { EFI_IMAGE_MACHINE_IA32, "IA32" },
-  { EFI_IMAGE_MACHINE_X64, "X64" },
-  { EFI_IMAGE_MACHINE_EBC, "EBC" },
-  { EFI_IMAGE_MACHINE_ARMT, "ARM" },
-  { EFI_IMAGE_MACHINE_AARCH64, "AA64" },
+  { IMAGE_FILE_MACHINE_I386, "IA32" },
+  { IMAGE_FILE_MACHINE_X64, "X64" },
+  { IMAGE_FILE_MACHINE_EBC, "EBC" },
+  { IMAGE_FILE_MACHINE_ARMTHUMB_MIXED, "ARM" },
+  { IMAGE_FILE_MACHINE_ARM64, "AA64" },
   { 0, NULL }
 };
 
diff --git a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h 
b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
index 77ded3f61139..6e044938f5c6 100644
--- a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
+++ b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
@@ -42,6 +42,7 @@
 #define IMAGE_FILE_MACHINE_X64 0x8664
 #define IMAGE_FILE_MACHINE_ARM 0x01c0  // Thumb only
 #define IMAGE_FILE_MACHINE_ARMT0x01c2  // 32bit Mixed ARM and 
Thumb/Thumb 2  Little Endian
+#define IMAGE_FILE_MACHINE_ARMTHUMB_MIXED IMAGE_FILE_MACHINE_ARMT
 #define IMAGE_FILE_MACHINE_ARM64   0xAA64  // 64bit ARM Architecture, 
Little Endian
 #define IMAGE_FILE_MACHINE_RISCV64 0x5064  // 64bit RISC-V ISA
 #define IMAGE_FILE_MACHINE_LOONGARCH64 0x6264  // 64bit LoongArch Architecture
diff --git a/BaseTools/Source/C/Common/BasePeCoff.c 
b/BaseTools/Source/C/Common/BasePeCoff.c
index 78ef072bc354..bd410fb97d3d 100644
--- a/BaseTools/Source/C/Common/BasePeCoff.c
+++ b/BaseTools/Source/C/Common/BasePeCoff.c
@@ -188,13 +188,13 @@ Routine Description:
 ImageContext->Machine = TeHdr->Machine;
   }
 
-  if (ImageContext->Machine != EFI_IMAGE_MACHINE_IA32 && \
-  ImageContext->Machine != EFI_IMAGE_MACHINE_X64  && \
-  ImageContext->Machine != EFI_IMAGE_MACHINE_ARMT && \
-  ImageContext->Machine != EFI_IMAGE_MACHINE_EBC  && \
-  ImageContext->Machine != EFI_IMAGE_MACHINE_AARCH64 && \
-  ImageContext->Machine != EFI_IMAGE_MACHINE_RISCV64 && \
-  ImageContext->Machine != EFI_IMAGE_MACHINE_LOONGARCH64) {
+  if (ImageContext->Machine != IMAGE_FILE_MACHINE_I386 && \
+  ImageContext->Machine != IMAGE_FILE_MACHINE_X64  && \
+  ImageContext->Machine != IMAGE_FILE_MACHINE_ARMTHUMB_MIXED && \
+  ImageContext->Machine != IMAGE_FILE_MACHINE_EBC  && \
+  ImageContext->Machine != IMAGE_FILE_MACHINE_ARM64 && \
+  ImageContext->Machine != IMAGE_FILE_MACHINE_RISCV64 && \
+  ImageContext->Machine != IMAGE_FILE_MACHINE_LOONGARCH64) {
 //
 // unsupported PeImage machine type
 //
@@ -801,16 +801,16 @@ Routine Description:
 
   default:
 switch (MachineType) {
-case EFI_IMAGE_MACHINE_IA32:
+case IMAGE_FILE_MACHINE_I386:
   Status = PeCoffLoaderRelocateIa32Image (Reloc, Fixup, , 
Adjust);
   break;
-case EFI_IMAGE_MACHINE_ARMT:
+case IMAGE_FILE_MACHINE_ARMTHUMB_MIXED:
   Status = PeCoffLoaderRelocateArmImage (, Fixup, , 
Adjust);
   break;
-case EFI_IMAGE_MACHINE_RISCV64:
+case IMAGE_FILE_MACHINE_RISCV64:
   Status = PeCoffLoaderRelocateRiscVImage (Reloc, Fixup, , 
Adjust);
   break;
-case EFI_IMAGE_MACHINE_LOONGARCH64:
+case IMAGE_FILE_MACHINE_LOONGARCH64:
   Status = PeCoffLoaderRelocateLoongArch64Image (Reloc, Fixup, 
, Adjust);
   break;
 default:
@@ -1305,14 +1305,14 @@ PeCoffLoaderGetPdbPointer (
 //   generate PE32+ image with PE32 Magic.
 //
 switch (Hdr.Pe32->FileHeader.Machine) {
-case EFI_IMAGE_MACHINE_IA32:
-case EFI_IMAGE_MACHINE_ARMT:
+case IMAGE_FILE_MACHINE_I386:
+case IMAGE_FILE_MACHINE_ARMTHUMB_MIXED:
   //
   // Assume PE32 image with IA32 Machine field.
   //
   Magic = EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC;
   break;
-case EFI_IMAGE_MACHINE_X64:
+case IMAGE_FILE_MACHINE_X64:
   //
   // Assume PE32+ image with X64 Machine field
   //
diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c 
b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
index c8d5cac8e26e..f466324d6192 100644
--- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
+++ 

[edk2-devel] [PATCH 4/8] MdePkg/PeImage.h: add bits from BaseTools version

[Gerd Hoffmann]

The BaseTools and MdePkg versions of PeImage.h diverged over time,
add some missing bits to the MdePkg header file in preparation for
removing the BaseTools version.

Signed-off-by: Gerd Hoffmann 
---
 MdePkg/Include/IndustryStandard/PeImage.h | 31 +++
 1 file changed, 31 insertions(+)

diff --git a/MdePkg/Include/IndustryStandard/PeImage.h 
b/MdePkg/Include/IndustryStandard/PeImage.h
index dd4cc25483bc..c232248cdc31 100644
--- a/MdePkg/Include/IndustryStandard/PeImage.h
+++ b/MdePkg/Include/IndustryStandard/PeImage.h
@@ -101,6 +101,7 @@ typedef struct {
 #define EFI_IMAGE_FILE_EXECUTABLE_IMAGE BIT1 ///< 0x0002  File is 
executable  (i.e. no unresolved externel references).
 #define EFI_IMAGE_FILE_LINE_NUMS_STRIPPED   BIT2 ///< 0x0004  Line numbers 
stripped from file.
 #define EFI_IMAGE_FILE_LOCAL_SYMS_STRIPPED  BIT3 ///< 0x0008  Local 
symbols stripped from file.
+#define EFI_IMAGE_FILE_LARGE_ADDRESS_AWARE  BIT5 ///< 0x0020  Supports 
addresses > 2-GB
 #define EFI_IMAGE_FILE_BYTES_REVERSED_LOBIT7 ///< 0x0080  Bytes of 
machine word are reversed.
 #define EFI_IMAGE_FILE_32BIT_MACHINEBIT8 ///< 0x0100  32 bit word 
machine.
 #define EFI_IMAGE_FILE_DEBUG_STRIPPED   BIT9 ///< 0x0200  Debugging 
info stripped from file in .DBG file.
@@ -577,6 +578,13 @@ typedef struct {
   UINT32AddressOfNameOrdinals;
 } EFI_IMAGE_EXPORT_DIRECTORY;
 
+//
+// Based export types.
+//
+#define EFI_IMAGE_EXPORT_ORDINAL_BASE  1
+#define EFI_IMAGE_EXPORT_ADDR_SIZE 4
+#define EFI_IMAGE_EXPORT_ORDINAL_SIZE  2
+
 ///
 /// Hint/Name Table.
 ///
@@ -669,6 +677,29 @@ typedef struct {
   //
 } EFI_IMAGE_DEBUG_CODEVIEW_MTOC_ENTRY;
 
+// avoid conflict with windows header files
+#ifndef RUNTIME_FUNCTION_INDIRECT
+
+//
+// .pdata entries for X64
+//
+typedef struct {
+  UINT32FunctionStartAddress;
+  UINT32FunctionEndAddress;
+  UINT32UnwindInfoAddress;
+} RUNTIME_FUNCTION;
+
+#endif
+
+typedef struct {
+  UINT8Version : 3;
+  UINT8Flags   : 5;
+  UINT8SizeOfProlog;
+  UINT8CountOfUnwindCodes;
+  UINT8FrameRegister   : 4;
+  UINT8FrameRegisterOffset : 4;
+} UNWIND_INFO;
+
 ///
 /// Resource format.
 ///
-- 
2.39.2



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[edk2-devel] [PATCH 3/8] BaseTools: remove duplicate includes: IndustryStandard/Acpi*.h

[Gerd Hoffmann]

Use the MdePkg version instead of maintaining a copy in BaseTools.

Signed-off-by: Gerd Hoffmann 
---
 .../Source/C/Include/IndustryStandard/Acpi.h  | 117 ---
 .../C/Include/IndustryStandard/Acpi1_0.h  | 285 
 .../C/Include/IndustryStandard/Acpi2_0.h  | 520 --
 .../C/Include/IndustryStandard/Acpi3_0.h  | 668 --
 .../Source/C/Include/Protocol/DevicePath.h|   2 +-
 BaseTools/Source/C/GenFw/GenFw.c  |   8 +-
 BaseTools/Source/C/Makefiles/header.makefile  |   1 +
 BaseTools/Source/C/Makefiles/ms.common|   1 +
 8 files changed, 7 insertions(+), 1595 deletions(-)
 delete mode 100644 BaseTools/Source/C/Include/IndustryStandard/Acpi.h
 delete mode 100644 BaseTools/Source/C/Include/IndustryStandard/Acpi1_0.h
 delete mode 100644 BaseTools/Source/C/Include/IndustryStandard/Acpi2_0.h
 delete mode 100644 BaseTools/Source/C/Include/IndustryStandard/Acpi3_0.h

diff --git a/BaseTools/Source/C/Include/IndustryStandard/Acpi.h 
b/BaseTools/Source/C/Include/IndustryStandard/Acpi.h
deleted file mode 100644
index 3516478ce400..
--- a/BaseTools/Source/C/Include/IndustryStandard/Acpi.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/** @file
-  This file contains some basic ACPI definitions that are consumed by drivers
-  that do not care about ACPI versions.
-
-  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
-
-  SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef _ACPI_H_
-#define _ACPI_H_
-
-//
-// Common table header, this prefaces all ACPI tables, including FACS, but
-// excluding the RSD PTR structure
-//
-typedef struct {
-  UINT32  Signature;
-  UINT32  Length;
-} EFI_ACPI_COMMON_HEADER;
-
-//
-// Common ACPI description table header.  This structure prefaces most ACPI 
tables.
-//
-#pragma pack(1)
-
-typedef struct {
-  UINT32  Signature;
-  UINT32  Length;
-  UINT8   Revision;
-  UINT8   Checksum;
-  UINT8   OemId[6];
-  UINT64  OemTableId;
-  UINT32  OemRevision;
-  UINT32  CreatorId;
-  UINT32  CreatorRevision;
-} EFI_ACPI_DESCRIPTION_HEADER;
-
-#pragma pack()
-//
-// Define for Pci Host Bridge Resource Allocation
-//
-#define ACPI_ADDRESS_SPACE_DESCRIPTOR 0x8A
-#define ACPI_END_TAG_DESCRIPTOR   0x79
-
-#define ACPI_ADDRESS_SPACE_TYPE_MEM   0x00
-#define ACPI_ADDRESS_SPACE_TYPE_IO0x01
-#define ACPI_ADDRESS_SPACE_TYPE_BUS   0x02
-
-//
-// Power Management Timer frequency is fixed at 3.579545MHz
-//
-#define ACPI_TIMER_FREQUENCY   3579545
-
-//
-// Make sure structures match spec
-//
-#pragma pack(1)
-
-typedef struct {
-  UINT8   Desc;
-  UINT16  Len;
-  UINT8   ResType;
-  UINT8   GenFlag;
-  UINT8   SpecificFlag;
-  UINT64  AddrSpaceGranularity;
-  UINT64  AddrRangeMin;
-  UINT64  AddrRangeMax;
-  UINT64  AddrTranslationOffset;
-  UINT64  AddrLen;
-} EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR;
-
-typedef struct {
-  UINT8 Desc;
-  UINT8 Checksum;
-} EFI_ACPI_END_TAG_DESCRIPTOR;
-
-//
-// General use definitions
-//
-#define EFI_ACPI_RESERVED_BYTE  0x00
-#define EFI_ACPI_RESERVED_WORD  0x
-#define EFI_ACPI_RESERVED_DWORD 0x
-#define EFI_ACPI_RESERVED_QWORD 0x
-
-//
-// Resource Type Specific Flags
-// Ref ACPI specification 6.4.3.5.5
-//
-// Bit [0]: Write Status, _RW
-//
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_WRITE(1 << 
0)
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_ONLY (0 << 
0)
-//
-// Bit [2:1]  : Memory Attributes, _MEM
-//
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_NON_CACHEABLE (0 << 
1)
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE (1 << 
1)
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_WRITE_COMBINING (2 << 
1)
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE(3 << 
1)
-//
-// Bit [4:3]  : Memory Attributes, _MTP
-//
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_MEMORY  (0 << 
3)
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_RESERVED(1 << 
3)
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_ACPI(2 << 
3)
-#define EFI_APCI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_NVS (3 << 
3)
-//
-// Bit [5]: Memory to I/O Translation, _TTP
-//
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_TRANSLATION  (1 << 
5)
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_STATIC   (0 << 
5)
-
-#pragma pack()
-
-#endif
diff --git a/BaseTools/Source/C/Include/IndustryStandard/Acpi1_0.h 
b/BaseTools/Source/C/Include/IndustryStandard/Acpi1_0.h
deleted file mode 100644
index 62bd9f477e0b..
--- a/BaseTools/Source/C/Include/IndustryStandard/Acpi1_0.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/** @file
-  ACPI 1.0b definitions from the ACPI Specification, revision 1.0b
-
-  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
-
-  SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef _ACPI_1_0_H_
-#define _ACPI_1_0_H_
-
-#include 

[edk2-devel] [PATCH 1/8] BaseTools: remove WinNtInclude.h

[Gerd Hoffmann]

Appears to be a relic for ancient windows / compiler versions,
windows builds in CI work just fine without it.

Signed-off-by: Gerd Hoffmann 
---
 BaseTools/Source/C/Common/WinNtInclude.h| 66 -
 BaseTools/Source/C/GenFv/GenFvInternalLib.c |  1 -
 BaseTools/Source/C/GenFw/Elf32Convert.c |  2 -
 BaseTools/Source/C/GenFw/Elf64Convert.c |  2 -
 BaseTools/Source/C/GenFw/ElfConvert.c   |  2 -
 BaseTools/Source/C/GenFw/GenFw.c|  2 -
 6 files changed, 75 deletions(-)
 delete mode 100644 BaseTools/Source/C/Common/WinNtInclude.h

diff --git a/BaseTools/Source/C/Common/WinNtInclude.h 
b/BaseTools/Source/C/Common/WinNtInclude.h
deleted file mode 100644
index 181e6ac33370..
--- a/BaseTools/Source/C/Common/WinNtInclude.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/** @file
-Include file for the WinNt Library
-
-Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef __WIN_NT_INCLUDE_H__
-#define __WIN_NT_INCLUDE_H__
-
-#define GUID  _WINNT_DUP_GUID_
-#define _LIST_ENTRY  _WINNT_DUP_LIST_ENTRY_FORWARD
-#define LIST_ENTRY   _WINNT_DUP_LIST_ENTRY
-
-#if (_MSC_VER < 1800)
-#define InterlockedIncrement _WINNT_DUP_InterlockedIncrement
-#define InterlockedDecrement _WINNT_DUP_InterlockedDecrement
-#define InterlockedCompareExchange64 _WINNT_DUP_InterlockedCompareExchange64
-#endif
-
-#undef UNALIGNED
-#undef CONST
-#undef VOID
-
-#ifndef __GNUC__
-#include "windows.h"
-
-//
-// Win32 include files do not compile clean with /W4, so we use the warning
-// pragma to suppress the warnings for Win32 only. This way our code can still
-// compile at /W4 (highest warning level) with /WX (warnings cause build
-// errors).
-//
-#pragma warning(disable : 4115)
-#pragma warning(disable : 4201)
-#pragma warning(disable : 4214)
-#pragma warning(disable : 4028)
-#pragma warning(disable : 4133)
-
-//
-// Set the warnings back on as the EFI code must be /W4.
-//
-#pragma warning(default : 4115)
-#pragma warning(default : 4201)
-#pragma warning(default : 4214)
-
-#endif
-
-#undef GUID
-#undef _LIST_ENTRY
-#undef LIST_ENTRY
-#undef InterlockedIncrement
-#undef InterlockedDecrement
-#undef InterlockedCompareExchange64
-#undef InterlockedCompareExchangePointer
-
-#define VOID void
-
-//
-// Prevent collisions with Windows API name macros that deal with Unicode/Not 
issues
-//
-#undef LoadImage
-#undef CreateEvent
-
-#endif
diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c 
b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
index 2df7182f8b52..c8d5cac8e26e 100644
--- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
+++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
@@ -25,7 +25,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 
 #include 
 
-#include "WinNtInclude.h"
 #include "GenFvInternalLib.h"
 #include "FvLib.h"
 #include "PeCoffLib.h"
diff --git a/BaseTools/Source/C/GenFw/Elf32Convert.c 
b/BaseTools/Source/C/GenFw/Elf32Convert.c
index 87d7f133f132..e9fb3593a91b 100644
--- a/BaseTools/Source/C/GenFw/Elf32Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf32Convert.c
@@ -9,8 +9,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
-#include "WinNtInclude.h"
-
 #ifndef __GNUC__
 #include 
 #include 
diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c 
b/BaseTools/Source/C/GenFw/Elf64Convert.c
index 8b50774beb1e..2078ff42002f 100644
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -10,8 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
-#include "WinNtInclude.h"
-
 #ifndef __GNUC__
 #include 
 #include 
diff --git a/BaseTools/Source/C/GenFw/ElfConvert.c 
b/BaseTools/Source/C/GenFw/ElfConvert.c
index be98544056ec..3205f61494b6 100644
--- a/BaseTools/Source/C/GenFw/ElfConvert.c
+++ b/BaseTools/Source/C/GenFw/ElfConvert.c
@@ -7,8 +7,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
-#include "WinNtInclude.h"
-
 #ifndef __GNUC__
 #include 
 #include 
diff --git a/BaseTools/Source/C/GenFw/GenFw.c b/BaseTools/Source/C/GenFw/GenFw.c
index 6f61f16788cd..3f79732a9160 100644
--- a/BaseTools/Source/C/GenFw/GenFw.c
+++ b/BaseTools/Source/C/GenFw/GenFw.c
@@ -6,8 +6,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
-#include "WinNtInclude.h"
-
 #ifndef __GNUC__
 #include 
 #include 
-- 
2.39.2



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[edk2-devel] [PATCH 2/8] BaseTools: remove duplicate includes: /ProcessorBind.h

[Gerd Hoffmann]

Use the MdePkg version instead of maintaining a copy in BaseTools.

Signed-off-by: Gerd Hoffmann 
---
 .../Source/C/Include/AArch64/ProcessorBind.h  | 148 --
 .../Source/C/Include/Arm/ProcessorBind.h  | 147 --
 .../Source/C/Include/Ia32/ProcessorBind.h | 155 ---
 .../C/Include/LoongArch64/ProcessorBind.h |  80 
 .../Source/C/Include/RiscV64/ProcessorBind.h  |  85 
 .../Source/C/Include/X64/ProcessorBind.h  | 183 --
 BaseTools/Source/C/Common/Decompress.c|   1 +
 BaseTools/Source/C/Makefiles/header.makefile  |  14 +-
 BaseTools/Source/C/Makefiles/ms.common|  12 +-
 9 files changed, 19 insertions(+), 806 deletions(-)
 delete mode 100644 BaseTools/Source/C/Include/AArch64/ProcessorBind.h
 delete mode 100644 BaseTools/Source/C/Include/Arm/ProcessorBind.h
 delete mode 100644 BaseTools/Source/C/Include/Ia32/ProcessorBind.h
 delete mode 100644 BaseTools/Source/C/Include/LoongArch64/ProcessorBind.h
 delete mode 100644 BaseTools/Source/C/Include/RiscV64/ProcessorBind.h
 delete mode 100644 BaseTools/Source/C/Include/X64/ProcessorBind.h

diff --git a/BaseTools/Source/C/Include/AArch64/ProcessorBind.h 
b/BaseTools/Source/C/Include/AArch64/ProcessorBind.h
deleted file mode 100644
index dfa725b2e363..
--- a/BaseTools/Source/C/Include/AArch64/ProcessorBind.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/** @file
-  Processor or Compiler specific defines and types for AArch64.
-
-  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
-  Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
-  Portions copyright (c) 2013, ARM Ltd. All rights reserved.
-
-  SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef __PROCESSOR_BIND_H__
-#define __PROCESSOR_BIND_H__
-
-///
-/// Define the processor type so other code can make processor based choices
-///
-#define MDE_CPU_AARCH64
-
-//
-// Make sure we are using the correct packing rules per EFI specification
-//
-#ifndef __GNUC__
-#pragma pack()
-#endif
-
-#if _MSC_EXTENSIONS
-  //
-  // use Microsoft* C compiler dependent integer width types
-  //
-  typedef unsigned __int64UINT64;
-  typedef __int64 INT64;
-  typedef unsigned __int32UINT32;
-  typedef __int32 INT32;
-  typedef unsigned short  UINT16;
-  typedef unsigned short  CHAR16;
-  typedef short   INT16;
-  typedef unsigned char   BOOLEAN;
-  typedef unsigned char   UINT8;
-  typedef charCHAR8;
-  typedef signed char INT8;
-#else
-  //
-  // Use ANSI C 2000 stdint.h integer width declarations
-  //
-  #include 
-  typedef uint8_t   BOOLEAN;
-  typedef int8_tINT8;
-  typedef uint8_t   UINT8;
-  typedef int16_t   INT16;
-  typedef uint16_t  UINT16;
-  typedef int32_t   INT32;
-  typedef uint32_t  UINT32;
-  typedef int64_t   INT64;
-  typedef uint64_t  UINT64;
-  typedef char  CHAR8;
-  typedef uint16_t  CHAR16;
-
-#endif
-
-///
-/// Unsigned value of native width.  (4 bytes on supported 32-bit processor 
instructions,
-/// 8 bytes on supported 64-bit processor instructions)
-///
-typedef UINT64  UINTN;
-
-///
-/// Signed value of native width.  (4 bytes on supported 32-bit processor 
instructions,
-/// 8 bytes on supported 64-bit processor instructions)
-///
-typedef INT64   INTN;
-
-//
-// Processor specific defines
-//
-
-///
-/// A value of native width with the highest bit set.
-///
-#define MAX_BIT  0x8000
-
-///
-/// A value of native width with the two highest bits set.
-///
-#define MAX_2_BITS   0xC000
-
-///
-/// The stack alignment required for AARCH64
-///
-#define CPU_STACK_ALIGNMENT  16
-
-//
-// Modifier to ensure that all protocol member functions and EFI intrinsics
-// use the correct C calling convention. All protocol member functions and
-// EFI intrinsics are required to modify their member functions with EFIAPI.
-//
-#define EFIAPI
-
-#if defined(__GNUC__)
-  ///
-  /// For GNU assembly code, .global or .globl can declare global symbols.
-  /// Define this macro to unify the usage.
-  ///
-  #define ASM_GLOBAL .globl
-
-  #if !defined(__APPLE__)
-///
-/// ARM EABI defines that the linker should not manipulate call relocations
-/// (do bl/blx conversion) unless the target symbol has function type.
-/// CodeSourcery 2010.09 started requiring the .type to function properly
-///
-#define INTERWORK_FUNC(func__)   .type ASM_PFX(func__), %function
-
-#define GCC_ASM_EXPORT(func__)  \
- .global  _CONCATENATE (__USER_LABEL_PREFIX__, func__);\
- .type ASM_PFX(func__), %function
-
-#define GCC_ASM_IMPORT(func__)  \
- .extern  _CONCATENATE (__USER_LABEL_PREFIX__, func__)
-
-  #else
-//
-// .type not supported by Apple Xcode tools
-//
-#define INTERWORK_FUNC(func__)
-
-#define GCC_ASM_EXPORT(func__)  \
- .globl  _CONCATENATE (__USER_LABEL_PREFIX__, func__)\

[edk2-devel] [PATCH 5/8] BaseTools: drop IMAGE_FILE_MACHINE_ARM hacks

[Gerd Hoffmann]

The #define for IMAGE_FILE_MACHINE_ARM is not present in MdePkg,
this looks like a relic not used any more.  Remove.

Signed-off-by: Gerd Hoffmann 
---
 BaseTools/Source/C/Common/BasePeCoff.c | 23 ---
 1 file changed, 4 insertions(+), 19 deletions(-)

diff --git a/BaseTools/Source/C/Common/BasePeCoff.c 
b/BaseTools/Source/C/Common/BasePeCoff.c
index 30400d1341dc..78ef072bc354 100644
--- a/BaseTools/Source/C/Common/BasePeCoff.c
+++ b/BaseTools/Source/C/Common/BasePeCoff.c
@@ -195,25 +195,10 @@ Routine Description:
   ImageContext->Machine != EFI_IMAGE_MACHINE_AARCH64 && \
   ImageContext->Machine != EFI_IMAGE_MACHINE_RISCV64 && \
   ImageContext->Machine != EFI_IMAGE_MACHINE_LOONGARCH64) {
-if (ImageContext->Machine == IMAGE_FILE_MACHINE_ARM) {
-  //
-  // There are two types of ARM images. Pure ARM and ARM/Thumb.
-  // If we see the ARM say it is the ARM/Thumb so there is only
-  // a single machine type we need to check for ARM.
-  //
-  ImageContext->Machine = EFI_IMAGE_MACHINE_ARMT;
-  if (ImageContext->IsTeImage == FALSE) {
-PeHdr->Pe32.FileHeader.Machine = ImageContext->Machine;
-  } else {
-TeHdr->Machine = ImageContext->Machine;
-  }
-
-} else {
-  //
-  // unsupported PeImage machine type
-  //
-  return RETURN_UNSUPPORTED;
-}
+//
+// unsupported PeImage machine type
+//
+return RETURN_UNSUPPORTED;
   }
 
   //
-- 
2.39.2



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[edk2-devel] [PATCH 0/8] BaseTools: remove duplicate includes.

[Gerd Hoffmann]

There is alot of code duplication between BaseTools and MdePkg (and also
MdeModulePkg).  This patch series starts reducing this by removing some
header files.  BaseTools are switched over to use the include files in
MdePkg instead.  It also cleans up some (apparently) obsolete code and
adapts BaseTools code in a few places to work with the MdePkg version of
the include files.

take care,
  Gerd

Gerd Hoffmann (8):
  BaseTools: remove WinNtInclude.h
  BaseTools: remove duplicate includes: /ProcessorBind.h
  BaseTools: remove duplicate includes: IndustryStandard/Acpi*.h
  MdePkg/PeImage.h: add bits from BaseTools version
  BaseTools: drop IMAGE_FILE_MACHINE_ARM hacks
  BaseTools: switch from EFI_IMAGE_MACHINE_* to IMAGE_FILE_MACHINE_*
  BaseTools: remove duplicate includes: IndustryStandard/PeImage.h
  BaseTools: remove duplicate includes: IndustryStandard/*.h

 BaseTools/Source/C/Common/WinNtInclude.h  |  66 --
 BaseTools/Source/C/EfiRom/EfiRom.h|  14 +-
 .../Source/C/Include/AArch64/ProcessorBind.h  | 148 
 .../Source/C/Include/Arm/ProcessorBind.h  | 147 
 .../Source/C/Include/Ia32/ProcessorBind.h | 155 
 .../Source/C/Include/IndustryStandard/Acpi.h  | 117 ---
 .../C/Include/IndustryStandard/Acpi1_0.h  | 285 ---
 .../C/Include/IndustryStandard/Acpi2_0.h  | 520 
 .../C/Include/IndustryStandard/Acpi3_0.h  | 668 ---
 .../C/Include/IndustryStandard/Bluetooth.h|  56 --
 .../C/Include/IndustryStandard/EfiPci.h   |  51 --
 ...emoryMappedConfigurationSpaceAccessTable.h |  39 -
 .../C/Include/IndustryStandard/PeImage.h  | 778 --
 .../Source/C/Include/IndustryStandard/pci22.h | 536 
 .../Source/C/Include/IndustryStandard/pci23.h |  18 -
 .../Source/C/Include/IndustryStandard/pci30.h |  38 -
 .../C/Include/LoongArch64/ProcessorBind.h |  80 --
 .../Source/C/Include/Protocol/DevicePath.h|   2 +-
 .../Source/C/Include/RiscV64/ProcessorBind.h  |  85 --
 .../Source/C/Include/X64/ProcessorBind.h  | 183 
 MdePkg/Include/IndustryStandard/PeImage.h |  31 +
 BaseTools/Source/C/Common/BasePeCoff.c|  51 +-
 BaseTools/Source/C/Common/Decompress.c|   1 +
 BaseTools/Source/C/GenFv/GenFvInternalLib.c   |  43 +-
 BaseTools/Source/C/GenFw/Elf32Convert.c   |   8 +-
 BaseTools/Source/C/GenFw/Elf64Convert.c   |  12 +-
 BaseTools/Source/C/GenFw/ElfConvert.c |   2 -
 BaseTools/Source/C/GenFw/GenFw.c  |  18 +-
 BaseTools/Source/C/Makefiles/header.makefile  |  15 +-
 BaseTools/Source/C/Makefiles/ms.common|  13 +-
 30 files changed, 112 insertions(+), 4068 deletions(-)
 delete mode 100644 BaseTools/Source/C/Common/WinNtInclude.h
 delete mode 100644 BaseTools/Source/C/Include/AArch64/ProcessorBind.h
 delete mode 100644 BaseTools/Source/C/Include/Arm/ProcessorBind.h
 delete mode 100644 BaseTools/Source/C/Include/Ia32/ProcessorBind.h
 delete mode 100644 BaseTools/Source/C/Include/IndustryStandard/Acpi.h
 delete mode 100644 BaseTools/Source/C/Include/IndustryStandard/Acpi1_0.h
 delete mode 100644 BaseTools/Source/C/Include/IndustryStandard/Acpi2_0.h
 delete mode 100644 BaseTools/Source/C/Include/IndustryStandard/Acpi3_0.h
 delete mode 100644 BaseTools/Source/C/Include/IndustryStandard/Bluetooth.h
 delete mode 100644 BaseTools/Source/C/Include/IndustryStandard/EfiPci.h
 delete mode 100644 
BaseTools/Source/C/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h
 delete mode 100644 BaseTools/Source/C/Include/IndustryStandard/PeImage.h
 delete mode 100644 BaseTools/Source/C/Include/IndustryStandard/pci22.h
 delete mode 100644 BaseTools/Source/C/Include/IndustryStandard/pci23.h
 delete mode 100644 BaseTools/Source/C/Include/IndustryStandard/pci30.h
 delete mode 100644 BaseTools/Source/C/Include/LoongArch64/ProcessorBind.h
 delete mode 100644 BaseTools/Source/C/Include/RiscV64/ProcessorBind.h
 delete mode 100644 BaseTools/Source/C/Include/X64/ProcessorBind.h

-- 
2.39.2



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[edk2-devel] [PATCH 1/1] OvmfPkg/RiscVVirt: Support multiple reserved memory ranges

[Sunil V L]

M-mode firmware ranges should not be used by EDK2/OS.
Currently, we search for mmode_resv0 node in FDT and mark it as the
reserved memory in EFI memory map. However, if there are multiple
M-mode firmware ranges, then this will miss those extra ranges
allowing the OS to access the memory and hit a fault.

This issue is exposed since recent opensbi started creating
two ranges for text and data.

Fix this by searching for all reserved memory nodes and marking
them as reserved in the EFI memory map.

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Andrei Warkentin 
Signed-off-by: Sunil V L 
---
 OvmfPkg/RiscVVirt/Sec/Memory.c | 208 +
 1 file changed, 136 insertions(+), 72 deletions(-)

diff --git a/OvmfPkg/RiscVVirt/Sec/Memory.c b/OvmfPkg/RiscVVirt/Sec/Memory.c
index 70935b07b56b..aeae361ebe90 100644
--- a/OvmfPkg/RiscVVirt/Sec/Memory.c
+++ b/OvmfPkg/RiscVVirt/Sec/Memory.c
@@ -38,31 +38,6 @@ BuildMemoryTypeInformationHob (
   VOID
   );
 
-/**
-  Build reserved memory range resource HOB.
-
-  @param  MemoryBase Reserved memory range base address.
-  @param  MemorySize Reserved memory range size.
-
-**/
-STATIC
-VOID
-AddReservedMemoryBaseSizeHob (
-  EFI_PHYSICAL_ADDRESS  MemoryBase,
-  UINT64MemorySize
-  )
-{
-  BuildResourceDescriptorHob (
-EFI_RESOURCE_MEMORY_RESERVED,
-EFI_RESOURCE_ATTRIBUTE_PRESENT |
-EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
-EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
-EFI_RESOURCE_ATTRIBUTE_TESTED,
-MemoryBase,
-MemorySize
-);
-}
-
 /**
   Create memory range resource HOB using the memory base
   address and size.
@@ -133,38 +108,143 @@ STATIC
 VOID
 InitializeRamRegions (
   EFI_PHYSICAL_ADDRESS  SystemMemoryBase,
-  UINT64SystemMemorySize,
-  EFI_PHYSICAL_ADDRESS  MmodeResvBase,
-  UINT64MmodeResvSize
+  UINT64SystemMemorySize
   )
 {
-  /*
-   * M-mode FW can be loaded anywhere in memory but should not overlap
-   * with the EDK2. This can happen if some other boot code loads the
-   * M-mode firmware.
-   *
-   * The M-mode firmware memory should be marked as reserved memory
-   * so that OS doesn't use it.
-   */
-  DEBUG ((
-DEBUG_INFO,
-"%a: M-mode FW Memory Start:0x%lx End:0x%lx\n",
-__FUNCTION__,
-MmodeResvBase,
-MmodeResvBase + MmodeResvSize
-));
-  AddReservedMemoryBaseSizeHob (MmodeResvBase, MmodeResvSize);
-
-  if (MmodeResvBase > SystemMemoryBase) {
-AddMemoryRangeHob (SystemMemoryBase, MmodeResvBase);
-  }
-
   AddMemoryRangeHob (
-MmodeResvBase + MmodeResvSize,
+SystemMemoryBase,
 SystemMemoryBase + SystemMemorySize
 );
 }
 
+STATIC
+INT32
+GetNumCells (
+  VOID *Fdt,
+  INT32Node,
+  CONST CHAR8  *Name
+  )
+{
+  CONST INT32  *Prop;
+  INT32Len;
+  UINT32   Val;
+
+  Prop = fdt_getprop (Fdt, Node, Name, );
+  if (Prop == NULL) {
+return Len;
+  }
+
+  if (Len != sizeof (*Prop)) {
+return -FDT_ERR_BADNCELLS;
+  }
+
+  Val = fdt32_to_cpu (*Prop);
+  if (Val > FDT_MAX_NCELLS) {
+return -FDT_ERR_BADNCELLS;
+  }
+
+  return (INT32)Val;
+}
+
+/** Mark reserved memory ranges in the EFI memory map
+ *
+ * The M-mode firmware ranges should not be used by the
+ * EDK2/OS. These ranges are passed via device tree using reserved
+ * memory nodes. Parse the DT and mark those ranges as of
+ * type EfiReservedMemoryType.
+ *
+ * NOTE: Device Tree spec section 3.5.4 says reserved memory regions
+ * without no-map property should be installed as EfiBootServicesData.
+ * As per UEFI spec, memory of type EfiBootServicesData can be used
+ * by the OS after ExitBootServices().
+ * This is not an issue for DT since OS can parse the DT also along
+ * with EFI memory map and avoid using these ranges. But with ACPI,
+ * there is no such mechanisms possible.
+ * Since EDK2 needs to support both DT and ACPI, we are deviating
+ * from the DT spec and marking all reserved memory ranges as
+ * EfiReservedMemoryType itself irrespective of no-map.
+ *
+ * @param FdtPointer Pointer to FDT
+ *
+**/
+STATIC
+VOID
+AddReservedMemoryMap (
+  VOID  *FdtPointer
+  )
+{
+  CONST INT32   *RegProp;
+  INT32 Node;
+  INT32 SubNode;
+  INT32 Len;
+  EFI_PHYSICAL_ADDRESS  Addr;
+  UINT64Size;
+  INTN  NumRsv, i;
+  INT32 NumAddrCells, NumSizeCells;
+
+  NumRsv = fdt_num_mem_rsv (FdtPointer);
+
+  /* Look for an existing entry and add it to the efi mem map. */
+  for (i = 0; i < NumRsv; i++) {
+if (fdt_get_mem_rsv (FdtPointer, i, , ) != 0) {
+  continue;
+}
+
+BuildMemoryAllocationHob (
+  Addr,
+  Size,
+  EfiReservedMemoryType
+  );
+  }
+
+  /* process reserved-memory */
+  Node = fdt_subnode_offset (FdtPointer, 0, "reserved-memory");
+  if (Node >= 0) {
+NumAddrCells = GetNumCells (FdtPointer, Node, "#address-cells");
+if 

Re: [edk2-devel] [PATCH 1/1] OvmfPkg/PlatformBootManagerLib: use utf8 for the serial console.

[Ard Biesheuvel]

On Thu, 23 Mar 2023 at 09:20, Gerd Hoffmann  wrote:
>
> On Wed, Mar 22, 2023 at 10:31:32AM -0600, Rebecca Cran wrote:
> > On 3/22/23 10:20 AM, Ard Biesheuvel wrote:
> > > On Fri, 17 Mar 2023 at 13:19, Gerd Hoffmann  wrote:
> > > > Time to leave behind relics from the last century and arrive in the
> > > > modern world.  Drop PC-ANSI Terminal Type for the serial console, use
> > > > UTF-8 instead.
> > > >
> > > > Signed-off-by: Gerd Hoffmann 
> > > No objections here but how will I be able to observe the difference?
> >
> > I'm not sure if it's as simple as this or if it depends on the terminal,
> > TERM setting etc.,
>
> It does.  It depends on the locale the terminal application is
> running in.  These days that is a utf-8 locale in 99% of the cases,
> i.e. "de_DE.UTF-8" for me.
>
> > but I saw a difference when I opened the UiApp and opened
> > the drop-down "Select Language".
> >
> > Before the patch, it showed "Fran?ais", and after, "Français".
>
> Yes, essentially everything which is not ascii shows correct now,
> including the line-drawing characters which you can see in alot
> of places in UiApp on the serial console.
>


Merged as #4164 - thanks


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Re: [edk2-devel] [Patch V4 00/21] Fix issues in CpuPageTableLib

[duntan]

Thank you Gerd!

Thanks,
Dun

-Original Message-
From: Gerd Hoffmann  
Sent: Thursday, March 23, 2023 5:13 PM
To: devel@edk2.groups.io; Tan, Dun 
Subject: Re: [edk2-devel] [Patch V4 00/21] Fix issues in CpuPageTableLib

On Thu, Mar 23, 2023 at 03:40:36PM +0800, duntan wrote:
> In the V4 atch set
> 1. In the patch "UefiCpuPkg/MpInitLib: Add code to initialize MapMask", add 
> code to set MapMask to MAX_UINT64 to fix the boot failure tested by Gred.
> 2. Add patches to enable PAE paing in CpuPageTable Lib and add random 
> test for PAE paging 3. Add patch to reduce the number of random test 
> since CI may timeout 4. Modify the patch to fix non-1:1 mapping issue

Tested-by: Gerd Hoffmann 
Acked-by: Gerd Hoffmann 



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Re: [edk2-devel] [Patch V4 00/21] Fix issues in CpuPageTableLib

[Gerd Hoffmann]

On Thu, Mar 23, 2023 at 03:40:36PM +0800, duntan wrote:
> In the V4 atch set
> 1. In the patch "UefiCpuPkg/MpInitLib: Add code to initialize MapMask", add 
> code to set MapMask to MAX_UINT64 to fix the boot failure tested by Gred.
> 2. Add patches to enable PAE paing in CpuPageTable Lib and add random test 
> for PAE paging
> 3. Add patch to reduce the number of random test since CI may timeout
> 4. Modify the patch to fix non-1:1 mapping issue

Tested-by: Gerd Hoffmann 
Acked-by: Gerd Hoffmann 



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Re: [edk2-devel] [PATCH 3/9] BaseTools: Update CLANGDWARF toolchain and remove CLANG35 and CLANG38

[Ard Biesheuvel]

On Thu, 23 Mar 2023 at 02:30, Rebecca Cran  wrote:
>
> On 3/22/23 5:49 AM, Ard Biesheuvel wrote:
>
> >
> > The reason I added CLANG3x support for ARM in the past is to ensure
> > compatibility with the ARM proprietary, Clang based toolchain. At the
> > time, we went with GNU ld, but I would actually prefer if we could
> > make this work with LLD as well.
>
> Just to confirm, I'll keep lld for X64 and IA32, but I won't add
> -fuse-ld=lld for ARM or AARCH64 since none of the toolchain definitions
> currently do so.
>
>
> The problem with trying to use lld for aarch64 is the following error:
>
>
> GenFw: ERROR 3000: Invalid
>WriteSections64():
> /home/bcran/uefi/edk2/Build/ArmVirtQemu-AARCH64/RELEASE_CLANGDWARF/AARCH64/ArmVirtPkg/MemoryInitPei/MemoryInitPeim/DEBUG/MemoryInit.dll
> due to its size (> 1 MB), this module requires 4 KB section alignment.
>

That seems to be a false positive error in GenFw.

It looks like LLD turns

ADRP
ADD

into

NOP
ADR

if the target is within -/+ 1 MiB but it doesn't update the
relocations, so GenFw goes off into the weeds. I.e..

 304:   d503201fnop
304: R_AARCH64_ADR_PREL_PG_HI21 .data
 308:   100015c1adr x1, 5c0 
308: R_AARCH64_ADD_ABS_LO12_NC  .data

This is just another indication that using --emit-relocs is a bad
idea, and we should really be building PIE executables and converting
those based on the dynamic relocation instead.

Adding -Wl,--no-relax to the DLINK flags should help with this,
although I notice that there are other LLD related issues, in the ID
map code I added to ArmVirtQemu a while ago, so ArmVirtQemu.dsc still
does not build.


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Re: [edk2-devel] [edk2-staging/OpenSSL11_EOL][PATCH 4/4] Readme: 0322 update

[Gerd Hoffmann]

  Hi,

> +### Level 2: A bit like workaround, with possibility of upstream to openssl
> +1. Enable the legacy path for X509 pubkey decode and pmeth initialization,  
> +The purpose is to avoid the use of EN/DECODE and Signature provider, will 
> reduce size about 90KB.  
> +(commit: x509: enable legacy path in pub decode)  
> +https://github.com/liyi77/openssl/commit/8780956da77c949ca42f6c4c3fd6ef7045646ef0
>   
> +(commit: evp: enable legacy pmeth)  
> +https://github.com/liyi77/openssl/commit/a2232b35aa308198b61c5734c1bfe1d0263f074b
>   

I suspect that is not going to work well long-term, probably openssl
will remove the code paths they consider being "legacy" at some point
in the future.  Probably not 3.0.x but maybe in 3.1 branch.

> +### Level 3: Totally workaround and hard to upstream to openssl, may need 
> scripts to apply them inside EDK2
> +1. Provider cut.  
> +(commit: CryptoPkg: add own openssl provider)  
> +https://github.com/liyi77/edk2-staging/commit/c3a5b69d8a3465259cfdca8f38b0dc7683b3690e
>   

Allow people implement their own providers looks like an openssl feature
to me.  So I don't think this will be a big problem to maintain, I
expect they try to keep the interfaces stable to not break apps doing
so.

The only little detail we do differently here is to remove the default
providers so LTO can actually remove the unused code.

> +(commit: x509: remove print function 7KB)  
> +https://github.com/liyi77/openssl/commit/faa5d6781c3af601bcbc11ff199e2955d7ff4306
>   

Did you double-check this doesn't break something?

It did for me, due to some code in openssl depending on a
working bio_sprintf() implementation.

take care,
  Gerd



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Re: [edk2-devel] [PATCH 1/1] OvmfPkg/PlatformBootManagerLib: use utf8 for the serial console.

[Gerd Hoffmann]

On Wed, Mar 22, 2023 at 10:31:32AM -0600, Rebecca Cran wrote:
> On 3/22/23 10:20 AM, Ard Biesheuvel wrote:
> > On Fri, 17 Mar 2023 at 13:19, Gerd Hoffmann  wrote:
> > > Time to leave behind relics from the last century and arrive in the
> > > modern world.  Drop PC-ANSI Terminal Type for the serial console, use
> > > UTF-8 instead.
> > > 
> > > Signed-off-by: Gerd Hoffmann 
> > No objections here but how will I be able to observe the difference?
> 
> I'm not sure if it's as simple as this or if it depends on the terminal,
> TERM setting etc.,

It does.  It depends on the locale the terminal application is
running in.  These days that is a utf-8 locale in 99% of the cases,
i.e. "de_DE.UTF-8" for me.

> but I saw a difference when I opened the UiApp and opened
> the drop-down "Select Language".
> 
> Before the patch, it showed "Fran?ais", and after, "Français".

Yes, essentially everything which is not ascii shows correct now,
including the line-drawing characters which you can see in alot
of places in UiApp on the serial console.

take care,
  Gerd



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[edk2-devel] [Patch V4 21/21] UefiCpuPkg/CpuPageTableLib: Reduce the number of random tests

[duntan]

Reduce the number of random tests. In previous patch, non-1:1
mapping is enbaled and it may need more than an hour and a half
for the CI test, which may lead to CI timeout. Reduce the number
of random test count to pass the CI.

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
---
 UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c | 10 
+-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git 
a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c 
b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c
index 8554eefa39..c60302eeac 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c
@@ -9,11 +9,11 @@
 #include "CpuPageTableLibUnitTest.h"
 
 // --- 
PageMode--TestCount-TestRangeCount---RandomOptions
-static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT  mTestContextPagingPae   = { 
PagingPae, 100, 20, USE_RANDOM_ARRAY };
-static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT  mTestContextPaging4Level= { 
Paging4Level, 100, 20, USE_RANDOM_ARRAY };
-static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT  mTestContextPaging4Level1GB = { 
Paging4Level1GB, 100, 20, USE_RANDOM_ARRAY };
-static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT  mTestContextPaging5Level= { 
Paging5Level, 100, 20, USE_RANDOM_ARRAY };
-static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT  mTestContextPaging5Level1GB = { 
Paging5Level1GB, 100, 20, USE_RANDOM_ARRAY };
+static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT  mTestContextPagingPae   = { 
PagingPae, 30, 20, USE_RANDOM_ARRAY };
+static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT  mTestContextPaging4Level= { 
Paging4Level, 30, 20, USE_RANDOM_ARRAY };
+static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT  mTestContextPaging4Level1GB = { 
Paging4Level1GB, 30, 20, USE_RANDOM_ARRAY };
+static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT  mTestContextPaging5Level= { 
Paging5Level, 30, 20, USE_RANDOM_ARRAY };
+static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT  mTestContextPaging5Level1GB = { 
Paging5Level1GB, 30, 20, USE_RANDOM_ARRAY };
 
 /**
   Check if the input parameters are not supported.
-- 
2.31.1.windows.1



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[edk2-devel] [Patch V4 20/21] UefiCpuPkg/CpuPageTableLib: Add RandomTest for PAE paging

[duntan]

Add RandomTest for PAE paging.

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
---
 UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c |  2 
++
 UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c  |  3 
+--
 UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c  | 12 

 3 files changed, 11 insertions(+), 6 deletions(-)

diff --git 
a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c 
b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c
index e1efc84c82..8554eefa39 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c
@@ -9,6 +9,7 @@
 #include "CpuPageTableLibUnitTest.h"
 
 // --- 
PageMode--TestCount-TestRangeCount---RandomOptions
+static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT  mTestContextPagingPae   = { 
PagingPae, 100, 20, USE_RANDOM_ARRAY };
 static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT  mTestContextPaging4Level= { 
Paging4Level, 100, 20, USE_RANDOM_ARRAY };
 static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT  mTestContextPaging4Level1GB = { 
Paging4Level1GB, 100, 20, USE_RANDOM_ARRAY };
 static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT  mTestContextPaging5Level= { 
Paging5Level, 100, 20, USE_RANDOM_ARRAY };
@@ -880,6 +881,7 @@ UefiTestMain (
 goto EXIT;
   }
 
+  AddTestCase (RandomTestCase, "Random Test for PagingPae", "Random Test 
Case1", TestCaseforRandomTest, NULL, NULL, );
   AddTestCase (RandomTestCase, "Random Test for Paging4Level", "Random Test 
Case1", TestCaseforRandomTest, NULL, NULL, );
   AddTestCase (RandomTestCase, "Random Test for Paging4Level1G", "Random Test 
Case2", TestCaseforRandomTest, NULL, NULL, );
   AddTestCase (RandomTestCase, "Random Test for Paging5Level", "Random Test 
Case3", TestCaseforRandomTest, NULL, NULL, );
diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c 
b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
index 18a5010c30..7e79b01823 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
@@ -258,10 +258,9 @@ ValidateAndRandomeModifyPageTable (
   UNIT_TEST_STATUS   Status;
   IA32_PAGING_ENTRY  *PagingEntry;
 
-  if ((PagingMode == Paging32bit) || (PagingMode == PagingPae) || (PagingMode 
>= PagingModeMax)) {
+  if ((PagingMode == Paging32bit) || (PagingMode >= PagingModeMax)) {
 //
 // 32bit paging is never supported.
-// PAE paging will be supported later.
 //
 return UNIT_TEST_ERROR_TEST_FAILED;
   }
diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c 
b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c
index 22f179c21f..67776255c2 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c
@@ -175,10 +175,9 @@ IsPageTableValid (
 return UNIT_TEST_PASSED;
   }
 
-  if ((PagingMode == Paging32bit) || (PagingMode == PagingPae) || (PagingMode 
>= PagingModeMax)) {
+  if ((PagingMode == Paging32bit) || (PagingMode >= PagingModeMax)) {
 //
 // 32bit paging is never supported.
-// PAE paging will be supported later.
 //
 return UNIT_TEST_ERROR_TEST_FAILED;
   }
@@ -187,7 +186,12 @@ IsPageTableValid (
   MaxLevel = (UINT8)(PagingMode >> 8);
 
   PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)PageTable;
-  for (Index = 0; Index < 512; Index++) {
+  for (Index = 0; Index < ((PagingMode == PagingPae) ? 4 : 512); Index++) {
+if (PagingMode == PagingPae) {
+  UT_ASSERT_EQUAL (PagingEntry[Index].PdptePae.Bits.MustBeZero, 0);
+  UT_ASSERT_EQUAL (PagingEntry[Index].PdptePae.Bits.MustBeZero2, 0);
+}
+
 Status = IsPageTableEntryValid ([Index], MaxLevel, 
MaxLeafLevel, Index << (9 * MaxLevel + 3));
 if (Status != UNIT_TEST_PASSED) {
   return Status;
@@ -264,7 +268,7 @@ GetEntryFromPageTable (
   UINT64 Index;
   IA32_PAGING_ENTRY  *PagingEntry;
 
-  if ((PagingMode == Paging32bit) || (PagingMode == PagingPae) || (PagingMode 
>= PagingModeMax)) {
+  if ((PagingMode == Paging32bit) || (PagingMode >= PagingModeMax)) {
 //
 // 32bit paging is never supported.
 // PAE paging will be supported later.
-- 
2.31.1.windows.1



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[edk2-devel] [Patch V4 19/21] UefiCpuPkg/CpuPageTableLib: Enable PAE paging

[duntan]

Modify CpuPageTableLib code to enable PAE paging.
In PageTableMap() API:
When creating new PAE page table, after creating page table,
set all MustBeZero fields of 4 PDPTE to 0. The MustBeZero
fields are treated as RW and other attributes by the common
map logic. So they might be set to 1.
When updating exsiting PAE page table, the special steps are:
1.Prepare 4K-aligned 32bytes memory in stack for 4 temp PDPTE.
2.Copy original 4 PDPTE to the 4 temp PDPTE and set the RW,
  UserSupervisor to 1 and set Nx of 4 temp PDPTE to 0.
4.After updating the page table, set the MustBeZero fields of
  4 temp PDPTE to 0.
5.Copy the temp PDPTE to original PDPTE.

In PageTableParse() API, also create 4 temp PDPTE in stack.
Copy original 4 PDPTE to the 4 temp PDPTE. Then set the RW,
UserSupervisor to 1 and set Nx of 4 temp PDPTE to 0. Finally
use the address of temp PDPTE as the page table address.

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
---
 UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h  | 10 +++---
 UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c   | 53 
-
 UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableParse.c | 25 
+
 3 files changed, 76 insertions(+), 12 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h 
b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h
index 2c67ecb469..521d56c148 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h
+++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h
@@ -15,11 +15,14 @@
 #include 
 #include 
 
-#define IA32_PE_BASE_ADDRESS_MASK_40  0xFF000ull
-#define IA32_PE_BASE_ADDRESS_MASK_39  0xFE000ull
+#define IA32_PE_BASE_ADDRESS_MASK_40 0xFF000ull
+#define IA32_PE_BASE_ADDRESS_MASK_39 0xFE000ull
+#define IA32_PE_BASE_ADDRESS_MASK_PAE_PDPTE  0xFFFE0ull
 
 #define REGION_LENGTH(l)  LShiftU64 (1, (l) * 9 + 3)
 
+#define MAX_PAE_PDPTE_NUM  4
+
 typedef enum {
   Pte   = 1,
   Pde   = 2,
@@ -60,7 +63,8 @@ typedef union {
   UINT64Uint64;
 } IA32_PAGE_NON_LEAF_ENTRY;
 
-#define IA32_PNLE_PAGE_TABLE_BASE_ADDRESS(pa)  ((pa)->Uint64 & 
IA32_PE_BASE_ADDRESS_MASK_40)
+#define IA32_PNLE_PAGE_TABLE_BASE_ADDRESS(pa)   ((pa)->Uint64 & 
IA32_PE_BASE_ADDRESS_MASK_40)
+#define IA32_PAE_PDPTE_PAGE_TABLE_BASE_ADDRESS(pa)  ((pa)->Uint64 & 
IA32_PE_BASE_ADDRESS_MASK_PAE_PDPTE)
 
 ///
 /// Format of a PML5 Entry (PML5E) that References a PML4 Table
diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c 
b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
index 773948349e..8769e45f25 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
@@ -661,15 +661,17 @@ PageTableMap (
   IA32_PAGE_LEVEL MaxLeafLevel;
   IA32_MAP_ATTRIBUTE  ParentAttribute;
   BOOLEAN LocalIsModified;
+  UINTN   Index;
+  IA32_PAGING_ENTRY   *PagingEntry;
+  UINT8   BufferInStack[SIZE_4KB - 1 + MAX_PAE_PDPTE_NUM * sizeof 
(IA32_PAGING_ENTRY)];
 
   if (Length == 0) {
 return RETURN_SUCCESS;
   }
 
-  if ((PagingMode == Paging32bit) || (PagingMode == PagingPae) || (PagingMode 
>= PagingModeMax)) {
+  if ((PagingMode == Paging32bit) || (PagingMode >= PagingModeMax)) {
 //
 // 32bit paging is never supported.
-// PAE paging will be supported later.
 //
 return RETURN_UNSUPPORTED;
   }
@@ -706,17 +708,32 @@ PageTableMap (
 
   MaxLeafLevel = (IA32_PAGE_LEVEL)(UINT8)PagingMode;
   MaxLevel = (IA32_PAGE_LEVEL)(UINT8)(PagingMode >> 8);
-  MaxLinearAddress = LShiftU64 (1, 12 + MaxLevel * 9);
+  MaxLinearAddress = (PagingMode == PagingPae) ? LShiftU64 (1, 32) : LShiftU64 
(1, 12 + MaxLevel * 9);
 
   if ((LinearAddress > MaxLinearAddress) || (Length > MaxLinearAddress - 
LinearAddress)) {
 //
-// Maximum linear address is (1 << 48) or (1 << 57)
+// Maximum linear address is (1 << 32), (1 << 48) or (1 << 57)
 //
 return RETURN_INVALID_PARAMETER;
   }
 
   TopPagingEntry.Uintn = *PageTable;
   if (TopPagingEntry.Uintn != 0) {
+if (PagingMode == PagingPae) {
+  //
+  // Create 4 temporary PDPTE at a 4k-aligned address.
+  // Copy the original PDPTE content and set ReadWrite, UserSupervisor to 
1, set Nx to 0.
+  //
+  TopPagingEntry.Uintn = ALIGN_VALUE ((UINTN)BufferInStack, BASE_4KB);
+  PagingEntry  = (IA32_PAGING_ENTRY *)(TopPagingEntry.Uintn);
+  CopyMem (PagingEntry, (VOID *)(*PageTable), MAX_PAE_PDPTE_NUM * sizeof 
(IA32_PAGING_ENTRY));
+  for (Index = 0; Index < MAX_PAE_PDPTE_NUM; Index++) {
+PagingEntry[Index].Pnle.Bits.ReadWrite  = 1;
+PagingEntry[Index].Pnle.Bits.UserSupervisor = 1;
+PagingEntry[Index].Pnle.Bits.Nx = 0;
+  }
+}
+
 TopPagingEntry.Pce.Present= 1;
 TopPagingEntry.Pce.ReadWrite  = 1;
 

[edk2-devel] [Patch V4 18/21] UefiCpuPkg: Combine branch for non-present and leaf ParentEntry

[duntan]

Combine 'if' condition branch for non-present and leaf Parent
Entry in PageTableLibMapInLevel. Most steps of these two condition
are the same. This commit doesn't change any functionality.

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
---
 UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 83 
+++
 1 file changed, 31 insertions(+), 52 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c 
b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
index 55a756ad90..773948349e 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
@@ -348,68 +348,45 @@ PageTableLibMapInLevel (
   // ParentPagingEntry ONLY is deferenced for checking Present and MustBeOne 
bits
   // when Modify is FALSE.
   //
-
-  if (ParentPagingEntry->Pce.Present == 0) {
-//
-// [LinearAddress, LinearAddress + Length] contains non-present range.
-//
-Status = IsAttributesAndMaskValidForNonPresentEntry (Attribute, Mask);
-if (RETURN_ERROR (Status)) {
-  return Status;
-}
-
+  if ((ParentPagingEntry->Pce.Present == 0) || IsPle (ParentPagingEntry, Level 
+ 1)) {
 //
-// Check the attribute in ParentPagingEntry is equal to attribute 
calculated by input Attribue and Mask.
-//
-PleBAttribute.Uint64 = PageTableLibGetPleBMapAttribute 
(>PleB, ParentAttribute);
-if ((IA32_MAP_ATTRIBUTE_ATTRIBUTES () & 
IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask))
-== (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & 
IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)))
-{
-  return RETURN_SUCCESS;
-}
-
-//
-// The parent entry is CR3 or PML5E/PML4E/PDPTE/PDE.
+// When ParentPagingEntry is non-present, parent entry is CR3 or 
PML5E/PML4E/PDPTE/PDE.
 // It does NOT point to an existing page directory.
+// When ParentPagingEntry is present, parent entry is leaf PDPTE_1G or 
PDE_2M. Split to 2M or 4K pages.
+// Note: it's impossible the parent entry is a PTE_4K.
 //
-ASSERT (Buffer == NULL || *BufferSize >= SIZE_4KB);
-CreateNew= TRUE;
-*BufferSize -= SIZE_4KB;
+OneOfPagingEntry.Pnle.Uint64 = 0;
+PleBAttribute.Uint64 = PageTableLibGetPleBMapAttribute 
(>PleB, ParentAttribute);
 
-if (Modify) {
-  ParentPagingEntry->Uintn = (UINTN)Buffer + *BufferSize;
-  ZeroMem ((VOID *)ParentPagingEntry->Uintn, SIZE_4KB);
+if (ParentPagingEntry->Pce.Present == 0) {
   //
-  // Set default attribute bits for PML5E/PML4E/PDPTE/PDE.
+  // [LinearAddress, LinearAddress + Length] contains non-present range.
   //
-  PageTableLibSetPnle (>Pnle, , 
);
+  Status = IsAttributesAndMaskValidForNonPresentEntry (Attribute, Mask);
+  if (RETURN_ERROR (Status)) {
+return Status;
+  }
 } else {
-  //
-  // Just make sure Present and MustBeZero (PageSize) bits are accurate.
-  //
-  OneOfPagingEntry.Pnle.Uint64 = 0;
+  PageTableLibSetPle (Level, , 0, , 
);
 }
-  } else if (IsPle (ParentPagingEntry, Level + 1)) {
-//
-// The parent entry is a PDPTE_1G or PDE_2M. Split to 2M or 4K pages.
-// Note: it's impossible the parent entry is a PTE_4K.
-//
+
 //
-// Use NOP attributes as the attribute of grand-parents because CPU will 
consider
-// the actual attributes of grand-parents when determing the memory type.
+// Check if the attribute, the physical address calculated by 
ParentPagingEntry is equal to
+// the attribute, the physical address calculated by input Attribue and 
Mask.
 //
-PleBAttribute.Uint64 = PageTableLibGetPleBMapAttribute 
(>PleB, ParentAttribute);
 if ((IA32_MAP_ATTRIBUTE_ATTRIBUTES () & 
IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask))
 == (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & 
IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)))
 {
-  //
-  // This function is called when the memory length is less than the 
region length of the parent level.
-  // No need to split the page when the attributes equal.
-  //
   if ((Mask->Bits.PageTableBaseAddressLow == 0) && 
(Mask->Bits.PageTableBaseAddressHigh == 0)) {
 return RETURN_SUCCESS;
   }
 
+  //
+  // Non-present entry won't reach there since:
+  // 1.When map non-present entry to present, the attribute must be 
different.
+  // 2.When still map non-present entry to non-present, 
PageTableBaseAddressLow and High in Mask must be 0.
+  //
+  ASSERT (ParentPagingEntry->Pce.Present == 1);
   PhysicalAddrInEntry = IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS 
() + PagingEntryIndex * RegionLength;
   PhysicalAddrInAttr  = (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS 
(Attribute) + Offset) & (~RegionMask);
   if (PhysicalAddrInEntry == PhysicalAddrInAttr) {
@@ -420,17 +397,19 @@ PageTableLibMapInLevel (
 ASSERT (Buffer == NULL || 

[edk2-devel] [Patch V4 17/21] UefiCpuPkg/CpuPageTableLib: Add check for page table creation

[duntan]

Add code to compare ParentPagingEntry Attribute and input
Attribute to decide if new next level page table is needed
in non-present ParentPagingEntry condition. This can help avoid
unneccessary page table creation.

For example, there is a page table in which [0, 1G] is mapped(Lv4[0]
,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry).And we
only want to map [1G, 1G+2M] linear address still as non-present.
The expected behaviour should be nothing happens in the process.
However, previous code logic doesn't check if ParentPagingEntry
Attribute and input Attribute are the same in non-present
ParentPagingEntry condition. Then a new 4K memory is allocated for
Lv2 since 1G+2M is not 1G-aligned.
So when ParentPagingEntry is non-present, before allocate 4K memory
for next level paging, we also check if ParentPagingEntry Attribute&
Mask and input Attribute are the same.

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
---
 UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c 
b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
index 982652b58b..55a756ad90 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
@@ -358,6 +358,16 @@ PageTableLibMapInLevel (
   return Status;
 }
 
+//
+// Check the attribute in ParentPagingEntry is equal to attribute 
calculated by input Attribue and Mask.
+//
+PleBAttribute.Uint64 = PageTableLibGetPleBMapAttribute 
(>PleB, ParentAttribute);
+if ((IA32_MAP_ATTRIBUTE_ATTRIBUTES () & 
IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask))
+== (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & 
IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)))
+{
+  return RETURN_SUCCESS;
+}
+
 //
 // The parent entry is CR3 or PML5E/PML4E/PDPTE/PDE.
 // It does NOT point to an existing page directory.
-- 
2.31.1.windows.1



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[edk2-devel] [Patch V4 16/21] UefiCpuPkg: Modify UnitTest code since tested API is changed

[duntan]

From: Zhiguang Liu 

Last commit changed the CpuPageTableLib API PageTableMap, unit
test code should also be modified.

Cc: Eric Dong 
Reviewed-by: Ray Ni 
Cc: Rahul Kumar 
Signed-off-by: Zhiguang Liu 
---
 UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c | 38 
++
 UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c  | 84 
+++-
 UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c  |  4 
++--
 3 files changed, 67 insertions(+), 59 deletions(-)

diff --git 
a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c 
b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c
index 6343b56c2f..e1efc84c82 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c
@@ -422,15 +422,14 @@ TestCaseManualSizeNotMatch (
   UINTN   MapCount;
   IA32_PAGING_ENTRY   *PagingEntry;
 
-  PagingMode = Paging4Level;
-  PageTableBufferSize= 0;
-  PageTable  = 0;
-  Buffer = NULL;
-  MapAttribute.Uint64= 0;
-  MapMask.Uint64 = MAX_UINT64;
-  MapAttribute.Bits.Present  = 1;
-  MapAttribute.Bits.ReadWrite= 1;
-  MapAttribute.Bits.PageTableBaseAddress = (SIZE_2MB - SIZE_4KB) >> 12;
+  PagingMode  = Paging4Level;
+  PageTableBufferSize = 0;
+  PageTable   = 0;
+  Buffer  = NULL;
+  MapMask.Uint64  = MAX_UINT64;
+  MapAttribute.Uint64 = (SIZE_2MB - SIZE_4KB);
+  MapAttribute.Bits.Present   = 1;
+  MapAttribute.Bits.ReadWrite = 1;
   //
   // Create Page table to cover [2M-4K, 4M], with ReadWrite = 1
   //
@@ -460,9 +459,9 @@ TestCaseManualSizeNotMatch (
   // [2M-4K,2M], R/W = 0
   // [2M   ,4M], R/W = 1
   //
-  PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)PageTable; 
  // Get 4 level entry
-  PagingEntry = (IA32_PAGING_ENTRY 
*)(UINTN)(PagingEntry->Pnle.Bits.PageTableBaseAddress << 12); // Get 3 level 
entry
-  PagingEntry = (IA32_PAGING_ENTRY 
*)(UINTN)(PagingEntry->Pnle.Bits.PageTableBaseAddress << 12); // Get 2 level 
entry
+  PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)PageTable; 
  // Get 4 level entry
+  PagingEntry = (IA32_PAGING_ENTRY 
*)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (PagingEntry); // Get 3 level entry
+  PagingEntry = (IA32_PAGING_ENTRY 
*)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (PagingEntry); // Get 2 level entry
   PagingEntry->Uint64 = PagingEntry->Uint64 & (~(UINT64)0x2);
   MapCount= 0;
   Status  = PageTableParse (PageTable, PagingMode, NULL, 
);
@@ -480,20 +479,19 @@ TestCaseManualSizeNotMatch (
 
   UT_ASSERT_EQUAL (Map[1].LinearAddress, SIZE_2MB);
   UT_ASSERT_EQUAL (Map[1].Length, SIZE_2MB);
-  ExpectedMapAttribute.Uint64= MapAttribute.Uint64;
-  ExpectedMapAttribute.Bits.ReadWrite= 1;
-  ExpectedMapAttribute.Bits.PageTableBaseAddress = SIZE_2MB >> 12;
+  ExpectedMapAttribute.Uint64 = MapAttribute.Uint64 + SIZE_4KB;
+  ExpectedMapAttribute.Bits.ReadWrite = 1;
   UT_ASSERT_EQUAL (Map[1].Attribute.Uint64, ExpectedMapAttribute.Uint64);
 
   //
   // Set Page table [2M-4K, 2M+4K]'s ReadWrite = 1, [2M,2M+4K]'s ReadWrite is 
already 1
   // Just need to set [2M-4K,2M], won't need extra size, so the status should 
be success
   //
-  MapAttribute.Bits.Present  = 1;
-  MapAttribute.Bits.ReadWrite= 1;
-  PageTableBufferSize= 0;
-  MapAttribute.Bits.PageTableBaseAddress = (SIZE_2MB - SIZE_4KB) >> 12;
-  Status = PageTableMap (, 
PagingMode, Buffer, , SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, 
, , NULL);
+  MapAttribute.Uint64 = SIZE_2MB - SIZE_4KB;
+  MapAttribute.Bits.Present   = 1;
+  MapAttribute.Bits.ReadWrite = 1;
+  PageTableBufferSize = 0;
+  Status  = PageTableMap (, PagingMode, Buffer, 
, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, , 
, NULL);
   UT_ASSERT_EQUAL (Status, RETURN_SUCCESS);
   return UNIT_TEST_PASSED;
 }
diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c 
b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
index 6f1485976a..18a5010c30 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
@@ -157,7 +157,8 @@ ValidateAndRandomeModifyPageTablePageTableEntry (
   )
 {
   UINT64 Index;
-  UINT64 TempPhysicalBase;
+  UINT32 PageTableBaseAddressLow;
+  UINT32 PageTableBaseAddressHigh;
   

[edk2-devel] [Patch V4 15/21] UefiCpuPkg: Fix IA32 build failure in CpuPageTableLib.inf

[duntan]

From: Zhiguang Liu 

The definition of IA32_MAP_ATTRIBUTE has 64 bits, and one of the bit
field PageTableBaseAddress is from bit 12 to bit 52. This means if the
compiler treats the 64bits value as two UINT32 value, the field
PageTableBaseAddress spans two UINT32 value. That's why when building in
NOOPT mode in IA32, the below issue is noticed:
unresolved external symbol __allshl
This patch fix the build failure by seperate field PageTableBaseAddress
into two fields, make sure no field spans two UINT32 value.

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Signed-off-by: Zhiguang Liu 
Signed-off-by: Ray Ni 
---
 UefiCpuPkg/Include/Library/CpuPageTableLib.h |  32 

 UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h| 125 
+++--
 UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c |  22 
+++---
 3 files changed, 90 insertions(+), 89 deletions(-)

diff --git a/UefiCpuPkg/Include/Library/CpuPageTableLib.h 
b/UefiCpuPkg/Include/Library/CpuPageTableLib.h
index c94d82ea65..5e545a35f6 100644
--- a/UefiCpuPkg/Include/Library/CpuPageTableLib.h
+++ b/UefiCpuPkg/Include/Library/CpuPageTableLib.h
@@ -11,22 +11,22 @@
 
 typedef union {
   struct {
-UINT64Present  : 1; // 0 = Not present in memory, 1 = 
Present in memory
-UINT64ReadWrite: 1; // 0 = Read-Only, 1= Read/Write
-UINT64UserSupervisor   : 1; // 0 = Supervisor, 1=User
-UINT64WriteThrough : 1; // 0 = Write-Back caching, 
1=Write-Through caching
-UINT64CacheDisabled: 1; // 0 = Cached, 1=Non-Cached
-UINT64Accessed : 1; // 0 = Not accessed, 1 = Accessed (set 
by CPU)
-UINT64Dirty: 1; // 0 = Not dirty, 1 = Dirty (set by 
CPU)
-UINT64Pat  : 1; // PAT
-
-UINT64Global   : 1; // 0 = Not global, 1 = Global (if 
CR4.PGE = 1)
-UINT64Reserved1: 3; // Ignored
-
-UINT64PageTableBaseAddress : 40; // Page Table Base Address
-UINT64Reserved2: 7;  // Ignored
-UINT64ProtectionKey: 4;  // Protection key
-UINT64Nx   : 1;  // No Execute bit
+UINT32Present  : 1;  // 0 = Not present in memory, 1 = 
Present in memory
+UINT32ReadWrite: 1;  // 0 = Read-Only, 1= Read/Write
+UINT32UserSupervisor   : 1;  // 0 = Supervisor, 1=User
+UINT32WriteThrough : 1;  // 0 = Write-Back caching, 
1=Write-Through caching
+UINT32CacheDisabled: 1;  // 0 = Cached, 1=Non-Cached
+UINT32Accessed : 1;  // 0 = Not accessed, 1 = Accessed 
(set by CPU)
+UINT32Dirty: 1;  // 0 = Not dirty, 1 = Dirty (set 
by CPU)
+UINT32Pat  : 1;  // PAT
+UINT32Global   : 1;  // 0 = Not global, 1 = Global (if 
CR4.PGE = 1)
+UINT32Reserved1: 3;  // Ignored
+UINT32PageTableBaseAddressLow  : 20; // Page Table Base Address Low
+
+UINT32PageTableBaseAddressHigh : 20; // Page Table Base Address High
+UINT32Reserved2: 7;  // Ignored
+UINT32ProtectionKey: 4;  // Protection key
+UINT32Nx   : 1;  // No Execute bit
   } Bits;
   UINT64Uint64;
 } IA32_MAP_ATTRIBUTE;
diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h 
b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h
index 8d856d7c7e..2c67ecb469 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h
+++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h
@@ -29,11 +29,12 @@ typedef enum {
 } IA32_PAGE_LEVEL;
 
 typedef struct {
-  UINT64Present: 1;   // 0 = Not present in memory, 1 = 
Present in memory
-  UINT64ReadWrite  : 1;   // 0 = Read-Only, 1= Read/Write
-  UINT64UserSupervisor : 1;   // 0 = Supervisor, 1=User
-  UINT64Reserved   : 58;
-  UINT64Nx : 1;// No Execute bit
+  UINT32Present: 1;   // 0 = Not present in memory, 1 = 
Present in memory
+  UINT32ReadWrite  : 1;   // 0 = Read-Only, 1= Read/Write
+  UINT32UserSupervisor : 1;   // 0 = Supervisor, 1=User
+  UINT32Reserved0  : 29;
+  UINT32Reserved1  : 31;
+  UINT32Nx : 1;// No Execute bit
 } IA32_PAGE_COMMON_ENTRY;
 
 ///
@@ -41,20 +42,20 @@ typedef struct {
 ///
 typedef union {
   struct {
-UINT64Present  : 1; // 0 = Not present in memory, 1 = 
Present in memory
-UINT64ReadWrite: 1; // 0 = Read-Only, 1= Read/Write
-UINT64UserSupervisor   : 1; // 0 = Supervisor, 1=User
-UINT64WriteThrough : 1; // 0 = Write-Back caching, 
1=Write-Through caching
-

[edk2-devel] [Patch V4 14/21] UefiCpuPkg/CpuPageTableLib: Modify RandomTest to check IsModified

[duntan]

Modify RandomTest to check if parameter IsModified of
PageTableMap() correctlly indicates whether input page table
is modified or not.

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Cc: Zhiguang Liu 
---
 UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c | 45 
+
 1 file changed, 33 insertions(+), 12 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c 
b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
index 816fd7b446..6f1485976a 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
@@ -636,6 +636,8 @@ SingleMapEntryTest (
   VOID*Buffer;
   IA32_MAP_ENTRY  *Map;
   UINTN   MapCount;
+  IA32_MAP_ENTRY  *Map2;
+  UINTN   MapCount2;
   UINTN   Index;
   UINTN   KeyPointCount;
   UINTN   NewKeyPointCount;
@@ -648,11 +650,13 @@ SingleMapEntryTest (
   UINT64  PreviousAddress;
   UINT64  RangeLimit;
   BOOLEAN IsNotPresent;
+  BOOLEAN IsModified;
 
   MapsIndex   = MapEntrys->Count;
   MapCount= 0;
   PreviousAddress = 0;
   IsNotPresent= FALSE;
+  IsModified  = FALSE;
 
   GenerateSingleRandomMapEntry (MaxAddress, MapEntrys);
   RangeLimit = MapEntrys->Maps[MapsIndex].LinearAddress + 
MapEntrys->Maps[MapsIndex].Length;
@@ -697,7 +701,7 @@ SingleMapEntryTest (
   MapEntrys->Maps[MapsIndex].Length,
   >Maps[MapsIndex].Attribute,
   >Maps[MapsIndex].Mask,
-  NULL
+  
   );
 
   Attribute = >Maps[MapsIndex].Attribute;
@@ -758,7 +762,7 @@ SingleMapEntryTest (
MapEntrys->Maps[MapsIndex].Length,
>Maps[MapsIndex].Attribute,
>Maps[MapsIndex].Mask,
-   NULL
+   
);
   }
 
@@ -772,18 +776,31 @@ SingleMapEntryTest (
 return TestStatus;
   }
 
-  MapCount = 0;
-  Status   = PageTableParse (*PageTable, PagingMode, NULL, );
-  if (MapCount != 0) {
+  MapCount2 = 0;
+  Status= PageTableParse (*PageTable, PagingMode, NULL, );
+  if (MapCount2 != 0) {
 UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL);
 
 //
-// Allocate memory for Maps
+// Allocate memory for Map2
 // Note the memory is only used in this one Single MapEntry Test
 //
-Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount * sizeof 
(IA32_MAP_ENTRY)));
-ASSERT (Map != NULL);
-Status = PageTableParse (*PageTable, PagingMode, Map, );
+Map2 = AllocatePages (EFI_SIZE_TO_PAGES (MapCount2 * sizeof 
(IA32_MAP_ENTRY)));
+ASSERT (Map2 != NULL);
+Status = PageTableParse (*PageTable, PagingMode, Map2, );
+  }
+
+  //
+  // Check if PageTable has been modified.
+  //
+  if (MapCount2 != MapCount) {
+UT_ASSERT_EQUAL (IsModified, TRUE);
+  } else {
+if (CompareMem (Map, Map2, MapCount2 * sizeof (IA32_MAP_ENTRY)) != 0) {
+  UT_ASSERT_EQUAL (IsModified, TRUE);
+} else {
+  UT_ASSERT_EQUAL (IsModified, FALSE);
+}
   }
 
   UT_ASSERT_EQUAL (Status, RETURN_SUCCESS);
@@ -793,17 +810,17 @@ SingleMapEntryTest (
   // Note the memory is only used in this one Single MapEntry Test
   //
   KeyPointCount = 0;
-  GetKeyPointList (MapEntrys, Map, MapCount, NULL, );
+  GetKeyPointList (MapEntrys, Map2, MapCount2, NULL, );
   KeyPointBuffer = AllocatePages (EFI_SIZE_TO_PAGES (KeyPointCount * sizeof 
(UINT64)));
   ASSERT (KeyPointBuffer != NULL);
   NewKeyPointCount = 0;
-  GetKeyPointList (MapEntrys, Map, MapCount, KeyPointBuffer, 
);
+  GetKeyPointList (MapEntrys, Map2, MapCount2, KeyPointBuffer, 
);
 
   //
   // Compare all key point's attribute
   //
   for (Index = 0; Index < NewKeyPointCount; Index++) {
-if (!CompareEntrysforOnePoint (KeyPointBuffer[Index], MapEntrys, Map, 
MapCount, InitMap, InitMapCount)) {
+if (!CompareEntrysforOnePoint (KeyPointBuffer[Index], MapEntrys, Map2, 
MapCount2, InitMap, InitMapCount)) {
   DEBUG ((DEBUG_INFO, "Error happens at below key point\n"));
   DEBUG ((DEBUG_INFO, "Index = %d KeyPointBuffer[Index] = 0x%lx\n", Index, 
KeyPointBuffer[Index]));
   Value = GetEntryFromPageTable (*PageTable, PagingMode, 
KeyPointBuffer[Index], );
@@ -817,6 +834,10 @@ SingleMapEntryTest (
 FreePages (Map, EFI_SIZE_TO_PAGES (MapCount * sizeof (IA32_MAP_ENTRY)));
   }
 
+  if (MapCount2 != 0) {
+FreePages (Map2, EFI_SIZE_TO_PAGES (MapCount2 * sizeof (IA32_MAP_ENTRY)));
+  }
+
   return UNIT_TEST_PASSED;
 }
 
-- 
2.31.1.windows.1



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[edk2-devel] [Patch V4 13/21] UefiCpuPkg/CpuPageTableLib: Add OUTPUT IsModified parameter.

[duntan]

Add OUTPUT IsModified parameter in PageTableMap() to indicate
if page table has been modified. With this parameter, caller
can know if need to call FlushTlb when the page table is in CR3.

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
---
 UefiCpuPkg/Include/Library/CpuPageTableLib.h  |  4 
+++-
 UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c  | 50 
+++---
 UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c | 72 

 UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c  |  6 
--
 UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c|  6 
--
 5 files changed, 90 insertions(+), 48 deletions(-)

diff --git a/UefiCpuPkg/Include/Library/CpuPageTableLib.h 
b/UefiCpuPkg/Include/Library/CpuPageTableLib.h
index 6bda15b5bc..c94d82ea65 100644
--- a/UefiCpuPkg/Include/Library/CpuPageTableLib.h
+++ b/UefiCpuPkg/Include/Library/CpuPageTableLib.h
@@ -74,6 +74,7 @@ typedef enum {
  Page table entries that map the linear 
address range are reset to 0 before set to the new attribute
  when a new physical base address is set.
   @param[in]  Mask   The mask used for attribute. The 
corresponding field in Attribute is ignored if that in Mask is 0.
+  @param[out] IsModified TRUE means page table is modified. FALSE 
means page table is not modified.
 
   @retval RETURN_UNSUPPORTEDPagingMode is not supported.
   @retval RETURN_INVALID_PARAMETER  PageTable, BufferSize, Attribute or Mask 
is NULL or the combination of Attribute and Mask is invalid.
@@ -93,7 +94,8 @@ PageTableMap (
   IN UINT64  LinearAddress,
   IN UINT64  Length,
   IN IA32_MAP_ATTRIBUTE  *Attribute,
-  IN IA32_MAP_ATTRIBUTE  *Mask
+  IN IA32_MAP_ATTRIBUTE  *Mask,
+  OUTBOOLEAN *IsModified   OPTIONAL
   );
 
 typedef struct {
diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c 
b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
index 2ad22b333d..797fc2f600 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
@@ -273,6 +273,7 @@ IsAttributesAndMaskValidForNonPresentEntry (
 Page table entries that map the linear 
address range are reset to 0 before set to the new attribute
 when a new physical base address is set.
   @param[in]  Mask  The mask used for attribute. The 
corresponding field in Attribute is ignored if that in Mask is 0.
+  @param[out] IsModifiedTRUE means page table is modified. FALSE 
means page table is not modified.
 
   @retval RETURN_INVALID_PARAMETER  The combination of Attribute and Mask for 
non-present entry is invalid.
   @retval RETURN_SUCCESSPageTable is created/updated successfully.
@@ -290,7 +291,8 @@ PageTableLibMapInLevel (
   IN UINT64  Length,
   IN UINT64  Offset,
   IN IA32_MAP_ATTRIBUTE  *Attribute,
-  IN IA32_MAP_ATTRIBUTE  *Mask
+  IN IA32_MAP_ATTRIBUTE  *Mask,
+  OUTBOOLEAN *IsModified
   )
 {
   RETURN_STATUS   Status;
@@ -316,6 +318,8 @@ PageTableLibMapInLevel (
   IA32_MAP_ATTRIBUTE  LocalParentAttribute;
   UINT64  PhysicalAddrInEntry;
   UINT64  PhysicalAddrInAttr;
+  IA32_PAGING_ENTRY   OriginalParentPagingEntry;
+  IA32_PAGING_ENTRY   OriginalCurrentPagingEntry;
 
   ASSERT (Level != 0);
   ASSERT ((Attribute != NULL) && (Mask != NULL));
@@ -328,8 +332,9 @@ PageTableLibMapInLevel (
   NopAttribute.Bits.ReadWrite  = 1;
   NopAttribute.Bits.UserSupervisor = 1;
 
-  LocalParentAttribute.Uint64 = ParentAttribute->Uint64;
-  ParentAttribute = 
+  LocalParentAttribute.Uint64  = ParentAttribute->Uint64;
+  ParentAttribute  = 
+  OriginalParentPagingEntry.Uint64 = ParentPagingEntry->Uint64;
 
   //
   // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 21) 
or 4K (1 << 12).
@@ -563,7 +568,15 @@ PageTableLibMapInLevel (
   ASSERT (CreateNew || (Mask->Bits.Nx == 0) || (Attribute->Bits.Nx == 
1));
 }
 
+//
+// Check if any leaf PagingEntry is modified.
+//
+OriginalCurrentPagingEntry.Uint64 = CurrentPagingEntry->Uint64;
 PageTableLibSetPle (Level, CurrentPagingEntry, Offset, Attribute, 
);
+
+if (OriginalCurrentPagingEntry.Uint64 != CurrentPagingEntry->Uint64) {
+  *IsModified = TRUE;
+}
   }
 } else {
   //
@@ -586,7 +599,8 @@ PageTableLibMapInLevel (
  Length,
  Offset,
  Attribute,
- Mask
+ Mask,

[edk2-devel] [Patch V4 12/21] UefiCpuPkg/CpuPageTableLib: Enable non-1:1 mapping in random test

[duntan]

Enable non-1:1 mapping in random test. In previous test, non-1:1
test will fail due to the non-1:1 mapping issue in CpuPageTableLib
and invalid Input Mask when creating new page table or mapping
not-present range. Now these issue have been fixed.

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Reviewed-by: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
---
 UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c | 8 

 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git 
a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c 
b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c
index 3e84e2ba11..d37cae9fbd 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c
@@ -9,10 +9,10 @@
 #include "CpuPageTableLibUnitTest.h"
 
 // --- 
PageMode--TestCount-TestRangeCount---RandomOptions
-static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT  mTestContextPaging4Level= { 
Paging4Level, 100, 20, ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY };
-static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT  mTestContextPaging4Level1GB = { 
Paging4Level1GB, 100, 20, ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY };
-static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT  mTestContextPaging5Level= { 
Paging5Level, 100, 20, ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY };
-static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT  mTestContextPaging5Level1GB = { 
Paging5Level1GB, 100, 20, ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY };
+static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT  mTestContextPaging4Level= { 
Paging4Level, 100, 20, USE_RANDOM_ARRAY };
+static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT  mTestContextPaging4Level1GB = { 
Paging4Level1GB, 100, 20, USE_RANDOM_ARRAY };
+static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT  mTestContextPaging5Level= { 
Paging5Level, 100, 20, USE_RANDOM_ARRAY };
+static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT  mTestContextPaging5Level1GB = { 
Paging5Level1GB, 100, 20, USE_RANDOM_ARRAY };
 
 /**
   Check if the input parameters are not supported.
-- 
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[edk2-devel] [Patch V4 11/21] UefiCpuPkg/CpuPageTableLib:Modify RandomTest to check Mask/Attr

[duntan]

Modify RandomTest to check invalid input. When creating new page
table or updating exsiting page table:
1.If set [LinearAddress, LinearAddress+Length] to non-preset, all
  other attributes should not be provided.
2.If [LinearAddress, LinearAddress+Length] contain non-present range,
  the Returnstatus of PageTableMap() should be InvalidParameter when:
2.1Some of attributes are not provided when mapping non-present range
   to present.
2.2Set any other attribute without setting the non-present range to
   Present.

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Cc: Zhiguang Liu 
---
 UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c | 150 
++
 UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c |   6 +-
 2 files changed, 131 insertions(+), 25 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c 
b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
index 52eb9daa10..b99e31f4c8 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
@@ -273,6 +273,27 @@ ValidateAndRandomeModifyPageTable (
   return Status;
 }
 
+/**
+  Remove the last MAP_ENTRY in MapEntrys.
+
+  @param MapEntrys   Pointer to MapEntrys buffer
+**/
+VOID
+RemoveLastMapEntry (
+  IN OUT MAP_ENTRYS  *MapEntrys
+  )
+{
+  UINTN  MapsIndex;
+
+  if (MapEntrys->Count == 0) {
+return;
+  }
+
+  MapsIndex = MapEntrys->Count - 1;
+  ZeroMem (&(MapEntrys->Maps[MapsIndex]), sizeof (MAP_ENTRY));
+  MapEntrys->Count = MapsIndex;
+}
+
 /**
   Generate single random map entry.
   The map entry can be the input of function PageTableMap
@@ -327,7 +348,16 @@ GenerateSingleRandomMapEntry (
 MapEntrys->Maps[MapsIndex].Mask.Uint64  = MapEntrys->Maps[Random32 (0, 
(UINT32)MapsIndex-1)].Mask.Uint64;
   } else {
 MapEntrys->Maps[MapsIndex].Attribute.Uint64 = Random64 (0, MAX_UINT64) & 
mSupportedBit.Uint64;
-MapEntrys->Maps[MapsIndex].Mask.Uint64  = Random64 (0, MAX_UINT64) & 
mSupportedBit.Uint64;
+if (RandomBoolean (5)) {
+  //
+  // The probability to get random Mask should be small since all bits of 
a random number
+  // have a high probability of containing 0, which may be a invalid input.
+  //
+  MapEntrys->Maps[MapsIndex].Mask.Uint64 = Random64 (0, MAX_UINT64) & 
mSupportedBit.Uint64;
+} else {
+  MapEntrys->Maps[MapsIndex].Mask.Uint64 = MAX_UINT64;
+}
+
 if (MapEntrys->Maps[MapsIndex].Mask.Bits.ProtectionKey != 0) {
   MapEntrys->Maps[MapsIndex].Mask.Bits.ProtectionKey = 0xF;
 }
@@ -337,15 +367,7 @@ GenerateSingleRandomMapEntry (
 MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress = 
MapEntrys->Maps[MapsIndex].LinearAddress >> 12;
 MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress  = 
0xFF;
   } else {
-//
-// Todo: If the mask bit for base address is zero, when dump the 
pagetable, every entry mapping to physical address zeor.
-//   This means the map count will be a large number, and impossible 
to finish in proper time.
-//   Need to avoid such case when remove the Random option 
ONLY_ONE_ONE_MAPPING
-//
 MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress = (Random64 
(0, (((UINT64)1)<<52) - 1) & AlignedTable[Random32 (0, ARRAY_SIZE 
(AlignedTable) -1)])>> 12;
-if (RandomBoolean (50)) {
-  MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress = 0;
-}
   }
 
   MapEntrys->Count += 1;
@@ -608,23 +630,62 @@ SingleMapEntryTest (
   IN UINTN  InitMapCount
   )
 {
-  UINTN MapsIndex;
-  RETURN_STATUS Status;
-  UINTN PageTableBufferSize;
-  VOID  *Buffer;
-  IA32_MAP_ENTRY*Map;
-  UINTN MapCount;
-  UINTN Index;
-  UINTN KeyPointCount;
-  UINTN NewKeyPointCount;
-  UINT64*KeyPointBuffer;
-  UINTN Level;
-  UINT64Value;
-  UNIT_TEST_STATUS  TestStatus;
-
-  MapsIndex = MapEntrys->Count;
+  UINTN   MapsIndex;
+  RETURN_STATUS   Status;
+  UINTN   PageTableBufferSize;
+  VOID*Buffer;
+  IA32_MAP_ENTRY  *Map;
+  UINTN   MapCount;
+  UINTN   Index;
+  UINTN   KeyPointCount;
+  UINTN   NewKeyPointCount;
+  UINT64  *KeyPointBuffer;
+  UINTN   Level;
+  UINT64  Value;
+  UNIT_TEST_STATUSTestStatus;
+  IA32_MAP_ATTRIBUTE  *Mask;
+  IA32_MAP_ATTRIBUTE  *Attribute;
+  UINT64  PreviousAddress;
+  UINT64  RangeLimit;
+  BOOLEAN IsNotPresent;
+
+  MapsIndex   = MapEntrys->Count;
+  MapCount= 0;
+  PreviousAddress = 0;
+  IsNotPresent= FALSE;
 
   

[edk2-devel] [Patch V4 10/21] UefiCpuPkg/CpuPageTableLib:Modify RandomBoolean() in RandomTest

[duntan]

Add an input parameter to control the probability of returning
true. Change RandomBoolean() in RandomTest from 50% chance
returning true to returning true with the percentage of input
Probability.

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
---
 UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c | 43 
+--
 1 file changed, 21 insertions(+), 22 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c 
b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
index 97a388ca1c..52eb9daa10 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
@@ -1,7 +1,7 @@
 /** @file
   Random test case for Unit tests of the CpuPageTableLib instance of the 
CpuPageTableLib class
 
-  Copyright (c) 2022, Intel Corporation. All rights reserved.
+  Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -81,22 +81,6 @@ LocalRandomBytes (
   }
 }
 
-/**
-  Return a random boolean.
-
-  @return boolean
-**/
-BOOLEAN
-RandomBoolean (
-  VOID
-  )
-{
-  BOOLEAN  Value;
-
-  LocalRandomBytes ((UINT8 *), sizeof (BOOLEAN));
-  return Value%2;
-}
-
 /**
   Return a 32bit random number.
 
@@ -139,6 +123,21 @@ Random64 (
   return (UINT64)(Value % (Limit - Start  + 1)) + Start;
 }
 
+/**
+  Returns true with the percentage of input Probability.
+
+  @param[in]   ProbabilityThe percentage to return true.
+
+  @return boolean
+**/
+BOOLEAN
+RandomBoolean (
+  UINT8  Probability
+  )
+{
+  return ((Probability > ((UINT8)Random64 (0, 100))) ? TRUE : FALSE);
+}
+
 /**
   Check if the Page table entry is valid
 
@@ -178,7 +177,7 @@ ValidateAndRandomeModifyPageTablePageTableEntry (
   UT_ASSERT_EQUAL ((PagingEntry->Uint64 & mValidMaskLeaf[Level].Uint64), 
PagingEntry->Uint64);
 }
 
-if ((RandomNumber < 100) && RandomBoolean ()) {
+if ((RandomNumber < 100) && RandomBoolean (50)) {
   RandomNumber++;
   if (Level == 1) {
 TempPhysicalBase = PagingEntry->Pte4K.Bits.PageTableBaseAddress;
@@ -211,7 +210,7 @@ ValidateAndRandomeModifyPageTablePageTableEntry (
 UT_ASSERT_EQUAL ((PagingEntry->Uint64 & mValidMaskNoLeaf[Level].Uint64), 
PagingEntry->Uint64);
   }
 
-  if ((RandomNumber < 100) && RandomBoolean ()) {
+  if ((RandomNumber < 100) && RandomBoolean (50)) {
 RandomNumber++;
 TempPhysicalBase = PagingEntry->Pnle.Bits.PageTableBaseAddress;
 
@@ -299,7 +298,7 @@ GenerateSingleRandomMapEntry (
   //
   // use AlignedTable to avoid that a random number can be very hard to be 1G 
or 2M aligned
   //
-  if ((MapsIndex != 0) &&  (RandomBoolean ())) {
+  if ((MapsIndex != 0) &&  (RandomBoolean (50))) {
 FormerLinearAddress = MapEntrys->Maps[Random32 (0, 
(UINT32)MapsIndex-1)].LinearAddress;
 if (FormerLinearAddress < 2 * (UINT64)SIZE_1GB) {
   FormerLinearAddressBottom = 0;
@@ -323,7 +322,7 @@ GenerateSingleRandomMapEntry (
   //
   MapEntrys->Maps[MapsIndex].Length = Random64 (0, MIN (MaxAddress - 
MapEntrys->Maps[MapsIndex].LinearAddress, 10 * (UINT64)SIZE_1GB)) & 
AlignedTable[Random32 (0, ARRAY_SIZE (AlignedTable) -1)];
 
-  if ((MapsIndex != 0)  && (RandomBoolean ())) {
+  if ((MapsIndex != 0)  && (RandomBoolean (50))) {
 MapEntrys->Maps[MapsIndex].Attribute.Uint64 = MapEntrys->Maps[Random32 (0, 
(UINT32)MapsIndex-1)].Attribute.Uint64;
 MapEntrys->Maps[MapsIndex].Mask.Uint64  = MapEntrys->Maps[Random32 (0, 
(UINT32)MapsIndex-1)].Mask.Uint64;
   } else {
@@ -344,7 +343,7 @@ GenerateSingleRandomMapEntry (
 //   Need to avoid such case when remove the Random option 
ONLY_ONE_ONE_MAPPING
 //
 MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress = (Random64 
(0, (((UINT64)1)<<52) - 1) & AlignedTable[Random32 (0, ARRAY_SIZE 
(AlignedTable) -1)])>> 12;
-if (RandomBoolean ()) {
+if (RandomBoolean (50)) {
   MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress = 0;
 }
   }
-- 
2.31.1.windows.1



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[edk2-devel] [Patch V4 09/21] UefiCpuPkg/CpuPageTableLib: Add manual test to check Mask and Attr

[duntan]

Add manual test case to check input Mask and Attribute. The check
steps are:
1.Create Page table to cover [0, 2G]. All fields of MapMask should
  be set.
2.Update Page table to set [2G - 8K,2G] from present to non-present.
  All fields of MapMask except present should not be set.
3.Still set [2G - 8K, 2G] as not present, this case is permitted.
  But set [2G - 8K, 2G] as RW is not permitted.
4.Update Page table to set [2G - 8K, 2G] as present and RW. All
  fields of MapMask should be set.

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
---
 UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c | 
129 
+++--
 1 file changed, 127 insertions(+), 2 deletions(-)

diff --git 
a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c 
b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c
index 3014a03243..3e84e2ba11 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c
@@ -1,7 +1,7 @@
 /** @file
   Unit tests of the CpuPageTableLib instance of the CpuPageTableLib class
 
-  Copyright (c) 2022, Intel Corporation. All rights reserved.
+  Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -697,6 +697,131 @@ TestCaseManualChangeNx (
   return UNIT_TEST_PASSED;
 }
 
+/**
+  Check if the input Mask and Attribute is as expected when creating new page 
table or
+  updating existing page table.
+
+  @param[in]  Context[Optional] An optional parameter that enables:
+ 1) test-case reuse with varied parameters and
+ 2) test-case re-entry for Target tests that need a
+ reboot.  This parameter is a VOID* and it is the
+ responsibility of the test author to ensure that the
+ contents are well understood by all test cases that 
may
+ consume it.
+
+  @retval  UNIT_TEST_PASSED The Unit test has completed and the 
test
+case was successful.
+  @retval  UNIT_TEST_ERROR_TEST_FAILED  A test case assertion has failed.
+**/
+UNIT_TEST_STATUS
+EFIAPI
+TestCaseToCheckMapMaskAndAttr (
+  IN UNIT_TEST_CONTEXT  Context
+  )
+{
+  UINTN   PageTable;
+  PAGING_MODE PagingMode;
+  VOID*Buffer;
+  UINTN   PageTableBufferSize;
+  IA32_MAP_ATTRIBUTE  MapAttribute;
+  IA32_MAP_ATTRIBUTE  ExpectedMapAttribute;
+  IA32_MAP_ATTRIBUTE  MapMask;
+  RETURN_STATUS   Status;
+  IA32_MAP_ENTRY  *Map;
+  UINTN   MapCount;
+
+  PagingMode= Paging4Level;
+  PageTableBufferSize   = 0;
+  PageTable = 0;
+  Buffer= NULL;
+  MapAttribute.Uint64   = 0;
+  MapAttribute.Bits.Present = 1;
+  MapMask.Uint64= 0;
+  MapMask.Bits.Present  = 1;
+  //
+  // Create Page table to cover [0, 2G]. All fields of MapMask should be set.
+  //
+  Status = PageTableMap (, PagingMode, Buffer, , 
0, SIZE_2GB, , );
+  UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER);
+  MapMask.Uint64 = MAX_UINT64;
+  Status = PageTableMap (, PagingMode, Buffer, 
, 0, SIZE_2GB, , );
+  UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL);
+  Buffer = AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize));
+  Status = PageTableMap (, PagingMode, Buffer, , 
0, SIZE_2GB, , );
+  UT_ASSERT_EQUAL (Status, RETURN_SUCCESS);
+
+  //
+  // Update Page table to set [2G - 8K, 2G] from present to non-present. All 
fields of MapMask except present should be set.
+  //
+  PageTableBufferSize= 0;
+  MapAttribute.Uint64= SIZE_2GB - SIZE_8KB;
+  MapMask.Uint64 = 0;
+  MapMask.Bits.Present   = 1;
+  MapMask.Bits.ReadWrite = 1;
+  Status = PageTableMap (, PagingMode, Buffer, 
, SIZE_2GB - SIZE_8KB, SIZE_8KB, , );
+  UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER);
+  MapMask.Bits.ReadWrite = 0;
+  Status = PageTableMap (, PagingMode, Buffer, 
, SIZE_2GB - SIZE_8KB, SIZE_8KB, , );
+  UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL);
+  Buffer = AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize));
+  Status = PageTableMap (, PagingMode, Buffer, , 
0, SIZE_2GB, , );
+  UT_ASSERT_EQUAL (Status, RETURN_SUCCESS);
+
+  //
+  // Still set [2G - 8K, 2G] as not present, this case is permitted. But set 
[2G - 8K, 2G] as RW is not permitted.
+  //
+  PageTableBufferSize  = 0;
+  MapAttribute.Uint64  = 0;
+  MapMask.Uint64   = 0;
+  MapMask.Bits.Present = 1;
+  Status   = PageTableMap (, PagingMode, Buffer, 
, SIZE_2GB - SIZE_8KB, SIZE_8KB, , );
+  UT_ASSERT_EQUAL (Status, RETURN_SUCCESS);
+  

[edk2-devel] [Patch V4 08/21] UefiCpuPkg/CpuPageTableLib:Add check for Mask and Attr

[duntan]

For different usage, check if the combination for Mask and
Attr is valid when creating or updating page table.

1.For non-present range
  1.1Mask.Present is 0 but some other attributes is provided.
 This case is invalid.
  1.2Mask.Present is 1 and Attr.Present is 0. In this case,all
 other attributes should not be provided.
  1.3Mask.Present is 1 and Attr.Present is 1. In this case,all
 attributes should be provided to intialize the attribute.

2.For present range
  2.1Mask.Present is 1 and Attr.Present is 0.In this case, all
 other attributes should not be provided.
All other usage for present range is permitted.
In the mentioned cases, 1.2 and 2.1 can be merged into 1 check.

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
---
 UefiCpuPkg/Include/Library/CpuPageTableLib.h |  2 +-
 UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 79 
+--
 2 files changed, 78 insertions(+), 3 deletions(-)

diff --git a/UefiCpuPkg/Include/Library/CpuPageTableLib.h 
b/UefiCpuPkg/Include/Library/CpuPageTableLib.h
index 5f44ece548..6bda15b5bc 100644
--- a/UefiCpuPkg/Include/Library/CpuPageTableLib.h
+++ b/UefiCpuPkg/Include/Library/CpuPageTableLib.h
@@ -76,7 +76,7 @@ typedef enum {
   @param[in]  Mask   The mask used for attribute. The 
corresponding field in Attribute is ignored if that in Mask is 0.
 
   @retval RETURN_UNSUPPORTEDPagingMode is not supported.
-  @retval RETURN_INVALID_PARAMETER  PageTable, BufferSize, Attribute or Mask 
is NULL.
+  @retval RETURN_INVALID_PARAMETER  PageTable, BufferSize, Attribute or Mask 
is NULL or the combination of Attribute and Mask is invalid.
   @retval RETURN_INVALID_PARAMETER  *BufferSize is not multiple of 4KB.
   @retval RETURN_BUFFER_TOO_SMALL   The buffer is too small for page table 
creation/updating.
 BufferSize is updated to indicate the 
expected buffer size.
diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c 
b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
index 76febdd42d..2ad22b333d 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
@@ -215,6 +215,43 @@ PageTableLibSetPnle (
   Pnle->Bits.CacheDisabled = 0;
 }
 
+/**
+  Check if the combination for Attribute and Mask is valid for non-present 
entry.
+  1.Mask.Present is 0 but some other attributes is provided. This case should 
be invalid.
+  2.Map non-present range to present. In this case, all attributes should be 
provided.
+
+  @param[in] AttributeThe attribute of the linear address range.
+  @param[in] Mask The mask used for attribute to check.
+
+  @retval RETURN_INVALID_PARAMETERThe combination for Attribute and Mask 
is invalid.
+  @retval RETURN_SUCCESS  The combination for Attribute and Mask 
is valid.
+**/
+RETURN_STATUS
+IsAttributesAndMaskValidForNonPresentEntry (
+  IN IA32_MAP_ATTRIBUTE  *Attribute,
+  IN IA32_MAP_ATTRIBUTE  *Mask
+  )
+{
+  if ((Mask->Bits.Present == 1) && (Attribute->Bits.Present == 1)) {
+//
+// Creating new page table or remapping non-present range to present.
+//
+if ((Mask->Bits.ReadWrite == 0) || (Mask->Bits.UserSupervisor == 0) || 
(Mask->Bits.WriteThrough == 0) || (Mask->Bits.CacheDisabled == 0) ||
+(Mask->Bits.Accessed == 0) || (Mask->Bits.Dirty == 0) || 
(Mask->Bits.Pat == 0) || (Mask->Bits.Global == 0) ||
+(Mask->Bits.PageTableBaseAddress == 0) || (Mask->Bits.ProtectionKey == 
0) || (Mask->Bits.Nx == 0))
+{
+  return RETURN_INVALID_PARAMETER;
+}
+  } else if ((Mask->Bits.Present == 0) && (Mask->Uint64 > 1)) {
+//
+// Only change other attributes for non-present range is not permitted.
+//
+return RETURN_INVALID_PARAMETER;
+  }
+
+  return RETURN_SUCCESS;
+}
+
 /**
   Update page table to map [LinearAddress, LinearAddress + Length) with 
specified attribute in the specified level.
 
@@ -237,6 +274,7 @@ PageTableLibSetPnle (
 when a new physical base address is set.
   @param[in]  Mask  The mask used for attribute. The 
corresponding field in Attribute is ignored if that in Mask is 0.
 
+  @retval RETURN_INVALID_PARAMETER  The combination of Attribute and Mask for 
non-present entry is invalid.
   @retval RETURN_SUCCESSPageTable is created/updated successfully.
 **/
 RETURN_STATUS
@@ -260,6 +298,7 @@ PageTableLibMapInLevel (
   UINTN   Index;
   IA32_PAGING_ENTRY   *PagingEntry;
   UINTN   PagingEntryIndex;
+  UINTN   PagingEntryIndexEnd;
   IA32_PAGING_ENTRY   *CurrentPagingEntry;
   UINT64  RegionLength;
   UINT64  SubLength;
@@ -306,6 +345,14 @@ PageTableLibMapInLevel (
   //
 
   if (ParentPagingEntry->Pce.Present == 0) {
+//
+// [LinearAddress, LinearAddress + 

[edk2-devel] [Patch V4 07/21] UefiCpuPkg/MpInitLib: Add code to initialize MapMask

[duntan]

In function CreatePageTable(), add code to initialize MapMask to
MAX_UINT64. When creating new page table or map non-present range
to present, all attributes should be provided.

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
---
 UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c 
b/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c
index 7cf91ed9c4..f20068152b 100644
--- a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c
+++ b/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c
@@ -36,10 +36,7 @@ CreatePageTable (
   MapAttribute.Uint64 = Address;
   MapAttribute.Bits.Present   = 1;
   MapAttribute.Bits.ReadWrite = 1;
-
-  MapMask.Bits.PageTableBaseAddress = 1;
-  MapMask.Bits.Present  = 1;
-  MapMask.Bits.ReadWrite= 1;
+  MapMask.Uint64  = MAX_UINT64;
 
   PageTable   = 0;
   PageTableBufferSize = 0;
-- 
2.31.1.windows.1



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[edk2-devel] [Patch V4 06/21] UefiCpuPkg/CpuPageTableLib: Fix issue when splitting leaf entry

[duntan]

When splitting leaf parent entry to smaller granularity, create
child page table before modifing parent entry. In previous code
logic, when splitting a leaf parent entry, parent entry will
point to a null 4k memory before child page table is created in
this 4k memory. When the page table to be modified is the page
table in CR3, if the executed CpuPageTableLib code is in the
range mapped by the modified leaf parent entry, then issue will
happen.

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
---
 UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c 
b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
index cf0cfeca77..76febdd42d 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
@@ -363,8 +363,13 @@ PageTableLibMapInLevel (
   //
   // Create 512 child-level entries that map to 2M/4K.
   //
-  ParentPagingEntry->Uintn = (UINTN)Buffer + *BufferSize;
-  ZeroMem ((VOID *)ParentPagingEntry->Uintn, SIZE_4KB);
+  PagingEntry = (IA32_PAGING_ENTRY *)((UINTN)Buffer + *BufferSize);
+  ZeroMem (PagingEntry, SIZE_4KB);
+
+  for (SubOffset = 0, Index = 0; Index < 512; Index++) {
+PagingEntry[Index].Uint64 = OneOfPagingEntry.Uint64 + SubOffset;
+SubOffset+= RegionLength;
+  }
 
   //
   // Set NOP attributes
@@ -372,12 +377,7 @@ PageTableLibMapInLevel (
   //   will make the entire region read-only even the child entries 
set the RW bit.
   //
   PageTableLibSetPnle (>Pnle, , 
);
-
-  PagingEntry = (IA32_PAGING_ENTRY 
*)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (>Pnle);
-  for (SubOffset = 0, Index = 0; Index < 512; Index++) {
-PagingEntry[Index].Uint64 = OneOfPagingEntry.Uint64 + SubOffset;
-SubOffset+= RegionLength;
-  }
+  ParentPagingEntry->Uint64 = ((UINTN)(VOID *)PagingEntry) | 
(ParentPagingEntry->Uint64 & (~IA32_PE_BASE_ADDRESS_MASK_40));
 }
   } else {
 //
-- 
2.31.1.windows.1



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[edk2-devel] [Patch V4 05/21] UefiCpuPkg/CpuPageTableLib:Clear PageSize bit(Bit7) for non-leaf

[duntan]

Clear PageSize bit(Bit7) for non-leaf entry in PageTableLibSetPnle.
This function is used to set non-leaf entry attributes so it should
make sure that the PageSize bit of the entry should be 0.

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
---
 UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c 
b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
index ad68792ca8..cf0cfeca77 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
@@ -202,7 +202,8 @@ PageTableLibSetPnle (
 Pnle->Bits.Nx = Attribute->Bits.Nx;
   }
 
-  Pnle->Bits.Accessed = 0;
+  Pnle->Bits.Accessed   = 0;
+  Pnle->Bits.MustBeZero = 0;
 
   //
   // Set the attributes (WT, CD, A) to 0.
-- 
2.31.1.windows.1



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[edk2-devel] [Patch V4 04/21] UefiCpuPkg/CpuPageTableLib: Fix the non-1:1 mapping issue

[duntan]

In previous code logic, when splitting a leaf parent entry to
smaller granularity child page table, if the parent entry
Attribute(without PageTableBaseAddress field) is equal to the
input attribute(without PageTableBaseAddress field), the split
process won't happen. This may lead to failure in non-1:1 mapping.

For example, there is a page table in which [0, 1G] is mapped(Lv4[0]
,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry). And we
want to remap [0, 2M] linear address range to [1G, 1G + 2M] with the
same attibute. The expected behaviour should be: split Lv3[0,0]
entry into 512 level2 entries and remap the first level2 entry to
cover [0, 2M]. But the split won't happen in previous code since
PageTableBaseAddress of input Attribute is not checked.

So, when checking if a leaf parent entry needs to be splitted, we
should also check if PageTableBaseAddress calculated by parent entry
is equal to the value caculated by input attribute.

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
---
 UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c 
b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
index 127b65183f..ad68792ca8 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
@@ -274,6 +274,8 @@ PageTableLibMapInLevel (
   IA32_MAP_ATTRIBUTE  ChildMask;
   IA32_MAP_ATTRIBUTE  CurrentMask;
   IA32_MAP_ATTRIBUTE  LocalParentAttribute;
+  UINT64  PhysicalAddrInEntry;
+  UINT64  PhysicalAddrInAttr;
 
   ASSERT (Level != 0);
   ASSERT ((Attribute != NULL) && (Mask != NULL));
@@ -341,7 +343,15 @@ PageTableLibMapInLevel (
   // This function is called when the memory length is less than the 
region length of the parent level.
   // No need to split the page when the attributes equal.
   //
-  return RETURN_SUCCESS;
+  if (Mask->Bits.PageTableBaseAddress == 0) {
+return RETURN_SUCCESS;
+  }
+
+  PhysicalAddrInEntry = IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS 
() + PagingEntryIndex * RegionLength;
+  PhysicalAddrInAttr  = (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS 
(Attribute) + Offset) & (~RegionMask);
+  if (PhysicalAddrInEntry == PhysicalAddrInAttr) {
+return RETURN_SUCCESS;
+  }
 }
 
 ASSERT (Buffer == NULL || *BufferSize >= SIZE_4KB);
-- 
2.31.1.windows.1



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[edk2-devel] [Patch V4 03/21] UefiCpuPkg/CpuPageTableLib:Initialize some LocalVariable at beginning

[duntan]

Move some local variable initialization to the beginning of the
function. Also delete duplicated calculation for RegionLength.

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
---
 UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 21 -
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c 
b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
index 218068a3e1..127b65183f 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
@@ -258,6 +258,7 @@ PageTableLibMapInLevel (
   UINTN   BitStart;
   UINTN   Index;
   IA32_PAGING_ENTRY   *PagingEntry;
+  UINTN   PagingEntryIndex;
   IA32_PAGING_ENTRY   *CurrentPagingEntry;
   UINT64  RegionLength;
   UINT64  SubLength;
@@ -288,6 +289,14 @@ PageTableLibMapInLevel (
   LocalParentAttribute.Uint64 = ParentAttribute->Uint64;
   ParentAttribute = 
 
+  //
+  // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 21) 
or 4K (1 << 12).
+  //
+  BitStart = 12 + (Level - 1) * 9;
+  PagingEntryIndex = (UINTN)BitFieldRead64 (LinearAddress + Offset, BitStart, 
BitStart + 9 - 1);
+  RegionLength = REGION_LENGTH (Level);
+  RegionMask   = RegionLength - 1;
+
   //
   // ParentPagingEntry ONLY is deferenced for checking Present and MustBeOne 
bits
   // when Modify is FALSE.
@@ -353,8 +362,7 @@ PageTableLibMapInLevel (
   //
   PageTableLibSetPnle (>Pnle, , 
);
 
-  RegionLength = REGION_LENGTH (Level);
-  PagingEntry  = (IA32_PAGING_ENTRY 
*)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (>Pnle);
+  PagingEntry = (IA32_PAGING_ENTRY 
*)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (>Pnle);
   for (SubOffset = 0, Index = 0; Index < 512; Index++) {
 PagingEntry[Index].Uint64 = OneOfPagingEntry.Uint64 + SubOffset;
 SubOffset+= RegionLength;
@@ -425,15 +433,10 @@ PageTableLibMapInLevel (
   }
 
   //
-  // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 21) 
or 4K (1 << 12).
   // RegionStart:  points to the linear address that's aligned on RegionLength 
and lower than (LinearAddress + Offset).
   //
-  BitStart = 12 + (Level - 1) * 9;
-  Index= (UINTN)BitFieldRead64 (LinearAddress + Offset, BitStart, 
BitStart + 9 - 1);
-  RegionLength = LShiftU64 (1, BitStart);
-  RegionMask   = RegionLength - 1;
-  RegionStart  = (LinearAddress + Offset) & ~RegionMask;
-
+  Index   = PagingEntryIndex;
+  RegionStart = (LinearAddress + Offset) & ~RegionMask;
   ParentAttribute->Uint64 = PageTableLibGetPnleMapAttribute 
(>Pnle, ParentAttribute);
 
   //
-- 
2.31.1.windows.1



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[edk2-devel] [Patch V4 02/21] UefiCpuPkg/CpuPageTableLib: Add check for input Length

[duntan]

Add check for input Length in PageTableMap (). Return
RETURN_SUCCESS when input Length is 0.

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
---
 UefiCpuPkg/Include/Library/CpuPageTableLib.h | 4 ++--
 UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 6 +-
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/UefiCpuPkg/Include/Library/CpuPageTableLib.h 
b/UefiCpuPkg/Include/Library/CpuPageTableLib.h
index 2dc9b7d18e..5f44ece548 100644
--- a/UefiCpuPkg/Include/Library/CpuPageTableLib.h
+++ b/UefiCpuPkg/Include/Library/CpuPageTableLib.h
@@ -1,7 +1,7 @@
 /** @file
   Public include file for PageTableLib library.
 
-  Copyright (c) 2022, Intel Corporation. All rights reserved.
+  Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -81,7 +81,7 @@ typedef enum {
   @retval RETURN_BUFFER_TOO_SMALL   The buffer is too small for page table 
creation/updating.
 BufferSize is updated to indicate the 
expected buffer size.
 Caller may still get 
RETURN_BUFFER_TOO_SMALL with the new BufferSize.
-  @retval RETURN_SUCCESSPageTable is created/updated successfully.
+  @retval RETURN_SUCCESSPageTable is created/updated successfully 
or the input Length is 0.
 **/
 RETURN_STATUS
 EFIAPI
diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c 
b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
index 52535e5a8d..218068a3e1 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
@@ -544,7 +544,7 @@ PageTableLibMapInLevel (
   @retval RETURN_BUFFER_TOO_SMALL   The buffer is too small for page table 
creation/updating.
 BufferSize is updated to indicate the 
expected buffer size.
 Caller may still get 
RETURN_BUFFER_TOO_SMALL with the new BufferSize.
-  @retval RETURN_SUCCESSPageTable is created/updated successfully.
+  @retval RETURN_SUCCESSPageTable is created/updated successfully 
or the input Length is 0.
 **/
 RETURN_STATUS
 EFIAPI
@@ -567,6 +567,10 @@ PageTableMap (
   IA32_PAGE_LEVEL MaxLeafLevel;
   IA32_MAP_ATTRIBUTE  ParentAttribute;
 
+  if (Length == 0) {
+return RETURN_SUCCESS;
+  }
+
   if ((PagingMode == Paging32bit) || (PagingMode == PagingPae) || (PagingMode 
>= PagingModeMax)) {
 //
 // 32bit paging is never supported.
-- 
2.31.1.windows.1



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[edk2-devel] [Patch V4 01/21] UefiCpuPkg/CpuPageTableLib: Remove unneeded 'if' condition

[duntan]

Remove unneeded 'if' condition in CpuPageTableLib code.
The deleted code is in the code branch for present non-leaf parent
entry. So the 'if' check for (ParentPagingEntry->Pnle.Bits.Present
== 0) is always FALSE.

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Reviewed-by: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
---
 UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 11 +--
 1 file changed, 1 insertion(+), 10 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c 
b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
index 37713ec659..52535e5a8d 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
@@ -1,7 +1,7 @@
 /** @file
   This library implements CpuPageTableLib that are generic for IA32 family CPU.
 
-  Copyright (c) 2022, Intel Corporation. All rights reserved.
+  Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -375,15 +375,6 @@ PageTableLibMapInLevel (
 //we need to change PDPTE[0].ReadWrite = 1 and let all 
PDE[0-255].ReadWrite = 0 in this step.
 //   when PDPTE[0].Nx = 1 but caller wants to map [0-2MB] as Nx = 0 
(PDT[0].Nx = 0)
 //we need to change PDPTE[0].Nx = 0 and let all PDE[0-255].Nx 
= 1 in this step.
-if ((ParentPagingEntry->Pnle.Bits.Present == 0) && (Mask->Bits.Present == 
1) && (Attribute->Bits.Present == 1)) {
-  if (Modify) {
-ParentPagingEntry->Pnle.Bits.Present = 1;
-  }
-
-  ChildAttribute.Bits.Present = 0;
-  ChildMask.Bits.Present  = 1;
-}
-
 if ((ParentPagingEntry->Pnle.Bits.ReadWrite == 0) && (Mask->Bits.ReadWrite 
== 1) && (Attribute->Bits.ReadWrite == 1)) {
   if (Modify) {
 ParentPagingEntry->Pnle.Bits.ReadWrite = 1;
-- 
2.31.1.windows.1



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[edk2-devel] [Patch V4 00/21] Fix issues in CpuPageTableLib

[duntan]

In the V4 atch set
1. In the patch "UefiCpuPkg/MpInitLib: Add code to initialize MapMask", add 
code to set MapMask to MAX_UINT64 to fix the boot failure tested by Gred.
2. Add patches to enable PAE paing in CpuPageTable Lib and add random test for 
PAE paging
3. Add patch to reduce the number of random test since CI may timeout
4. Modify the patch to fix non-1:1 mapping issue

Dun Tan (19):
  UefiCpuPkg/CpuPageTableLib: Remove unneeded 'if' condition
  UefiCpuPkg/CpuPageTableLib: Add check for input Length
  UefiCpuPkg/CpuPageTableLib:Initialize some LocalVariable at beginning
  UefiCpuPkg/CpuPageTableLib: Fix the non-1:1 mapping issue
  UefiCpuPkg/CpuPageTableLib:Clear PageSize bit(Bit7) for non-leaf
  UefiCpuPkg/CpuPageTableLib: Fix issue when splitting leaf entry
  UefiCpuPkg/MpInitLib: Add code to initialize MapMask
  UefiCpuPkg/CpuPageTableLib:Add check for Mask and Attr
  UefiCpuPkg/CpuPageTableLib: Add manual test to check Mask and Attr
  UefiCpuPkg/CpuPageTableLib:Modify RandomBoolean() in RandomTest
  UefiCpuPkg/CpuPageTableLib:Modify RandomTest to check Mask/Attr
  UefiCpuPkg/CpuPageTableLib: Enable non-1:1 mapping in random test
  UefiCpuPkg/CpuPageTableLib: Add OUTPUT IsModified parameter.
  UefiCpuPkg/CpuPageTableLib: Modify RandomTest to check IsModified
  UefiCpuPkg/CpuPageTableLib: Add check for page table creation
  UefiCpuPkg: Combine branch for non-present and leaf ParentEntry
  UefiCpuPkg/CpuPageTableLib: Enable PAE paging
  UefiCpuPkg/CpuPageTableLib: Add RandomTest for PAE paging
  UefiCpuPkg/CpuPageTableLib: Reduce the number of random tests

Zhiguang Liu (2):
  UefiCpuPkg: Fix IA32 build failure in CpuPageTableLib.inf
  UefiCpuPkg: Modify UnitTest code since tested API is changed

 UefiCpuPkg/Include/Library/CpuPageTableLib.h  |  
42 ++
 UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h | 
135 
++-
 UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c  | 
312 

 UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableParse.c|  
25 +
 UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c | 
225 
+++--
 UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c  | 
323 
---
 UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c  |  
22 +++---
 UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c|  
11 +--
 8 files changed, 768 insertions(+), 327 deletions(-)

-- 
2.31.1.windows.1



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[edk2-devel] [PATCH v3 3/3] Maintainers.txt: Adds AMD/MinBoardPkg maintainers

[Abdul Lateef Attar via groups.io]

From: Abdul Lateef Attar 

Adds maintainers for AMD/MinBoardPkg

Signed-off-by: Abdul Lateef Attar 
Cc: Ard Biesheuvel 
Cc: Leif Lindholm 
Cc: Abner Chang 
Cc: Michael D Kinney 
---
 Maintainers.txt | 5 +
 1 file changed, 5 insertions(+)

diff --git a/Maintainers.txt b/Maintainers.txt
index 747191366070..3ce578abcf7e 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -91,6 +91,11 @@ F: Silicon/AMD/Styx/
 M: Ard Biesheuvel 
 M: Leif Lindholm 
 
+AMD MinBoard package for MinPlatformPkg
+F: Platform/AMD/MinBoardPkg
+M: Abner Chang 
+M: Abdul Lateef Attar 
+
 Ampere Computing
 F: Platform/Ampere
 F: Silicon/Ampere
-- 
2.25.1



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[edk2-devel] [PATCH v3 2/3] Platform/AMD/MinBoardPkg: Adds SetCacheMtrrLib library

[Abdul Lateef Attar via groups.io]

Adds SetCacheMtrrLib library for MinBoardPkg,
which sets MTRR values for PEI phase and also
modifies the MTRR value at the end of PEI phase.

Signed-off-by: Abdul Lateef Attar 
Cc: Ard Biesheuvel 
Cc: Leif Lindholm 
Cc: Abner Chang 
Cc: Michael D Kinney 
---
 Platform/AMD/MinBoardPkg/MinBoardPkg.dsc  |   9 ++
 .../SetCacheMtrrLib/SetCacheMtrrLib.inf   |  37 +
 .../Library/SetCacheMtrrLib/SetCacheMtrrLib.c | 133 ++
 3 files changed, 179 insertions(+)
 create mode 100644 
Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
 create mode 100644 
Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c

diff --git a/Platform/AMD/MinBoardPkg/MinBoardPkg.dsc 
b/Platform/AMD/MinBoardPkg/MinBoardPkg.dsc
index 8c120c0649e7..810fac7aa9de 100644
--- a/Platform/AMD/MinBoardPkg/MinBoardPkg.dsc
+++ b/Platform/AMD/MinBoardPkg/MinBoardPkg.dsc
@@ -17,5 +17,14 @@ [Defines]
   SUPPORTED_ARCHITECTURES = IA32 | X64
 
 [Packages]
+  MdePkg/MdePkg.dec
   MinBoardPkg/MinBoardPkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses.common.PEIM]
+  SetCacheMtrrLib|MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
+
+[Components.IA32]
+  MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
 
diff --git 
a/Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf 
b/Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
new file mode 100644
index ..add2e71651f9
--- /dev/null
+++ b/Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
@@ -0,0 +1,37 @@
+## @file
+# Component information file for Platform SetCacheMtrr Library.
+# This library implementation is for AMD processor based platforms.
+#
+# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 1.29
+  BASE_NAME  = PeiSetCacheMtrrLib
+  FILE_GUID  = 1E8468E0-5EB4-4088-9B52-BFDC6E4DAE87
+  MODULE_TYPE= PEIM
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = SetCacheMtrrLib
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  MtrrLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[Sources]
+  SetCacheMtrrLib.c
+
+[Guids]
+
+[Pcd]
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize
+
diff --git a/Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c 
b/Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c
new file mode 100644
index ..33b774fedbd3
--- /dev/null
+++ b/Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c
@@ -0,0 +1,133 @@
+/** @file
+
+SetCacheMtrr library functions.
+This library implementation is for AMD processor based platforms.
+
+Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+
+/**
+  This function sets the cache MTRR values for PEI phase.
+**/
+VOID
+EFIAPI
+SetCacheMtrr (
+  VOID
+  )
+{
+  EFI_STATUS  Status;
+
+  Status = MtrrSetMemoryAttribute (
+ 0,
+ 0xA,
+ CacheWriteBack
+ );
+  if (EFI_ERROR (Status)) {
+DEBUG ((
+  DEBUG_ERROR,
+  "Error(%r) in setting CacheWriteBack for 0-0x9\n",
+  Status
+  ));
+  }
+
+  Status = MtrrSetMemoryAttribute (
+ 0xA,
+ 0x2,
+ CacheUncacheable
+ );
+  if (EFI_ERROR (Status)) {
+DEBUG ((
+  DEBUG_ERROR,
+  "Error(%r) in setting CacheUncacheable for 0xA-0xB\n",
+  Status
+  ));
+  }
+
+  Status = MtrrSetMemoryAttribute (
+ 0xC,
+ 0x4,
+ CacheWriteProtected
+ );
+  if (EFI_ERROR (Status)) {
+DEBUG ((
+  DEBUG_ERROR,
+  "Error(%r) in setting CacheWriteProtected for 0xC-0xF\n",
+  Status
+  ));
+  }
+
+  Status = MtrrSetMemoryAttribute (
+ 0x10,
+ 0xAFF0,
+ CacheWriteBack
+ );
+  if (EFI_ERROR (Status)) {
+DEBUG ((
+  DEBUG_ERROR,
+  "Error(%r) in setting CacheWriteBack for 0x10-0xAFFF\n",
+  Status
+  ));
+  }
+
+  Status = MtrrSetMemoryAttribute (
+ PcdGet32 (PcdFlashAreaBaseAddress),
+ PcdGet32 (PcdFlashAreaSize),
+ CacheWriteProtected
+ );
+  if (EFI_ERROR (Status)) {
+DEBUG ((
+  DEBUG_ERROR,
+  "Error(%r) in setting CacheWriteProtected for 0x%X-0x%X\n",
+  Status,
+  PcdGet32 (PcdFlashAreaBaseAddress),
+  PcdGet32 (PcdFlashAreaBaseAddress) + PcdGet32 (PcdFlashAreaSize)
+  ));
+  }
+
+  MtrrDebugPrintAllMtrrs ();
+  return;
+}
+
+/**
+  Update MTRR setting in EndOfPei phase.
+  This function 

[edk2-devel] [PATCH v3 1/3] Platform/AMD: Adds MinBoardPkg to support MinPlatformPkg

[Abdul Lateef Attar via groups.io]

Adds initial DEC and DSC file for MinBoardPkg.
This package provides supporting modules for AMD boards to
leverage MinPlatformPkg framework.

Signed-off-by: Abdul Lateef Attar 
Cc: Ard Biesheuvel 
Cc: Leif Lindholm 
Cc: Abner Chang 
Cc: Michael D Kinney 
---
 Platform/AMD/MinBoardPkg/MinBoardPkg.dec | 19 +++
 Platform/AMD/MinBoardPkg/MinBoardPkg.dsc | 21 +
 2 files changed, 40 insertions(+)
 create mode 100644 Platform/AMD/MinBoardPkg/MinBoardPkg.dec
 create mode 100644 Platform/AMD/MinBoardPkg/MinBoardPkg.dsc

diff --git a/Platform/AMD/MinBoardPkg/MinBoardPkg.dec 
b/Platform/AMD/MinBoardPkg/MinBoardPkg.dec
new file mode 100644
index ..23d737d196a2
--- /dev/null
+++ b/Platform/AMD/MinBoardPkg/MinBoardPkg.dec
@@ -0,0 +1,19 @@
+## @file MinBoardPkg.dec
+#  Declaration file for AMD's MinBoardPkg.
+#
+#  This package supports AMD processor family based board as per the 
MinPlatform
+#  Arch specification.
+#
+#  Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#  @par Specification Reference:
+#   -https://tianocore-docs.github.io/edk2-MinimumPlatformSpecification/draft/ 
0.7
+##
+
+[Defines]
+  DEC_SPECIFICATION  = 1.27
+  PACKAGE_NAME   = MinBoardPkg
+  PACKAGE_GUID   = 44F9D761-9ECB-43DD-A5AC-177E5048701B
+  PACKAGE_VERSION= 0.1
+
diff --git a/Platform/AMD/MinBoardPkg/MinBoardPkg.dsc 
b/Platform/AMD/MinBoardPkg/MinBoardPkg.dsc
new file mode 100644
index ..8c120c0649e7
--- /dev/null
+++ b/Platform/AMD/MinBoardPkg/MinBoardPkg.dsc
@@ -0,0 +1,21 @@
+## @file
+#  MinBoardPkg.dsc
+#
+#  Description file for AMD MinBoardPkg
+#
+#  Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+  DSC_SPECIFICATION   = 1.30
+  PLATFORM_GUID   = 88F8A9AE-2FA0-4D58-A6F9-05F635C05F4E
+  PLATFORM_NAME   = MinBoardPkg
+  PLATFORM_VERSION= 0.1
+  OUTPUT_DIRECTORY= Build/$(PLATFORM_NAME)
+  BUILD_TARGETS   = DEBUG | RELEASE | NOOPT
+  SUPPORTED_ARCHITECTURES = IA32 | X64
+
+[Packages]
+  MinBoardPkg/MinBoardPkg.dec
+
-- 
2.25.1



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[edk2-devel] [PATCH v3 0/3] Adds Platform/AMD/MinBoardPkg

[Abdul Lateef Attar via groups.io]

V3 changes:
  Dropped the PlatformPkg package.
  Rename BoardPkg to MinBoardPkg
  Addressed review comments from Leif and Abner.

Adds AMD/MinBoardPkg to support MinPlatformPkg framework.

PR: https://github.com/tianocore/edk2-platforms/pull/72

Cc: Ard Biesheuvel 
Cc: Leif Lindholm 
Cc: Abner Chang 
Cc: Michael D Kinney 
Cc: Abdul Lateef Attar 

Abdul Lateef Attar (3):
  Platform/AMD: Adds MinBoardPkg to support MinPlatformPkg
  Platform/AMD/MinBoardPkg: Adds SetCacheMtrrLib library
  Maintainers.txt: Adds AMD/MinBoardPkg maintainers

 Platform/AMD/MinBoardPkg/MinBoardPkg.dec  |  19 +++
 Platform/AMD/MinBoardPkg/MinBoardPkg.dsc  |  30 
 .../SetCacheMtrrLib/SetCacheMtrrLib.inf   |  37 +
 .../Library/SetCacheMtrrLib/SetCacheMtrrLib.c | 133 ++
 Maintainers.txt   |   5 +
 5 files changed, 224 insertions(+)
 create mode 100644 Platform/AMD/MinBoardPkg/MinBoardPkg.dec
 create mode 100644 Platform/AMD/MinBoardPkg/MinBoardPkg.dsc
 create mode 100644 
Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
 create mode 100644 
Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c

-- 
2.25.1



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