Re: Visibility of RISCV_BOOT_HARTID
On Thu, Oct 13, 2022 at 2:18 AM wrote: > > > On Thu, 2022-10-13 at 06:27 +0200, Sebastian Huber wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you > > know the content is safe > > > > On 12/10/2022 16:36, Joel Sherrill wrote: > > > Hi > > > > > > I was looking at the bsp default settings for sparc/leon3 to show > > > someone and noticed this which is out of place. > > > > > > # boot hartid (processor number) of risc-v cpu (default 0) > > > RISCV_BOOT_HARTID = 0 > > > > > > I looked around and see it is an architecture specific ini setting > > > but > > > placed in a directory with architecture independent settings. We > > > don't > > > appear to have any other examples of a cpukit option that is > > > architecture specific. So it is lumped in with all the architecture > > > independent ini settings. > > > > This was easy to fix: > > > > > https://git.rtems.org/rtems/commit/?id=97fce5120c08180a86301b03e61d0a06db5f8b9b > > > Oh... I didn't see it and tried different way. > > > We had long discussions about presenting these options with better > > > names, documentation, etc as part of the waf transition. Seems > > > unfortunate to have this show up in all configurations. > > > > > > Any thoughts on how to clean this up? > > > > It would be nice if more developers could invest some time to learn > > how > > the build system works. > > Yes.. need to learn more about the build system. > Agreed. I came across this while teaching an RTEMS class and admit I didn't even begin to think about a solution. When I spot something while teaching, if it is more than a spelling or grammar error, I make a note of it. I usually just report it during the class week. Thanks to both of you for responding and Sebastian for fixing it. --joel > > Regards > Padmarao > > > > -- > > embedded brains GmbH > > Herr Sebastian HUBER > > Dornierstr. 4 > > 82178 Puchheim > > Germany > > email: sebastian.hu...@embedded-brains.de > > phone: +49-89-18 94 741 - 16 > > fax: +49-89-18 94 741 - 08 > > > > Registergericht: Amtsgericht München > > Registernummer: HRB 157899 > > Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas > > Dörfler > > Unsere Datenschutzerklärung finden Sie hier: > > https://embedded-brains.de/datenschutzerklaerung/ > > ___ > > devel mailing list > > devel@rtems.org > > http://lists.rtems.org/mailman/listinfo/devel > ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: Visibility of RISCV_BOOT_HARTID
> On Thu, 2022-10-13 at 06:27 +0200, Sebastian Huber wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you > know the content is safe > > On 12/10/2022 16:36, Joel Sherrill wrote: > > Hi > > > > I was looking at the bsp default settings for sparc/leon3 to show > > someone and noticed this which is out of place. > > > > # boot hartid (processor number) of risc-v cpu (default 0) > > RISCV_BOOT_HARTID = 0 > > > > I looked around and see it is an architecture specific ini setting > > but > > placed in a directory with architecture independent settings. We > > don't > > appear to have any other examples of a cpukit option that is > > architecture specific. So it is lumped in with all the architecture > > independent ini settings. > > This was easy to fix: > > https://git.rtems.org/rtems/commit/?id=97fce5120c08180a86301b03e61d0a06db5f8b9b > Oh... I didn't see it and tried different way. > > We had long discussions about presenting these options with better > > names, documentation, etc as part of the waf transition. Seems > > unfortunate to have this show up in all configurations. > > > > Any thoughts on how to clean this up? > > It would be nice if more developers could invest some time to learn > how > the build system works. Yes.. need to learn more about the build system. Regards Padmarao > > -- > embedded brains GmbH > Herr Sebastian HUBER > Dornierstr. 4 > 82178 Puchheim > Germany > email: sebastian.hu...@embedded-brains.de > phone: +49-89-18 94 741 - 16 > fax: +49-89-18 94 741 - 08 > > Registergericht: Amtsgericht München > Registernummer: HRB 157899 > Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas > Dörfler > Unsere Datenschutzerklärung finden Sie hier: > https://embedded-brains.de/datenschutzerklaerung/ > ___ > devel mailing list > devel@rtems.org > http://lists.rtems.org/mailman/listinfo/devel ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: Visibility of RISCV_BOOT_HARTID
Hi Joel,
We can do like below to remove visibility of RISCV_BOOT_HARTID from
other architecture configurations and only visible to RISC-V.
Changes in spec/build/cpukits
1. Remove "optboothartid" build-dependency from "cpuotps"
2. Add the "cpuriscvhartid" to generate the "hartid.h" using "optbootha
rtid
"
3. Link "cpuriscvhartid" build-dependency in "cpuriscv"
4. Include "hartid.h" in "cpukit/score/cpu/riscv/include/rtems/score/ri
scv.h"
I have modified the RTEMS source like below
**
cpukit/score/cpu/riscv/include/rtems/score/riscv.h | 2 ++
spec/build/cpukit/cpuopts.yml | 2 --
spec/build/cpukit/cpuriscv.yml | 4 +++-
spec/build/cpukit/cpuriscvhartid.yml | 13 +
4 files changed, 18 insertions(+), 3 deletions(-)
create mode 100644 spec/build/cpukit/cpuriscvhartid.yml
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/riscv.h
b/cpukit/score/cpu/riscv/include/rtems/score/riscv.h
index f770578715..3e0169981b 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/riscv.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/riscv.h
@@ -36,6 +36,8 @@
#ifndef _RTEMS_SCORE_RISCV_H
#define _RTEMS_SCORE_RISCV_H
+#include
+
#ifdef __cplusplus
extern "C" {
#endif
diff --git a/spec/build/cpukit/cpuopts.yml
b/spec/build/cpukit/cpuopts.yml
index dcfca62d05..86cc7f676a 100644
--- a/spec/build/cpukit/cpuopts.yml
+++ b/spec/build/cpukit/cpuopts.yml
@@ -33,8 +33,6 @@ links:
uid: optinstall
- role: build-dependency
uid: optada
-- role: build-dependency
- uid: optboothartid
- role: build-dependency
uid: optbuildlabel
- role: build-dependency
diff --git a/spec/build/cpukit/cpuriscv.yml
b/spec/build/cpukit/cpuriscv.yml
index 2671c5c5f0..c8365e550a 100644
--- a/spec/build/cpukit/cpuriscv.yml
+++ b/spec/build/cpukit/cpuriscv.yml
@@ -24,7 +24,9 @@ install:
- cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
- cpukit/score/cpu/riscv/include/rtems/score/riscv-utility.h
- cpukit/score/cpu/riscv/include/rtems/score/riscv.h
-links: []
+links:
+- role: build-dependency
+ uid: cpuriscvhartid
source:
- cpukit/score/cpu/riscv/cpu.c
- cpukit/score/cpu/riscv/riscv-context-initialize.c
diff --git a/spec/build/cpukit/cpuriscvhartid.yml
b/spec/build/cpukit/cpuriscvhartid.yml
new file mode 100644
index 00..60f22bd3bd
--- /dev/null
+++ b/spec/build/cpukit/cpuriscvhartid.yml
@@ -0,0 +1,13 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: config-header
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (
http://www.embedded-brains.de)
+enabled-by: true
+guard: _RTEMS_SCORE_HARTID_H
+include-headers: []
+install-path: ${BSP_INCLUDEDIR}/rtems/score
+links:
+- role: build-dependency
+ uid: optboothartid
+target: cpukit/include/rtems/score/hartid.h
+type: build
\ No newline at end of file
--
2.25.1
***
Regards
Padmarao
On Wed, 2022-10-12 at 09:36 -0500, Joel Sherrill wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> Hi
>
> I was looking at the bsp default settings for sparc/leon3 to show
> someone and noticed this which is out of place.
>
> # boot hartid (processor number) of risc-v cpu (default 0)
> RISCV_BOOT_HARTID = 0
>
> I looked around and see it is an architecture specific ini setting
> but placed in a directory with architecture independent settings. We
> don't appear to have any other examples of a cpukit option that is
> architecture specific. So it is lumped in with all the architecture
> independent ini settings.
>
> We had long discussions about presenting these options with better
> names, documentation, etc as part of the waf transition. Seems
> unfortunate to have this show up in all configurations.
>
> Any thoughts on how to clean this up?
>
> Thanks.
>
> --joel
>
>
> ___
> devel mailing list
> devel@rtems.org
> http://lists.rtems.org/mailman/listinfo/devel
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
Re: Visibility of RISCV_BOOT_HARTID
On 12/10/2022 16:36, Joel Sherrill wrote: Hi I was looking at the bsp default settings for sparc/leon3 to show someone and noticed this which is out of place. # boot hartid (processor number) of risc-v cpu (default 0) RISCV_BOOT_HARTID = 0 I looked around and see it is an architecture specific ini setting but placed in a directory with architecture independent settings. We don't appear to have any other examples of a cpukit option that is architecture specific. So it is lumped in with all the architecture independent ini settings. This was easy to fix: https://git.rtems.org/rtems/commit/?id=97fce5120c08180a86301b03e61d0a06db5f8b9b We had long discussions about presenting these options with better names, documentation, etc as part of the waf transition. Seems unfortunate to have this show up in all configurations. Any thoughts on how to clean this up? It would be nice if more developers could invest some time to learn how the build system works. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
RE: Visibility of RISCV_BOOT_HARTID
Hi Joel,This is relevant to my interests since I am working on a RISC-V BSP variant and I am adding a few options in the spec/build/bsps/riscv/riscv directory.Could this instance be fixed by moving it to the spec/build/bsps/riscv directory?Regards,AlanFrom: Joel SherrillSent: Wednesday, October 12, 2022 10:36 AMTo: rtems-de...@rtems.orgSubject: Visibility of RISCV_BOOT_HARTID Hi I was looking at the bsp default settings for sparc/leon3 to show someone and noticed this which is out of place. # boot hartid (processor number) of risc-v cpu (default 0)RISCV_BOOT_HARTID = 0 I looked around and see it is an architecture specific ini setting but placed in a directory with architecture independent settings. We don't appear to have any other examples of a cpukit option that is architecture specific. So it is lumped in with all the architecture independent ini settings. We had long discussions about presenting these options with better names, documentation, etc as part of the waf transition. Seems unfortunate to have this show up in all configurations. Any thoughts on how to clean this up? Thanks. --joel ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
