basic blt programming on ATI Radeon
Hi,
I am writing a blt funtion to transfer a rectangular area
image data from offscreen to onscreen on ATI Radeon 7500
graphic card. But after lots of tries, I still couldn't
see the image on my screen.:( Can someone help me check
this out ?
>From the blt example code ( for windows) provided by ATI doc,
the major steps include Radeon initialization, reading
image data to (src_x, src_y) in frame buffer, setting bunch
of related registers, and then initiating the blt operation
by setting the initiator register.
The resolution is set to 800x600x8. The following is my code.
+
/* Initialization */
xres = 800;
yres = 600;
img_bpp = 8;
bytepp = (img_bpp + 1)/8;
pitch = ((xres * bytepp + 0x3f) & ~(0x3f))/64;
byte_pitch = pitch * 64;
... ...
/* copy image data from system memory to src_x, src_y
* rectangular area in frame buffer. Variable dinfo is
* a structure used to save image infomation. Image
* data is saved linearly in system memory.
*/
width = dinfo->img_width[blt_index];
height = dinfo->img_height[blt_index];
src_x = 0;
src_y = 600;
dstaddr = (char *) (agp_dev.vga_base + byte_pitch * src_y + src_x);
srcaddr = (char *) (image_data_base + dinfo->img_offset[blt_index]);
for(i=0; iright, top->bottom
temp = readl(agp_dev.reg_base + DP_CNTL);
writel (0x03|temp, agp_dev.reg_base + DP_CNTL);
// make the src pixel = dst pixel = 8bpp pseudocolor
temp = readl (agp_dev.reg_base + DP_DATATYPE);
writel ( temp|0x00030002 ,agp_dev.reg_base + DP_DATATYPE);
Radeon_WaitForFifo (2);
// set destination x and y values
writel ((dst_y << 16 ) | dst_x, agp_dev.reg_base + DST_Y_X);
// this is the blt initiator.
writel (width | (height << 16 ), agp_dev.reg_base +
DST_HEIGHT_WIDTH);
... ...
++
void Radeon_WaitForFifo (dword entries)
{
while ((readl(agp_dev.reg_base + RBBM_STATUS) & 0x007f) <
entries)
{
printk("\nNo enough entries in command FIFO.\n");
}
return;
}
++
Questions:
1. Is Radeon_WaitForFifo necessary if there are enough entries
in command fifo?
2. If command fifo full, does that mean I cannot set registers
successfully until needed entries are available?
3. Do I have to set some registers at "Radeon initialization"
step?
4. What's the problem with my code?
Thanks in advance,
jing
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kernel paging problem
Hi,guys, My graphic card is ATI radeon 7500 with 128M memory. I want to write several megabytes image data into video memory for later use. But everytime when I tried to write data more than 512kB, the system generated following error: ++ Unable to handle kernel paging request at virtual address e8ad3000 printing eip: e88ce4b1 *pde = 01922067 *pte = Oops: 0002 CPU:0 EIP:0010:[]Not tainted EFLAGS: 00010283 eax: a3a3a3a3 ebx: 0008 ecx: 0001 edx: e88d3000 esi: e8d0f8a8 edi: ad00 ebp: d9cf3f24 esp: d9cf3ecc ds: 0018 es: 0018 ss: 0018 Process stim (pid: 1334, stackpage=d9cf3000) Stack: 0005 db201000 0feb 2140 09d0 11a0 32e0 32e0 32e0 0001d4c0 0008 0004 0325 0004 d9cf3f5c 000c e88a5100 e88a5118 0246 e88a5100 e88a5118 e88a34d6 Call Trace: [] [] [] [] [] [] [] [] [] Code: 89 04 9a 8b 44 be 04 89 44 9a 04 8b 44 be 08 89 44 9a 08 8b UNMAPPING AREA AT KERNEL REQUEST. UNMAPPING AREA AT KERNEL REQUEST. UNMAPPING AREA AT KERNEL REQUEST. +++ What's this kernel paging problem about? Can anyone give me some hints? Thanks in advance, jing ___ Devel mailing list [EMAIL PROTECTED] http://XFree86.Org/mailman/listinfo/devel
Re: bitblt operation in frame buffer
Hi, Michel, Thank you so much for your information. I tried to set those registers you told me, but my bitblt operation still doesn't work. What confused me is that how the graphic card knows that the source image is saved with lineal trajectory instead of rectangular trajectory? Because it seems that register DP_SRC_SOURCE should be the one to set how the source image is saved, but there is no option for saving source image in frame buffer with lineal trajectory which is what I really want. Do you have any idea about this? Thanks again, jing Quoting Michel Dänzer <[EMAIL PROTECTED]>: > On Fre, 2003-02-07 at 07:55, [EMAIL PROTECTED] wrote: > > > > I want to transfer a block of image data from source offset in > > off_screen to a specified rectangular area in on_screen area. > > If the source image is saved with rectangular trajectory, > > I can set some registers such as SRC_Y_X, DR_MIX, > > DP_CNTL,DST_Y_X and DST_HEIGHT_WIDTH to transfer pixels from > > SRC_Y_X to DST_Y_X. However, in order to save memory space, I > > want to save the image data in frame buffer with lineal > > trajectory instead of a rectangular area. Can I still transfer > > the image pixels by just setting some registers? > > > > If I can, which register is for src offset? > > (I assume this is about Radeons) > > The GMC_SRC_PITCH_OFFSET_CNTL bit in the DP_GUI_MASTER_CNTL register > controls whether the default offset, pitch and tiling are used for > the > source or whether the SRC_PITCH_OFFSET register is used. > > > Hope this helps, > > > -- > Earthling Michel Dänzer (MrCooper)/ Debian GNU/Linux (powerpc) > developer > XFree86 and DRI project member / CS student, Free Software > enthusiast > > ___ > Devel mailing list > [EMAIL PROTECTED] > http://XFree86.Org/mailman/listinfo/devel > ___ Devel mailing list [EMAIL PROTECTED] http://XFree86.Org/mailman/listinfo/devel
bitblt operation in frame buffer
Hi, I want to transfer a block of image data from source offset in off_screen to a specified rectangular area in on_screen area. If the source image is saved with rectangular trajectory, I can set some registers such as SRC_Y_X, DR_MIX, DP_CNTL,DST_Y_X and DST_HEIGHT_WIDTH to transfer pixels from SRC_Y_X to DST_Y_X. However, in order to save memory space, I want to save the image data in frame buffer with lineal trajectory instead of a rectangular area. Can I still transfer the image pixels by just setting some registers? If I can, which register is for src offset? If cannot, a possible value of register DP_SRC_SOURCE is "hostdata,lineal trajectory", and I guess it means that I can set some register value to source address, in which image data is saved in continuous address in host memory. But what is this register? I had a tough time to find it. :( Thank you so~~~ much, jing ___ Devel mailing list [EMAIL PROTECTED] http://XFree86.Org/mailman/listinfo/devel
a question about register CRT_OFFSET of ATI Radeon 7500
Hi, I want to change graphic surface origin offset in video memory of my ATI Radeon card by changing the value of register CRTC_OFFSET. Does the change occur on the screen immediately or not until it synchronizes with VSYNC? thanks a lot, jing ___ Devel mailing list [EMAIL PROTECTED] http://XFree86.Org/mailman/listinfo/devel
register for video memory
Hi, I am looking for the registers that can specify the video memory's offset where the image is shown on the screen. Does this register exist? If it does, can someone tell me any hint or keyword so that I can search it in related data sheets? My graphic card is ATI Radeon 7500. Thanks in advance, jing ___ Devel mailing list [EMAIL PROTECTED] http://XFree86.Org/mailman/listinfo/devel
