Re: [RESEND PATCH 2/3 v6] cpufreq: mediatek: Add MT8173 cpufreq driver
Hi,
On Monday, August 17, 2015 05:24:24 PM Pi-Cheng Chen wrote:
Mediatek MT8173 is an ARMv8 based quad-core (2*Cortex-A53 and
2*Cortex-A72) SoC with duall clusters. For each cluster, two voltage
inputs, Vproc and Vsram are supplied by two regulators. For the big
cluster, two regulators come from different PMICs. In this case, when
scaling voltage inputs of the cluster, the voltages of two regulator
inputs need to be controlled by software explicitly under the SoC
specific limitation:
100mV Vsram - Vproc 200mV
which is called 'voltage tracking' mechanism. And when scaling the
frequency of cluster clock input, the input MUX need to be parented to
another intermediate stable PLL first and reparented to the original
PLL once the original PLL is stable at the target frequency. This patch
implements those mechanisms to enable CPU DVFS support for Mediatek
MT8173 SoC.
Signed-off-by: Pi-Cheng Chen pi-cheng.c...@linaro.org
Acked-by: Viresh Kumar viresh.ku...@linaro.org
---
drivers/cpufreq/Kconfig.arm | 7 +
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/mt8173-cpufreq.c | 524
+++
3 files changed, 532 insertions(+)
create mode 100644 drivers/cpufreq/mt8173-cpufreq.c
[...]
+static struct platform_driver mt8173_cpufreq_platdrv = {
+ .driver = {
+ .name = mt8173-cpufreq,
+ },
+ .probe = mt8173_cpufreq_probe,
+};
+
+static int mt8173_cpufreq_driver_init(void)
+{
+ struct platform_device *pdev;
+ int err;
+
+ err = platform_driver_register(mt8173_cpufreq_platdrv);
+ if (err)
+ return err;
+
+ /*
+ * Since there's no place to hold device registration code and no
+ * device tree based way to match cpufreq driver yet, both the driver
+ * and the device registration codes are put here to handle defer
+ * probing.
+ */
+ pdev = platform_device_register_simple(mt8173-cpufreq, -1, NULL, 0);
This is not very friendly for multiplatform support
(mt8173_cpufreq_driver_init() can be called on other platforms,
i.e. Samsung Exynos7 one if ARCH_EXYNOS7 is also enabled in
the kernel config).
Why can't it be fixed with checking Device Tree with
of_machine_is_compatible(mediatek,mt8173)
(assuming that it can be used on arm64 like on arm32)?
+ if (IS_ERR(pdev)) {
+ pr_err(failed to register mtk-cpufreq platform device\n);
+ return PTR_ERR(pdev);
+ }
+
+ return 0;
+}
+device_initcall(mt8173_cpufreq_driver_init);
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics
--
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Re: [RESEND PATCH 2/3 v6] cpufreq: mediatek: Add MT8173 cpufreq driver
On 18-08-15, 12:09, Bartlomiej Zolnierkiewicz wrote: + pdev = platform_device_register_simple(mt8173-cpufreq, -1, NULL, 0); This is not very friendly for multiplatform support (mt8173_cpufreq_driver_init() can be called on other platforms, i.e. Samsung Exynos7 one if ARCH_EXYNOS7 is also enabled in the kernel config). Why can't it be fixed with checking Device Tree with of_machine_is_compatible(mediatek,mt8173) (assuming that it can be used on arm64 like on arm32)? Because I asked him to remove that in v5 :( as I somehow had in mind that this wouldn't even compile for other platforms. @Pi-cheng: Please send v7 only for this patch and add the DT platform check you were doing earlier. Sorry. -- viresh -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] spi: mediatek: fix spi incorrect endian usage and remove redundant clock
This patch fixes incorrect endian usage, removes redundant
clock in prepare_hardware/unprepare_hardware and revises
coding styles.
Signed-off-by: Leilk Liu leilk@mediatek.com
---
Change in this patch:
1. fix incorrect endian usage on big-endian system.
2. delete redundant clock in prepare/unprepare_hardware.
3. revise coding styles.
---
drivers/spi/spi-mt65xx.c | 163 +--
include/linux/platform_data/spi-mt65xx.h | 2 -
2 files changed, 69 insertions(+), 96 deletions(-)
diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
index 519f50c..a9da887 100644
--- a/drivers/spi/spi-mt65xx.c
+++ b/drivers/spi/spi-mt65xx.c
@@ -16,6 +16,7 @@
#include linux/device.h
#include linux/err.h
#include linux/interrupt.h
+#include linux/io.h
#include linux/ioport.h
#include linux/module.h
#include linux/of.h
@@ -48,15 +49,8 @@
#define SPI_CFG1_PACKET_LOOP_MASK 0xff00
#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff
-#define SPI_CMD_ACT_OFFSET0
-#define SPI_CMD_RESUME_OFFSET 1
-#define SPI_CMD_CPHA_OFFSET 8
-#define SPI_CMD_CPOL_OFFSET 9
-#define SPI_CMD_TXMSBF_OFFSET 12
-#define SPI_CMD_RXMSBF_OFFSET 13
-#define SPI_CMD_RX_ENDIAN_OFFSET 14
-#define SPI_CMD_TX_ENDIAN_OFFSET 15
-
+#define SPI_CMD_ACT BIT(0)
+#define SPI_CMD_RESUME BIT(1)
#define SPI_CMD_RST BIT(2)
#define SPI_CMD_PAUSE_EN BIT(4)
#define SPI_CMD_DEASSERT BIT(5)
@@ -71,12 +65,10 @@
#define SPI_CMD_FINISH_IEBIT(16)
#define SPI_CMD_PAUSE_IE BIT(17)
-#define MTK_SPI_QUIRK_PAD_SELECT 1
-/* Must explicitly send dummy Tx bytes to do Rx only transfer */
-#define MTK_SPI_QUIRK_MUST_TX 1
-
#define MT8173_SPI_MAX_PAD_SEL 3
+#define MTK_SPI_PAUSE_INT_STATUS 0x2
+
#define MTK_SPI_IDLE 0
#define MTK_SPI_PAUSED 1
@@ -84,8 +76,9 @@
#define MTK_SPI_PACKET_SIZE 1024
struct mtk_spi_compatible {
- u32 need_pad_sel;
- u32 must_tx;
+ bool need_pad_sel;
+ /* Must explicitly send dummy Tx bytes to do Rx only transfer */
+ bool must_tx;
};
struct mtk_spi {
@@ -100,19 +93,11 @@ struct mtk_spi {
const struct mtk_spi_compatible *dev_comp;
};
-static const struct mtk_spi_compatible mt6589_compat = {
- .need_pad_sel = 0,
- .must_tx = 0,
-};
-
-static const struct mtk_spi_compatible mt8135_compat = {
- .need_pad_sel = 0,
- .must_tx = 0,
-};
-
+static const struct mtk_spi_compatible mt6589_compat;
+static const struct mtk_spi_compatible mt8135_compat;
static const struct mtk_spi_compatible mt8173_compat = {
- .need_pad_sel = MTK_SPI_QUIRK_PAD_SELECT,
- .must_tx = MTK_SPI_QUIRK_MUST_TX,
+ .need_pad_sel = true,
+ .must_tx = true,
};
/*
@@ -122,8 +107,6 @@ static const struct mtk_spi_compatible mt8173_compat = {
static const struct mtk_chip_config mtk_default_chip_info = {
.rx_mlsb = 1,
.tx_mlsb = 1,
- .tx_endian = 0,
- .rx_endian = 0,
};
static const struct of_device_id mtk_spi_of_match[] = {
@@ -156,14 +139,23 @@ static void mtk_spi_config(struct mtk_spi *mdata,
reg_val = readl(mdata-base + SPI_CMD_REG);
/* set the mlsbx and mlsbtx */
- reg_val = ~(SPI_CMD_TXMSBF | SPI_CMD_RXMSBF);
- reg_val |= (chip_config-tx_mlsb SPI_CMD_TXMSBF_OFFSET);
- reg_val |= (chip_config-rx_mlsb SPI_CMD_RXMSBF_OFFSET);
+ if (chip_config-tx_mlsb)
+ reg_val |= SPI_CMD_TXMSBF;
+ else
+ reg_val = ~SPI_CMD_TXMSBF;
+ if (chip_config-rx_mlsb)
+ reg_val |= SPI_CMD_RXMSBF;
+ else
+ reg_val = ~SPI_CMD_RXMSBF;
/* set the tx/rx endian */
- reg_val = ~(SPI_CMD_TX_ENDIAN | SPI_CMD_RX_ENDIAN);
- reg_val |= (chip_config-tx_endian SPI_CMD_TX_ENDIAN_OFFSET);
- reg_val |= (chip_config-rx_endian SPI_CMD_RX_ENDIAN_OFFSET);
+#ifdef __LITTLE_ENDIAN
+ reg_val = ~SPI_CMD_TX_ENDIAN;
+ reg_val = ~SPI_CMD_RX_ENDIAN;
+#else
+ reg_val |= SPI_CMD_TX_ENDIAN;
+ reg_val |= SPI_CMD_RX_ENDIAN;
+#endif
/* set finish and pause interrupt always enable */
reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_EN;
@@ -186,30 +178,14 @@ static int mtk_spi_prepare_hardware(struct spi_master
*master)
struct spi_transfer *trans;
struct mtk_spi *mdata = spi_master_get_devdata(master);
struct spi_message *msg = master-cur_msg;
- int ret;
-
- ret = clk_prepare_enable(mdata-spi_clk);
- if (ret 0) {
- dev_err(master-dev, failed to enable clock (%d)\n, ret);
- return ret;
- }
trans = list_first_entry(msg-transfers, struct spi_transfer,
transfer_list);
- if (trans-cs_change == 0) {
+ if (!trans-cs_change) {
mdata-state =
Re: [PATCH v2 0/2] spi: dw: Reintroduce optional 16 bit data register I/O
On Mon, Jul 27, 2015 at 4:59 PM, Mark Brown broo...@kernel.org wrote: On Mon, Jul 27, 2015 at 01:38:57PM +0200, Michael van der Westhuizen wrote: It's possible there was some discussion of the patch that made it look it needed a resubmit, or that it was buried as reply in the middle of discussion of some other patches (eg, a previous version). Either way to repeat what I said if you want me to review a patch please send me the patch. I’ve just resent the series. You've sent them as a reply in the middle of another thread which is something I just indicated above was a bad idea in the message you're replying to here (it's a great way to either make it hard to figure out what the current version of the code is or get your message deleted along with the rest of the thread) and you've decided to label them as [RESEND instead of [PATCH :( Michael, I believe you need to resend as a v3 in a separate thread if you aware of this code. (Though it seems already late for v4.3) -- With Best Regards, Andy Shevchenko -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [2/2] ARM: dts: Add missing irq pinctrl for max77686 on smdk5250
On 18.08.2015 15:27, Pankaj Dubey wrote: Hi Krzysztof, On Monday 17 August 2015 11:20 AM, Krzysztof Kozlowski wrote: 2015-05-02 14:49 GMT+09:00 Krzysztof Kozlowski k.kozlowsk...@gmail.com: W dniu 28.04.2015 o 20:02, Pankaj Dubey pisze: Hi Kukjin, Any updated for this patch. Without this PMIC RTC is not working on SMDK5250. Could you resend the patch after rebasing it? Best regards, Krzysztof Dear Pankaj and Yadwinder, Do you plan to do anything with this patch? Best regards, Krzysztof Just noticed that the patch in subject is already merged in kgene tree. Yes, you're right. There was another patch [1/2]: ARM: dts: Fix bootup issue on smdk5250 which was posted along with this is still not merged. Resending it once again. [1]: http://www.spinics.net/lists/linux-samsung-soc/msg39100.html Thanks! Best regards, Krzysztof -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 0/3] introduce driver for the Atmel SDMMC
Hi, On Wed, Jul 29, 2015 at 04:22:45PM +0200, Ludovic Desroches wrote: Hi, This set of patches introduce a driver for the new Atmel SDMMC device avaible on SAMA5D2 SoC. There is also a resend of an old patch which has not been taken. Ulf asked for some reviews since it could impact all sdhci devices but nobody did it... This patch is not necessary for patch 2/3. It only fixes a special use case. If there are objections about it, drop it, I don't want to delay the Atmel SDMMC driver inclusion only for this patch. Ping, any objections about this driver? Changes: - from v1: - update license Ludovic Desroches (3): mmc: sdhci: switch from programmable clock mode to divided one if needed mmc: sdhci-of-at91: introduce driver for the Atmel SDMMC MAINTAINERS: add entry for Atmel sdhci-of-at91 driver .../devicetree/bindings/mmc/sdhci-atmel.txt| 21 +++ MAINTAINERS| 6 + drivers/mmc/host/Kconfig | 8 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-of-at91.c | 192 + drivers/mmc/host/sdhci.c | 29 +++- 6 files changed, 248 insertions(+), 9 deletions(-) create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-atmel.txt create mode 100644 drivers/mmc/host/sdhci-of-at91.c -- 2.5.0 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RESEND PATCH v2 2/2] spi: dw: Allow interface drivers to limit data I/O to word sizes
On Mon, Jul 27, 2015 at 2:37 PM, Michael van der Westhuizen
mich...@smart-africa.com wrote:
The commit dd11444327ce (spi: dw-spi: Convert 16bit accesses to 32bit
accesses) changed all 16bit accesses in the DW_apb_ssi driver to 32bit.
This, unfortunately, breaks data register access on picoXcell, where the
DW IP needs data register accesses to be word accesses (all other
accesses appear to be OK).
This change introduces a new master variable to allow interface drivers
to specify that 16bit data transfer I/O is required. This change also
introduces the ability to set this variable via device tree bindings in
the MMIO interface driver.
Before this change, on a picoXcell pc3x3:
spi_master spi32766: interrupt_transfer: fifo overrun/underrun
m25p80 spi32766.0: error -5 reading 9f
m25p80: probe of spi32766.0 failed with error -5
After this change:
m25p80 spi32766.0: m25p40 (512 Kbytes)
Fixes: dd11444327ce (spi: dw-spi: Convert 16bit accesses to 32bit accesses)
Signed-off-by: Michael van der Westhuizen mich...@smart-africa.com
Reviewed-by: Andy Shevchenko andriy.shevche...@linux.intel.com
One minor comment below.
---
Changes in v2:
- Incorporate review feedback from Andy Shevchenko
- Rework the DT bindings to accept an I/O register width as a
number of bytes rather than using a boolean spefifying the
width preference to be 16 bits.
- Add data register access wrapper functions and use them when
reading and writing the data register.
drivers/spi/spi-dw-mmio.c | 4
drivers/spi/spi-dw.c | 4 ++--
drivers/spi/spi-dw.h | 35 +++
3 files changed, 41 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index eb03e12..e76bf72 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -74,6 +74,10 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
dws-max_freq = clk_get_rate(dwsmmio-clk);
+ if (pdev-dev.of_node)
of_property_read_u32() is NULL-aware. Since the option is optional we
may drop the condition.
+ of_property_read_u32(pdev-dev.of_node, snps,reg-io-width,
Like Rob said, drop 'snps,' prefix as it is a generic property name.
+dws-reg_io_width);
+
num_cs = 4;
if (pdev-dev.of_node)
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index 8d67d03..4fbfcdc 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -194,7 +194,7 @@ static void dw_writer(struct dw_spi *dws)
else
txw = *(u16 *)(dws-tx);
}
- dw_writel(dws, DW_SPI_DR, txw);
+ dw_write_io_reg(dws, DW_SPI_DR, txw);
dws-tx += dws-n_bytes;
}
}
@@ -205,7 +205,7 @@ static void dw_reader(struct dw_spi *dws)
u16 rxw;
while (max--) {
- rxw = dw_readl(dws, DW_SPI_DR);
+ rxw = dw_read_io_reg(dws, DW_SPI_DR);
/* Care rx only if the transfer's original rx is not null */
if (dws-rx_end - dws-len) {
if (dws-n_bytes == 1)
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 6c91391..b75ed32 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -109,6 +109,7 @@ struct dw_spi {
u32 fifo_len; /* depth of the FIFO buffer */
u32 max_freq; /* max bus freq supported */
+ u32 reg_io_width; /* DR I/O width in bytes */
u16 bus_num;
u16 num_cs; /* supported slave numbers */
@@ -145,11 +146,45 @@ static inline u32 dw_readl(struct dw_spi *dws, u32
offset)
return __raw_readl(dws-regs + offset);
}
+static inline u16 dw_readw(struct dw_spi *dws, u32 offset)
+{
+ return __raw_readw(dws-regs + offset);
+}
+
static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
{
__raw_writel(val, dws-regs + offset);
}
+static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val)
+{
+ __raw_writew(val, dws-regs + offset);
+}
+
+static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
+{
+ switch (dws-reg_io_width) {
+ case 2:
+ return dw_readw(dws, offset);
+ case 4:
+ default:
+ return dw_readl(dws, offset);
+ }
+}
+
+static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
+{
+ switch (dws-reg_io_width) {
+ case 2:
+ dw_writew(dws, offset, val);
+ break;
+ case 4:
+ default:
+ dw_writel(dws, offset, val);
+ break;
+ }
+}
+
static inline void spi_enable_chip(struct dw_spi *dws, int enable)
{
[PATCH v7 2/3] pwm: add MediaTek display PWM driver support
Add display PWM driver support to modify backlight for MT8173 and MT6595.
The PWM has one channel to control the brightness of the display.
When the (high_width / period) is closer to 1, the screen is brighter;
otherwise, it is darker.
Signed-off-by: YH Huang yh.hu...@mediatek.com
---
drivers/pwm/Kconfig| 11 +++
drivers/pwm/Makefile |1 +
drivers/pwm/pwm-mtk-disp.c | 232
3 files changed, 244 insertions(+)
create mode 100644 drivers/pwm/pwm-mtk-disp.c
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index b1541f4..24acd8f 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -211,6 +211,17 @@ config PWM_LPSS_PLATFORM
To compile this driver as a module, choose M here: the module
will be called pwm-lpss-platform.
+config PWM_MTK_DISP
+ tristate MediaTek display PWM driver
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ depends on HAS_IOMEM
+ help
+ Generic PWM framework driver for MediaTek disp-pwm device.
+ The PWM is used to control the backlight brightness for display.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-mtk-disp.
+
config PWM_MXS
tristate Freescale MXS PWM support
depends on ARCH_MXS OF
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index ec50eb5..99c9e75 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_PWM_LPC32XX) += pwm-lpc32xx.o
obj-$(CONFIG_PWM_LPSS) += pwm-lpss.o
obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-pci.o
obj-$(CONFIG_PWM_LPSS_PLATFORM)+= pwm-lpss-platform.o
+obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o
obj-$(CONFIG_PWM_MXS) += pwm-mxs.o
obj-$(CONFIG_PWM_PCA9685) += pwm-pca9685.o
obj-$(CONFIG_PWM_PUV3) += pwm-puv3.o
diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c
new file mode 100644
index 000..90aea6f
--- /dev/null
+++ b/drivers/pwm/pwm-mtk-disp.c
@@ -0,0 +1,232 @@
+/*
+ * MediaTek display pulse-width-modulation controller driver.
+ * Copyright (c) 2015 MediaTek Inc.
+ * Author: YH Huang yh.hu...@mediatek.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk.h
+#include linux/err.h
+#include linux/io.h
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/pwm.h
+#include linux/slab.h
+
+#define DISP_PWM_EN0x00
+#define PWM_ENABLE_MASKBIT(0)
+
+#define DISP_PWM_COMMIT0x08
+#define PWM_COMMIT_MASKBIT(0)
+
+#define DISP_PWM_CON_0 0x10
+#define PWM_CLKDIV_SHIFT 16
+#define PWM_CLKDIV_MAX 0x3ff
+#define PWM_CLKDIV_MASK(PWM_CLKDIV_MAX PWM_CLKDIV_SHIFT)
+
+#define DISP_PWM_CON_1 0x14
+#define PWM_PERIOD_BIT_WIDTH 12
+#define PWM_PERIOD_MASK((1 PWM_PERIOD_BIT_WIDTH) - 1)
+
+#define PWM_HIGH_WIDTH_SHIFT 16
+#define PWM_HIGH_WIDTH_MASK(0x1fff PWM_HIGH_WIDTH_SHIFT)
+
+struct mtk_disp_pwm {
+ struct pwm_chip chip;
+ struct clk *clk_main;
+ struct clk *clk_mm;
+ void __iomem *base;
+};
+
+static inline struct mtk_disp_pwm *to_mtk_disp_pwm(struct pwm_chip *chip)
+{
+ return container_of(chip, struct mtk_disp_pwm, chip);
+}
+
+static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset,
+u32 mask, u32 value)
+{
+ void __iomem *address;
+ u32 val;
+
+ address = mdp-base + offset;
+ val = readl(address);
+ val = ~mask;
+ val |= value;
+ writel(val, address);
+}
+
+static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
+ int duty_ns, int period_ns)
+{
+ struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
+ u64 div, rate;
+ u32 clk_div, period, high_width, value;
+
+ /*
+* Find period, high_width and clk_div to suit duty_ns and period_ns.
+* Calculate proper div value to keep period value in the bound.
+*
+* period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE
+* duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE
+*
+* period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1
+* high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1))
+*/
+ rate = clk_get_rate(mdp-clk_main);
+ clk_div = div_u64(rate * period_ns, NSEC_PER_SEC)
+
[PATCH v7 3/3] arm64: dts: mt8173: add MT8173 display PWM driver support node
Add display PWM node in mt8173-evb.dts and mt8173.dtsi.
Signed-off-by: YH Huang yh.hu...@mediatek.com
---
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 13 +
arch/arm64/boot/dts/mediatek/mt8173.dtsi| 22 ++
2 files changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
index 4be66ca..de95cf3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
@@ -92,6 +92,13 @@
};
pio {
+ disp_pwm0_pins: disp_pwm0_pins {
+ pins1 {
+ pinmux = MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0;
+ output-low;
+ };
+ };
+
mmc0_pins_default: mmc0default {
pins_cmd_dat {
pinmux = MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0,
@@ -190,6 +197,12 @@
};
};
+pwm0 {
+ pinctrl-names = default;
+ pinctrl-0 = disp_pwm0_pins;
+ status = okay;
+};
+
pwrap {
pmic: mt6397 {
compatible = mediatek,mt6397;
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 6c3f047..68b1ef0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -501,6 +501,28 @@
#clock-cells = 1;
};
+ pwm0: pwm@1401e000 {
+ compatible = mediatek,mt8173-disp-pwm,
+mediatek,mt6595-disp-pwm;
+ reg = 0 0x1401e000 0 0x1000;
+ #pwm-cells = 2;
+ clocks = mmsys CLK_MM_DISP_PWM026M,
+mmsys CLK_MM_DISP_PWM0MM;
+ clock-names = main, mm;
+ status = disabled;
+ };
+
+ pwm1: pwm@1401f000 {
+ compatible = mediatek,mt8173-disp-pwm,
+mediatek,mt6595-disp-pwm;
+ reg = 0 0x1401f000 0 0x1000;
+ #pwm-cells = 2;
+ clocks = mmsys CLK_MM_DISP_PWM126M,
+mmsys CLK_MM_DISP_PWM1MM;
+ clock-names = main, mm;
+ status = disabled;
+ };
+
imgsys: clock-controller@1500 {
compatible = mediatek,mt8173-imgsys, syscon;
reg = 0 0x1500 0 0x1000;
--
1.7.9.5
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[PATCH v7 1/3] dt-bindings: pwm: add MediaTek display PWM bindings
Document the device-tree binding of MediaTek display PWM.
The PWM has one channel to control the backlight brightness for display.
It supports MT8173 and MT6595.
Signed-off-by: YH Huang yh.hu...@mediatek.com
---
.../devicetree/bindings/pwm/pwm-mtk-disp.txt | 42
1 file changed, 42 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt
diff --git a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt
b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt
new file mode 100644
index 000..f8f59ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt
@@ -0,0 +1,42 @@
+MediaTek display PWM controller
+
+Required properties:
+ - compatible: should be mediatek,name-disp-pwm:
+ - mediatek,mt8173-disp-pwm: found on mt8173 SoC.
+ - mediatek,mt6595-disp-pwm: found on mt6595 SoC.
+ - reg: physical base address and length of the controller's registers.
+ - #pwm-cells: must be 2. See pwm.txt in this directory for a description of
+ the cell format.
+ - clocks: phandle and clock specifier of the PWM reference clock.
+ - clock-names: must contain the following:
+ - main: clock used to generate PWM signals.
+ - mm: sync signals from the modules of mmsys.
+ - pinctrl-names: Must contain a default entry.
+ - pinctrl-0: One property must exist for each entry in pinctrl-names.
+ See pinctrl/pinctrl-bindings.txt for details of the property values.
+
+Example:
+ pwm0: pwm@1401e000 {
+ compatible = mediatek,mt8173-disp-pwm,
+mediatek,mt6595-disp-pwm;
+ reg = 0 0x1401e000 0 0x1000;
+ #pwm-cells = 2;
+ clocks = mmsys CLK_MM_DISP_PWM026M,
+mmsys CLK_MM_DISP_PWM0MM;
+ clock-names = main, mm;
+ pinctrl-names = default;
+ pinctrl-0 = disp_pwm0_pins;
+ };
+
+ backlight_lcd: backlight_lcd {
+ compatible = pwm-backlight;
+ pwms = pwm0 0 100;
+ brightness-levels =
+ 0 16 32 48 64 80 96 112
+ 128 144 160 176 192 208 224 240
+ 255
+ ;
+ default-brightness-level = 9;
+ power-supply = mt6397_vio18_reg;
+ enable-gpios = pio 95 GPIO_ACTIVE_HIGH;
+ };
--
1.7.9.5
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[PATCH v7 0/3] Add MediaTek display PWM driver
This patch series add the use of display PWM driver, documentation and device tree for Mediatek SoCs. The driver is used to support the backlight of the panel. This is based on v4.2-rc1. The clock definitions (CLK_MM_DISP_PWM*) are added by James Liao's patch: clk: mediatek: Add subsystem clocks of MT8173 Change in v7: 1. Add the dependency HAS_IOMEM in Kconfig. 2. Revise misprints and coding style for readability. Change in v6: 1. Enable clocks in the pwm_enable function. 2. Remove suspend/resume code since pwm-backlight driver has done the same things. 3. Revise some code to make it easier to read. Change in v5: 1. Configure PWM output via pinctrl. 2. Fix the parameter name in dtsi. Change in v4: 1. Codebase is on v4.2-rc1. 2. Add the PWM node in dtsi. 3. Change the dependency in Kconfig. 4. Rewrite some code for readability. Change in v3: 1. Add suspend/resume function. 2. Fix the formula for high_width calculation. 3. Rewrite some code to make it easier to read. 4. Add more information in the commit message. Change in v2: 1. Rewrite descriptions for driver in kconfig to make it much clear. 2. Rename the driver from pwm-mediatek-disp to pwm-mtk-disp. 3. Disable clocks in the error path. 4. Change the shift values in decimal instead of hex. 5. Rename and add some variables or function name for consistency and readability. 6. Drop unnecessary parentheses, spaces, variables and add newlines to make the code easiler to read. YH Huang (3): dt-bindings: pwm: add MediaTek display PWM bindings pwm: add MediaTek display PWM driver support arm64: dts: mt8173: add MT8173 display PWM driver support node .../devicetree/bindings/pwm/pwm-mtk-disp.txt | 42 arch/arm64/boot/dts/mediatek/mt8173-evb.dts| 13 ++ arch/arm64/boot/dts/mediatek/mt8173.dtsi | 22 ++ drivers/pwm/Kconfig| 11 + drivers/pwm/Makefile |1 + drivers/pwm/pwm-mtk-disp.c | 232 6 files changed, 321 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt create mode 100644 drivers/pwm/pwm-mtk-disp.c -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2] i2c: allow specifying separate wakeup interrupt in device tree
Instead of having each i2c driver individually parse device tree data in
case it or platform supports separate wakeup interrupt, and handle
enabling and disabling wakeup interrupts in their power management
routines, let's have i2c core do that for us.
Platforms wishing to specify separate wakeup interrupt for the device
should use named interrupt syntax in their DTSes:
interrupt-parent = intc1;
interrupts = 5 0, 6 0;
interrupt-names = irq, wakeup;
This patch is inspired by work done by Vignesh R vigne...@ti.com for
pixcir_i2c_ts driver.
Signed-off-by: Dmitry Torokhov dmitry.torok...@gmail.com
---
v1 - v2:
- added binding documentation for interrupts property;
- simplified initializing device as wakeup source - now just doing based on
client's flags.
Documentation/devicetree/bindings/i2c/i2c.txt | 16 +++--
drivers/i2c/i2c-core.c| 51 ++-
2 files changed, 56 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/i2c/i2c.txt
b/Documentation/devicetree/bindings/i2c/i2c.txt
index 1175efe..8a99150 100644
--- a/Documentation/devicetree/bindings/i2c/i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c.txt
@@ -12,7 +12,7 @@ Required properties
- compatible - name of I2C bus controller following generic names
recommended practice.
-For other required properties e.g. to describe register sets, interrupts,
+For other required properties e.g. to describe register sets,
clocks, etc. check the binding documentation of the specific driver.
The cells properties above define that an address of children of an I2C bus
@@ -29,5 +29,17 @@ Optional properties
These properties may not be supported by all drivers. However, if a driver
wants to support one of the below features, it should adapt the bindings below.
-- clock-frequency - frequency of bus clock in Hz
+- clock-frequency - frequency of bus clock in Hz.
- wakeup-source- device can be used as a wakeup source.
+
+- interrupts - interrupts used by the device.
+- interrupt-names - irq and wakeup names are recognized by I2C core,
+ other names are left to individual drivers.
+
+Binding may contain optional interrupts property, describing interrupts
+used by the device. I2C core will assign irq interrupt (or the very first
+interrupt if not using interrupt names) as primary interrupt for the slave.
+
+Also, if device is marked as a wakeup source, I2C core will set up wakeup
+interrupt for the device. If wakeup interrupt name is not present in the
+binding, then primary interrupt will be used as wakeup interrupt.
diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
index e6d4935..d8fd226 100644
--- a/drivers/i2c/i2c-core.c
+++ b/drivers/i2c/i2c-core.c
@@ -47,6 +47,7 @@
#include linux/rwsem.h
#include linux/pm_runtime.h
#include linux/pm_domain.h
+#include linux/pm_wakeirq.h
#include linux/acpi.h
#include linux/jump_label.h
#include asm/uaccess.h
@@ -639,11 +640,13 @@ static int i2c_device_probe(struct device *dev)
if (!client-irq) {
int irq = -ENOENT;
- if (dev-of_node)
- irq = of_irq_get(dev-of_node, 0);
- else if (ACPI_COMPANION(dev))
+ if (dev-of_node) {
+ irq = of_irq_get_byname(dev-of_node, irq);
+ if (irq == -EINVAL || irq == -ENODATA)
+ irq = of_irq_get(dev-of_node, 0);
+ } else if (ACPI_COMPANION(dev)) {
irq = acpi_dev_gpio_irq_get(ACPI_COMPANION(dev), 0);
-
+ }
if (irq == -EPROBE_DEFER)
return irq;
if (irq 0)
@@ -656,23 +659,49 @@ static int i2c_device_probe(struct device *dev)
if (!driver-probe || !driver-id_table)
return -ENODEV;
- if (!device_can_wakeup(client-dev))
- device_init_wakeup(client-dev,
- client-flags I2C_CLIENT_WAKE);
+ if (client-flags I2C_CLIENT_WAKE) {
+ int wakeirq = -ENOENT;
+
+ if (dev-of_node) {
+ wakeirq = of_irq_get_byname(dev-of_node, wakeup);
+ if (wakeirq == -EPROBE_DEFER)
+ return wakeirq;
+ }
+
+ device_init_wakeup(client-dev, true);
+
+ if (wakeirq 0 wakeirq != client-irq)
+ status = dev_pm_set_dedicated_wake_irq(dev, wakeirq);
+ else if (client-irq 0)
+ status = dev_pm_set_wake_irq(dev, wakeirq);
+ else
+ status = 0;
+
+ if (status)
+ dev_warn(client-dev, failed to set up wakeup irq);
+ }
+
dev_dbg(dev, probe\n);
status = of_clk_set_defaults(dev-of_node,
Re: [PATCH v5 4/4] arm64, dt, thunderx: Add initial dts for Cavium Thunder SoC in 2 Node topology.
Dear Ganapatrao, On Fri, 14 Aug 2015 22:09:34 +0530 Ganapatrao Kulkarni gkulka...@caviumnetworks.com wrote: adding dt file for Cavium's Thunder SoC in 2 Node topology using arm,associativity device node property. Signed-off-by: Ganapatrao Kulkarni gkulka...@caviumnetworks.com --- arch/arm64/boot/dts/cavium/Makefile | 2 +- arch/arm64/boot/dts/cavium/thunder-88xx-2n.dts | 78 +++ arch/arm64/boot/dts/cavium/thunder-88xx-2n.dtsi | 790 3 files changed, 869 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/cavium/thunder-88xx-2n.dts create mode 100644 arch/arm64/boot/dts/cavium/thunder-88xx-2n.dtsi diff --git a/arch/arm64/boot/dts/cavium/Makefile b/arch/arm64/boot/dts/cavium/Makefile index e34f89d..7fe7067 100644 --- a/arch/arm64/boot/dts/cavium/Makefile +++ b/arch/arm64/boot/dts/cavium/Makefile @@ -1,4 +1,4 @@ -dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb +dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb thunder-88xx-2n.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx-2n.dts b/arch/arm64/boot/dts/cavium/thunder-88xx-2n.dts new file mode 100644 index 000..adbd3a9 --- /dev/null +++ b/arch/arm64/boot/dts/cavium/thunder-88xx-2n.dts @@ -0,0 +1,78 @@ +/* + * Cavium Thunder DTS file - Thunder board description + * + * Copyright (C) 2014, Cavium Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA From the kernel logs, seems this FSF mailing address isn't valid. It's better to remove this paragraph about writing to FSF I also submitted a patch to remove this paragraph from existing thunder-88xx dts: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/358225.html Thanks, Jisheng -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [2/2] ARM: dts: Add missing irq pinctrl for max77686 on smdk5250
Hi Krzysztof,
On Monday 17 August 2015 11:20 AM, Krzysztof Kozlowski wrote:
2015-05-02 14:49 GMT+09:00 Krzysztof Kozlowski k.kozlowsk...@gmail.com:
W dniu 28.04.2015 o 20:02, Pankaj Dubey pisze:
Hi Kukjin,
Any updated for this patch. Without this PMIC RTC is not working on
SMDK5250.
Could you resend the patch after rebasing it?
Best regards,
Krzysztof
Dear Pankaj and Yadwinder,
Do you plan to do anything with this patch?
Best regards,
Krzysztof
Just noticed that the patch in subject is already merged in kgene tree.
There was another patch [1/2]: ARM: dts: Fix bootup issue on smdk5250
which was posted along with this is still not merged. Resending it once
again.
[1]: http://www.spinics.net/lists/linux-samsung-soc/msg39100.html
Thanks,
Pankaj Dubey
Thanks,
Pankaj Dubey
On Tuesday 18 November 2014 05:38 PM, Yadwinder Singh Brar wrote:
This patch adds pinctrl configuration for using configuring gpx3-2 as an
external interrupt from max77686. Though max77686 RTC is enabled and gets
probed by default, it doesnt work as its unable to get interrupt.
This patch makes max77686 RTC work and also configures it as wakeup
source.
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Pankaj Dubey pankaj.du...@samsung.com
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 95b5b51..19cd918 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -131,6 +131,9 @@
reg = 0x09;
interrupt-parent = gpx3;
interrupts = 2 IRQ_TYPE_NONE;
+pinctrl-names = default;
+pinctrl-0 = max77686_irq;
+wakeup-source;
voltage-regulators {
ldo1_reg: LDO1 {
@@ -411,3 +414,12 @@
};
};
};
+
+pinctrl_0 {
+max77686_irq: max77686-irq {
+samsung,pins = gpx3-2;
+samsung,pin-function = 0xf;
+samsung,pin-pud = 0;
+samsung,pin-drv = 0;
+};
+};
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Re: [2/2] ARM: dts: Add missing irq pinctrl for max77686 on smdk5250
Hi Krzysztof,
On Monday 17 August 2015 11:20 AM, Krzysztof Kozlowski wrote:
2015-05-02 14:49 GMT+09:00 Krzysztof Kozlowski k.kozlowsk...@gmail.com:
W dniu 28.04.2015 o 20:02, Pankaj Dubey pisze:
Hi Kukjin,
Any updated for this patch. Without this PMIC RTC is not working on
SMDK5250.
Could you resend the patch after rebasing it?
Best regards,
Krzysztof
Dear Pankaj and Yadwinder,
Do you plan to do anything with this patch?
Thanks for reminding us. Somehow I missed this.
I will resend the patch shortly after rebasing and testing.
Thanks,
Pankaj Dubey
Best regards,
Krzysztof
Thanks,
Pankaj Dubey
On Tuesday 18 November 2014 05:38 PM, Yadwinder Singh Brar wrote:
This patch adds pinctrl configuration for using configuring gpx3-2 as an
external interrupt from max77686. Though max77686 RTC is enabled and gets
probed by default, it doesnt work as its unable to get interrupt.
This patch makes max77686 RTC work and also configures it as wakeup
source.
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Pankaj Dubey pankaj.du...@samsung.com
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 95b5b51..19cd918 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -131,6 +131,9 @@
reg = 0x09;
interrupt-parent = gpx3;
interrupts = 2 IRQ_TYPE_NONE;
+pinctrl-names = default;
+pinctrl-0 = max77686_irq;
+wakeup-source;
voltage-regulators {
ldo1_reg: LDO1 {
@@ -411,3 +414,12 @@
};
};
};
+
+pinctrl_0 {
+max77686_irq: max77686-irq {
+samsung,pins = gpx3-2;
+samsung,pin-function = 0xf;
+samsung,pin-pud = 0;
+samsung,pin-drv = 0;
+};
+};
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Re: [PATCH] spi: mediatek: fix spi incorrect endian usage and remove redundant clock
Hi,
On Tue, Aug 18, 2015 at 12:53 PM, Leilk Liu leilk@mediatek.com wrote:
This patch fixes incorrect endian usage, removes redundant
clock in prepare_hardware/unprepare_hardware and revises
coding styles.
Signed-off-by: Leilk Liu leilk@mediatek.com
---
Change in this patch:
1. fix incorrect endian usage on big-endian system.
2. delete redundant clock in prepare/unprepare_hardware.
3. revise coding styles.
The usual philosophy is to have one change per patch, so this might be
better as three patches. But this is Mark's call. Since the driver
isn't yet in Linus' tree, it might be a-ok to mix style improvements
and actual fixes, but as soon as it landed in Linus' tree you need to
keep them separate, so fixes can be easily backported.
Regarding the content ...
---
drivers/spi/spi-mt65xx.c | 163
+--
include/linux/platform_data/spi-mt65xx.h | 2 -
2 files changed, 69 insertions(+), 96 deletions(-)
diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
index 519f50c..a9da887 100644
--- a/drivers/spi/spi-mt65xx.c
+++ b/drivers/spi/spi-mt65xx.c
@@ -694,6 +662,7 @@ static int mtk_spi_resume(struct device *dev)
if (!pm_runtime_suspended(dev)) {
ret = clk_prepare_enable(mdata-spi_clk);
if (ret 0)
+ dev_err(dev, failed to enable spi_clk (%d)\n, ret);
return ret;
You need to add braces here, else the return ret isn't covered by
the if () anymore and you always return at this place.
}
@@ -720,8 +689,14 @@ static int mtk_spi_runtime_resume(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct mtk_spi *mdata = spi_master_get_devdata(master);
+ int ret;
+
+ ret = clk_prepare_enable(mdata-spi_clk);
+ if (ret 0)
+ dev_err(dev, failed to enable spi_clk (%d)\n, ret);
+ return ret;
Same here. Although at least here it should be harmless, as
clk_prepare_enable doesn't return 0.
- return clk_prepare_enable(mdata-spi_clk);
+ return 0;
}
#endif /* CONFIG_PM */
Jonas
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[PATCH v2 4/6] ARM: dts: qs600: remove unnecessary i2c pinctrl nodes in board file.
This patch removes unnecessary i2c pinctrl nodes in board file, these
are already defined in the soc specific file qcom-apq8064.dtsi.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 9 -
1 file changed, 9 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
index ebde2b7..06b3a70 100644
--- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
@@ -21,15 +21,6 @@
};
soc {
- pinctrl@80 {
- i2c1_pins: i2c1 {
- mux {
- pins = gpio20, gpio21;
- function = gsbi1;
- };
- };
- };
-
rpm@108000 {
regulators {
vin_lvs1_3_6-supply = pm8921_s4;
--
1.9.1
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[PATCH v2 3/6] ARM: dts: apq8064-ifc6410: add notify led support.
This patch adds notify led support on IFC6410, whose trigger can be
configured from userspace.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index b1f9ddb..08daafe 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -221,6 +221,18 @@
status = okay;
};
+ leds {
+ compatible = gpio-leds;
+ pinctrl-names = default;
+ pinctrl-0 = notify_led;
+
+ led@1 {
+ label = apq8064:green:user1;
+ gpios = pm8921_gpio 18 GPIO_ACTIVE_HIGH;
+ default-state = on;
+ };
+ };
+
qcom,ssbi@50 {
pmic@0 {
gpio@150 {
@@ -232,6 +244,15 @@
power-source =
PM8921_GPIO_S4;
};
};
+
+ notify_led: nled {
+ pios {
+ pins = gpio18;
+ function = normal;
+ bias-disable;
+ power-source =
PM8921_GPIO_S4;
+ };
+ };
};
};
};
--
1.9.1
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[PATCH v2 6/6] ARM: dts: qs600: Add SD card detect support.
This patch adds SD card detect support.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
index c095849..8c7bdc4 100644
--- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
@@ -25,6 +25,16 @@
};
soc {
+ pinctrl@80 {
+ card_detect: card_detect {
+ mux {
+ pins = gpio26;
+ function = gpio;
+ bias-disable;
+ };
+ };
+ };
+
rpm@108000 {
regulators {
vin_lvs1_3_6-supply = pm8921_s4;
@@ -193,6 +203,9 @@
sdcc3: sdcc@1218 {
status = okay;
vmmc-supply = v3p3_fixed;
+ pinctrl-names = default;
+ pinctrl-0 = card_detect;
+ cd-gpios= tlmm_pinmux 26
GPIO_ACTIVE_LOW;
};
/* WLAN */
sdcc4: sdcc@121c {
--
1.9.1
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Re: [PATCH] spi: mediatek: fix spi incorrect endian usage and remove redundant clock
On Tue, 2015-08-18 at 14:19 +0200, Jonas Gorski wrote:
Hi,
On Tue, Aug 18, 2015 at 12:53 PM, Leilk Liu leilk@mediatek.com wrote:
This patch fixes incorrect endian usage, removes redundant
clock in prepare_hardware/unprepare_hardware and revises
coding styles.
Signed-off-by: Leilk Liu leilk@mediatek.com
---
Change in this patch:
1. fix incorrect endian usage on big-endian system.
2. delete redundant clock in prepare/unprepare_hardware.
3. revise coding styles.
The usual philosophy is to have one change per patch, so this might be
better as three patches. But this is Mark's call. Since the driver
isn't yet in Linus' tree, it might be a-ok to mix style improvements
and actual fixes, but as soon as it landed in Linus' tree you need to
keep them separate, so fixes can be easily backported.
OK, I'll divide this patch to three patches on next version.
Regarding the content ...
---
drivers/spi/spi-mt65xx.c | 163
+--
include/linux/platform_data/spi-mt65xx.h | 2 -
2 files changed, 69 insertions(+), 96 deletions(-)
diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
index 519f50c..a9da887 100644
--- a/drivers/spi/spi-mt65xx.c
+++ b/drivers/spi/spi-mt65xx.c
@@ -694,6 +662,7 @@ static int mtk_spi_resume(struct device *dev)
if (!pm_runtime_suspended(dev)) {
ret = clk_prepare_enable(mdata-spi_clk);
if (ret 0)
+ dev_err(dev, failed to enable spi_clk (%d)\n,
ret);
return ret;
You need to add braces here, else the return ret isn't covered by
the if () anymore and you always return at this place.
Yes.I'll fix it.
}
@@ -720,8 +689,14 @@ static int mtk_spi_runtime_resume(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct mtk_spi *mdata = spi_master_get_devdata(master);
+ int ret;
+
+ ret = clk_prepare_enable(mdata-spi_clk);
+ if (ret 0)
+ dev_err(dev, failed to enable spi_clk (%d)\n, ret);
+ return ret;
Same here. Although at least here it should be harmless, as
clk_prepare_enable doesn't return 0.
Yes.I'll fix it too.
- return clk_prepare_enable(mdata-spi_clk);
+ return 0;
}
#endif /* CONFIG_PM */
Jonas
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Re: [PATCH v3 0/3] qcom: Add SMEM MTD parser
Hi, On Tue, Aug 18, 2015 at 1:47 AM, Mathieu Olivari math...@codeaurora.org wrote: QCOM platforms such as IPQ806x are using SMEM to store their flash layout. This patch set adds the DT nodes required to instanciate SMEM on IPQ806x and add an MTD parser using it. This change is based on the SMEM driver posted here: *https://lkml.org/lkml/2015/7/27/1125 Nice work. After testing it on AP148 I see this: [2.481507] 12 qcom-smem partitions found on MTD device qcom-nandc [2.481540] Creating 12 MTD partitions on qcom-nandc: [2.486690] 0x-0x0004 : 0:SBL1 [2.492842] 0x0004-0x0018 : 0:MIBIB [2.497857] 0x0018-0x002c : 0:SBL2 [2.502895] 0x002c-0x0054 : 0:SBL3 [2.507828] 0x0054-0x0066 : 0:DDRCONFIG [2.512857] 0x0066-0x0078 : 0:SSD [2.518074] 0x0078-0x00a0 : 0:TZ [2.522834] 0x00a0-0x00c8 : 0:RPM [2.527607] 0x00c8-0x0118 : 0:APPSBL [2.532472] 0x0118-0x0120 : 0:APPSBLENV [2.537586] 0x0120-0x0134 : 0:ART [2.543140] 0x0134-0x0534 : rootfs Are all these partition names supposed to be prefixed with 0:? This is using the OpenWrt applied version. Jonas -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/6] ARM: dts: ifc6410: Add pwrseq support for WLAN
This patch adds pwrseq for WLAN which resets the WLAN just before the
SDIO bus is up.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 31 ++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index 88d6655..b1f9ddb 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -1,5 +1,6 @@
#include qcom-apq8064-v2.0.dtsi
#include dt-bindings/gpio/gpio.h
+#include dt-bindings/pinctrl/qcom,pmic-gpio.h
/ {
model = Qualcomm APQ8064/IFC6410;
@@ -10,6 +11,20 @@
serial1 = gsbi6_serial;
};
+ pwrseq {
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+ compatible = simple-bus;
+
+ sdcc4_pwrseq: sdcc4_pwrseq {
+ pinctrl-names = default;
+ pinctrl-0 = wlan_default_gpios;
+ compatible = mmc-pwrseq-simple;
+ reset-gpios = pm8921_gpio 43 GPIO_ACTIVE_LOW;
+ };
+ };
+
soc {
pinctrl@80 {
card_detect: card_detect {
@@ -206,6 +221,21 @@
status = okay;
};
+ qcom,ssbi@50 {
+ pmic@0 {
+ gpio@150 {
+ wlan_default_gpios: wlan-gpios {
+ pios {
+ pins = gpio43;
+ function = normal;
+ bias-disable;
+ power-source =
PM8921_GPIO_S4;
+ };
+ };
+ };
+ };
+ };
+
amba {
/* eMMC */
sdcc1: sdcc@1240 {
@@ -227,6 +257,7 @@
status = okay;
vmmc-supply = ext_3p3v;
vqmmc-supply = pm8921_lvs1;
+ mmc-pwrseq = sdcc4_pwrseq;
};
};
};
--
1.9.1
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[PATCH v2 2/6] ARM: dts: qs600: add pwrseq support to WLAN
Add pwrseq support to sdcc4 which would enable a proper reset of WLAN
without ugly hacks in the board support file.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 32 +
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
index 34ccb26..ebde2b7 100644
--- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
@@ -1,9 +1,25 @@
#include qcom-apq8064-v2.0.dtsi
+#include dt-bindings/gpio/gpio.h
+#include dt-bindings/pinctrl/qcom,pmic-gpio.h
/ {
model = CompuLab CM-QS600;
compatible = qcom,apq8064-cm-qs600, qcom,apq8064;
+ pwrseq {
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+ compatible = simple-bus;
+
+ sdcc4_pwrseq: sdcc4_pwrseq {
+ pinctrl-names = default;
+ pinctrl-0 = wlan_default_gpios;
+ compatible = mmc-pwrseq-simple;
+ reset-gpios = pm8921_gpio 43 GPIO_ACTIVE_LOW;
+ };
+ };
+
soc {
pinctrl@80 {
i2c1_pins: i2c1 {
@@ -155,6 +171,21 @@
regulator-always-on;
};
+ qcom,ssbi@50 {
+ pmic@0 {
+ gpio@150 {
+ wlan_default_gpios: wlan-gpios {
+ pios {
+ pins = gpio43;
+ function = normal;
+ bias-disable;
+ power-source =
PM8921_GPIO_S4;
+ };
+ };
+ };
+ };
+ };
+
amba {
/* eMMC */
sdcc1: sdcc@1240 {
@@ -173,6 +204,7 @@
status = okay;
vmmc-supply = v3p3_fixed;
vqmmc-supply = v3p3_fixed;
+ mmc-pwrseq = sdcc4_pwrseq;
};
};
};
--
1.9.1
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[PATCH v2 5/6] ARM: dts: qs600: add alias to serial0
This patch add alias node with serial0.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
index 06b3a70..c095849 100644
--- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
@@ -6,6 +6,10 @@
model = CompuLab CM-QS600;
compatible = qcom,apq8064-cm-qs600, qcom,apq8064;
+ aliases {
+ serial0 = gsbi7_serial;
+ };
+
pwrseq {
#address-cells = 1;
#size-cells = 1;
--
1.9.1
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[PATCH v2 0/6] DT: APQ8064 for qcom-dt-next
Hi Andy, Apologies for the long delay in sending new version of the patches. Here are the new patches with fixes and dropping the MDP and panel related changes. Some dt patches which depend on pmic header dt-bindings/pinctrl/qcom,pmic-gpio.h which is availble in linux-next. Changes since v1(https://lkml.org/lkml/2015/7/28/489) - Fixed style related errors spotted by Stephen and Bjorn - dropped mdp and Panel related DT, as it seems to go no where w.r.t cleaning up the driver. - Added few more patches for qs600 which are very trival. thanks, srini Srinivas Kandagatla (6): ARM: dts: ifc6410: Add pwrseq support for WLAN ARM: dts: qs600: add pwrseq support to WLAN ARM: dts: apq8064-ifc6410: add notify led support. ARM: dts: qs600: remove unnecessary i2c pinctrl nodes in board file. ARM: dts: qs600: add alias to serial0 ARM: dts: qs600: Add SD card detect support. arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 46 +++-- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 52 + 2 files changed, 95 insertions(+), 3 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 1/2] iio: light: Add support for UPISEMI uS5182d als and proximity sensor
On 18 August 2015 16:28:20 BST, Adriana Reus adriana.r...@intel.com wrote: Thanks for the review, added some comments inline, next patch set coming soon. Adriana On 15.08.2015 17:27, Jonathan Cameron wrote: On 14/08/15 10:29, Adriana Reus wrote: Add support for UPISEMI us5182d als and proximity sensor. Supports raw readings. Data sheet for this device can be found here: http://www.upi-semi.com/temp/uS5182D-DS-P0103-temp.pdf Signed-off-by: Adriana Reus adriana.r...@intel.com Mostly looking pretty good. I've partly been (slightly) pickier than normal here because we are stalled for a few weeks anyway by the fact the merge window for IIO is now probably done (about a week before Linus opens his) and also we have device tree docs that will need comments or to sit for quite a while on the mailing list. Thanks, Jonathan --- Changes since v2: - Adressed Peter's comments (with the exception of setting the ths_vals array as const - if I do that the compiler will eventually whine because it gets passed as an argument to device_property_read). That should be a giveaway that you want to have a copy rather than one instance of this. Stick a copy in your data structure with defaults if no others are supplied. Note we might have two different instances of this part on one device with different thresholds... - Tried to break down the compound register values into more intuitive definitions. Much improved . - Eliminated the read helper functions. drivers/iio/light/Kconfig | 10 + drivers/iio/light/Makefile | 1 + drivers/iio/light/us5182d.c | 484 3 files changed, 495 insertions(+) create mode 100644 drivers/iio/light/us5182d.c diff --git a/drivers/iio/light/Kconfig b/drivers/iio/light/Kconfig index 7ed859a..0442f01 100644 --- a/drivers/iio/light/Kconfig +++ b/drivers/iio/light/Kconfig @@ -287,6 +287,16 @@ config TSL4531 To compile this driver as a module, choose M here: the module will be called tsl4531. +config US5182D + tristate UPISEMI light and proximity sensor + depends on I2C + help +If you say yes here you get support for the UPISEMI US5182D +ambient light and proximity sensor. + +This driver can also be built as a module. If so, the module +will be called us5182d. + config VCNL4000 tristate VCNL4000 combined ALS and proximity sensor depends on I2C diff --git a/drivers/iio/light/Makefile b/drivers/iio/light/Makefile index 91c74c0..528cc8f 100644 --- a/drivers/iio/light/Makefile +++ b/drivers/iio/light/Makefile @@ -27,4 +27,5 @@ obj-$(CONFIG_STK3310) += stk3310.o obj-$(CONFIG_TCS3414) += tcs3414.o obj-$(CONFIG_TCS3472) += tcs3472.o obj-$(CONFIG_TSL4531) += tsl4531.o +obj-$(CONFIG_US5182D) += us5182d.o obj-$(CONFIG_VCNL4000)+= vcnl4000.o diff --git a/drivers/iio/light/us5182d.c b/drivers/iio/light/us5182d.c new file mode 100644 index 000..9ba99f5 --- /dev/null +++ b/drivers/iio/light/us5182d.c @@ -0,0 +1,484 @@ +/* + * Copyright (c) 2015 Intel Corporation + * + * Driver for UPISEMI us5182d Proximity and Ambient Light Sensor. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * To do: Interrupt support. + */ + +#include linux/kernel.h +#include linux/module.h +#include linux/acpi.h +#include linux/delay.h +#include linux/i2c.h +#include linux/iio/iio.h +#include linux/iio/sysfs.h +#include linux/mutex.h + +#define US5182D_REG_CFG0 0x00 +#define US5182D_REG_CFG1 0x01 +#define US5182D_REG_CFG2 0x02 +#define US5182D_REG_CFG3 0x03 +#define US5182D_REG_CFG4 0x10 + +/* + * Registers for tuning the auto dark current cancelling feature. + * DARK_TH(reg 0x27,0x28) - threshold (counts) for auto dark cancelling. + * when ALS DARK_TH -- ALS_Code = ALS - Upper(0x2A) * Dark + * when ALS DARK_TH -- ALS_Code = ALS - Lower(0x29) * Dark + */ +#define US5182D_REG_UDARK_TH 0x27 +#define US5182D_REG_DARK_AUTO_EN 0x2b +#define US5182D_REG_AUTO_LDARK_GAIN0x29 +#define US5182D_REG_AUTO_HDARK_GAIN0x2a + I'd be tempted to name these to make it clear which reg they are in. US5182D_CFG0_ONESHOT_EN etc. Hartmut did a nice tidy up of another driver the other day. He pulled the register address and elements down into one place and used a it
Re: [PATCH v3 3/3] mtd: add SMEM parser for QCOM platforms
On Mon 17 Aug 16:47 PDT 2015, Mathieu Olivari wrote: On QCOM platforms using MTD devices storage (such as IPQ806x), SMEM is used to store partition layout. This new parser can now be used to read SMEM and use it to register an MTD layout according to its content. Looks good, but the license string should be GPL v2 (lower case v). Just as a hint...I made checkpatch warn you about that a while back ;) The rest is Acked-by: Bjorn Andersson bjorn.anders...@sonymobile.com [..] + +MODULE_LICENSE(GPL V2); Regards, Bjorn -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 2/5] pci:host: Add Altera PCIe host controller driver
On Mon, Aug 17, 2015 at 4:09 AM, Ley Foon Tan lf...@altera.com wrote:
This patch adds the Altera PCIe host controller driver.
Signed-off-by: Ley Foon Tan lf...@altera.com
---
drivers/pci/host/Kconfig | 7 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-altera.c | 543
+
3 files changed, 551 insertions(+)
create mode 100644 drivers/pci/host/pcie-altera.c
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 675c2d1..4b4754a 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -145,4 +145,11 @@ config PCIE_IPROC_BCMA
Say Y here if you want to use the Broadcom iProc PCIe controller
through the BCMA bus interface
snip
+
+/* Address translation table entry size */
+#define ATT_ENTRY_SIZE 8
+
+#define DWORD_MASK 3
+
+struct altera_pcie {
+ struct platform_device *pdev;
+ struct resource *txs;
You have Txs documented in the bindings document, you have a pointer
here, but you've never used it
anywhre in the code? What is it for?
+ void __iomem*cra_base;
+ int irq;
+ u8 root_bus_nr;
+ struct irq_domain *irq_domain;
+ struct resource bus_range;
+ struct list_headresources;
+};
+
snip
+
+static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
+ int where, u32 *value)
+{
+ int ret;
+ u32 headers[TLP_HDR_SIZE];
+
+ if (bus == pcie-root_bus_nr)
+ headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD0);
+ else
+ headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD1);
+
+ headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie-root_bus_nr, devfn),
+ TLP_READ_TAG);
+ headers[2] = TLP_CFG_DW2(bus, devfn, where);
+
+ tlp_write_packet(pcie, headers, 0);
+
+ ret = tlp_read_packet(pcie, value);
+ if (ret)
+ *value = ~0UL; /* return 0x if error */
+
+ return ret;
+}
+
+static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
+ int where, u32 value)
+{
+ u32 headers[TLP_HDR_SIZE];
+
+ if (bus == pcie-root_bus_nr)
+ headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR0);
+ else
+ headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR1);
+
+ headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie-root_bus_nr, devfn),
+ TLP_WRITE_TAG);
+ headers[2] = TLP_CFG_DW2(bus, devfn, where);
+
+ tlp_write_packet(pcie, headers, value);
+
+ tlp_read_packet(pcie, NULL);
You need to check for the error here.
+
+ /* Keep an eye out for changes to the root bus number */
+ if ((bus == pcie-root_bus_nr) (where == PCI_PRIMARY_BUS))
+ pcie-root_bus_nr = (u8)(value);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
snip
+
+static int altera_pcie_parse_dt(struct altera_pcie *pcie)
+{
+ struct resource *cra;
+ struct platform_device *pdev = pcie-pdev;
+
+ cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, Cra);
+ if (!cra) {
+ cra = platform_get_resource_byname(pdev, IORESOURCE_MEM,
cra);
+ if (!cra) {
+ dev_err(pdev-dev,
+ no cra memory resource defined\n);
+ return -ENODEV;
+ }
+ }
+
What about Txs?
Dinh
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Re: [PATCH 1/2] ARM: dts: rockchip: add veyron-jaq board
Hi Brian,
Am Dienstag, 18. August 2015, 11:44:14 schrieb Brian Norris:
a.k.a. Haier Chromebook 11
Signed-off-by: Brian Norris briannor...@chromium.org
Cc: Alexandru M Stan ams...@chromium.org
Cc: Douglas Anderson diand...@chromium.org
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/rk3288-veyron-jaq.dts | 176
2 files changed, 177 insertions(+)
create mode 100644 arch/arm/boot/dts/rk3288-veyron-jaq.dts
missing binding documentation in
Documentation/devicetree/bindings/arm/rockchip.txt (needs new entry above
Jerry)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7805a6541a38..7a2c3c88ce9e 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -493,6 +493,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-jerry.dtb \
rk3288-veyron-minnie.dtb \
rk3288-veyron-pinky.dtb \
+ rk3288-veyron-jaq.dtb \
rk3288-veyron-speedy.dtb
please sort alphabetically (in this case somewhere above jerry)
dtb-$(CONFIG_ARCH_S3C24XX) += \
s3c2416-smdk2416.dtb
diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts
b/arch/arm/boot/dts/rk3288-veyron-jaq.dts new file mode 100644
index ..ea6130156216
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
@@ -0,0 +1,176 @@
+/*
+ * Google Veyron Jaq Rev 1+ board device tree source
+ *
+ * Copyright 2015 Google, Inc
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the Software), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include rk3288-veyron-chromebook.dtsi
+#include cros-ec-sbs.dtsi
+
+/ {
+ model = Google Jaq;
+ compatible = google,veyron-jaq-rev5, google,veyron-jaq-rev4,
+ google,veyron-jaq-rev3, google,veyron-jaq-rev2,
+ google,veyron-jaq-rev1, google,veyron-jaq,
+ google,veyron, rockchip,rk3288;
+
+ panel_regulator: panel-regulator {
+ compatible = regulator-fixed;
+ enable-active-high;
+ gpio = gpio7 14 GPIO_ACTIVE_HIGH;
+ pinctrl-names = default;
+ pinctrl-0 = lcd_enable_h;
+ regulator-name = panel_regulator;
+ vin-supply = vcc33_sys;
+ };
+
+ vcc18_lcd: vcc18-lcd {
+ compatible = regulator-fixed;
+ enable-active-high;
+ gpio = gpio2 13 GPIO_ACTIVE_HIGH;
+ pinctrl-names = default;
+ pinctrl-0 = avdd_1v8_disp_en;
+ regulator-name = vcc18_lcd;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = vcc18_wl;
+ };
+
+ backlight_regulator: backlight-regulator {
+ compatible = regulator-fixed;
+ enable-active-high;
+ gpio = gpio2 12 GPIO_ACTIVE_HIGH;
+ pinctrl-names = default;
+ pinctrl-0 = bl_pwr_en;
+ regulator-name = backlight_regulator;
+ vin-supply = vcc33_sys;
+ startup-delay-us = 15000;
+ };
Re: [PATCH v4 4/5] Documentation: dt-bindings: pci: altera pcie device tree binding
On Mon, Aug 17, 2015 at 4:09 AM, Ley Foon Tan lf...@altera.com wrote:
This patch adds the bindings for Altera PCIe host controller driver and
Altera PCIe MSI driver.
Signed-off-by: Ley Foon Tan lf...@altera.com
---
.../devicetree/bindings/pci/altera-pcie-msi.txt| 27
.../devicetree/bindings/pci/altera-pcie.txt| 49
++
2 files changed, 76 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
b/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
new file mode 100644
index 000..7f330c9
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
@@ -0,0 +1,27 @@
+* Altera PCIe MSI controller
+
+Required properties:
+- compatible: should contain altr,msi-1.0
+- reg: specifies the physical base address of the controller and
+ the length of the memory mapped region.
+- reg-names: Must include the following entries:
+ csr: CSR registers
+ vector_slave: vectors region
Can you be a little bit more specific here? What is a vectors region?
Also, I'm not 100% sure, but I think vector-slave should be used.
+-interrupts: specifies the interrupt source of the parent interrupt
+ controller. The format of the interrupt specifier depends on
the
+ parent interrupt controller.
Need to document interrupt-parent .
+- num-vectors: Number of vectors, range 1 to 32.
+- msi-controller: indicates that this is MSI controller node
+
+
+Example
+msi0: msi@0xFF20 {
+ compatible = altr,msi-1.0;
+ reg = 0xFF20 0x0010
+ 0xFF200010 0x0080;
+ reg-names = csr, vector_slave;
+ interrupt-parent = hps_0_arm_gic_0;
+ interrupts = 0 42 4;
+ msi-controller = 1;
+ num-vectors = 32;
+};
diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt
b/Documentation/devicetree/bindings/pci/altera-pcie.txt
new file mode 100644
index 000..73a8dc0
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/altera-pcie.txt
@@ -0,0 +1,49 @@
+* Altera PCIe controller
+
+Required properties:
+- compatible : should contain altr,pcie-root-port-1.0
+- reg: A list of physical base address and length for TXS and CRA.
+- reg-names: Must include the following entries:
+ Txs or txs: TXS region
What is a TXS region?
+ Cra or cra: Control register access region
+-interrupts: specifies the interrupt source of the parent interrupt
controller.
+ The format of the interrupt specifier depends on the parent
interrupt
+ controller.
+- device_type: must be pci
+- #address-cells: set to 3
+- #size-cells: set to 2
+- #interrupt-cells:set to 1
+- ranges: Describes the translation of addresses for root ports
and standard
+ PCI regions.
+- interrupt-map-mask and interrupt-map: standard PCI properties
+ to define the mapping of the PCIe interface to interrupt
+ numbers.
interrupt-parent ?
Dinh
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Re: [PATCH v3 1/3] ARM: qcom: add SFPB nodes to IPQ806x dts
On Mon 17 Aug 16:47 PDT 2015, Mathieu Olivari wrote:
Add one new node to the ipq806x.dtsi file to declare register the
hardware spinlock devices. This mechanism is required to be used by
other drivers such as SMEM.
Reviewed-by: Bjorn Andersson bjorn.anders...@sonymobile.com
Signed-off-by: Mathieu Olivari math...@codeaurora.org
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi
b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 9f727d8..8d366ae 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -329,5 +329,16 @@
#reset-cells = 1;
};
+ sfpb_mutex_block: syscon@1200600 {
+ compatible = syscon;
+ reg = 0x01200600 0x100;
I have this block listed to start at 0x120 and used 0x604 as offset
when testing this. In my docs there's nothing in those first 0x600 bytes
though, so this works fine for me.
+ };
+ };
+
+ sfpb_mutex: sfpb-mutex {
+ compatible = qcom,sfpb-mutex;
+ syscon = sfpb_mutex_block 4 4;
+
+ #hwlock-cells = 1;
};
};
Regards,
Bjorn
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Re: [PATCH v3 2/4] ASoC: rockchip: Add rockchip SPDIF transceiver driver
Hi Sjoerd,
+static int rk_spdif_probe(struct platform_device *pdev)
+{
+ struct rk_spdif_dev *spdif;
+ struct resource *res;
+ void __iomem *regs;
+ int ret;
+
+ spdif = devm_kzalloc(pdev-dev, sizeof(*spdif), GFP_KERNEL);
+ if (!spdif)
+ return -ENOMEM;
+
+ spdif-hclk = devm_clk_get(pdev-dev, spdif_hclk);
I guess this could be named just hclk - as it is the identifier local to the
spdif-ip. (Of course in the binding too)
+ if (IS_ERR(spdif-hclk)) {
+ dev_err(pdev-dev, Can't retrieve rk_spdif bus clock\n);
+ return PTR_ERR(spdif-hclk);
+ }
+ ret = clk_prepare_enable(spdif-hclk);
+ if (ret) {
+ dev_err(spdif-dev, hclock enable failed %d\n, ret);
+ return ret;
+ }
+
+ spdif-mclk = devm_clk_get(pdev-dev, spdif_clk);
The Rockchip TRMs (and the rest of the driver as well) refer to this clock as
mclk, so I guess the identifier could just be named the same.
+ if (IS_ERR(spdif-mclk)) {
+ dev_err(pdev-dev, Can't retrieve rk_spdif master clock\n);
+ return PTR_ERR(spdif-hclk);
+ }
+
+ ret = clk_prepare_enable(spdif-mclk);
+ if (ret) {
+ dev_err(spdif-dev, clock enable failed %d\n, ret);
+ return ret;
+ }
I guess this plays into what Mark already wrote, but as the code stands right
now, you enable the mclk here and then through runtime_resume as well, so that
it stays running all the time, as the refcount is either 2 or 1 but never 0.
Also I don't think mixing devm_clk_get + clk_prepare_enable calls works well.
If the devm_clk_get(... spdif_clk) fails, the hclk would stay running right
now.
[...]
+static int rk_spdif_remove(struct platform_device *pdev)
+{
+ struct rk_spdif_dev *spdif = dev_get_drvdata(pdev-dev);
+
+ pm_runtime_disable(pdev-dev);
+ if (!pm_runtime_status_suspended(pdev-dev))
+ rk_spdif_runtime_suspend(pdev-dev);
+
+ clk_disable_unprepare(spdif-mclk);
+ clk_disable_unprepare(spdif-hclk);
+ snd_dmaengine_pcm_unregister(pdev-dev);
+ snd_soc_unregister_component(pdev-dev);
I think the ordering should stay symmetric to the probe function, where you
have
clk_enable
snd_register
so here it should probably be
snd_unregister
clk_disable
Heiko
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Re: [PATCH v3 2/3] ARM: qcom: add SMEM device node to IPQ806x dts
On Mon 17 Aug 16:47 PDT 2015, Mathieu Olivari wrote:
SMEM is used on IPQ806x to store various board related information such
as boot device and flash partition layout. We'll declare it as a device
so we can make use of it thanks to the new SMEM soc driver.
Signed-off-by: Mathieu Olivari math...@codeaurora.org
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi
b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 8d366ae..85dbccf 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -55,7 +55,7 @@
no-map;
};
- smem@4100 {
+ smem: smem@4100 {
I would preferred if you used a name like smem_region, although I
don't think we will use the phandle name smem for anything else...
reg = 0x4100 0x20;
no-map;
};
@@ -341,4 +341,10 @@
#hwlock-cells = 1;
};
+
+ smem {
+ compatible = qcom,smem;
+ memory-region = smem;
+ hwlocks = sfpb_mutex 3;
+ };
};
Acked-by: Bjorn Andersson bjorn.anders...@sonymobile.com
Regards,
Bjorn
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Re: [PATCH v3 0/3] qcom: Add SMEM MTD parser
On Tue, Aug 18, 2015 at 02:30:14PM +0200, Jonas Gorski wrote: Hi, On Tue, Aug 18, 2015 at 1:47 AM, Mathieu Olivari math...@codeaurora.org wrote: QCOM platforms such as IPQ806x are using SMEM to store their flash layout. This patch set adds the DT nodes required to instanciate SMEM on IPQ806x and add an MTD parser using it. This change is based on the SMEM driver posted here: *https://lkml.org/lkml/2015/7/27/1125 Nice work. After testing it on AP148 I see this: [2.481507] 12 qcom-smem partitions found on MTD device qcom-nandc [2.481540] Creating 12 MTD partitions on qcom-nandc: [2.486690] 0x-0x0004 : 0:SBL1 [2.492842] 0x0004-0x0018 : 0:MIBIB [2.497857] 0x0018-0x002c : 0:SBL2 [2.502895] 0x002c-0x0054 : 0:SBL3 [2.507828] 0x0054-0x0066 : 0:DDRCONFIG [2.512857] 0x0066-0x0078 : 0:SSD [2.518074] 0x0078-0x00a0 : 0:TZ [2.522834] 0x00a0-0x00c8 : 0:RPM [2.527607] 0x00c8-0x0118 : 0:APPSBL [2.532472] 0x0118-0x0120 : 0:APPSBLENV [2.537586] 0x0120-0x0134 : 0:ART [2.543140] 0x0134-0x0534 : rootfs Are all these partition names supposed to be prefixed with 0:? This is using the OpenWrt applied version. Yes. These are the names as they are listed in SMEM. If you run the smem command from the U-boot prompt, you will see the same information. I'm not sure what the 0: prefix means, and where it comes from to be honest. Jonas -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 2/2] devicetree: Add documentation for UPISEMI us5182d ALS and Proximity sensor
On 18 August 2015 16:13:02 BST, Adriana Reus adriana.r...@intel.com wrote:
Thank you Jonathan, I'll add a new patch set soon, added some comments
inline also.
Adriana
On 15.08.2015 17:31, Jonathan Cameron wrote:
On 14/08/15 10:29, Adriana Reus wrote:
Added entries in trivial-devices and i2c/vendor-prefixes for
the us5182d als and proximity sensor. Also added a documentation
file for
this sensor's properties.
Signed-off-by: Adriana Reus adriana.r...@intel.com
It's not a trivial device if it has it's own docs. So don't add it
to that list
(the point is to not have separate docs for devices that don't really
have
any device tree data other than where they are.
right, I'll add a new path set soon.
Few more bits inline.
---
No changes - resending because I forgot to cc devicetree.
.../devicetree/bindings/i2c/trivial-devices.txt| 1 +
.../devicetree/bindings/iio/light/us5182d.txt | 24
++
.../devicetree/bindings/vendor-prefixes.txt| 1 +
3 files changed, 26 insertions(+)
create mode 100644
Documentation/devicetree/bindings/iio/light/us5182d.txt
diff --git
a/Documentation/devicetree/bindings/i2c/trivial-devices.txt
b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
index 00f8652..96d3b9c 100644
--- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt
+++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
@@ -99,4 +99,5 @@ ti,tsc2003I2C Touch-Screen Controller
ti,tmp102 Low Power Digital Temperature Sensor with SMBUS/Two
Wire Serial Interface
ti,tmp103 Low Power Digital Temperature Sensor with SMBUS/Two
Wire Serial Interface
ti,tmp275 Digital Temperature Sensor
+upisemi,usd5182Als and Proximity Sensor
winbond,wpct301 i2c trusted platform module (TPM)
diff --git a/Documentation/devicetree/bindings/iio/light/us5182d.txt
b/Documentation/devicetree/bindings/iio/light/us5182d.txt
new file mode 100644
index 000..9ac3336
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/light/us5182d.txt
@@ -0,0 +1,24 @@
+* UPISEMI us5182d I2C ALS and Proximity sensor
+
+Required properties:
+- compatible: must be upisemi,usd5182
+- reg: the I2C address of the device
+
+Optional properties:
+- upisemi,glass-coef: glass attenuation factor
+- upisemi,dark-ths: array of thresholds corresponding to every
scale
That needs more detail. I've read the driver and I am not sure what
exactly
you mean! Why should a scale have a threshold?
I'll try to be more specific. These are values representing adc counts,
that's why there are different values corresponding to every scale.
+- upisemi,upper-dark-gain: tuning factor applied when light th
+- upisemi,lower-dark-gain: tuning factor applied when light th
+
+Example:
+
+usd5182@39 {
+compatible = upisemi,usd5182;
+reg = 0x39;
+upisemi,glass-coef = 1000 ;
+upisemi,dark-ths = /bits/ 16 170 200 512 512 800
2000 4000 8000;
+upisemi,upper-dark-gain = /bits/ 8 0x00;
+upisemi,lower-dark-gain = /bits/ 8 0x16;
Not sure why these are in hex.. Or why we care if they are 8 bits.
If there is a limit
on the possible values, perhaps mention it in the docs above.
I should have been (much) more specific here: that represents a float
number with 4 integer bits and 4 fractional bits (Q4.4), so I find hex
more intuitive since it's split in half, let me know if you think
otherwise.
One for the device tree guys to answer rather than me. My gut feeling would be
a representation that made this obvious but I have no idea what normal choice
would be.
I'll add a more complete description. As for the /bits/ x
it's because currently in the driver I use the read_property_u8 or
*_u16
functions, these require that the dts entry be as I wrote it in the
example, and since it's an example it should be functional, so I feel
that is ok as it is.
+};
+
One blank line at the end is neough.
+
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index d444757..5b40bab 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -211,6 +211,7 @@ toshiba Toshiba Corporation
toumazToumaz
tplinkTP-LINK Technologies Co., Ltd.
truly Truly Semiconductors Limited
+upisemiuPI Semiconductor Corp.
usi Universal Scientific Industrial Co., Ltd.
v3V3 Semiconductor
variscite Variscite Ltd.
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[PATCH 2/2] ARM: dts: rockchip: correct regulator PM properties
This DTS file was submitted with non-upstream bindings. I happened
across this while reviewing the jaq DTS.
Signed-off-by: Brian Norris briannor...@chromium.org
Cc: Alexandru M Stan ams...@chromium.org
Cc: Douglas Anderson diand...@chromium.org
---
Tested on jaq, not minnie
arch/arm/boot/dts/rk3288-veyron-minnie.dts | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts
b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
index 0e30bd6bf92b..6f619c154dc6 100644
--- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
@@ -128,12 +128,16 @@
regulator-min-microvolt = 330;
regulator-max-microvolt = 330;
regulator-name = vcc33_touch;
- regulator-suspend-mem-disabled;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
};
vcc5v_touch: SWITCH_REG2 {
regulator-name = vcc5v_touch;
- regulator-suspend-mem-disabled;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
};
};
};
--
2.5.0.276.gf5e568e
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[PATCH 1/2] ARM: dts: rockchip: add veyron-jaq board
a.k.a. Haier Chromebook 11
Signed-off-by: Brian Norris briannor...@chromium.org
Cc: Alexandru M Stan ams...@chromium.org
Cc: Douglas Anderson diand...@chromium.org
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/rk3288-veyron-jaq.dts | 176
2 files changed, 177 insertions(+)
create mode 100644 arch/arm/boot/dts/rk3288-veyron-jaq.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7805a6541a38..7a2c3c88ce9e 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -493,6 +493,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-jerry.dtb \
rk3288-veyron-minnie.dtb \
rk3288-veyron-pinky.dtb \
+ rk3288-veyron-jaq.dtb \
rk3288-veyron-speedy.dtb
dtb-$(CONFIG_ARCH_S3C24XX) += \
s3c2416-smdk2416.dtb
diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts
b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
new file mode 100644
index ..ea6130156216
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
@@ -0,0 +1,176 @@
+/*
+ * Google Veyron Jaq Rev 1+ board device tree source
+ *
+ * Copyright 2015 Google, Inc
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the Software), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include rk3288-veyron-chromebook.dtsi
+#include cros-ec-sbs.dtsi
+
+/ {
+ model = Google Jaq;
+ compatible = google,veyron-jaq-rev5, google,veyron-jaq-rev4,
+google,veyron-jaq-rev3, google,veyron-jaq-rev2,
+google,veyron-jaq-rev1, google,veyron-jaq,
+google,veyron, rockchip,rk3288;
+
+ panel_regulator: panel-regulator {
+ compatible = regulator-fixed;
+ enable-active-high;
+ gpio = gpio7 14 GPIO_ACTIVE_HIGH;
+ pinctrl-names = default;
+ pinctrl-0 = lcd_enable_h;
+ regulator-name = panel_regulator;
+ vin-supply = vcc33_sys;
+ };
+
+ vcc18_lcd: vcc18-lcd {
+ compatible = regulator-fixed;
+ enable-active-high;
+ gpio = gpio2 13 GPIO_ACTIVE_HIGH;
+ pinctrl-names = default;
+ pinctrl-0 = avdd_1v8_disp_en;
+ regulator-name = vcc18_lcd;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = vcc18_wl;
+ };
+
+ backlight_regulator: backlight-regulator {
+ compatible = regulator-fixed;
+ enable-active-high;
+ gpio = gpio2 12 GPIO_ACTIVE_HIGH;
+ pinctrl-names = default;
+ pinctrl-0 = bl_pwr_en;
+ regulator-name = backlight_regulator;
+ vin-supply = vcc33_sys;
+ startup-delay-us = 15000;
+ };
+};
+
+rk808 {
+ pinctrl-names = default;
+ pinctrl-0 = pmic_int_l dvs_1 dvs_2;
+ dvs-gpios = gpio7 12 GPIO_ACTIVE_HIGH,
+ gpio7 15 GPIO_ACTIVE_HIGH;
+
+ regulators {
+ mic_vcc: LDO_REG2 {
+ regulator-name =
Re: [PATCH 2/2] ARM: dts: rockchip: correct regulator PM properties
Hi Brian,
thanks for catching these oversights, but see below
Am Dienstag, 18. August 2015, 11:44:15 schrieb Brian Norris:
This DTS file was submitted with non-upstream bindings. I happened
across this while reviewing the jaq DTS.
Signed-off-by: Brian Norris briannor...@chromium.org
Cc: Alexandru M Stan ams...@chromium.org
Cc: Douglas Anderson diand...@chromium.org
---
Tested on jaq, not minnie
arch/arm/boot/dts/rk3288-veyron-minnie.dts | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts
b/arch/arm/boot/dts/rk3288-veyron-minnie.dts index
0e30bd6bf92b..6f619c154dc6 100644
--- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
@@ -128,12 +128,16 @@
regulator-min-microvolt = 330;
regulator-max-microvolt = 330;
regulator-name = vcc33_touch;
- regulator-suspend-mem-disabled;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
};
vcc5v_touch: SWITCH_REG2 {
regulator-name = vcc5v_touch;
- regulator-suspend-mem-disabled;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
wouldn't regulator-suspend-mem-disabled translate to regulator-off-in-suspend?
At least looks like it according to https://lkml.org/lkml/2013/7/25/592
Heiko
};
};
};
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Re: [PATCH 2/2] ARM: dts: rockchip: correct regulator PM properties
Hello Heiko,
On Tue, Aug 18, 2015 at 9:17 PM, Heiko Stuebner he...@sntech.de wrote:
Hi Brian,
thanks for catching these oversights, but see below
Am Dienstag, 18. August 2015, 11:44:15 schrieb Brian Norris:
This DTS file was submitted with non-upstream bindings. I happened
across this while reviewing the jaq DTS.
Signed-off-by: Brian Norris briannor...@chromium.org
Cc: Alexandru M Stan ams...@chromium.org
Cc: Douglas Anderson diand...@chromium.org
---
Tested on jaq, not minnie
arch/arm/boot/dts/rk3288-veyron-minnie.dts | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts
b/arch/arm/boot/dts/rk3288-veyron-minnie.dts index
0e30bd6bf92b..6f619c154dc6 100644
--- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
@@ -128,12 +128,16 @@
regulator-min-microvolt = 330;
regulator-max-microvolt = 330;
regulator-name = vcc33_touch;
- regulator-suspend-mem-disabled;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
};
vcc5v_touch: SWITCH_REG2 {
regulator-name = vcc5v_touch;
- regulator-suspend-mem-disabled;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
wouldn't regulator-suspend-mem-disabled translate to regulator-off-in-suspend?
Correct, the downstream regulator-suspend-mem-disabled is equivalent
to regulator-off-in-suspend in mainline.
At least looks like it according to https://lkml.org/lkml/2013/7/25/592
I guess you meant https://lkml.org/lkml/2014/10/10/162 since it was
Chanwoo's and not Vincent's version that finally landed.
Heiko
Best regards,
Javier
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Re: [PATCH 2/2] ARM: dts: rockchip: correct regulator PM properties
On Tue, Aug 18, 2015 at 10:30 PM, Javier Martinez Canillas
jav...@dowhile0.org wrote:
On Tue, Aug 18, 2015 at 9:17 PM, Heiko Stuebner he...@sntech.de wrote:
vcc5v_touch: SWITCH_REG2 {
regulator-name = vcc5v_touch;
- regulator-suspend-mem-disabled;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
wouldn't regulator-suspend-mem-disabled translate to
regulator-off-in-suspend?
Correct, the downstream regulator-suspend-mem-disabled is equivalent
to regulator-off-in-suspend in mainline.
At least looks like it according to https://lkml.org/lkml/2013/7/25/592
I guess you meant https://lkml.org/lkml/2014/10/10/162 since it was
Chanwoo's and not Vincent's version that finally landed.
oh, now I got that you referenced Vincent's patch just to show the
regulator-suspend-mem-disabled property description.
Sorry for the noise then but yes you are right about the translation :-)
Best regards,
Javier
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Re: [PATCH 3/7] drm/vc4: Add KMS support for Raspberry Pi.
Daniel Vetter dan...@ffwll.ch writes: On Thu, Aug 13, 2015 at 01:44:03PM -0700, Eric Anholt wrote: Daniel Vetter dan...@ffwll.ch writes: On Wed, Aug 12, 2015 at 05:56:16PM -0700, Eric Anholt wrote: This is the start of a full VC4 driver. Right now this just supports configuring the display using a pre-existing video mode (because changing the pixel clock isn't available yet, and doesn't work when it is). However, this is enough for fbcon and bringing up X using xf86-video-modesetting. Signed-off-by: Eric Anholt e...@anholt.net --- drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/vc4/Kconfig | 14 + drivers/gpu/drm/vc4/Makefile | 18 ++ drivers/gpu/drm/vc4/vc4_bo.c | 54 drivers/gpu/drm/vc4/vc4_crtc.c| 583 ++ drivers/gpu/drm/vc4/vc4_debugfs.c | 38 +++ drivers/gpu/drm/vc4/vc4_drv.c | 249 +++ drivers/gpu/drm/vc4/vc4_drv.h | 123 +++ drivers/gpu/drm/vc4/vc4_hdmi.c| 651 ++ drivers/gpu/drm/vc4/vc4_hvs.c | 172 ++ drivers/gpu/drm/vc4/vc4_kms.c | 84 + drivers/gpu/drm/vc4/vc4_plane.c | 320 +++ drivers/gpu/drm/vc4/vc4_regs.h| 562 14 files changed, 2871 insertions(+) create mode 100644 drivers/gpu/drm/vc4/Kconfig create mode 100644 drivers/gpu/drm/vc4/Makefile create mode 100644 drivers/gpu/drm/vc4/vc4_bo.c create mode 100644 drivers/gpu/drm/vc4/vc4_crtc.c create mode 100644 drivers/gpu/drm/vc4/vc4_debugfs.c create mode 100644 drivers/gpu/drm/vc4/vc4_drv.c create mode 100644 drivers/gpu/drm/vc4/vc4_drv.h create mode 100644 drivers/gpu/drm/vc4/vc4_hdmi.c create mode 100644 drivers/gpu/drm/vc4/vc4_hvs.c create mode 100644 drivers/gpu/drm/vc4/vc4_kms.c create mode 100644 drivers/gpu/drm/vc4/vc4_plane.c create mode 100644 drivers/gpu/drm/vc4/vc4_regs.h Made a quick pass and found a few things to update to latest drm developments. Of course didn't look at the hardware details since no clue, but looks really nice overall. If you have anything about the hardware that you were curious about, I'd be interested in trying to explain them in the comments to the extent that I can. It's unfortunate that we haven't shipped docs for the display side of things, but had to do a lot of reading of the verilog just to get this far, anyway. The only thing I spotted is that you right now only register a primary and cursor plane. I guess the plan we once discussed about exposing piles of planes for -modesetting accel isn't there yet? But otherwise I really didn't go into the hardware details. Yeah, I haven't done piles of planes because what we have right now means I don't have to do the bandwidth limits tracking yet. signature.asc Description: PGP signature
Re: [PATCH V7 1/2] mtd: spi-nor: Bindings for Cadence Quad SPI Flash Controller driver.
Hi all, On 08/18/2015 12:48 AM, Vikas MANOCHA wrote: [...] +Required properties: +- compatible : Should be cdns,qspi-nor. +- reg : Contains two entries, each of which is a tuple consisting of a +physical address and length. The first entry is the address and +length of the controller register set. The second entry is the +address and length of the QSPI Controller data area. Controller data area, i think it means mapped NOR Flash address ? Probably ; Graham ? If yes, it would be more clear with Physical base address size of NOR Flash. This is the Direct mode thing, correct ? We don't support this, so I think we should drop this bit altogether and keep only one single address in this field. No it's not. It's the location of the SRAM fifo. Also direct mode location I think, if that were ever used. The size is determined by a configuration parameter during system design. On Altera Cyclone5 the size is really big compared to SRAM fifo. I don't know why, maybe some hw engineer thought it would be better to have a large size in case direct mode was used. BR, Graham -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 2/3] ARM: qcom: add SMEM device node to IPQ806x dts
SMEM is used on IPQ806x to store various board related information such
as boot device and flash partition layout. We'll declare it as a device
so we can make use of it thanks to the new SMEM soc driver.
Signed-off-by: Mathieu Olivari math...@codeaurora.org
---
Notes:
v2:
*Rename smem tag into smem_region
arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi
b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 8d366ae..9834c94 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -55,7 +55,7 @@
no-map;
};
- smem@4100 {
+ smem_region: smem@4100 {
reg = 0x4100 0x20;
no-map;
};
@@ -341,4 +341,10 @@
#hwlock-cells = 1;
};
+
+ smem {
+ compatible = qcom,smem;
+ memory-region = smem_region;
+ hwlocks = sfpb_mutex 3;
+ };
};
--
2.1.4
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[PATCH v4 3/3] mtd: add SMEM parser for QCOM platforms
On QCOM platforms using MTD devices storage (such as IPQ806x), SMEM is
used to store partition layout. This new parser can now be used to read
SMEM and use it to register an MTD layout according to its content.
Signed-off-by: Mathieu Olivari math...@codeaurora.org
---
Notes:
v2:
*Release the SPI device reference after looking it up (put_device())
*Represent SMEM data as __le32 rather than u32
*Move new DT nodes in their proper respective location
*Address readability concerns in MTD parser
v3:
*Redefine SMEM functions prototypes for better readability
*Duplicate MTD name instead of pointing to SMEM string location in case
mtd layer tries to free it
*Rework some of the comments
v4:
*Fix case in the license string
drivers/mtd/Kconfig | 7 ++
drivers/mtd/Makefile | 1 +
drivers/mtd/qcom_smem_part.c | 246 +++
3 files changed, 254 insertions(+)
create mode 100644 drivers/mtd/qcom_smem_part.c
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index a03ad29..debc887 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -155,6 +155,13 @@ config MTD_BCM47XX_PARTS
This provides partitions parser for devices based on BCM47xx
boards.
+config MTD_QCOM_SMEM_PARTS
+ tristate QCOM SMEM partitioning support
+ depends on QCOM_SMEM
+ help
+ This provides partitions parser for QCOM devices using SMEM
+ such as IPQ806x.
+
comment User Modules And Translation Layers
#
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 99bb9a1..b3c7de4 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_MTD_AFS_PARTS) += afs.o
obj-$(CONFIG_MTD_AR7_PARTS)+= ar7part.o
obj-$(CONFIG_MTD_BCM63XX_PARTS)+= bcm63xxpart.o
obj-$(CONFIG_MTD_BCM47XX_PARTS)+= bcm47xxpart.o
+obj-$(CONFIG_MTD_QCOM_SMEM_PARTS) += qcom_smem_part.o
# 'Users' - code which presents functionality to userspace.
obj-$(CONFIG_MTD_BLKDEVS) += mtd_blkdevs.o
diff --git a/drivers/mtd/qcom_smem_part.c b/drivers/mtd/qcom_smem_part.c
new file mode 100644
index 000..b4f8acc
--- /dev/null
+++ b/drivers/mtd/qcom_smem_part.c
@@ -0,0 +1,246 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/kernel.h
+#include linux/device.h
+#include linux/slab.h
+
+#include linux/mtd/mtd.h
+#include linux/mtd/partitions.h
+#include linux/spi/spi.h
+#include linux/module.h
+
+#include linux/soc/qcom/smem.h
+
+/* Processor/host identifier for the application processor */
+#define QCOM_SMEM_GLOBAL 0
+
+/* SMEM items index */
+#define SMEM_AARM_PARTITION_TABLE 9
+#define SMEM_BOOT_FLASH_TYPE 421
+#define SMEM_BOOT_FLASH_BLOCK_SIZE 424
+
+/* SMEM Flash types */
+#define SMEM_FLASH_NAND2
+#define SMEM_FLASH_SPI 6
+
+#define SMEM_PART_NAME_SZ 16
+#define SMEM_PARTS_MAX 32
+
+struct smem_partition {
+ char name[SMEM_PART_NAME_SZ];
+ __le32 start;
+ __le32 size;
+ __le32 attr;
+};
+
+struct smem_partition_table {
+ u8 magic[8];
+ __le32 version;
+ __le32 len;
+ struct smem_partition parts[SMEM_PARTS_MAX];
+};
+
+/* SMEM Magic values in partition table */
+static const u8 SMEM_PTABLE_MAGIC[] = {
+ 0xaa, 0x73, 0xee, 0x55,
+ 0xdb, 0xbd, 0x5e, 0xe3,
+};
+
+static int qcom_smem_get_flash_blksz(void)
+{
+ int ret;
+ size_t size;
+ u64 *smem_blksz;
+
+ ret = qcom_smem_get(QCOM_SMEM_GLOBAL, SMEM_BOOT_FLASH_BLOCK_SIZE,
+ (void **) smem_blksz, size);
+
+ if (ret 0) {
+ pr_err(Unable to read flash blksz from SMEM\n);
+ return -ENOENT;
+ }
+
+ if (size != sizeof(*smem_blksz)) {
+ pr_err(Invalid flash blksz size in SMEM\n);
+ return -EINVAL;
+ }
+
+ /* Sanity check block size value before casting it */
+ if (*smem_blksz INT_MAX) {
+ pr_err(Invalid flash block size in SMEM\n);
+ return -EINVAL;
+ }
+
+ return (int) *smem_blksz;
+}
+
+static int qcom_smem_get_flash_type(void)
+{
+ int ret;
+ size_t size;
+ u64 *smem_flash_type;
+
+ ret = qcom_smem_get(QCOM_SMEM_GLOBAL, SMEM_BOOT_FLASH_TYPE,
+ (void **) smem_flash_type, size);
+
+ if (ret 0) {
+
[PATCH v4 1/3] ARM: qcom: add SFPB nodes to IPQ806x dts
Add one new node to the ipq806x.dtsi file to declare register the
hardware spinlock devices. This mechanism is required to be used by
other drivers such as SMEM.
Signed-off-by: Mathieu Olivari math...@codeaurora.org
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi
b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 9f727d8..8d366ae 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -329,5 +329,16 @@
#reset-cells = 1;
};
+ sfpb_mutex_block: syscon@1200600 {
+ compatible = syscon;
+ reg = 0x01200600 0x100;
+ };
+ };
+
+ sfpb_mutex: sfpb-mutex {
+ compatible = qcom,sfpb-mutex;
+ syscon = sfpb_mutex_block 4 4;
+
+ #hwlock-cells = 1;
};
};
--
2.1.4
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[PATCH v2 7/7] ARM: bcm2835: Add VC4 to the device tree.
VC4 is the GPU (display and 3D) present on the 2835.
Signed-off-by: Eric Anholt e...@anholt.net
---
v2: Sort by register address, mark HDMI as disabled by default in the
SoC file and enable it from -rpi.
arch/arm/boot/dts/bcm2835-rpi.dtsi | 4
arch/arm/boot/dts/bcm2835.dtsi | 44 ++
2 files changed, 48 insertions(+)
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi
b/arch/arm/boot/dts/bcm2835-rpi.dtsi
index 29cc7ba..f7217906 100644
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -49,6 +49,10 @@
status = okay;
};
+hdmi {
+ status = okay;
+};
+
sdhci {
status = okay;
bus-width = 4;
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index 20574cc..e625a21 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -1,4 +1,5 @@
#include dt-bindings/pinctrl/bcm2835.h
+#include dt-bindings/gpio/gpio.h
#include skeleton.dtsi
/ {
@@ -131,6 +132,18 @@
status = disabled;
};
+ pv0: brcm,vc4-pixelvalve@7e206000 {
+ compatible = brcm,vc4-pixelvalve;
+ reg = 0x7e206000 0x100;
+ interrupts = 2 13; /* pwa2 */
+ };
+
+ pv1: brcm,vc4-pixelvalve@7e207000 {
+ compatible = brcm,vc4-pixelvalve;
+ reg = 0x7e207000 0x100;
+ interrupts = 2 14; /* pwa1 */
+ };
+
sdhci: sdhci@7e30 {
compatible = brcm,bcm2835-sdhci;
reg = 0x7e30 0x100;
@@ -139,6 +152,12 @@
status = disabled;
};
+ hvs: brcm,hvs@7e40 {
+ compatible = brcm,vc4-hvs;
+ reg = 0x7e40 0x6000;
+ interrupts = 2 1;
+ };
+
i2c1: i2c@7e804000 {
compatible = brcm,bcm2835-i2c;
reg = 0x7e804000 0x1000;
@@ -159,6 +178,23 @@
status = disabled;
};
+ pv2: brcm,vc4-pixelvalve@7e807000 {
+ compatible = brcm,vc4-pixelvalve;
+ reg = 0x7e807000 0x100;
+ interrupts = 2 10; /* pixelvalve */
+ };
+
+ hdmi: brcm,vc4-hdmi@7e902000 {
+ compatible = brcm,vc4-hdmi;
+ reg = 0x7e902000 0x600,
+ 0x7e808000 0x100;
+ interrupts = 2 8, 2 9;
+ ddc = i2c2;
+ hpd-gpio = gpio 46 GPIO_ACTIVE_HIGH;
+ crtc = pv2;
+ status = disabled;
+ };
+
usb@7e98 {
compatible = brcm,bcm2835-usb;
reg = 0x7e98 0x1;
@@ -168,6 +204,14 @@
arm-pmu {
compatible = arm,arm1176-pmu;
};
+
+ vc4: vc4@0x7e4c {
+ compatible = brcm,vc4;
+
+ crtcs = pv0, pv1, pv2;
+ encoders = hdmi;
+ hvss = hvs;
+ };
};
clocks {
--
2.1.4
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[PATCH v2 5/7] drm/vc4: Allow vblank to be disabled
From: Derek Foreman der...@osg.samsung.com Signed-off-by: Derek Foreman der...@osg.samsung.com Signed-off-by: Eric Anholt e...@anholt.net --- drivers/gpu/drm/vc4/vc4_kms.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c index a34439f..f881cd4 100644 --- a/drivers/gpu/drm/vc4/vc4_kms.c +++ b/drivers/gpu/drm/vc4/vc4_kms.c @@ -77,6 +77,8 @@ int vc4_kms_load(struct drm_device *dev) dev-mode_config.funcs = vc4_mode_funcs; dev-mode_config.preferred_depth = 24; + dev-vblank_disable_allowed = true; + ret = vc4_init_modeset_objects(dev); if (ret) goto fail; -- 2.1.4 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/7] drm/vc4: Add devicetree bindings for VC4.
VC4 is the GPU (display and 3D) subsystem present on the 2835 and some
other Broadcom SoCs.
This binding follows the model of msm, imx, sti, and others, where
there is a subsystem node for the whole GPU, with nodes for the
individual HW components within it.
Signed-off-by: Eric Anholt e...@anholt.net
---
v2: Extend the commit message, fix several nits from Stephen Warren.
.../devicetree/bindings/gpu/brcm,bcm-vc4.txt | 79 ++
1 file changed, 79 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpu/brcm,bcm-vc4.txt
diff --git a/Documentation/devicetree/bindings/gpu/brcm,bcm-vc4.txt
b/Documentation/devicetree/bindings/gpu/brcm,bcm-vc4.txt
new file mode 100644
index 000..1b9fedc
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/brcm,bcm-vc4.txt
@@ -0,0 +1,79 @@
+Broadcom VC4 GPU
+
+The VC4 device present on the Raspberry Pi includes a display system
+with HDMI output and the HVS scaler for compositing display planes.
+
+Required properties for VC4:
+- compatible: Should be brcm,vc4
+- crtcs: List of phandles of pixelvalve scanout engines
+- hvss:List of phandles of HVS video scalers
+- encoders:List of phandles of output encoders (HDMI, SDTV)
+
+Required properties for Pixel Valve:
+- compatible: Should be brcm,vc4-pixelvalve
+- reg: Physical base address and length of the PV's registers
+- interrupts: The interrupt number
+ See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
+
+Required properties for HVS:
+- compatible: Should be brcm,vc4-hvs
+- reg: Physical base address and length of the HVS's registers
+- interrupts: The interrupt number
+ See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
+
+Required properties for HDMI
+- compatible: Should be brcm,vc4-hdmi
+- reg: Physical base address and length of the two register ranges
+ (HDMI and HD, in that order)
+- interrupts: The interrupt numbers
+ See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
+- ddc: phandle of the I2C controller used for DDC EDID probing
+- crtc:phandle to the pixelvalve CRTC the HDMI encoder is
attached to
+
+Optional properties for HDMI:
+- hpd-gpio:The GPIO pin for HDMI hotplug detect (if it doesn't appear
+ as an interrupt/status bit in the HDMI controller
+ itself). See bindings/pinctrl/brcm,bcm2835-gpio.txt
+
+Example:
+pv0: brcm,vc4-pixelvalve@7e206000 {
+ compatible = brcm,vc4-pixelvalve;
+ reg = 0x7e206000 0x100;
+ interrupts = 2 13; /* pwa2 */
+};
+
+pv1: brcm,vc4-pixelvalve@7e207000 {
+ compatible = brcm,vc4-pixelvalve;
+ reg = 0x7e207000 0x100;
+ interrupts = 2 14; /* pwa1 */
+};
+
+pv2: brcm,vc4-pixelvalve@7e807000 {
+ compatible = brcm,vc4-pixelvalve;
+ reg = 0x7e807000 0x100;
+ interrupts = 2 10; /* pixelvalve */
+};
+
+hvs: brcm,hvs@7e40 {
+ compatible = brcm,vc4-hvs;
+ reg = 0x7e40 0x6000;
+ interrupts = 2 1;
+};
+
+hdmi: brcm,vc4-hdmi@7e902000 {
+ compatible = brcm,vc4-hdmi;
+ reg = 0x7e902000 0x600,
+ 0x7e808000 0x100;
+ interrupts = 2 8, 2 9;
+ ddc = i2c2;
+ hpd-gpio = gpio 46 GPIO_ACTIVE_HIGH;
+ crtc = pv2;
+};
+
+vc4: vc4@0x7e4c {
+ compatible = brcm,vc4;
+
+ crtcs = pv0, pv1, pv2;
+ encoders = hdmi;
+ hvss = hvs;
+};
--
2.1.4
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[PATCH v2 6/7] ARM: bcm2835: Add the DDC I2C controller to the device tree.
We need to use it for getting video modes over HDMI.
Signed-off-by: Eric Anholt e...@anholt.net
---
v2: Mark it as disabled by default, and enable it in bcm2835-rpi.
arch/arm/boot/dts/bcm2835-rpi.dtsi | 4
arch/arm/boot/dts/bcm2835.dtsi | 10 ++
2 files changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi
b/arch/arm/boot/dts/bcm2835-rpi.dtsi
index 46780bb..29cc7ba 100644
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -45,6 +45,10 @@
clock-frequency = 10;
};
+i2c2 {
+ status = okay;
+};
+
sdhci {
status = okay;
bus-width = 4;
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index 301c73f..20574cc 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -149,6 +149,16 @@
status = disabled;
};
+ i2c2: i2c@7e805000 {
+ compatible = brcm,bcm2835-i2c;
+ reg = 0x7e805000 0x1000;
+ interrupts = 2 21;
+ clocks = clk_i2c;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ };
+
usb@7e98 {
compatible = brcm,bcm2835-usb;
reg = 0x7e98 0x1;
--
2.1.4
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[PATCH v2 3/7] drm/vc4: Add KMS support for Raspberry Pi.
This is the start of a full VC4 driver. Right now this just supports
configuring the display using a pre-existing video mode (because
changing the pixel clock isn't available yet, and doesn't work when it
is). However, this is enough for fbcon and bringing up X using
xf86-video-modesetting.
Signed-off-by: Eric Anholt e...@anholt.net
---
v2: Drop FB_HELPER select thanks to Archit's patches. Do manual init
ordering instead of using the .load hook. Structure registration
more like tegra's, but still using the typical component code.
Drop no-op hooks for atomic_begin and mode_fixup() now that
they're optional. Drop sentinel in Makefile. Fix minor style
nits I noticed on another reread.
drivers/gpu/drm/Kconfig | 2 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/vc4/Kconfig | 13 +
drivers/gpu/drm/vc4/Makefile | 17 +
drivers/gpu/drm/vc4/vc4_bo.c | 52
drivers/gpu/drm/vc4/vc4_crtc.c| 565 ++
drivers/gpu/drm/vc4/vc4_debugfs.c | 38 +++
drivers/gpu/drm/vc4/vc4_drv.c | 271
drivers/gpu/drm/vc4/vc4_drv.h | 120
drivers/gpu/drm/vc4/vc4_hdmi.c| 633 ++
drivers/gpu/drm/vc4/vc4_hvs.c | 161 ++
drivers/gpu/drm/vc4/vc4_kms.c | 84 +
drivers/gpu/drm/vc4/vc4_plane.c | 320 +++
drivers/gpu/drm/vc4/vc4_regs.h| 562 +
14 files changed, 2839 insertions(+)
create mode 100644 drivers/gpu/drm/vc4/Kconfig
create mode 100644 drivers/gpu/drm/vc4/Makefile
create mode 100644 drivers/gpu/drm/vc4/vc4_bo.c
create mode 100644 drivers/gpu/drm/vc4/vc4_crtc.c
create mode 100644 drivers/gpu/drm/vc4/vc4_debugfs.c
create mode 100644 drivers/gpu/drm/vc4/vc4_drv.c
create mode 100644 drivers/gpu/drm/vc4/vc4_drv.h
create mode 100644 drivers/gpu/drm/vc4/vc4_hdmi.c
create mode 100644 drivers/gpu/drm/vc4/vc4_hvs.c
create mode 100644 drivers/gpu/drm/vc4/vc4_kms.c
create mode 100644 drivers/gpu/drm/vc4/vc4_plane.c
create mode 100644 drivers/gpu/drm/vc4/vc4_regs.h
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 06ae500..19bb0db 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -260,3 +260,5 @@ source drivers/gpu/drm/sti/Kconfig
source drivers/gpu/drm/amd/amdkfd/Kconfig
source drivers/gpu/drm/imx/Kconfig
+
+source drivers/gpu/drm/vc4/Kconfig
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 8858510..283ed8e 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_DRM_MGA) += mga/
obj-$(CONFIG_DRM_I810) += i810/
obj-$(CONFIG_DRM_I915) += i915/
obj-$(CONFIG_DRM_MGAG200) += mgag200/
+obj-$(CONFIG_DRM_VC4) += vc4/
obj-$(CONFIG_DRM_CIRRUS_QEMU) += cirrus/
obj-$(CONFIG_DRM_SIS) += sis/
obj-$(CONFIG_DRM_SAVAGE)+= savage/
diff --git a/drivers/gpu/drm/vc4/Kconfig b/drivers/gpu/drm/vc4/Kconfig
new file mode 100644
index 000..e810ef7
--- /dev/null
+++ b/drivers/gpu/drm/vc4/Kconfig
@@ -0,0 +1,13 @@
+config DRM_VC4
+ tristate Broadcom VC4 Graphics
+ depends on ARCH_BCM2835
+ depends on DRM
+ select DRM_KMS_HELPER
+ select DRM_KMS_CMA_HELPER
+ help
+ Choose this option if you have a system that has a Broadcom
+ VC4 GPU, such as the Raspberry Pi or other BCM2708/BCM2835.
+
+ This driver requires that avoid_warnings=2 be present in
+ the config.txt for the firmware, to keep it from smashing
+ our display setup.
diff --git a/drivers/gpu/drm/vc4/Makefile b/drivers/gpu/drm/vc4/Makefile
new file mode 100644
index 000..32b4f9c
--- /dev/null
+++ b/drivers/gpu/drm/vc4/Makefile
@@ -0,0 +1,17 @@
+ccflags-y := -Iinclude/drm
+
+# Please keep these build lists sorted!
+
+# core driver code
+vc4-y := \
+ vc4_bo.o \
+ vc4_crtc.o \
+ vc4_drv.o \
+ vc4_kms.o \
+ vc4_hdmi.o \
+ vc4_hvs.o \
+ vc4_plane.o
+
+vc4-$(CONFIG_DEBUG_FS) += vc4_debugfs.o
+
+obj-$(CONFIG_DRM_VC4) += vc4.o
diff --git a/drivers/gpu/drm/vc4/vc4_bo.c b/drivers/gpu/drm/vc4/vc4_bo.c
new file mode 100644
index 000..ab9f510
--- /dev/null
+++ b/drivers/gpu/drm/vc4/vc4_bo.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright © 2015 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* DOC: VC4 GEM BO management support.
+ *
+ * The VC4 GPU architecture (both scanout and rendering) has direct
+ * access to system memory with no MMU in between. To support it, we
+ * use the GEM CMA helper functions to allocate contiguous ranges of
+ * physical memory for our BOs.
+ */
+
+#include vc4_drv.h
+
+struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size)
+{
+ struct drm_gem_cma_object *cma_obj;
+
+ cma_obj = drm_gem_cma_create(dev, size);
+ if
[PATCH] ARM: qcom: Disable i2c device on gsbi4 for ipq806x
Disable the i2c device on gsbi4 and mark gsbi4_h and gsbi4_qup clks as
unused. If they are enabled, clock framework will turn them off at end
of probe. On ipq806x by design gsbi4_qup, gsbi4_h clks and i2c on gsbi4
are meant for RPM usage. So turning them off in kernel is incorrect.
Signed-off-by: Mathieu Olivari math...@codeaurora.org
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 9 -
drivers/clk/qcom/gcc-ipq806x.c | 6 +++---
2 files changed, 3 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
index b08907a..36e2b04 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -46,15 +46,6 @@
serial@1634 {
status = ok;
};
-
- i2c4: i2c@1638 {
- status = ok;
-
- clock-frequency = 20;
-
- pinctrl-0 = i2c4_pins;
- pinctrl-names = default;
- };
};
gsbi5: gsbi@1a20 {
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 5639699..eb4065e 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -809,7 +809,7 @@ static struct clk_rcg gsbi6_qup_src = {
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.ops = clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
},
},
};
@@ -874,7 +874,7 @@ static struct clk_branch gsbi7_qup_clk = {
.parent_names = (const char *[]){ gsbi7_qup_src },
.num_parents = 1,
.ops = clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
},
},
};
@@ -922,7 +922,7 @@ static struct clk_branch gsbi4_h_clk = {
.hw.init = (struct clk_init_data){
.name = gsbi4_h_clk,
.ops = clk_branch_ops,
- .flags = CLK_IS_ROOT,
+ .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
},
},
};
--
2.1.4
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Re: [PATCH V7 1/2] mtd: spi-nor: Bindings for Cadence Quad SPI Flash Controller driver.
Hi, On 08/18/2015 12:03 PM, Graham Moore wrote: Hi all, On 08/18/2015 12:48 AM, Vikas MANOCHA wrote: [...] +Required properties: +- compatible : Should be cdns,qspi-nor. +- reg : Contains two entries, each of which is a tuple consisting of a +physical address and length. The first entry is the address and +length of the controller register set. The second entry is the +address and length of the QSPI Controller data area. Controller data area, i think it means mapped NOR Flash address ? Probably ; Graham ? If yes, it would be more clear with Physical base address size of NOR Flash. This is the Direct mode thing, correct ? We don't support this, so I think we should drop this bit altogether and keep only one single address in this field. No it's not. It's the location of the SRAM fifo. Also direct mode location I think, if that were ever used. Hmm...It is the base address of NOR flash. SRAM is not memory mapped. The size is determined by a configuration parameter during system design. On Altera Cyclone5 the size is really big compared to SRAM fifo. I don't know why, maybe some hw engineer thought it would be better to have a large size in case direct mode was used. my comment is about second parameter of property reg which is NOR flash address, so above explanation does not make sense for it. Also in direct mode, sram does not come into play. Rgds, Vikas BR, Graham . -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V7 2/2] mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller.
Hi, On 08/18/2015 12:17 PM, Graham Moore wrote: Hi Vikas, On 08/17/2015 09:34 PM, vikas wrote: Hi Marek, [...] + +/* Operation timeout value */ +#define CQSPI_TIMEOUT_MS 500 +#define CQSPI_READ_TIMEOUT_MS 10 please add some comment about the timeouts value selection. I wish I could comment, but I don't know the origin of these values. The 500 ms value is probably just a very long time. In my opinion we should have some logical value based on some worst timing like read/write sector. I let you decide on this point. [...] + + cqspi-irq_mask = CQSPI_IRQ_MASK_RD; + writel(cqspi-irq_mask, reg_base + CQSPI_REG_IRQMASK); here interrupt mask is being configured for every read, better would be to move it in init. [...] + + cqspi-irq_mask = CQSPI_IRQ_MASK_WR; + writel(cqspi-irq_mask, reg_base + CQSPI_REG_IRQMASK); same like read, it should be moved to init. It uses different masks for read and write Yeah i saw it but why not to OR these values configure for once in init. After that in ISR, check for the interrupt source take action accordingly. I think other drivers also use it this way. Rgds, Vikas [...] BR, Graham . -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 2/2] spi: dw: Allow interface drivers to limit data I/O to word sizes
The commit dd11444327ce (spi: dw-spi: Convert 16bit accesses to 32bit
accesses) changed all 16bit accesses in the DW_apb_ssi driver to 32bit.
This, unfortunately, breaks data register access on picoXcell, where the
DW IP needs data register accesses to be word accesses (all other
accesses appear to be OK).
This change introduces a new master variable to allow interface drivers
to specify that 16bit data transfer I/O is required. This change also
introduces the ability to set this variable via device tree bindings in
the MMIO interface driver. Both the core and the MMIO interface driver
default to the current 32bit behaviour.
Before this change, on a picoXcell pc3x3:
spi_master spi32766: interrupt_transfer: fifo overrun/underrun
m25p80 spi32766.0: error -5 reading 9f
m25p80: probe of spi32766.0 failed with error -5
After this change:
m25p80 spi32766.0: m25p40 (512 Kbytes)
Fixes: dd11444327ce (spi: dw-spi: Convert 16bit accesses to 32bit accesses)
Signed-off-by: Michael van der Westhuizen mich...@smart-africa.com
---
Changes in v3:
- Rename the DT property as requested by Rob Herring.
Changes in v2:
- Incorporate review feedback from Andy Shevchenko
- Rework the DT bindings to accept an I/O register width as a
number of bytes rather than using a boolean spefifying the
width preference to be 16 bits.
- Add data register access wrapper functions and use them when
reading and writing the data register.
drivers/spi/spi-dw-mmio.c | 3 +++
drivers/spi/spi-dw.c | 4 ++--
drivers/spi/spi-dw.h | 35 +++
3 files changed, 40 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index eb03e12..7edede6 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -74,6 +74,9 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
dws-max_freq = clk_get_rate(dwsmmio-clk);
+ of_property_read_u32(pdev-dev.of_node, reg-io-width,
+dws-reg_io_width);
+
num_cs = 4;
if (pdev-dev.of_node)
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index 8d67d03..4fbfcdc 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -194,7 +194,7 @@ static void dw_writer(struct dw_spi *dws)
else
txw = *(u16 *)(dws-tx);
}
- dw_writel(dws, DW_SPI_DR, txw);
+ dw_write_io_reg(dws, DW_SPI_DR, txw);
dws-tx += dws-n_bytes;
}
}
@@ -205,7 +205,7 @@ static void dw_reader(struct dw_spi *dws)
u16 rxw;
while (max--) {
- rxw = dw_readl(dws, DW_SPI_DR);
+ rxw = dw_read_io_reg(dws, DW_SPI_DR);
/* Care rx only if the transfer's original rx is not null */
if (dws-rx_end - dws-len) {
if (dws-n_bytes == 1)
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 6c91391..b75ed32 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -109,6 +109,7 @@ struct dw_spi {
u32 fifo_len; /* depth of the FIFO buffer */
u32 max_freq; /* max bus freq supported */
+ u32 reg_io_width; /* DR I/O width in bytes */
u16 bus_num;
u16 num_cs; /* supported slave numbers */
@@ -145,11 +146,45 @@ static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
return __raw_readl(dws-regs + offset);
}
+static inline u16 dw_readw(struct dw_spi *dws, u32 offset)
+{
+ return __raw_readw(dws-regs + offset);
+}
+
static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
{
__raw_writel(val, dws-regs + offset);
}
+static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val)
+{
+ __raw_writew(val, dws-regs + offset);
+}
+
+static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
+{
+ switch (dws-reg_io_width) {
+ case 2:
+ return dw_readw(dws, offset);
+ case 4:
+ default:
+ return dw_readl(dws, offset);
+ }
+}
+
+static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
+{
+ switch (dws-reg_io_width) {
+ case 2:
+ dw_writew(dws, offset, val);
+ break;
+ case 4:
+ default:
+ dw_writel(dws, offset, val);
+ break;
+ }
+}
+
static inline void spi_enable_chip(struct dw_spi *dws, int enable)
{
dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
--
2.1.4
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[PATCH v3 0/2] spi: dw: Reintroduce optional 16 bit data register I/O
The commit dd11444327ce (spi: dw-spi: Convert 16bit accesses to 32bit accesses) globally changed all register access in the dw_apb_ssi driver to 32 bit access, which breaks data register (FIFO) access on picoXcell platforms. This series introduces a variable to the core spi-dw driver to indicate to the core that either 16 or 32 bit data register access is appropriate, with the code defaulting to the current 32 bit behaviour. The dw-spi-mmio driver is updated to support optionally setting this variable from the device tree and the binding documentation is updated. Prior to applying this change the following error presents on a picoXcell pc3x3 platform: spi_master spi32766: interrupt_transfer: fifo overrun/underrun m25p80 spi32766.0: error -5 reading 9f m25p80: probe of spi32766.0 failed with error -5 With this series applied: m25p80 spi32766.0: m25p40 (512 Kbytes) Changes in v3: - Rename the DT property as requested by Rob Herring. Changes in v2: - Incorporate review feedback from Andy Shevchenko, reworking the bindings to reflect common practice and adjusting the driver to suit. - Add a wrapper inline function for accessing the data register using the configured with. Michael van der Westhuizen (2): dt: snps,dw-apb-ssi: Document new I/O data register width property spi: dw: Allow interface drivers to limit data I/O to word sizes drivers/spi/spi-dw-mmio.c | 3 +++ drivers/spi/spi-dw.c | 4 ++-- drivers/spi/spi-dw.h | 35 +++ 3 files changed, 40 insertions(+), 2 deletions(-) -- 2.1.4 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 1/2] dt: snps,dw-apb-ssi: Document new I/O data register width property
This change documents a new property for the snps,dw-apb-ssi device, allowing an implementer to specify either four byte or two bytes access to the SPI controller data register. This supports a change that unbreaks this driver on picoXcell platforms. Signed-off-by: Michael van der Westhuizen mich...@smart-africa.com --- Changes in v3: - Rename the DT property as requested by Rob Herring. Changes in v2: - Incorporate review feedback from Andy Shevchenko, reworking the bindings to reflect common practice. Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt index bd99193..204b311 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt @@ -10,6 +10,8 @@ Required properties: Optional properties: - cs-gpios : Specifies the gpio pis to be used for chipselects. - num-cs : The number of chipselects. If omitted, this will default to 4. +- reg-io-width : The I/O register width (in bytes) implemented by this + device. Supported values are 2 or 4 (the default). Child nodes as per the generic SPI binding. -- 2.1.4 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] ARM: qcom: add uart labels to IPQ806x dts
We want to use references to UART devices from the board specific dts
files, so we'll label them according to their gsbi number.
Signed-off-by: Mathieu Olivari math...@codeaurora.org
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi
b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 9834c94..2f270d7 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -159,8 +159,9 @@
syscon-tcsr = tcsr;
- serial@1249 {
- compatible = qcom,msm-uartdm-v1.3,
qcom,msm-uartdm;
+ uart2: serial@1249 {
+ compatible = qcom,msm-uartdm-v1.3,
+qcom,msm-uartdm;
reg = 0x1249 0x1000,
0x1248 0x1000;
interrupts = 0 195 0x0;
@@ -197,8 +198,9 @@
syscon-tcsr = tcsr;
- serial@1634 {
- compatible = qcom,msm-uartdm-v1.3,
qcom,msm-uartdm;
+ uart4: serial@1634 {
+ compatible = qcom,msm-uartdm-v1.3,
+qcom,msm-uartdm;
reg = 0x1634 0x1000,
0x1630 0x1000;
interrupts = 0 152 0x0;
@@ -234,8 +236,9 @@
syscon-tcsr = tcsr;
- serial@1a24 {
- compatible = qcom,msm-uartdm-v1.3,
qcom,msm-uartdm;
+ uart5: serial@1a24 {
+ compatible = qcom,msm-uartdm-v1.3,
+qcom,msm-uartdm;
reg = 0x1a24 0x1000,
0x1a20 0x1000;
interrupts = 0 154 0x0;
--
2.1.4
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[PATCH 2/2] ARM: qcom: enable uart output by default on AP148
This change adds a new chosen node to boot using UART console on AP148
Signed-off-by: Mathieu Olivari math...@codeaurora.org
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
index 55b2910..b08907a 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -14,6 +14,14 @@
};
};
+ alias {
+ serial0 = uart4;
+ };
+
+ chosen {
+ linux,stdout-path = serial0:115200n8;
+ };
+
soc {
pinmux@80 {
i2c4_pins: i2c4_pinmux {
--
2.1.4
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[PATCH] regulator: Introduce property to flag set-load support
Introduce regulator-allow-set-load property to make it possible to
flag in the board configuration that a regulator is allowed to have the
load requirements changed.
Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com
---
Documentation/devicetree/bindings/regulator/regulator.txt | 1 +
drivers/regulator/of_regulator.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/regulator/regulator.txt
b/Documentation/devicetree/bindings/regulator/regulator.txt
index 24bd422cecd5..1d112fc456aa 100644
--- a/Documentation/devicetree/bindings/regulator/regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/regulator.txt
@@ -11,6 +11,7 @@ Optional properties:
- regulator-always-on: boolean, regulator should never be disabled
- regulator-boot-on: bootloader/firmware enabled regulator
- regulator-allow-bypass: allow the regulator to go into bypass mode
+- regulator-allow-set-load: allow the regulator performance level to be
configured
- name-supply: phandle to the parent supply/regulator node
- regulator-ramp-delay: ramp delay for regulator(in uV/uS)
For hardware which supports disabling ramp rate, it should be explicitly
diff --git a/drivers/regulator/of_regulator.c b/drivers/regulator/of_regulator.c
index 250700c853bf..499e437c7e91 100644
--- a/drivers/regulator/of_regulator.c
+++ b/drivers/regulator/of_regulator.c
@@ -76,6 +76,9 @@ static void of_get_regulation_constraints(struct device_node
*np,
if (of_property_read_bool(np, regulator-allow-bypass))
constraints-valid_ops_mask |= REGULATOR_CHANGE_BYPASS;
+ if (of_property_read_bool(np, regulator-allow-set-load))
+ constraints-valid_ops_mask |= REGULATOR_CHANGE_DRMS;
+
ret = of_property_read_u32(np, regulator-ramp-delay, pval);
if (!ret) {
if (pval)
--
1.8.2.2
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[PATCH v4 0/3] qcom: Add SMEM MTD parser
QCOM platforms such as IPQ806x are using SMEM to store their flash layout. This patch set adds the DT nodes required to instanciate SMEM on IPQ806x and add an MTD parser using it. This change is based on the SMEM driver posted here: *https://lkml.org/lkml/2015/7/27/1125 v2: *Release the SPI device reference after looking it up (put_device()) *Represent SMEM data as __le32 rather than u32 *Move new DT nodes in their proper respective location *Address readability concerns in MTD parser v3: *Address Bjorn's comments v4: *Fix licensing case *Fix smem tag in dts file Mathieu Olivari (3): ARM: qcom: add SFPB nodes to IPQ806x dts ARM: qcom: add SMEM device node to IPQ806x dts mtd: add SMEM parser for QCOM platforms arch/arm/boot/dts/qcom-ipq8064.dtsi | 23 +++- drivers/mtd/Kconfig | 7 ++ drivers/mtd/Makefile| 1 + drivers/mtd/qcom_smem_part.c| 224 4 files changed, 254 insertions(+), 1 deletion(-) create mode 100644 drivers/mtd/qcom_smem_part.c -- 2.1.4 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/2] ARM: qcom: enable console output on IPQ806x
This change set adds uart nodes in ipq806x dtsi and add the chosen node in AP148 dts file to use it as a console. Mathieu Olivari (2): ARM: qcom: add uart labels to IPQ806x dts ARCH: qcom: enable uart output by default on AP148 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 8 arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +-- 2 files changed, 17 insertions(+), 6 deletions(-) -- 2.1.4 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/3] spi: mediatek: fix spi incorrect endian usage
TX_ENDIAN/RX_ENDIAN bits define whether to reverse the endian
order of the data DMA from/to memory. The endian order should
keep the same with cpu endian.
Signed-off-by: Leilk Liu leilk@mediatek.com
---
drivers/spi/spi-mt65xx.c | 43
include/linux/platform_data/spi-mt65xx.h | 2 --
2 files changed, 16 insertions(+), 29 deletions(-)
diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
index 1c2b215..eaadc7e 100644
--- a/drivers/spi/spi-mt65xx.c
+++ b/drivers/spi/spi-mt65xx.c
@@ -107,8 +107,6 @@ static const struct mtk_spi_compatible mt8173_compat = {
static const struct mtk_chip_config mtk_default_chip_info = {
.rx_mlsb = 1,
.tx_mlsb = 1,
- .tx_endian = 0,
- .rx_endian = 0,
};
static const struct of_device_id mtk_spi_of_match[] = {
@@ -151,14 +149,13 @@ static void mtk_spi_config(struct mtk_spi *mdata,
reg_val = ~SPI_CMD_RXMSBF;
/* set the tx/rx endian */
- if (chip_config-tx_endian)
- reg_val |= SPI_CMD_TX_ENDIAN;
- else
- reg_val = ~SPI_CMD_TX_ENDIAN;
- if (chip_config-rx_endian)
- reg_val |= SPI_CMD_RX_ENDIAN;
- else
- reg_val = ~SPI_CMD_RX_ENDIAN;
+#ifdef __LITTLE_ENDIAN
+ reg_val = ~SPI_CMD_TX_ENDIAN;
+ reg_val = ~SPI_CMD_RX_ENDIAN;
+#else
+ reg_val |= SPI_CMD_TX_ENDIAN;
+ reg_val |= SPI_CMD_RX_ENDIAN;
+#endif
/* set finish and pause interrupt always enable */
reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_EN;
@@ -348,7 +345,7 @@ static int mtk_spi_fifo_transfer(struct spi_master *master,
struct spi_device *spi,
struct spi_transfer *xfer)
{
- int cnt, i;
+ int cnt;
struct mtk_spi *mdata = spi_master_get_devdata(master);
mdata-cur_transfer = xfer;
@@ -360,10 +357,7 @@ static int mtk_spi_fifo_transfer(struct spi_master *master,
cnt = xfer-len / 4 + 1;
else
cnt = xfer-len / 4;
-
- for (i = 0; i cnt; i++)
- writel(*((u32 *)xfer-tx_buf + i),
- mdata-base + SPI_TX_DATA_REG);
+ iowrite32_rep(mdata-base + SPI_TX_DATA_REG, xfer-tx_buf, cnt);
mtk_spi_enable_transfer(master);
@@ -433,7 +427,7 @@ static bool mtk_spi_can_dma(struct spi_master *master,
static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
{
- u32 cmd, reg_val, i;
+ u32 cmd, reg_val, cnt;
struct spi_master *master = dev_id;
struct mtk_spi *mdata = spi_master_get_devdata(master);
struct spi_transfer *trans = mdata-cur_transfer;
@@ -445,18 +439,13 @@ static irqreturn_t mtk_spi_interrupt(int irq, void
*dev_id)
mdata-state = MTK_SPI_IDLE;
if (!master-can_dma(master, master-cur_msg-spi, trans)) {
- /* xfer len is not N*4 bytes every time in a transfer,
-* but SPI_RX_DATA_REG must reads 4 bytes once,
-* so rx buffer byte by byte.
-*/
if (trans-rx_buf) {
- for (i = 0; i mdata-xfer_len; i++) {
- if (i % 4 == 0)
- reg_val =
- readl(mdata-base + SPI_RX_DATA_REG);
- *((u8 *)(trans-rx_buf + i)) =
- (reg_val ((i % 4) * 8)) 0xff;
- }
+ if (mdata-xfer_len % 4)
+ cnt = mdata-xfer_len / 4 + 1;
+ else
+ cnt = mdata-xfer_len / 4;
+ ioread32_rep(mdata-base + SPI_RX_DATA_REG,
+trans-rx_buf, cnt);
}
spi_finalize_current_transfer(master);
return IRQ_HANDLED;
diff --git a/include/linux/platform_data/spi-mt65xx.h
b/include/linux/platform_data/spi-mt65xx.h
index 7512255..54b0448 100644
--- a/include/linux/platform_data/spi-mt65xx.h
+++ b/include/linux/platform_data/spi-mt65xx.h
@@ -16,7 +16,5 @@
struct mtk_chip_config {
u32 tx_mlsb;
u32 rx_mlsb;
- u32 tx_endian;
- u32 rx_endian;
};
#endif
--
1.8.1.1.dirty
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[PATCH 2/3] spi: mediatek: remove redundant clock in prepare_hardware/unprepare_hardware
clock in prepare_hardware/unprepare_hardware is redundant
with pm_runtime, so remove them.
Signed-off-by: Leilk Liu leilk@mediatek.com
---
drivers/spi/spi-mt65xx.c | 17 -
1 file changed, 17 deletions(-)
diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
index 814bca4..1c2b215 100644
--- a/drivers/spi/spi-mt65xx.c
+++ b/drivers/spi/spi-mt65xx.c
@@ -181,13 +181,6 @@ static int mtk_spi_prepare_hardware(struct spi_master
*master)
struct spi_transfer *trans;
struct mtk_spi *mdata = spi_master_get_devdata(master);
struct spi_message *msg = master-cur_msg;
- int ret;
-
- ret = clk_prepare_enable(mdata-spi_clk);
- if (ret 0) {
- dev_err(master-dev, failed to enable clock (%d)\n, ret);
- return ret;
- }
trans = list_first_entry(msg-transfers, struct spi_transfer,
transfer_list);
@@ -196,15 +189,6 @@ static int mtk_spi_prepare_hardware(struct spi_master
*master)
mtk_spi_reset(mdata);
}
- return ret;
-}
-
-static int mtk_spi_unprepare_hardware(struct spi_master *master)
-{
- struct mtk_spi *mdata = spi_master_get_devdata(master);
-
- clk_disable_unprepare(mdata-spi_clk);
-
return 0;
}
@@ -537,7 +521,6 @@ static int mtk_spi_probe(struct platform_device *pdev)
master-set_cs = mtk_spi_set_cs;
master-prepare_transfer_hardware = mtk_spi_prepare_hardware;
- master-unprepare_transfer_hardware = mtk_spi_unprepare_hardware;
master-prepare_message = mtk_spi_prepare_message;
master-transfer_one = mtk_spi_transfer_one;
master-can_dma = mtk_spi_can_dma;
--
1.8.1.1.dirty
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[PATCH 0/3] Fixup mediatek spi driver
Change in this patch: 1. revise coding styles. 2. delete redundant clock in prepare/unprepare_hardware. 3. fix incorrect endian usage on big-endian system. Leilk Liu (3): spi: mediatek: revise coding style spi: mediatek: remove redundant clock in prepare_hardware/unprepare_hardware spi: mediatek: fix spi incorrect endian usage drivers/spi/spi-mt65xx.c | 169 +-- include/linux/platform_data/spi-mt65xx.h | 2 - 2 files changed, 73 insertions(+), 98 deletions(-) -- 1.8.1.1.dirty -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 8/8] ARM: dts: sun8i: sinlinx-sina33: Enable Reduced Serial Bus controller
The Reduced Serial Bus controller is used to talk to the onboard PMIC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
index 1d5390d4e03a..13ce68f06dd6 100644
--- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
+++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
@@ -130,6 +130,10 @@
};
};
+r_rsb {
+ status = okay;
+};
+
uart0 {
pinctrl-names = default;
pinctrl-0 = uart0_pins_b;
--
2.5.0
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[PATCH v3 3/8] rsb: Linux driver framework for Reduced Serial Bus (RSB)
Reduced Serial Bus (RSB) is an Allwinner proprietery interface
used to communicate with PMICs and other peripheral ICs.
RSB is a two-wire push-pull serial bus that supports 1 master
device and up to 15 active slave devices.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/Kconfig| 2 +
drivers/Makefile | 1 +
drivers/rsb/Kconfig| 11 ++
drivers/rsb/Makefile | 4 +
drivers/rsb/rsb-core.c | 511 +
include/linux/rsb.h| 144 ++
6 files changed, 673 insertions(+)
create mode 100644 drivers/rsb/Kconfig
create mode 100644 drivers/rsb/Makefile
create mode 100644 drivers/rsb/rsb-core.c
create mode 100644 include/linux/rsb.h
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 6e973b8e3a3b..4ada2d3eb832 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -54,6 +54,8 @@ source drivers/spi/Kconfig
source drivers/spmi/Kconfig
+source drivers/rsb/Kconfig
+
source drivers/hsi/Kconfig
source drivers/pps/Kconfig
diff --git a/drivers/Makefile b/drivers/Makefile
index e4b260ecec15..75e0fc8fe28c 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -75,6 +75,7 @@ obj-$(CONFIG_TARGET_CORE) += target/
obj-$(CONFIG_MTD) += mtd/
obj-$(CONFIG_SPI) += spi/
obj-$(CONFIG_SPMI) += spmi/
+obj-$(CONFIG_RSB) += rsb/
obj-y += hsi/
obj-y += net/
obj-$(CONFIG_ATM) += atm/
diff --git a/drivers/rsb/Kconfig b/drivers/rsb/Kconfig
new file mode 100644
index ..6642e1db6d98
--- /dev/null
+++ b/drivers/rsb/Kconfig
@@ -0,0 +1,11 @@
+#
+# RSB driver configuration
+#
+menuconfig RSB
+ tristate RSB support
+ help
+ RSB (Reduced Serial Bus) is a two-wire serial interface between
+ baseband and application processors and Power Management
+ Integrated Circuits (PMIC) or other peripherals.
+
+ These are commonly seen on newer Allwinner SoCs and X-Powers ICs.
diff --git a/drivers/rsb/Makefile b/drivers/rsb/Makefile
new file mode 100644
index ..6fe56526fbf3
--- /dev/null
+++ b/drivers/rsb/Makefile
@@ -0,0 +1,4 @@
+#
+# Makefile for kernel RSB framework.
+#
+obj-$(CONFIG_RSB) += rsb-core.o
diff --git a/drivers/rsb/rsb-core.c b/drivers/rsb/rsb-core.c
new file mode 100644
index ..6682d827aebb
--- /dev/null
+++ b/drivers/rsb/rsb-core.c
@@ -0,0 +1,511 @@
+/*
+ * Copyright (c) 2015, Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai w...@csie.org
+ *
+ * Allwinner Reduced Serial Bus (RSB) driver
+ *
+ * based on spmi/spmi.c
+ *
+ * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk/clk-conf.h
+#include linux/kernel.h
+#include linux/errno.h
+#include linux/idr.h
+#include linux/module.h
+#include linux/of.h
+#include linux/of_device.h
+#include linux/of_irq.h
+#include linux/platform_device.h
+#include linux/rsb.h
+#include linux/slab.h
+
+static DEFINE_IDA(ctrl_ida);
+
+static void rsb_dev_release(struct device *dev)
+{
+ struct rsb_device *rdev = to_rsb_device(dev);
+
+ kfree(rdev);
+}
+
+static const struct device_type rsb_dev_type = {
+ .release= rsb_dev_release,
+};
+
+static void rsb_ctrl_release(struct device *dev)
+{
+ struct rsb_controller *ctrl = to_rsb_controller(dev);
+
+ ida_simple_remove(ctrl_ida, ctrl-nr);
+ kfree(ctrl);
+}
+
+static const struct device_type rsb_ctrl_type = {
+ .release= rsb_ctrl_release,
+};
+
+static int rsb_device_match(struct device *dev, struct device_driver *drv)
+{
+ if (of_driver_match_device(dev, drv))
+ return 1;
+
+ return strcmp(dev_name(dev), drv-name) == 0;
+}
+
+static inline int rsb_init_cmd(struct rsb_controller *ctrl)
+{
+ int ret;
+
+ if (!ctrl || !ctrl-init_cmd || ctrl-dev.type != rsb_ctrl_type)
+ return -EINVAL;
+
+ mutex_lock(ctrl-lock);
+ ret = ctrl-init_cmd(ctrl);
+ mutex_unlock(ctrl-lock);
+
+ return ret;
+}
+
+static inline int rsb_rtsaddr_cmd(struct rsb_controller *ctrl, u16 hwaddr,
+ u8 rtaddr)
+{
+ int ret;
+
+ if (!ctrl || !ctrl-rtsaddr_cmd || ctrl-dev.type != rsb_ctrl_type)
+ return -EINVAL;
+
+ mutex_lock(ctrl-lock);
+ ret = ctrl-rtsaddr_cmd(ctrl, hwaddr, rtaddr);
+ mutex_unlock(ctrl-lock);
+
+ return ret;
+}
+
+static inline int rsb_read_cmd(struct rsb_controller *ctrl, u8 rtaddr,
+
[PATCH v3 5/8] regmap: rsb: Add support for Reduced Serial Bus (RSB) based regmaps
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/base/regmap/Kconfig | 6 +-
drivers/base/regmap/Makefile | 1 +
drivers/base/regmap/regmap-rsb.c | 121 +++
include/linux/regmap.h | 36
4 files changed, 163 insertions(+), 1 deletion(-)
create mode 100644 drivers/base/regmap/regmap-rsb.c
diff --git a/drivers/base/regmap/Kconfig b/drivers/base/regmap/Kconfig
index db9d00c36a3e..afb41994c51e 100644
--- a/drivers/base/regmap/Kconfig
+++ b/drivers/base/regmap/Kconfig
@@ -3,7 +3,7 @@
# subsystems should select the appropriate symbols.
config REGMAP
- default y if (REGMAP_I2C || REGMAP_SPI || REGMAP_SPMI || REGMAP_AC97 ||
REGMAP_MMIO || REGMAP_IRQ)
+ default y if (REGMAP_I2C || REGMAP_SPI || REGMAP_SPMI || REGMAP_RSB ||
REGMAP_AC97 || REGMAP_MMIO || REGMAP_IRQ)
select LZO_COMPRESS
select LZO_DECOMPRESS
select IRQ_DOMAIN if REGMAP_IRQ
@@ -24,6 +24,10 @@ config REGMAP_SPMI
tristate
depends on SPMI
+config REGMAP_RSB
+ tristate
+ depends on RSB
+
config REGMAP_MMIO
tristate
diff --git a/drivers/base/regmap/Makefile b/drivers/base/regmap/Makefile
index 609e4c84f485..dad32b3903d4 100644
--- a/drivers/base/regmap/Makefile
+++ b/drivers/base/regmap/Makefile
@@ -8,5 +8,6 @@ obj-$(CONFIG_REGMAP_AC97) += regmap-ac97.o
obj-$(CONFIG_REGMAP_I2C) += regmap-i2c.o
obj-$(CONFIG_REGMAP_SPI) += regmap-spi.o
obj-$(CONFIG_REGMAP_SPMI) += regmap-spmi.o
+obj-$(CONFIG_REGMAP_RSB) += regmap-rsb.o
obj-$(CONFIG_REGMAP_MMIO) += regmap-mmio.o
obj-$(CONFIG_REGMAP_IRQ) += regmap-irq.o
diff --git a/drivers/base/regmap/regmap-rsb.c b/drivers/base/regmap/regmap-rsb.c
new file mode 100644
index ..e82aa980abe1
--- /dev/null
+++ b/drivers/base/regmap/regmap-rsb.c
@@ -0,0 +1,121 @@
+/*
+ * Register map access API - RSB support
+ *
+ * Copyright 2015 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai w...@csie.org
+ *
+ * Based on regmap-i2c.c
+ *
+ * Copyright 2011 Wolfson Microelectronics plc
+ *
+ * Author: Mark Brown broo...@opensource.wolfsonmicro.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/regmap.h
+#include linux/rsb.h
+#include linux/module.h
+#include linux/slab.h
+
+#include internal.h
+
+struct rsb_context {
+ struct rsb_device *rsb;
+ int size;
+};
+
+static int regmap_rsb_reg_read(void *context, unsigned int reg,
+ unsigned int *val)
+{
+ struct rsb_context *ctx = context;
+ struct rsb_device *rsb = ctx-rsb;
+
+ if (reg 0xff)
+ return -EINVAL;
+
+ return rsb_register_read(rsb, reg, val, ctx-size);
+}
+
+static int regmap_rsb_reg_write(void *context, unsigned int reg,
+ unsigned int val)
+{
+ struct rsb_context *ctx = context;
+ struct rsb_device *rsb = ctx-rsb;
+
+ return rsb_register_write(rsb, reg, val, ctx-size);
+}
+
+static void regmap_rsb_free_context(void *context)
+{
+ struct rsb_context *ctx = context;
+
+ kfree(ctx);
+}
+
+static struct regmap_bus regmap_rsb = {
+ .reg_write = regmap_rsb_reg_write,
+ .reg_read = regmap_rsb_reg_read,
+ .free_context = regmap_rsb_free_context,
+ .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
+ .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
+};
+
+static struct rsb_context *regmap_rsb_init_context(struct rsb_device *rsb,
+ const struct regmap_config *config)
+{
+ struct rsb_context *ctx;
+
+ switch (config-val_bits) {
+ case 8:
+ case 16:
+ case 32:
+ break;
+ default:
+ return ERR_PTR(-EINVAL);
+ }
+
+ ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
+ if (!ctx)
+ return ERR_PTR(-ENOMEM);
+
+ ctx-rsb = rsb;
+ ctx-size = config-val_bits / 8;
+
+ return ctx;
+}
+
+struct regmap *__regmap_init_rsb(struct rsb_device *rsb,
+const struct regmap_config *config,
+struct lock_class_key *lock_key,
+const char *lock_name)
+{
+ struct rsb_context *ctx = regmap_rsb_init_context(rsb, config);
+
+ if (IS_ERR(ctx))
+ return ERR_CAST(ctx);
+
+ return __regmap_init(rsb-dev, regmap_rsb, ctx, config,
+lock_key, lock_name);
+}
+EXPORT_SYMBOL_GPL(__regmap_init_rsb);
+
+struct regmap *__devm_regmap_init_rsb(struct rsb_device *rsb,
+ const struct regmap_config *config,
+ struct lock_class_key *lock_key,
+ const char *lock_name)
+{
+ struct rsb_context *ctx = regmap_rsb_init_context(rsb, config);
+
+
[PATCH v3 4/8] rsb: sunxi: Add driver for Allwinner Reduced Serial Bus controller
Signed-off-by: Chen-Yu Tsai w...@csie.org --- drivers/rsb/Kconfig | 15 ++ drivers/rsb/Makefile| 2 + drivers/rsb/rsb-sunxi.c | 441 3 files changed, 458 insertions(+) create mode 100644 drivers/rsb/rsb-sunxi.c diff --git a/drivers/rsb/Kconfig b/drivers/rsb/Kconfig index 6642e1db6d98..54a28a39e0e2 100644 --- a/drivers/rsb/Kconfig +++ b/drivers/rsb/Kconfig @@ -9,3 +9,18 @@ menuconfig RSB Integrated Circuits (PMIC) or other peripherals. These are commonly seen on newer Allwinner SoCs and X-Powers ICs. + +if RSB + +config RSB_SUNXI + tristate Allwinner RSB Controller + depends on ARCH_SUNXI || COMPILE_TEST + default MACH_SUN8I || MACH_SUN9I + help + If you say yes to this option, support will be included for the + built-in RSB controller on Allwinner sun8i/sun9i family SoCs. + + This is required for communicating with X-Powers PMICs and other + devices that have the RSB interface. + +endif diff --git a/drivers/rsb/Makefile b/drivers/rsb/Makefile index 6fe56526fbf3..31cd615f7e58 100644 --- a/drivers/rsb/Makefile +++ b/drivers/rsb/Makefile @@ -2,3 +2,5 @@ # Makefile for kernel RSB framework. # obj-$(CONFIG_RSB) += rsb-core.o + +obj-$(CONFIG_RSB_SUNXI)+= rsb-sunxi.o diff --git a/drivers/rsb/rsb-sunxi.c b/drivers/rsb/rsb-sunxi.c new file mode 100644 index ..07b24291fe4d --- /dev/null +++ b/drivers/rsb/rsb-sunxi.c @@ -0,0 +1,441 @@ +/* + * RSB (Reduced Serial Bus) driver. + * + * Author: Chen-Yu Tsai w...@csie.org + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed as is without any warranty of any + * kind, whether express or implied. + * + * The RSB controller looks like an SMBus controller which only supports + * byte and word data transfers. But, it differs from standard SMBus + * protocol on several aspects: + * - it uses addresses set at runtime to address slaves. Runtime addresses + * are sent to slaves using their 12bit hardware addresses. Up to 15 + * runtime addresses are available. + * - it adds a parity bit every 8bits of data and address for read and + * write accesses; this replaces the ack bit + * - only one read access is required to read a byte (instead of a write + * followed by a read access in standard SMBus protocol) + * - there's no Ack bit after each read access + * + * This means this bus cannot be used to interface with standard SMBus + * devices. Devices known to support this interface include the AXP223, + * AXP809, and AXP806 PMICs, and the AC100 audio codec, all from X-Powers. + * + * A description of the operation and wire protocol can be found in the + * RSB section of Allwinner's A80 user manual, which can be found at + * + * https://github.com/allwinner-zh/documents/tree/master/A80 + * + * This document is officially released by Allwinner. + * + * This driver is based on i2c-sun6i-p2wi.c, the P2WI bus driver. + * + */ +#include linux/clk.h +#include linux/interrupt.h +#include linux/io.h +#include linux/iopoll.h +#include linux/module.h +#include linux/of.h +#include linux/platform_device.h +#include linux/reset.h +#include linux/rsb.h + +/* RSB registers */ +#define RSB_CTRL 0x0 /* Global control */ +#define RSB_CCR0x4 /* Clock control */ +#define RSB_INTE 0x8 /* Interrupt controls */ +#define RSB_INTS 0xc /* Interrupt status */ +#define RSB_ADDR 0x10/* Address to send with read/write command */ +#define RSB_DATA 0x1c/* Data to read/write */ +#define RSB_LCR0x24/* Line control */ +#define RSB_DMCR 0x28/* Device mode (init) control */ +#define RSB_CMD0x2c/* RSB Command */ +#define RSB_DAR0x30/* Device address / runtime address */ + +/* CTRL fields */ +#define RSB_CTRL_START_TRANS BIT(7) +#define RSB_CTRL_ABORT_TRANS BIT(6) +#define RSB_CTRL_GLOBAL_INT_ENBBIT(1) +#define RSB_CTRL_SOFT_RST BIT(0) + +/* CLK CTRL fields */ +#define RSB_CCR_SDA_OUT_DELAY(v) (((v) 0x7) 8) +#define RSB_CCR_MAX_CLK_DIV0xff +#define RSB_CCR_CLK_DIV(v) ((v) RSB_CCR_MAX_CLK_DIV) + +/* STATUS fields */ +#define RSB_INTS_TRANS_ERR_ACK BIT(16) +#define RSB_INTS_TRANS_ERR_DATA_BIT(v) (((v) 8) 0xf) +#define RSB_INTS_TRANS_ERR_DATAGENMASK(11, 8) +#define RSB_INTS_LOAD_BSY BIT(2) +#define RSB_INTS_TRANS_ERR BIT(1) +#define RSB_INTS_TRANS_OVERBIT(0) + +/* LINE CTRL fields*/ +#define RSB_LCR_SCL_STATE BIT(5) +#define RSB_LCR_SDA_STATE BIT(4) +#define RSB_LCR_SCL_CTLBIT(3) +#define RSB_LCR_SCL_CTL_EN BIT(2) +#define RSB_LCR_SDA_CTLBIT(1) +#define RSB_LCR_SDA_CTL_EN BIT(0) + +/* DEVICE MODE CTRL
[PATCH 1/3] spi: mediatek: revise coding style
This patch revises mediatek spi driver coding styles.
Signed-off-by: Leilk Liu leilk@mediatek.com
---
drivers/spi/spi-mt65xx.c | 125 ---
1 file changed, 65 insertions(+), 60 deletions(-)
diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
index c467ce0..814bca4 100644
--- a/drivers/spi/spi-mt65xx.c
+++ b/drivers/spi/spi-mt65xx.c
@@ -16,6 +16,7 @@
#include linux/device.h
#include linux/err.h
#include linux/interrupt.h
+#include linux/io.h
#include linux/ioport.h
#include linux/module.h
#include linux/of.h
@@ -48,15 +49,8 @@
#define SPI_CFG1_PACKET_LOOP_MASK 0xff00
#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff
-#define SPI_CMD_ACT_OFFSET0
-#define SPI_CMD_RESUME_OFFSET 1
-#define SPI_CMD_CPHA_OFFSET 8
-#define SPI_CMD_CPOL_OFFSET 9
-#define SPI_CMD_TXMSBF_OFFSET 12
-#define SPI_CMD_RXMSBF_OFFSET 13
-#define SPI_CMD_RX_ENDIAN_OFFSET 14
-#define SPI_CMD_TX_ENDIAN_OFFSET 15
-
+#define SPI_CMD_ACT BIT(0)
+#define SPI_CMD_RESUME BIT(1)
#define SPI_CMD_RST BIT(2)
#define SPI_CMD_PAUSE_EN BIT(4)
#define SPI_CMD_DEASSERT BIT(5)
@@ -71,12 +65,10 @@
#define SPI_CMD_FINISH_IEBIT(16)
#define SPI_CMD_PAUSE_IE BIT(17)
-#define MTK_SPI_QUIRK_PAD_SELECT 1
-/* Must explicitly send dummy Tx bytes to do Rx only transfer */
-#define MTK_SPI_QUIRK_MUST_TX 1
-
#define MT8173_SPI_MAX_PAD_SEL 3
+#define MTK_SPI_PAUSE_INT_STATUS 0x2
+
#define MTK_SPI_IDLE 0
#define MTK_SPI_PAUSED 1
@@ -84,8 +76,9 @@
#define MTK_SPI_PACKET_SIZE 1024
struct mtk_spi_compatible {
- u32 need_pad_sel;
- u32 must_tx;
+ bool need_pad_sel;
+ /* Must explicitly send dummy Tx bytes to do Rx only transfer */
+ bool must_tx;
};
struct mtk_spi {
@@ -100,19 +93,11 @@ struct mtk_spi {
const struct mtk_spi_compatible *dev_comp;
};
-static const struct mtk_spi_compatible mt6589_compat = {
- .need_pad_sel = 0,
- .must_tx = 0,
-};
-
-static const struct mtk_spi_compatible mt8135_compat = {
- .need_pad_sel = 0,
- .must_tx = 0,
-};
-
+static const struct mtk_spi_compatible mt6589_compat;
+static const struct mtk_spi_compatible mt8135_compat;
static const struct mtk_spi_compatible mt8173_compat = {
- .need_pad_sel = MTK_SPI_QUIRK_PAD_SELECT,
- .must_tx = MTK_SPI_QUIRK_MUST_TX,
+ .need_pad_sel = true,
+ .must_tx = true,
};
/*
@@ -156,14 +141,24 @@ static void mtk_spi_config(struct mtk_spi *mdata,
reg_val = readl(mdata-base + SPI_CMD_REG);
/* set the mlsbx and mlsbtx */
- reg_val = ~(SPI_CMD_TXMSBF | SPI_CMD_RXMSBF);
- reg_val |= (chip_config-tx_mlsb SPI_CMD_TXMSBF_OFFSET);
- reg_val |= (chip_config-rx_mlsb SPI_CMD_RXMSBF_OFFSET);
+ if (chip_config-tx_mlsb)
+ reg_val |= SPI_CMD_TXMSBF;
+ else
+ reg_val = ~SPI_CMD_TXMSBF;
+ if (chip_config-rx_mlsb)
+ reg_val |= SPI_CMD_RXMSBF;
+ else
+ reg_val = ~SPI_CMD_RXMSBF;
/* set the tx/rx endian */
- reg_val = ~(SPI_CMD_TX_ENDIAN | SPI_CMD_RX_ENDIAN);
- reg_val |= (chip_config-tx_endian SPI_CMD_TX_ENDIAN_OFFSET);
- reg_val |= (chip_config-rx_endian SPI_CMD_RX_ENDIAN_OFFSET);
+ if (chip_config-tx_endian)
+ reg_val |= SPI_CMD_TX_ENDIAN;
+ else
+ reg_val = ~SPI_CMD_TX_ENDIAN;
+ if (chip_config-rx_endian)
+ reg_val |= SPI_CMD_RX_ENDIAN;
+ else
+ reg_val = ~SPI_CMD_RX_ENDIAN;
/* set finish and pause interrupt always enable */
reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_EN;
@@ -196,7 +191,7 @@ static int mtk_spi_prepare_hardware(struct spi_master
*master)
trans = list_first_entry(msg-transfers, struct spi_transfer,
transfer_list);
- if (trans-cs_change == 0) {
+ if (!trans-cs_change) {
mdata-state = MTK_SPI_IDLE;
mtk_spi_reset(mdata);
}
@@ -226,9 +221,14 @@ static int mtk_spi_prepare_message(struct spi_master
*master,
cpol = spi-mode SPI_CPOL ? 1 : 0;
reg_val = readl(mdata-base + SPI_CMD_REG);
- reg_val = ~(SPI_CMD_CPHA | SPI_CMD_CPOL);
- reg_val |= (cpha SPI_CMD_CPHA_OFFSET);
- reg_val |= (cpol SPI_CMD_CPOL_OFFSET);
+ if (cpha)
+ reg_val |= SPI_CMD_CPHA;
+ else
+ reg_val = ~SPI_CMD_CPHA;
+ if (cpol)
+ reg_val |= SPI_CMD_CPOL;
+ else
+ reg_val = ~SPI_CMD_CPOL;
writel(reg_val, mdata-base + SPI_CMD_REG);
chip_config = spi-controller_data;
@@ -257,8 +257,7 @@ static void mtk_spi_set_cs(struct spi_device *spi, bool
enable)
static void mtk_spi_prepare_transfer(struct spi_master
[PATCH v6 2/2] pwm: Add support for R-Car PWM Timer
This patch adds support for R-Car SoCs PWM Timer. The PWM timer of
R-Car H2 has 7 channels. So, we can use the channels if we describe
device tree nodes.
Signed-off-by: Yoshihiro Shimoda yoshihiro.shimoda...@renesas.com
Reviewed-by: Simon Horman horms+rene...@verge.net.au
---
drivers/pwm/Kconfig| 11 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-rcar.c | 265 +
3 files changed, 277 insertions(+)
create mode 100644 drivers/pwm/pwm-rcar.c
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index b1541f4..3e58a68 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -249,6 +249,17 @@ config PWM_PXA
To compile this driver as a module, choose M here: the module
will be called pwm-pxa.
+config PWM_RCAR
+ tristate Renesas R-Car PWM support
+ depends on ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2 || COMPILE_TEST
+ depends on HAS_IOMEM
+ help
+ This driver exposes the PWM Timer controller found in Renesas
+ R-Car chips through the PWM API.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-rcar.
+
config PWM_RENESAS_TPU
tristate Renesas TPU PWM support
depends on ARCH_SHMOBILE || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index ec50eb5..79d3dc3 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_PWM_MXS) += pwm-mxs.o
obj-$(CONFIG_PWM_PCA9685) += pwm-pca9685.o
obj-$(CONFIG_PWM_PUV3) += pwm-puv3.o
obj-$(CONFIG_PWM_PXA) += pwm-pxa.o
+obj-$(CONFIG_PWM_RCAR) += pwm-rcar.o
obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o
obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
diff --git a/drivers/pwm/pwm-rcar.c b/drivers/pwm/pwm-rcar.c
new file mode 100644
index 000..a29fd78
--- /dev/null
+++ b/drivers/pwm/pwm-rcar.c
@@ -0,0 +1,265 @@
+/*
+ * R-Car PWM Timer driver
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/clk.h
+#include linux/err.h
+#include linux/io.h
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/pm_runtime.h
+#include linux/pwm.h
+#include linux/slab.h
+
+#define RCAR_PWM_MAX_DIVISION 24
+#define RCAR_PWM_MAX_CYCLE 1023
+
+#define RCAR_PWMCR 0x00
+#define RCAR_PWMCNT0x04
+
+#define RCAR_PWMCR_CC0_MASK0x000f
+#define RCAR_PWMCR_CC0_SHIFT 16
+#define RCAR_PWMCR_CCMDBIT(15)
+#define RCAR_PWMCR_SYNCBIT(11)
+#define RCAR_PWMCR_SS0 BIT(4)
+#define RCAR_PWMCR_EN0 BIT(0)
+
+#define RCAR_PWMCNT_CYC0_MASK 0x03ff
+#define RCAR_PWMCNT_CYC0_SHIFT 16
+#define RCAR_PWMCNT_PH0_MASK 0x03ff
+#define RCAR_PWMCNT_PH0_SHIFT 0
+
+struct rcar_pwm_chip {
+ struct pwm_chip chip;
+ void __iomem *base;
+ struct clk *clk;
+};
+
+static inline struct rcar_pwm_chip *to_rcar_pwm_chip(struct pwm_chip *chip)
+{
+ return container_of(chip, struct rcar_pwm_chip, chip);
+}
+
+static void rcar_pwm_write(struct rcar_pwm_chip *rp, u32 data, u32 reg)
+{
+ writel(data, rp-base + reg);
+}
+
+static u32 rcar_pwm_read(struct rcar_pwm_chip *rp, u32 reg)
+{
+ return readl(rp-base + reg);
+}
+
+static void rcar_pwm_bit_modify(struct rcar_pwm_chip *rp, u32 mask, u32 data,
+ u32 reg)
+{
+ u32 val = rcar_pwm_read(rp, reg);
+
+ val = ~mask;
+ val |= data mask;
+ rcar_pwm_write(rp, val, reg);
+}
+
+static int rcar_pwm_get_clock_division(struct rcar_pwm_chip *rp, int period_ns)
+{
+ unsigned int div;
+ unsigned long clk_rate = clk_get_rate(rp-clk);
+ unsigned long long max; /* max cycle / nanoseconds */
+
+ if (clk_rate == 0)
+ return -EINVAL;
+
+ for (div = 0; div = RCAR_PWM_MAX_DIVISION; div++) {
+ max = (unsigned long long)NSEC_PER_SEC * RCAR_PWM_MAX_CYCLE *
+ (1 div);
+ do_div(max, clk_rate);
+ if (period_ns max)
+ break;
+ }
+
+ return (div = RCAR_PWM_MAX_DIVISION) ? div : -ERANGE;
+}
+
+static void rcar_pwm_set_clock_control(struct rcar_pwm_chip *rp, int div)
+{
+ u32 val = rcar_pwm_read(rp, RCAR_PWMCR);
+
+ val = ~(RCAR_PWMCR_CCMD | RCAR_PWMCR_CC0_MASK);
+ if (div 1)
+ val |= RCAR_PWMCR_CCMD;
+ div = 1;
+ val |= div RCAR_PWMCR_CC0_SHIFT;
+ rcar_pwm_write(rp, val, RCAR_PWMCR);
+}
+
+static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, int duty_ns,
+ int period_ns)
+{
+ unsigned long long one_cycle, tmp; /* 0.01
[PATCH v6 0/2] pwm: Add support for R-Car PWM Timer
This patch set is based on the latest linux-pwm.git / for-next branch. (commit id = 6e146f5c41da7e9601fe92fb4d06b45431dbf95b) Changes from v5: - Fix coding style and unreadable code in patch 2. - Add Reviewed-by: Simon Horman horms+rene...@verge.net.au. Changes from v4: - Clean up coding style and typo in patch 2. - Change to_rcar_pwm_chip() macro to static inline function in patch 2. - Use writel()/readl() instead of iowrite32()/ioread32() in patch 2. - Add an error handling in rcar_pwm_config() to avoid silent in patch 2. - Remove success message in rcar_pwm_probe() in patch 2. - Change rcar_pwm_remove() to always call pm_runtime_disable() in patch 2. Changes from v3: - Fix register size in patch 1. - Add Acked-by: Geert Uytterhoeven geert+rene...@glider.be in patch 1 - Remove an unnecessary definition in patch 2. - Use ULL to avoid overflow in patch 2. - Remove unnecessary casts in patch 2. Changes from v2: - Add compatible string renesas,pwm-rcar. - Remove compatible strings renesas,pwm-r8a77xx in rcar_pwm_of_table. - Fix build error. Changes from v1: - Change compatible string to SoC-specific compatible values. - Fix #pwm-call value to 2 in the device tree document. - Fix depends on value in Kconfig. - Fix help explanation in Kconfig. - Remove an unnecessary member in rcar_pwm_chip. - Remove hardcoded number of channels and change chip.npwm value to 1. - Fix formulas for clock calculation to improve accuracy. Yoshihiro Shimoda (2): pwm: Add device tree binding document for R-Car PWM Timer pwm: Add support for R-Car PWM Timer .../devicetree/bindings/pwm/renesas,pwm-rcar.txt | 27 +++ drivers/pwm/Kconfig| 11 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-rcar.c | 265 + 4 files changed, 304 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt create mode 100644 drivers/pwm/pwm-rcar.c -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 1/2] pwm: Add device tree binding document for R-Car PWM Timer
Add binding document for Renesas PWM Timer on R-Car SoCs.
Signed-off-by: Yoshihiro Shimoda yoshihiro.shimoda...@renesas.com
Acked-by: Geert Uytterhoeven geert+rene...@glider.be
Reviewed-by: Simon Horman horms+rene...@verge.net.au
---
.../devicetree/bindings/pwm/renesas,pwm-rcar.txt | 27 ++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
diff --git a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
new file mode 100644
index 000..ea0a27b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt
@@ -0,0 +1,27 @@
+* Renesas R-Car PWM Timer Controller
+
+Required Properties:
+- compatible: should be one of the following.
+ - renesas,pwm-rcar: for generic R-Car compatible PWM Timer
+ - renesas,pwm-r8a7778: for R-Car M1A
+ - renesas,pwm-r8a7779: for R-Car H1
+ - renesas,pwm-r8a7790: for R-Car H2
+ - renesas,pwm-r8a7791: for R-Car M2-W
+ - renesas,pwm-r8a7794: for R-Car E2
+- reg: base address and length of the registers block for the PWM.
+- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
+ the cells format.
+- clocks: clock phandle and specifier pair.
+- pinctrl-0: phandle, referring to a default pin configuration node.
+- pinctrl-names: Set to default.
+
+Example: R8A7790 (R-Car H2) PWM Timer node
+
+ pwm0: pwm@e6e3 {
+ compatible = renesas,pwm-r8a7790, renesas,pwm-rcar;
+ reg = 0 0xe6e3 0 0x8;
+ #pwm-cells = 2;
+ clocks = mstp5_clks R8A7790_CLK_PWM;
+ pinctrl-0 = pwm0_pins;
+ pinctrl-names = default;
+ };
--
1.9.1
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[PATCH v3 6/8] ARM: dts: sun8i: Add Reduced Serial Bus controller device node to A23/A33 dtsi
This patch adds a device node for the Reduced Serial Bus (RSB)
controller and the defacto pinmux setting to the A23/A33 dtsi.
Since there is only one possible pinmux setting for RSB, just
set it in the dtsi.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 27a925ec17d2..db3671382cb2 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -661,6 +661,13 @@
#size-cells = 0;
#gpio-cells = 3;
+ r_rsb_pins: r_rsb {
+ allwinner,pins = PL0, PL1;
+ allwinner,function = s_rsb;
+ allwinner,drive = SUN4I_PINCTRL_20_MA;
+ allwinner,pull = SUN4I_PINCTRL_PULL_UP;
+ };
+
r_uart_pins_a: r_uart@0 {
allwinner,pins = PL2, PL3;
allwinner,function = s_uart;
@@ -668,5 +675,19 @@
allwinner,pull = SUN4I_PINCTRL_NO_PULL;
};
};
+
+ r_rsb: i2c@01f03400 {
+ compatible = allwinner,sun8i-a23-rsb;
+ reg = 0x01f03400 0x400;
+ interrupts = GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH;
+ clocks = apb0_gates 3;
+ clock-frequency = 300;
+ resets = apb0_rst 3;
+ pinctrl-names = default;
+ pinctrl-0 = r_rsb_pins;
+ status = disabled;
+ #address-cells = 2;
+ #size-cells = 0;
+ };
};
};
--
2.5.0
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[PATCH v3 0/8] ARM: sunxi: Add Reduced Serial Bus support
Hi everyone, This is my third attempt at adding support for Allwinner's Reduced Serial Bus (RSB), which is used to communicate with PMICs and other peripherals on their newer SoCs, such as the A23/A33/A80. RSB is a simplified two wire interface using push-pull outputs, supporting multiple slaves, address and data parity checks, and clock speeds up to 20 MHz. The bus only supports simple register read/writes, with possible register sizes of 8/16/32 bits. Access sizes not matching the slave device register sizes result in NACKs or errors. 32 bit registers in devices have yet to be seen. Previous attempts to add support through the I2C subsystem have been rejected, as the bus line protocol is too different to even consider. In this version, RSB is implemented as a new bus type, much like SPMI. Even though there will almost certainly be only one RSB driver, it's still split into the bus core framework and vendor specific driver, like other subsystems. Theoretically someone could implement a bit-banging driver for it. Patches 1 2 add the DT bindings for common RSB properties and the controller. Patches 3 4 add the RSB framework core and sunxi driver. Patch 5 (based on regmap/for-next) adds an RSB regmap driver. Patch 6 adds the RSB nodes for A23/A33 dtsi. Patch 7 8 enable the RSB controller on the boards I have. Still to come are axp20x driver support for the RSB based AXP223. The complete series can be found at: https://github.com/wens/linux/tree/sunxi-rsb-v3 Since this is a new subsystem, I'm not sure who should pick up the first 4 patches, or whether they are even in the right place. Any suggestions? Regards, ChenYu Chen-Yu Tsai (8): rsb: Add generic Reduced Serial Bus (RSB) controller binding documentation rsb: sunxi: Add Allwinner Reduced Serial Bus (RSB) controller bindings rsb: Linux driver framework for Reduced Serial Bus (RSB) rsb: sunxi: Add driver for Allwinner Reduced Serial Bus controller regmap: rsb: Add support for Reduced Serial Bus (RSB) based regmaps ARM: dts: sun8i: Add Reduced Serial Bus controller device node to A23/A33 dtsi ARM: dts: sun8i: ippo-q8h-v5: Enable Reduced Serial Bus controller ARM: dts: sun8i: sinlinx-sina33: Enable Reduced Serial Bus controller .../devicetree/bindings/rsb/rsb-sunxi.txt | 34 ++ Documentation/devicetree/bindings/rsb/rsb.txt | 50 ++ arch/arm/boot/dts/sun8i-a23-a33.dtsi | 21 + arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts| 4 + arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 4 + drivers/Kconfig| 2 + drivers/Makefile | 1 + drivers/base/regmap/Kconfig| 6 +- drivers/base/regmap/Makefile | 1 + drivers/base/regmap/regmap-rsb.c | 121 + drivers/rsb/Kconfig| 26 ++ drivers/rsb/Makefile | 6 + drivers/rsb/rsb-core.c | 511 + drivers/rsb/rsb-sunxi.c| 441 ++ include/linux/regmap.h | 36 ++ include/linux/rsb.h| 144 ++ 16 files changed, 1407 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/rsb/rsb-sunxi.txt create mode 100644 Documentation/devicetree/bindings/rsb/rsb.txt create mode 100644 drivers/base/regmap/regmap-rsb.c create mode 100644 drivers/rsb/Kconfig create mode 100644 drivers/rsb/Makefile create mode 100644 drivers/rsb/rsb-core.c create mode 100644 drivers/rsb/rsb-sunxi.c create mode 100644 include/linux/rsb.h -- 2.5.0 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 7/8] ARM: dts: sun8i: ippo-q8h-v5: Enable Reduced Serial Bus controller
The Reduced Serial Bus controller is used to talk to the onboard PMIC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
index 8d9da6886a4c..2e45a82c8981 100644
--- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
+++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
@@ -120,6 +120,10 @@
};
};
+r_rsb {
+ status = okay;
+};
+
r_uart {
pinctrl-names = default;
pinctrl-0 = r_uart_pins_a;
--
2.5.0
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[PATCH v7 2/3] cpufreq: mediatek: Add MT8173 cpufreq driver
Mediatek MT8173 is an ARMv8 based quad-core (2*Cortex-A53 and
2*Cortex-A72) SoC with duall clusters. For each cluster, two voltage
inputs, Vproc and Vsram are supplied by two regulators. For the big
cluster, two regulators come from different PMICs. In this case, when
scaling voltage inputs of the cluster, the voltages of two regulator
inputs need to be controlled by software explicitly under the SoC
specific limitation:
100mV Vsram - Vproc 200mV
which is called 'voltage tracking' mechanism. And when scaling the
frequency of cluster clock input, the input MUX need to be parented to
another intermediate stable PLL first and reparented to the original
PLL once the original PLL is stable at the target frequency. This patch
implements those mechanisms to enable CPU DVFS support for Mediatek
MT8173 SoC.
Signed-off-by: Pi-Cheng Chen pi-cheng.c...@linaro.org
Acked-by: Viresh Kumar viresh.ku...@linaro.org
---
Changes in v7:
- add of_machine_is_compatible() check to be multiplatform friendly
---
drivers/cpufreq/Kconfig.arm | 7 +
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/mt8173-cpufreq.c | 527 +++
3 files changed, 535 insertions(+)
create mode 100644 drivers/cpufreq/mt8173-cpufreq.c
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index cc8a71c..2bacf24 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -130,6 +130,13 @@ config ARM_KIRKWOOD_CPUFREQ
This adds the CPUFreq driver for Marvell Kirkwood
SoCs.
+config ARM_MT8173_CPUFREQ
+ bool Mediatek MT8173 CPUFreq support
+ depends on ARCH_MEDIATEK REGULATOR
+ select PM_OPP
+ help
+ This adds the CPUFreq driver support for Mediatek MT8173 SoC.
+
config ARM_OMAP2PLUS_CPUFREQ
bool TI OMAP2+
depends on ARCH_OMAP2PLUS
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index 2169bf7..9c75faf 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -62,6 +62,7 @@ obj-$(CONFIG_ARM_HISI_ACPU_CPUFREQ) += hisi-acpu-cpufreq.o
obj-$(CONFIG_ARM_IMX6Q_CPUFREQ)+= imx6q-cpufreq.o
obj-$(CONFIG_ARM_INTEGRATOR) += integrator-cpufreq.o
obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o
+obj-$(CONFIG_ARM_MT8173_CPUFREQ) += mt8173-cpufreq.o
obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ)+= omap-cpufreq.o
obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o
obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o
diff --git a/drivers/cpufreq/mt8173-cpufreq.c b/drivers/cpufreq/mt8173-cpufreq.c
new file mode 100644
index 000..49caed2
--- /dev/null
+++ b/drivers/cpufreq/mt8173-cpufreq.c
@@ -0,0 +1,527 @@
+/*
+ * Copyright (c) 2015 Linaro Ltd.
+ * Author: Pi-Cheng Chen pi-cheng.c...@linaro.org
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk.h
+#include linux/cpu.h
+#include linux/cpu_cooling.h
+#include linux/cpufreq.h
+#include linux/cpumask.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/pm_opp.h
+#include linux/regulator/consumer.h
+#include linux/slab.h
+#include linux/thermal.h
+
+#define MIN_VOLT_SHIFT (10)
+#define MAX_VOLT_SHIFT (20)
+#define MAX_VOLT_LIMIT (115)
+#define VOLT_TOL (1)
+
+/*
+ * The struct mtk_cpu_dvfs_info holds necessary information for doing CPU DVFS
+ * on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in
+ * Mediatek SoCs has two voltage inputs, Vproc and Vsram. In some cases the two
+ * voltage inputs need to be controlled under a hardware limitation:
+ * 100mV Vsram - Vproc 200mV
+ *
+ * When scaling the clock frequency of a CPU clock domain, the clock source
+ * needs to be switched to another stable PLL clock temporarily until
+ * the original PLL becomes stable at target frequency.
+ */
+struct mtk_cpu_dvfs_info {
+ struct device *cpu_dev;
+ struct regulator *proc_reg;
+ struct regulator *sram_reg;
+ struct clk *cpu_clk;
+ struct clk *inter_clk;
+ struct thermal_cooling_device *cdev;
+ int intermediate_voltage;
+ bool need_voltage_tracking;
+};
+
+static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
+ int new_vproc)
+{
+ struct regulator *proc_reg = info-proc_reg;
+ struct regulator *sram_reg = info-sram_reg;
+ int old_vproc, old_vsram, new_vsram, vsram, vproc, ret;
+
+ old_vproc = regulator_get_voltage(proc_reg);
+ old_vsram =
[PATCH v3 2/8] rsb: sunxi: Add Allwinner Reduced Serial Bus (RSB) controller bindings
Recent Allwinner SoCs, starting with the A23, have a Reduced Serial Bus
(RSB) controller. This is used to talk to the PMIC, and later with the
A80 and A83 platform, the audio codec IC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
.../devicetree/bindings/rsb/rsb-sunxi.txt | 34 ++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rsb/rsb-sunxi.txt
diff --git a/Documentation/devicetree/bindings/rsb/rsb-sunxi.txt
b/Documentation/devicetree/bindings/rsb/rsb-sunxi.txt
new file mode 100644
index ..057d24b84628
--- /dev/null
+++ b/Documentation/devicetree/bindings/rsb/rsb-sunxi.txt
@@ -0,0 +1,34 @@
+
+* Allwinner RSB (Reduced Serial Bus) controller
+
+Required properties :
+
+ - reg : Offset and length of the register set for the controller.
+ - compatible : Shall be allwinner,sun8i-a23-rsb.
+ - interrupts : The interrupt line associated to the RSB controller.
+ - clocks : The gate clk associated to the RSB controller.
+ - resets : The reset line associated to the RSB controller.
+ - #address-cells : shall be 2
+ - #size-cells : shall be 0
+
+Optional properties :
+
+ - clock-frequency : Desired RSB bus clock frequency in Hz. Maximum is 20MHz.
+If not set the current hardware setting shall be used.
+
+See rsb.txt for the generic RSB bindings for RSB slaves / child nodes.
+
+Example:
+
+ rsb@01f03400 {
+ compatible = allwinner,sun8i-a23-rsb;
+ reg = 0x01f03400 0x400;
+ interrupts = 0 39 4;
+ clocks = apb0_gates 3;
+ clock-frequency = 300;
+ resets = apb0_rst 3;
+ #address-cells = 2;
+ #size-cells = 0;
+
+ /* child nodes ... */
+ };
--
2.5.0
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[PATCH v3 1/8] rsb: Add generic Reduced Serial Bus (RSB) controller binding documentation
Reduced Serial Bus is a proprietary 2-line push-pull serial bus
supporting multiple slave devices.
It was developed by Allwinner, Inc. and used by Allwinner and X-Powers,
Inc. for their line of PMICs and other peripheral ICs.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/rsb/rsb.txt | 50 +++
1 file changed, 50 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rsb/rsb.txt
diff --git a/Documentation/devicetree/bindings/rsb/rsb.txt
b/Documentation/devicetree/bindings/rsb/rsb.txt
new file mode 100644
index ..0b027948ca9c
--- /dev/null
+++ b/Documentation/devicetree/bindings/rsb/rsb.txt
@@ -0,0 +1,50 @@
+Reduced Serial Bus (RSB) Controller
+
+This document defines a generic set of bindings for use by RSB controllers.
+A controller is modelled in device tree as a node with zero or more child
+nodes, each representing a unique slave device on the bus.
+
+Required properties:
+
+ - #address-cells : must be 2
+ - #size-cells : must be 0
+
+Optional properties:
+
+ - clock-frequency : Desired bus clock frequency in Hz. Maximum is 20 MHz.
+
+Child nodes:
+
+An RSB controller node can contain zero or more child nodes representing
+slave devices on the bus. Child 'reg' properties are specified as a
+runtime address, hardware address pair. The hardware address is hardwired
+in the device, which can normally be found in the datasheet. The runtime
+address is set by software. No 2 devices on the same bus shall have the
+same runtime address.
+
+Valid runtime addresses - There are only 15 valid runtime addresses:
+
+0x17, 0x2d, 0x3a, 0x4e, 0x59, 0x63, 0x74, 0x8b,
+0x9c, 0xa6, 0xb1, 0xc5, 0xd2, 0xe8, 0xff
+
+It is highly recommended that one choose the same runtime addresses as
+vendor BSPs use so that a) the addresses remain the same across different
+software systems, and b) addresses of supported and listed slave devices
+don't conflict with unsupported or not yet listed devices.
+
+Example:
+
+ rsb@... {
+ compatible = ...;
+ reg = ...;
+ /* ... */
+ #address-cells = 2;
+ #size-cells = 0;
+
+ pmic@2d {
+ compatible = ...;
+ reg = 0x2d 0x3e3;
+
+ /* ... */
+ };
+ };
--
2.5.0
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[PATCH v4 3/5] dt/bindings: qcom_nandc: Add DT bindings
Add DT bindings document for the Qualcomm NAND controller driver.
Cc: devicetree@vger.kernel.org
v4:
- No changes
v3:
- Don't use '0x' when specifying nand controller address space
- Add optional property for on-flash bbt usage
Acked-by: Andy Gross agr...@codeaurora.org
Signed-off-by: Archit Taneja arch...@codeaurora.org
---
.../devicetree/bindings/mtd/qcom_nandc.txt | 49 ++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt
diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
new file mode 100644
index 000..1de4643
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
@@ -0,0 +1,49 @@
+* Qualcomm NAND controller
+
+Required properties:
+- compatible: should be qcom,ebi2-nand for IPQ806x
+- reg: MMIO address range
+- clocks: must contain core clock and always on clock
+- clock-names: must contain core for the core clock and aon for the
+ always on clock
+- dmas:DMA specifier, consisting of a phandle to the
ADM DMA
+ controller node and the channel number to be used for
+ NAND. Refer to dma.txt and qcom_adm.txt for more details
+- dma-names: must be rxtx
+- qcom,cmd-crci: must contain the ADM command type CRCI block instance
+ number specified for the NAND controller on the given
+ platform
+- qcom,data-crci: must contain the ADM data type CRCI block instance
+ number specified for the NAND controller on the given
+ platform
+
+Optional properties:
+- nand-bus-width: bus width. Must be 8 or 16. If not present, 8 is chosen
+ as default
+
+- nand-ecc-strength: number of bits to correct per ECC step. Must be 4 or 8
+ bits. If not present, 4 is chosen as default
+- nand-on-flash-bbt: Create/use on-flash bad block table
+
+The device tree may optionally contain sub-nodes describing partitions of the
+address space. See partition.txt for more detail.
+
+Example:
+
+nand@1ac0 {
+ compatible = qcom,ebi2-nandc;
+ reg = 0x1ac0 0x800;
+
+ clocks = gcc EBI2_CLK,
+gcc EBI2_AON_CLK;
+ clock-names = core, aon;
+
+ dmas = adm_dma 3;
+ dma-names = rxtx;
+ qcom,cmd-crci = 15;
+ qcom,data-crci = 3;
+
+ partition@0 {
+ ...
+ };
+};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
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[PATCH v4 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform
Enable the NAND controller node on the AP148 platform. Provide pinmux
information.
v4:
- Move bias-disable out of mux and create a separate group for it.
- Place the dma node inside soc node and give the full path with address.
v3, v2, v1:
- No changes
Cc: devicetree@vger.kernel.org
Signed-off-by: Archit Taneja arch...@codeaurora.org
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 40
1 file changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
index 7f9ea50..648994c 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -30,6 +30,32 @@
bias-none;
};
};
+ nand_pins: nand_pins {
+ mux {
+ pins = gpio34, gpio35, gpio36,
+ gpio37, gpio38, gpio39,
+ gpio40, gpio41, gpio42,
+ gpio43, gpio44, gpio45,
+ gpio46, gpio47;
+ function = nand;
+ drive-strength = 10;
+ };
+ disable {
+ pins = gpio34, gpio35, gpio36,
+ gpio37, gpio38;
+ bias-disable;
+ };
+ pullups {
+ pins = gpio39;
+ bias-pull-up;
+ };
+ hold {
+ pins = gpio40, gpio41, gpio42,
+ gpio43, gpio44, gpio45,
+ gpio46, gpio47;
+ bias-bus-hold;
+ };
+ };
};
gsbi@1630 {
@@ -93,5 +119,19 @@
sata@2900 {
status = ok;
};
+
+ dma@1830 {
+ status = ok;
+ };
+
+ nand@1ac0 {
+ status = ok;
+
+ pinctrl-0 = nand_pins;
+ pinctrl-names = default;
+
+ nand-ecc-strength = 4;
+ nand-bus-width = 8;
+ };
};
};
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[PATCH v4 4/5] arm: qcom: dts: Add NAND controller node for ipq806x
The nand controller in IPQ806x is of the 'EBI2 type'. Use the corresponding
compatible string.
Cc: devicetree@vger.kernel.org
Reviewed-by: Andy Gross agr...@codeaurora.org
Signed-off-by: Archit Taneja arch...@codeaurora.org
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi
b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 1e1b3f0..a7f0ee5 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -350,5 +350,20 @@
status = disabled;
};
+ nand@1ac0 {
+ compatible = qcom,ebi2-nandc;
+ reg = 0x1ac0 0x800;
+
+ clocks = gcc EBI2_CLK,
+gcc EBI2_AON_CLK;
+ clock-names = core, aon;
+
+ dmas = adm_dma 3;
+ dma-names = rxtx;
+ qcom,cmd-crci = 15;
+ qcom,data-crci = 3;
+
+ status = disabled;
+ };
};
};
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[PATCH] ARM: qcom: add memory node to IPQ806x/AP148
On recent bootloaders, the bootloader patches the DT blob with memory
information. However, with old bootloader, this operation doesn't
happen, which leads the board to freeze in the early init code.
This patch adds the memory node to the AP148 dts explicitly to cover all
boot cases.
Signed-off-by: Mathieu Olivari math...@codeaurora.org
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
index 36e2b04..6886d09 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -4,6 +4,11 @@
model = Qualcomm IPQ8064/AP148;
compatible = qcom,ipq8064-ap148, qcom,ipq8064;
+ memory@0 {
+ reg = 0x4200 0x1e00;
+ device_type = memory;
+ };
+
reserved-memory {
#address-cells = 1;
#size-cells = 1;
--
2.1.4
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Re: [PATCH v4 2/5] pci:host: Add Altera PCIe host controller driver
On Wed, Aug 19, 2015 at 3:11 AM, Dinh Nguyen dinh.li...@gmail.com wrote:
On Mon, Aug 17, 2015 at 4:09 AM, Ley Foon Tan lf...@altera.com wrote:
This patch adds the Altera PCIe host controller driver.
Signed-off-by: Ley Foon Tan lf...@altera.com
---
drivers/pci/host/Kconfig | 7 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-altera.c | 543
+
3 files changed, 551 insertions(+)
create mode 100644 drivers/pci/host/pcie-altera.c
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 675c2d1..4b4754a 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -145,4 +145,11 @@ config PCIE_IPROC_BCMA
Say Y here if you want to use the Broadcom iProc PCIe controller
through the BCMA bus interface
snip
+
+/* Address translation table entry size */
+#define ATT_ENTRY_SIZE 8
+
+#define DWORD_MASK 3
+
+struct altera_pcie {
+ struct platform_device *pdev;
+ struct resource *txs;
You have Txs documented in the bindings document, you have a pointer
here, but you've never used it
anywhre in the code? What is it for?
Good catch. Forgot to remove this txs field here, we no longer require
to keep this in struct.
+ void __iomem*cra_base;
+ int irq;
+ u8 root_bus_nr;
+ struct irq_domain *irq_domain;
+ struct resource bus_range;
+ struct list_headresources;
+};
+
snip
+
+static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
+ int where, u32 *value)
+{
+ int ret;
+ u32 headers[TLP_HDR_SIZE];
+
+ if (bus == pcie-root_bus_nr)
+ headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD0);
+ else
+ headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD1);
+
+ headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie-root_bus_nr, devfn),
+ TLP_READ_TAG);
+ headers[2] = TLP_CFG_DW2(bus, devfn, where);
+
+ tlp_write_packet(pcie, headers, 0);
+
+ ret = tlp_read_packet(pcie, value);
+ if (ret)
+ *value = ~0UL; /* return 0x if error */
+
+ return ret;
+}
+
+static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
+ int where, u32 value)
+{
+ u32 headers[TLP_HDR_SIZE];
+
+ if (bus == pcie-root_bus_nr)
+ headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR0);
+ else
+ headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR1);
+
+ headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie-root_bus_nr, devfn),
+ TLP_WRITE_TAG);
+ headers[2] = TLP_CFG_DW2(bus, devfn, where);
+
+ tlp_write_packet(pcie, headers, value);
+
+ tlp_read_packet(pcie, NULL);
You need to check for the error here.
Okay.
+
+ /* Keep an eye out for changes to the root bus number */
+ if ((bus == pcie-root_bus_nr) (where == PCI_PRIMARY_BUS))
+ pcie-root_bus_nr = (u8)(value);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
snip
+
+static int altera_pcie_parse_dt(struct altera_pcie *pcie)
+{
+ struct resource *cra;
+ struct platform_device *pdev = pcie-pdev;
+
+ cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, Cra);
+ if (!cra) {
+ cra = platform_get_resource_byname(pdev, IORESOURCE_MEM,
cra);
+ if (!cra) {
+ dev_err(pdev-dev,
+ no cra memory resource defined\n);
+ return -ENODEV;
+ }
+ }
+
What about Txs?
We doesn't need to get resource for Txs here. We use standard pci
binding with ranges dts parameter to map the pci memory region.
Our dts generator still will generate this Txs dts parameter,
because it is one of Avalon slave port of PCIe IP.
Regards
Ley Foon
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Re: [PATCH v4 4/5] Documentation: dt-bindings: pci: altera pcie device tree binding
On Wed, Aug 19, 2015 at 3:22 AM, Dinh Nguyen dinh.li...@gmail.com wrote:
On Mon, Aug 17, 2015 at 4:09 AM, Ley Foon Tan lf...@altera.com wrote:
This patch adds the bindings for Altera PCIe host controller driver and
Altera PCIe MSI driver.
Signed-off-by: Ley Foon Tan lf...@altera.com
---
.../devicetree/bindings/pci/altera-pcie-msi.txt| 27
.../devicetree/bindings/pci/altera-pcie.txt| 49
++
2 files changed, 76 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
b/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
new file mode 100644
index 000..7f330c9
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
@@ -0,0 +1,27 @@
+* Altera PCIe MSI controller
+
+Required properties:
+- compatible: should contain altr,msi-1.0
+- reg: specifies the physical base address of the controller and
+ the length of the memory mapped region.
+- reg-names: Must include the following entries:
+ csr: CSR registers
+ vector_slave: vectors region
Can you be a little bit more specific here? What is a vectors region?
Also, I'm not 100% sure, but I think vector-slave should be used.
This parameter is the Avalon slave name in MSI IP hardware. It is auto
generated from dts generator.
I can add more description for it here.
+-interrupts: specifies the interrupt source of the parent interrupt
+ controller. The format of the interrupt specifier depends on
the
+ parent interrupt controller.
Need to document interrupt-parent .
Okay.
+- num-vectors: Number of vectors, range 1 to 32.
+- msi-controller: indicates that this is MSI controller node
+
+
+Example
+msi0: msi@0xFF20 {
+ compatible = altr,msi-1.0;
+ reg = 0xFF20 0x0010
+ 0xFF200010 0x0080;
+ reg-names = csr, vector_slave;
+ interrupt-parent = hps_0_arm_gic_0;
+ interrupts = 0 42 4;
+ msi-controller = 1;
+ num-vectors = 32;
+};
diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt
b/Documentation/devicetree/bindings/pci/altera-pcie.txt
new file mode 100644
index 000..73a8dc0
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/altera-pcie.txt
@@ -0,0 +1,49 @@
+* Altera PCIe controller
+
+Required properties:
+- compatible : should contain altr,pcie-root-port-1.0
+- reg: A list of physical base address and length for TXS and CRA.
+- reg-names: Must include the following entries:
+ Txs or txs: TXS region
What is a TXS region?
It is TX slave port in PCIe IP. I can update this.
+ Cra or cra: Control register access region
+-interrupts: specifies the interrupt source of the parent interrupt
controller.
+ The format of the interrupt specifier depends on the parent
interrupt
+ controller.
+- device_type: must be pci
+- #address-cells: set to 3
+- #size-cells: set to 2
+- #interrupt-cells:set to 1
+- ranges: Describes the translation of addresses for root
ports and standard
+ PCI regions.
+- interrupt-map-mask and interrupt-map: standard PCI properties
+ to define the mapping of the PCIe interface to interrupt
+ numbers.
interrupt-parent ?
Will add it.
Thanks.
Regards
Ley Foon
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Re: [PATCH 2/2] ARM: dts: rockchip: correct regulator PM properties
On Tue, Aug 18, 2015 at 09:17:06PM +0200, Heiko Stuebner wrote:
Am Dienstag, 18. August 2015, 11:44:15 schrieb Brian Norris:
This DTS file was submitted with non-upstream bindings. I happened
across this while reviewing the jaq DTS.
Signed-off-by: Brian Norris briannor...@chromium.org
Cc: Alexandru M Stan ams...@chromium.org
Cc: Douglas Anderson diand...@chromium.org
---
Tested on jaq, not minnie
arch/arm/boot/dts/rk3288-veyron-minnie.dts | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts
b/arch/arm/boot/dts/rk3288-veyron-minnie.dts index
0e30bd6bf92b..6f619c154dc6 100644
--- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
@@ -128,12 +128,16 @@
regulator-min-microvolt = 330;
regulator-max-microvolt = 330;
regulator-name = vcc33_touch;
- regulator-suspend-mem-disabled;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
};
vcc5v_touch: SWITCH_REG2 {
regulator-name = vcc5v_touch;
- regulator-suspend-mem-disabled;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
wouldn't regulator-suspend-mem-disabled translate to regulator-off-in-suspend?
At least looks like it according to https://lkml.org/lkml/2013/7/25/592
You are right. My bad. Will fix. (Need to fix this in jaq too.)
Thanks,
Brian
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Re: [PATCH 1/2] ARM: dts: rockchip: add veyron-jaq board
Thanks for the quick review.
On Tue, Aug 18, 2015 at 09:19:05PM +0200, Heiko Stuebner wrote:
Am Dienstag, 18. August 2015, 11:44:14 schrieb Brian Norris:
a.k.a. Haier Chromebook 11
Signed-off-by: Brian Norris briannor...@chromium.org
Cc: Alexandru M Stan ams...@chromium.org
Cc: Douglas Anderson diand...@chromium.org
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/rk3288-veyron-jaq.dts | 176
2 files changed, 177 insertions(+)
create mode 100644 arch/arm/boot/dts/rk3288-veyron-jaq.dts
missing binding documentation in
Documentation/devicetree/bindings/arm/rockchip.txt (needs new entry above
Jerry)
I don't know how I managed this, but I had already fixed this up in my
tree and amended the commit. I must have grabbed an old commit ref when
generating the patches... Sorry, will fix when sending v2.
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7805a6541a38..7a2c3c88ce9e 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -493,6 +493,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-jerry.dtb \
rk3288-veyron-minnie.dtb \
rk3288-veyron-pinky.dtb \
+ rk3288-veyron-jaq.dtb \
rk3288-veyron-speedy.dtb
please sort alphabetically (in this case somewhere above jerry)
Will do.
dtb-$(CONFIG_ARCH_S3C24XX) += \
s3c2416-smdk2416.dtb
diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts
b/arch/arm/boot/dts/rk3288-veyron-jaq.dts new file mode 100644
index ..ea6130156216
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
@@ -0,0 +1,176 @@
+/*
+ * Google Veyron Jaq Rev 1+ board device tree source
+ *
+ * Copyright 2015 Google, Inc
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the Software), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include rk3288-veyron-chromebook.dtsi
+#include cros-ec-sbs.dtsi
+
+/ {
+ model = Google Jaq;
+ compatible = google,veyron-jaq-rev5, google,veyron-jaq-rev4,
+google,veyron-jaq-rev3, google,veyron-jaq-rev2,
+google,veyron-jaq-rev1, google,veyron-jaq,
+google,veyron, rockchip,rk3288;
+
+ panel_regulator: panel-regulator {
+ compatible = regulator-fixed;
+ enable-active-high;
+ gpio = gpio7 14 GPIO_ACTIVE_HIGH;
+ pinctrl-names = default;
+ pinctrl-0 = lcd_enable_h;
+ regulator-name = panel_regulator;
+ vin-supply = vcc33_sys;
+ };
+
+ vcc18_lcd: vcc18-lcd {
+ compatible = regulator-fixed;
+ enable-active-high;
+ gpio = gpio2 13 GPIO_ACTIVE_HIGH;
+ pinctrl-names = default;
+ pinctrl-0 = avdd_1v8_disp_en;
+ regulator-name = vcc18_lcd;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = vcc18_wl;
+ };
+
+ backlight_regulator: backlight-regulator {
+
Re: [PATCH 2/2] ARM: dts: rockchip: correct regulator PM properties
On Tue, Aug 18, 2015 at 03:48:31PM -0700, Brian Norris wrote:
On Tue, Aug 18, 2015 at 09:17:06PM +0200, Heiko Stuebner wrote:
Am Dienstag, 18. August 2015, 11:44:15 schrieb Brian Norris:
This DTS file was submitted with non-upstream bindings. I happened
across this while reviewing the jaq DTS.
Signed-off-by: Brian Norris briannor...@chromium.org
Cc: Alexandru M Stan ams...@chromium.org
Cc: Douglas Anderson diand...@chromium.org
---
Tested on jaq, not minnie
arch/arm/boot/dts/rk3288-veyron-minnie.dts | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts
b/arch/arm/boot/dts/rk3288-veyron-minnie.dts index
0e30bd6bf92b..6f619c154dc6 100644
--- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
@@ -128,12 +128,16 @@
regulator-min-microvolt = 330;
regulator-max-microvolt = 330;
regulator-name = vcc33_touch;
- regulator-suspend-mem-disabled;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
};
vcc5v_touch: SWITCH_REG2 {
regulator-name = vcc5v_touch;
- regulator-suspend-mem-disabled;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
wouldn't regulator-suspend-mem-disabled translate to
regulator-off-in-suspend?
At least looks like it according to https://lkml.org/lkml/2013/7/25/592
You are right. My bad. Will fix. (Need to fix this in jaq too.)
Now that I'm looking a little closer, it seems like other existing DTS's
are broken too, then. Jerry looks like it was converted to the
regulator-state-mem node binding, but the conversion doesn't seem to
make sense when I compare the chromium DTS sources with the for-next
source I see in your tree.
In -next:
regulators {
mic_vcc: LDO_REG2 {
regulator-name = mic_vcc;
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = 180;
regulator-max-microvolt = 180;
regulator-state-mem {
regulator-on-in-suspend;
};
};
};
But chromium had:
regulators {
mic_vcc: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = 180;
regulator-max-microvolt = 180;
regulator-name = mic_vcc;
regulator-suspend-mem-disabled;
};
};
So I guess I'll make the proper conversion for all the veyron variants I
see.
Brian
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Re: [PATCH v2 1/5] input: touchscreen: add imx6ul_tsc driver support
Hi Haibo, On Tue, Jul 28, 2015 at 05:58:37PM +0800, Haibo Chen wrote: Freescale i.MX6UL contains a internal touchscreen controller, this patch add a driver to support this controller. This looks pretty reasonable; just a few comments below. Signed-off-by: Haibo Chen haibo.c...@freescale.com --- drivers/input/touchscreen/Kconfig | 12 + drivers/input/touchscreen/Makefile | 1 + drivers/input/touchscreen/imx6ul_tsc.c | 504 + 3 files changed, 517 insertions(+) create mode 100644 drivers/input/touchscreen/imx6ul_tsc.c diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig index 5b272ba..32c300d 100644 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig @@ -479,6 +479,18 @@ config TOUCHSCREEN_MTOUCH To compile this driver as a module, choose M here: the module will be called mtouch. +config TOUCHSCREEN_IMX6UL_TSC + tristate Freescale i.MX6UL touchscreen controller + depends on OF + help + Say Y here if you have a Freescale i.MX6UL, and want to + use the internal touchscreen controller. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + moduel will be called imx6ul_tsc. + config TOUCHSCREEN_INEXIO tristate iNexio serial touchscreens select SERIO diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile index c85aae2..9379b32 100644 --- a/drivers/input/touchscreen/Makefile +++ b/drivers/input/touchscreen/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_TOUCHSCREEN_EGALAX)+= egalax_ts.o obj-$(CONFIG_TOUCHSCREEN_FUJITSU)+= fujitsu_ts.o obj-$(CONFIG_TOUCHSCREEN_GOODIX) += goodix.o obj-$(CONFIG_TOUCHSCREEN_ILI210X)+= ili210x.o +obj-$(CONFIG_TOUCHSCREEN_IMX6UL_TSC) += imx6ul_tsc.o obj-$(CONFIG_TOUCHSCREEN_INEXIO) += inexio.o obj-$(CONFIG_TOUCHSCREEN_INTEL_MID) += intel-mid-touch.o obj-$(CONFIG_TOUCHSCREEN_IPROC) += bcm_iproc_tsc.o diff --git a/drivers/input/touchscreen/imx6ul_tsc.c b/drivers/input/touchscreen/imx6ul_tsc.c new file mode 100644 index 000..807f1db --- /dev/null +++ b/drivers/input/touchscreen/imx6ul_tsc.c @@ -0,0 +1,504 @@ +/* + * Freescale i.MX6UL touchscreen controller driver + * + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include linux/errno.h +#include linux/kernel.h +#include linux/module.h +#include linux/gpio.h +#include linux/input.h +#include linux/slab.h +#include linux/completion.h +#include linux/delay.h +#include linux/of.h +#include linux/of_device.h +#include linux/of_gpio.h +#include linux/of_irq.h I do not think you need of_irq and of_device. +#include linux/interrupt.h +#include linux/platform_device.h +#include linux/clk.h +#include linux/io.h + +/* ADC configuration registers field define */ +#define ADC_AIEN (0x1 7) +#define ADC_CONV_DISABLE 0x1F +#define ADC_CAL (0x1 7) +#define ADC_CALF 0x2 +#define ADC_12BIT_MODE (0x2 2) +#define ADC_IPG_CLK 0x00 +#define ADC_CLK_DIV_8(0x03 5) +#define ADC_SHORT_SAMPLE_MODE(0x0 4) +#define ADC_HARDWARE_TRIGGER (0x1 13) +#define SELECT_CHANNEL_4 0x04 +#define SELECT_CHANNEL_1 0x01 +#define DISABLE_CONVERSION_INT (0x0 7) + +/* ADC registers */ +#define REG_ADC_HC0 0x00 +#define REG_ADC_HC1 0x04 +#define REG_ADC_HC2 0x08 +#define REG_ADC_HC3 0x0C +#define REG_ADC_HC4 0x10 +#define REG_ADC_HS 0x14 +#define REG_ADC_R0 0x18 +#define REG_ADC_CFG 0x2C +#define REG_ADC_GC 0x30 +#define REG_ADC_GS 0x34 + +#define ADC_TIMEOUT msecs_to_jiffies(100) + +/* TSC registers */ +#define REG_TSC_BASIC_SETING 0x00 +#define REG_TSC_PRE_CHARGE_TIME 0x10 +#define REG_TSC_FLOW_CONTROL 0x20 +#define REG_TSC_MEASURE_VALUE0x30 +#define REG_TSC_INT_EN 0x40 +#define REG_TSC_INT_SIG_EN 0x50 +#define REG_TSC_INT_STATUS 0x60 +#define REG_TSC_DEBUG_MODE 0x70 +#define REG_TSC_DEBUG_MODE2 0x80 + +/* TSC configuration registers field define */ +#define DETECT_4_WIRE_MODE (0x0 4) +#define AUTO_MEASURE 0x1 +#define MEASURE_SIGNAL 0x1 +#define DETECT_SIGNAL(0x1 4) +#define VALID_SIGNAL (0x1 8) +#define MEASURE_INT_EN 0x1 +#define MEASURE_SIG_EN 0x1 +#define VALID_SIG_EN (0x1 8) +#define DE_GLITCH_2 (0x2 29) +#define START_SENSE (0x1 12) +#define TSC_DISABLE (0x1 16) +#define DETECT_MODE 0x2 +
[PATCH] ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes
This SoC is integrated with 4 Cortex-A9 cores. The GIC bindings
says that the bits[15:8] of the 3rd cell of the interrupts property
represents PPI interrupt CPU mask. Because the timer interrupts are
wired to all of the 4 cores, bits[15:8] should be set to 0xf.
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---
arch/arm/boot/dts/uniphier-proxstream2.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/uniphier-proxstream2.dtsi
b/arch/arm/boot/dts/uniphier-proxstream2.dtsi
index ccf795a..4c7b246 100644
--- a/arch/arm/boot/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/boot/dts/uniphier-proxstream2.dtsi
@@ -249,14 +249,14 @@
timer@6200 {
compatible = arm,cortex-a9-global-timer;
reg = 0x6200 0x20;
- interrupts = 1 11 0x304;
+ interrupts = 1 11 0xf04;
clocks = arm_timer_clk;
};
timer@6600 {
compatible = arm,cortex-a9-twd-timer;
reg = 0x6600 0x20;
- interrupts = 1 13 0x304;
+ interrupts = 1 13 0xf04;
clocks = arm_timer_clk;
};
--
1.9.1
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[PATCH v2] ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes
This SoC is integrated with 4 Cortex-A9 cores. The GIC bindings
document says that the bits[15:8] of the 3rd cell of the interrupts
property represents PPI interrupt CPU mask. Because the timer
interrupts are wired to all of the 4 cores, bits[15:8] should be set
to 0xf.
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---
Changes in v2:
- Fix git-description
arch/arm/boot/dts/uniphier-proxstream2.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/uniphier-proxstream2.dtsi
b/arch/arm/boot/dts/uniphier-proxstream2.dtsi
index ccf795a..4c7b246 100644
--- a/arch/arm/boot/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/boot/dts/uniphier-proxstream2.dtsi
@@ -249,14 +249,14 @@
timer@6200 {
compatible = arm,cortex-a9-global-timer;
reg = 0x6200 0x20;
- interrupts = 1 11 0x304;
+ interrupts = 1 11 0xf04;
clocks = arm_timer_clk;
};
timer@6600 {
compatible = arm,cortex-a9-twd-timer;
reg = 0x6600 0x20;
- interrupts = 1 13 0x304;
+ interrupts = 1 13 0xf04;
clocks = arm_timer_clk;
};
--
1.9.1
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Re: [PATCH] ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes
2015-08-19 14:45 GMT+09:00 Masahiro Yamada yamada.masah...@socionext.com: This SoC is integrated with 4 Cortex-A9 cores. The GIC bindings says that the bits[15:8] of the 3rd cell of the interrupts property represents PPI interrupt CPU mask. Because the timer interrupts are wired to all of the 4 cores, bits[15:8] should be set to 0xf. Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com This has been superseded by v2. -- Best Regards Masahiro Yamada -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 2/3] cpufreq: mediatek: Add MT8173 cpufreq driver
On 19-08-15, 10:05, Pi-Cheng Chen wrote: Mediatek MT8173 is an ARMv8 based quad-core (2*Cortex-A53 and 2*Cortex-A72) SoC with duall clusters. For each cluster, two voltage inputs, Vproc and Vsram are supplied by two regulators. For the big cluster, two regulators come from different PMICs. In this case, when scaling voltage inputs of the cluster, the voltages of two regulator inputs need to be controlled by software explicitly under the SoC specific limitation: 100mV Vsram - Vproc 200mV which is called 'voltage tracking' mechanism. And when scaling the frequency of cluster clock input, the input MUX need to be parented to another intermediate stable PLL first and reparented to the original PLL once the original PLL is stable at the target frequency. This patch implements those mechanisms to enable CPU DVFS support for Mediatek MT8173 SoC. Signed-off-by: Pi-Cheng Chen pi-cheng.c...@linaro.org Acked-by: Viresh Kumar viresh.ku...@linaro.org --- Changes in v7: - add of_machine_is_compatible() check to be multiplatform friendly Looks fine, thanks. -- viresh -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/5] Documentation: Detail permitted DT properties for the imx6ul_tsc
Hi,
On Tue, Jul 28, 2015 at 05:58:38PM +0800, Haibo Chen wrote:
Here we apply required documentation for the imx6ul touch screen
controller driver which describe available properties and how to
use them.
Signed-off-by: Haibo Chen haibo.c...@freescale.com
---
.../bindings/input/touchscreen/imx6ul_tsc.txt | 36
++
1 file changed, 36 insertions(+)
create mode 100644
Documentation/devicetree/bindings/input/touchscreen/imx6ul_tsc.txt
diff --git
a/Documentation/devicetree/bindings/input/touchscreen/imx6ul_tsc.txt
b/Documentation/devicetree/bindings/input/touchscreen/imx6ul_tsc.txt
new file mode 100644
index 000..ac41c32
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/touchscreen/imx6ul_tsc.txt
@@ -0,0 +1,36 @@
+* Freescale i.MX6UL Touch Controller
+
+Required properties:
+- compatible: must be fsl,imx6ul-tsc.
+- reg: this touch controller address and the ADC2 address.
This suggests that this driver is using a unit ADC2. Which also means
that there are more than one ADC which are probably identical?
Shouldn't these ADCs be properly described by their own device nodes
instead of these two register ranges, two interrupts and two clocks?
Is 'ADC2' usable without tsc? Then ADC1/ADC2 should perhaps get a proper
IIO driver.
Unfortunately I don't have the reference manual to have a look how this
all works.
Best regards,
Markus
+- interrupts: the interrupt of this touch controller and ADC2.
+- clocks: the root clock of touch controller and ADC2.
+- clock-names; must be tsc and adc.
+- xnur-gpio: the X- gpio this controller connect to.
+ This xnur-gpio returns to high once the finger leave the touch screen (The
+ last touch event the touch controller capture).
+
+Optional properties:
+- measure-delay-time: the value of measure delay time.
+ Before X-axis or Y-axis measurement, the screen need some time before
+ even potential distribution ready.
+ This value depends on the touch screen.
+- pre-charge-time: the touch screen need some time to precharge.
+ This value depends on the touch screen.
+
+Example:
+ tsc: tsc@0204 {
+ compatible = fsl,imx6ul-tsc;
+ reg = 0x0204 0x4000, 0x0219c000 0x4000;
+ interrupts = GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH,
+ GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH;
+ clocks = clks IMX6UL_CLK_IPG,
+ clks IMX6UL_CLK_ADC2;
+ clock-names = tsc, adc;
+ pinctrl-names = default;
+ pinctrl-0 = pinctrl_tsc;
+ xnur-gpio = gpio1 3 GPIO_ACTIVE_HIGH;
+ measure-delay-time = 0xfff;
+ pre-charge-time = 0x;
+ status = okay;
+ };
--
1.9.1
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Re: [PATCH v3 2/2] devicetree: Add documentation for UPISEMI us5182d ALS and Proximity sensor
Thank you Jonathan, I'll add a new patch set soon, added some comments
inline also.
Adriana
On 15.08.2015 17:31, Jonathan Cameron wrote:
On 14/08/15 10:29, Adriana Reus wrote:
Added entries in trivial-devices and i2c/vendor-prefixes for
the us5182d als and proximity sensor. Also added a documentation file for
this sensor's properties.
Signed-off-by: Adriana Reus adriana.r...@intel.com
It's not a trivial device if it has it's own docs. So don't add it to that list
(the point is to not have separate docs for devices that don't really have
any device tree data other than where they are.
right, I'll add a new path set soon.
Few more bits inline.
---
No changes - resending because I forgot to cc devicetree.
.../devicetree/bindings/i2c/trivial-devices.txt| 1 +
.../devicetree/bindings/iio/light/us5182d.txt | 24 ++
.../devicetree/bindings/vendor-prefixes.txt| 1 +
3 files changed, 26 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/light/us5182d.txt
diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt
b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
index 00f8652..96d3b9c 100644
--- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt
+++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
@@ -99,4 +99,5 @@ ti,tsc2003I2C Touch-Screen Controller
ti,tmp102 Low Power Digital Temperature Sensor with SMBUS/Two
Wire Serial Interface
ti,tmp103 Low Power Digital Temperature Sensor with SMBUS/Two
Wire Serial Interface
ti,tmp275 Digital Temperature Sensor
+upisemi,usd5182Als and Proximity Sensor
winbond,wpct301 i2c trusted platform module (TPM)
diff --git a/Documentation/devicetree/bindings/iio/light/us5182d.txt
b/Documentation/devicetree/bindings/iio/light/us5182d.txt
new file mode 100644
index 000..9ac3336
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/light/us5182d.txt
@@ -0,0 +1,24 @@
+* UPISEMI us5182d I2C ALS and Proximity sensor
+
+Required properties:
+- compatible: must be upisemi,usd5182
+- reg: the I2C address of the device
+
+Optional properties:
+- upisemi,glass-coef: glass attenuation factor
+- upisemi,dark-ths: array of thresholds corresponding to every scale
That needs more detail. I've read the driver and I am not sure what exactly
you mean! Why should a scale have a threshold?
I'll try to be more specific. These are values representing adc counts,
that's why there are different values corresponding to every scale.
+- upisemi,upper-dark-gain: tuning factor applied when light th
+- upisemi,lower-dark-gain: tuning factor applied when light th
+
+Example:
+
+usd5182@39 {
+compatible = upisemi,usd5182;
+reg = 0x39;
+upisemi,glass-coef = 1000 ;
+upisemi,dark-ths = /bits/ 16 170 200 512 512 800 2000 4000
8000;
+upisemi,upper-dark-gain = /bits/ 8 0x00;
+upisemi,lower-dark-gain = /bits/ 8 0x16;
Not sure why these are in hex.. Or why we care if they are 8 bits. If there is
a limit
on the possible values, perhaps mention it in the docs above.
I should have been (much) more specific here: that represents a float
number with 4 integer bits and 4 fractional bits (Q4.4), so I find hex
more intuitive since it's split in half, let me know if you think
otherwise. I'll add a more complete description. As for the /bits/ x
it's because currently in the driver I use the read_property_u8 or *_u16
functions, these require that the dts entry be as I wrote it in the
example, and since it's an example it should be functional, so I feel
that is ok as it is.
+};
+
One blank line at the end is neough.
+
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index d444757..5b40bab 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -211,6 +211,7 @@ toshiba Toshiba Corporation
toumazToumaz
tplinkTP-LINK Technologies Co., Ltd.
truly Truly Semiconductors Limited
+upisemiuPI Semiconductor Corp.
usi Universal Scientific Industrial Co., Ltd.
v3V3 Semiconductor
variscite Variscite Ltd.
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[RFC PATCH 5/7] DMA: tegra-apb: Move common code into separate source files
Move code that is common between the Tegra20-APB DMA and Tegra210 ADMA
driver into separate source files.
Signed-off-by: Jon Hunter jonath...@nvidia.com
---
drivers/dma/Kconfig | 4 +
drivers/dma/Makefile | 1 +
drivers/dma/tegra-common.c| 733 ++
drivers/dma/tegra-common.h| 226 +++
drivers/dma/tegra20-apb-dma.c | 910 +-
5 files changed, 972 insertions(+), 902 deletions(-)
create mode 100644 drivers/dma/tegra-common.c
create mode 100644 drivers/dma/tegra-common.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index ff50af3f1bb0..dd79b0bf0876 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -189,10 +189,14 @@ config TXX9_DMAC
Support the TXx9 SoC internal DMA controller. This can be
integrated in chips such as the Toshiba TX4927/38/39.
+config TEGRA_DMA_COMMON
+ bool
+
config TEGRA20_APB_DMA
bool NVIDIA Tegra20 APB DMA support
depends on ARCH_TEGRA
select DMA_ENGINE
+ select TEGRA_DMA_COMMON
help
Support for the NVIDIA Tegra20 APB DMA controller driver. The
DMA controller is having multiple DMA channel which can be
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 264eb3c52446..d9c2bf5ef0bd 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_SIRF_DMA) += sirf-dma.o
obj-$(CONFIG_TI_EDMA) += edma.o
obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o
+obj-$(CONFIG_TEGRA_DMA_COMMON) += tegra-common.o
obj-$(CONFIG_S3C24XX_DMAC) += s3c24xx-dma.o
obj-$(CONFIG_PL330_DMA) += pl330.o
obj-$(CONFIG_PCH_DMA) += pch_dma.o
diff --git a/drivers/dma/tegra-common.c b/drivers/dma/tegra-common.c
new file mode 100644
index ..fff0a143f5bb
--- /dev/null
+++ b/drivers/dma/tegra-common.c
@@ -0,0 +1,733 @@
+/*
+ * Helper functions for NVIDIA DMA drivers.
+ *
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include linux/delay.h
+#include linux/dmaengine.h
+#include linux/interrupt.h
+#include linux/pm_runtime.h
+#include linux/slab.h
+
+#include dmaengine.h
+#include tegra-common.h
+
+static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *txd)
+{
+ struct tegra_dma_desc *dma_desc = txd_to_tegra_dma_desc(txd);
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(txd-chan);
+ unsigned long flags;
+ dma_cookie_t cookie;
+
+ spin_lock_irqsave(tdc-lock, flags);
+ dma_desc-dma_status = DMA_IN_PROGRESS;
+ cookie = dma_cookie_assign(dma_desc-txd);
+ list_splice_tail_init(dma_desc-tx_list, tdc-pending_sg_req);
+ spin_unlock_irqrestore(tdc-lock, flags);
+ return cookie;
+}
+
+/* Get DMA desc from free list, if not there then allocate it. */
+static struct tegra_dma_desc *tegra_dma_desc_get(struct tegra_dma_channel *tdc)
+{
+ struct tegra_dma_desc *dma_desc;
+ unsigned long flags;
+
+ spin_lock_irqsave(tdc-lock, flags);
+
+ /* Do not allocate if desc are waiting for ack */
+ list_for_each_entry(dma_desc, tdc-free_dma_desc, node) {
+ if (async_tx_test_ack(dma_desc-txd)) {
+ list_del(dma_desc-node);
+ spin_unlock_irqrestore(tdc-lock, flags);
+ dma_desc-txd.flags = 0;
+ return dma_desc;
+ }
+ }
+
+ spin_unlock_irqrestore(tdc-lock, flags);
+
+ /* Allocate DMA desc */
+ dma_desc = kzalloc(sizeof(*dma_desc), GFP_ATOMIC);
+ if (!dma_desc)
+ return NULL;
+
+ dma_async_tx_descriptor_init(dma_desc-txd, tdc-dma_chan);
+ dma_desc-txd.tx_submit = tegra_dma_tx_submit;
+ dma_desc-txd.flags = 0;
+ return dma_desc;
+}
+
+static void tegra_dma_desc_put(struct tegra_dma_channel *tdc,
+ struct tegra_dma_desc *dma_desc)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(tdc-lock, flags);
+ if (!list_empty(dma_desc-tx_list))
+ list_splice_init(dma_desc-tx_list, tdc-free_sg_req);
+ list_add_tail(dma_desc-node, tdc-free_dma_desc);
+ spin_unlock_irqrestore(tdc-lock, flags);
+}
+
+static struct tegra_dma_sg_req *tegra_dma_sg_req_get(
+ struct tegra_dma_channel *tdc)
+{
+ struct tegra_dma_sg_req *sg_req = NULL;
+ unsigned long flags;
+
+
[RFC PATCH 4/7] DMA: tegra-apb: Add a function table for functions dealing with registers
In preparation for adding the Tegra210 ADMA driver, add a function table
for calling functions that access hardware registers. This way code that
is common between the Tegra20-APB DMA and Tegra210 DMA driver can be moved
into a separate source file and used by both DMA drivers.
Note that all function pointers in the table are compulsory and so no
checking that the function pointer is valid is performed.
Signed-off-by: Jon Hunter jonath...@nvidia.com
---
drivers/dma/tegra20-apb-dma.c | 92 +--
1 file changed, 71 insertions(+), 21 deletions(-)
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index c1eb25075756..7947acdf23db 100644
--- a/drivers/dma/tegra20-apb-dma.c
+++ b/drivers/dma/tegra20-apb-dma.c
@@ -209,6 +209,33 @@ struct tegra_dma_channel {
struct tegra_dma_channel_regs channel_reg;
};
+struct tegra_dma_ops {
+ u32 (*get_xfer_count)(struct tegra_dma_channel *tdc);
+ int (*get_xfer_params_cyclic)(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req,
+ enum dma_transfer_direction direction,
+ unsigned int flags);
+ int (*get_xfer_params_sg)(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req,
+ enum dma_transfer_direction direction,
+ unsigned int flags);
+ u32 (*irq_clear)(struct tegra_dma_channel *tdc);
+ u32 (*irq_status)(struct tegra_dma_channel *tdc);
+ void (*pause)(struct tegra_dma_channel *tdc,
+ bool wait_for_burst_complete);
+ void (*program)(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req);
+ void (*resume)(struct tegra_dma_channel *tdc);
+ void (*set_xfer_params)(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req,
+ struct tegra_dma_sg_req *sg_base,
+ enum dma_transfer_direction direction,
+ u32 mem, u32 len);
+ void (*start)(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req);
+ void (*stop)(struct tegra_dma_channel *tdc);
+};
+
/* tegra_dma: Tegra DMA specific information */
struct tegra_dma {
struct dma_device dma_dev;
@@ -218,6 +245,7 @@ struct tegra_dma {
spinlock_t global_lock;
void __iomem*base_addr;
const struct tegra_dma_chip_data *chip_data;
+ const struct tegra_dma_ops *ops;
/*
* Counter for managing global pausing of the DMA controller.
@@ -504,6 +532,7 @@ static void tegra_dma_start(struct tegra_dma_channel *tdc,
static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
struct tegra_dma_sg_req *nsg_req)
{
+ const struct tegra_dma_ops *ops = tdc-tdma-ops;
unsigned long status;
/*
@@ -517,8 +546,8 @@ static void tegra_dma_configure_for_next(struct
tegra_dma_channel *tdc,
* If there is already IEC status then interrupt handler need to
* load new configuration.
*/
- tegra_dma_pause(tdc, false);
- status = tegra_dma_irq_status(tdc);
+ ops-pause(tdc, false);
+ status = ops-irq_status(tdc);
/*
* If interrupt is pending then do nothing as the ISR will handle
@@ -527,17 +556,18 @@ static void tegra_dma_configure_for_next(struct
tegra_dma_channel *tdc,
if (status) {
dev_err(tdc2dev(tdc),
Skipping new configuration as interrupt is pending\n);
- tegra_dma_resume(tdc);
+ ops-resume(tdc);
return;
}
/* Safe to program new configuration */
- tegra_dma_program(tdc, nsg_req);
- tegra_dma_resume(tdc);
+ ops-program(tdc, nsg_req);
+ ops-resume(tdc);
}
static void tdc_start_head_req(struct tegra_dma_channel *tdc)
{
+ const struct tegra_dma_ops *ops = tdc-tdma-ops;
struct tegra_dma_sg_req *sg_req;
if (list_empty(tdc-pending_sg_req))
@@ -545,7 +575,7 @@ static void tdc_start_head_req(struct tegra_dma_channel
*tdc)
sg_req = list_first_entry(tdc-pending_sg_req,
typeof(*sg_req), node);
- tegra_dma_start(tdc, sg_req);
+ ops-start(tdc, sg_req);
sg_req-configured = true;
tdc-busy = true;
}
@@ -599,11 +629,12 @@ static void tegra_dma_abort_all(struct tegra_dma_channel
*tdc)
static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
struct tegra_dma_sg_req *last_sg_req, bool to_terminate)
{
+ const struct tegra_dma_ops *ops = tdc-tdma-ops;
struct tegra_dma_sg_req *hsgreq = NULL;
[RFC PATCH 1/7] DMA: tegra-apb: Correct runtime-pm usage
The tegra-apb DMA driver enables runtime-pm but never calls
pm_runtime_get/put and hence the runtime-pm callbacks are never invoked.
The driver manages the clocks by directly calling clk_prepare_enable()
and clk_unprepare_disable().
Fix this by replacing the clk_prepare_enable() and clk_disable_unprepare()
with pm_runtime_get_sync() and pm_runtime_put(), respectively. Note that
the consequence of this is that if runtime-pm is disabled, then the clocks
will remain on the entire time the driver is loaded. However, if
runtime-pm is disabled, then power is not most likely not a concern.
Signed-off-by: Jon Hunter jonath...@nvidia.com
---
drivers/dma/tegra20-apb-dma.c | 36
1 file changed, 12 insertions(+), 24 deletions(-)
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index c8f79dcaaee8..097432ea89fa 100644
--- a/drivers/dma/tegra20-apb-dma.c
+++ b/drivers/dma/tegra20-apb-dma.c
@@ -1182,14 +1182,11 @@ static int tegra_dma_alloc_chan_resources(struct
dma_chan *dc)
{
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
struct tegra_dma *tdma = tdc-tdma;
- int ret;
dma_cookie_init(tdc-dma_chan);
tdc-config_init = false;
- ret = clk_prepare_enable(tdma-dma_clk);
- if (ret 0)
- dev_err(tdc2dev(tdc), clk_prepare_enable failed: %d\n, ret);
- return ret;
+
+ return pm_runtime_get_sync(tdma-dev);
}
static void tegra_dma_free_chan_resources(struct dma_chan *dc)
@@ -1232,7 +1229,7 @@ static void tegra_dma_free_chan_resources(struct dma_chan
*dc)
list_del(sg_req-node);
kfree(sg_req);
}
- clk_disable_unprepare(tdma-dma_clk);
+ pm_runtime_put(tdma-dev);
tdc-slave_id = 0;
}
@@ -1356,21 +1353,13 @@ static int tegra_dma_probe(struct platform_device *pdev)
spin_lock_init(tdma-global_lock);
pm_runtime_enable(pdev-dev);
- if (!pm_runtime_enabled(pdev-dev)) {
+ if (!pm_runtime_enabled(pdev-dev))
ret = tegra_dma_runtime_resume(pdev-dev);
- if (ret) {
- dev_err(pdev-dev, dma_runtime_resume failed %d\n,
- ret);
- goto err_pm_disable;
- }
- }
+ else
+ ret = pm_runtime_get_sync(pdev-dev);
- /* Enable clock before accessing registers */
- ret = clk_prepare_enable(tdma-dma_clk);
- if (ret 0) {
- dev_err(pdev-dev, clk_prepare_enable failed: %d\n, ret);
+ if (ret)
goto err_pm_disable;
- }
/* Reset DMA controller */
reset_control_assert(tdma-rst);
@@ -1382,7 +1371,7 @@ static int tegra_dma_probe(struct platform_device *pdev)
tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xul);
- clk_disable_unprepare(tdma-dma_clk);
+ pm_runtime_put(pdev-dev);
INIT_LIST_HEAD(tdma-dma_dev.channels);
for (i = 0; i cdata-nr_channels; i++) {
@@ -1484,7 +1473,6 @@ err_irq:
struct tegra_dma_channel *tdc = tdma-channels[i];
tasklet_kill(tdc-tasklet);
}
-
err_pm_disable:
pm_runtime_disable(pdev-dev);
if (!pm_runtime_status_suspended(pdev-dev))
@@ -1543,7 +1531,7 @@ static int tegra_dma_pm_suspend(struct device *dev)
int ret;
/* Enable clock before accessing register */
- ret = tegra_dma_runtime_resume(dev);
+ ret = pm_runtime_get_sync(dev);
if (ret 0)
return ret;
@@ -1560,7 +1548,7 @@ static int tegra_dma_pm_suspend(struct device *dev)
}
/* Disable clock */
- tegra_dma_runtime_suspend(dev);
+ pm_runtime_put(dev);
return 0;
}
@@ -1571,7 +1559,7 @@ static int tegra_dma_pm_resume(struct device *dev)
int ret;
/* Enable clock before accessing register */
- ret = tegra_dma_runtime_resume(dev);
+ ret = pm_runtime_get_sync(dev);
if (ret 0)
return ret;
@@ -1592,7 +1580,7 @@ static int tegra_dma_pm_resume(struct device *dev)
}
/* Disable clock */
- tegra_dma_runtime_suspend(dev);
+ pm_runtime_put(dev);
return 0;
}
#endif
--
2.1.4
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[RFC PATCH 2/7] DMA: tegra-apb: Move code dealing with h/w registers into separate functions
In preparation for adding the Tegra210 ADMA driver, that is based upon the
Tegra20-APB DMA driver, move code that accesses hardware registers into
specific functions. The Tegra210 ADMA and Tegra20-APB DMA drivers are not
compatible from a hardware register perspective, but the drivers are very
much the same. Hence, by isolating code that deals with the hardware
registers it will then be possible to add a function table to call code
that accesses the hardware registers and re-use the common driver code
for both DMAs.
Signed-off-by: Jon Hunter jonath...@nvidia.com
---
drivers/dma/tegra20-apb-dma.c | 277 ++
1 file changed, 170 insertions(+), 107 deletions(-)
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index 097432ea89fa..e552a4efef71 100644
--- a/drivers/dma/tegra20-apb-dma.c
+++ b/drivers/dma/tegra20-apb-dma.c
@@ -359,6 +359,18 @@ static int tegra_dma_slave_config(struct dma_chan *dc,
return 0;
}
+static u32 tegra_dma_get_xfer_count(struct tegra_dma_channel *tdc)
+{
+ u32 wcount;
+
+ if (tdc-tdma-chip_data-support_separate_wcount_reg)
+ wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER);
+ else
+ wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
+
+ return (wcount TEGRA_APBDMA_STATUS_COUNT_MASK) - 4;
+}
+
static void tegra_dma_global_pause(struct tegra_dma_channel *tdc,
bool wait_for_burst_complete)
{
@@ -394,6 +406,38 @@ out:
spin_unlock(tdma-global_lock);
}
+static u32 tegra_dma_irq_status(struct tegra_dma_channel *tdc)
+{
+ u32 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
+
+ return status TEGRA_APBDMA_STATUS_ISE_EOC;
+}
+
+static u32 tegra_dma_irq_clear(struct tegra_dma_channel *tdc)
+{
+ u32 status = tegra_dma_irq_status(tdc);
+
+ if (status) {
+ dev_dbg(tdc2dev(tdc), %s():clearing interrupt\n, __func__);
+ tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
+ }
+
+ return status;
+}
+
+static void tegra_dma_program(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *nsg_req)
+{
+ tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req-ch_regs.apb_ptr);
+ tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req-ch_regs.ahb_ptr);
+ if (tdc-tdma-chip_data-support_separate_wcount_reg)
+ tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT,
+ nsg_req-ch_regs.wcount);
+ tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
+ nsg_req-ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
+ nsg_req-configured = true;
+}
+
static void tegra_dma_pause(struct tegra_dma_channel *tdc,
bool wait_for_burst_complete)
{
@@ -423,7 +467,6 @@ static void tegra_dma_resume(struct tegra_dma_channel *tdc)
static void tegra_dma_stop(struct tegra_dma_channel *tdc)
{
u32 csr;
- u32 status;
/* Disable interrupts */
csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
@@ -435,11 +478,8 @@ static void tegra_dma_stop(struct tegra_dma_channel *tdc)
tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
/* Clear interrupt status if it is there */
- status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
- if (status TEGRA_APBDMA_STATUS_ISE_EOC) {
- dev_dbg(tdc2dev(tdc), %s():clearing interrupt\n, __func__);
- tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
- }
+ tegra_dma_irq_clear(tdc);
+
tdc-busy = false;
}
@@ -478,13 +518,13 @@ static void tegra_dma_configure_for_next(struct
tegra_dma_channel *tdc,
* load new configuration.
*/
tegra_dma_pause(tdc, false);
- status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
+ status = tegra_dma_irq_status(tdc);
/*
* If interrupt is pending then do nothing as the ISR will handle
* the programing for new request.
*/
- if (status TEGRA_APBDMA_STATUS_ISE_EOC) {
+ if (status) {
dev_err(tdc2dev(tdc),
Skipping new configuration as interrupt is pending\n);
tegra_dma_resume(tdc);
@@ -492,15 +532,7 @@ static void tegra_dma_configure_for_next(struct
tegra_dma_channel *tdc,
}
/* Safe to program new configuration */
- tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req-ch_regs.apb_ptr);
- tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req-ch_regs.ahb_ptr);
- if (tdc-tdma-chip_data-support_separate_wcount_reg)
- tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT,
- nsg_req-ch_regs.wcount);
- tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
- nsg_req-ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
- nsg_req-configured = true;
-
+ tegra_dma_program(tdc, nsg_req);
tegra_dma_resume(tdc);
}
@@ -534,10 +566,10 @@ static void tdc_configure_next_head_desc(struct
[RFC PATCH 3/7] DMA: tegra-apb: Clean-up and simplify setting up of transfer parameters
Most of the DMA transfer parameters that are configured for scatter-gather
or cyclic transfers are the same. Therefore, move the setup of common
parameters into the tegra_dma_get_xfer_params() function used for both
scatter-gather and cyclic transfers.
Note that TEGRA_APBDMA_AHBSEQ_WRAP_NONE is defined as 0 and so this setting
can be completely removed.
Signed-off-by: Jon Hunter jonath...@nvidia.com
---
drivers/dma/tegra20-apb-dma.c | 53 ---
1 file changed, 19 insertions(+), 34 deletions(-)
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index e552a4efef71..c1eb25075756 100644
--- a/drivers/dma/tegra20-apb-dma.c
+++ b/drivers/dma/tegra20-apb-dma.c
@@ -940,7 +940,8 @@ static inline int get_burst_size(struct tegra_dma_channel
*tdc,
static int tegra_dma_get_xfer_params(struct tegra_dma_channel *tdc,
struct tegra_dma_channel_regs *ch_regs,
-enum dma_transfer_direction direction)
+enum dma_transfer_direction direction,
+unsigned int flags)
{
switch (direction) {
case DMA_MEM_TO_DEV:
@@ -948,48 +949,32 @@ static int tegra_dma_get_xfer_params(struct
tegra_dma_channel *tdc,
ch_regs-apb_seq = get_bus_width(tdc,
tdc-dma_sconfig.dst_addr_width);
ch_regs-csr = TEGRA_APBDMA_CSR_DIR;
- return 0;
+ break;
case DMA_DEV_TO_MEM:
ch_regs-apb_ptr = tdc-dma_sconfig.src_addr;
ch_regs-apb_seq = get_bus_width(tdc,
tdc-dma_sconfig.src_addr_width);
ch_regs-csr = 0;
- return 0;
+ break;
default:
dev_err(tdc2dev(tdc), Dma direction is not supported\n);
return -EINVAL;
}
- return -EINVAL;
-}
-
-static int tegra_dma_get_xfer_params_sg(struct tegra_dma_channel *tdc,
- struct tegra_dma_sg_req *sg_req,
- enum dma_transfer_direction direction,
- unsigned int flags)
-{
- struct tegra_dma_channel_regs *ch_regs = sg_req-ch_regs;
- int ret;
-
- ret = tegra_dma_get_xfer_params(tdc, ch_regs, direction);
- if (ret 0)
- return ret;
+ ch_regs-apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
ch_regs-ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
- ch_regs-ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE
- TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
ch_regs-ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
- ch_regs-csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW;
+ ch_regs-csr |= TEGRA_APBDMA_CSR_FLOW;
ch_regs-csr |= tdc-slave_id TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
+
if (flags DMA_PREP_INTERRUPT)
ch_regs-csr |= TEGRA_APBDMA_CSR_IE_EOC;
- ch_regs-apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
-
return 0;
}
-static int tegra_dma_get_xfer_params_cyclic(struct tegra_dma_channel *tdc,
+static int tegra_dma_get_xfer_params_sg(struct tegra_dma_channel *tdc,
struct tegra_dma_sg_req *sg_req,
enum dma_transfer_direction direction,
unsigned int flags)
@@ -997,23 +982,23 @@ static int tegra_dma_get_xfer_params_cyclic(struct
tegra_dma_channel *tdc,
struct tegra_dma_channel_regs *ch_regs = sg_req-ch_regs;
int ret;
- ret = tegra_dma_get_xfer_params(tdc, ch_regs, direction);
+ ret = tegra_dma_get_xfer_params(tdc, ch_regs, direction, flags);
if (ret 0)
return ret;
- ch_regs-ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
- ch_regs-ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE
- TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
- ch_regs-ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
+ ch_regs-csr |= TEGRA_APBDMA_CSR_ONCE;
- ch_regs-csr |= TEGRA_APBDMA_CSR_FLOW;
- if (flags DMA_PREP_INTERRUPT)
- ch_regs-csr |= TEGRA_APBDMA_CSR_IE_EOC;
- ch_regs-csr |= tdc-slave_id TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
+ return 0;
+}
- ch_regs-apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
+static int tegra_dma_get_xfer_params_cyclic(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req,
+ enum dma_transfer_direction direction,
+ unsigned int flags)
+{
+ struct tegra_dma_channel_regs *ch_regs = sg_req-ch_regs;
- return 0;
+ return tegra_dma_get_xfer_params(tdc, ch_regs, direction, flags);
}
static void tegra_dma_prep_wcount(struct
[RFC PATCH 6/7] Documentation: DT: Add binding documentation for NVIDIA ADMA
Add device-tree binding documentation for the Tegra210 Audio DMA
controller.
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Ian Campbell ijc+devicet...@hellion.org.uk
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Jon Hunter jonath...@nvidia.com
---
.../devicetree/bindings/dma/tegra210-adma.txt | 49 ++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/tegra210-adma.txt
diff --git a/Documentation/devicetree/bindings/dma/tegra210-adma.txt
b/Documentation/devicetree/bindings/dma/tegra210-adma.txt
new file mode 100644
index ..38310d7e7e77
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/tegra210-adma.txt
@@ -0,0 +1,49 @@
+* NVIDIA Tegra Audio DMA controller
+
+Required properties:
+- compatible: Should be nvidia,chip-adma
+- reg: Should contain DMA registers location and length. This should include
+ all of the per-channel registers.
+- interrupt-parent: Phandle to the interrupt parent controller.
+- interrupts: Should contain all of the per-channel DMA interrupts.
+- clocks: Must contain two entries, one for the power-domain clock and one
+ for the module clock.
+ See ../clocks/clock-bindings.txt for details.
+- #dma-cells : Must be 1. This dictates the length of DMA specifiers in
+ client nodes' dmas properties. The specifier represents the DMA request
+ select value for the peripheral. For more details, consult the Tegra TRM's
+ documentation of the APB DMA channel control register REQ_SEL field.
+
+Examples:
+
+adma: adma@702e2000 {
+ compatible = nvidia,tegra210-adma;
+ reg = 0x0 0x702e2000 0x0 0x2000;
+ interrupt-parent = tegra_agic;
+ interrupts = GIC_SPI INT_ADMA_EOT0 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI INT_ADMA_EOT1 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI INT_ADMA_EOT2 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI INT_ADMA_EOT3 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI INT_ADMA_EOT4 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI INT_ADMA_EOT5 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI INT_ADMA_EOT6 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI INT_ADMA_EOT7 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI INT_ADMA_EOT8 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI INT_ADMA_EOT9 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI INT_ADMA_EOT10 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI INT_ADMA_EOT11 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI INT_ADMA_EOT12 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI INT_ADMA_EOT13 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI INT_ADMA_EOT14 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI INT_ADMA_EOT15 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI INT_ADMA_EOT16 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI INT_ADMA_EOT17 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI INT_ADMA_EOT18 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI INT_ADMA_EOT19 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI INT_ADMA_EOT20 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI INT_ADMA_EOT21 IRQ_TYPE_LEVEL_HIGH;
+ clocks = tegra_car TEGRA210_CLK_D_AUDIO,
+tegra_car TEGRA210_CLK_ADMA_APE;
+ clock-names = adma, adma.ape;
+ #dma-cells = 1;
+};
--
2.1.4
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