Re: [PATCH v2 1/3] Documentation: bindings: brcmstb: Document write-pairing

[Gregory Fong]

On Tue, Sep 15, 2015 at 11:14 AM, Florian Fainelli  wrote:
> Document the hif-cpubiuctrl node a bit more, and add a documentation
> entry for the optional "brcm,write-pairing" property.
>
> Signed-off-by: Florian Fainelli 

Acked-by: Gregory Fong 
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Re: [PATCH v2 3/3] ARM: brcmstb: Setup BIU control registers during boot

[Gregory Fong]

On Tue, Sep 15, 2015 at 11:15 AM, Florian Fainelli  wrote:
> Call brcmstb_biuctrl_init() in brcmstb's init_irq machine descriptor
> callback since we need to setup the Bus Interface Unit before SMP in
> particular, but we also need to be able to remap registers.
>
> Signed-off-by: Florian Fainelli 

Acked-by: Gregory Fong 
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Re: [PATCH v2 2/3] soc: brcmstb: Add Bus Interface Unit control setup

[Gregory Fong]

On Tue, Sep 15, 2015 at 11:14 AM, Florian Fainelli  wrote:
> Broadcom STB SoCs (brcmstb) require an early setup of their Bus
> Interface Unit control register, this needs to happen before SMP is
> brought up because it affects how the CPU complex will be interfaced to
> the memory controller.
>
> Add support code which properly initializes the BIU registers based on
> whether "brcm,write-pairing" is present in Device Tree, and take care of
> saving and restoring credit register settings during system-wide
> suspend/resume operations.
>
> Signed-off-by: Florian Fainelli 
> ---
> Changes in v2:
>
> - add a pr_fmt prefix which is more descriptive
>
>  drivers/soc/brcmstb/Makefile|   2 +-
>  drivers/soc/brcmstb/biuctrl.c   | 119 
> 
>  include/linux/soc/brcmstb/brcmstb.h |  10 +++
>  3 files changed, 130 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/soc/brcmstb/biuctrl.c
>  create mode 100644 include/linux/soc/brcmstb/brcmstb.h
>
> [...]
> diff --git a/drivers/soc/brcmstb/biuctrl.c b/drivers/soc/brcmstb/biuctrl.c
> new file mode 100644
> index ..1d4deada1c4d
> --- /dev/null
> +++ b/drivers/soc/brcmstb/biuctrl.c
> @@ -0,0 +1,119 @@
> [...]
> +int __init brcmstb_biuctrl_init(void)
> +{
> +   int ret = 0;
> +
> +   ret = setup_hifcpubiuctrl_regs();
> +   if (ret)
> +   return ret;
> +
> +   ret = mcp_write_pairing_set();
> +   if (ret) {
> +   pr_err("MCP: Unable to disable write pairing!\n");
> +   return ret;

The return value isn't used in patch 3.  Is there a point to returning
an error from this function in either of the above two locations,
considering that?

Looks good otherwise.

Acked-by: Gregory Fong 
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[PATCH] ARM: dts: imx6qdl: complement the missed clock of spdif

[Shengjiu Wang]

Complement the devicetree of spdif node

Signed-off-by: Shengjiu Wang 
---
 arch/arm/boot/dts/imx6qdl.dtsi | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 53044b0..2b6cc8b 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -219,15 +219,15 @@
   < 15 18 0>;
dma-names = "rx", "tx";
clocks = < 
IMX6QDL_CLK_SPDIF_GCLK>, < IMX6QDL_CLK_OSC>,
-< IMX6QDL_CLK_SPDIF>, 
< IMX6QDL_CLK_DUMMY>,
-< IMX6QDL_CLK_DUMMY>, 
< IMX6QDL_CLK_DUMMY>,
-< IMX6QDL_CLK_DUMMY>, 
< IMX6QDL_CLK_DUMMY>,
-< IMX6QDL_CLK_DUMMY>;
+< IMX6QDL_CLK_SPDIF>, 
< IMX6QDL_CLK_ASRC>,
+< IMX6QDL_CLK_DUMMY>, 
< IMX6QDL_CLK_ESAI_EXTAL>,
+< IMX6QDL_CLK_IPG>, 
< IMX6QDL_CLK_MLB>,
+< IMX6QDL_CLK_DUMMY>, 
< IMX6QDL_CLK_SPBA>;
clock-names = "core",  "rxtx0",
  "rxtx1", "rxtx2",
  "rxtx3", "rxtx4",
  "rxtx5", "rxtx6",
- "rxtx7";
+ "rxtx7", "dma";
status = "disabled";
};
 
-- 
1.9.1

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[PATCH v3 00/09] ARM: shmobile: APMU DT support via SMP Enable method V3

[Magnus Damm]

ARM: shmobile: APMU DT support via SMP Enable method V3

[PATCH v3 01/09] devicetree: bindings: Renesas APMU and SMP Enable method
[PATCH v3 02/09] ARM: shmobile: Add APMU DT support via Enable method
[PATCH v3 03/09] ARM: shmobile: Add APMU nodes to r8a7793 DTSI
[PATCH v3 04/09] ARM: shmobile: r8a7793 boot address update
[PATCH v3 05/09] ARM: shmobile: Add APMU nodes to r8a7790 DTSI
[PATCH v3 06/09] ARM: shmobile: Add APMU nodes to r8a7791 DTSI
[PATCH v3 07/09] ARM: shmobile: Add function to prioritize DT SMP
[PATCH v3 08/09] ARM: shmobile: Prioritize r8a7790 DT APMU support
[PATCH v3 09/09] ARM: shmobile: Prioritize r8a7791 DT APMU support

These patches add DT support for the APMU hardware commonly found in
Renesas R-Car Gen2 SoCs. Without these patches the APMU gets configured
through data expressed in C, and with this series applied it is possible
to describe the APMU configuration in DT and let the enable method point
out that the APMU should be used.

Patch 1 and 2 are Documenting and adding DT support to the APMU driver
together with enabling use of the enable-method way to describe that
the APMU hardware is needed for SMP operation.

Patch 3 and 4 add r8a7793 SMP support using this the new APMU DT interface.

Patch 5 and 6 are related to r8a7790/r8a7791 support that get a DTSI update
to describe the APMU hardware. To avoid breaking support for older DTBs out
in the wild these patches keep the older existing C code APMU configuration
as-is. Patch 7-9 make sure that during run-time, if the APMU is installed
via the DT enable-method then it will not be overriden by older non-DT
configuration.

I suggest making APMU DT configuration mandatory for SMP operation on
newer SoCs and that we keep the old APMU support code in place for a
good number of kernel releases or until we can identify a couple of major
reasons good enough to force a DTB update on the end users.

In the future r8a7794 support may be added by using code similar to
patch 3 and 4 - without any C-based SMP code and fallback.

Signed-off-by: Magnus Damm 
---

 Written against renesas-drivers-2015-09-15-v4.3-rc1
 
 Documentation/devicetree/bindings/arm/cpus.txt   |1 
 Documentation/devicetree/bindings/power/renesas,apmu.txt |   31 
 arch/arm/boot/dts/r8a7790.dtsi   |   13 +
 arch/arm/boot/dts/r8a7791.dtsi   |7 +
 arch/arm/boot/dts/r8a7793.dtsi   |   14 ++
 arch/arm/mach-shmobile/common.h  |1 
 arch/arm/mach-shmobile/platsmp-apmu.c|   92 +-
 arch/arm/mach-shmobile/platsmp.c |7 +
 arch/arm/mach-shmobile/pm-rcar-gen2.c|5 
 arch/arm/mach-shmobile/setup-r8a7790.c   |1 
 arch/arm/mach-shmobile/setup-r8a7791.c   |1 
 11 files changed, 168 insertions(+), 5 deletions(-)
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[PATCH v3 01/09] devicetree: bindings: Renesas APMU and SMP Enable method

[Magnus Damm]

From: Magnus Damm 

Add DT binding documentation for the APMU hardware and add "renesas,apmu"
to the list of enable methods for the ARM cpus.

Signed-off-by: Magnus Damm 
---

 Changes since V2:
 - s/Until/Unit/g - thanks Geert!

 Changes since V1:
 - None

 Documentation/devicetree/bindings/arm/cpus.txt   |1 
 Documentation/devicetree/bindings/power/renesas,apmu.txt |   31 ++
 2 files changed, 32 insertions(+)

--- 0001/Documentation/devicetree/bindings/arm/cpus.txt
+++ work/Documentation/devicetree/bindings/arm/cpus.txt 2015-09-16 
20:32:46.710513000 +0900
@@ -198,6 +198,7 @@ nodes to be present and contain the prop
"qcom,gcc-msm8660"
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
+   "renesas,apmu"
"rockchip,rk3066-smp"
"ste,dbx500-smp"
 
--- /dev/null
+++ work/Documentation/devicetree/bindings/power/renesas,apmu.txt   
2015-09-16 20:42:09.000513000 +0900
@@ -0,0 +1,31 @@
+DT bindings for the Renesas Advanced Power Management Unit
+
+Renesas R-Car line of SoCs utilize one or more APMU hardware units
+for CPU core power domain control including SMP boot and CPU Hotplug.
+
+Required properties:
+
+- compatible: Should be "renesas,apmu-", "renesas,apmu" as fallback.
+ Examples with soctypes are:
+   - "renesas,apmu-r8a7790" (R-Car H2)
+   - "renesas,apmu-r8a7791" (R-Car M2-W)
+   - "renesas,apmu-r8a7792" (R-Car V2H)
+   - "renesas,apmu-r8a7793" (R-Car M2-N)
+   - "renesas,apmu-r8a7794" (R-Car E2)
+
+- reg: Base address and length of the I/O registers used by the APMU.
+
+- cpus: This node contains a list of CPU cores, which should match the order
+  of CPU cores used by the WUPCR and PSTR reigsters in the Advanced Power
+  Management Unit section of the device's datasheet.
+
+
+Example:
+
+This shows the r8a7791 APMU that can control CPU0 and CPU1.
+
+   apmu@e6152000 {
+   compatible = "renesas,apmu-r8a7791", "renesas,apmu";
+   reg = <0 0xe6152000 0 0x188>;
+   cpus = < >;
+   };
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[PATCH v3 02/09] ARM: shmobile: Add APMU DT support via Enable method

[Magnus Damm]

From: Magnus Damm 

Allow DT configuration of the APMU hardware in the case when the APMU is
pointed out in the DTB via the enable-method. The ability to configure
the APMU via C code is still kept intact to prevent DTB breakage for older
SoCs that do not rely on the enable-method for SMP support.

Signed-off-by: Magnus Damm 
---

 Changes since V2:
 - Moved is_allowed declaration, break when allowed - thanks Geert!

 Changes since V1:
 - Adjusted to use .cpu_can_disable instead of .cpu_disable

 arch/arm/mach-shmobile/platsmp-apmu.c |   92 +++--
 1 file changed, 88 insertions(+), 4 deletions(-)

--- 0001/arch/arm/mach-shmobile/platsmp-apmu.c
+++ work/arch/arm/mach-shmobile/platsmp-apmu.c  2015-09-16 20:46:23.400513000 
+0900
@@ -24,6 +24,7 @@
 #include 
 #include "common.h"
 #include "platsmp-apmu.h"
+#include "rcar-gen2.h"
 
 static struct {
void __iomem *iomem;
@@ -117,15 +118,67 @@ static void apmu_parse_cfg(void (*fn)(st
}
 }
 
-void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
-  struct rcar_apmu_config *apmu_config,
-  int num)
+static const struct of_device_id apmu_ids[] = {
+   { .compatible = "renesas,apmu" },
+   { /*sentinel*/ }
+};
+
+static void apmu_parse_dt(void (*fn)(struct resource *res, int cpu, int bit))
+{
+   struct device_node *np_apmu, *np_cpu;
+   struct resource res;
+   u32 id;
+   int bit, index;
+
+   for_each_matching_node(np_apmu, apmu_ids) {
+   /* only enable the cluster that includes the boot CPU */
+   bool is_allowed = false;
+   for (bit = 0; bit < CONFIG_NR_CPUS; bit++) {
+   np_cpu = of_parse_phandle(np_apmu, "cpus", bit);
+   if (np_cpu) {
+   if (!of_property_read_u32(np_cpu, "reg", )) {
+   if (id == cpu_logical_map(0)) {
+   is_allowed = true;
+   of_node_put(np_cpu);
+   break;
+   }
+   
+   }
+   of_node_put(np_cpu);
+   }
+   }
+   if (!is_allowed)
+   continue;
+
+   for (bit = 0; bit < CONFIG_NR_CPUS; bit++) {
+   np_cpu = of_parse_phandle(np_apmu, "cpus", bit);
+   if (np_cpu) {
+   if (!of_property_read_u32(np_cpu, "reg", )) {
+   index = get_logical_index(id);
+   if ((index >= 0) &&
+   !of_address_to_resource(np_apmu,
+   0, ))
+   fn(, index, bit);
+   }
+   of_node_put(np_cpu);
+   }
+   }
+   of_node_put(np_apmu);
+   }
+}
+
+static void __init shmobile_smp_apmu_setup_boot(void)
 {
/* install boot code shared by all CPUs */
shmobile_boot_fn = virt_to_phys(shmobile_smp_boot);
shmobile_boot_arg = MPIDR_HWID_BITMASK;
+}
 
-   /* perform per-cpu setup */
+void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
+  struct rcar_apmu_config *apmu_config,
+  int num)
+{
+   shmobile_smp_apmu_setup_boot();
apmu_parse_cfg(apmu_init_cpu, apmu_config, num);
 }
 
@@ -236,3 +289,34 @@ void __init shmobile_smp_apmu_suspend_in
shmobile_suspend_ops.enter = shmobile_smp_apmu_enter_suspend;
 }
 #endif
+
+static void __init shmobile_smp_apmu_prepare_cpus_dt(unsigned int max_cpus)
+{
+   shmobile_smp_apmu_setup_boot();
+   apmu_parse_dt(apmu_init_cpu);
+   rcar_gen2_pm_init();
+}
+
+static int shmobile_smp_apmu_boot_secondary_md21(unsigned int cpu,
+struct task_struct *idle)
+{
+   /* Error out when hardware debug mode is enabled */
+   if (rcar_gen2_read_mode_pins() & BIT(21)) {
+   pr_warn("Unable to boot CPU%u when MD21 is set\n", cpu);
+   return -ENOTSUPP;
+   }
+
+   return shmobile_smp_apmu_boot_secondary(cpu, idle);
+}
+
+static struct smp_operations apmu_smp_ops __initdata = {
+   .smp_prepare_cpus   = shmobile_smp_apmu_prepare_cpus_dt,
+   .smp_boot_secondary = shmobile_smp_apmu_boot_secondary_md21,
+#ifdef CONFIG_HOTPLUG_CPU
+   .cpu_can_disable= shmobile_smp_cpu_can_disable,
+   .cpu_die= 

[PATCH v2 0/5] net: Hisilicon Network Subsystem support

[huangdaode]

This is V2 of Hisilicon Network Subsystem(HNS) patchesets taking care
about LKML comments.

Please find out the changes from the change logs. 
This patchset is rebased on mainline kernel Linux 4.3-rc1 branch.

[PATCH v2 1/5] Device Tree Binding Documentation
[PATCH v2 2/5] Merge MDIO Module
[PATCH v2 3/5] Hisilicon Network Acceleration Engine Framework
[PATCH v2 4/5] Distributed System Area Fabric Module
[PATCH v2 5/5] Basic Ethernet Driver Module

Changes from V1:
1. Remove "inline" in C file (according to LKML comment, same in below).
2. Fix a bug about class_find_device.
3. Change the DTS pattern on hnae, restruct it to compatible with Hi1610 soc.
4. Unified hip04_mdio and hip05_mdio into hns_mdio, which is more usaul for 
   later SOCs.

V1 Patches Reference: https://lkml.org/lkml/2015/8/14/165

Thanks

huangdaode (5):
  net: add Hisilicon Network Subsystem support (config and documents)
  net: add Hisilicon Network Subsystem MDIO support
  net: add Hisilicon Network Subsystem hnae framework support
  net: add Hisilicon Network Subsystem DSAF support
  net: add Hisilicon Network Subsystem basic ethernet support

 .../bindings/net/hisilicon-hip04-net.txt   |4 +-
 .../devicetree/bindings/net/hisilicon-hns-dsaf.txt |   49 +
 .../devicetree/bindings/net/hisilicon-hns-mdio.txt |   22 +
 .../devicetree/bindings/net/hisilicon-hns-nic.txt  |   47 +
 arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi   |  193 ++
 drivers/net/ethernet/hisilicon/Kconfig |   34 +-
 drivers/net/ethernet/hisilicon/Makefile|4 +-
 drivers/net/ethernet/hisilicon/hip04_mdio.c|  185 --
 drivers/net/ethernet/hisilicon/hns/Makefile|   12 +
 drivers/net/ethernet/hisilicon/hns/hnae.c  |  507 
 drivers/net/ethernet/hisilicon/hns/hnae.h  |  583 +
 drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c  |  777 +++
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c |  704 ++
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.h |   45 +
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.c  |  900 +++
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.h  |  456 
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c | 2445 
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h |  427 
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c |  317 +++
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.h |   43 +
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c  |  583 +
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.h  |  105 +
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c  | 1023 
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.h  |  137 ++
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h  |  972 
 .../net/ethernet/hisilicon/hns/hns_dsaf_xgmac.c|  836 +++
 .../net/ethernet/hisilicon/hns/hns_dsaf_xgmac.h|   15 +
 drivers/net/ethernet/hisilicon/hns/hns_enet.c  | 1646 +
 drivers/net/ethernet/hisilicon/hns/hns_enet.h  |   84 +
 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c   | 1230 ++
 drivers/net/ethernet/hisilicon/hns_mdio.c  |  520 +
 31 files changed, 14716 insertions(+), 189 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt
 create mode 100644 Documentation/devicetree/bindings/net/hisilicon-hns-mdio.txt
 create mode 100644 Documentation/devicetree/bindings/net/hisilicon-hns-nic.txt
 create mode 100644 arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
 delete mode 100644 drivers/net/ethernet/hisilicon/hip04_mdio.c
 create mode 100644 drivers/net/ethernet/hisilicon/hns/Makefile
 create mode 100644 drivers/net/ethernet/hisilicon/hns/hnae.c
 create mode 100644 drivers/net/ethernet/hisilicon/hns/hnae.h
 create mode 100644 drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c
 create mode 100644 drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c
 create mode 100644 drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.h
 create mode 100644 drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.c
 create mode 100644 drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.h
 create mode 100644 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
 create mode 100644 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h
 create mode 100644 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c
 create mode 100644 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.h
 create mode 100644 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c
 create mode 100644 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.h
 create mode 100644 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c
 create mode 100644 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.h
 create mode 100644 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h
 create mode 100644 drivers/net/ethernet/hisilicon/hns/hns_dsaf_xgmac.c
 create mode 100644 drivers/net/ethernet/hisilicon/hns/hns_dsaf_xgmac.h
 create mode 100644 drivers/net/ethernet/hisilicon/hns/hns_enet.c
 create mode 100644 

[PATCH v2 3/5] net: add Hisilicon Network Subsystem hnae framework support

[huangdaode]

HNAE (Hisilicon Network Acceleration Engine) is a framework to provide a
unified ring buffer interface for Hisilicon Network Acceleration
Engines.

With the interface, upper layer can work as ethernet driver, ODP driver
or other service driver on purpose.

Signed-off-by: huangdaode 
Signed-off-by: Kenneth Lee 
Signed-off-by: Yisen Zhuang 
---
 drivers/net/ethernet/hisilicon/Kconfig  |   7 +
 drivers/net/ethernet/hisilicon/Makefile |   1 +
 drivers/net/ethernet/hisilicon/hns/Makefile |   5 +
 drivers/net/ethernet/hisilicon/hns/hnae.c   | 507 
 drivers/net/ethernet/hisilicon/hns/hnae.h   | 583 
 5 files changed, 1103 insertions(+)
 create mode 100644 drivers/net/ethernet/hisilicon/hns/Makefile
 create mode 100644 drivers/net/ethernet/hisilicon/hns/hnae.c
 create mode 100644 drivers/net/ethernet/hisilicon/hns/hnae.h

diff --git a/drivers/net/ethernet/hisilicon/Kconfig 
b/drivers/net/ethernet/hisilicon/Kconfig
index 9184f1d..85a2609 100644
--- a/drivers/net/ethernet/hisilicon/Kconfig
+++ b/drivers/net/ethernet/hisilicon/Kconfig
@@ -39,4 +39,11 @@ config HNS_MDIO
  This selects the HNS MDIO support. It is needed by HNS_DSAF to access
  the PHY
 
+config HNS
+   tristate "Hisilicon Network Subsystem Support (Framework)"
+   ---help---
+ This selects the framework support for Hisilicon Network Subsystem. It
+ is needed by any driver which provides HNS acceleration engine or make
+ use of the engine
+
 endif # NET_VENDOR_HISILICON
diff --git a/drivers/net/ethernet/hisilicon/Makefile 
b/drivers/net/ethernet/hisilicon/Makefile
index 04b4b21..390b71f 100644
--- a/drivers/net/ethernet/hisilicon/Makefile
+++ b/drivers/net/ethernet/hisilicon/Makefile
@@ -5,3 +5,4 @@
 obj-$(CONFIG_HIX5HD2_GMAC) += hix5hd2_gmac.o
 obj-$(CONFIG_HIP04_ETH) += hip04_eth.o
 obj-$(CONFIG_HNS_MDIO) += hns_mdio.o
+obj-$(CONFIG_HNS) += hns/
diff --git a/drivers/net/ethernet/hisilicon/hns/Makefile 
b/drivers/net/ethernet/hisilicon/hns/Makefile
new file mode 100644
index 000..8a5f1e7
--- /dev/null
+++ b/drivers/net/ethernet/hisilicon/hns/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the HISILICON network device drivers.
+#
+
+obj-$(CONFIG_HNS) += hnae.o
diff --git a/drivers/net/ethernet/hisilicon/hns/hnae.c 
b/drivers/net/ethernet/hisilicon/hns/hnae.c
new file mode 100644
index 000..0a0a9e8
--- /dev/null
+++ b/drivers/net/ethernet/hisilicon/hns/hnae.c
@@ -0,0 +1,507 @@
+/*
+ * Copyright (c) 2014-2015 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include "hnae.h"
+
+#define cls_to_ae_dev(dev) container_of(dev, struct hnae_ae_dev, cls_dev)
+
+static struct class *hnae_class;
+
+static void
+hnae_list_add(spinlock_t *lock, struct list_head *node, struct list_head *head)
+{
+   unsigned long flags;
+
+   spin_lock_irqsave(lock, flags);
+   list_add_tail_rcu(node, head);
+   spin_unlock_irqrestore(lock, flags);
+}
+
+static void hnae_list_del(spinlock_t *lock, struct list_head *node)
+{
+   unsigned long flags;
+
+   spin_lock_irqsave(lock, flags);
+   list_del_rcu(node);
+   spin_unlock_irqrestore(lock, flags);
+}
+
+static int hnae_alloc_buffer(struct hnae_ring *ring, struct hnae_desc_cb *cb)
+{
+   unsigned int order = hnae_page_order(ring);
+   struct page *p = dev_alloc_pages(order);
+
+   if (!p)
+   return -ENOMEM;
+
+   cb->priv = p;
+   cb->page_offset = 0;
+   cb->reuse_flag = 0;
+   cb->buf  = page_address(p);
+   cb->length = hnae_page_size(ring);
+   cb->type = DESC_TYPE_PAGE;
+
+   return 0;
+}
+
+static void hnae_free_buffer(struct hnae_ring *ring, struct hnae_desc_cb *cb)
+{
+   if (cb->type == DESC_TYPE_SKB)
+   dev_kfree_skb_any((struct sk_buff *)cb->priv);
+   else if (unlikely(is_rx_ring(ring)))
+   put_page((struct page *)cb->priv);
+   memset(cb, 0, sizeof(*cb));
+}
+
+static int hnae_map_buffer(struct hnae_ring *ring, struct hnae_desc_cb *cb)
+{
+   cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
+  cb->length, ring_to_dma_dir(ring));
+
+   if (dma_mapping_error(ring_to_dev(ring), cb->dma))
+   return -EIO;
+
+   return 0;
+}
+
+static void hnae_unmap_buffer(struct hnae_ring *ring, struct hnae_desc_cb *cb)
+{
+   if (cb->type == DESC_TYPE_SKB)
+   dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
+ring_to_dma_dir(ring));
+   else
+   dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
+  

[PATCH v2 1/5] net: add Hisilicon Network Subsystem support (config and documents)

[huangdaode]

The Hisilicon Network Subsystem is a long term evolution IP which is
supposed to be used in Hisilicon ICT SoC. The IP, which is called hns
for short, is a TCP/IP acceleration engine, which can directly decode
TCP/IP stream and distribute them to different ring buffers.

HNS can be configured to work on different mode for different scenario.
This patch make use only some of the mode to make it as standard
ethernet NIC. The other mode will be added soon.

The whole function has 4 kernel sub-modules:

hnae: the HNS acceleration engine framework. It provides a abstract
interface between the engine and the upper layers which make use of the
engine by ring buffer.

hns_enet_drv: a standard ethernet driver that base on the ring buffer.

hns_dsaf: one of the implementation of HNS acceleration engine, which is
applied on Hililicon hip05, Hi1610 and other later-on SoCs

hns_mdio: the mdio control to the PHY, used by acceleration engine

This submit add basic config and documents

Signed-off-by: huangdaode 
Signed-off-by: Kenneth Lee 
Signed-off-by: Yisen Zhuang 
---
 .../bindings/net/hisilicon-hip04-net.txt   |   4 +-
 .../devicetree/bindings/net/hisilicon-hns-dsaf.txt |  49 ++
 .../devicetree/bindings/net/hisilicon-hns-mdio.txt |  22 +++
 .../devicetree/bindings/net/hisilicon-hns-nic.txt  |  47 +
 arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi   | 193 +
 5 files changed, 313 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt
 create mode 100644 Documentation/devicetree/bindings/net/hisilicon-hns-mdio.txt
 create mode 100644 Documentation/devicetree/bindings/net/hisilicon-hns-nic.txt
 create mode 100644 arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi

diff --git a/Documentation/devicetree/bindings/net/hisilicon-hip04-net.txt 
b/Documentation/devicetree/bindings/net/hisilicon-hip04-net.txt
index 988fc69..d1df8a0 100644
--- a/Documentation/devicetree/bindings/net/hisilicon-hip04-net.txt
+++ b/Documentation/devicetree/bindings/net/hisilicon-hip04-net.txt
@@ -32,13 +32,13 @@ Required properties:
 
 Required properties:
 
-- compatible: should be "hisilicon,hip04-mdio".
+- compatible: should be "hisilicon,mdio".
 - Inherits from MDIO bus node binding [2]
 [2] Documentation/devicetree/bindings/net/phy.txt
 
 Example:
mdio {
-   compatible = "hisilicon,hip04-mdio";
+   compatible = "hisilicon,mdio";
reg = <0x28f1000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt 
b/Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt
new file mode 100644
index 000..80411b2
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt
@@ -0,0 +1,49 @@
+Hisilicon DSA Fabric device controller
+
+Required properties:
+- compatible: should be "hisilicon,hns-dsaf-v1" or "hisilicon,hns-dsaf-v2".
+  "hisilicon,hns-dsaf-v1" is for hip05.
+  "hisilicon,hns-dsaf-v2" is for Hi1610 and Hi1612.
+- dsa-name: dsa fabric name who provide this interface.
+  should be "dsafX", X is the dsaf id.
+- mode: dsa fabric mode string. only support one of dsaf modes like these:
+   "2port-64vf",
+   "6port-16rss",
+   "6port-16vf".
+- interrupt-parent: the interrupt parent of this device.
+- interrupts: should contain the DSA Fabric and rcb interrupt.
+- reg: specifies base physical address(es) and size of the device registers.
+  The first region is external interface control register base and size.
+  The second region is SerDes base register and size.
+  The third region is the PPE register base and size.
+  The fourth region is dsa fabric base register and size.
+  The fifth region is cpld base register and size, it is not required if do 
not use cpld.
+- phy-handle: phy handle of physicl port, 0 if not any phy device. see 
ethernet.txt [1].
+- buf-size: rx buffer size, should be 16-1024.
+- desc-num: number of description in TX and RX queue, should be 512, 1024, 
2048 or 4096.
+
+[1] Documentation/devicetree/bindings/net/phy.txt
+
+Example:
+
+dsa: dsa@c700 {
+   compatible = "hisilicon,hns-dsaf-v1";
+   dsa_name = "dsaf0";
+   mode = "6port-16rss";
+   interrupt-parent = <_dsa>;
+   reg = <0x0 0xC000 0x0 0x42
+  0x0 0xC200 0x0 0x30
+  0x0 0xc500 0x0 0x89
+  0x0 0xc700 0x0 0x6>;
+   phy-handle = <0 0 0 0 _phy4 _phy5 0 0>;
+   interrupts = <131 4>,<132 4>, <133 4>,<134 4>,
+<135 4>,<136 4>, <137 4>,<138 4>,
+<139 4>,<140 4>, <141 4>,<142 4>,
+<143 4>,<144 4>, <145 4>,<146 4>,
+<147 4>,<148 4>, <384 1>,<385 1>,
+<386 1>,<387 1>, <388 1>,<389 1>,
+<390 1>,<391 1>,

[PATCH 3/3] arm64: dts: rockchip: Add the needed timer for rk3368 SoC

[Caesar Wang]

There is a need of a broadcast timer in this case to ensure proper
wakeup when the cpus are in sleep mode and a timer expires.

Signed-off-by: Caesar Wang 
---

 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index a712bea..99edbaa 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -214,6 +214,12 @@
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
};
 
+   timer@ff81 {
+   compatible = "rockchip,rk3288-timer";
+   reg = <0x0 0xff81 0x0 0x20>;
+   interrupts = ;
+   };
+
xin24m: oscillator {
compatible = "fixed-clock";
clock-frequency = <2400>;
-- 
1.9.1

--
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[PATCH v3 08/09] ARM: shmobile: Prioritize r8a7790 DT APMU support

[Magnus Damm]

From: Magnus Damm 

Adjust the r8a7790 SoC support code to not configure any non-DT SMP code
in case the DT-based enable-method has been installed already.

Signed-off-by: Magnus Damm 
---

 Changes since V2:
 - None

 Changes since V1:
 - New patch.

 arch/arm/mach-shmobile/setup-r8a7790.c |1 +
 1 file changed, 1 insertion(+)

--- 0001/arch/arm/mach-shmobile/setup-r8a7790.c
+++ work/arch/arm/mach-shmobile/setup-r8a7790.c 2015-08-23 15:44:29.102366518 
+0900
@@ -28,6 +28,7 @@ static const char * const r8a7790_boards
 };
 
 DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
+   .smp_init   = shmobile_smp_init_fallback_ops,
.smp= smp_ops(r8a7790_smp_ops),
.init_early = shmobile_init_delay,
.init_time  = rcar_gen2_timer_init,
--
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[PATCH v3 06/09] ARM: shmobile: Add APMU nodes to r8a7791 DTSI

[Magnus Damm]

From: Magnus Damm 

Add an APMU DT node for the r8a7791 SoC and use the enable-method to
point out that the APMU should be used for SMP support.

Signed-off-by: Magnus Damm 
---

 Changes from V2:
 - None

 Changes from V1:
 - None

 arch/arm/boot/dts/r8a7791.dtsi |7 +++
 1 file changed, 7 insertions(+)

--- 0001/arch/arm/boot/dts/r8a7791.dtsi
+++ work/arch/arm/boot/dts/r8a7791.dtsi 2015-08-23 15:42:10.522366518 +0900
@@ -42,6 +42,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+   enable-method = "renesas,apmu";
 
cpu0: cpu@0 {
device_type = "cpu";
@@ -69,6 +70,12 @@
};
};
 
+   apmu@e6152000 {
+   compatible = "renesas,apmu-r8a7791", "renesas,apmu";
+   reg = <0 0xe6152000 0 0x188>;
+   cpus = < >;
+   };
+
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
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[PATCH v3 07/09] ARM: shmobile: Add function to prioritize DT SMP

[Magnus Damm]

From: Magnus Damm 

Add a function to check if other DT based method is available, and
if so return false to not hook up smp_ops from the machine vector.

This results in that DT-based SMP support has priority over older
C-based smp_ops code, and in case DT-based SMP support code does not
exist in the DTB then the old smp_ops code will still work as-is.

Signed-off-by: Magnus Damm 
---

 Changes since V2:
 - None

 Changes since V1:
 - Reworked r8a7791-specific version to become reusable function.

 arch/arm/mach-shmobile/common.h  |1 +
 arch/arm/mach-shmobile/platsmp.c |7 +++
 2 files changed, 8 insertions(+)

--- 0001/arch/arm/mach-shmobile/common.h
+++ work/arch/arm/mach-shmobile/common.h2015-08-23 15:26:18.722366518 
+0900
@@ -11,6 +11,7 @@ extern void shmobile_smp_sleep(void);
 extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn,
  unsigned long arg);
 extern bool shmobile_smp_cpu_can_disable(unsigned int cpu);
+extern bool shmobile_smp_init_fallback_ops(void);
 extern void shmobile_boot_scu(void);
 extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus);
 extern void shmobile_smp_scu_cpu_die(unsigned int cpu);
--- 0001/arch/arm/mach-shmobile/platsmp.c
+++ work/arch/arm/mach-shmobile/platsmp.c   2015-08-23 15:26:13.692366518 
+0900
@@ -36,3 +36,10 @@ bool shmobile_smp_cpu_can_disable(unsign
return true; /* Hotplug of any CPU is supported */
 }
 #endif
+
+bool __init shmobile_smp_init_fallback_ops(void)
+{
+   /* fallback on PSCI/smp_ops if no other DT based method is detected */
+   return platform_can_secondary_boot() ? true : false;
+}
+
--
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[PATCH v3 05/09] ARM: shmobile: Add APMU nodes to r8a7790 DTSI

[Magnus Damm]

From: Magnus Damm 

Add an APMU DT node for the r8a7790 SoC and use the enable-method to
point out that the APMU should be used for SMP support.

Signed-off-by: Magnus Damm 
---

 Changes from V2:
 - None

 Changes from V1:
 - New patch

 arch/arm/boot/dts/r8a7790.dtsi |   13 +
 1 file changed, 13 insertions(+)

--- 0001/arch/arm/boot/dts/r8a7790.dtsi
+++ work/arch/arm/boot/dts/r8a7790.dtsi 2015-08-23 15:51:24.132366518 +0900
@@ -43,6 +43,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+   enable-method = "renesas,apmu";
 
cpu0: cpu@0 {
device_type = "cpu";
@@ -112,6 +113,18 @@
};
};
 
+   apmu@e6151000 {
+   compatible = "renesas,apmu-r8a7790", "renesas,apmu";
+   reg = <0 0xe6151000 0 0x188>;
+   cpus = <   >;
+   };
+
+   apmu@e6152000 {
+   compatible = "renesas,apmu-r8a7790", "renesas,apmu";
+   reg = <0 0xe6152000 0 0x188>;
+   cpus = <   >;
+   };
+
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
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[PATCH v3 04/09] ARM: shmobile: r8a7793 boot address update

[Magnus Damm]

From: Magnus Damm 

Extend the R-Car Gen2 PM code to include r8a7793 boot address
configuration information. r8a7793 boots from ICRAM1.

Signed-off-by: Magnus Damm 
---

 Changes from V2:
 - New patch

 arch/arm/mach-shmobile/pm-rcar-gen2.c |5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

--- 0001/arch/arm/mach-shmobile/pm-rcar-gen2.c
+++ work/arch/arm/mach-shmobile/pm-rcar-gen2.c  2015-09-16 22:08:12.610513000 
+0900
@@ -28,6 +28,7 @@
 /* On-chip RAM */
 #define MERAM  0xe808
 #define RAM0xe630
+#define ICRAM1 0xe63c
 
 /* SYSC */
 #define SYSCIER 0x0c
@@ -78,10 +79,12 @@ void __init rcar_gen2_pm_init(void)
if (of_machine_is_compatible("renesas,r8a7790")) {
boot_vector_addr = MERAM;
syscier = 0x013111ef;
-
} else if (of_machine_is_compatible("renesas,r8a7791")) {
boot_vector_addr = RAM;
syscier = 0x00111003;
+   } else if (of_machine_is_compatible("renesas,r8a7793")) {
+   boot_vector_addr = ICRAM1;
+   syscier = 0x00111003;
}
 
/* RAM for jump stub, because BAR requires 256KB aligned address */
--
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[PATCH v3 03/09] ARM: shmobile: Add APMU nodes to r8a7793 DTSI

[Magnus Damm]

From: Magnus Damm 

Add an APMU DT node for the r8a7793 SoC and use the enable-method to
point out that the APMU should be used for SMP support.

Signed-off-by: Magnus Damm 
---

 Changes from V2:
 - New patch

 arch/arm/boot/dts/r8a7793.dtsi |   14 ++
 1 file changed, 14 insertions(+)

--- 0001/arch/arm/boot/dts/r8a7793.dtsi
+++ work/arch/arm/boot/dts/r8a7793.dtsi 2015-09-16 20:53:27.660513000 +0900
@@ -21,6 +21,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+   enable-method = "renesas,apmu";
 
cpu0: cpu@0 {
device_type = "cpu";
@@ -39,6 +40,19 @@
   < 75 100>,
   < 375000 100>;
};
+
+   cpu1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a15";
+   reg = <1>;
+   clock-frequency = <15>;
+   };
+   };
+
+   apmu@e6152000 {
+   compatible = "renesas,apmu-r8a7793", "renesas,apmu";
+   reg = <0 0xe6152000 0 0x188>;
+   cpus = < >;
};
 
gic: interrupt-controller@f1001000 {
--
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[PATCH v3 09/09] ARM: shmobile: Prioritize r8a7791 DT APMU support

[Magnus Damm]

From: Magnus Damm 

Adjust the r8a7791 SoC support code to not configure any non-DT SMP code
in case the DT-based enable-method has been installed already.

Signed-off-by: Magnus Damm 
---

 Changes since V2:
 - None

 Changes since V1:
 - Broke out bits from former r8a7791-specific patch.

 arch/arm/mach-shmobile/setup-r8a7791.c |1 +
 1 file changed, 1 insertion(+)

--- 0001/arch/arm/mach-shmobile/setup-r8a7791.c
+++ work/arch/arm/mach-shmobile/setup-r8a7791.c 2015-08-23 15:46:53.002366518 
+0900
@@ -29,6 +29,7 @@ static const char *const r8a7791_boards_
 };
 
 DT_MACHINE_START(R8A7791_DT, "Generic R8A7791 (Flattened Device Tree)")
+   .smp_init   = shmobile_smp_init_fallback_ops,
.smp= smp_ops(r8a7791_smp_ops),
.init_early = shmobile_init_delay,
.init_time  = rcar_gen2_timer_init,
--
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[PATCH v2 5/5] net: add Hisilicon Network Subsystem basic ethernet support

[huangdaode]

This is to add basic ethernet support for HNS. It is one of the way to
use the HNS acceleration engine. But most of the decoding/encoding
capability of the AE cannot be used in this way.

This submit contains the basic feature as a ethernet driver. More will
be added later.

Signed-off-by: huangdaode 
Signed-off-by: Kenneth Lee 
Signed-off-by: Yisen Zhuang 
---
 drivers/net/ethernet/hisilicon/Kconfig   |8 +
 drivers/net/ethernet/hisilicon/hns/Makefile  |3 +
 drivers/net/ethernet/hisilicon/hns/hns_enet.c| 1646 ++
 drivers/net/ethernet/hisilicon/hns/hns_enet.h|   84 ++
 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c | 1230 
 5 files changed, 2971 insertions(+)
 create mode 100644 drivers/net/ethernet/hisilicon/hns/hns_enet.c
 create mode 100644 drivers/net/ethernet/hisilicon/hns/hns_enet.h
 create mode 100644 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c

diff --git a/drivers/net/ethernet/hisilicon/Kconfig 
b/drivers/net/ethernet/hisilicon/Kconfig
index aae2c47..165b5a8 100644
--- a/drivers/net/ethernet/hisilicon/Kconfig
+++ b/drivers/net/ethernet/hisilicon/Kconfig
@@ -55,4 +55,12 @@ config HNS_DSAF
  acceleration engine support. The engine is used in Hisilicon hip05,
  Hi1610 and further ICT SoC
 
+config HNS_ENET
+   tristate "Hisilicon HNS Ethernet Device Support"
+   select PHYLIB
+   select HNS
+   ---help---
+ This selects the general ethernet driver for HNS.  This module make
+ use of any HNS AE driver, such as HNS_DSAF
+
 endif # NET_VENDOR_HISILICON
diff --git a/drivers/net/ethernet/hisilicon/hns/Makefile 
b/drivers/net/ethernet/hisilicon/hns/Makefile
index 0516af7..6010c83 100644
--- a/drivers/net/ethernet/hisilicon/hns/Makefile
+++ b/drivers/net/ethernet/hisilicon/hns/Makefile
@@ -7,3 +7,6 @@ obj-$(CONFIG_HNS) += hnae.o
 obj-$(CONFIG_HNS_DSAF) += hns_dsaf.o
 hns_dsaf-objs = hns_ae_adapt.o hns_dsaf_gmac.o hns_dsaf_mac.o hns_dsaf_misc.o \
hns_dsaf_main.o hns_dsaf_ppe.o hns_dsaf_rcb.o hns_dsaf_xgmac.o
+
+obj-$(CONFIG_HNS_ENET) += hns_enet_drv.o
+hns_enet_drv-objs = hns_enet.o hns_ethtool.o
diff --git a/drivers/net/ethernet/hisilicon/hns/hns_enet.c 
b/drivers/net/ethernet/hisilicon/hns/hns_enet.c
new file mode 100644
index 000..0713ced
--- /dev/null
+++ b/drivers/net/ethernet/hisilicon/hns/hns_enet.c
@@ -0,0 +1,1646 @@
+/*
+ * Copyright (c) 2014-2015 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "hnae.h"
+#include "hns_enet.h"
+
+#define NIC_MAX_Q_PER_VF 16
+#define HNS_NIC_TX_TIMEOUT (5 * HZ)
+
+#define SERVICE_TIMER_HZ (1 * HZ)
+
+#define NIC_TX_CLEAN_MAX_NUM 256
+#define NIC_RX_CLEAN_MAX_NUM 64
+
+#define RCB_ERR_PRINT_CYCLE 1000
+
+#define RCB_IRQ_NOT_INITED 0
+#define RCB_IRQ_INITED 1
+
+static void fill_desc(struct hnae_ring *ring, void *priv,
+ int size, dma_addr_t dma, int frag_end,
+ int buf_num, enum hns_desc_type type)
+{
+   struct hnae_desc *desc = >desc[ring->next_to_use];
+   struct hnae_desc_cb *desc_cb = >desc_cb[ring->next_to_use];
+   struct sk_buff *skb;
+   __be16 protocol;
+   u32 ip_offset;
+   u32 asid_bufnum_pid = 0;
+   u32 flag_ipoffset = 0;
+
+   desc_cb->priv = priv;
+   desc_cb->length = size;
+   desc_cb->dma = dma;
+   desc_cb->type = type;
+
+   desc->addr = cpu_to_le64(dma);
+   desc->tx.send_size = cpu_to_le16((u16)size);
+
+   /*config bd buffer end */
+   flag_ipoffset |= 1 << HNS_TXD_VLD_B;
+
+   asid_bufnum_pid |= buf_num << HNS_TXD_BUFNUM_S;
+
+   if (type == DESC_TYPE_SKB) {
+   skb = (struct sk_buff *)priv;
+
+   if (skb->ip_summed == CHECKSUM_PARTIAL) {
+   protocol = skb->protocol;
+   ip_offset = ETH_HLEN;
+
+   /*if it is a SW VLAN check the next protocol*/
+   if (protocol == htons(ETH_P_8021Q)) {
+   ip_offset += VLAN_HLEN;
+   protocol = vlan_get_protocol(skb);
+   skb->protocol = protocol;
+   }
+
+   if (skb->protocol == htons(ETH_P_IP)) {
+   flag_ipoffset |= 1 << HNS_TXD_L3CS_B;
+   /* check for tcp/udp header */
+   flag_ipoffset |= 1 << HNS_TXD_L4CS_B;
+
+   } else if (skb->protocol == htons(ETH_P_IPV6)) {
+   /* 

[PATCH v2 2/5] net: add Hisilicon Network Subsystem MDIO support

[huangdaode]

The MDIO support for Hisilicon Network Subsystem. It is used in Hislicon
hip04, hip05 and Hi1610 SoC to control the external PHY

Signed-off-by: huangdaode 
Signed-off-by: Yisen Zhuang 
Signed-off-by: Kenneth Lee 
---
 drivers/net/ethernet/hisilicon/Kconfig  |  10 +-
 drivers/net/ethernet/hisilicon/Makefile |   3 +-
 drivers/net/ethernet/hisilicon/hip04_mdio.c | 185 --
 drivers/net/ethernet/hisilicon/hns_mdio.c   | 520 
 4 files changed, 531 insertions(+), 187 deletions(-)
 delete mode 100644 drivers/net/ethernet/hisilicon/hip04_mdio.c
 create mode 100644 drivers/net/ethernet/hisilicon/hns_mdio.c

diff --git a/drivers/net/ethernet/hisilicon/Kconfig 
b/drivers/net/ethernet/hisilicon/Kconfig
index dead17b..9184f1d 100644
--- a/drivers/net/ethernet/hisilicon/Kconfig
+++ b/drivers/net/ethernet/hisilicon/Kconfig
@@ -5,7 +5,7 @@
 config NET_VENDOR_HISILICON
bool "Hisilicon devices"
default y
-   depends on ARM
+   depends on ARM || ARM64
---help---
  If you have a network (Ethernet) card belonging to this class, say Y.
 
@@ -27,8 +27,16 @@ config HIP04_ETH
select PHYLIB
select MARVELL_PHY
select MFD_SYSCON
+   select HNS_MDIO
---help---
  If you wish to compile a kernel for a hardware with hisilicon p04 SoC 
and
  want to use the internal ethernet then you should answer Y to this.
 
+config HNS_MDIO
+   tristate "Hisilicon HNS MDIO device Support"
+   select MDIO
+   ---help---
+ This selects the HNS MDIO support. It is needed by HNS_DSAF to access
+ the PHY
+
 endif # NET_VENDOR_HISILICON
diff --git a/drivers/net/ethernet/hisilicon/Makefile 
b/drivers/net/ethernet/hisilicon/Makefile
index 6c14540..04b4b21 100644
--- a/drivers/net/ethernet/hisilicon/Makefile
+++ b/drivers/net/ethernet/hisilicon/Makefile
@@ -3,4 +3,5 @@
 #
 
 obj-$(CONFIG_HIX5HD2_GMAC) += hix5hd2_gmac.o
-obj-$(CONFIG_HIP04_ETH) += hip04_mdio.o hip04_eth.o
+obj-$(CONFIG_HIP04_ETH) += hip04_eth.o
+obj-$(CONFIG_HNS_MDIO) += hns_mdio.o
diff --git a/drivers/net/ethernet/hisilicon/hip04_mdio.c 
b/drivers/net/ethernet/hisilicon/hip04_mdio.c
deleted file mode 100644
index fca0a5b..000
--- a/drivers/net/ethernet/hisilicon/hip04_mdio.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/* Copyright (c) 2014 Linaro Ltd.
- * Copyright (c) 2014 Hisilicon Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#define MDIO_CMD_REG   0x0
-#define MDIO_ADDR_REG  0x4
-#define MDIO_WDATA_REG 0x8
-#define MDIO_RDATA_REG 0xc
-#define MDIO_STA_REG   0x10
-
-#define MDIO_START BIT(14)
-#define MDIO_R_VALID   BIT(1)
-#define MDIO_READ  (BIT(12) | BIT(11) | MDIO_START)
-#define MDIO_WRITE (BIT(12) | BIT(10) | MDIO_START)
-
-struct hip04_mdio_priv {
-   void __iomem *base;
-};
-
-#define WAIT_TIMEOUT 10
-static int hip04_mdio_wait_ready(struct mii_bus *bus)
-{
-   struct hip04_mdio_priv *priv = bus->priv;
-   int i;
-
-   for (i = 0; readl_relaxed(priv->base + MDIO_CMD_REG) & MDIO_START; i++) 
{
-   if (i == WAIT_TIMEOUT)
-   return -ETIMEDOUT;
-   msleep(20);
-   }
-
-   return 0;
-}
-
-static int hip04_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
-{
-   struct hip04_mdio_priv *priv = bus->priv;
-   u32 val;
-   int ret;
-
-   ret = hip04_mdio_wait_ready(bus);
-   if (ret < 0)
-   goto out;
-
-   val = regnum | (mii_id << 5) | MDIO_READ;
-   writel_relaxed(val, priv->base + MDIO_CMD_REG);
-
-   ret = hip04_mdio_wait_ready(bus);
-   if (ret < 0)
-   goto out;
-
-   val = readl_relaxed(priv->base + MDIO_STA_REG);
-   if (val & MDIO_R_VALID) {
-   dev_err(bus->parent, "SMI bus read not valid\n");
-   ret = -ENODEV;
-   goto out;
-   }
-
-   val = readl_relaxed(priv->base + MDIO_RDATA_REG);
-   ret = val & 0x;
-out:
-   return ret;
-}
-
-static int hip04_mdio_write(struct mii_bus *bus, int mii_id,
-   int regnum, u16 value)
-{
-   struct hip04_mdio_priv *priv = bus->priv;
-   u32 val;
-   int ret;
-
-   ret = hip04_mdio_wait_ready(bus);
-   if (ret < 0)
-   goto out;
-
-   writel_relaxed(value, priv->base + MDIO_WDATA_REG);
-   val = regnum | (mii_id << 5) | MDIO_WRITE;
-   writel_relaxed(val, priv->base + MDIO_CMD_REG);
-out:
-   return ret;
-}
-
-static int hip04_mdio_reset(struct mii_bus *bus)
-{
-   int temp, i;
-
-   

[PATCH 0/3] Support the timer on RK3368 SoC

[Caesar Wang]

Timer0~11 count up from zero to a programmed value and
generate an interrupt when the count reaches the programmed value.

TIMER0, TIMER1, TIMER2, Timer3, TIMER4 and TIMER5 are in the CPU
subsystem, using timer ch0 ~ ch5 respectively. The timer clock is 24MHz
OSC.

This series are found on RK3368 SoC, verified on rk3368 evb board.



Caesar Wang (3):
  clocksource: rockchip: Make the driver more readability and compatible
  arm64: Enable the timer on Rockchip architecture
  arm64: dts: rockchip: Add the needed timer for rk3368 SoC

 arch/arm64/Kconfig.platforms |  1 +
 arch/arm64/boot/dts/rockchip/rk3368.dtsi |  6 ++
 drivers/clocksource/rockchip_timer.c | 29 +++--
 3 files changed, 22 insertions(+), 14 deletions(-)

-- 
1.9.1

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[PATCH] Add driver for the si514 clock generator chip

[Mike Looijmans]

This patch adds the driver and devicetree documentation for the
Silicon Labs SI514 clock generator chip. This is an I2C controlled
oscilator capable of generating clock signals ranging from 100kHz
to 250MHz.

Signed-off-by: Mike Looijmans 
---
 .../devicetree/bindings/clock/silabs,si514.txt |  27 ++
 drivers/clk/Kconfig|  10 +
 drivers/clk/Makefile   |   1 +
 drivers/clk/clk-si514.c| 393 +
 4 files changed, 431 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/silabs,si514.txt
 create mode 100644 drivers/clk/clk-si514.c

diff --git a/Documentation/devicetree/bindings/clock/silabs,si514.txt 
b/Documentation/devicetree/bindings/clock/silabs,si514.txt
new file mode 100644
index 000..05964d1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/silabs,si514.txt
@@ -0,0 +1,27 @@
+Binding for Silicon Labs 514 programmable I2C clock generator.
+
+Reference
+This binding uses the common clock binding[1]. Details about the device can be
+found in the datasheet[2].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Si514 datasheet
+http://www.silabs.com/Support%20Documents/TechnicalDocs/si514.pdf
+
+Required properties:
+ - compatible: Shall be "silabs,si514"
+ - reg: I2C device address.
+ - #clock-cells: From common clock bindings: Shall be 0.
+
+Optional properties:
+ - clock-output-names: From common clock bindings. Recommended to be "si514".
+ - clock-frequency: Output frequency to generate. This defines the output
+   frequency set during boot. It can be reprogrammed during
+   runtime through the common clock framework.
+
+Example:
+   si514: clock-generator@55 {
+   reg = <0x55>;
+   #clock-cells = <0>;
+   compatible = "silabs,si514";
+   };
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 7a431f7..312bc70 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -68,6 +68,16 @@ config COMMON_CLK_SI5351
  This driver supports Silicon Labs 5351A/B/C programmable clock
  generators.
 
+config COMMON_CLK_SI514
+   tristate "Clock driver for SiLabs 514 devices"
+   depends on I2C
+   depends on OF
+   select REGMAP_I2C
+   help
+   ---help---
+ This driver supports the Silicon Labs 514 programmable clock
+ generator.
+
 config COMMON_CLK_SI570
tristate "Clock driver for SiLabs 570 and compatible devices"
depends on I2C
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index f1b50db..505f5d7 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_CLK_QORIQ)   += clk-qoriq.o
 obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o
 obj-$(CONFIG_COMMON_CLK_S2MPS11)   += clk-s2mps11.o
 obj-$(CONFIG_COMMON_CLK_SI5351)+= clk-si5351.o
+obj-$(CONFIG_COMMON_CLK_SI514) += clk-si514.o
 obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o
 obj-$(CONFIG_COMMON_CLK_CDCE925)   += clk-cdce925.o
 obj-$(CONFIG_CLK_TWL6040)  += clk-twl6040.o
diff --git a/drivers/clk/clk-si514.c b/drivers/clk/clk-si514.c
new file mode 100644
index 000..ca70818
--- /dev/null
+++ b/drivers/clk/clk-si514.c
@@ -0,0 +1,393 @@
+/*
+ * Driver for Silicon Labs Si514 Programmable Oscillator
+ *
+ * Copyright (C) 2015 Topic Embedded Products
+ *
+ * Author: Mike Looijmans 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* I2C registers */
+#define SI514_REG_LP   0
+#define SI514_REG_M_FRAC1  5
+#define SI514_REG_M_FRAC2  6
+#define SI514_REG_M_FRAC3  7
+#define SI514_REG_M_INT_FRAC   8
+#define SI514_REG_M_INT9
+#define SI514_REG_HS_DIV   10
+#define SI514_REG_LS_HS_DIV11
+#define SI514_REG_OE_STATE 14
+#define SI514_REG_RESET128
+#define SI514_REG_CONTROL  132
+
+/* Register values */
+#define SI514_RESET_RSTBIT(7)
+
+#define SI514_CONTROL_FCAL BIT(0)
+#define SI514_CONTROL_OE   BIT(2)
+
+#define SI514_MIN_FREQ 10U
+#define SI514_MAX_FREQ  25000U
+
+#define FXO  3198U
+
+#define FVCO_MIN   208000U
+#define FVCO_MAX   25U
+
+#define HS_DIV_MAX 1022
+
+struct clk_si514 

[PATCH v2 1/9] ARM: dts: rockchip: add core rk3036 dts

[Xing Zheng]

Initial release for rk3036, node definitions rk3036 sdk board.

Signed-off-by: Xing Zheng 
---

Changes in v2: None

 arch/arm/boot/dts/Makefile   |1 +
 arch/arm/boot/dts/rk3036-sdk.dts |   62 +++
 arch/arm/boot/dts/rk3036.dtsi|  381 ++
 3 files changed, 444 insertions(+)
 create mode 100644 arch/arm/boot/dts/rk3036-sdk.dts
 create mode 100644 arch/arm/boot/dts/rk3036.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d39ce4b..48260c4 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -502,6 +502,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3066a-bqcurie2.dtb \
rk3066a-marsboard.dtb \
rk3066a-rayeager.dtb \
+   rk3036-sdk.dtb \
rk3188-radxarock.dtb \
rk3288-evb-act8846.dtb \
rk3288-evb-rk808.dtb \
diff --git a/arch/arm/boot/dts/rk3036-sdk.dts b/arch/arm/boot/dts/rk3036-sdk.dts
new file mode 100644
index 000..9187f93
--- /dev/null
+++ b/arch/arm/boot/dts/rk3036-sdk.dts
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c)  2015 Xing Zheng 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk3036.dtsi"
+
+/ {
+   model = "SDK-RK3036";
+   compatible = "sdk,sdk-rk3036", "rockchip,rk3036";
+};
+
+ {
+   status = "okay";
+
+hym8563: hym8563@51 {
+   compatible = "haoyu,hym8563";
+   reg = <0x51>;
+   #clock-cells = <0>;
+   clock-frequency = <32768>;
+   clock-output-names = "xin32k";
+   };
+};
\ No newline at end of file
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
new file mode 100644
index 000..b7459c0
--- /dev/null
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -0,0 +1,381 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do 

Re: [RFC 0/2] drm/dsi: DSI for devices with different control bus

[Archit Taneja]

On 9/15/2015 9:13 PM, Rob Herring wrote:

On 09/15/2015 05:32 AM, Archit Taneja wrote:

Hi Rob, Mark,

We've been trying to figure out the right way to represent a class
of display encoder devices in DT.


I've been meaning to reply on this.


These devices have registers that are generally configured via i2c. Once
the device is configured, it takes in video data from the mipi
dsi bus.

Until now, all the devices we've supported devices that can be are
configured by the dsi bus itself, and hence, we've been able to
represent them in DT as children under the dsi host.

For the above class of devices (using both i2c and dsi), we aren't
able to conclude upon what's the better approach among the two:

1. Represent the device via 2 different nodes in DT. One would be
a child under an i2c adapter, the other a child of a dsi host. We
would have two device drivers, one i2c client, and the other a
mipi dsi device.

2. Represent the device as an i2c client in DT. Provide an api
to create "dummy" dsi devices. The i2c client driver would use
this api to register a dsi device, and link itself with the dsi
host.

What do you think would be the way to go here? I guess you
might have faced something similar in other subsystems.


The closest thing I can think of are WiFi/BT combo chips that use
SDIO+UART. In that case, 2 nodes makes sense as these chips are
essentially 2 independent functions in a single chip and both interfaces
are control interfaces (as well as data). This case is a bit different
with both interfaces being tied to the same function.

So in this case, I think option 2 is the right way for the reasons
already outlined in this thread. I think there needs to be more
consistency in how the of-graph connections are defined with the core
doing more of the graph traversing. So having an i2c device plus
of-graph seems more consistent with other non-DSI cases.

The main open issue seemed to be setting the VC. At least for the
ADV7533, it can be whatever you want it to be. The host and device just
need to agree. I see no need for that to be in DT at least in this case.
But then I'm not sure what are typical constraints for VC assignment.
I'd guess that constraints are on the device side and hosts can support
whatever the device wants. If so, then it can purely be up to the driver
to set.


2 DSI devices connected to the same host shouldn't have the same VC.
When representing the DSI nodes via DT, we use the 'reg' property to
assign the VC.

Although, in practice, we don't generally have multiple devices
on the same bus. The trend is to have multiple DSI hosts on the
platform to support more devices.

If we have checks that ensures the DT way and the new manual way
of creation of DSI devices doesn't result in having conflicting VCs
for devices, we should be okay.



Implementation-wise, I don't think that I'd call this a dummy device.
There are multiple ways for devices to get created in the driver model.
DT is just one way. You are just creating the device in a different way
outside of DT which is fine.



Thanks for the feedback.

Archit

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[PATCH v2 00/11] clocksource: sh_cmt: DT binding rework V2

[Magnus Damm]

clocksource: sh_cmt: DT binding rework V2

[PATCH v2 01/11] devicetree: bindings: Remove sh7372 CMT binding
[PATCH v2 02/11] clocksource: sh_cmt: Use 0x3f mask for SH_CMT_48BIT case
[PATCH v2 03/11] devicetree: bindings: R-Car Gen2 CMT0 and CMT1 bindings
[PATCH v2 04/11] clocksource: sh_cmt: Support separate R-Car Gen2 CMT0/1
[PATCH v2 05/11] devicetree: bindings: r8a73a4 and R-Car Gen2 CMT bindings
[PATCH v2 06/11] ARM: shmobile: Update CMT compat string users in DTS
[PATCH v2 07/11] devicetree: bindings: Deprecate property, update example
[PATCH v2 08/11] ARM: shmobile: Remove CMT renesas,channels-mask from DTS
[PATCH v2 09/11] devicetree: bindings: Remove unused 32-bit CMT bindings
[PATCH v2 10/11] clocksource: sh_cmt: Remove unused 32-bit CMT bindings
[PATCH v2 11/11] devicetree: bindings: Remove deprecated properties

This series reworks the CMT DT bindings to try to deal with the following:
- R-Car Gen2 CMT0 and CMT1 hardware instances are not identical
- The property renesas,channels-mask is not enough to describe the difference
- DT should describe the hardware, not the software implementation
- Not all documented DT bindings are actually used

Without these patches the binding "renesas,cmt-48-gen2" is used for both
CMT0 and CMT1 on R-Car Gen2 SoCs. CMT0 and CMT1 are currently seen by the
Linux device driver as compatible hardware, and the device-specific property
"renesas,channels-mask" is used to point out some of the hardware configuration
differences. Since the driver is not feature complete only some differences are
described and when diving into the data sheet we can see that:

1) CMT0 is not 48-bit at all, instead it only supports 32-bit counters.
2) Some channels of CMT1 are 48-bit, some 32-bit.
3) A couple of CMT1 channels have even more features.

It turns out that none of the above differences are described in our current
DT files. And since we use the same compat string for CMT0 and CMT1 the driver
itself cannot enable features specific only to CMT1 without first updating
the DTS. So this series is ground work for future feature patches.

It seems that we have two choices if we want to support CMT1 features:
A) Keep existing DT bindings, add more properties for CMT1
B) Rework the compatible strings and keep configuration in the driver

Judging by above it seems that DT update is inevitable. In my mind it is
rather painful to update the DT so I'd like to minimize the number of
updates and let the majority of the changes only happen in the driver.
And since we should really describe hardware in DT but driver features tend
to be implemented incrementally then B) seems like a good fit to me.

I wouldn't mind going with A) but to be honest I must say that the existing
compat string "renesas,cmt-48-gen2" is just too confusing with "48"
(when CMT0 is 32bit-only) and also "gen2" (used without product line R-Car).

Because of that I've gone with B) and reworked the bindings to separate
CMT0 from CMT1 and keep channel configuration in the device driver.

While at it I've deprecated "renesas,channels-mask" and the old DT compat
strings. Per-SoC compat strings have also been reworked, but are not left
around documented as deprecated since they were never used by the driver.

Comments are very welcome! If all are in favor then it would be good to
merge patch 1-5 first and patch 6-8 later once 1-5 are in. Old DTBs are
left working but treated as low-feature CMT0. New DTBs including patch 6
will not work on old kernels.

V2 patch series fixes patch 1-2 and adds patches 9, 10, 11.
Patch 9 and 10 cleans up r8a7740 and sh73a0 bindings.
Patch 11 removes deprecated properties as proposed by Laurent.

Many thanks to Geert and Laurent for feedback!

Signed-off-by: Magnus Damm 
Acked-by: Geert Uytterhoeven  (For patch 1-8)
Tested-by: Geert Uytterhoeven  (For patch 1-8)
Acked-by: Laurent Pinchart  (For patch 1-7)
---

 Written against renesas-drivers-2015-09-15-v4.3-rc1

 Documentation/devicetree/bindings/timer/renesas,cmt.txt |   85 ++-
 arch/arm/boot/dts/r8a73a4.dtsi  |5 
 arch/arm/boot/dts/r8a7740.dtsi  |3 
 arch/arm/boot/dts/r8a7790.dtsi  |   10 -
 arch/arm/boot/dts/r8a7791.dtsi  |   10 -
 arch/arm/boot/dts/r8a7793.dtsi  |   10 -
 arch/arm/boot/dts/r8a7794.dtsi  |   10 -
 arch/arm/boot/dts/sh73a0.dtsi   |3 
 drivers/clocksource/sh_cmt.c|   54 ++---
 9 files changed, 85 insertions(+), 105 deletions(-)
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[PATCH v2 11/11] scsi: ufs: Add exynos ufs platform data

[Alim Akhtar]

This adds ufs_hba_exynos_ops{} to platform data, so that
exynos ufs driver can be probed.

Signed-off-by: Alim Akhtar 
---
 drivers/scsi/ufs/ufshcd-pltfrm.c |2 ++
 drivers/scsi/ufs/ufshcd.h|1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/scsi/ufs/ufshcd-pltfrm.c b/drivers/scsi/ufs/ufshcd-pltfrm.c
index 7db9564..39dae76 100644
--- a/drivers/scsi/ufs/ufshcd-pltfrm.c
+++ b/drivers/scsi/ufs/ufshcd-pltfrm.c
@@ -373,6 +373,8 @@ static int ufshcd_pltfrm_remove(struct platform_device 
*pdev)
 
 static const struct of_device_id ufs_of_match[] = {
{ .compatible = "jedec,ufs-1.1"},
+   { .compatible = "samsung,exynos7-ufs",
+.data  = _hba_exynos_ops},
{},
 };
 
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 83fe605..15f2a7c 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -687,4 +687,5 @@ static inline int ufshcd_dme_peer_get(struct ufs_hba *hba,
 
 int ufshcd_hold(struct ufs_hba *hba, bool async);
 void ufshcd_release(struct ufs_hba *hba);
+extern const struct ufs_hba_variant_ops ufs_hba_exynos_ops;
 #endif /* End of Header */
-- 
1.7.10.4

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[PATCH v2 10/11] clocksource: sh_cmt: Remove unused 32-bit CMT bindings

[Magnus Damm]

From: Magnus Damm 

Remove the 32-bit CMT compat strings to reduce maintenance burden.

It should be fine to break DT compatibility because the 32-bit
32-bit CMT DT binding was never part of any upstream DTS file.

Signed-off-by: Magnus Damm 
---

 Changes since V1:
 - New patch

 drivers/clocksource/sh_cmt.c |2 --
 1 file changed, 2 deletions(-)

--- 0005/drivers/clocksource/sh_cmt.c
+++ work/drivers/clocksource/sh_cmt.c   2015-09-17 18:06:35.940513000 +0900
@@ -957,8 +957,6 @@ static const struct platform_device_id s
 MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
 
 static const struct of_device_id sh_cmt_of_table[] __maybe_unused = {
-   { .compatible = "renesas,cmt-32", .data = _cmt_info[SH_CMT_32BIT] },
-   { .compatible = "renesas,cmt-32-fast", .data = 
_cmt_info[SH_CMT_32BIT_FAST] },
{ .compatible = "renesas,cmt-48", .data = _cmt_info[SH_CMT_48BIT] },
{ .compatible = "renesas,cmt-48-gen2", .data = 
_cmt_info[SH_CMT0_RCAR_GEN2] },
{ .compatible = "renesas,cmt0-rcar-gen2", .data = 
_cmt_info[SH_CMT0_RCAR_GEN2] },
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[PATCH v2 08/11] scsi: ufs: make ufshcd_config_pwr_mode of non-static func

[Alim Akhtar]

From: Seungwon Jeon 

This makes ufshcd_config_pwr_mode non-static so that other vendors
like exynos can use the same.

Signed-off-by: Seungwon Jeon 
Signed-off-by: Alim Akhtar 
---
 drivers/scsi/ufs/ufshcd.c |5 ++---
 drivers/scsi/ufs/ufshcd.h |2 ++
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index ccf7c83..da52c45 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -185,8 +185,6 @@ static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba, 
bool en);
 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
 static irqreturn_t ufshcd_intr(int irq, void *__hba);
-static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
-   struct ufs_pa_layer_attr *desired_pwr_mode);
 static int ufshcd_change_power_mode(struct ufs_hba *hba,
 struct ufs_pa_layer_attr *pwr_mode);
 
@@ -2597,7 +2595,7 @@ static int ufshcd_change_power_mode(struct ufs_hba *hba,
  * @hba: per-adapter instance
  * @desired_pwr_mode: desired power configuration
  */
-static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
+int ufshcd_config_pwr_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr *desired_pwr_mode)
 {
struct ufs_pa_layer_attr final_params = { 0 };
@@ -2613,6 +2611,7 @@ static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
 
return ret;
 }
+EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
 
 /**
  * ufshcd_complete_dev_init() - checks device readiness
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 2fd0c3c..83fe605 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -636,6 +636,8 @@ extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 
attr_sel,
   u8 attr_set, u32 mib_val, u8 peer);
 extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
   u32 *mib_val, u8 peer);
+extern int ufshcd_config_pwr_mode(struct ufs_hba *hba,
+   struct ufs_pa_layer_attr *desired_pwr_mode);
 
 /* UIC command interfaces for DME primitives */
 #define DME_LOCAL  0
-- 
1.7.10.4

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[PATCH v2 11/11] devicetree: bindings: Remove deprecated properties

[Magnus Damm]

From: Magnus Damm 

The deprecated DT properies are part of the GIT history,
no need to keep them around any longer.

Signed-off-by: Magnus Damm 
---

 Changes since V1:
 - New patch

 Documentation/devicetree/bindings/timer/renesas,cmt.txt |4 
 1 file changed, 4 deletions(-)

--- 0011/Documentation/devicetree/bindings/timer/renesas,cmt.txt
+++ work/Documentation/devicetree/bindings/timer/renesas,cmt.txt
2015-09-17 18:08:17.000513000 +0900
@@ -35,8 +35,6 @@ Required Properties:
 - "renesas,cmt1-rcar-gen2" for 48-bit CMT1 devices included in R-Car Gen2.
These are fallbacks for r8a73a4 and all the R-Car Gen2
entries listed above.
-
-- "renesas,cmt-48-gen2" is , use "renesas,cmt[01]-*" instead.
 
   - reg: base address and length of the registers block for the timer module.
   - interrupts: interrupt-specifier for the timer, one per channel.
@@ -44,8 +42,6 @@ Required Properties:
 in clock-names.
   - clock-names: must contain "fck" for the functional clock.
 
-  - renesas,channels-mask: , information kept in device driver.
-
 
 Example: R8A7790 (R-Car H2) CMT0 and CMT1 nodes
 
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[PATCH v2 10/11] scsi: ufs-exynos: add UFS host support for Exynos SoCs

[Alim Akhtar]

From: Seungwon Jeon 

This patch introduces Exynos UFS host controller driver,
which mainly handles vendor-specific operations including
link startup, power mode change and hibernation/unhibernation.

Signed-off-by: Seungwon Jeon 
Signed-off-by: Alim Akhtar 
---
 .../devicetree/bindings/ufs/ufs-exynos.txt |   93 ++
 drivers/scsi/ufs/Kconfig   |   12 +
 drivers/scsi/ufs/Makefile  |1 +
 drivers/scsi/ufs/ufs-exynos-hw.c   |  147 +++
 drivers/scsi/ufs/ufs-exynos-hw.h   |   43 +
 drivers/scsi/ufs/ufs-exynos.c  | 1173 
 drivers/scsi/ufs/ufs-exynos.h  |  463 
 drivers/scsi/ufs/ufshci.h  |   26 +-
 drivers/scsi/ufs/unipro.h  |   47 +
 9 files changed, 2004 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt
 create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c
 create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h
 create mode 100644 drivers/scsi/ufs/ufs-exynos.c
 create mode 100644 drivers/scsi/ufs/ufs-exynos.h

diff --git a/Documentation/devicetree/bindings/ufs/ufs-exynos.txt 
b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
new file mode 100644
index 000..188a240
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/ufs-exynos.txt
@@ -0,0 +1,93 @@
+* Exynos Universal Flash Storage (UFS) Host Controller
+
+UFSHC nodes are defined to describe on-chip UFS host controllers.
+Each UFS controller instance should have its own node.
+
+Required properties:
+- compatible: compatible list, contains "samsung,exynos7-ufs"
+- interrupts: 
+- reg   : 
+
+Optional properties:
+- vdd-hba-supply: phandle to UFS host controller supply regulator node
+- vcc-supply: phandle to VCC supply regulator node
+- vccq-supply   : phandle to VCCQ supply regulator node
+- vccq2-supply  : phandle to VCCQ2 supply regulator node
+- vcc-supply-1p8: For embedded UFS devices, valid VCC range is 
1.7-1.95V
+  or 2.7-3.6V. This boolean property when set, 
specifies
+ to use low voltage range of 1.7-1.95V. Note for 
external
+ UFS cards this property is invalid and valid VCC 
range is
+ always 2.7-3.6V.
+- vcc-max-microamp  : specifies max. load that can be drawn from vcc supply
+- vccq-max-microamp : specifies max. load that can be drawn from vccq 
supply
+- vccq2-max-microamp: specifies max. load that can be drawn from vccq2 
supply
+- -fixed-regulator : boolean property specifying that -supply is a 
fixed regulator
+
+- clocks: List of phandle and clock specifier pairs
+- clock-names   : List of clock input name strings sorted in the same
+  order as the clocks property.
+- freq-table-hz: Array of  operating frequencies 
stored in the same
+  order as the clocks property. If this property is not
+ defined or a value in the array is "0" then it is 
assumed
+ that the frequency is set by the parent clock or a
+ fixed rate clock source.
+- pclk-freq-avail-range : specifies available frequency range(min/max) for APB 
clock
+- ufs,pwr-attr-mode : specifies mode value for power mode change
+- ufs,pwr-attr-lane : specifies lane count value for power mode change
+- ufs,pwr-attr-gear : specifies gear count value for power mode change
+- ufs,pwr-attr-hs-series : specifies HS rate series for power mode change
+- ufs,pwr-local-l2-timer : specifies array of local UNIPRO L2 timer values
+  
+- ufs,pwr-remote-l2-timer : specifies array of remote UNIPRO L2 timer values
+  
+- ufs-rx-adv-fine-gran-sup_en : specifies support of fine granularity of MPHY,
+ this is a boolean property.
+- ufs-rx-adv-fine-gran-step : specifies granularity steps of MPHY
+- ufs-rx-adv-min-activate-time-cap : specifies rx advanced minimum activate 
time of MPHY
+- ufs-pa-granularity : specifies Granularity for PA_TActivate and 
PA_Hibern8Time
+- ufs-pa-tacctivate : specifies time wake-up remote M-RX
+- ufs-pa-hibern8time : specifies minimum time to wait in HIBERN8 state
+
+Note: If above properties are not defined it can be assumed that the supply
+regulators or clocks are always on.
+
+Example:
+   ufshc@0x1557 {
+   compatible = "samsung,exynos7-ufs";
+   reg = <0xfc598000 0x800>;
+   reg = <0x1557 0x100>,
+ <0x15570100 0x100>,
+ 

[PATCH v2 09/11] scsi: ufs: return value of pwr_change_notify

[Alim Akhtar]

From: Seungwon Jeon 

Behavior of the "power mode change" contains vendor specific
operation known as pwr_change_notify. This change adds return
for pwr_change_notify to find success or failure.

Signed-off-by: Seungwon Jeon 
Signed-off-by: Alim Akhtar 
---
 drivers/scsi/ufs/ufshcd.c |   22 +++---
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index da52c45..0c9f319 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -2579,14 +2579,18 @@ static int ufshcd_change_power_mode(struct ufs_hba *hba,
dev_err(hba->dev,
"%s: power mode change failed %d\n", __func__, ret);
} else {
-   if (hba->vops && hba->vops->pwr_change_notify)
-   hba->vops->pwr_change_notify(hba,
-   POST_CHANGE, NULL, pwr_mode);
+   if (hba->vops && hba->vops->pwr_change_notify) {
+   ret = hba->vops->pwr_change_notify(hba,
+   POST_CHANGE, NULL, pwr_mode);
+   if (ret)
+   goto out;
+   }
 
memcpy(>pwr_info, pwr_mode,
sizeof(struct ufs_pa_layer_attr));
}
 
+out:
return ret;
 }
 
@@ -2601,14 +2605,18 @@ int ufshcd_config_pwr_mode(struct ufs_hba *hba,
struct ufs_pa_layer_attr final_params = { 0 };
int ret;
 
-   if (hba->vops && hba->vops->pwr_change_notify)
-   hba->vops->pwr_change_notify(hba,
-PRE_CHANGE, desired_pwr_mode, _params);
-   else
+   if (hba->vops && hba->vops->pwr_change_notify) {
+   ret = hba->vops->pwr_change_notify(hba,
+   PRE_CHANGE, desired_pwr_mode, _params);
+   if (ret)
+   goto out;
+   } else {
memcpy(_params, desired_pwr_mode, sizeof(final_params));
+   }
 
ret = ufshcd_change_power_mode(hba, _params);
 
+out:
return ret;
 }
 EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
-- 
1.7.10.4

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[PATCH v2 04/11] scsi: ufs: add quirk not to allow reset of interrupt aggregation

[Alim Akhtar]

From: Seungwon Jeon 

Some host controller supports interrupt aggregation, but doesn't
allow to reset counter and timer by s/w.

Signed-off-by: Seungwon Jeon 
Signed-off-by: Alim Akhtar 
---
 drivers/scsi/ufs/ufshcd.c |3 ++-
 drivers/scsi/ufs/ufshcd.h |6 ++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 257bffc..7b87075 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -3204,7 +3204,8 @@ static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
 * false interrupt if device completes another request after resetting
 * aggregation and before reading the DB.
 */
-   if (ufshcd_is_intr_aggr_allowed(hba))
+   if (ufshcd_is_intr_aggr_allowed(hba) &&
+   !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
ufshcd_reset_intr_aggr(hba);
 
tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index ba38842..c59f8ae 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -471,6 +471,12 @@ struct ufs_hba {
 */
#define UFSHCI_QUIRK_BROKEN_REQ_LIST_CLRUFS_BIT(7)
 
+   /*
+* This quirk needs to be enabled if host controller doesn't allow
+* that the interrupt aggregation timer and counter are reset by s/w.
+*/
+   #define UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR   UFS_BIT(8)
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
 
wait_queue_head_t tm_wq;
-- 
1.7.10.4

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[PATCH v2 03/11] scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr

[Alim Akhtar]

From: Seungwon Jeon 

In the right behavior, setting the bit to '0' indicates clear and
'1' indicates no change. If host contoller handles this the other way,
UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR can be used.

Signed-off-by: Seungwon Jeon 
Signed-off-by: Alim Akhtar 
---
 drivers/scsi/ufs/ufshcd.c |   20 ++--
 drivers/scsi/ufs/ufshcd.h |5 +
 2 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 90f76e7..257bffc 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -358,7 +358,23 @@ static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, 
int slot)
  */
 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
 {
-   ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+   if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
+   ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+   else
+   ufshcd_writel(hba, ~(1 << pos), 
REG_UTP_TRANSFER_REQ_LIST_CLEAR);
+}
+
+/**
+ * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
+ * @hba: per adapter instance
+ * @pos: position of the bit to be cleared
+ */
+static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
+{
+   if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
+   ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
+   else
+   ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
 }
 
 /**
@@ -3691,7 +3707,7 @@ static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int 
tag)
goto out;
 
spin_lock_irqsave(hba->host->host_lock, flags);
-   ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
+   ufshcd_utmrl_clear(hba, tag);
spin_unlock_irqrestore(hba->host->host_lock, flags);
 
/* poll for max. 1 sec to clear door bell register by h/w */
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 9ed4c9e..ba38842 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -466,6 +466,11 @@ struct ufs_hba {
 */
#define UFSHCI_QUIRK_BYTE_ALIGN_UTRDUFS_BIT(6)
 
+   /*
+* Cleaer handling for transfer/task request list is just opposite.
+*/
+   #define UFSHCI_QUIRK_BROKEN_REQ_LIST_CLRUFS_BIT(7)
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
 
wait_queue_head_t tm_wq;
-- 
1.7.10.4

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[PATCH v2 07/11] scsi: ufs: add add specific callback for hibern8

[Alim Akhtar]

From: Seungwon Jeon 

Some host controller needs specific handling before/after
(un)hibernation, This change adds specific callback function
to support vendor's implementation.

Signed-off-by: Seungwon Jeon 
Signed-off-by: Alim Akhtar 
---
 drivers/scsi/ufs/ufshcd.c |   36 
 drivers/scsi/ufs/ufshcd.h |3 +++
 2 files changed, 35 insertions(+), 4 deletions(-)

diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 2f0de4b..ccf7c83 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -181,8 +181,7 @@ static int ufshcd_probe_hba(struct ufs_hba *hba);
 static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
 bool skip_ref_clk);
 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
-static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
-static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
+static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba, bool en);
 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
 static irqreturn_t ufshcd_intr(int irq, void *__hba);
@@ -215,6 +214,16 @@ static inline void ufshcd_disable_irq(struct ufs_hba *hba)
}
 }
 
+static inline int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
+{
+   return ufshcd_uic_hibern8_ctrl(hba, true);
+}
+
+static inline int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
+{
+   return ufshcd_uic_hibern8_ctrl(hba, false);
+}
+
 /*
  * ufshcd_wait_for_register - wait for register value to change
  * @hba - per-adapter interface
@@ -2395,7 +2404,7 @@ out:
return ret;
 }
 
-static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
+static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
 {
struct uic_command uic_cmd = {0};
 
@@ -2404,7 +2413,7 @@ static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
return ufshcd_uic_pwr_ctrl(hba, _cmd);
 }
 
-static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
+static int __ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
 {
struct uic_command uic_cmd = {0};
int ret;
@@ -2419,6 +2428,25 @@ static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
return ret;
 }
 
+static int ufshcd_uic_hibern8_ctrl(struct ufs_hba *hba, bool en)
+{
+   int ret;
+
+   if (hba->vops && hba->vops->hibern8_notify)
+   hba->vops->hibern8_notify(hba, en, PRE_CHANGE);
+
+   ret = en ? __ufshcd_uic_hibern8_enter(hba) :
+   __ufshcd_uic_hibern8_exit(hba);
+   if (ret)
+   goto out;
+
+   if (hba->vops && hba->vops->hibern8_notify)
+   hba->vops->hibern8_notify(hba, en, POST_CHANGE);
+
+out:
+   return ret;
+}
+
  /**
  * ufshcd_init_pwr_info - setting the POR (power on reset)
  * values in hba power info
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 149d74e..2fd0c3c 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -260,6 +260,8 @@ struct ufs_pwr_mode_info {
  * @specify_nexus_t_xfer_req:
  * @specify_nexus_t_tm_req: called before command is issued to allow vendor
  * specific handling to be set for nexus type.
+ * @hibern8_notify: called before and after hibernate/unhibernate is carried 
out
+ * to allow vendor spesific implementation.
  * @suspend: called during host controller PM callback
  * @resume: called during host controller PM callback
  */
@@ -276,6 +278,7 @@ struct ufs_hba_variant_ops {
int (*pwr_change_notify)(struct ufs_hba *,
bool, struct ufs_pa_layer_attr *,
struct ufs_pa_layer_attr *);
+   void(*hibern8_notify)(struct ufs_hba *, bool, bool);
void(*specify_nexus_t_xfer_req)(struct ufs_hba *,
int, struct scsi_cmnd *);
void(*specify_nexus_t_tm_req)(struct ufs_hba *, int, u8);
-- 
1.7.10.4

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[PATCH v2 05/11] scsi: ufs: add quirk to enable host controller without hce

[Alim Akhtar]

From: Seungwon Jeon 

Some host controller doesn't support host controller enable via HCE.

Signed-off-by: Seungwon Jeon 
Signed-off-by: Alim Akhtar 
---
 drivers/scsi/ufs/ufshcd.c |   76 +++--
 drivers/scsi/ufs/ufshcd.h |5 +++
 2 files changed, 79 insertions(+), 2 deletions(-)

diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 7b87075..0fcfa71 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -2106,6 +2106,52 @@ static int ufshcd_dme_link_startup(struct ufs_hba *hba)
"dme-link-startup: error code %d\n", ret);
return ret;
 }
+/**
+ * ufshcd_dme_reset - UIC command for DME_RESET
+ * @hba: per adapter instance
+ *
+ * DME_RESET command is issued in order to reset UniPro stack.
+ * This function now deal with cold reset.
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static int ufshcd_dme_reset(struct ufs_hba *hba)
+{
+   struct uic_command uic_cmd = {0};
+   int ret;
+
+   uic_cmd.command = UIC_CMD_DME_RESET;
+
+   ret = ufshcd_send_uic_cmd(hba, _cmd);
+   if (ret)
+   dev_err(hba->dev,
+   "dme-reset: error code %d\n", ret);
+
+   return ret;
+}
+
+/**
+ * ufshcd_dme_enable - UIC command for DME_ENABLE
+ * @hba: per adapter instance
+ *
+ * DME_ENABLE command is issued in order to enable UniPro stack.
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static int ufshcd_dme_enable(struct ufs_hba *hba)
+{
+   struct uic_command uic_cmd = {0};
+   int ret;
+
+   uic_cmd.command = UIC_CMD_DME_ENABLE;
+
+   ret = ufshcd_send_uic_cmd(hba, _cmd);
+   if (ret)
+   dev_err(hba->dev,
+   "dme-reset: error code %d\n", ret);
+
+   return ret;
+}
 
 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
 {
@@ -2642,7 +2688,7 @@ out:
 }
 
 /**
- * ufshcd_hba_enable - initialize the controller
+ * ufshcd_hba_execute_hce - initialize the controller
  * @hba: per adapter instance
  *
  * The controller resets itself and controller firmware initialization
@@ -2651,7 +2697,7 @@ out:
  *
  * Returns 0 on success, non-zero value on failure
  */
-static int ufshcd_hba_enable(struct ufs_hba *hba)
+static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
 {
int retry;
 
@@ -2717,6 +2763,32 @@ static int ufshcd_hba_enable(struct ufs_hba *hba)
return 0;
 }
 
+static int ufshcd_hba_enable(struct ufs_hba *hba)
+{
+   int ret;
+
+   if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
+   ufshcd_set_link_off(hba);
+   if (hba->vops && hba->vops->hce_enable_notify)
+   hba->vops->hce_enable_notify(hba, PRE_CHANGE);
+
+   /* enable UIC related interrupts */
+   ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
+   ret = ufshcd_dme_reset(hba);
+   if (!ret) {
+   ret = ufshcd_dme_enable(hba);
+   if (!ret && hba->vops && hba->vops->hce_enable_notify)
+   hba->vops->hce_enable_notify(hba, POST_CHANGE);
+   if (ret)
+   dev_err(hba->dev,
+   "Host controller enable failed with 
non-hce\n");
+   }
+   } else {
+   ret = ufshcd_hba_execute_hce(hba);
+   }
+
+   return ret;
+}
 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
 {
int tx_lanes, i, err = 0;
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index c59f8ae..c6dc107 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -477,6 +477,11 @@ struct ufs_hba {
 */
#define UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR   UFS_BIT(8)
 
+   /*
+* This quirks needs to be enabled if host controller cannot be
+* enabled via HCE register.
+*/
+   #define UFSHCI_QUIRK_BROKEN_HCE UFS_BIT(9)
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
 
wait_queue_head_t tm_wq;
-- 
1.7.10.4

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Re: [PATCH v2 0/9] Build and support rk3036 SoC platform

[Heiko Stübner]

Hi,

Am Donnerstag, 17. September 2015, 16:28:51 schrieb Xing Zheng:
> we need to support rk3036 soc platform via upstream, there are
> 3 primary parts for the initial release of minimum system: dts,
> pinctrl, and clock tree for rk3036, and additional, add a rtc
> hym8563 patch to fix initial invaild, we can use these startup
> and run to init processs.
> 
> Thanks.
> 
> changed in v2:
> - based on v1, add clock controller documentation
> - enable timer5 startup
> - add smp for cpu1
> - initial set time for rtc-hym8563
> 
> changes since v1:
> - add dts, pinctrl and clock tree for rk3036 soc platform
> 
> The patchset (9):
> 9) rtc: hym8563: make sure hym8563 can be normal work
> 8) ARM: rockchip: add support smp for rk3036
> 7) rockchip: make sure timer5 is enabled on rk3036 platforms
> 6) pinctrl: rockchip: add support for the rk3036
> 5) dt-bindings: add documentation of rk3036 clock controller
> 4) clk: rockchip: add new clock type and controller for rk3036
> 3) clk: rockchip: add clock controller for rk3036
> 2) clk: rockchip: add dt-binding header for rk3036
> 1) ARM: dts: rockchip: add core rk3036 dts
> 
> 
> Changes in v2:
> Signed-off-by: Xing Zheng 
> 
> Xing Zheng (9):
>   ARM: dts: rockchip: add core rk3036 dts
>   clk: rockchip: add dt-binding header for rk3036
>   clk: rockchip: add clock controller for rk3036
>   clk: rockchip: add new clock type and controller for rk3036
>   dt-bindings: add documentation of rk3036 clock controller
>   pinctrl: rockchip: add support for the rk3036
>   rockchip: make sure timer5 is enabled on rk3036 platforms
>   ARM: rockchip: add support smp for rk3036
>   rtc: hym8563: make sure hym8563 can be normal work

am I missing some patches? I only got patches 1-4.

Anyway, you should reorder a bit

- whatever other patches are necessary before
- dt-bindings: add documentation of rk3036 clock controller
- clk: rockchip: add dt-binding header for rk3036
- clk: rockchip: add new pll type for rk3036
-  clk: rockchip: add clock controller for rk3036
- ARM: dts: rockchip: add core rk3036 dts

The dts patch for example depends on the clock-header, so it really should 
come after its addition.


Heiko

> 
>  .../bindings/clock/rockchip,rk3036-cru.txt |   60 +++
>  .../bindings/pinctrl/rockchip,pinctrl.txt  |1 +
>  arch/arm/boot/dts/Makefile |1 +
>  arch/arm/boot/dts/rk3036-sdk.dts   |   62 +++
>  arch/arm/boot/dts/rk3036.dtsi  |  381 +++
>  arch/arm/mach-rockchip/platsmp.c   |  121 +
>  arch/arm/mach-rockchip/rockchip.c  |   22 +
>  drivers/clk/rockchip/Makefile  |1 +
>  drivers/clk/rockchip/clk-pll.c |  262 +-
>  drivers/clk/rockchip/clk-rk3036.c  |  504
>  drivers/clk/rockchip/clk.h |  
> 30 ++
>  drivers/pinctrl/pinctrl-rockchip.c |   17 +
>  drivers/rtc/rtc-hym8563.c  |   93 
>  include/dt-bindings/clock/rk3036-cru.h |  198 
>  14 files changed, 1752 insertions(+), 1 deletion(-)
>  create mode 100644
> Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt create mode
> 100644 arch/arm/boot/dts/rk3036-sdk.dts
>  create mode 100644 arch/arm/boot/dts/rk3036.dtsi
>  create mode 100644 drivers/clk/rockchip/clk-rk3036.c
>  create mode 100644 include/dt-bindings/clock/rk3036-cru.h

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Re: [PATCH v2 10/11] clocksource: sh_cmt: Remove unused 32-bit CMT bindings

[Geert Uytterhoeven]

On Thu, Sep 17, 2015 at 11:55 AM, Magnus Damm  wrote:
> From: Magnus Damm 
>
> Remove the 32-bit CMT compat strings to reduce maintenance burden.
>
> It should be fine to break DT compatibility because the 32-bit
> 32-bit CMT DT binding was never part of any upstream DTS file.
>
> Signed-off-by: Magnus Damm 

Acked-by: Geert Uytterhoeven 

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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[PATCH v2 06/11] scsi: ufs: add specific callback for nexus type

[Alim Akhtar]

From: Seungwon Jeon 

Some host controller needs nexus type information for handling
command. This change adds specific callback function to support
vendor's implementation.

Signed-off-by: Seungwon Jeon 
Signed-off-by: Alim Akhtar 
---
 drivers/scsi/ufs/ufshcd.c |6 ++
 drivers/scsi/ufs/ufshcd.h |6 ++
 2 files changed, 12 insertions(+)

diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 0fcfa71..2f0de4b 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -1377,6 +1377,8 @@ static int ufshcd_queuecommand(struct Scsi_Host *host, 
struct scsi_cmnd *cmd)
 
/* issue command to the controller */
spin_lock_irqsave(hba->host->host_lock, flags);
+   if (hba->vops && hba->vops->specify_nexus_t_xfer_req)
+   hba->vops->specify_nexus_t_xfer_req(hba, tag, lrbp->cmd);
ufshcd_send_command(hba, tag);
 out_unlock:
spin_unlock_irqrestore(hba->host->host_lock, flags);
@@ -1577,6 +1579,8 @@ static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
hba->dev_cmd.complete = 
 
spin_lock_irqsave(hba->host->host_lock, flags);
+   if (hba->vops && hba->vops->specify_nexus_t_xfer_req)
+   hba->vops->specify_nexus_t_xfer_req(hba, tag, lrbp->cmd);
ufshcd_send_command(hba, tag);
spin_unlock_irqrestore(hba->host->host_lock, flags);
 
@@ -3848,6 +3852,8 @@ static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int 
lun_id, int task_id,
task_req_upiup->input_param2 = cpu_to_be32(task_id);
 
/* send command to the controller */
+   if (hba->vops && hba->vops->specify_nexus_t_tm_req)
+   hba->vops->specify_nexus_t_tm_req(hba, free_slot, tm_function);
__set_bit(free_slot, >outstanding_tasks);
ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
 
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index c6dc107..149d74e 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -257,6 +257,9 @@ struct ufs_pwr_mode_info {
  * @pwr_change_notify: called before and after a power mode change
  * is carried out to allow vendor spesific capabilities
  * to be set.
+ * @specify_nexus_t_xfer_req:
+ * @specify_nexus_t_tm_req: called before command is issued to allow vendor
+ * specific handling to be set for nexus type.
  * @suspend: called during host controller PM callback
  * @resume: called during host controller PM callback
  */
@@ -273,6 +276,9 @@ struct ufs_hba_variant_ops {
int (*pwr_change_notify)(struct ufs_hba *,
bool, struct ufs_pa_layer_attr *,
struct ufs_pa_layer_attr *);
+   void(*specify_nexus_t_xfer_req)(struct ufs_hba *,
+   int, struct scsi_cmnd *);
+   void(*specify_nexus_t_tm_req)(struct ufs_hba *, int, u8);
int (*suspend)(struct ufs_hba *, enum ufs_pm_op);
int (*resume)(struct ufs_hba *, enum ufs_pm_op);
 };
-- 
1.7.10.4

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Re: [PATCH v2 09/11] devicetree: bindings: Remove unused 32-bit CMT bindings

[Geert Uytterhoeven]

On Thu, Sep 17, 2015 at 11:54 AM, Magnus Damm  wrote:
> From: Magnus Damm 
>
> Remove the 32-bit CMT compat strings to reduce maintenance burden.
>
> It should be fine to break DT compatibility because the 32-bit
> 32-bit CMT DT binding was never part of any upstream DTS file.
>
> Signed-off-by: Magnus Damm 

Acked-by: Geert Uytterhoeven 

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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[PATCH v2 08/11] ARM: shmobile: Remove CMT renesas,channels-mask from DTS

[Magnus Damm]

From: Magnus Damm 

Update the DTS to remove the now deprecated "renesas,channels-mask" property.

The channel information is now kept in the device driver and can easily
be determined based on the compat string.

Signed-off-by: Magnus Damm 
Acked-by: Geert Uytterhoeven 
Tested-by: Geert Uytterhoeven 
---

 Changes since V1:
 - Rebased on top of power-domain changes
 - Added Acked-by and Tested-by from Geert

 arch/arm/boot/dts/r8a73a4.dtsi |3 ---
 arch/arm/boot/dts/r8a7740.dtsi |3 ---
 arch/arm/boot/dts/r8a7790.dtsi |6 --
 arch/arm/boot/dts/r8a7791.dtsi |6 --
 arch/arm/boot/dts/r8a7793.dtsi |6 --
 arch/arm/boot/dts/r8a7794.dtsi |6 --
 arch/arm/boot/dts/sh73a0.dtsi  |3 ---
 7 files changed, 33 deletions(-)

--- 0010/arch/arm/boot/dts/r8a73a4.dtsi
+++ work/arch/arm/boot/dts/r8a73a4.dtsi 2015-09-17 17:41:05.250513000 +0900
@@ -120,9 +120,6 @@
clocks = <_clks R8A73A4_CLK_CMT1>;
clock-names = "fck";
power-domains = <_c5>;
-
-   renesas,channels-mask = <0xff>;
-
status = "disabled";
};
 
--- 0001/arch/arm/boot/dts/r8a7740.dtsi
+++ work/arch/arm/boot/dts/r8a7740.dtsi 2015-09-17 17:41:05.250513000 +0900
@@ -60,9 +60,6 @@
clocks = <_clks R8A7740_CLK_CMT1>;
clock-names = "fck";
power-domains = <_c5>;
-
-   renesas,channels-mask = <0x3f>;
-
status = "disabled";
};
 
--- 0010/arch/arm/boot/dts/r8a7790.dtsi
+++ work/arch/arm/boot/dts/r8a7790.dtsi 2015-09-17 17:45:02.110513000 +0900
@@ -226,9 +226,6 @@
clocks = <_clks R8A7790_CLK_CMT0>;
clock-names = "fck";
power-domains = <_clocks>;
-
-   renesas,channels-mask = <0x60>;
-
status = "disabled";
};
 
@@ -246,9 +243,6 @@
clocks = <_clks R8A7790_CLK_CMT1>;
clock-names = "fck";
power-domains = <_clocks>;
-
-   renesas,channels-mask = <0xff>;
-
status = "disabled";
};
 
--- 0010/arch/arm/boot/dts/r8a7791.dtsi
+++ work/arch/arm/boot/dts/r8a7791.dtsi 2015-09-17 17:44:54.210513000 +0900
@@ -209,9 +209,6 @@
clocks = <_clks R8A7791_CLK_CMT0>;
clock-names = "fck";
power-domains = <_clocks>;
-
-   renesas,channels-mask = <0x60>;
-
status = "disabled";
};
 
@@ -229,9 +226,6 @@
clocks = <_clks R8A7791_CLK_CMT1>;
clock-names = "fck";
power-domains = <_clocks>;
-
-   renesas,channels-mask = <0xff>;
-
status = "disabled";
};
 
--- 0010/arch/arm/boot/dts/r8a7793.dtsi
+++ work/arch/arm/boot/dts/r8a7793.dtsi 2015-09-17 17:44:48.400513000 +0900
@@ -69,9 +69,6 @@
clocks = <_clks R8A7793_CLK_CMT0>;
clock-names = "fck";
power-domains = <_clocks>;
-
-   renesas,channels-mask = <0x60>;
-
status = "disabled";
};
 
@@ -89,9 +86,6 @@
clocks = <_clks R8A7793_CLK_CMT1>;
clock-names = "fck";
power-domains = <_clocks>;
-
-   renesas,channels-mask = <0xff>;
-
status = "disabled";
};
 
--- 0010/arch/arm/boot/dts/r8a7794.dtsi
+++ work/arch/arm/boot/dts/r8a7794.dtsi 2015-09-17 17:44:43.300513000 +0900
@@ -161,9 +161,6 @@
clocks = <_clks R8A7794_CLK_CMT0>;
clock-names = "fck";
power-domains = <_clocks>;
-
-   renesas,channels-mask = <0x60>;
-
status = "disabled";
};
 
@@ -181,9 +178,6 @@
clocks = <_clks R8A7794_CLK_CMT1>;
clock-names = "fck";
power-domains = <_clocks>;
-
-   renesas,channels-mask = <0xff>;
-
status = "disabled";
};
 
--- 0001/arch/arm/boot/dts/sh73a0.dtsi
+++ work/arch/arm/boot/dts/sh73a0.dtsi  2015-09-17 17:44:32.950513000 +0900
@@ -84,9 +84,6 @@
clocks = <_clks SH73A0_CLK_CMT1>;
clock-names = "fck";
power-domains = <_c5>;
-
-   renesas,channels-mask = <0x3f>;
-
status = "disabled";
};
 
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[PATCH v2 01/11] phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC

[Alim Akhtar]

From: Seungwon Jeon 

This patch introduces Exynos UFS PHY driver. This driver
supports to deal with phy calibration and power control
according to UFS host driver's behavior.

Signed-off-by: Seungwon Jeon 
Signed-off-by: Alim Akhtar 
Cc: Kishon Vijay Abraham I 
---
 .../devicetree/bindings/phy/samsung-phy.txt|   22 ++
 drivers/phy/Kconfig|7 +
 drivers/phy/Makefile   |1 +
 drivers/phy/phy-exynos-ufs.c   |  262 
 drivers/phy/phy-exynos-ufs.h   |   85 +++
 drivers/phy/phy-exynos7-ufs.h  |   89 +++
 include/linux/phy/phy-exynos-ufs.h |  107 
 7 files changed, 573 insertions(+)
 create mode 100644 drivers/phy/phy-exynos-ufs.c
 create mode 100644 drivers/phy/phy-exynos-ufs.h
 create mode 100644 drivers/phy/phy-exynos7-ufs.h
 create mode 100644 include/linux/phy/phy-exynos-ufs.h

diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt 
b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 60c6f2a..1abe2c4 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -174,3 +174,25 @@ Example:
usbdrdphy0 = _phy0;
usbdrdphy1 = _phy1;
};
+
+Samsung Exynos7 soc serise UFS PHY Controller
+-
+
+UFS PHY nodes are defined to describe on-chip UFS Physical layer controllers.
+Each UFS PHY controller should have its own node.
+
+Required properties:
+- compatible: compatible list, contains "samsung,exynos7-ufs-phy"
+- reg : offset and length of the UFS PHY register set;
+- reg-names : reg name(s) must be 'phy-pma';
+- #phy-cells : must be zero
+- samsung,syscon-phandle : a phandle to the PMU system controller, no arguments
+
+Example:
+   ufs_phy: ufs-phy@0x15571800 {
+   compatible = "samsung,exynos7-ufs-phy";
+   reg = <0x15571800 0x240>;
+   reg-names = "phy-pma";
+   samsung,syscon-phandle = <_system_controller>;
+   #phy-cells = <0>;
+   };
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 6b8dd16..7449376 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -358,4 +358,11 @@ config PHY_BRCMSTB_SATA
  Enable this to support the SATA3 PHY on 28nm Broadcom STB SoCs.
  Likely useful only with CONFIG_SATA_BRCMSTB enabled.
 
+config PHY_EXYNOS_UFS
+   tristate "EXYNOS SoC series UFS PHY driver"
+   depends on OF && ARCH_EXYNOS
+   select GENERIC_PHY
+   help
+ Support for UFS PHY on Samsung EXYNOS chipsets.
+
 endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f344e1b..7a36818 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -45,3 +45,4 @@ obj-$(CONFIG_PHY_QCOM_UFS)+= phy-qcom-ufs-qmp-14nm.o
 obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o
 obj-$(CONFIG_PHY_BRCMSTB_SATA) += phy-brcmstb-sata.o
 obj-$(CONFIG_PHY_PISTACHIO_USB)+= phy-pistachio-usb.o
+obj-$(CONFIG_PHY_EXYNOS_UFS)   += phy-exynos-ufs.o
diff --git a/drivers/phy/phy-exynos-ufs.c b/drivers/phy/phy-exynos-ufs.c
new file mode 100644
index 000..7d24610
--- /dev/null
+++ b/drivers/phy/phy-exynos-ufs.c
@@ -0,0 +1,262 @@
+/*
+ * UFS PHY driver for Samsung EXYNOS SoC
+ *
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ * Author: Seungwon Jeon 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "phy-exynos-ufs.h"
+
+#define for_each_phy_lane(phy, i) \
+   for (i = 0; i < (phy)->lane_cnt; i++)
+#define for_each_phy_cfg(cfg) \
+   for (; (cfg)->id; (cfg)++)
+
+#define phy_pma_writel(phy, val, reg) \
+   writel((val), (phy)->reg_pma + (reg))
+#define phy_pma_readl(phy, reg) \
+   readl((phy)->reg_pma + (reg))
+
+#define PHY_DEF_LANE_CNT   1
+
+static void exynos_ufs_phy_config(struct exynos_ufs_phy *phy,
+   const struct exynos_ufs_phy_cfg *cfg, u8 lane)
+{
+   enum {LANE_0, LANE_1}; /* lane index */
+
+   switch (lane) {
+   case LANE_0:
+   phy_pma_writel(phy, cfg->val, cfg->off_0);
+   break;
+   case LANE_1:
+   if (cfg->id == PHY_TRSV_BLK)
+   phy_pma_writel(phy, cfg->val, cfg->off_1);
+   break;
+   }
+}
+
+static bool match_cfg_to_pwr_mode(u8 desc, u8 required_pwr)
+{
+   if (IS_PWR_MODE_ANY(desc))
+   return true;
+

[PATCH v2 07/11] devicetree: bindings: Deprecate property, update example

[Magnus Damm]

From: Magnus Damm 

Deprecate "renesas,channels-mask" and update the r8a7790 CMT example.

Signed-off-by: Magnus Damm 
Acked-by: Geert Uytterhoeven 
Tested-by: Geert Uytterhoeven 
Acked-by: Laurent Pinchart 
---

 Changes since V1:
 - Added Acked-by and Tested-by from Geert
 - Added Acked-by from Laurent

 Documentation/devicetree/bindings/timer/renesas,cmt.txt |   24 ++-
 1 file changed, 17 insertions(+), 7 deletions(-)

--- 0009/Documentation/devicetree/bindings/timer/renesas,cmt.txt
+++ work/Documentation/devicetree/bindings/timer/renesas,cmt.txt
2015-09-17 17:39:47.080513000 +0900
@@ -60,21 +60,31 @@ Required Properties:
 in clock-names.
   - clock-names: must contain "fck" for the functional clock.
 
-  - renesas,channels-mask: bitmask of the available channels.
+  - renesas,channels-mask: , information kept in device driver.
 
 
-Example: R8A7790 (R-Car H2) CMT0 node
-
-   CMT0 on R8A7790 implements hardware channels 5 and 6 only and names
-   them channels 0 and 1 in the documentation.
+Example: R8A7790 (R-Car H2) CMT0 and CMT1 nodes
 
cmt0: timer@ffca {
-   compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
+   compatible = "renesas,cmt0-r8a7790", "renesas,cmt0-rcar-gen2";
reg = <0 0xffca 0 0x1004>;
interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
 <0 142 IRQ_TYPE_LEVEL_HIGH>;
clocks = <_clks R8A7790_CLK_CMT0>;
clock-names = "fck";
+   };
 
-   renesas,channels-mask = <0x60>;
+   cmt1: timer@e613 {
+   compatible = "renesas,cmt1-r8a7790", "renesas,cmt1-rcar-gen2";
+   reg = <0 0xe613 0 0x1004>;
+   interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
+<0 121 IRQ_TYPE_LEVEL_HIGH>,
+<0 122 IRQ_TYPE_LEVEL_HIGH>,
+<0 123 IRQ_TYPE_LEVEL_HIGH>,
+<0 124 IRQ_TYPE_LEVEL_HIGH>,
+<0 125 IRQ_TYPE_LEVEL_HIGH>,
+<0 126 IRQ_TYPE_LEVEL_HIGH>,
+<0 127 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = <_clks R8A7790_CLK_CMT1>;
+   clock-names = "fck";
};
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[PATCH v2 09/11] devicetree: bindings: Remove unused 32-bit CMT bindings

[Magnus Damm]

From: Magnus Damm 

Remove the 32-bit CMT compat strings to reduce maintenance burden.

It should be fine to break DT compatibility because the 32-bit
32-bit CMT DT binding was never part of any upstream DTS file.

Signed-off-by: Magnus Damm 
---

 Changes since V1:
 - New patch

 Documentation/devicetree/bindings/timer/renesas,cmt.txt |   16 ---
 1 file changed, 16 deletions(-)

--- 0008/Documentation/devicetree/bindings/timer/renesas,cmt.txt
+++ work/Documentation/devicetree/bindings/timer/renesas,cmt.txt
2015-09-17 18:04:35.060513000 +0900
@@ -12,22 +12,6 @@ datasheets.
 Required Properties:
 
   - compatible: must contain one or more of the following:
-- "renesas,cmt-32-r8a7740" for the r8a7740 32-bit CMT
-   (CMT0)
-- "renesas,cmt-32-sh73a0" for the sh73a0 32-bit CMT
-   (CMT0)
-- "renesas,cmt-32" for all 32-bit CMT without fast clock support
-   (CMT0 on sh73a0 and r8a7740)
-   This is a fallback for the above renesas,cmt-32-* entries.
-
-- "renesas,cmt-32-fast-r8a7740" for the r8a7740 32-bit CMT with fast
-   clock support (CMT[234])
-- "renesas,cmt-32-fast-sh73a0" for the sh73A0 32-bit CMT with fast
-   clock support (CMT[234])
-- "renesas,cmt-32-fast" for all 32-bit CMT with fast clock support
-   (CMT[234] on sh73a0 and r8a7740)
-   This is a fallback for the above renesas,cmt-32-fast-* entries.
-
 - "renesas,cmt-48-sh73a0" for the sh73A0 48-bit CMT
(CMT1)
 - "renesas,cmt-48-r8a7740" for the r8a7740 48-bit CMT
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[PATCH v2 02/11] scsi: ufs: add quirk to contain unconformable utrd field

[Alim Akhtar]

From: Seungwon Jeon 

UTRD(UTP Transfer Request Descriptor)'s field such as offset/length,
especially response's has DWORD expression. This quirk can be specified
for host controller not to conform standard.

Signed-off-by: Seungwon Jeon 
Signed-off-by: Alim Akhtar 
---
 drivers/scsi/ufs/ufshcd.c |   28 +---
 drivers/scsi/ufs/ufshcd.h |7 +++
 2 files changed, 28 insertions(+), 7 deletions(-)

diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index b0ade73..90f76e7 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -1009,7 +1009,7 @@ ufshcd_send_uic_cmd(struct ufs_hba *hba, struct 
uic_command *uic_cmd)
  *
  * Returns 0 in case of success, non-zero value in case of failure
  */
-static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
+static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
 {
struct ufshcd_sg_entry *prd_table;
struct scatterlist *sg;
@@ -1023,8 +1023,13 @@ static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
return sg_segments;
 
if (sg_segments) {
-   lrbp->utr_descriptor_ptr->prd_table_length =
-   cpu_to_le16((u16) (sg_segments));
+   if (hba->quirks & UFSHCI_QUIRK_BYTE_ALIGN_UTRD)
+   lrbp->utr_descriptor_ptr->prd_table_length =
+   cpu_to_le16((u16)(sg_segments *
+   sizeof(struct ufshcd_sg_entry)));
+   else
+   lrbp->utr_descriptor_ptr->prd_table_length =
+   cpu_to_le16((u16) (sg_segments));
 
prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
 
@@ -1347,7 +1352,7 @@ static int ufshcd_queuecommand(struct Scsi_Host *host, 
struct scsi_cmnd *cmd)
 
/* form UPIU before issuing the command */
ufshcd_compose_upiu(hba, lrbp);
-   err = ufshcd_map_sg(lrbp);
+   err = ufshcd_map_sg(hba, lrbp);
if (err) {
lrbp->cmd = NULL;
clear_bit_unlock(tag, >lrb_in_use);
@@ -2034,13 +2039,22 @@ static void ufshcd_host_memory_configure(struct ufs_hba 
*hba)
utrdlp[i].command_desc_base_addr_hi =

cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
 
+   if (hba->quirks & UFSHCI_QUIRK_BYTE_ALIGN_UTRD) {
+   utrdlp[i].response_upiu_offset =
+   cpu_to_le16(response_offset);
+   utrdlp[i].prd_table_offset =
+   cpu_to_le16(prdt_offset);
+   utrdlp[i].response_upiu_length =
+   cpu_to_le16(ALIGNED_UPIU_SIZE);
+   } else {
/* Response upiu and prdt offset should be in double words */
-   utrdlp[i].response_upiu_offset =
+   utrdlp[i].response_upiu_offset =
cpu_to_le16((response_offset >> 2));
-   utrdlp[i].prd_table_offset =
+   utrdlp[i].prd_table_offset =
cpu_to_le16((prdt_offset >> 2));
-   utrdlp[i].response_upiu_length =
+   utrdlp[i].response_upiu_length =
cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
+   }
 
hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
hba->lrb[i].ucd_req_ptr =
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index c40a0e7..9ed4c9e 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -459,6 +459,13 @@ struct ufs_hba {
 */
#define UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION UFS_BIT(5)
 
+   /*
+* This quirk needs to be enabled if host controller doesn't conform
+* with UTRD. Some fields such as offset/length might not be in double 
word,
+* but in byte.
+*/
+   #define UFSHCI_QUIRK_BYTE_ALIGN_UTRDUFS_BIT(6)
+
unsigned int quirks;/* Deviations from standard UFSHCI spec. */
 
wait_queue_head_t tm_wq;
-- 
1.7.10.4

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[PATCH v2 00/11] exynos-ufs: add support for Exynos

[Alim Akhtar]

This patch-set introduces UFS (Universal Flash Storage) host support
for Samsung Exynos SoC. Mostly, it consists of UFS PHY and host specific driver.
And it also contains some quirks handling for Exynos.

-Changes since v1:
* Addressed review comments from Alexey[1] and various review comments from 
Amit.
* Updated email id of Seungwon as his samsung id is void now.
* Added ufs platform data

[1]-> https://lkml.org/lkml/2015/8/23/124

Alim Akhtar (1):
  scsi: ufs: Add exynos ufs platform data

Seungwon Jeon (10):
  phy: exynos-ufs: add UFS PHY driver for EXYNOS SoC
  scsi: ufs: add quirk to contain unconformable utrd field
  scsi: ufs: add quirk to fix mishandling utrlclr/utmrlclr
  scsi: ufs: add quirk not to allow reset of interrupt aggregation
  scsi: ufs: add quirk to enable host controller without hce
  scsi: ufs: add specific callback for nexus type
  scsi: ufs: add add specific callback for hibern8
  scsi: ufs: make ufshcd_config_pwr_mode of non-static func
  scsi: ufs: return value of pwr_change_notify
  scsi: ufs-exynos: add UFS host support for Exynos SoCs

 .../devicetree/bindings/phy/samsung-phy.txt|   22 +
 .../devicetree/bindings/ufs/ufs-exynos.txt |   93 ++
 drivers/phy/Kconfig|7 +
 drivers/phy/Makefile   |1 +
 drivers/phy/phy-exynos-ufs.c   |  262 +
 drivers/phy/phy-exynos-ufs.h   |   85 ++
 drivers/phy/phy-exynos7-ufs.h  |   89 ++
 drivers/scsi/ufs/Kconfig   |   12 +
 drivers/scsi/ufs/Makefile  |1 +
 drivers/scsi/ufs/ufs-exynos-hw.c   |  147 +++
 drivers/scsi/ufs/ufs-exynos-hw.h   |   43 +
 drivers/scsi/ufs/ufs-exynos.c  | 1173 
 drivers/scsi/ufs/ufs-exynos.h  |  463 
 drivers/scsi/ufs/ufshcd-pltfrm.c   |2 +
 drivers/scsi/ufs/ufshcd.c  |  196 +++-
 drivers/scsi/ufs/ufshcd.h  |   35 +
 drivers/scsi/ufs/ufshci.h  |   26 +-
 drivers/scsi/ufs/unipro.h  |   47 +
 include/linux/phy/phy-exynos-ufs.h |  107 ++
 19 files changed, 2784 insertions(+), 27 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/ufs/ufs-exynos.txt
 create mode 100644 drivers/phy/phy-exynos-ufs.c
 create mode 100644 drivers/phy/phy-exynos-ufs.h
 create mode 100644 drivers/phy/phy-exynos7-ufs.h
 create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.c
 create mode 100644 drivers/scsi/ufs/ufs-exynos-hw.h
 create mode 100644 drivers/scsi/ufs/ufs-exynos.c
 create mode 100644 drivers/scsi/ufs/ufs-exynos.h
 create mode 100644 include/linux/phy/phy-exynos-ufs.h

-- 
1.7.10.4

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[PATCH v2 05/11] devicetree: bindings: r8a73a4 and R-Car Gen2 CMT bindings

[Magnus Damm]

From: Magnus Damm 

Update SoC-specific bindings for r8a73a4 and R-Car Gen2 CMT0 and CMT1.

Signed-off-by: Magnus Damm 
Acked-by: Geert Uytterhoeven 
Tested-by: Geert Uytterhoeven 
Acked-by: Laurent Pinchart 
---

 Changes since V1:
 - Added Acked-by and Tested-by from Geert
 - Added Acked-by from Laurent

 Documentation/devicetree/bindings/timer/renesas,cmt.txt |   26 ---
 1 file changed, 15 insertions(+), 11 deletions(-)

--- 0005/Documentation/devicetree/bindings/timer/renesas,cmt.txt
+++ work/Documentation/devicetree/bindings/timer/renesas,cmt.txt
2015-09-17 17:31:02.650513000 +0900
@@ -36,20 +36,24 @@ Required Properties:
(CMT1 on sh73a0 and r8a7740)
This is a fallback for the above renesas,cmt-48-* entries.
 
+- "renesas,cmt0-r8a73a4" for the 32-bit CMT0 device included in r8a73a4.
+- "renesas,cmt1-r8a73a4" for the 48-bit CMT1 device included in r8a73a4.
+- "renesas,cmt0-r8a7790" for the 32-bit CMT0 device included in r8a7790.
+- "renesas,cmt1-r8a7790" for the 48-bit CMT1 device included in r8a7790.
+- "renesas,cmt0-r8a7791" for the 32-bit CMT0 device included in r8a7791.
+- "renesas,cmt1-r8a7791" for the 48-bit CMT1 device included in r8a7791.
+- "renesas,cmt0-r8a7793" for the 32-bit CMT0 device included in r8a7793.
+- "renesas,cmt1-r8a7793" for the 48-bit CMT1 device included in r8a7793.
+- "renesas,cmt0-r8a7794" for the 32-bit CMT0 device included in r8a7794.
+- "renesas,cmt1-r8a7794" for the 48-bit CMT1 device included in r8a7794.
+
 - "renesas,cmt0-rcar-gen2" for 32-bit CMT0 devices included in R-Car Gen2.
 - "renesas,cmt1-rcar-gen2" for 48-bit CMT1 devices included in R-Car Gen2.
+   These are fallbacks for r8a73a4 and all the R-Car Gen2
+   entries listed above.
 
-- "renesas,cmt-48-r8a73a4" for the r8a73a4 48-bit CMT
-   (CMT[01])
-- "renesas,cmt-48-r8a7790" for the r8a7790 48-bit CMT
-   (CMT[01])
-- "renesas,cmt-48-r8a7791" for the r8a7791 48-bit CMT
-   (CMT[01])
-- "renesas,cmt-48-gen2" for all second generation 48-bit CMT
-   (CMT[01] on r8a73a4, r8a7790 and r8a7791)
-   This is a fallback for the renesas,cmt-48-r8a73a4,
-   renesas,cmt-48-r8a7790 and renesas,cmt-48-r8a7791 entries.
-
+- "renesas,cmt-48-gen2" is , use "renesas,cmt[01]-*" instead.
+
   - reg: base address and length of the registers block for the timer module.
   - interrupts: interrupt-specifier for the timer, one per channel.
   - clocks: a list of phandle + clock-specifier pairs, one for each entry
--
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[PATCH v2 06/11] ARM: shmobile: Update CMT compat string users in DTS

[Magnus Damm]

From: Magnus Damm 

Use recently updated r8a73a4 and R-Car Gen2 CMT0 and CMT1 compat strings.

With this change in place we can keep device-specific configuration in
the driver and the driver can be able to support CMT1 specific features.

Signed-off-by: Magnus Damm 
Acked-by: Geert Uytterhoeven 
Tested-by: Geert Uytterhoeven 
Acked-by: Laurent Pinchart 
---

 Changes since V1:
 - Added Acked-by and Tested-by from Geert
 - Added Acked-by from Laurent

 arch/arm/boot/dts/r8a73a4.dtsi |2 +-
 arch/arm/boot/dts/r8a7790.dtsi |4 ++--
 arch/arm/boot/dts/r8a7791.dtsi |4 ++--
 arch/arm/boot/dts/r8a7793.dtsi |4 ++--
 arch/arm/boot/dts/r8a7794.dtsi |4 ++--
 5 files changed, 9 insertions(+), 9 deletions(-)

--- 0001/arch/arm/boot/dts/r8a73a4.dtsi
+++ work/arch/arm/boot/dts/r8a73a4.dtsi 2015-09-17 17:35:37.230513000 +0900
@@ -114,7 +114,7 @@
};
 
cmt1: timer@e613 {
-   compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2";
+   compatible = "renesas,cmt1-r8a73a4", "renesas,cmt1-rcar-gen2";
reg = <0 0xe613 0 0x1004>;
interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <_clks R8A73A4_CLK_CMT1>;
--- 0001/arch/arm/boot/dts/r8a7790.dtsi
+++ work/arch/arm/boot/dts/r8a7790.dtsi 2015-09-17 17:35:37.230513000 +0900
@@ -219,7 +219,7 @@
};
 
cmt0: timer@ffca {
-   compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
+   compatible = "renesas,cmt0-r8a7790", "renesas,cmt0-rcar-gen2";
reg = <0 0xffca 0 0x1004>;
interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
 <0 143 IRQ_TYPE_LEVEL_HIGH>;
@@ -233,7 +233,7 @@
};
 
cmt1: timer@e613 {
-   compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
+   compatible = "renesas,cmt1-r8a7790", "renesas,cmt1-rcar-gen2";
reg = <0 0xe613 0 0x1004>;
interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
 <0 121 IRQ_TYPE_LEVEL_HIGH>,
--- 0001/arch/arm/boot/dts/r8a7791.dtsi
+++ work/arch/arm/boot/dts/r8a7791.dtsi 2015-09-17 17:35:37.230513000 +0900
@@ -202,7 +202,7 @@
};
 
cmt0: timer@ffca {
-   compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
+   compatible = "renesas,cmt0-r8a7791", "renesas,cmt0-rcar-gen2";
reg = <0 0xffca 0 0x1004>;
interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
 <0 143 IRQ_TYPE_LEVEL_HIGH>;
@@ -216,7 +216,7 @@
};
 
cmt1: timer@e613 {
-   compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
+   compatible = "renesas,cmt1-r8a7791", "renesas,cmt1-rcar-gen2";
reg = <0 0xe613 0 0x1004>;
interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
 <0 121 IRQ_TYPE_LEVEL_HIGH>,
--- 0001/arch/arm/boot/dts/r8a7793.dtsi
+++ work/arch/arm/boot/dts/r8a7793.dtsi 2015-09-17 17:35:37.230513000 +0900
@@ -62,7 +62,7 @@
};
 
cmt0: timer@ffca {
-   compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
+   compatible = "renesas,cmt0-r8a7793", "renesas,cmt0-rcar-gen2";
reg = <0 0xffca 0 0x1004>;
interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
 <0 143 IRQ_TYPE_LEVEL_HIGH>;
@@ -76,7 +76,7 @@
};
 
cmt1: timer@e613 {
-   compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
+   compatible = "renesas,cmt1-r8a7793", "renesas,cmt1-rcar-gen2";
reg = <0 0xe613 0 0x1004>;
interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
 <0 121 IRQ_TYPE_LEVEL_HIGH>,
--- 0001/arch/arm/boot/dts/r8a7794.dtsi
+++ work/arch/arm/boot/dts/r8a7794.dtsi 2015-09-17 17:35:37.230513000 +0900
@@ -154,7 +154,7 @@
};
 
cmt0: timer@ffca {
-   compatible = "renesas,cmt-48-gen2";
+   compatible = "renesas,cmt0-r8a7794", "renesas,cmt0-rcar-gen2";
reg = <0 0xffca 0 0x1004>;
interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
 <0 143 IRQ_TYPE_LEVEL_HIGH>;
@@ -168,7 +168,7 @@
};
 
cmt1: timer@e613 {
-   compatible = "renesas,cmt-48-gen2";
+   compatible = "renesas,cmt1-r8a7794", "renesas,cmt1-rcar-gen2";
reg = <0 0xe613 0 0x1004>;
interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
 <0 121 IRQ_TYPE_LEVEL_HIGH>,
--
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Re: [PATCH v2 11/11] devicetree: bindings: Remove deprecated properties

[Geert Uytterhoeven]

On Thu, Sep 17, 2015 at 11:55 AM, Magnus Damm  wrote:
> From: Magnus Damm 
>
> The deprecated DT properies are part of the GIT history,

properties

> no need to keep them around any longer.

They're still in the driver because in-the-field R-Car Gen2 DTSes use them,
right? You may add a comment in the driver, to prevent a janitor from
re-adding them to the bindings.

> Signed-off-by: Magnus Damm 

Nevertheless
Acked-by: Geert Uytterhoeven 

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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[PATCH v2 02/11] clocksource: sh_cmt: Use 0x3f mask for SH_CMT_48BIT case

[Magnus Damm]

From: Magnus Damm 

Always use 0x3f as channel mask for the SH_CMT_48BIT type of devices.
Once this patch is applied the "renesas,channels-mask" property will
be ignored by the driver for older devices matching SH_CMT_48BIT. In
the future when all CMT types store channel mask in the driver then
we will be able to deprecate and remove "renesas,channels-mask" from DTS.

Signed-off-by: Magnus Damm 
Acked-by: Geert Uytterhoeven 
Tested-by: Geert Uytterhoeven 
Acked-by: Laurent Pinchart 
---

 Changes since V1:
 - Fixed compile error - thanks Geert!
 - Added Acked-by and Tested-by from Geert
 - Added Acked-by from Laurent

drivers/clocksource/sh_cmt.c |   14 +++---
 1 file changed, 11 insertions(+), 3 deletions(-)

--- 0001/drivers/clocksource/sh_cmt.c
+++ work/drivers/clocksource/sh_cmt.c   2015-09-17 17:25:15.820513000 +0900
@@ -74,6 +74,8 @@ enum sh_cmt_model {
 struct sh_cmt_info {
enum sh_cmt_model model;
 
+   unsigned long channels_mask;
+
unsigned long width; /* 16 or 32 bit version of hardware block */
unsigned long overflow_bit;
unsigned long clear_bits;
@@ -212,6 +214,7 @@ static const struct sh_cmt_info sh_cmt_i
},
[SH_CMT_48BIT] = {
.model = SH_CMT_48BIT,
+   .channels_mask = 0x3f,
.width = 32,
.overflow_bit = SH_CMT32_CMCSR_CMF,
.clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
@@ -972,9 +975,14 @@ static int sh_cmt_setup(struct sh_cmt_de
id = of_match_node(sh_cmt_of_table, pdev->dev.of_node);
cmt->info = id->data;
 
-   ret = sh_cmt_parse_dt(cmt);
-   if (ret < 0)
-   return ret;
+   /* prefer in-driver channel configuration over DT */
+   if (cmt->info->channels_mask) {
+   cmt->hw_channels = cmt->info->channels_mask;
+   } else {
+   ret = sh_cmt_parse_dt(cmt);
+   if (ret < 0)
+   return ret;
+   }
} else if (pdev->dev.platform_data) {
struct sh_timer_config *cfg = pdev->dev.platform_data;
const struct platform_device_id *id = pdev->id_entry;
--
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[PATCH v2 04/11] clocksource: sh_cmt: Support separate R-Car Gen2 CMT0/1

[Magnus Damm]

From: Magnus Damm 

Add support for the new R-Car Gen2 CMT0 and CMT1 bindings. Support
for the old DT binding is still kept around, however devices using
such binding will be treated as a low-feature CMT0 device. If users
want to make use of CMT1-specific features then they need to update
their DTBs. No special CMT1-specific features are however implemented
by his patch, only DT bindings are redone as groundwork for future
feature patches.

Signed-off-by: Magnus Damm 
Acked-by: Geert Uytterhoeven 
Tested-by: Geert Uytterhoeven 
Acked-by: Laurent Pinchart 
---

 Changes since V1:
 - Added Acked-by and Tested-by from Geert
 - Added Acked-by from Laurent

 drivers/clocksource/sh_cmt.c |   38 +++---
 1 file changed, 27 insertions(+), 11 deletions(-)

--- 0003/drivers/clocksource/sh_cmt.c
+++ work/drivers/clocksource/sh_cmt.c   2015-09-17 17:28:33.380513000 +0900
@@ -39,16 +39,16 @@ struct sh_cmt_device;
  * SoC but also on the particular instance. The following table lists the main
  * characteristics of those flavours.
  *
- * 16B 32B 32B-F   48B 48B-2
+ * 16B 32B 32B-F   48B R-Car Gen2
  * 
-
  * Channels2   1/4 1   6   2/8
  * Control Width   16  16  16  16  32
  * Counter Width   16  32  32  32/48   32/48
  * Shared Start/Stop   Y   Y   Y   Y   N
  *
- * The 48-bit gen2 version has a per-channel start/stop register located in the
- * channel registers block. All other versions have a shared start/stop 
register
- * located in the global space.
+ * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
+ * located in the channel registers block. All other versions have a shared
+ * start/stop register located in the global space.
  *
  * Channels are indexed from 0 to N-1 in the documentation. The channel index
  * infers the start/stop bit position in the control register and the channel
@@ -68,7 +68,8 @@ enum sh_cmt_model {
SH_CMT_32BIT,
SH_CMT_32BIT_FAST,
SH_CMT_48BIT,
-   SH_CMT_48BIT_GEN2,
+   SH_CMT0_RCAR_GEN2,
+   SH_CMT1_RCAR_GEN2,
 };
 
 struct sh_cmt_info {
@@ -223,8 +224,20 @@ static const struct sh_cmt_info sh_cmt_i
.read_count = sh_cmt_read32,
.write_count = sh_cmt_write32,
},
-   [SH_CMT_48BIT_GEN2] = {
-   .model = SH_CMT_48BIT_GEN2,
+   [SH_CMT0_RCAR_GEN2] = {
+   .model = SH_CMT0_RCAR_GEN2,
+   .channels_mask = 0x60,
+   .width = 32,
+   .overflow_bit = SH_CMT32_CMCSR_CMF,
+   .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
+   .read_control = sh_cmt_read32,
+   .write_control = sh_cmt_write32,
+   .read_count = sh_cmt_read32,
+   .write_count = sh_cmt_write32,
+   },
+   [SH_CMT1_RCAR_GEN2] = {
+   .model = SH_CMT1_RCAR_GEN2,
+   .channels_mask = 0xff,
.width = 32,
.overflow_bit = SH_CMT32_CMCSR_CMF,
.clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
@@ -867,6 +880,7 @@ static int sh_cmt_setup_channel(struct s
ch->cmt = cmt;
ch->index = index;
ch->hwidx = hwidx;
+   ch->timer_bit = hwidx;
 
/*
 * Compute the address of the channel control register block. For the
@@ -888,9 +902,11 @@ static int sh_cmt_setup_channel(struct s
 */
ch->ioctrl = cmt->mapbase + 0x40;
break;
-   case SH_CMT_48BIT_GEN2:
+   case SH_CMT0_RCAR_GEN2:
+   case SH_CMT1_RCAR_GEN2:
ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
ch->ioctrl = ch->iostart + 0x10;
+   ch->timer_bit = 0;
break;
}
 
@@ -902,8 +918,6 @@ static int sh_cmt_setup_channel(struct s
ch->match_value = ch->max_match_value;
raw_spin_lock_init(>lock);
 
-   ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2 ? 0 : ch->hwidx;
-
ret = sh_cmt_register(ch, dev_name(>pdev->dev),
  clockevent, clocksource);
if (ret) {
@@ -946,7 +960,9 @@ static const struct of_device_id sh_cmt_
{ .compatible = "renesas,cmt-32", .data = _cmt_info[SH_CMT_32BIT] },
{ .compatible = "renesas,cmt-32-fast", .data = 
_cmt_info[SH_CMT_32BIT_FAST] },
{ .compatible = "renesas,cmt-48", .data = _cmt_info[SH_CMT_48BIT] },
-   { .compatible = "renesas,cmt-48-gen2", .data = 
_cmt_info[SH_CMT_48BIT_GEN2] },
+   { .compatible = "renesas,cmt-48-gen2", .data = 
_cmt_info[SH_CMT0_RCAR_GEN2] },
+   { .compatible = 

[PATCH v2 01/11] devicetree: bindings: Remove sh7372 CMT binding

[Magnus Damm]

From: Magnus Damm 

Remove the sh7372 CMT compat string to reduce maintenance burden.

It should be fine to break DT compatibility because:
1) The sh7372 SoC support has been removed from upstream
2) The sh7372 CMT DT binding was never part of upstream DTS
3) The CMT driver never matches on the sh7372 binding

Signed-off-by: Magnus Damm 
Acked-by: Geert Uytterhoeven 
Tested-by: Geert Uytterhoeven 
Acked-by: Laurent Pinchart 
---

 Changes since V1:
 - Removed all references to sh7372
 - Added Acked-by and Tested-by from Geert
 - Added Acked-by from Laurent

 Documentation/devicetree/bindings/timer/renesas,cmt.txt |   12 +++-
 1 file changed, 3 insertions(+), 9 deletions(-)

--- 0001/Documentation/devicetree/bindings/timer/renesas,cmt.txt
+++ work/Documentation/devicetree/bindings/timer/renesas,cmt.txt
2015-09-17 17:22:52.420513000 +0900
@@ -14,32 +14,26 @@ Required Properties:
   - compatible: must contain one or more of the following:
 - "renesas,cmt-32-r8a7740" for the r8a7740 32-bit CMT
(CMT0)
-- "renesas,cmt-32-sh7372" for the sh7372 32-bit CMT
-   (CMT0)
 - "renesas,cmt-32-sh73a0" for the sh73a0 32-bit CMT
(CMT0)
 - "renesas,cmt-32" for all 32-bit CMT without fast clock support
-   (CMT0 on sh7372, sh73a0 and r8a7740)
+   (CMT0 on sh73a0 and r8a7740)
This is a fallback for the above renesas,cmt-32-* entries.
 
 - "renesas,cmt-32-fast-r8a7740" for the r8a7740 32-bit CMT with fast
clock support (CMT[234])
-- "renesas,cmt-32-fast-sh7372" for the sh7372 32-bit CMT with fast
-   clock support (CMT[234])
 - "renesas,cmt-32-fast-sh73a0" for the sh73A0 32-bit CMT with fast
clock support (CMT[234])
 - "renesas,cmt-32-fast" for all 32-bit CMT with fast clock support
-   (CMT[234] on sh7372, sh73a0 and r8a7740)
+   (CMT[234] on sh73a0 and r8a7740)
This is a fallback for the above renesas,cmt-32-fast-* entries.
 
-- "renesas,cmt-48-sh7372" for the sh7372 48-bit CMT
-   (CMT1)
 - "renesas,cmt-48-sh73a0" for the sh73A0 48-bit CMT
(CMT1)
 - "renesas,cmt-48-r8a7740" for the r8a7740 48-bit CMT
(CMT1)
 - "renesas,cmt-48" for all non-second generation 48-bit CMT
-   (CMT1 on sh7372, sh73a0 and r8a7740)
+   (CMT1 on sh73a0 and r8a7740)
This is a fallback for the above renesas,cmt-48-* entries.
 
 - "renesas,cmt-48-r8a73a4" for the r8a73a4 48-bit CMT
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[PATCH v2 03/11] devicetree: bindings: R-Car Gen2 CMT0 and CMT1 bindings

[Magnus Damm]

From: Magnus Damm 

Add documentation for new separate CMT0 and CMT1 DT compatible strings
for R-Car Gen2. These compat strings allow us to enable CMT1-specific
features in the driver. The old compat strings will be deprecated in
the not so distant future.

Signed-off-by: Magnus Damm 
Acked-by: Geert Uytterhoeven 
Tested-by: Geert Uytterhoeven 
Acked-by: Laurent Pinchart 
---

 Changes since V1:
 - Added Acked-by and Tested-by from Geert
 - Added Acked-by from Laurent

 Documentation/devicetree/bindings/timer/renesas,cmt.txt |3 +++
 1 file changed, 3 insertions(+)

--- 0002/Documentation/devicetree/bindings/timer/renesas,cmt.txt
+++ work/Documentation/devicetree/bindings/timer/renesas,cmt.txt
2015-09-17 17:26:57.440513000 +0900
@@ -36,6 +36,9 @@ Required Properties:
(CMT1 on sh73a0 and r8a7740)
This is a fallback for the above renesas,cmt-48-* entries.
 
+- "renesas,cmt0-rcar-gen2" for 32-bit CMT0 devices included in R-Car Gen2.
+- "renesas,cmt1-rcar-gen2" for 48-bit CMT1 devices included in R-Car Gen2.
+
 - "renesas,cmt-48-r8a73a4" for the r8a73a4 48-bit CMT
(CMT[01])
 - "renesas,cmt-48-r8a7790" for the r8a7790 48-bit CMT
--
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Re: [PATCH RFC 5/8] drm: hisilicon: fill interface function of encoder\connector part

[Archit Taneja]

On 9/15/2015 3:07 PM, Xinwei Kong wrote:

This patch enables the adv7533 module which is connecting hisilicon SOC
by dsi module. while using DSI module and adv7533 module to implement the
encoder/connector interface of DRM\KMS.

Signed-off-by: Xinliang Liu 
Signed-off-by: Xinwei Kong 
Signed-off-by: Andy Green 
Signed-off-by: Jiwen Qi 
Signed-off-by: Yu Gong 
---
  drivers/gpu/drm/hisilicon/Kconfig  |  10 +
  drivers/gpu/drm/hisilicon/hisi_drm_connector.c |  34 ++
  drivers/gpu/drm/hisilicon/hisi_drm_connector.h |   8 +
  drivers/gpu/drm/hisilicon/hisi_drm_dsi.c   | 670 +
  drivers/gpu/drm/hisilicon/hisi_drm_encoder.c   |  52 ++
  drivers/gpu/drm/hisilicon/hisi_drm_encoder.h   |  19 +
  drivers/gpu/drm/hisilicon/hisi_dsi_reg.h   |  91 
  7 files changed, 884 insertions(+)
  create mode 100644 drivers/gpu/drm/hisilicon/hisi_dsi_reg.h






+struct hisi_connector_funcs hisi_dsi_connector_ops = {
+   .get_modes = dsi_connector_get_modes,
+};
+
+struct hisi_encoder_funcs hisi_dsi_encoder_ops = {
+   .mode_set = dsi_encoder_mode_set,
+   .enable = dsi_encoder_enable,
+   .disable = dsi_encoder_disable,
+};
+
  static int hisi_dsi_bind(struct device *dev, struct device *master,
 void *data)
  {
@@ -52,8 +682,23 @@ static int hisi_dsi_bind(struct device *dev, struct device 
*master,

hisi_drm_encoder_init(ctx->dev, >dsi.hisi_encoder.base.base);

+#ifdef CONFIG_DRM_HISI_HAS_SLAVE_ENCODER
+   ret = ctx->drm_i2c_driver->encoder_init(ctx->client, ctx->dev,
+   >dsi.hisi_encoder.base);
+   if (ret) {
+   DRM_ERROR("fail to init drm i2c encoder\n");
+   return ret;
+   }
+
+   if (!ctx->dsi.hisi_encoder.base.slave_funcs) {
+   DRM_ERROR("failed check encoder function\n");
+   return -ENODEV;
+   }
+#endif


A slave encoder isn't supposed to be used this way. A slave encoder is
supposed to register itself to drm as an encoder object. A slave
encoder connects directly to a crtc, and operate like a normal encoder.
In other words, a slave encoder isn't something that attaches to a
'master' encoder as the driver does here. 'Slave encoder' here means
that the encoder is a part of a different bus (like i2c etc).

Currently, the driver is directly calling slave encoder ops in 
hisi_drm_encoder.c.




+
hisi_drm_connector_init(ctx->dev, >dsi.hisi_encoder.base.base,
>dsi.hisi_connector.connector);
+
return ret;
  }

@@ -102,6 +747,27 @@ static int hisi_dsi_probe(struct platform_device *pdev)
return -EINVAL;
}

+#ifdef CONFIG_DRM_HISI_HAS_SLAVE_ENCODER
+   ctx->client = of_find_i2c_device_by_node(slave_node);
+   of_node_put(slave_node);
+   if (!ctx->client) {
+   DRM_ERROR("failed to find slave encoder i2c client\n");
+   return -EPROBE_DEFER;
+   }
+
+   if (!ctx->client->dev.driver) {
+   DRM_ERROR("%s: NULL client driver\n", __func__);
+   return -EPROBE_DEFER;
+   }
+
+   ctx->drm_i2c_driver = to_drm_i2c_encoder_driver(
+   to_i2c_driver(ctx->client->dev.driver));
+   if (IS_ERR(ctx->drm_i2c_driver)) {
+   DRM_ERROR("failed to initialize encoder driver");
+   return -EPROBE_DEFER;
+   }
+#endif
+
dsi = >dsi;
dsi->ctx = ctx;
dsi->lanes = 3;
@@ -110,6 +776,10 @@ static int hisi_dsi_probe(struct platform_device *pdev)
dsi->format = MIPI_DSI_FMT_RGB888;
dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE;

+   dsi->hisi_encoder.ops = _dsi_encoder_ops;
+   dsi->hisi_connector.encoder = >hisi_encoder.base.base;
+   dsi->hisi_connector.ops = _dsi_connector_ops;
+
return component_add(>dev, _dsi_ops);
  }

diff --git a/drivers/gpu/drm/hisilicon/hisi_drm_encoder.c 
b/drivers/gpu/drm/hisilicon/hisi_drm_encoder.c
index 89fc73d..acd73d8 100644
--- a/drivers/gpu/drm/hisilicon/hisi_drm_encoder.c
+++ b/drivers/gpu/drm/hisilicon/hisi_drm_encoder.c
@@ -15,18 +15,49 @@

  #include "hisi_drm_encoder.h"

+#define to_hisi_encoder(encoder) \
+   container_of(encoder, struct hisi_encoder, base.base)
+
  void hisi_drm_encoder_disable(struct drm_encoder *encoder)
  {
+   struct hisi_encoder *hencoder = to_hisi_encoder(encoder);
+   struct hisi_encoder_funcs *ops = hencoder->ops;
+   struct drm_encoder_slave_funcs *sfuncs = get_slave_funcs(encoder);
+
+   if (ops->enable)
+   ops->disable(encoder);
+
+   if (sfuncs && sfuncs->dpms)
+   sfuncs->dpms(encoder, DRM_MODE_DPMS_OFF);
  }



The encoder should represent only the DSI encoder hardware here. It
shouldn't be calling slave encoder ops.

What you want is 

Re: [PATCH v2 1/2] mmc: sdhci-of-arasan: add phy support for sdhci-of-arasan

[Ulf Hansson]

On 14 September 2015 at 08:29, Shawn Lin  wrote:
> This patch adds Generic PHY access for sdhci-of-arasan. Driver
> can get PHY handler from dt-binding, and power-on/init the PHY.
> Also we add pm ops for PHY here if CONFIG_PM_SLEEP is enabled.
> Currently, it's just mandatory for arasan,sdhci-5.1.

I am trying to understand how a PHY can be used together with a
MMC/SD/SDIO controller. Normally the card connector doesn't hold any
intelligence, so I wonder if PHY is correctly used here.

Could you try to explain, HW-wise, what role the PHY has for you?

Kind regards
Uffe

>
> Signed-off-by: Shawn Lin 
>
> Serise-changes: 2
> - Keep phy as a mandatory requirement for arasan,sdhci-5.1
>
> ---
>
> Changes in v2: None
>
>  drivers/mmc/host/sdhci-of-arasan.c | 97 
> ++
>  1 file changed, 97 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-of-arasan.c 
> b/drivers/mmc/host/sdhci-of-arasan.c
> index 75379cb..2c13ef8 100644
> --- a/drivers/mmc/host/sdhci-of-arasan.c
> +++ b/drivers/mmc/host/sdhci-of-arasan.c
> @@ -21,6 +21,7 @@
>
>  #include 
>  #include 
> +#include 
>  #include "sdhci-pltfm.h"
>
>  #define SDHCI_ARASAN_CLK_CTRL_OFFSET   0x2c
> @@ -35,6 +36,7 @@
>   */
>  struct sdhci_arasan_data {
> struct clk  *clk_ahb;
> +   struct phy  *phy;
>  };
>
>  static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host)
> @@ -70,6 +72,62 @@ static struct sdhci_pltfm_data sdhci_arasan_pdata = {
>
>  #ifdef CONFIG_PM_SLEEP
>  /**
> +  * sdhci_arasan_suspend_phy - Suspend phy method for the driver
> +  * @phy:Handler of phy structure
> +  * Returns 0 on success and error value on error
> +  *
> +  * Put the phy in a deactive state.
> +  */
> +static int sdhci_arasan_suspend_phy(struct phy *phy)
> +{
> +   int ret;
> +
> +   ret = phy_exit(phy);
> +   if (ret < 0)
> +   goto err_phy_exit;
> +
> +   ret = phy_power_off(phy);
> +   if (ret < 0)
> +   goto err_phy_pwr_off;
> +
> +   return 0;
> +
> +err_phy_pwr_off:
> +   phy_power_on(phy);
> +err_phy_exit:
> +   phy_init(phy);
> +   return ret;
> +}
> +
> +/**
> +  * sdhci_arasan_resume_phy - Resume phy method for the driver
> +  * @phy:Handler of phy structure
> +  * Returns 0 on success and error value on error
> +  *
> +  * Put the phy in a active state.
> +  */
> +static int sdhci_arasan_resume_phy(struct phy *phy)
> +{
> +   int ret;
> +
> +   ret = phy_power_on(phy);
> +   if (ret < 0)
> +   goto err_phy_pwr_on;
> +
> +   ret = phy_init(phy);
> +   if (ret < 0)
> +   goto err_phy_init;
> +
> +   return 0;
> +
> +err_phy_init:
> +   phy_exit(phy);
> +err_phy_pwr_on:
> +   phy_power_off(phy);
> +   return ret;
> +}
> +
> +/**
>   * sdhci_arasan_suspend - Suspend method for the driver
>   * @dev:   Address of the device structure
>   * Returns 0 on success and error value on error
> @@ -91,6 +149,12 @@ static int sdhci_arasan_suspend(struct device *dev)
> clk_disable(pltfm_host->clk);
> clk_disable(sdhci_arasan->clk_ahb);
>
> +   if (sdhci_arasan->phy) {
> +   ret = sdhci_arasan_suspend_phy(sdhci_arasan->phy);
> +   if (ret < 0)
> +   return ret;
> +   }
> +
> return 0;
>  }
>
> @@ -122,6 +186,12 @@ static int sdhci_arasan_resume(struct device *dev)
> return ret;
> }
>
> +   if (sdhci_arasan->phy) {
> +   ret = sdhci_arasan_resume_phy(sdhci_arasan->phy);
> +   if (ret < 0)
> +   return ret;
> +   }
> +
> return sdhci_resume_host(host);
>  }
>  #endif /* ! CONFIG_PM_SLEEP */
> @@ -166,6 +236,33 @@ static int sdhci_arasan_probe(struct platform_device 
> *pdev)
> goto clk_dis_ahb;
> }
>
> +   sdhci_arasan->phy = NULL;
> +   if (of_device_is_compatible(pdev->dev.of_node,
> +   "arasan,sdhci-5.1")) {
> +   sdhci_arasan->phy = devm_phy_get(>dev,
> +"phy_arasan");
> +   if (IS_ERR(sdhci_arasan->phy)) {
> +   ret = -ENODEV;
> +   dev_err(>dev, "No phy for arasan,sdhci-5.1.\n");
> +   goto clk_dis_ahb;
> +   }
> +
> +   ret = phy_power_on(sdhci_arasan->phy);
> +   if (ret < 0) {
> +   dev_err(>dev, "phy_power_on err.\n");
> +   phy_power_off(sdhci_arasan->phy);
> +   goto clk_dis_ahb;
> +   }
> +
> +   ret = phy_init(sdhci_arasan->phy);
> +   if (ret < 0) {
> +   dev_err(>dev, "phy_init err.\n");
> +   phy_exit(sdhci_arasan->phy);
> +   phy_power_off(sdhci_arasan->phy);
> +  

Re: [PATCH RFC 6/8] drm: hisilicon: Add support for fbdev

[Rob Clark]

On Wed, Sep 16, 2015 at 5:48 AM, Xinliang Liu  wrote:
>
>
> On 16 September 2015 at 02:25, Rob Herring  wrote:
> Hi Rob, thanks a lot for reply:-)
>
>> On 09/15/2015 04:37 AM, Xinwei Kong wrote:
>> > If you config DRM_HISI_FBDEV optional, this patch will only support
>> > fbdev
>> > mode while also supporting double buffer.
>>
>> This is a lot of duplicated code from CMA fbdev. Is double buffering the
>> only reason why CMA fbdev can't be used or are there some other
>> constraints?
>
> Yes, double buffering is the main reason we rewrite our own fbdev.
> CMA fbdev only create one buffer. But we need at least  double buffer for
> running Android with fbdev.
>
>> Double buffering in fbdev has always been a hack, so I'm
>> guessing that is not a feature that should be added here.
>>
> If so, I think it is hard to be accepted for my cma fbdev patch to support
> multi buffer.
> This early week, I have sent a cma fbdev patch for supporting this. The
> subject is
> "[PATCH] drm/cma-helper: Add multi buffer support for cma fbdev".
> We do have a strong will to support this feature. I described the reason in
> the patch. Please take a look for me. Thank you very much.

fwiw, drm_gralloc has support for kms.  Currently it is expected to be
paired w/ a mesa gpu driver, which might not work for everyone, but I
suppose the display part of it could be extracted out for a
gralloc.kms.so for pure sw rendering.. that might be a better
approach.

http://git.android-x86.org/?p=platform/hardware/drm_gralloc.git

BR,
-R

> -Xinliang
>
>> Rob
>>
>> > Signed-off-by: Xinliang Liu 
>> > Signed-off-by: Xinwei Kong 
>> > Signed-off-by: Andy Green 
>> > Signed-off-by: Jiwen Qi 
>> > Signed-off-by: Yu Gong 
>> > ---
>> >  drivers/gpu/drm/hisilicon/Kconfig  |  13 +
>> >  drivers/gpu/drm/hisilicon/Makefile |   3 +-
>> >  drivers/gpu/drm/hisilicon/hisi_drm_connector.c |   4 +
>> >  drivers/gpu/drm/hisilicon/hisi_drm_drv.c   |   9 +
>> >  drivers/gpu/drm/hisilicon/hisi_drm_dsi.c   |  15 +
>> >  drivers/gpu/drm/hisilicon/hisi_drm_fb.h|   5 +
>> >  drivers/gpu/drm/hisilicon/hisi_drm_fbdev.c | 395
>> > +
>> >  drivers/gpu/drm/hisilicon/hisi_drm_fbdev.h |  24 ++
>> >  8 files changed, 467 insertions(+), 1 deletion(-)
>> >  create mode 100644 drivers/gpu/drm/hisilicon/hisi_drm_fbdev.c
>> >  create mode 100644 drivers/gpu/drm/hisilicon/hisi_drm_fbdev.h
>>
>
>
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
>
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Re: [PATCH] efi/libstub/fdt: Standardize the names of EFI stub parameters

[Shannon Zhao]

Hi,

>From the comments on this patch, IIUC, we don't object to the change
brought by this patch. What we didn't reach an agreement is how to
support runtime service for Dom0. Right? If so, I think this patch
doesn't conflict with adding support for runtime service in the future.
So could we move this patch forward? Then I could continue working on
adding ARM ACPI support on Xen.

Any comments?

Thanks,
-- 
Shannon

On 2015/9/10 16:41, Shannon Zhao wrote:
> From: Shannon Zhao 
> 
> These EFI stub parameters are used to internal communication between EFI
> stub and Linux kernel and EFI stub creates these parameters. But for Xen
> on ARM when booting with UEFI, Xen will create a minimal DT providing
> these parameters for Dom0 and Dom0 is not only Linux kernel, but also
> other OS (such as FreeBSD) which will be used in the future. So here
> we plan to standardize the names by dropping the prefix "linux," and
> make them common to other OS. Also this will not break the compatibility
> since these parameters are used to internal communication between EFI
> stub and kernel.
> 
> Signed-off-by: Shannon Zhao 
> ---
> Look at [1] for the discussion about this in Xen ML. The purpose of this
> patch is to standardize the names to make Linux ARM kernel work on Xen
> with UEFI. Also it hopes other OS(e.g. FreeBSD), which will be used as
> Dom0 on Xen, could support this mechanism as well.
> 
> [1]http://lists.xenproject.org/archives/html/xen-devel/2015-08/msg02250.html
> 
>  Documentation/arm/uefi.txt | 10 +-
>  drivers/firmware/efi/efi.c | 10 +-
>  drivers/firmware/efi/libstub/fdt.c | 10 +-
>  3 files changed, 15 insertions(+), 15 deletions(-)
> 
> diff --git a/Documentation/arm/uefi.txt b/Documentation/arm/uefi.txt
> index d60030a..8c83243 100644
> --- a/Documentation/arm/uefi.txt
> +++ b/Documentation/arm/uefi.txt
> @@ -45,18 +45,18 @@ following parameters:
>  
> 
>  Name  | Size   | Description
>  
> 
> -linux,uefi-system-table   | 64-bit | Physical address of the UEFI System 
> Table.
> +uefi-system-table | 64-bit | Physical address of the UEFI System 
> Table.
>  
> 
> -linux,uefi-mmap-start | 64-bit | Physical address of the UEFI memory map,
> +uefi-mmap-start   | 64-bit | Physical address of the UEFI memory map,
>|| populated by the UEFI GetMemoryMap() 
> call.
>  
> 
> -linux,uefi-mmap-size  | 32-bit | Size in bytes of the UEFI memory map
> +uefi-mmap-size| 32-bit | Size in bytes of the UEFI memory map
>|| pointed to in previous entry.
>  
> 
> -linux,uefi-mmap-desc-size | 32-bit | Size in bytes of each entry in the UEFI
> +uefi-mmap-desc-size   | 32-bit | Size in bytes of each entry in the UEFI
>|| memory map.
>  
> 
> -linux,uefi-mmap-desc-ver  | 32-bit | Version of the mmap descriptor format.
> +uefi-mmap-desc-ver| 32-bit | Version of the mmap descriptor format.
>  
> 
>  linux,uefi-stub-kern-ver  | string | Copy of linux_banner from build.
>  
> 
> diff --git a/drivers/firmware/efi/efi.c b/drivers/firmware/efi/efi.c
> index d6144e3..3878715 100644
> --- a/drivers/firmware/efi/efi.c
> +++ b/drivers/firmware/efi/efi.c
> @@ -481,11 +481,11 @@ static __initdata struct {
>   int offset;
>   int size;
>  } dt_params[] = {
> - UEFI_PARAM("System Table", "linux,uefi-system-table", system_table),
> - UEFI_PARAM("MemMap Address", "linux,uefi-mmap-start", mmap),
> - UEFI_PARAM("MemMap Size", "linux,uefi-mmap-size", mmap_size),
> - UEFI_PARAM("MemMap Desc. Size", "linux,uefi-mmap-desc-size", desc_size),
> - UEFI_PARAM("MemMap Desc. Version", "linux,uefi-mmap-desc-ver", desc_ver)
> + UEFI_PARAM("System Table", "uefi-system-table", system_table),
> + UEFI_PARAM("MemMap Address", "uefi-mmap-start", mmap),
> + UEFI_PARAM("MemMap Size", "uefi-mmap-size", mmap_size),
> + UEFI_PARAM("MemMap Desc. Size", "uefi-mmap-desc-size", desc_size),
> + UEFI_PARAM("MemMap Desc. Version", "uefi-mmap-desc-ver", desc_ver)
>  };
>  
>  struct param_info {
> diff --git a/drivers/firmware/efi/libstub/fdt.c 
> b/drivers/firmware/efi/libstub/fdt.c
> index ef5d764..e94589a 100644
> --- 

[PATCH V4 1/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings

[Chen Feng]

Add DT bindings documentation for hi6220 SoC reset controller.

Signed-off-by: Chen Feng 
---
 .../bindings/reset/hisilicon,hi6220-reset.txt  | 97 ++
 1 file changed, 97 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt

diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt 
b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
new file mode 100644
index 000..c0f7928
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
@@ -0,0 +1,97 @@
+Hisilicon System Reset Controller
+==
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+The reset controller node must be a sub-node of the chip controller
+node on SoCs.
+
+Required properties:
+- compatible: may be "hisilicon,hi6220-reset-ctl"
+- reg: should be register base and length as documented in the
+  datasheet
+- #reset-cells: 1, see below
+
+Example:
+
+   reset_ctrl: reset_ctrl@f703 {
+   compatible = "hisilicon,hi6220-reset-ctl";
+   reg = <0x0 0xf703 0x0 0x1000>;
+   #reset-cells = <1>;
+   };
+
+Specifying reset lines connected to IP modules
+==
+example:
+
+uart1: uart1@. {
+   ...
+resets = <_ctrl 0x305>;
+   ...
+};
+
+The following RESET_INDEX values are valid for hi6220 SoC:
+   PERIPH_RSTDIS0_MMC0 = 0x000,
+   PERIPH_RSTDIS0_MMC1 = 0x001,
+   PERIPH_RSTDIS0_MMC2 = 0x002,
+   PERIPH_RSTDIS0_NANDC= 0x003,
+   PERIPH_RSTDIS0_USBOTG_BUS   = 0x004,
+   PERIPH_RSTDIS0_POR_PICOPHY  = 0x005,
+   PERIPH_RSTDIS0_USBOTG   = 0x006,
+   PERIPH_RSTDIS0_USBOTG_32K   = 0x007,
+
+   PERIPH_RSTDIS1_HIFI = 0x100,
+   PERIPH_RSTDIS1_DIGACODEC= 0x105,
+
+   PERIPH_RSTEN2_IPF   = 0x200,
+   PERIPH_RSTEN2_SOCP  = 0x201,
+   PERIPH_RSTEN2_DMAC  = 0x202,
+   PERIPH_RSTEN2_SECENG= 0x203,
+   PERIPH_RSTEN2_ABB   = 0x204,
+   PERIPH_RSTEN2_HPM0  = 0x205,
+   PERIPH_RSTEN2_HPM1  = 0x206,
+   PERIPH_RSTEN2_HPM2  = 0x207,
+   PERIPH_RSTEN2_HPM3  = 0x208,
+
+   PERIPH_RSTEN3_CSSYS = 0x300,
+   PERIPH_RSTEN3_I2C0  = 0x301,
+   PERIPH_RSTEN3_I2C1  = 0x302,
+   PERIPH_RSTEN3_I2C2  = 0x303,
+   PERIPH_RSTEN3_I2C3  = 0x304,
+   PERIPH_RSTEN3_UART1 = 0x305,
+   PERIPH_RSTEN3_UART2 = 0x306,
+   PERIPH_RSTEN3_UART3 = 0x307,
+   PERIPH_RSTEN3_UART4 = 0x308,
+   PERIPH_RSTEN3_SSP   = 0x309,
+   PERIPH_RSTEN3_PWM   = 0x30a,
+   PERIPH_RSTEN3_BLPWM = 0x30b,
+   PERIPH_RSTEN3_TSENSOR   = 0x30c,
+   PERIPH_RSTEN3_DAPB  = 0x312,
+   PERIPH_RSTEN3_HKADC = 0x313,
+   PERIPH_RSTEN3_CODEC_SSI = 0x314,
+   PERIPH_RSTEN3_PMUSSI1   = 0x316,
+
+   PERIPH_RSTEN8_RS0   = 0x400,
+   PERIPH_RSTEN8_RS2   = 0x401,
+   PERIPH_RSTEN8_RS3   = 0x402,
+   PERIPH_RSTEN8_MS0   = 0x403,
+   PERIPH_RSTEN8_MS2   = 0x405,
+   PERIPH_RSTEN8_XG2RAM0   = 0x406,
+   PERIPH_RSTEN8_X2SRAM_TZMA   = 0x407,
+   PERIPH_RSTEN8_SRAM  = 0x408,
+   PERIPH_RSTEN8_HARQ  = 0x40a,
+   PERIPH_RSTEN8_DDRC  = 0x40c,
+   PERIPH_RSTEN8_DDRC_APB  = 0x40d,
+   PERIPH_RSTEN8_DDRPACK_APB   = 0x40e,
+   PERIPH_RSTEN8_DDRT  = 0x411,
+
+   PERIPH_RSDIST9_CARM_DAP = 0x500,
+   PERIPH_RSDIST9_CARM_ATB = 0x501,
+   PERIPH_RSDIST9_CARM_LBUS= 0x502,
+   PERIPH_RSDIST9_CARM_POR = 0x503,
+   PERIPH_RSDIST9_CARM_CORE= 0x504,
+   PERIPH_RSDIST9_CARM_DBG = 0x505,
+   PERIPH_RSDIST9_CARM_L2  = 0x506,
+   PERIPH_RSDIST9_CARM_SOCDBG  = 0x507,
+   PERIPH_RSDIST9_CARM_ETM = 0x508,
-- 
1.9.1

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[PATCH V4 2/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC

[Chen Feng]

Add reset driver for hi6220-hikey board,this driver supply deassert
of IP. on hi6220 SoC.

Signed-off-by: Chen Feng 
---
 drivers/reset/Kconfig  |   1 +
 drivers/reset/Makefile |   1 +
 drivers/reset/hisilicon/Kconfig|   5 ++
 drivers/reset/hisilicon/Makefile   |   1 +
 drivers/reset/hisilicon/hi6220_reset.c | 107 +
 5 files changed, 115 insertions(+)
 create mode 100644 drivers/reset/hisilicon/Kconfig
 create mode 100644 drivers/reset/hisilicon/Makefile
 create mode 100644 drivers/reset/hisilicon/hi6220_reset.c

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 0615f50..df37212 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -13,3 +13,4 @@ menuconfig RESET_CONTROLLER
  If unsure, say no.
 
 source "drivers/reset/sti/Kconfig"
+source "drivers/reset/hisilicon/Kconfig"
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 157d421..331d7b2 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
 obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o
 obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
 obj-$(CONFIG_ARCH_STI) += sti/
+obj-$(CONFIG_ARCH_HISI) += hisilicon/
diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig
new file mode 100644
index 000..26bf95a
--- /dev/null
+++ b/drivers/reset/hisilicon/Kconfig
@@ -0,0 +1,5 @@
+config COMMON_RESET_HI6220
+   tristate "Hi6220 Reset Driver"
+   depends on (ARCH_HISI && RESET_CONTROLLER)
+   help
+ Build the Hisilicon Hi6220 reset driver.
diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile
new file mode 100644
index 000..c932f86
--- /dev/null
+++ b/drivers/reset/hisilicon/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o
diff --git a/drivers/reset/hisilicon/hi6220_reset.c 
b/drivers/reset/hisilicon/hi6220_reset.c
new file mode 100644
index 000..eac9531
--- /dev/null
+++ b/drivers/reset/hisilicon/hi6220_reset.c
@@ -0,0 +1,107 @@
+/*
+ * Hisilicon Hi6220 reset controller driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Feng Chen 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ASSERT_OFFSET0x300
+#define DEASSERT_OFFSET  0x304
+#define MAX_INDEX0x509
+
+#define to_reset_data(x) container_of(x, struct hi6220_reset_data, rc_dev)
+
+struct hi6220_reset_data {
+   void __iomem*assert_base;
+   void __iomem*deassert_base;
+   struct reset_controller_dev rc_dev;
+};
+
+static int hi6220_reset_assert(struct reset_controller_dev *rc_dev,
+  unsigned long idx)
+{
+   struct hi6220_reset_data *data = to_reset_data(rc_dev);
+
+   int bank = idx >> 8;
+   int offset = idx & 0xff;
+
+   writel(BIT(offset), data->assert_base + (bank * 0x10));
+
+   return 0;
+}
+
+static int hi6220_reset_deassert(struct reset_controller_dev *rc_dev,
+unsigned long idx)
+{
+   struct hi6220_reset_data *data = to_reset_data(rc_dev);
+
+   int bank = idx >> 8;
+   int offset = idx & 0xff;
+
+   writel(BIT(offset), data->deassert_base + (bank * 0x10));
+
+   return 0;
+}
+
+static struct reset_control_ops hi6220_reset_ops = {
+   .assert = hi6220_reset_assert,
+   .deassert = hi6220_reset_deassert,
+};
+
+static int hi6220_reset_probe(struct platform_device *pdev)
+{
+   struct hi6220_reset_data *data;
+   struct resource *res;
+   void __iomem *src_base;
+
+   data = devm_kzalloc(>dev, sizeof(*data), GFP_KERNEL);
+   if (!data)
+   return -ENOMEM;
+
+   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   src_base = devm_ioremap_resource(>dev, res);
+   if (IS_ERR(src_base))
+   return PTR_ERR(src_base);
+
+   data->assert_base = src_base + ASSERT_OFFSET;
+   data->deassert_base = src_base + DEASSERT_OFFSET;
+   data->rc_dev.nr_resets = MAX_INDEX;
+   data->rc_dev.ops = _reset_ops;
+   data->rc_dev.of_node = pdev->dev.of_node;
+
+   reset_controller_register(>rc_dev);
+
+   return 0;
+}
+
+static const struct of_device_id hi6220_reset_match[] = {
+   { .compatible = "hisilicon,hi6220-reset-ctl" },
+   { },
+};
+
+static struct platform_driver hi6220_reset_driver = {
+   .probe = hi6220_reset_probe,
+   .driver = {
+   .name = "reset-hi6220",
+   .of_match_table = hi6220_reset_match,
+   },
+};
+
+static int __init hi6220_reset_init(void)
+{
+   return 

[PATCH V4 3/3] arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC

[Chen Feng]

Add reset controller for hi6220 hikey-board.

Signed-off-by: Chen Feng 
---
 arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi 
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 3f03380..3f055e2 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -167,5 +167,12 @@
clocks = <_ctrl 36>, <_ctrl 36>;
clock-names = "uartclk", "apb_pclk";
};
+
+   reset_ctrl: reset_ctrl@f703 {
+   compatible = "hisilicon,hi6220-reset-ctl";
+   reg = <0x0 0xf703 0x0 0x1000>;
+   #reset-cells = <1>;
+   };
+
};
 };
-- 
1.9.1

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Re: [PATCH RFC 1/8] dt-bindings: Document the hi6220 bindings for DRM driver

[Xinwei Kong]

hi architt

On 2015/9/16 17:10, Archit Taneja wrote:
> Hi,
> 
> On 09/16/2015 02:04 PM, Xinwei Kong wrote:
>> hi architt
>>
>> On 2015/9/16 2:11, Rob Herring wrote:
>>> On 09/15/2015 04:37 AM, Xinwei Kong wrote:
 This adds documentation of device tree bindings for the
 Graphics Processing Unit of hi6220 SOC.

 Signed-off-by: Xinliang Liu 
 Signed-off-by: Xinwei Kong 
 Signed-off-by: Andy Green 
 Signed-off-by: Jiwen Qi 
 Signed-off-by: Yu Gong 
 ---
   .../devicetree/bindings/gpu/hisilicon,hi6220.txt   | 69 
 ++
   1 file changed, 69 insertions(+)
   create mode 100644 
 Documentation/devicetree/bindings/gpu/hisilicon,hi6220.txt

 diff --git a/Documentation/devicetree/bindings/gpu/hisilicon,hi6220.txt 
 b/Documentation/devicetree/bindings/gpu/hisilicon,hi6220.txt
 new file mode 100644
 index 000..173ac63
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/gpu/hisilicon,hi6220.txt
 @@ -0,0 +1,69 @@
 + * Hisilicon hi6220 Graphics Processing Unit for HiKey board
 +
 + ** display-subsystem: Master device for binding DRM sub-components
>>>
>>> DRM is a Linuxism that doesn't belong in the binding.
>>>
 +This master device is parent node and it will be responsible to bind 
 all
 +sub-components devices node.
>>>
>>> Are these nodes a single block in the h/w? If not, you should describe
>>> the connection of sub-nodes with of-graph instead.
>>>
 +- Required properties :
 +  - compatible: "hisilicon,display-subsystem".
 +  - #address-cells, #size-cells: Must be present if the device has 
 sub-nodes.
 +  - ranges: to allow probing of subdevices.
 +  - dma-coherent: Present if dma operations are coherent.
 +
 + ** ade: Graphic overlay, Graphic post-processing, display timing control.
 +This device is child node of display-subsystem
 +- Required properties :
 +  - compatible: "hisilicon,hi6220-ade".
 +  - reg: physical base address of the ADE register and length of 
 memory
 +region.
 +  - reg-names: Should contain the reg names "ade_base" and 
 "media_base".
 +  - interrupt: The interrupt number to the cpu. Defines the interrupt
 +by ADE.
 +  - clocks: The clocks needed by the ADE module.
 +  - clock-names: the name of the clocks.
 +
 + ** dsi: support mipi dsi interface
 +This device is child node of display-subsystem
 +- Required properties :
 +  - compatible: "hisilicon,hi6220-dsi".
 +  - reg: physical base address of the DSI register and length of 
 memory
 +region.
 +  - clocks: The clocks needed by the DSI module.
 +  - clock-names: the name of the clocks.
 +  -encoder-slave: phandles to a 'encoder-slave' subnode which DSI 
 connect
 +ADV7533 in order to support hdmi display.
>>>
>>> What the ADV7533 binding looks like is still being discussed.
>>> "encoder-slave" is certainly DRM specific and not how it should be done.
>>> Most likely, this needs to use the of-graph ports.
>>>
>> I dont how to implement the encoder bridge stuff in upstream,
>> you think that I will how to handle this part?
> 
> You can use of-graph ports to link the dsi output with the adv7533
> bridge.
> 
> An example of the binding looks like:
> 
> Documentation/devicetree/bindings/drm/msm/dsi.txt
> 
> The implementation of this on the dsi host side of drm/msm
> can be found in dsi_host_parse_dt, in:
> 
> drivers/gpu/drm/msm/dsi/dsi_host.c
> 
> You can get to know more about of-graph parsing here:
> 
> Documentation/devicetree/bindings/graph.txt
> 
I study your patch about of-graph parsing, I know that how to parse this
dts endpoint node. Then i dont kow how to use this device_node (which is
get by "of_graph_get_remote_port_parent" function.) to hook adv7533 operation.

can you give me some help to how to use the adv7533 interface by device_node or
other way to use adv7533?

> I'd started going through the drm/hisil patches. I'll
> share more comments there.
> 
> Thanks,
> Archit
> 
>>
>> Thank you
>> xinwei
>>
>>> Also, the ADV7533 connection is specific to HiKey. This binding should
>>> just generically describe how any bridge or panel is connected.
>>>
>>> Rob
>>>
>>> .
>>>
>>
>> -- 
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>> the body of a message to majord...@vger.kernel.org
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>>
> 

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Re: [PATCH v2 09/11] devicetree: bindings: Remove unused 32-bit CMT bindings

[Sergei Shtylyov]

Hello.

On 9/17/2015 12:54 PM, Magnus Damm wrote:


From: Magnus Damm 

Remove the 32-bit CMT compat strings to reduce maintenance burden.

It should be fine to break DT compatibility because the 32-bit
32-bit CMT DT binding was never part of any upstream DTS file.


   Nit: "32-bit" repeated twice.


Signed-off-by: Magnus Damm 

[...]

MBR, Sergei

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[PATCH v2 5/9] dt-bindings: add documentation of rk3036 clock controller

[Xing Zheng]

Add the devicetree binding for the cru on the rk3036 which quite similar
structured as previous clock controllers.

Signed-off-by: Xing Zheng 
---

Changes in v2: None

 .../bindings/clock/rockchip,rk3036-cru.txt |   60 
 1 file changed, 60 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt 
b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
new file mode 100644
index 000..ac3037a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
@@ -0,0 +1,60 @@
+* Rockchip RK3036 Clock and Reset Unit
+
+The RK3036 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: should be "rockchip,rk3036-cru"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+  If missing pll rates are not changable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "xin32k" - rtc clock - optional,
+ - "ext_i2s" - external I2S clock - optional,
+ - "ext_hsadc" - external HSADC clock - optional,
+ - "ext_vip" - external VIP clock - optional,
+ - "ext_isp" - external ISP clock - optional,
+ - "ext_jtag" - external JTAG clock - optional
+
+Example: Clock controller node:
+
+   cru: cru@2000 {
+   compatible = "rockchip,rk3036-cru";
+   reg = <0x2000 0x1000>;
+   rockchip,grf = <>;
+
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller:
+
+   uart0: serial@2006 {
+   compatible = "snps,dw-apb-uart";
+   reg = <0x2006 0x100>;
+   interrupts = ;
+   reg-shift = <2>;
+   reg-io-width = <4>;
+   clocks = < SCLK_UART0>;
+   };
-- 
1.7.9.5


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Re: [PATCH v2 11/11] devicetree: bindings: Remove deprecated properties

[Magnus Damm]

Hi Geert,

On Thu, Sep 17, 2015 at 7:04 PM, Geert Uytterhoeven
 wrote:
> On Thu, Sep 17, 2015 at 11:55 AM, Magnus Damm  wrote:
>> From: Magnus Damm 
>>
>> The deprecated DT properies are part of the GIT history,
>
> properties

Oops!

>> no need to keep them around any longer.
>
> They're still in the driver because in-the-field R-Car Gen2 DTSes use them,
> right? You may add a comment in the driver, to prevent a janitor from
> re-adding them to the bindings.

Yes, good idea!

>> Signed-off-by: Magnus Damm 
>
> Nevertheless
> Acked-by: Geert Uytterhoeven 

Thank you!

/ magnus
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[PATCH v2 6/9] pinctrl: rockchip: add support for the rk3036

[Xing Zheng]

Add new type for rk3036 and many parts of pinctrl rk3036 are similar
with rk2928's.

Signed-off-by: Xing Zheng 
---

Changes in v2: None

 .../bindings/pinctrl/rockchip,pinctrl.txt  |1 +
 drivers/pinctrl/pinctrl-rockchip.c |   17 +
 2 files changed, 18 insertions(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
index 391ef4b..c73f2bb 100644
--- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
@@ -22,6 +22,7 @@ Required properties for iomux controller:
   - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
   "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
   "rockchip,rk3288-pinctrl", "rockchip,rk3368-pinctrl"
+  "rockchip,rk3036-pinctrl"
   - rockchip,grf: phandle referencing a syscon providing the
 "general register files"
 
diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index c5246c0..9c49510 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -2089,6 +2089,21 @@ static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
.pull_calc_reg  = rk2928_calc_pull_reg_and_bit,
 };
 
+static struct rockchip_pin_bank rk3036_pin_banks[] = {
+   PIN_BANK(0, 32, "gpio0"),
+   PIN_BANK(1, 32, "gpio1"),
+   PIN_BANK(2, 32, "gpio2"),
+};
+
+static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
+   .pin_banks  = rk3036_pin_banks,
+   .nr_banks   = ARRAY_SIZE(rk3036_pin_banks),
+   .label  = "RK3036-GPIO",
+   .type   = RK2928,
+   .grf_mux_offset = 0xa8,
+   .pull_calc_reg  = rk2928_calc_pull_reg_and_bit,
+};
+
 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
PIN_BANK(0, 32, "gpio0"),
PIN_BANK(1, 32, "gpio1"),
@@ -2207,6 +,8 @@ static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
{ .compatible = "rockchip,rk2928-pinctrl",
.data = (void *)_pin_ctrl },
+   { .compatible = "rockchip,rk3036-pinctrl",
+   .data = (void *)_pin_ctrl },
{ .compatible = "rockchip,rk3066a-pinctrl",
.data = (void *)_pin_ctrl },
{ .compatible = "rockchip,rk3066b-pinctrl",
-- 
1.7.9.5


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[PATCH v2] Add driver for the si514 clock generator chip

[Mike Looijmans]

This patch adds the driver and devicetree documentation for the
Silicon Labs SI514 clock generator chip. This is an I2C controlled
oscilator capable of generating clock signals ranging from 100kHz
to 250MHz.

Signed-off-by: Mike Looijmans 
---
v2: Fix e-mail address list (using old maintainer list, sorry).
Rebase on master.

 .../devicetree/bindings/clock/silabs,si514.txt |  27 ++
 drivers/clk/Kconfig|  10 +
 drivers/clk/Makefile   |   1 +
 drivers/clk/clk-si514.c| 393 +
 4 files changed, 431 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/silabs,si514.txt
 create mode 100644 drivers/clk/clk-si514.c

diff --git a/Documentation/devicetree/bindings/clock/silabs,si514.txt 
b/Documentation/devicetree/bindings/clock/silabs,si514.txt
new file mode 100644
index 000..05964d1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/silabs,si514.txt
@@ -0,0 +1,27 @@
+Binding for Silicon Labs 514 programmable I2C clock generator.
+
+Reference
+This binding uses the common clock binding[1]. Details about the device can be
+found in the datasheet[2].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Si514 datasheet
+http://www.silabs.com/Support%20Documents/TechnicalDocs/si514.pdf
+
+Required properties:
+ - compatible: Shall be "silabs,si514"
+ - reg: I2C device address.
+ - #clock-cells: From common clock bindings: Shall be 0.
+
+Optional properties:
+ - clock-output-names: From common clock bindings. Recommended to be "si514".
+ - clock-frequency: Output frequency to generate. This defines the output
+   frequency set during boot. It can be reprogrammed during
+   runtime through the common clock framework.
+
+Example:
+   si514: clock-generator@55 {
+   reg = <0x55>;
+   #clock-cells = <0>;
+   compatible = "silabs,si514";
+   };
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 42f7120..6ac7deb5 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -68,6 +68,16 @@ config COMMON_CLK_SI5351
  This driver supports Silicon Labs 5351A/B/C programmable clock
  generators.
 
+config COMMON_CLK_SI514
+   tristate "Clock driver for SiLabs 514 devices"
+   depends on I2C
+   depends on OF
+   select REGMAP_I2C
+   help
+   ---help---
+ This driver supports the Silicon Labs 514 programmable clock
+ generator.
+
 config COMMON_CLK_SI570
tristate "Clock driver for SiLabs 570 and compatible devices"
depends on I2C
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d08b3e5..6594e53 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_CLK_QORIQ)   += clk-qoriq.o
 obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o
 obj-$(CONFIG_COMMON_CLK_S2MPS11)   += clk-s2mps11.o
 obj-$(CONFIG_COMMON_CLK_SI5351)+= clk-si5351.o
+obj-$(CONFIG_COMMON_CLK_SI514) += clk-si514.o
 obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o
 obj-$(CONFIG_COMMON_CLK_CDCE925)   += clk-cdce925.o
 obj-$(CONFIG_ARCH_STM32)   += clk-stm32f4.o
diff --git a/drivers/clk/clk-si514.c b/drivers/clk/clk-si514.c
new file mode 100644
index 000..ca70818
--- /dev/null
+++ b/drivers/clk/clk-si514.c
@@ -0,0 +1,393 @@
+/*
+ * Driver for Silicon Labs Si514 Programmable Oscillator
+ *
+ * Copyright (C) 2015 Topic Embedded Products
+ *
+ * Author: Mike Looijmans 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* I2C registers */
+#define SI514_REG_LP   0
+#define SI514_REG_M_FRAC1  5
+#define SI514_REG_M_FRAC2  6
+#define SI514_REG_M_FRAC3  7
+#define SI514_REG_M_INT_FRAC   8
+#define SI514_REG_M_INT9
+#define SI514_REG_HS_DIV   10
+#define SI514_REG_LS_HS_DIV11
+#define SI514_REG_OE_STATE 14
+#define SI514_REG_RESET128
+#define SI514_REG_CONTROL  132
+
+/* Register values */
+#define SI514_RESET_RSTBIT(7)
+
+#define SI514_CONTROL_FCAL BIT(0)
+#define SI514_CONTROL_OE   BIT(2)
+
+#define SI514_MIN_FREQ 10U
+#define SI514_MAX_FREQ  25000U
+
+#define FXO  3198U
+
+#define FVCO_MIN   208000U

Re: [PATCH v5] dtb: Create a common home for cross-architecture dtsi files.

[Ian Campbell]

Hi Olof,

On Mon, 2015-08-24 at 15:22 -0700, Olof Johansson wrote:

A little while ago you were trying to explain the scheme you would like to
see on IRC but my thick skull was getting in the way :-/ Then you had to
run...

So, ping?

Ian.
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Re: [PATCH 2/3] devicetree: bindings: use input-event-codes.h for evdev codes

[Ian Campbell]

On Wed, 2015-09-16 at 15:40 +0100, Ian Campbell wrote:
> > The intend of the symlink was that the conversion script would copy the 
> > target,
> > rather then follow the symlink. This sorta assumes that there are will be 
> > not
> > symlinks under dt-bindings which link to files inside dt-bindings and thus
> > should be preserved as symlinks.
> > 
> > If the copy done in the script will follow the symlink then nothing should
> > really change for the split DT repo.
> 
> Interesting idea. I'll see if I can make the conversion routine do that.
> 
> TBH I have a horrid feeling that this is going to be beyond git rewrite
> -branch, at least in the mode it is used in today.

It seems that it is possible, after a fashion.

The downside is that either _all_ symlinks (which end up in the output) get
flattened or some sort of black/whitelisting is needed in the conversion
scripts themselves (potentially leading to issues or discontinuities) as
new stuff arrives).

It isn't possible AFAICT tell if a symlink points to something outside of
the converted set of paths and adjust, at least not without an unreasonable
amount of overhead on each commit during the rewrite.

Since this new file would be the first symlink in the converted repo I took
the former approach in my lash up to try it out, which was essentially to
insert the below script into the middle of the "git ls-files | rewrite
-paths.sed" pipeline which is called by git filter-branch --index-filter.
Not pretty but it does seem to work.

I want to avoid switching to --tree-filter if at all possible because it
checks out the tree and is therefore a _little_ I/O intensive ;-)

Ian.

#!/bin/bash

set -e

while read mode object stage path ; do
case "$mode" in
12)
# symbolic link
deref=$(echo $GIT_COMMIT:$path | git cat-file 
--batch-check='deref-ok %(objectname)' --follow-symlinks)
case "$deref" in
deref-ok*)
echo -e "100644 ${deref#deref-ok } $stage\t$path"
;;
dangling*) # skip
;;
*) # the rest, missing etc
echo >&2 "Failed to parse symlink $GIT_COMMIT:$path $deref"
exit 1
;;
esac
;;
100*)
# Regular file, just pass through
echo -e "$mode $object $stage\t$path"
;;
*)
echo >&2 "Unhandled ls-tree entry: $line"
exit 1
;;
esac
done
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Re: [PATCH RFC 2/8] drm: hisilicon: Add new DRM driver for hisilicon Soc

[Archit Taneja]

Hi,

On 9/15/2015 3:07 PM, Xinwei Kong wrote:

This patch creates this driver itself and register all the sub-components
which is from DTS inode, this driver uses components framework mechanism
to bind all the sub-components.

This patch also introduces a memory manager for hisilison drm. As cma
framebuffer helpers can no more be used.

Signed-off-by: Xinliang Liu 
Signed-off-by: Xinwei Kong 
Signed-off-by: Andy Green 
Signed-off-by: Jiwen Qi 
Signed-off-by: Yu Gong 
---
  arch/arm64/configs/defconfig |   5 +
  drivers/gpu/drm/Kconfig  |   2 +
  drivers/gpu/drm/Makefile |   1 +
  drivers/gpu/drm/hisilicon/Kconfig|   9 ++
  drivers/gpu/drm/hisilicon/Makefile   |   7 ++
  drivers/gpu/drm/hisilicon/hisi_ade.c | 166 +
  drivers/gpu/drm/hisilicon/hisi_drm_drv.c | 206 +++
  drivers/gpu/drm/hisilicon/hisi_drm_dsi.c | 131 
  drivers/gpu/drm/hisilicon/hisi_drm_fb.c  | 156 +++
  drivers/gpu/drm/hisilicon/hisi_drm_fb.h  |  26 
  10 files changed, 709 insertions(+)
  create mode 100644 drivers/gpu/drm/hisilicon/Kconfig
  create mode 100644 drivers/gpu/drm/hisilicon/Makefile
  create mode 100644 drivers/gpu/drm/hisilicon/hisi_ade.c
  create mode 100644 drivers/gpu/drm/hisilicon/hisi_drm_drv.c
  create mode 100644 drivers/gpu/drm/hisilicon/hisi_drm_dsi.c
  create mode 100644 drivers/gpu/drm/hisilicon/hisi_drm_fb.c
  create mode 100644 drivers/gpu/drm/hisilicon/hisi_drm_fb.h






diff --git a/drivers/gpu/drm/hisilicon/hisi_drm_dsi.c 
b/drivers/gpu/drm/hisilicon/hisi_drm_dsi.c
new file mode 100644
index 000..a8dbaad
--- /dev/null
+++ b/drivers/gpu/drm/hisilicon/hisi_drm_dsi.c
@@ -0,0 +1,131 @@
+/*
+ * Hisilicon Terminal SoCs drm driver
+ *
+ * Copyright (c) 2014-2015 Hisilicon Limited.
+ * Author: Xinwei Kong  for hisilicon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include 
+#include 
+
+#include 
+#include 
+
+#define DSI_24BITS_1   (5)
+
+struct hisi_dsi {
+   u32 lanes;
+   u32 format;
+   u32 date_enable_pol;
+   u32 mode_flags;
+   u8 color_mode;
+   void *ctx;
+};
+
+struct hisi_dsi_context {
+   struct hisi_dsi dsi;
+   struct clk *dsi_cfg_clk;
+   struct drm_device *dev;
+
+   void __iomem *base;
+   int nominal_pixel_clk_kHz;
+};
+
+static int hisi_dsi_bind(struct device *dev, struct device *master,
+void *data)
+{
+   int ret = 0;
+
+   return ret;
+}
+
+static void hisi_dsi_unbind(struct device *dev, struct device *master,
+   void *data)
+{
+   /* do nothing */
+}
+
+static const struct component_ops hisi_dsi_ops = {
+   .bind   = hisi_dsi_bind,
+   .unbind = hisi_dsi_unbind,
+};
+
+static int hisi_dsi_probe(struct platform_device *pdev)
+{
+   struct hisi_dsi_context *ctx;
+   struct hisi_dsi *dsi;
+   struct resource *res;
+   struct device_node *slave_node;
+   struct device_node *np = pdev->dev.of_node;
+   int ret;
+
+   ctx = devm_kzalloc(>dev, sizeof(*ctx), GFP_KERNEL);
+   if (!ctx) {
+   DRM_ERROR("failed to allocate hisi dsi context.\n");
+   ret = -ENOMEM;
+   }
+
+   ctx->dsi_cfg_clk = devm_clk_get(>dev, "pclk_dsi");
+   if (IS_ERR(ctx->dsi_cfg_clk)) {
+   DRM_ERROR("failed to parse the dsi config clock\n");
+   ret = PTR_ERR(ctx->dsi_cfg_clk);
+   }
+
+   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   ctx->base = devm_ioremap_resource(>dev, res);
+   if (IS_ERR(ctx->base)) {
+   DRM_ERROR("failed to remap dsi io region\n");
+   ret = PTR_ERR(ctx->base);
+   }
+
+   slave_node = of_parse_phandle(np, "encoder-slave", 0);
+   if (!slave_node) {
+   DRM_ERROR("failed to parse the slave encoder node\n");
+   return -EINVAL;
+   }
+
+   dsi = >dsi;
+   dsi->ctx = ctx;
+   dsi->lanes = 3;
+   dsi->date_enable_pol = 0;
+   dsi->color_mode = DSI_24BITS_1;
+   dsi->format = MIPI_DSI_FMT_RGB888;
+   dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
+
+   return component_add(>dev, _dsi_ops);
+}
+


The DSI driver should register the dsi host via 
mipi_dsi_host_register(). That's the standard way of establishing a

connection between a host and dsi peripherals.

The dsi_context approach isn't something that will work very well.
With this approach, you're forced to set DSI parameters like number of
lanes, format, mode flags etc in the host driver, rather than receiving
them from the 

Re: [PATCH v4 15/16] clk: shmobile: mstp: Consider "zb_clk" suitable for power management

[Simon Horman]

Hi Mike, Hi Stephen,

On Tue, Aug 04, 2015 at 02:28:16PM +0200, Geert Uytterhoeven wrote:
> Currently the CPG/MSTP Clock Domain code looks for MSTP clocks to power
> manage a device.
> 
> Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0),
> the Bus State Controller (BSC) is not power-managed by an MSTP clock,
> but by a plain CPG clock (zb_clk).  Add a special case to handle this,
> so the clock is properly managed, and devices connected to the BSC work
> as expected.
> 
> Signed-off-by: Geert Uytterhoeven 
> Reviewed-by: Ulf Hansson 

for one reason or another I seem to have this patch queued up in
my renesas tree for v4.4, without any Acks.

I think it would be best if one of you took the patch instead.
Though I'm also happy to take it with Acks.

Let me know how you would like to proceed.

> ---
> v4:
>   - Add Reviewed-by,
> 
> v3:
>   - Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
> 
> v2:
>   - New.
> ---
>  drivers/clk/shmobile/clk-mstp.c | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c
> index b1df7b2f1e970adb..a117c3f0f257b5e1 100644
> --- a/drivers/clk/shmobile/clk-mstp.c
> +++ b/drivers/clk/shmobile/clk-mstp.c
> @@ -259,6 +259,10 @@ int cpg_mstp_attach_dev(struct generic_pm_domain 
> *domain, struct device *dev)
>   "renesas,cpg-mstp-clocks"))
>   goto found;
>  
> + /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock*/
> + if (!strcmp(clkspec.np->name, "zb_clk"))
> + goto found;
> +
>   of_node_put(clkspec.np);
>   i++;
>   }
> -- 
> 1.9.1
> 
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Re: [PATCH v1 1/3] ARM: dts: rockchip: add core rk3036 dts

[Xing Zheng]

On 2015年08月28日 16:59, Heiko Stuebner wrote:

Hi,

Am Freitag, 28. August 2015, 13:46:46 schrieb Xing Zheng:

Initial release for rk3036, node definitions rk3036 sdk board.

Signed-off-by: Xing Zheng
---

Changes in v1: None

  arch/arm/boot/dts/Makefile   |1 +
  arch/arm/boot/dts/rk3036-sdk.dts |  362
++ 2 files changed, 363 insertions(+)

as Eddie already said, please split into two files ... just look at the other
Rockchip socs for inspiration :-)

Done.

  create mode 100644 arch/arm/boot/dts/rk3036-sdk.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 6d7cec1..7014a3b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -501,6 +501,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3066a-bqcurie2.dtb \
rk3066a-marsboard.dtb \
rk3066a-rayeager.dtb \
+   rk3036-sdk.dtb \
rk3188-radxarock.dtb \
rk3288-evb-act8846.dtb \
rk3288-evb-rk808.dtb \
diff --git a/arch/arm/boot/dts/rk3036-sdk.dts
b/arch/arm/boot/dts/rk3036-sdk.dts new file mode 100644
index 000..0149c9a
--- /dev/null
+++ b/arch/arm/boot/dts/rk3036-sdk.dts
@@ -0,0 +1,362 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include
+#include
+#include
+#include
+#include
+#include "skeleton.dtsi"
+
+/ {
+   compatible = "rockchip,rk3036";
+
+   interrupt-parent =<>;
+
+   aliases {
+   serial0 =
+   serial1 =
+   serial2 =
+   };
+
+   memory {
+   reg =<0x6000 0x4000>;

missing
device_type = "memory";

Done.



+   };
+
+arm-pmu {
+compatible = "arm,cortex-a7-pmu";
+interrupts =,
+;

missing interrupt-affinity to map irq->cpu_core ?

Done.

+};
+
+   cpus {
+   #address-cells =<1>;
+   #size-cells =<0>;
+   //enable-method = "rockchip,rk3066-smp";

please don't leave commented code around


Done.

+
+   cpu@f00 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg =<0xf00>;
+   operating-points =<
+   /* KHzuV */
+816000 100
+   >;
+   #cooling-cells =<2>; /* min followed by max */
+   clock-latency =<4>;
+   clocks =< ARMCLK>;
+   resets =< SRST_CORE0>;
+   };
+   cpu@f01 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg =<0xf01>;
+   resets =< SRST_CORE1>;
+   };
+   };
+
+   amba {
+   compatible = "arm,amba-bus";
+   #address-cells =<1>;
+   #size-cells =<1>;
+   ranges;
+
+pdma: pdma@20078000 {
+

Re: [PATCH v1 3/3] clk: rockchip: add clock controller for rk3036

[Xing Zheng]

On 2015年08月28日 17:54, Heiko Stuebner wrote:

Hi,

Am Freitag, 28. August 2015, 13:46:48 schrieb Xing Zheng:

Add the clock tree definition for the new rk3036 SoC,
but there are some issues to be fixed:
1. soc will crash if gpll run rate_change_remuxed
2. rk3036_clk_suspend and rk3036_clk_resume should be done
in clk-rk3036.c

---

Changes in v1:
Signed-off-by: Xing Zheng

  drivers/clk/rockchip/Makefile  |1 +
  drivers/clk/rockchip/clk-pll.c |  247 ++-

please split this into separate patches.
- addition of the new pll type
- three patches for binding-document, dt-binding header and clock controller
   like in "clk: rockchip: add support for the clock-tree of the rk3368"
   patches 4, 5 and 7:
   "dt-bindings: add documentation of rk3036 clock controller"
   "clk: rockchip: add dt-binding header for rk3036"
   "clk: rockchip: add rk3036 clock controller"

   so you should get in sum 4 clock patches.

[0]http://lists.infradead.org/pipermail/linux-rockchip/2015-July/003394.html

OK.

  drivers/clk/rockchip/clk-rk3036.c  |  539
 drivers/clk/rockchip/clk.h |
30 ++
  include/dt-bindings/clock/rk3036-cru.h |  247 +++
  5 files changed, 1063 insertions(+), 1 deletion(-)
  create mode 100644 drivers/clk/rockchip/clk-rk3036.c
  create mode 100644 include/dt-bindings/clock/rk3036-cru.h

diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index b27edd6..d599829 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -10,6 +10,7 @@ obj-y += clk-inverter.o
  obj-y += clk-mmc-phase.o
  obj-$(CONFIG_RESET_CONTROLLER)+= softrst.o

+obj-y  += clk-rk3036.o
  obj-y += clk-rk3188.o
  obj-y += clk-rk3288.o
  obj-y += clk-rk3368.o
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 96903ae..cf56826 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -2,6 +2,9 @@
   * Copyright (c) 2014 MundoReader S.L.
   * Author: Heiko Stuebner
   *
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng
+ *
   * This program is free software; you can redistribute it and/or modify
   * it under the terms of the GNU General Public License as published by
   * the Free Software Foundation; either version 2 of the License, or
@@ -48,6 +51,8 @@ struct rockchip_clk_pll {
  #define to_rockchip_clk_pll_nb(nb) \
container_of(nb, struct rockchip_clk_pll, clk_nb)

+static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll);
+
  static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
struct rockchip_clk_pll *pll, unsigned long rate)
  {
@@ -90,6 +95,11 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll
*pll) unsigned int val;
int delay = 2400, ret;

+   /* the plls of rk3036 wait lock */
+   if (pll->type == pll_rk3036 || pll->lock_offset == -1) {
+   return rockchip_rk3036_pll_wait_lock(pll);
+   }
+

according to the rk3036 trm I have the GRF_SOC_STATUS0 [6:4] also contains the
pll lock status like on the other socs. So you could just use the default
mechanism of asking the GRF lock status like the other socs do, without
needing to override the wait_lock .

Oh, sorry, I missed this advice. I will check and test on next version.



while (delay>  0) {
ret = regmap_read(grf, pll->lock_offset,);
if (ret) {
@@ -305,6 +315,235 @@ static void rockchip_rk3066_pll_init(struct clk_hw
*hw) rockchip_rk3066_pll_set_rate(hw, drate, prate);
}
  }
+/**
+ * PLL used in RK3036
+ */
+
+#define RK3036_PLL_RESET_DELAY(nr) ((nr * 500) / 24 + 1)
+
+#define RK3036_PLLCON(i)   (i * 0x4)
+#define RK3036_PLLCON0_FBDIV_MASK  0xfff
+#define RK3036_PLLCON0_FBDIV_SHIFT 0
+#define RK3036_PLLCON0_POSTDIV1_MASK   0x7
+#define RK3036_PLLCON0_POSTDIV1_SHIFT  12
+#define RK3036_PLLCON1_REFDIV_MASK 0x3f
+#define RK3036_PLLCON1_REFDIV_SHIFT0
+#define RK3036_PLLCON1_POSTDIV2_MASK   0x7
+#define RK3036_PLLCON1_POSTDIV2_SHIFT  6
+#define RK3036_PLLCON1_DSMPD_MASK  0x1
+#define RK3036_PLLCON1_DSMPD_SHIFT 12
+#define RK3036_PLLCON2_FRAC_MASK   0xff
+#define RK3036_PLLCON2_FRAC_SHIFT  0
+
+#define RK3036_MODECON 0x40
+#define RK3036_MODECON_AWM (1<<  0)  /* apll work mode */
+
+#define RK3036_PLLCON0_BYPASS  (1<<  15)
+#define RK3036_PLLCON1_LOCK_STATUS (1<<  10)
+#define RK3036_PLLCON1_RESET   (1<<  14)
+
+static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll)
+{
+   u32 pllcon;
+   int delay = 2400;
+
+   /* poll check the lock status in rk3036 

Re: [PATCH v4 15/16] clk: shmobile: mstp: Consider "zb_clk" suitable for power management

[Simon Horman]

On Thu, Sep 17, 2015 at 05:45:18PM +0900, Simon Horman wrote:
> Hi Mike, Hi Stephen,
> 
> On Tue, Aug 04, 2015 at 02:28:16PM +0200, Geert Uytterhoeven wrote:
> > Currently the CPG/MSTP Clock Domain code looks for MSTP clocks to power
> > manage a device.
> > 
> > Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0),
> > the Bus State Controller (BSC) is not power-managed by an MSTP clock,
> > but by a plain CPG clock (zb_clk).  Add a special case to handle this,
> > so the clock is properly managed, and devices connected to the BSC work
> > as expected.
> > 
> > Signed-off-by: Geert Uytterhoeven 
> > Reviewed-by: Ulf Hansson 
> 
> for one reason or another I seem to have this patch queued up in
> my renesas tree for v4.4, without any Acks.
> 
> I think it would be best if one of you took the patch instead.
> Though I'm also happy to take it with Acks.
> 
> Let me know how you would like to proceed.

Sorry to revise the above, I should have checked more closely
before I sent my previous email. I now see that I have an SoC patch
that depends on this one. So if possible I'd like to take this one
through my tree with an Ack or two.

Thanks in advance!

> > ---
> > v4:
> >   - Add Reviewed-by,
> > 
> > v3:
> >   - Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
> > 
> > v2:
> >   - New.
> > ---
> >  drivers/clk/shmobile/clk-mstp.c | 4 
> >  1 file changed, 4 insertions(+)
> > 
> > diff --git a/drivers/clk/shmobile/clk-mstp.c 
> > b/drivers/clk/shmobile/clk-mstp.c
> > index b1df7b2f1e970adb..a117c3f0f257b5e1 100644
> > --- a/drivers/clk/shmobile/clk-mstp.c
> > +++ b/drivers/clk/shmobile/clk-mstp.c
> > @@ -259,6 +259,10 @@ int cpg_mstp_attach_dev(struct generic_pm_domain 
> > *domain, struct device *dev)
> > "renesas,cpg-mstp-clocks"))
> > goto found;
> >  
> > +   /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock*/
> > +   if (!strcmp(clkspec.np->name, "zb_clk"))
> > +   goto found;
> > +
> > of_node_put(clkspec.np);
> > i++;
> > }
> > -- 
> > 1.9.1
> > 
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Re: [PATCH v2 1/9] ARM: dts: rockchip: add core rk3036 dts

[Heiko Stübner]

Am Donnerstag, 17. September 2015, 16:28:52 schrieb Xing Zheng:
> Initial release for rk3036, node definitions rk3036 sdk board.
> 
> Signed-off-by: Xing Zheng 
> ---
> 
> Changes in v2: None
> 
>  arch/arm/boot/dts/Makefile   |1 +
>  arch/arm/boot/dts/rk3036-sdk.dts |   62 +++
>  arch/arm/boot/dts/rk3036.dtsi|  381
> ++ 3 files changed, 444 insertions(+)
>  create mode 100644 arch/arm/boot/dts/rk3036-sdk.dts
>  create mode 100644 arch/arm/boot/dts/rk3036.dtsi
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index d39ce4b..48260c4 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -502,6 +502,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
>   rk3066a-bqcurie2.dtb \
>   rk3066a-marsboard.dtb \
>   rk3066a-rayeager.dtb \
> + rk3036-sdk.dtb \

ordering ... please put the rk3036 above rk3066 boards


>   rk3188-radxarock.dtb \
>   rk3288-evb-act8846.dtb \
>   rk3288-evb-rk808.dtb \
> diff --git a/arch/arm/boot/dts/rk3036-sdk.dts
> b/arch/arm/boot/dts/rk3036-sdk.dts new file mode 100644
> index 000..9187f93
> --- /dev/null
> +++ b/arch/arm/boot/dts/rk3036-sdk.dts

or "rk3036-evb.dts"? What is the actual board named?

> @@ -0,0 +1,62 @@
> +/*
> + * Copyright (c)  2015 Xing Zheng 

this probably wants a Rockchip copyright notice?


> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + *  Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +
> +#include "rk3036.dtsi"
> +
> +/ {
> + model = "SDK-RK3036";
> + compatible = "sdk,sdk-rk3036", "rockchip,rk3036";

model = "Rockchip RK3036-SDK";
compatible = "rockchip,rk3036-sdk", "rockchip,rk3036";

or

model = "Rockchip RK3036 Evaluation board";
compatible = "rockchip,rk3036-evb", "rockchip,rk3036";

depending on what the real board is labeled


> +};
> +
> + {
> + status = "okay";
> +
> +hym8563: hym8563@51 {
> + compatible = "haoyu,hym8563";
> + reg = <0x51>;
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + clock-output-names = "xin32k";
> + };
> +};
> \ No newline at end of file

missing newline as stated above


> diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
> new file mode 100644
> index 000..b7459c0
> --- /dev/null
> +++ b/arch/arm/boot/dts/rk3036.dtsi
> @@ -0,0 +1,381 @@
> +/*
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This 

Re: [PATCH] regulator: tps65023: add device tree support

[Mark Brown]

On Thu, Sep 17, 2015 at 10:43:35AM +0200, Thomas Elste wrote:

> And I will use a separate patch for the binding document (just found
> Documentation/devicetree/bindings/submitting-patches.txt).

It's actually fine to just have them in the same patch for a simple
driver using established bindings like this - the DT maintainers are
unlikely to have the bandwidth to look at it anyway.  But splitting is
also OK.


signature.asc
Description: Digital signature

[PATCH v2 0/9] Build and support rk3036 SoC platform

[Xing Zheng]

Hi,
we need to support rk3036 soc platform via upstream, there are
3 primary parts for the initial release of minimum system: dts,
pinctrl, and clock tree for rk3036, and additional, add a rtc
hym8563 patch to fix initial invaild, we can use these startup
and run to init processs.

Thanks.

changed in v2:
- based on v1, add clock controller documentation
- enable timer5 startup
- add smp for cpu1
- initial set time for rtc-hym8563

changes since v1:
- add dts, pinctrl and clock tree for rk3036 soc platform

The patchset (9):
9) rtc: hym8563: make sure hym8563 can be normal work
8) ARM: rockchip: add support smp for rk3036
7) rockchip: make sure timer5 is enabled on rk3036 platforms
6) pinctrl: rockchip: add support for the rk3036
5) dt-bindings: add documentation of rk3036 clock controller
4) clk: rockchip: add new clock type and controller for rk3036
3) clk: rockchip: add clock controller for rk3036
2) clk: rockchip: add dt-binding header for rk3036
1) ARM: dts: rockchip: add core rk3036 dts


Changes in v2:
Signed-off-by: Xing Zheng 

Xing Zheng (9):
  ARM: dts: rockchip: add core rk3036 dts
  clk: rockchip: add dt-binding header for rk3036
  clk: rockchip: add clock controller for rk3036
  clk: rockchip: add new clock type and controller for rk3036
  dt-bindings: add documentation of rk3036 clock controller
  pinctrl: rockchip: add support for the rk3036
  rockchip: make sure timer5 is enabled on rk3036 platforms
  ARM: rockchip: add support smp for rk3036
  rtc: hym8563: make sure hym8563 can be normal work

 .../bindings/clock/rockchip,rk3036-cru.txt |   60 +++
 .../bindings/pinctrl/rockchip,pinctrl.txt  |1 +
 arch/arm/boot/dts/Makefile |1 +
 arch/arm/boot/dts/rk3036-sdk.dts   |   62 +++
 arch/arm/boot/dts/rk3036.dtsi  |  381 +++
 arch/arm/mach-rockchip/platsmp.c   |  121 +
 arch/arm/mach-rockchip/rockchip.c  |   22 +
 drivers/clk/rockchip/Makefile  |1 +
 drivers/clk/rockchip/clk-pll.c |  262 +-
 drivers/clk/rockchip/clk-rk3036.c  |  504 
 drivers/clk/rockchip/clk.h |   30 ++
 drivers/pinctrl/pinctrl-rockchip.c |   17 +
 drivers/rtc/rtc-hym8563.c  |   93 
 include/dt-bindings/clock/rk3036-cru.h |  198 
 14 files changed, 1752 insertions(+), 1 deletion(-)
 create mode 100644 
Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
 create mode 100644 arch/arm/boot/dts/rk3036-sdk.dts
 create mode 100644 arch/arm/boot/dts/rk3036.dtsi
 create mode 100644 drivers/clk/rockchip/clk-rk3036.c
 create mode 100644 include/dt-bindings/clock/rk3036-cru.h

-- 
1.7.9.5


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[PATCH v2 2/9] clk: rockchip: add dt-binding header for rk3036

[Xing Zheng]

Add the dt-bindings header for the rk3036, that gets shared between
the clock controller and the clock references in the dts.

Signed-off-by: Xing Zheng 
---

Changes in v2: None

 include/dt-bindings/clock/rk3036-cru.h |  198 
 1 file changed, 198 insertions(+)
 create mode 100644 include/dt-bindings/clock/rk3036-cru.h

diff --git a/include/dt-bindings/clock/rk3036-cru.h 
b/include/dt-bindings/clock/rk3036-cru.h
new file mode 100644
index 000..b0033ef
--- /dev/null
+++ b/include/dt-bindings/clock/rk3036-cru.h
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner 
+ *
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
+
+/* core clocks */
+#define PLL_APLL   1
+#define PLL_DPLL   2
+#define PLL_GPLL   3
+#define ARMCLK 4
+
+/* sclk gates (special clocks) */
+#define SCLK_GPU   64
+#define SCLK_SPI   65
+#define SCLK_SDMMC 68
+#define SCLK_SDIO  69
+#define SCLK_EMMC  71
+#define SCLK_NANDC 76
+#define SCLK_UART0 77
+#define SCLK_UART1 78
+#define SCLK_UART2 79
+#define SCLK_I2S   82
+#define SCLK_SPDIF 83
+#define SCLK_TIMER085
+#define SCLK_TIMER186
+#define SCLK_TIMER287
+#define SCLK_TIMER388
+#define SCLK_OTGPHY0   93
+#define SCLK_OTGPHY1   94
+#define SCLK_LCDC  100
+#define SCLK_HDMI  109
+#define SCLK_HEVC  111
+#define SCLK_I2S_OUT   113
+#define SCLK_SDMMC_DRV 114
+#define SCLK_SDIO_DRV  115
+#define SCLK_EMMC_DRV  117
+#define SCLK_SDMMC_SAMPLE  118
+#define SCLK_SDIO_SAMPLE   119
+#define SCLK_EMMC_SAMPLE   121
+#define SCLK_PVTM_CORE  123
+#define SCLK_PVTM_GPU   124
+#define SCLK_PVTM_VIDEO 125
+#define SCLK_MAC   151
+#define SCLK_MACREF152
+#define SCLK_SFC   160
+
+#define DCLK_LCDC  190
+
+/* aclk gates */
+#define ACLK_DMAC2 194
+#define ACLK_LCDC  197
+#define ACLK_VIO   203
+#define ACLK_VCODEC208
+#define ACLK_CPU   209
+#define ACLK_PERI  210
+
+/* pclk gates */
+#define PCLK_GPIO0 320
+#define PCLK_GPIO1 321
+#define PCLK_GPIO2 322
+#define PCLK_GRF   329
+#define PCLK_I2C0  332
+#define PCLK_I2C1  333
+#define PCLK_I2C2  334
+#define PCLK_SPI   338
+#define PCLK_UART0 341
+#define PCLK_UART1 342
+#define PCLK_UART2 343
+#define PCLK_PWM   350
+#define PCLK_TIMER 353
+#define PCLK_HDMI  360
+#define PCLK_CPU   362
+#define PCLK_PERI  363
+#define PCLK_DDRUPCTL  364
+#define PCLK_WDT   368
+
+/* hclk gates */
+#define HCLK_OTG0  449
+#define HCLK_OTG1  450
+#define HCLK_NANDC 453
+#define HCLK_SDMMC 456
+#define HCLK_SDIO  457
+#define HCLK_EMMC  459
+#define HCLK_I2S   462
+#define HCLK_LCDC  465
+#define HCLK_ROM   467
+#define HCLK_VIO_BUS   472
+#define HCLK_VCODEC476
+#define HCLK_CPU   477
+#define HCLK_PERI  478
+
+#define CLK_NR_CLKS(HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0 0
+#define SRST_CORE1 1
+#define SRST_CORE0_DBG 4
+#define SRST_CORE1_DBG 5
+#define SRST_CORE0_POR 8
+#define SRST_CORE1_POR 9
+#define SRST_L2C   12
+#define SRST_TOPDBG13
+#define SRST_STRC_SYS_A14
+#define SRST_PD_CORE_NIU   15
+
+#define SRST_TIMER216
+#define SRST_CPUSYS_H  17
+#define SRST_AHB2APB_H 19
+#define SRST_TIMER320
+#define SRST_INTMEM21
+#define SRST_ROM   22
+#define SRST_PERI_NIU  23
+#define SRST_I2S   24
+#define SRST_DDR_PLL   25
+#define SRST_GPU_DLL   26
+#define 

[PATCH 1/3] doc: dt: add documentation for Mediatek spi-nor controller

[Bayi Cheng]

Add device tree binding documentation for serial flash with
Mediatek serial flash controller

Change-Id: Iaecd0bb7ba1b224f1e27bd7063f0b8d7ea30175a
Signed-off-by: Bayi Cheng 
---
 Documentation/devicetree/bindings/mtd/mtk_quadspi.txt | 18 ++
 1 file changed, 18 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mtd/mtk_quadspi.txt

diff --git a/Documentation/devicetree/bindings/mtd/mtk_quadspi.txt 
b/Documentation/devicetree/bindings/mtd/mtk_quadspi.txt
new file mode 100644
index 000..6153227
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/mtk_quadspi.txt
@@ -0,0 +1,18 @@
+* MTD SPI nor driver for MTK MT81xx (and similar) serial flash controller
+
+Required properties:
+- compatible: Should be "mediatek,mt8173-nor";
+- reg: Physical base address and length of the controller's register
+- clocks: spi source clock amd serial flash controller's clock
+- clock-names: "spi", "sf"
+  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+
+Example:
+nor_flash: nor@1100d000 {
+   compatible = "mediatek,mt8173-nor";
+   reg = <0 0x1100D000 0 0xE0>;
+   clocks = < CLK_PERI_SPI>,
+< CLK_TOP_SPINFI_IFR_SEL>;
+   clock-names = "spi", "sf";
+};
+
-- 
1.8.1.1.dirty

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Re: [PATCH] regulator: tps65023: add device tree support

[Thomas Elste]

> > +static struct regulator_init_data*
> > +   of_get_tps65023_platform_data(struct device *dev)
> > +{
> > +   struct regulator_init_data *reg_data;
> > +   struct device_node *np = dev->of_node;
> > +   struct device_node *regulators;
> > +   struct of_regulator_match *matches;
> > +   int idx, count, ret;
> > +
> > +   regulators = of_get_child_by_name(np, "regulators");
> > +   if (!regulators) {
> > +   dev_err(dev, "Regulator node not found\n");
> > +   return NULL;
> > +   }
> 
> There's now core support for this so no need to open code in the
> driver
> - set of_match and regulators_node in the regulator_desc instead.
Thanks for reviewing. I'll change the patch to matching regulator nodes
via regulator core code.

And I will use a separate patch for the binding document (just found
Documentation/devicetree/bindings/submitting-patches.txt).


Best regards
Thomas

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Re: [PATCH v2 2/9] clk: rockchip: add dt-binding header for rk3036

[Heiko Stübner]

Am Donnerstag, 17. September 2015, 16:28:53 schrieb Xing Zheng:
> Add the dt-bindings header for the rk3036, that gets shared between
> the clock controller and the clock references in the dts.
> 
> Signed-off-by: Xing Zheng 
> ---
> 
> Changes in v2: None
> 
>  include/dt-bindings/clock/rk3036-cru.h |  198
>  1 file changed, 198 insertions(+)
>  create mode 100644 include/dt-bindings/clock/rk3036-cru.h
> 
> diff --git a/include/dt-bindings/clock/rk3036-cru.h
> b/include/dt-bindings/clock/rk3036-cru.h new file mode 100644
> index 000..b0033ef
> --- /dev/null
> +++ b/include/dt-bindings/clock/rk3036-cru.h
> @@ -0,0 +1,198 @@
> +/*
> + * Copyright (c) 2014 MundoReader S.L.
> + * Author: Heiko Stuebner 

you can probably drop that copyright line ... I didn't do anything here ;-)

> + *
> + * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
> + * Author: Xing Zheng 
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
> +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
> +
> +/* core clocks */
> +#define PLL_APLL 1
> +#define PLL_DPLL 2
> +#define PLL_GPLL 3
> +#define ARMCLK   4
> +
> +/* sclk gates (special clocks) */

you have a lot of gaps in the numbering ... intentional?


otherwise
Reviewed-by: Heiko Stuebner 

> +#define SCLK_GPU 64
> +#define SCLK_SPI 65
> +#define SCLK_SDMMC   68
> +#define SCLK_SDIO69
> +#define SCLK_EMMC71
> +#define SCLK_NANDC   76
> +#define SCLK_UART0   77
> +#define SCLK_UART1   78
> +#define SCLK_UART2   79
> +#define SCLK_I2S 82
> +#define SCLK_SPDIF   83
> +#define SCLK_TIMER0  85
> +#define SCLK_TIMER1  86
> +#define SCLK_TIMER2  87
> +#define SCLK_TIMER3  88
> +#define SCLK_OTGPHY0 93
> +#define SCLK_OTGPHY1 94
> +#define SCLK_LCDC100
> +#define SCLK_HDMI109
> +#define SCLK_HEVC111
> +#define SCLK_I2S_OUT 113
> +#define SCLK_SDMMC_DRV   114
> +#define SCLK_SDIO_DRV115
> +#define SCLK_EMMC_DRV117
> +#define SCLK_SDMMC_SAMPLE118
> +#define SCLK_SDIO_SAMPLE 119
> +#define SCLK_EMMC_SAMPLE 121
> +#define SCLK_PVTM_CORE  123
> +#define SCLK_PVTM_GPU   124
> +#define SCLK_PVTM_VIDEO 125
> +#define SCLK_MAC 151
> +#define SCLK_MACREF  152
> +#define SCLK_SFC 160
> +
> +#define DCLK_LCDC190
> +
> +/* aclk gates */
> +#define ACLK_DMAC2   194
> +#define ACLK_LCDC197
> +#define ACLK_VIO 203
> +#define ACLK_VCODEC  208
> +#define ACLK_CPU 209
> +#define ACLK_PERI210
> +
> +/* pclk gates */
> +#define PCLK_GPIO0   320
> +#define PCLK_GPIO1   321
> +#define PCLK_GPIO2   322
> +#define PCLK_GRF 329
> +#define PCLK_I2C0332
> +#define PCLK_I2C1333
> +#define PCLK_I2C2334
> +#define PCLK_SPI 338
> +#define PCLK_UART0   341
> +#define PCLK_UART1   342
> +#define PCLK_UART2   343
> +#define PCLK_PWM 350
> +#define PCLK_TIMER   353
> +#define PCLK_HDMI360
> +#define PCLK_CPU 362
> +#define PCLK_PERI363
> +#define PCLK_DDRUPCTL364
> +#define PCLK_WDT 368
> +
> +/* hclk gates */
> +#define HCLK_OTG0449
> +#define HCLK_OTG1450
> +#define HCLK_NANDC   453
> +#define HCLK_SDMMC   456
> +#define HCLK_SDIO457
> +#define HCLK_EMMC459
> +#define HCLK_I2S 462
> +#define HCLK_LCDC465
> +#define HCLK_ROM 467
> +#define HCLK_VIO_BUS 472
> +#define HCLK_VCODEC  476
> +#define HCLK_CPU 477
> +#define HCLK_PERI478
> +
> +#define CLK_NR_CLKS  (HCLK_PERI + 1)
> +
> +/* soft-reset indices */
> +#define SRST_CORE0   0
> +#define SRST_CORE1   1
> +#define SRST_CORE0_DBG   4
> +#define SRST_CORE1_DBG   5
> +#define SRST_CORE0_POR   8
> +#define SRST_CORE1_POR   9
> +#define SRST_L2C 12
> +#define SRST_TOPDBG  13
> 

Re: [RESEND PATCH 0/2] ST PLL fixes for 4.3-rc2

[Maxime Coquelin]

On 09/17/2015 12:30 AM, Stephen Boyd wrote:

On 09/16, Gabriel Fernandez wrote:

This patch set fixes a kernel crash :

[..]

This kernel crash is due to a broken compatibility with this commit:
commit 5eb26c605909 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into 
st_pll3200c32_cx_x")

It isn't clear who's supposed to apply this because the To: list
is huge. Did you want to take this through arm-soc? If so, feel
free to take my acked-by on the second patch. The first patch
doesn't even apply to clk tree because the patch introducing the
typo didn't go through our tree.

Indeed Stephen, I see it went through my tree (STi DT).
So the first patch should be taken through arm-soc.
The second patch, should be taken through yours I think.

Regards,
Maxime
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Re: [PATCH v2 09/11] devicetree: bindings: Remove unused 32-bit CMT bindings

[Magnus Damm]

Hi Sergei,

On Thu, Sep 17, 2015 at 9:14 PM, Sergei Shtylyov
 wrote:
> Hello.
>
> On 9/17/2015 12:54 PM, Magnus Damm wrote:
>
>> From: Magnus Damm 
>>
>> Remove the 32-bit CMT compat strings to reduce maintenance burden.
>>
>> It should be fine to break DT compatibility because the 32-bit
>> 32-bit CMT DT binding was never part of any upstream DTS file.
>
>
>Nit: "32-bit" repeated twice.

Oops, will fix, thanks for reporting!

Cheers,

/ magnus
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Re: [PATCH v2 6/9] pinctrl: rockchip: add support for the rk3036

[Heiko Stübner]

Am Donnerstag, 17. September 2015, 18:34:20 schrieb Xing Zheng:
> Add new type for rk3036 and many parts of pinctrl rk3036 are similar
> with rk2928's.
> 
> Signed-off-by: Xing Zheng 

very nice that the rk3036 pin-controller works with already established 
infrastructure :-)

Reviewed-by: Heiko Stuebner 

> ---
> 
> Changes in v2: None
> 
>  .../bindings/pinctrl/rockchip,pinctrl.txt  |1 +
>  drivers/pinctrl/pinctrl-rockchip.c |   17 +
> 2 files changed, 18 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
> b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt index
> 391ef4b..c73f2bb 100644
> --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
> @@ -22,6 +22,7 @@ Required properties for iomux controller:
>- compatible: one of "rockchip,rk2928-pinctrl",
> "rockchip,rk3066a-pinctrl" "rockchip,rk3066b-pinctrl",
> "rockchip,rk3188-pinctrl"
>  "rockchip,rk3288-pinctrl", "rockchip,rk3368-pinctrl"
> +"rockchip,rk3036-pinctrl"
>- rockchip,grf: phandle referencing a syscon providing the
>"general register files"
> 
> diff --git a/drivers/pinctrl/pinctrl-rockchip.c
> b/drivers/pinctrl/pinctrl-rockchip.c index c5246c0..9c49510 100644
> --- a/drivers/pinctrl/pinctrl-rockchip.c
> +++ b/drivers/pinctrl/pinctrl-rockchip.c
> @@ -2089,6 +2089,21 @@ static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
>   .pull_calc_reg  = rk2928_calc_pull_reg_and_bit,
>  };
> 
> +static struct rockchip_pin_bank rk3036_pin_banks[] = {
> + PIN_BANK(0, 32, "gpio0"),
> + PIN_BANK(1, 32, "gpio1"),
> + PIN_BANK(2, 32, "gpio2"),
> +};
> +
> +static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
> + .pin_banks  = rk3036_pin_banks,
> + .nr_banks   = ARRAY_SIZE(rk3036_pin_banks),
> + .label  = "RK3036-GPIO",
> + .type   = RK2928,
> + .grf_mux_offset = 0xa8,
> + .pull_calc_reg  = rk2928_calc_pull_reg_and_bit,
> +};
> +
>  static struct rockchip_pin_bank rk3066a_pin_banks[] = {
>   PIN_BANK(0, 32, "gpio0"),
>   PIN_BANK(1, 32, "gpio1"),
> @@ -2207,6 +,8 @@ static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
>  static const struct of_device_id rockchip_pinctrl_dt_match[] = {
>   { .compatible = "rockchip,rk2928-pinctrl",
>   .data = (void *)_pin_ctrl },
> + { .compatible = "rockchip,rk3036-pinctrl",
> + .data = (void *)_pin_ctrl },
>   { .compatible = "rockchip,rk3066a-pinctrl",
>   .data = (void *)_pin_ctrl },
>   { .compatible = "rockchip,rk3066b-pinctrl",

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[PATCH RESEND] ARM: dts: Move display-timings node from fimd to dp

[Tomeu Vizoso]

From: Sean Paul 

This patch moves the display-timings node from fimd to dp to reflect the
device tree bindings change.

Signed-off-by: Sean Paul 
[tomeu.viz...@collabora.com: Rebased]
Signed-off-by: Tomeu Vizoso 

---

Hi,

looks like a long time ago the bindings were changed and the DTs for
these boards weren't updated.

I have retaken Sean's forgotten patch and rebased it, but I have only
tested on an Arndale that exynos-drm doesn't complain about missing
timings.

Regards,

Tomeu
---
 arch/arm/boot/dts/exynos5250-arndale.dts  |  8 
 arch/arm/boot/dts/exynos5250-smdk5250.dts | 16 
 arch/arm/boot/dts/exynos5420-smdk5420.dts |  7 ---
 3 files changed, 16 insertions(+), 15 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts 
b/arch/arm/boot/dts/exynos5250-arndale.dts
index db3f65f3eb45..c000532c1444 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -129,10 +129,6 @@
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <4>;
-};
-
- {
-   status = "okay";
 
display-timings {
native-mode = <>;
@@ -152,6 +148,10 @@
};
 };
 
+ {
+   status = "okay";
+};
+
  {
hpd-gpio = < 7 GPIO_ACTIVE_LOW>;
vdd_osc-supply = <_reg>;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts 
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index c625e71217aa..0f5dcd418af8 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -89,14 +89,6 @@
pinctrl-names = "default";
pinctrl-0 = <_hpd>;
status = "okay";
-};
-
- {
-   samsung,vbus-gpio = < 6 GPIO_ACTIVE_HIGH>;
-};
-
- {
-   status = "okay";
 
display-timings {
native-mode = <>;
@@ -116,6 +108,14 @@
};
 };
 
+ {
+   samsung,vbus-gpio = < 6 GPIO_ACTIVE_HIGH>;
+};
+
+ {
+   status = "okay";
+};
+
  {
hpd-gpio = < 7 GPIO_ACTIVE_HIGH>;
 };
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts 
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 98871f972c8a..7520d52f4e22 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -98,10 +98,7 @@
samsung,link-rate = <0x0a>;
samsung,lane-count = <4>;
status = "okay";
-};
 
- {
-   status = "okay";
display-timings {
native-mode = <>;
timing0: timing@0 {
@@ -118,6 +115,10 @@
};
 };
 
+ {
+   status = "okay";
+};
+
  {
status = "okay";
hpd-gpio = < 7 0>;
-- 
2.4.3

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[PATCH 1/3] ASoC: codecs: Add da7219 codec driver

[Adam Thomson]

This adds support for the DA7219 audio codec with built-in advanced
accessory detect features.

Signed-off-by: Adam Thomson 
---
 include/sound/da7219-aad.h|   99 +++
 include/sound/da7219.h|   76 ++
 sound/soc/codecs/Kconfig  |4 +
 sound/soc/codecs/Makefile |2 +
 sound/soc/codecs/da7219-aad.c |  800 ++
 sound/soc/codecs/da7219-aad.h |  209 +
 sound/soc/codecs/da7219.c | 1877 +
 sound/soc/codecs/da7219.h |  807 ++
 8 files changed, 3874 insertions(+)
 create mode 100644 include/sound/da7219-aad.h
 create mode 100644 include/sound/da7219.h
 create mode 100644 sound/soc/codecs/da7219-aad.c
 create mode 100644 sound/soc/codecs/da7219-aad.h
 create mode 100644 sound/soc/codecs/da7219.c
 create mode 100644 sound/soc/codecs/da7219.h

diff --git a/include/sound/da7219-aad.h b/include/sound/da7219-aad.h
new file mode 100644
index 000..17802fb
--- /dev/null
+++ b/include/sound/da7219-aad.h
@@ -0,0 +1,99 @@
+/*
+ * da7219-aad.h - DA7322 ASoC Codec AAD Driver Platform Data
+ *
+ * Copyright (c) 2015 Dialog Semiconductor Ltd.
+ *
+ * Author: Adam Thomson 
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __DA7219_AAD_PDATA_H
+#define __DA7219_AAD_PDATA_H
+
+enum da7219_aad_micbias_pulse_lvl {
+   DA7219_AAD_MICBIAS_PULSE_LVL_OFF = 0,
+   DA7219_AAD_MICBIAS_PULSE_LVL_2_8V = 6,
+   DA7219_AAD_MICBIAS_PULSE_LVL_2_9V,
+};
+
+enum da7219_aad_btn_cfg {
+   DA7219_AAD_BTN_CFG_2MS = 1,
+   DA7219_AAD_BTN_CFG_5MS,
+   DA7219_AAD_BTN_CFG_10MS,
+   DA7219_AAD_BTN_CFG_50MS,
+   DA7219_AAD_BTN_CFG_100MS,
+   DA7219_AAD_BTN_CFG_200MS,
+   DA7219_AAD_BTN_CFG_500MS,
+};
+
+enum da7219_aad_mic_det_thr {
+   DA7219_AAD_MIC_DET_THR_200_OHMS = 0,
+   DA7219_AAD_MIC_DET_THR_500_OHMS,
+   DA7219_AAD_MIC_DET_THR_750_OHMS,
+   DA7219_AAD_MIC_DET_THR_1000_OHMS,
+};
+
+enum da7219_aad_jack_ins_deb {
+   DA7219_AAD_JACK_INS_DEB_5MS = 0,
+   DA7219_AAD_JACK_INS_DEB_10MS,
+   DA7219_AAD_JACK_INS_DEB_20MS,
+   DA7219_AAD_JACK_INS_DEB_50MS,
+   DA7219_AAD_JACK_INS_DEB_100MS,
+   DA7219_AAD_JACK_INS_DEB_200MS,
+   DA7219_AAD_JACK_INS_DEB_500MS,
+   DA7219_AAD_JACK_INS_DEB_1S,
+};
+
+enum da7219_aad_jack_det_rate {
+   DA7219_AAD_JACK_DET_RATE_32_64MS = 0,
+   DA7219_AAD_JACK_DET_RATE_64_128MS,
+   DA7219_AAD_JACK_DET_RATE_128_256MS,
+   DA7219_AAD_JACK_DET_RATE_256_512MS,
+};
+
+enum da7219_aad_jack_rem_deb {
+   DA7219_AAD_JACK_REM_DEB_1MS = 0,
+   DA7219_AAD_JACK_REM_DEB_5MS,
+   DA7219_AAD_JACK_REM_DEB_10MS,
+   DA7219_AAD_JACK_REM_DEB_20MS,
+};
+
+enum da7219_aad_btn_avg {
+   DA7219_AAD_BTN_AVG_1 = 0,
+   DA7219_AAD_BTN_AVG_2,
+   DA7219_AAD_BTN_AVG_4,
+   DA7219_AAD_BTN_AVG_8,
+};
+
+enum da7219_aad_adc_1bit_rpt {
+   DA7219_AAD_ADC_1BIT_RPT_1 = 0,
+   DA7219_AAD_ADC_1BIT_RPT_2,
+   DA7219_AAD_ADC_1BIT_RPT_4,
+   DA7219_AAD_ADC_1BIT_RPT_8,
+};
+
+struct da7219_aad_pdata {
+   int irq;
+
+   enum da7219_aad_micbias_pulse_lvl micbias_pulse_lvl;
+   u32 micbias_pulse_time;
+   enum da7219_aad_btn_cfg btn_cfg;
+   enum da7219_aad_mic_det_thr mic_det_thr;
+   enum da7219_aad_jack_ins_deb jack_ins_deb;
+   enum da7219_aad_jack_det_rate jack_det_rate;
+   enum da7219_aad_jack_rem_deb jack_rem_deb;
+
+   u8 a_d_btn_thr;
+   u8 d_b_btn_thr;
+   u8 b_c_btn_thr;
+   u8 c_mic_btn_thr;
+
+   enum da7219_aad_btn_avg btn_avg;
+   enum da7219_aad_adc_1bit_rpt adc_1bit_rpt;
+};
+
+#endif /* __DA7219_AAD_PDATA_H */
diff --git a/include/sound/da7219.h b/include/sound/da7219.h
new file mode 100644
index 000..f246df2
--- /dev/null
+++ b/include/sound/da7219.h
@@ -0,0 +1,76 @@
+/*
+ * da7219.h - DA7219 ASoC Codec Driver Platform Data
+ *
+ * Copyright (c) 2015 Dialog Semiconductor
+ *
+ * Author: Adam Thomson 
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __DA7219_PDATA_H
+#define __DA7219_PDATA_H
+
+/* IO Voltage */
+enum da7219_io_voltage_lvl {
+   DA7219_IO_VOLTAGE_LVL_2_5V_3_6V = 0,
+   DA7219_IO_VOLTAGE_LVL_1_2V_2_8V
+};
+
+/* LDO */
+enum da7219_ldo_lvl_sel {
+   DA7219_LDO_LVL_SEL_1_05V = 0,
+   DA7219_LDO_LVL_SEL_1_10V,
+   DA7219_LDO_LVL_SEL_1_20V,
+   DA7219_LDO_LVL_SEL_1_40V,
+};
+
+/* Mic Bias */
+enum da7219_micbias_voltage {
+   

[PATCH 3/3] MAINTAINERS: da7219: Add entry to cover DA7219 bindings document

[Adam Thomson]

This adds an entry to indicate the DA7219 bindings document (and
other Dialog codecs bindings documents) are supported.

Signed-off-by: Adam Thomson 
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 7ba7ab7..a235822 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3361,6 +3361,7 @@ M:Support Opensource 

 W: http://www.dialog-semiconductor.com/products
 S: Supported
 F: Documentation/hwmon/da90??
+F: Documentation/devicetree/bindings/sound/da[79]*.txt
 F: drivers/gpio/gpio-da90??.c
 F: drivers/hwmon/da90??-hwmon.c
 F: drivers/iio/adc/da91??-*.c
-- 
1.9.3

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[PATCH v5 21/23] driver core: Allow deferring probes until late init

[Tomeu Vizoso]

Add a field to struct device that instructs the device-driver core to
defer the probe of this device until the late_initcall level.

By letting all built-in drivers to register before starting to probe, we
can avoid any deferred probes by probing dependencies on demand.

Signed-off-by: Tomeu Vizoso 

---

Changes in v5: None
Changes in v4:
- Add Kconfig DELAY_DEVICE_PROBES to allow disabling delayed probing in
  machines with initcalls that depend on devices probing at a given time.

Changes in v3: None
Changes in v2: None

 drivers/base/Kconfig   | 18 ++
 drivers/base/dd.c  |  7 +++
 include/linux/device.h |  2 ++
 3 files changed, 27 insertions(+)

diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig
index 98504ec99c7d..44b5d33b1f49 100644
--- a/drivers/base/Kconfig
+++ b/drivers/base/Kconfig
@@ -324,4 +324,22 @@ config CMA_ALIGNMENT
 
 endif
 
+config DELAY_DEVICE_PROBES
+   bool "Allow delaying the probe of some devices"
+   default y
+   help
+ Devices can be matched to a driver and probed from the moment they
+ are registered, but early during boot their probes are likely to be
+ deferred because some dependency isn't available yet because most
+ drivers haven't been registered yet.
+
+ Enabling this option allows the device registration code to delay the
+ probing of a specific device until device_initcall_sync, when all
+ built-in drivers have been registered already.
+
+ In some platforms there may be implicit assumptions about when some
+ devices are probed, so enabling this option could cause problems 
there.
+
+ If unsure, say Y here.
+
 endmenu
diff --git a/drivers/base/dd.c b/drivers/base/dd.c
index 5caa8478404d..300c59562fc9 100644
--- a/drivers/base/dd.c
+++ b/drivers/base/dd.c
@@ -417,6 +417,13 @@ int driver_probe_device(struct device_driver *drv, struct 
device *dev)
if (!device_is_registered(dev))
return -ENODEV;
 
+#if IS_ENABLED(CONFIG_DELAY_DEVICE_PROBES)
+   if (!driver_deferred_probe_enable && dev->probe_late) {
+   driver_deferred_probe_add(dev);
+   return 0;
+   }
+#endif
+
pr_debug("bus: '%s': %s: matched device %s with driver %s\n",
 drv->bus->name, __func__, dev_name(dev), drv->name);
 
diff --git a/include/linux/device.h b/include/linux/device.h
index d8be07bc9c3f..fe5c50ffd7d3 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -748,6 +748,7 @@ struct device_dma_parameters {
  *
  * @offline_disabled: If set, the device is permanently online.
  * @offline:   Set after successful invocation of bus type's .offline().
+ * @probe_late:If set, device will be probed in the late initcall 
level.
  *
  * At the lowest level, every device in a Linux system is represented by an
  * instance of struct device. The device structure contains the information
@@ -832,6 +833,7 @@ struct device {
 
booloffline_disabled:1;
booloffline:1;
+   boolprobe_late:1;
 };
 
 static inline struct device *kobj_to_dev(struct kobject *kobj)
-- 
2.4.3

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[PATCH v5 17/23] pinctrl: Probe pinctrl devices on demand

[Tomeu Vizoso]

When looking up a pin controller through its OF node, probe it if it
hasn't already.

The goal is to reduce deferred probes to a minimum, as it makes it very
cumbersome to find out why a device failed to probe, and can introduce
very big delays in when a critical device is probed.

Signed-off-by: Tomeu Vizoso 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/pinctrl/devicetree.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c
index fe04e748dfe4..f5340b8e1dbe 100644
--- a/drivers/pinctrl/devicetree.c
+++ b/drivers/pinctrl/devicetree.c
@@ -18,6 +18,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -110,6 +111,8 @@ static int dt_to_map_one_config(struct pinctrl *p, const 
char *statename,
struct pinctrl_map *map;
unsigned num_maps;
 
+   of_device_probe(np_config);
+
/* Find the pin controller containing np_config */
np_pctldev = of_node_get(np_config);
for (;;) {
-- 
2.4.3

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[PATCH v5 18/23] phy: core: Probe phy providers on demand

[Tomeu Vizoso]

When looking up a phy provider through its OF node, probe it if it
hasn't already.

The goal is to reduce deferred probes to a minimum, as it makes it very
cumbersome to find out why a device failed to probe, and can introduce
very big delays in when a critical device is probed.

Signed-off-by: Tomeu Vizoso 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/phy/phy-core.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index fc48fac003a6..94e90031d7f3 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -363,6 +364,8 @@ static struct phy *_of_phy_get(struct device_node *np, int 
index)
if (ret)
return ERR_PTR(-ENODEV);
 
+   of_device_probe(args.np);
+
mutex_lock(_provider_mutex);
phy_provider = of_phy_provider_lookup(args.np);
if (IS_ERR(phy_provider) || !try_module_get(phy_provider->owner)) {
-- 
2.4.3

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[PATCH v5 19/23] dma: of: Probe DMA controllers on demand

[Tomeu Vizoso]

When looking up a DMA controller through its OF node, probe it if it
hasn't already.

The goal is to reduce deferred probes to a minimum, as it makes it very
cumbersome to find out why a device failed to probe, and can introduce
very big delays in when a critical device is probed.

Signed-off-by: Tomeu Vizoso 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/dma/of-dma.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/dma/of-dma.c b/drivers/dma/of-dma.c
index 1e1f2986eba8..e899832f7df3 100644
--- a/drivers/dma/of-dma.c
+++ b/drivers/dma/of-dma.c
@@ -16,6 +16,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 static LIST_HEAD(of_dma_list);
@@ -263,6 +264,8 @@ struct dma_chan *of_dma_request_slave_channel(struct 
device_node *np,
if (of_dma_match_channel(np, name, i, _spec))
continue;
 
+   of_device_probe(dma_spec.np);
+
mutex_lock(_dma_lock);
ofdma = of_dma_find_controller(_spec);
 
-- 
2.4.3

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[PATCH v5 16/23] clk: Probe clk providers on demand

[Tomeu Vizoso]

When looking up a clock through its OF node, probe it if it hasn't
already.

The goal is to reduce deferred probes to a minimum, as it makes it very
cumbersome to find out why a device failed to probe, and can introduce
very big delays in when a critical device is probed.

Signed-off-by: Tomeu Vizoso 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/clk/clk.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 43e2c3ad6c31..e5fe02a11c36 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -3004,6 +3005,8 @@ struct clk *__of_clk_get_from_provider(struct 
of_phandle_args *clkspec,
if (!clkspec)
return ERR_PTR(-EINVAL);
 
+   of_device_probe(clkspec->np);
+
/* Check if we have such a provider in our array */
mutex_lock(_clk_mutex);
list_for_each_entry(provider, _clk_providers, link) {
-- 
2.4.3

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[PATCH v2 1/7] Documentation: hw_random: Fix device node name reference /dev/hw_random => /dev/hwrng

[Lee Jones]

In April 2009, commit d405640 ("Driver Core: misc: add node name support
for misc devices.") inadvertently changed the device node name from
/dev/hw_random to /dev/hwrng.  Since 6 years has passed since the change
it seems unpractical to change it back, as this node name is probably
considered ABI by now.  So instead, we'll just change the documentation
to match the current situation.

NB: It looks like rng-tools have already been updated.

Signed-off-by: Lee Jones 
---
 Documentation/hw_random.txt | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/Documentation/hw_random.txt b/Documentation/hw_random.txt
index 026e237..fce1634 100644
--- a/Documentation/hw_random.txt
+++ b/Documentation/hw_random.txt
@@ -3,7 +3,7 @@ Introduction:
The hw_random framework is software that makes use of a
special hardware feature on your CPU or motherboard,
a Random Number Generator (RNG).  The software has two parts:
-   a core providing the /dev/hw_random character device and its
+   a core providing the /dev/hwrng character device and its
sysfs support, plus a hardware-specific driver that plugs
into that core.
 
@@ -14,7 +14,7 @@ Introduction:
 
http://sourceforge.net/projects/gkernel/
 
-   Those tools use /dev/hw_random to fill the kernel entropy pool,
+   Those tools use /dev/hwrng to fill the kernel entropy pool,
which is used internally and exported by the /dev/urandom and
/dev/random special files.
 
@@ -32,13 +32,13 @@ Theory of operation:
The rng-tools package uses such tests in "rngd", and lets you
run them by hand with a "rngtest" utility.
 
-   /dev/hw_random is char device major 10, minor 183.
+   /dev/hwrng is char device major 10, minor 183.
 
CLASS DEVICE.  There is a /sys/class/misc/hw_random node with
two unique attributes, "rng_available" and "rng_current".  The
"rng_available" attribute lists the hardware-specific drivers
available, while "rng_current" lists the one which is currently
-   connected to /dev/hw_random.  If your system has more than one
+   connected to /dev/hwrng.  If your system has more than one
RNG available, you may change the one used by writing a name from
the list in "rng_available" into "rng_current".
 
-- 
1.9.1

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Re: [PATCH v2 2/2] of: changesets: Introduce changeset helper methods

[Rob Herring]

On 09/16/2015 11:11 AM, Pantelis Antoniou wrote:
> Changesets are very powerful, but the lack of a helper API
> makes using them cumbersome. Introduce a simple copy based
> API that makes things considerably easier.
> 
> To wit, adding a property using the raw API.
> 
>   struct property *prop;
>   prop = kzalloc(sizeof(*prop)), GFP_KERNEL);
>   prop->name = kstrdup("compatible");
>   prop->value = kstrdup("foo,bar");
>   prop->length = strlen(prop->value) + 1;
>   of_changeset_add_property(ocs, np, prop);
> 
> while using the helper API
> 
>   of_changeset_add_property_string(ocs, np, "compatible",
>   "foo,bar");

How about updating the unittest to use this.

> 
> Signed-off-by: Pantelis Antoniou 
> ---
>  drivers/of/dynamic.c | 251 
> +++
>  include/linux/of.h   |  74 +++
>  2 files changed, 325 insertions(+)
> 
> diff --git a/drivers/of/dynamic.c b/drivers/of/dynamic.c
> index e452171..afa8e31 100644
> --- a/drivers/of/dynamic.c
> +++ b/drivers/of/dynamic.c
> @@ -796,3 +796,254 @@ int of_changeset_action(struct of_changeset *ocs, 
> unsigned long action,
>   list_add_tail(>node, >entries);
>   return 0;
>  }
> +
> +/* changeset helpers */
> +
> +/**
> + * of_changeset_create_device_node - Create an empty device node
> + *
> + * @ocs: changeset pointer
> + * @parent:  parent device node
> + * @fmt: format string for the node's full_name
> + * @args:argument list for the format string
> + *
> + * Create an empty device node, marking it as detached and allocated.
> + *
> + * Returns a device node on success, an error encoded pointer otherwise
> + */
> +struct device_node *of_changeset_create_device_nodev(
> + struct of_changeset *ocs, struct device_node *parent,
> + const char *fmt, va_list vargs)
> +{
> + struct device_node *node;
> +
> + node = __of_node_dupv(NULL, fmt, vargs);
> + if (!node)
> + return ERR_PTR(-ENOMEM);
> +
> + node->parent = parent;
> + return node;
> +}

EXPORT_SYMBOL_GPL here and on others?

> +
> +/**
> + * of_changeset_create_device_node - Create an empty device node
> + *
> + * @ocs: changeset pointer
> + * @parent:  parent device node
> + * @fmt: Format string for the node's full_name
> + * ...   Arguments
> + *
> + * Create an empty device node, marking it as detached and allocated.
> + *
> + * Returns a device node on success, an error encoded pointer otherwise
> + */
> +struct device_node *of_changeset_create_device_node(
> + struct of_changeset *ocs, struct device_node *parent,
> + const char *fmt, ...)
> +{
> + va_list vargs;
> + struct device_node *node;
> +
> + va_start(vargs, fmt);
> + node = of_changeset_create_device_nodev(ocs, parent, fmt, vargs);
> + va_end(vargs);
> + return node;
> +}
> +
> +/**
> + * of_changeset_add_property_copy - Create a new property copying name & 
> value
> + *
> + * @ocs: changeset pointer
> + * @np:  device node pointer
> + * @name:name of the property
> + * @value:   pointer to the value data
> + * @length:  length of the value in bytes
> + *
> + * Adds a property to the changeset by making copies of the name & value
> + * entries.
> + *
> + * Returns zero on success, a negative error value otherwise.
> + */
> +int of_changeset_add_property_copy(struct of_changeset *ocs,
> + struct device_node *np, const char *name, const void *value,
> + int length)
> +{
> + struct property *prop;
> + char *new_name;
> + void *new_value;

> + int ret;
> +
> + ret = -ENOMEM;

One line

> +
> + prop = kzalloc(sizeof(*prop), GFP_KERNEL);
> + if (!prop)
> + goto out_no_prop;
> +
> + new_name = kstrdup(name, GFP_KERNEL);
> + if (!new_name)
> + goto out_no_name;
> +
> + /*
> +  * NOTE: There is no check for zero length value.
> +  * In case of a boolean property, this will allocate a value
> +  * of zero bytes. We do this to work around the use
> +  * of of_get_property() calls on boolean values.
> +  */
> + new_value = kmemdup(value, length, GFP_KERNEL);
> + if (!new_value)
> + goto out_no_value;
> +
> + of_property_set_flag(prop, OF_DYNAMIC);
> +
> + prop->name = new_name;
> + prop->value = new_value;
> + prop->length = length;
> +
> + ret = of_changeset_add_property(ocs, np, prop);
> + if (ret != 0)
> + goto out_no_add;
> +
> + return 0;
> +
> +out_no_add:
> + kfree(prop->value);
> +out_no_value:
> + kfree(prop->name);
> +out_no_name:
> + kfree(prop);
> +out_no_prop:
> + return ret;
> +}
> +
> +/**
> + * of_changeset_add_property_string - Create a new string property
> + *
> + * @ocs: changeset pointer
> + * @np:  device node pointer
> + * @name:name of the property
> + * @str: string 

[PATCH 2/3] ASoC: da7219: Add bindings documentation for DA7219 audio codec

[Adam Thomson]

Signed-off-by: Adam Thomson 
---
 Documentation/devicetree/bindings/sound/da7219.txt | 106 +
 1 file changed, 106 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sound/da7219.txt

diff --git a/Documentation/devicetree/bindings/sound/da7219.txt 
b/Documentation/devicetree/bindings/sound/da7219.txt
new file mode 100644
index 000..b29fe2e
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/da7219.txt
@@ -0,0 +1,106 @@
+Dialog Semiconductor DA7219 Audio Codec bindings
+
+DA7219 is an audio codec with advanced accessory detect features.
+
+==
+
+Required properties:
+- compatible : Should be "dlg,da7219"
+- reg: Specifies the I2C slave address
+
+Optional properties:
+- wakeup-source: Flag to indicate this device can wake system (suspend/resume).
+
+- clocks : phandle and clock specifier for codec MCLK.
+- clock-names : Clock name string for 'clocks' attribute, should be "mclk".
+
+- dlg,io-lvl : Expected voltage level range for digital IO
+   ["2.5V_3.6V", "1.2V_2.8V"]
+- dlg,ldo-lvl : Required internal LDO voltage (mV) level
+   [<1050>, <1100>, <1200>, <1400>]
+- dlg,micbias-lvl : Voltage (mV) for Mic Bias
+   [<1800>, <2000>, <2200>, <2400>, <2600>, <2800>, <3000>]
+- dlg,mic-amp-in-sel : Mic input source type
+   ["diff", "se_p", "se_n"]
+- dlg,cp-mchange : Charge pump voltage tracking mode
+   ["largest_vol", "dac_vol", "sig_mag"]
+- dlg,cp-vol-thresh : Charge pump volume threshold value (6-bit value)
+   [ 0 - 0x3F ]
+
+==
+
+Child node - 'da7219_aad':
+
+Required properties:
+- interrupt-parent : Specifies the phandle of the interrupt controller to which
+  the IRQs from DA7219 AAD block are delivered to.
+- interrupts : IRQ line info for DA7219 AAD block.
+  (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt 
for
+   further information relating to interrupt properties)
+
+Optional properties:
+- dlg,micbias-pulse-lvl : Mic bias higher voltage pulse level (mV).
+   [<2800>, <2900>]
+- dlg,micbias-pulse-time : Mic bias higher voltage pulse duration (ms)
+- dlg,btn-cfg : Periodic button press measurements for 4-pole jack (ms)
+   [<2>, <5>, <10>, <50>, <100>, <200>, <500>]
+- dlg,mic-det-thr : Impedance threshold for mic detection measurement (Ohms)
+   [<200>, <500>, <750>, <1000>]
+- dlg,jack-ins-deb : Debounce time for jack insertion (ms)
+   [<5>, <10>, <20>, <50>, <100>, <200>, <500>, <1000>]
+- dlg,jack-det-rate: Jack type detection latency (3/4 pole)
+   ["32ms_64ms", "64ms_128ms", "128ms_256ms", "256ms_512ms"]
+- dlg,jack-rem-deb : Debounce time for jack removal (ms)
+   [<1>, <5>, <10>, <20>]
+- dlg,a-d-btn-thr : Impedance threshold between buttons A and D
+   [0x0 - 0xFF]
+- dlg,d-b-btn-thr : Impedance threshold between buttons D and B
+   [0x0 - 0xFF]
+- dlg,b-c-btn-thr : Impedance threshold between buttons B and C
+   [0x0 - 0xFF]
+- dlg,c-mic-btn-thr : Impedance threshold between button C and Mic
+   [0x0 - 0xFF]
+- dlg,btn-avg : Number of 8-bit readings for averaged button measurement
+   [<1>, <2>, <4>, <8>]
+- dlg,adc-1bit-rpt : Repeat count for 1-bit button measurement
+   [<1>, <2>, <4>, <8>]
+
+==
+
+Example:
+
+   codec: da7219@1a {
+   compatible = "dlg,da7219";
+   reg = <0x1a>;
+
+   clocks = < 201>;
+   clock-names = "mclk";
+
+   dlg,io-lvl = "1.2V_2.8V";
+   dlg,ldo-lvl = <1200>;
+
+   dlg,micbias-lvl = <2600>;
+   dlg,mic-amp-in-sel = "diff";
+
+   dlg,cp-mchange = "sig_mag";
+   dlg,cp-vol-thresh = <0x34>;
+
+   da7219_aad {
+   interrupt-parent = <>;
+   interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
+
+   dlg,btn-cfg = <50>;
+   dlg,mic-det-thr = <500>;
+   dlg,jack-ins-deb = <20>;
+   dlg,jack-det-rate = "32ms_64ms";
+   dlg,jack-rem-deb = <1>;
+
+   dlg,a-d-btn-thr = <0xa>;
+   dlg,d-b-btn-thr = <0x16>;
+   dlg,b-c-btn-thr = <0x21>;
+   dlg,c-mic-btn-thr = <0x3E>;
+
+   dlg,btn-avg = <4>;
+   dlg,adc-1bit-rpt = <1>;
+   };
+   };
-- 
1.9.3

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[PATCH 0/3] ASoC: Add support for DA7219 audio codec

[Adam Thomson]

This patch set adds support for the DA7219 audio codec with built-in
advanced accessory detection functionality. Patch set includes codec driver,
associated DT bindings documentation and MAINTAINERS file updates to cover new
bindings.

Adam Thomson (3):
  ASoC: codecs: Add da7219 codec driver
  ASoC: da7219: Add bindings documentation for DA7219 audio codec
  MAINTAINERS: da7219: Add entry to cover DA7219 bindings document

 Documentation/devicetree/bindings/sound/da7219.txt |  106 ++
 MAINTAINERS|1 +
 include/sound/da7219-aad.h |   99 ++
 include/sound/da7219.h |   76 +
 sound/soc/codecs/Kconfig   |4 +
 sound/soc/codecs/Makefile  |2 +
 sound/soc/codecs/da7219-aad.c  |  800 +
 sound/soc/codecs/da7219-aad.h  |  209 +++
 sound/soc/codecs/da7219.c  | 1877 
 sound/soc/codecs/da7219.h  |  807 +
 10 files changed, 3981 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sound/da7219.txt
 create mode 100644 include/sound/da7219-aad.h
 create mode 100644 include/sound/da7219.h
 create mode 100644 sound/soc/codecs/da7219-aad.c
 create mode 100644 sound/soc/codecs/da7219-aad.h
 create mode 100644 sound/soc/codecs/da7219.c
 create mode 100644 sound/soc/codecs/da7219.h

--
1.9.3

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Re: [PATCH v4 0/4] PCI: arm64/powerpc: Fix parsing of linux,pci-probe-only

[Bjorn Helgaas]

On Fri, Sep 04, 2015 at 05:50:07PM +0100, Marc Zyngier wrote:
> The pci-host-generic driver parses the linux,pci-probe-only property,
> and assumes that it will have a boolean parameter.
> 
> Turns out that the Seattle DTS file has a naked "linux,pci-probe-only"
> property, which leads to the driver dereferencing some unsuspecting
> memory location. Nothing really bad happens (we end up reading some
> other bit of DT, fortunately), but that not a reason to keep it this
> way. Turns out that the Pseries code (where this code was lifted from)
> may suffer from the same issue.
> 
> The first patch introduces a common (and fixed) version of that check
> that can be used by drivers and architectures that require it. The two
> following patches change the pci-host-generic driver and the powerpc
> code to use it.
> 
> Finally, the bad property is removed from the Seatle DTS, because it
> is simply not necessary (it actually prevents me from using SR-IOV,
> which otherwise runs fine without the probe-only thing).
> 
> This has been tested on the offending Seattle board.
> 
> * From v3:
>   - Restrict the property lookup to /chosen (Rob)
>   - Acked-by on patch #4 from Suravee
>   - I swear this is the last time I rework these patches! ;-)
> 
> * From v2:
>   - Use of_property_read_u32 to safely read the property (Rob)
>   - Add a log message to indicate when we enable probe-only
> (probably quite useful for debugging)
> 
> * From v1:
>   - Consolidate the parsing in of_pci.c (Bjorn)
> 
> Marc Zyngier (4):
>   of/pci: Add of_pci_check_probe_only to parse "linux,pci-probe-only"
>   PCI: pci-host-generic: Fix lookup of linux,pci-probe-only property
>   powerpc: PCI: Fix lookup of linux,pci-probe-only property
>   arm64: dts: Drop linux,pci-probe-only from the Seattle DTS
> 
>  arch/arm64/boot/dts/amd/amd-overdrive.dts |  1 -
>  arch/powerpc/platforms/pseries/setup.c| 14 ++
>  drivers/of/of_pci.c   | 28 
>  drivers/pci/host/pci-host-generic.c   |  9 +
>  include/linux/of_pci.h|  3 +++
>  5 files changed, 34 insertions(+), 21 deletions(-)

Applied with the comment tweak and acks to pci/host-generic for v4.4,
thanks!
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Re: [PATCH v1 1/2] soc: ti: display firmware file name as part of boot log

[santosh.shilim...@oracle.com]

On 9/16/15 12:13 PM, santosh shilimkar wrote:

On 9/16/2015 10:01 AM, Murali Karicheri wrote:

On 09/15/2015 05:20 PM, santosh shilimkar wrote:

On 9/15/2015 11:14 AM, Murali Karicheri wrote:

On 09/09/2015 12:38 PM, Murali Karicheri wrote:


[..]

Santosh,

I have checked v4.3-rc1 and I don't see it. Did you send the pull
request?


They are in the queue fo 4.4-rc1. They were too late for 4.3.
You might know already, typically as a rule of thumb followed
on arm-soc, we need to get patches reviewed/acked by rc4 to make
it for next merge window.
Ofcourse genuine bug fixes can make it to the same cycle.

Is there a branch where you have applied the patches that you can
provide me? I want to send it to internal list for merge.


Yes. I will push it out later this week. Will drop you
note when I do that.


Rebased version against v4.3-rc1 are available below. They
should also appear in linux-next soon.

git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone.git

for_4.4/dts
for_4.4/drivers-soc
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Re: [PATCH v5 01/23] driver core: Add pre_probe callback to bus_type

[Alan Stern]

On Thu, 17 Sep 2015, Tomeu Vizoso wrote:

> Some buses (eg. AMBA) need access to some HW resources (it may need a
> clock to be enabled so a device ID can be read) before a device can be
> matched to a driver.
> 
> The pre_probe callback allows the device-driver core to request the bus
> to perform this initialization and can defer the probe if any of the
> resources needed are missing.
> 
> This gives us more flexibility when setting the order in which devices
> are probed because the resources needed to get the matching information
> don't need to be available by the time that the bus devices are
> registered.

Can't the subsystem do this itself in its matching routine?

Alan Stern

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Re: [PATCH 2/2] arm64: dts: mt8173: add timer node

[Sudeep Holla]

On 17/09/15 15:56, Yingjoe Chen wrote:

On Thu, 2015-09-17 at 14:51 +0100, Sudeep Holla wrote:


On 16/09/15 03:04, Yingjoe Chen wrote:

From: Daniel Kurtz 

Add device node to enable GPT timer. This timer will be
used as sched clock source.



Interesting any known issues with or advantage over the arch timers
to prefer it as sched clock source. I see even arch timers are present
in DT, hence the question. Or is it just a incorrect commit log ?

How does this get selected as sched clock source ? I don't see
sched_clock_register in mtk_timer.c

To be clear, I am not against adding this timer support, but just want
to know is it preferred for sched clock source ? if yes why ? better
resolution ?


Hi Sudeep,

Thanks for your review.

I hit the send too soon and missed cover letter, please see:
http://lists.infradead.org/pipermail/linux-mediatek/2015-September/002303.html



OK


The main reason to use GPT as sched clock is it won't stop during idle.




I think your are confusing the system counter with arch timers. System
counter is always-on, but the arch timers(logic implementing timers
comparators) might not be off when the processor is powered down.

I think you need this timer and are using it for low power idle states
in which case you will use this as a clock event and not clock source.
It will be used as a hardware broadcast event source.

There's no call to sched_clock_register in mtk_timer.c, so it can't be
the sched clock, so you need to fix the commit log.

[...]


diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index d18ee42..d763803 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -238,6 +238,15 @@
reg = <0 0x10007000 0 0x100>;
};

+   timer: timer@10008000 {
+   compatible = "mediatek,mt8173-timer",


Missing documentation ? I am referring upstream and it might be in some
patches already queued perhaps ?


This is documented in
Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt.
Do you mean I should add "mediatek,mt8173-timer" to that file?



Yes

Regards,
Sudeep
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Re: [RFC] Potential issue with GPIO/IRQ flags

[Andrew F. Davis]

On 09/16/2015 08:26 PM, Rob Herring wrote:

On Wed, Sep 16, 2015 at 4:07 PM, Andrew F. Davis  wrote:

Hello all,

I've noticed that in a few DT bindings GPIO_ACTIVE_* defines are
incorrectly used as interrupt flags. GPIO_ACTIVE_*'s are defined
in:

include/dt-bindings/gpio/gpio.h

and are used to describe GPIO pins. IRQ types are defined in:

include/dt-bindings/interrupt-controller/irq.h

and are flags for IRQ pins.


It is perfectly valid for the meaning of the field to be defined by
the interrupt controller, and gpio interrupts could do something
different. We've tried to standardize this though.



Sure, but in this case these are not what the interrupt controller
is expecting.


These seem to have been mixed up in a few places, take for example:
arch/arm/boot/dts/tegra124-jetson-tk1.dts. On line 1393 we see the
correct usage, but just before on line 1384 we see the issue.
GPIO_ACTIVE_HIGH is defined as 0, the same as IRQ_TYPE_NONE. If
this IRQ was not hard-coded with the correct edge in the driver
this would not work. What the author probably wanted was
IRQ_TYPE_LEVEL_HIGH.

Now lets look at commit c21e678b256b, in this the IRQ flags did not
matter as the correct flag was hard-coded (IRQF_TRIGGER_LOW), this
patch moves this to the DT, but changed the flag to GPIO_ACTIVE_LOW
instead of the desired IRQ_TYPE_LEVEL_LOW. GPIO_ACTIVE_LOW is defined
as 1, or IRQ_TYPE_EDGE_RISING in IRQ flags, which is not the
equivalent to IRQF_TRIGGER_LOW the author was probably looking for.

A quick grep (git grep "interrupt.*GPIO_ACTIVE_") shows several more
instances of this. I found this by using one of these files as an
example and giving myself a lot of problems, so I would like to fix
this before it spreads anymore.

I have a couple of ideas of how to go at this, first would be to
just replace the incorrect flags with what was intended, but for
some of these I don't know what was intended and do not have the
board to test.

My other solution would be to just change all instances of the GPIO
flags to their value corresponding IRQ flags:

- interrupts = <11 GPIO_ACTIVE_LOW>;
+ interrupts = <11 IRQ_TYPE_EDGE_RISING>;

this would not make any functional change as the defines would
still evaluate to the same value, but would make it obvious where
a problem may be and that they should probably be checked and
corrected, maybe we could even put a comment after:

- interrupts = <11 GPIO_ACTIVE_LOW>;
+ interrupts = <11 IRQ_TYPE_EDGE_RISING>; // FIXME: Check IRQ type

Well, what do you think?


This seems fine. It is no less wrong.



I'm not sure what you mean here.

Regards,
Andrew


Rob


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[PATCH v4 3/3] ARM: mvebu: remove static LED setup for netxbig boards

[Simon Guinot]

Since DT support is now available for the LEDs found on the LaCie
netxbig boards (Kirkwood-based), then the old-fashion netxbig board
setup file is no longer needed. This patch removes this file.

Signed-off-by: Simon Guinot 
Acked-by: Gregory CLEMENT 
---
 arch/arm/mach-mvebu/Kconfig|   7 --
 arch/arm/mach-mvebu/Makefile   |   1 -
 arch/arm/mach-mvebu/board.h|  21 -
 arch/arm/mach-mvebu/kirkwood.c |   4 -
 arch/arm/mach-mvebu/netxbig.c  | 191 -
 5 files changed, 224 deletions(-)
 delete mode 100644 arch/arm/mach-mvebu/board.h
 delete mode 100644 arch/arm/mach-mvebu/netxbig.c

Changes for v4:
- Add some Acked-by.

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 97473168d6b6..5453f901099b 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -116,11 +116,4 @@ config MACH_KIRKWOOD
  Say 'Y' here if you want your kernel to support boards based
  on the Marvell Kirkwood device tree.
 
-config MACH_NETXBIG
-   bool "LaCie 2Big and 5Big Network v2"
-   depends on MACH_KIRKWOOD
-   help
- Say 'Y' here if you want your kernel to support the
- LaCie 2Big and 5Big Network v2
-
 endif
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index b4f01497ce0b..ecf9e0c3b107 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -13,4 +13,3 @@ endif
 
 obj-$(CONFIG_MACH_DOVE) += dove.o
 obj-$(CONFIG_MACH_KIRKWOOD) += kirkwood.o kirkwood-pm.o
-obj-$(CONFIG_MACH_NETXBIG)  += netxbig.o
diff --git a/arch/arm/mach-mvebu/board.h b/arch/arm/mach-mvebu/board.h
deleted file mode 100644
index 98e32cc2ef3d..
--- a/arch/arm/mach-mvebu/board.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Board functions for Marvell System On Chip
- *
- * Copyright (C) 2014
- *
- * Andrew Lunn 
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ARCH_MVEBU_BOARD_H
-#define __ARCH_MVEBU_BOARD_H
-
-#ifdef CONFIG_MACH_NETXBIG
-void netxbig_init(void);
-#else
-static inline void netxbig_init(void) {};
-#endif
-#endif
diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c
index 925f75f54268..f9d8e1ea7183 100644
--- a/arch/arm/mach-mvebu/kirkwood.c
+++ b/arch/arm/mach-mvebu/kirkwood.c
@@ -25,7 +25,6 @@
 #include "kirkwood.h"
 #include "kirkwood-pm.h"
 #include "common.h"
-#include "board.h"
 
 static struct resource kirkwood_cpufreq_resources[] = {
[0] = {
@@ -180,9 +179,6 @@ static void __init kirkwood_dt_init(void)
kirkwood_pm_init();
kirkwood_dt_eth_fixup();
 
-   if (of_machine_is_compatible("lacie,netxbig"))
-   netxbig_init();
-
of_platform_populate(NULL, of_default_bus_match_table, auxdata, NULL);
 }
 
diff --git a/arch/arm/mach-mvebu/netxbig.c b/arch/arm/mach-mvebu/netxbig.c
deleted file mode 100644
index 94b11b6585a4..
--- a/arch/arm/mach-mvebu/netxbig.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * arch/arm/mach-mvbu/board-netxbig.c
- *
- * LaCie 2Big and 5Big Network v2 board setup
- *
- * Copyright (C) 2010 Simon Guinot 
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include 
-#include 
-#include 
-#include 
-#include "common.h"
-
-/*
- * GPIO extension LEDs
- /
-
-/*
- * The LEDs are controlled by a CPLD and can be configured through a GPIO
- * extension bus:
- *
- * - address register : bit [0-2] -> GPIO [47-49]
- * - data register: bit [0-2] -> GPIO [44-46]
- * - enable register  : GPIO 29
- */
-
-static int netxbig_v2_gpio_ext_addr[] = { 47, 48, 49 };
-static int netxbig_v2_gpio_ext_data[] = { 44, 45, 46 };
-
-static struct netxbig_gpio_ext netxbig_v2_gpio_ext = {
-   .addr   = netxbig_v2_gpio_ext_addr,
-   .num_addr   = ARRAY_SIZE(netxbig_v2_gpio_ext_addr),
-   .data   = netxbig_v2_gpio_ext_data,
-   .num_data   = ARRAY_SIZE(netxbig_v2_gpio_ext_data),
-   .enable = 29,
-};
-
-/*
- * Address register selection:
- *
- * addr | register
- * 
- *   0  | front LED
- *   1  | front LED brightness
- *